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nest-open-source / manifest_repos / bootloader / 836ad32e08388e0e4ce8d03fe4f14d2c3ea8ba13 / . / berlin_tools / bootloader / include / Firmware_Berlin_BG2CDP_A0 / cpu_ca7.h
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/********************************************************************************
* Marvell GPL License Option
*
* If you received this File from Marvell, you may opt to use, redistribute and/or
* modify this File in accordance with the terms and conditions of the General
* Public License Version 2, June 1991 (the "GPL License"), a copy of which is
* available along with the File in the license.txt file or by writing to the Free
* Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
* on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
*
* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
* WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
* DISCLAIMED. The GPL License provides additional details about this warranty
* disclaimer.
******************************************************************************/
//////
/// don't edit! auto-generated by docc: cpu_ca7.h
////////////////////////////////////////////////////////////
#ifndef cpu_ca7_h
#define cpu_ca7_h (){}
#include "ctypes.h"
#pragma pack(1)
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _DOCC_H_BITOPS_
#define _DOCC_H_BITOPS_ (){}
#define _bSETMASK_(b) ((b)<32 ? (1<<((b)&31)) : 0)
#define _NSETMASK_(msb,lsb) (_bSETMASK_((msb)+1)-_bSETMASK_(lsb))
#define _bCLRMASK_(b) (~_bSETMASK_(b))
#define _NCLRMASK_(msb,lsb) (~_NSETMASK_(msb,lsb))
#define _BFGET_(r,msb,lsb) (_NSETMASK_((msb)-(lsb),0)&((r)>>(lsb)))
#define _BFSET_(r,msb,lsb,v) do{ (r)&=_NCLRMASK_(msb,lsb); (r)|=_NSETMASK_(msb,lsb)&((v)<<(lsb)); }while(0)
#endif
//////
///
/// $INTERFACE CA7Reg (4,4)
/// ###
/// * All the controls for CORTEXA7 System
/// ###
/// # # ----------------------------------------------------------
/// @ 0x00000 CTRL0 (RW-)
/// ###
/// * Clock related controls
/// ###
/// %unsigned 1 PLLBypassClkSel 0x0
/// ###
/// * 0: Select external fast reference clock during PLL bypass
/// * 1: Select fvs clock during PLL bypass
/// ###
/// %unsigned 1 PW_STR 0x0
/// ###
/// * CORTEXA7 pulse latch clock width control
/// * 0: 75ps clock pulse width
/// * 1: 60ps clock pulse width(for debug)
/// ###
/// %% 30 # Stuffing bits...
/// @ 0x00004 CTRL1 (RW-)
/// ###
/// * System controls of CPU. All the bits of this register are only sampled during reset of the CPU. Most of them should only be changed while the CPU is in reset.
/// ###
/// %unsigned 2 CFGEND 0x0
/// ###
/// * Individual processor control of the endianness configuration at reset. It sets the initial value of the EE bit in the CP15 System Control Register (One bit for each core):
/// * 0 EE bit is LOW.
/// * 1 EE bit is HIGH.
/// * This signal is only sampled during reset of the processor.
/// ###
/// %unsigned 2 CFGTE 0x0
/// ###
/// * Individual processor control of the default exception handling state. It sets the initial value of the TE bit in the CP15 System Control Register (One bit for each core):
/// * 0 TE bit is LOW.
/// * 1 TE bit is HIGH.
/// * This signal is only sampled during reset of the processor.
/// ###
/// %unsigned 4 CLUSTERID 0x0
/// ###
/// * Value read in the Cluster ID field, bits[11:8], of the CP15 Multiprocessor Affinity Register (MPDIR).
/// * This signal is only sampled during reset of the processor.
/// ###
/// %unsigned 2 VINITHI 0xF
/// ###
/// * Individual processor control of the location of the exception vectors at reset. It sets the initial value of the V bit in the CP15 System Control Register (One bit for each core):
/// * 0 Exception vectors start at address 0x00000000.
/// * 1 Exception vectors start at address 0xFFFF0000.
/// * This signal is only sampled during reset of the processor.
/// ###
/// %unsigned 2 CP15SDISABLE 0x0
/// ###
/// * Disable write access to some secure CP15 registers.(One bit for each core)
/// ###
/// %unsigned 1 CFGSDISABLE 0x0
/// ###
/// * Disable write access to some secure GIC registers(Current not used be cause GIC is not present in CORTEXA7 system)
/// ###
/// %unsigned 2 L1RSTDISABLE 0x0
/// ###
/// * Disable automatic L1 cache invalidate at reset(one bit for each core)
/// * 0 L1 cache is reset by hardware.
/// * 1 L1 cache is not reset by hardware.
/// ###
/// %unsigned 1 L2RSTDISABLE 0x0
/// ###
/// * Disable automatic L2 cache invalidate at reset:
/// * 0 L2 cache is reset by hardware.
/// * 1 L2 cache is not reset by hardware.
/// ###
/// %unsigned 1 DFTRAMHOLD 0x0
/// ###
/// * Disables the RAM chip selects during scan testing
/// * 1'b1: RAMs are held(chip select is invalid)
/// * 1'b0: RAMs are not held(chip select is valid)
/// ###
/// %% 15 # Stuffing bits...
/// @ 0x00008 CTRL2 (RW-)
/// ###
/// * CA7 power management
/// ###
/// %unsigned 1 l2ram_cntrl1_i 0x1
/// ###
/// * L2ram power switch control 1
/// * 0: power off
/// * 1: power on
/// ###
/// %unsigned 1 l2ram_cntrl2_i 0x1
/// ###
/// * L2ram power switch control 2
/// * 0: power off
/// * 1: power on
/// ###
/// %unsigned 1 mp_cntrl1_i 0x1
/// ###
/// * Big banks of switches inside the integration power switch control 1
/// * 0: power off
/// * 1: power on
/// ###
/// %unsigned 1 mp_cntrl2_i 0x1
/// ###
/// * Big banks of switches inside the integration power switch control 2
/// * 0: power off
/// * 1: power on
/// ###
/// %unsigned 1 dist_pwrsw_mp_cntrl_i 0x0
/// ###
/// * Distributed switches inside the integration level control(low active)
/// * 0: power on
/// * 1: power off
/// ###
/// %unsigned 1 cpu0_pwrsw_cntrl1_i 0x1
/// ###
/// * Cpu0 power switch control 1
/// * 0: power off
/// * 1: power on
/// ###
/// %unsigned 1 cpu1_pwrsw_cntrl1_i 0x1
/// ###
/// * Cpu1 power switch control 1
/// * 0: power off
/// * 1: power on
/// ###
/// %unsigned 1 cpu0_pwrsw_cntrl2_i 0x1
/// ###
/// * Cpu0 power switch control 2
/// * 0: power off
/// * 1: power on
/// ###
/// %unsigned 1 cpu1_pwrsw_cntrl2_i 0x1
/// ###
/// * Cpu1 power switch control 2
/// * 0: power off
/// * 1: power on
/// ###
/// %unsigned 1 cpu0_dist_pwrsw_cntrl1_i 0x0
/// ###
/// * Cpu0 distributed switches inside cpu control(low active)
/// * 0: power on
/// * 1: power off
/// ###
/// %unsigned 1 cpu1_dist_pwrsw_cntrl1_i 0x0
/// ###
/// * Cpu1 distributed switches inside cpu control(low active)
/// * 0: power on
/// * 1: power off
/// ###
/// %unsigned 1 cpu0_nisolate_cpu 0x1
/// ###
/// * Cpu0 isolation control(Active low)
/// ###
/// %unsigned 1 cpu1_nisolate_cpu 0x1
/// ###
/// * Cpu1 isolation control(Active low)
/// ###
/// %unsigned 1 mp_nisolate_cpu 0x1
/// ###
/// * CORTEXA7 mp level isolation control(Isolation not implemented right now)
/// ###
/// %unsigned 1 l2_sram_pdwn 0x0
/// ###
/// * L2 SRAM power mode control
/// * 1'b1: Power down mode
/// * 1'b0: Normal mode
/// ###
/// %% 17 # Stuffing bits...
/// @ 0x0000C CTRL3 (RW-)
/// ###
/// * CoreSight related controls
/// ###
/// %unsigned 2 dbgen 0x3
/// ###
/// * Invasive Debug Enable
/// * 0 Not enable
/// * 1 Enable
/// ###
/// %unsigned 2 spiden 0x3
/// ###
/// * Secure Invasive Debug Enable
/// * 0 Not enable
/// * 1 Enable
/// ###
/// %unsigned 2 niden 0x3
/// ###
/// * Non Invasive Debug Enable
/// * 0 Not enable
/// * 1 Enable
/// ###
/// %unsigned 2 spniden 0x3
/// ###
/// * Secure Non Invasive Debug Enable
/// * 0 Not enable
/// * 1 Enable
/// ###
/// %% 24 # Stuffing bits...
/// @ 0x00010 CTRL4 (RW-)
/// ###
/// * ACE Bus configuration
/// ###
/// %unsigned 1 ACINACTM 0x0
/// ###
/// * Snoop interface is inactive and no longer accepting requests
/// ###
/// %unsigned 1 BROADCASTCACHEMAINT 0x0
/// ###
/// * Enable broadcasting of cache maintenance operations to downstream caches:
/// * 0 Cache maintenance operations are not broadcasted to downstream caches.
/// * 1 Cache maintenance operations are broadcasted to downstream caches.
/// * This signal is only sampled during reset of the processor.
/// ###
/// %unsigned 1 BROADCASTINNER 0x0
/// ###
/// * Enable broadcasting of inner shareable transactions:
/// * 0 Inner shareable transactions are not broadcasted externally.
/// * 1 Inner shareable transactions are broadcasted externally.
/// * If BROADCASTINNER is tied HIGH, you must also tie BROADCASTOUTER HIGH.
/// * This signal is only sampled during reset of the processor.
/// ###
/// %unsigned 1 BROADCASTOUTER 0x0
/// ###
/// * Enable broadcasting of outer shareable transactions:
/// * 0 Outer shareable transactions are not broadcasted externally.
/// * 1 Outer shareable transactions are broadcasted externally.
/// * This signal is only sampled during reset of the processor.
/// ###
/// %unsigned 1 SYSBARDISABLE 0x1
/// ###
/// * Disable broadcasting of barriers onto system bus:
/// * 0 Barriers are broadcasted onto system bus, this requires an AMBA 4 interconnect.
/// * 1 Barriers are not broadcasted onto the system bus. This is compatible with an AXI3 interconnect.
/// * If SYSBARDISABLE is tied HIGH, you must tie the following signals LOW for full AXI3 compatibility:
/// * 1. BROADCASTCACHEMAINT.
/// * 2. BROADCASTINNER.
/// * 3. BROADCASTOUTER.
/// * This signal is only sampled during reset of the processor.
/// ###
/// %% 27 # Stuffing bits...
/// @ 0x00014 CTRL5 (RW-)
/// ###
/// * CPU Memory RWTC Control
/// ###
/// %unsigned 2 IDATA_WTC 0x1
/// ###
/// * ICache data ram WTC setup
/// ###
/// %unsigned 2 IDATA_RTC 0x2
/// ###
/// * ICache data ram RTC setup
/// ###
/// %unsigned 2 ITAG_WTC 0x1
/// ###
/// * ICache tag ram WTC setup
/// ###
/// %unsigned 2 ITAG_RTC 0x2
/// ###
/// * ICache tag ram RTC setup
/// ###
/// %unsigned 2 DDATA_WTC 0x1
/// ###
/// * DCache data ram WTC setup
/// ###
/// %unsigned 2 DDATA_RTC 0x2
/// ###
/// * DCache data ram RTC setup
/// ###
/// %unsigned 2 DTAG_WTC 0x1
/// ###
/// * DCache tag ram WTC setup
/// ###
/// %unsigned 2 DTAG_RTC 0x2
/// ###
/// * DCache tag ram RTC setup
/// ###
/// %unsigned 2 DDIRTY_WTC 0x1
/// ###
/// * DCache dirty ram WTC setup
/// ###
/// %unsigned 2 DDIRTY_RTC 0x2
/// ###
/// * DCache dirty ram RTC setup
/// ###
/// %unsigned 2 TLB_WTC 0x1
/// ###
/// * TLB ram WTC setup
/// ###
/// %unsigned 2 TLB_RTC 0x2
/// ###
/// * TLB ram RTC setup
/// ###
/// %unsigned 2 SCU_TAG_WTC 0x1
/// ###
/// * SCU tag ram WTC setup
/// ###
/// %unsigned 2 SCU_TAG_RTC 0x2
/// ###
/// * SCU tag ram RTC setup
/// ###
/// %unsigned 2 L2_DATA_WTC 0x1
/// ###
/// * L2 data ram WTC setup
/// ###
/// %unsigned 2 L2_DATA_RTC 0x2
/// ###
/// * L2 data ram RTC setup
/// ###
/// # 0x00018 CTRL51
/// %unsigned 2 L2_TAG_WTC 0x1
/// ###
/// * L2 tag ram WTC setup
/// ###
/// %unsigned 2 L2_TAG_RTC 0x2
/// ###
/// * L2 tag ram RTC setup
/// ###
/// %% 28 # Stuffing bits...
/// @ 0x0001C CPUPwrCtrl (RW-)
/// ###
/// * CPU Power control registers
/// ###
/// %unsigned 2 DBGPWRDUP 0x3
/// ###
/// * Processor powered up.(One for each core)
/// ###
/// %% 30 # Stuffing bits...
/// @ 0x00020 CPU_Status (R-)
/// ###
/// * CPU Power control status registers
/// ###
/// %unsigned 2 standby_wfe 0x0
/// ###
/// * Indicates if a processor is in WFE standby mode:(One for each core)
/// * 0 Processor not in WFE standby mode.
/// * 1 Processor in WFE standby mode.
/// ###
/// %unsigned 2 standby_wfi 0x0
/// ###
/// * Indicates if a processor is in WFI standby mode:(One for each core)
/// * 0 Processor not in WFI standby mode.
/// * 1 Processor in WFI standby mode.
/// ###
/// %unsigned 1 L2standby_wfi 0x0
/// ###
/// * Indicates if L2 is in WFI standby mode. This signal is active when the following are true:
/// * 1. All processors are in standby WFI.
/// * 2. ACINACTM and AINACTS are asserted HIGH.
/// * 3. L2 memory system is idle.
/// ###
/// %unsigned 2 ETMSTANDBYWFX 0x0
/// ###
/// * Indicates when the trace FIFO is
/// * empty.
/// ###
/// %unsigned 2 DBGPWRUPREQ 0x0
/// ###
/// * Power up request:
/// * 0 Power down debug request to the power controller.
/// * 1 Power up request to the power controller.
/// ###
/// %unsigned 2 DBGNOPWRDWN 0x0
/// ###
/// * No power-down request:
/// * 0 On a power-down request, the SoC power controller powers down the processor
/// * 1 On a power-down request, the SoC power controller does not power down the processor.
/// ###
/// %% 21 # Stuffing bits...
/// @ 0x00024 ETM_REG (RW-)
/// ###
/// * ETM Registers
/// ###
/// %unsigned 3 MAXEXTIN 0x1
/// ###
/// * Number of external inputs the ASIC supports, maximum four.
/// ###
/// %unsigned 2 MAXEXTOUT 0x1
/// ###
/// * Number of external outputs the ASIC supports, maximum two.
/// ###
/// %% 27 # Stuffing bits...
/// @ 0x00028 PowerStatus (R-)
/// ###
/// * Cortex-A7 core power switch acknowledge signals
/// ###
/// %unsigned 1 l2ram_pwrsw_ack1 0x0
/// ###
/// * L2ram power switch acknowledge signal 1
/// ###
/// %unsigned 1 l2ram_pwrsw_ack2 0x0
/// ###
/// * L2ram power switch acknowledge signal 2
/// ###
/// %unsigned 1 mp_pwrsw_ack1 0x0
/// ###
/// * Big banks of switches inside the integration power switch acknowledge 1 (Polarity for this ack signal is different from all other ack signals. It is low active.)
/// ###
/// %unsigned 1 mp_pwrsw_ack2 0x0
/// ###
/// * Big banks of switches inside the integration power switch acknowledge 2
/// ###
/// %unsigned 1 cpu0_pwrsw_ack1 0x0
/// ###
/// * Cpu0 power switch acknowledge signal 1
/// ###
/// %unsigned 1 cpu1_pwrsw_ack1 0x0
/// ###
/// * Cpu1 power switch acknowledge signal 1
/// ###
/// %unsigned 1 cpu0_pwrsw_ack2 0x0
/// ###
/// * Cpu0 power switch acknowledge signal 2
/// ###
/// %unsigned 1 cpu1_pwrsw_ack2 0x0
/// ###
/// * Cpu1 power switch acknowledge signal 2
/// ###
/// %% 24 # Stuffing bits...
/// @ 0x0002C SRSoftResetn (P)
/// ###
/// * CortexA7 self-recover Reset Controls (can recover by itself)
/// ###
/// %unsigned 1 SRCPURESETALL 0x0
/// ###
/// * 1 Apply reset to all processors including NEON and VFP, Debug, ETM breakpoint, watchpoint logic and L2
/// * 0 normal operation
/// ###
/// %unsigned 1 SRCOREPORESET0 0x0
/// ###
/// * Individual CPU0 processor reset:
/// * 1 Apply reset to processor that includes NEON and VFP, Debug, ETM, breakpoint and watchpoint logic.
/// * 0 normal operation
/// ###
/// %unsigned 1 SRCOREPORESET1 0x0
/// ###
/// * Individual CPU1 processor reset:
/// * 1 Apply reset to processor that includes NEON and VFP, Debug, ETM, breakpoint and watchpoint logic.
/// * 0 normal operation
/// ###
/// %unsigned 1 SRCORERESET0 0x0
/// ###
/// * Individual CPU0 processor reset excluding Debug and PTM:
/// * 1 Apply reset to processor that includes NEON and VFP, but excludes Debug, PTM, breakpoint and watchpoint logic.
/// * 0 normal operation
/// ###
/// %unsigned 1 SRCORERESET1 0x0
/// ###
/// * Individual CPU1 processor reset excluding Debug and PTM:
/// * 1 Apply reset to processor that includes NEON and VFP, but excludes Debug, PTM, breakpoint and watchpoint logic.
/// * 0 normal operation
/// ###
/// %unsigned 1 SRDBGRESET0 0x0
/// ###
/// * Individual CPU0 Debug logic resets:
/// * 1 Apply reset to debug, breakpoint and watchpoint logic.
/// * 0 normal operation
/// ###
/// %unsigned 1 SRDBGRESET1 0x0
/// ###
/// * Individual CPU1 Debug logic resets:
/// * 1 Apply reset to debug, breakpoint and watchpoint logic.
/// * 0 normal operation
/// ###
/// %unsigned 1 SRETMRESET0 0x0
/// ###
/// * Individual ETM reset:
/// * 1 Apply reset to ETM0 logic.
/// * 0 normal operation
/// ###
/// %unsigned 1 SRETMRESET1 0x0
/// ###
/// * Individual ETM1 reset:
/// * 1 Apply reset to ETM1 logic.
/// * 0 normal operation
/// ###
/// %unsigned 1 SRL2RESET 0x0
/// ###
/// * SCU global reset:
/// * 1 Apply reset to shared L2 memory system controller.
/// * 0 normal operation
/// ###
/// %unsigned 1 SRSOCDBGRESET 0x0
/// ###
/// * This is the system-level debug reset. It initializes the shared Debug APB, the CTI, and the CTM. It also causes:
/// * • nDBGRESET[3:0] and nETMRESET[3:0] to be asserted.
/// * • debug logic in the processor power domain and in the debug power domain to be reset.
/// ###
/// %% 21 # Stuffing bits...
/// @ 0x00030 SoftResetn (P)
/// ###
/// * CortexA7 Reset Controls (can't recover by itself)
/// ###
/// %unsigned 1 CA7RESETALL 0x0
/// ###
/// * Reset CA7, Timer and Asyncbridge
/// * 0 Apply reset to the whole CA7, Timer and Asyncbridge
/// * 1 Normal operation
/// ###
/// %unsigned 1 COREPORESET0 0x1
/// ###
/// * Individual CPU0 processor reset:
/// * 0 Apply reset to processor that includes NEON and VFP, Debug, ETM, breakpoint and watchpoint logic.
/// * 1 Do not apply reset to processor that includes NEON and VFP, Debug, ETM, breakpoint and watchpoint logic.
/// ###
/// %unsigned 1 COREPORESET1 0x1
/// ###
/// * Individual CPU1 processor reset:
/// * 0 Apply reset to processor that includes NEON and VFP, Debug, ETM, breakpoint and watchpoint logic.
/// * 1 Do not apply reset to processor that includes NEON and VFP, Debug, ETM, breakpoint and watchpoint logic.
/// ###
/// %unsigned 1 CORERESET0 0x1
/// ###
/// * Individual CPU0 processor reset excluding Debug and ETM:
/// * 0 Apply reset to processor that includes NEON and VFP, but excludes Debug, ETM, breakpoint and watchpoint logic.
/// * 1 Do not apply reset to processor that includes NEON and VFP, but excludes Debug, ETM, breakpoint and watchpoint logic.
/// ###
/// %unsigned 1 CORERESET1 0x1
/// ###
/// * Individual CPU1 processor reset excluding Debug and ETM:
/// * 0 Apply reset to processor that includes NEON and VFP, but excludes Debug, ETM, breakpoint and watchpoint logic.
/// * 1 Do not apply reset to processor that includes NEON and VFP, but excludes Debug, ETM, breakpoint and watchpoint logic.
/// ###
/// %unsigned 1 DBGRESET0 0x1
/// ###
/// * Individual processor CPU0 Debug reset:
/// * 0 Apply reset to Debug, breakpoint and watchpoint logic.
/// * 1 Do not apply reset to Debug, breakpoint and watchpoint logic.
/// ###
/// %unsigned 1 DBGRESET1 0x1
/// ###
/// * Individual CPU1 processor Debug reset:
/// * 0 Apply reset to Debug, breakpoint and watchpoint logic.
/// * 1 Do not apply reset to Debug, breakpoint and watchpoint logic.
/// ###
/// %unsigned 1 ETMRESET0 0x1
/// ###
/// * Individual ETM0 reset:
/// * 0 Apply reset to ETM0 logic.
/// * 1 Do not apply reset ETM0 logic.
/// ###
/// %unsigned 1 ETMRESET1 0x1
/// ###
/// * Individual ETM1 reset:
/// * 0 Apply reset to ETM1 logic.
/// * 1 Do not apply reset to ETM1 logic.
/// ###
/// %unsigned 1 SOCDBGRESET 0x1
/// ###
/// * This is the system-level debug reset. It initializes the shared Debug APB, the CTI, and the CTM. It also causes:
/// * • nDBGRESET[3:0] and nETMRESET[3:0] to be asserted.
/// * • debug logic in the processor power domain and in the debug power domain to be reset.
/// ###
/// %unsigned 1 L2RESET 0x1
/// ###
/// * SCU global reset:
/// * 0 Apply reset to shared L2 memory system controller.
/// * 1 Do not apply reset to shared L2 memory system controller.
/// ###
/// %unsigned 1 MBISTRESET 0x1
/// ###
/// * MBIST test reset. This signal overrides the system resets when the MBISTREQ signal is asserted.
/// * 0: Apply Reset
/// * 1: Not Apply Reset
/// ###
/// %unsigned 1 CPUTimer 0x1
/// ###
/// * Active low reset for cpu timer
/// ###
/// %unsigned 1 PTMTimer 0x1
/// ###
/// * Active low reset for ptm timestamp generator
/// ###
/// %unsigned 1 CA7_SYNC_FARM 0x1
/// ###
/// * Active low reset for CA7 asynchronous signals
/// ###
/// %unsigned 1 SRAM_FNRST 0x1
/// ###
/// * Active low reset for CA7 L2 DATA RAM repair logic reset
/// ###
/// %% 16 # Stuffing bits...
/// @ 0x00034 TimerCtrl (P)
/// ###
/// * CPU and PTM Timer control
/// ###
/// %unsigned 1 CPUTimerEn 0x0
/// ###
/// * Cpu timer enable
/// * 1'b1: enable counter 1'b0: disable counter
/// ###
/// %unsigned 1 CPUTimerLoad 0x0
/// ###
/// * Load CPU Timer Value from register
/// * This load is valid when CPUTimerEn is 1'b0
/// ###
/// %% 30 # Stuffing bits...
/// # 0x00038 TimerCtrl1
/// %unsigned 32 CPUTimerLoadValueHi 0x0
/// ###
/// * Cpu timer load value(High 32 bits)
/// ###
/// # 0x0003C TimerCtrl2
/// %unsigned 32 CPUTimerLoadValueLo 0x0
/// ###
/// * Cpu timer load value(Low 32 bits)
/// ###
/// # 0x00040 TimerCtrl3
/// %unsigned 1 PTMTimerEn 0x0
/// ###
/// * PTM timer enable
/// * 1'b1: enable timer 1'b0: disable timer
/// ###
/// %unsigned 1 PTMTimerLoad 0x0
/// ###
/// * Load PTM Timer Preset Value
/// * This load is valid when PTMTimerEn is 1'b0
/// ###
/// %% 30 # Stuffing bits...
/// # 0x00044 TimerCtrl4
/// %unsigned 32 PTMTimerLoadValueHi 0x0
/// ###
/// * PTM timer load value(High 32 bits)
/// ###
/// # 0x00048 TimerCtrl5
/// %unsigned 32 PTMTimerLoadValueLo 0x0
/// ###
/// * PTM timer load value(Low 32 bits)
/// ###
/// @ 0x0004C TimerValue (R-)
/// ###
/// * CPU and PTM Timer Value
/// ###
/// %unsigned 32 CPUTimerValueHi 0x0
/// ###
/// * Cpu timer value(High 32 bits)
/// ###
/// # 0x00050 TimerValue1
/// %unsigned 32 CPUTimerValueLo 0x0
/// ###
/// * Cpu timer value(Low 32 bits)
/// ###
/// # 0x00054 TimerValue2
/// %unsigned 32 PTMTimerValueHi 0x0
/// ###
/// * PTM timer value(High 32 bits)
/// ###
/// # 0x00058 TimerValue3
/// %unsigned 32 PTMTimerValueLo 0x0
/// ###
/// * PTM timer value(Low 32 bits)
/// ###
/// @ 0x0005C mbisr_Ctrl (P)
/// ###
/// * Memory BISR control
/// ###
/// %unsigned 4 efuse_TEST 0xA
/// ###
/// * Test control for efuse in mbisr_ctrl module
/// ###
/// %% 28 # Stuffing bits...
/// @ 0x00060 CSSY_RWTC (P)
/// ###
/// * CoreSight memory RWTC control
/// ###
/// %unsigned 32 31to0 0xAAAA99AA
/// # 0x00064 CSSY_RWTC1
/// %unsigned 26 57to32 0x2A95B5A
/// %% 6 # Stuffing bits...
/// @ 0x00068 CSSY_Ctrl (P)
/// ###
/// * CoreSight control
/// ###
/// %unsigned 1 dbgen 0x1
/// ###
/// * Invasive Debug Enable
/// ###
/// %unsigned 1 spiden 0x1
/// ###
/// * Secure Invasive Debug Enable
/// ###
/// %unsigned 1 niden 0x1
/// ###
/// * Non Invasive Debug Enable
/// ###
/// %unsigned 1 spniden 0x1
/// ###
/// * Secure Non Invasive Debug Enable
/// ###
/// %unsigned 1 DEVICEEN 0x1
/// ###
/// * Enable APB-AP interface
/// ###
/// %% 27 # Stuffing bits...
/// @ 0x0006C dummy (P)
/// %unsigned 32 dummy 0x0
/// ###
/// * Not used. May be used for ECO
/// ###
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 112B, bits: 495b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_CA7Reg
#define h_CA7Reg (){}
#define RA_CA7Reg_CTRL0 0x0000
#define BA_CA7Reg_CTRL0_PLLBypassClkSel 0x0000
#define B16CA7Reg_CTRL0_PLLBypassClkSel 0x0000
#define LSb32CA7Reg_CTRL0_PLLBypassClkSel 0
#define LSb16CA7Reg_CTRL0_PLLBypassClkSel 0
#define bCA7Reg_CTRL0_PLLBypassClkSel 1
#define MSK32CA7Reg_CTRL0_PLLBypassClkSel 0x00000001
#define BA_CA7Reg_CTRL0_PW_STR 0x0000
#define B16CA7Reg_CTRL0_PW_STR 0x0000
#define LSb32CA7Reg_CTRL0_PW_STR 1
#define LSb16CA7Reg_CTRL0_PW_STR 1
#define bCA7Reg_CTRL0_PW_STR 1
#define MSK32CA7Reg_CTRL0_PW_STR 0x00000002
///////////////////////////////////////////////////////////
#define RA_CA7Reg_CTRL1 0x0004
#define BA_CA7Reg_CTRL1_CFGEND 0x0004
#define B16CA7Reg_CTRL1_CFGEND 0x0004
#define LSb32CA7Reg_CTRL1_CFGEND 0
#define LSb16CA7Reg_CTRL1_CFGEND 0
#define bCA7Reg_CTRL1_CFGEND 2
#define MSK32CA7Reg_CTRL1_CFGEND 0x00000003
#define BA_CA7Reg_CTRL1_CFGTE 0x0004
#define B16CA7Reg_CTRL1_CFGTE 0x0004
#define LSb32CA7Reg_CTRL1_CFGTE 2
#define LSb16CA7Reg_CTRL1_CFGTE 2
#define bCA7Reg_CTRL1_CFGTE 2
#define MSK32CA7Reg_CTRL1_CFGTE 0x0000000C
#define BA_CA7Reg_CTRL1_CLUSTERID 0x0004
#define B16CA7Reg_CTRL1_CLUSTERID 0x0004
#define LSb32CA7Reg_CTRL1_CLUSTERID 4
#define LSb16CA7Reg_CTRL1_CLUSTERID 4
#define bCA7Reg_CTRL1_CLUSTERID 4
#define MSK32CA7Reg_CTRL1_CLUSTERID 0x000000F0
#define BA_CA7Reg_CTRL1_VINITHI 0x0005
#define B16CA7Reg_CTRL1_VINITHI 0x0004
#define LSb32CA7Reg_CTRL1_VINITHI 8
#define LSb16CA7Reg_CTRL1_VINITHI 8
#define bCA7Reg_CTRL1_VINITHI 2
#define MSK32CA7Reg_CTRL1_VINITHI 0x00000300
#define BA_CA7Reg_CTRL1_CP15SDISABLE 0x0005
#define B16CA7Reg_CTRL1_CP15SDISABLE 0x0004
#define LSb32CA7Reg_CTRL1_CP15SDISABLE 10
#define LSb16CA7Reg_CTRL1_CP15SDISABLE 10
#define bCA7Reg_CTRL1_CP15SDISABLE 2
#define MSK32CA7Reg_CTRL1_CP15SDISABLE 0x00000C00
#define BA_CA7Reg_CTRL1_CFGSDISABLE 0x0005
#define B16CA7Reg_CTRL1_CFGSDISABLE 0x0004
#define LSb32CA7Reg_CTRL1_CFGSDISABLE 12
#define LSb16CA7Reg_CTRL1_CFGSDISABLE 12
#define bCA7Reg_CTRL1_CFGSDISABLE 1
#define MSK32CA7Reg_CTRL1_CFGSDISABLE 0x00001000
#define BA_CA7Reg_CTRL1_L1RSTDISABLE 0x0005
#define B16CA7Reg_CTRL1_L1RSTDISABLE 0x0004
#define LSb32CA7Reg_CTRL1_L1RSTDISABLE 13
#define LSb16CA7Reg_CTRL1_L1RSTDISABLE 13
#define bCA7Reg_CTRL1_L1RSTDISABLE 2
#define MSK32CA7Reg_CTRL1_L1RSTDISABLE 0x00006000
#define BA_CA7Reg_CTRL1_L2RSTDISABLE 0x0005
#define B16CA7Reg_CTRL1_L2RSTDISABLE 0x0004
#define LSb32CA7Reg_CTRL1_L2RSTDISABLE 15
#define LSb16CA7Reg_CTRL1_L2RSTDISABLE 15
#define bCA7Reg_CTRL1_L2RSTDISABLE 1
#define MSK32CA7Reg_CTRL1_L2RSTDISABLE 0x00008000
#define BA_CA7Reg_CTRL1_DFTRAMHOLD 0x0006
#define B16CA7Reg_CTRL1_DFTRAMHOLD 0x0006
#define LSb32CA7Reg_CTRL1_DFTRAMHOLD 16
#define LSb16CA7Reg_CTRL1_DFTRAMHOLD 0
#define bCA7Reg_CTRL1_DFTRAMHOLD 1
#define MSK32CA7Reg_CTRL1_DFTRAMHOLD 0x00010000
///////////////////////////////////////////////////////////
#define RA_CA7Reg_CTRL2 0x0008
#define BA_CA7Reg_CTRL2_l2ram_cntrl1_i 0x0008
#define B16CA7Reg_CTRL2_l2ram_cntrl1_i 0x0008
#define LSb32CA7Reg_CTRL2_l2ram_cntrl1_i 0
#define LSb16CA7Reg_CTRL2_l2ram_cntrl1_i 0
#define bCA7Reg_CTRL2_l2ram_cntrl1_i 1
#define MSK32CA7Reg_CTRL2_l2ram_cntrl1_i 0x00000001
#define BA_CA7Reg_CTRL2_l2ram_cntrl2_i 0x0008
#define B16CA7Reg_CTRL2_l2ram_cntrl2_i 0x0008
#define LSb32CA7Reg_CTRL2_l2ram_cntrl2_i 1
#define LSb16CA7Reg_CTRL2_l2ram_cntrl2_i 1
#define bCA7Reg_CTRL2_l2ram_cntrl2_i 1
#define MSK32CA7Reg_CTRL2_l2ram_cntrl2_i 0x00000002
#define BA_CA7Reg_CTRL2_mp_cntrl1_i 0x0008
#define B16CA7Reg_CTRL2_mp_cntrl1_i 0x0008
#define LSb32CA7Reg_CTRL2_mp_cntrl1_i 2
#define LSb16CA7Reg_CTRL2_mp_cntrl1_i 2
#define bCA7Reg_CTRL2_mp_cntrl1_i 1
#define MSK32CA7Reg_CTRL2_mp_cntrl1_i 0x00000004
#define BA_CA7Reg_CTRL2_mp_cntrl2_i 0x0008
#define B16CA7Reg_CTRL2_mp_cntrl2_i 0x0008
#define LSb32CA7Reg_CTRL2_mp_cntrl2_i 3
#define LSb16CA7Reg_CTRL2_mp_cntrl2_i 3
#define bCA7Reg_CTRL2_mp_cntrl2_i 1
#define MSK32CA7Reg_CTRL2_mp_cntrl2_i 0x00000008
#define BA_CA7Reg_CTRL2_dist_pwrsw_mp_cntrl_i 0x0008
#define B16CA7Reg_CTRL2_dist_pwrsw_mp_cntrl_i 0x0008
#define LSb32CA7Reg_CTRL2_dist_pwrsw_mp_cntrl_i 4
#define LSb16CA7Reg_CTRL2_dist_pwrsw_mp_cntrl_i 4
#define bCA7Reg_CTRL2_dist_pwrsw_mp_cntrl_i 1
#define MSK32CA7Reg_CTRL2_dist_pwrsw_mp_cntrl_i 0x00000010
#define BA_CA7Reg_CTRL2_cpu0_pwrsw_cntrl1_i 0x0008
#define B16CA7Reg_CTRL2_cpu0_pwrsw_cntrl1_i 0x0008
#define LSb32CA7Reg_CTRL2_cpu0_pwrsw_cntrl1_i 5
#define LSb16CA7Reg_CTRL2_cpu0_pwrsw_cntrl1_i 5
#define bCA7Reg_CTRL2_cpu0_pwrsw_cntrl1_i 1
#define MSK32CA7Reg_CTRL2_cpu0_pwrsw_cntrl1_i 0x00000020
#define BA_CA7Reg_CTRL2_cpu1_pwrsw_cntrl1_i 0x0008
#define B16CA7Reg_CTRL2_cpu1_pwrsw_cntrl1_i 0x0008
#define LSb32CA7Reg_CTRL2_cpu1_pwrsw_cntrl1_i 6
#define LSb16CA7Reg_CTRL2_cpu1_pwrsw_cntrl1_i 6
#define bCA7Reg_CTRL2_cpu1_pwrsw_cntrl1_i 1
#define MSK32CA7Reg_CTRL2_cpu1_pwrsw_cntrl1_i 0x00000040
#define BA_CA7Reg_CTRL2_cpu0_pwrsw_cntrl2_i 0x0008
#define B16CA7Reg_CTRL2_cpu0_pwrsw_cntrl2_i 0x0008
#define LSb32CA7Reg_CTRL2_cpu0_pwrsw_cntrl2_i 7
#define LSb16CA7Reg_CTRL2_cpu0_pwrsw_cntrl2_i 7
#define bCA7Reg_CTRL2_cpu0_pwrsw_cntrl2_i 1
#define MSK32CA7Reg_CTRL2_cpu0_pwrsw_cntrl2_i 0x00000080
#define BA_CA7Reg_CTRL2_cpu1_pwrsw_cntrl2_i 0x0009
#define B16CA7Reg_CTRL2_cpu1_pwrsw_cntrl2_i 0x0008
#define LSb32CA7Reg_CTRL2_cpu1_pwrsw_cntrl2_i 8
#define LSb16CA7Reg_CTRL2_cpu1_pwrsw_cntrl2_i 8
#define bCA7Reg_CTRL2_cpu1_pwrsw_cntrl2_i 1
#define MSK32CA7Reg_CTRL2_cpu1_pwrsw_cntrl2_i 0x00000100
#define BA_CA7Reg_CTRL2_cpu0_dist_pwrsw_cntrl1_i 0x0009
#define B16CA7Reg_CTRL2_cpu0_dist_pwrsw_cntrl1_i 0x0008
#define LSb32CA7Reg_CTRL2_cpu0_dist_pwrsw_cntrl1_i 9
#define LSb16CA7Reg_CTRL2_cpu0_dist_pwrsw_cntrl1_i 9
#define bCA7Reg_CTRL2_cpu0_dist_pwrsw_cntrl1_i 1
#define MSK32CA7Reg_CTRL2_cpu0_dist_pwrsw_cntrl1_i 0x00000200
#define BA_CA7Reg_CTRL2_cpu1_dist_pwrsw_cntrl1_i 0x0009
#define B16CA7Reg_CTRL2_cpu1_dist_pwrsw_cntrl1_i 0x0008
#define LSb32CA7Reg_CTRL2_cpu1_dist_pwrsw_cntrl1_i 10
#define LSb16CA7Reg_CTRL2_cpu1_dist_pwrsw_cntrl1_i 10
#define bCA7Reg_CTRL2_cpu1_dist_pwrsw_cntrl1_i 1
#define MSK32CA7Reg_CTRL2_cpu1_dist_pwrsw_cntrl1_i 0x00000400
#define BA_CA7Reg_CTRL2_cpu0_nisolate_cpu 0x0009
#define B16CA7Reg_CTRL2_cpu0_nisolate_cpu 0x0008
#define LSb32CA7Reg_CTRL2_cpu0_nisolate_cpu 11
#define LSb16CA7Reg_CTRL2_cpu0_nisolate_cpu 11
#define bCA7Reg_CTRL2_cpu0_nisolate_cpu 1
#define MSK32CA7Reg_CTRL2_cpu0_nisolate_cpu 0x00000800
#define BA_CA7Reg_CTRL2_cpu1_nisolate_cpu 0x0009
#define B16CA7Reg_CTRL2_cpu1_nisolate_cpu 0x0008
#define LSb32CA7Reg_CTRL2_cpu1_nisolate_cpu 12
#define LSb16CA7Reg_CTRL2_cpu1_nisolate_cpu 12
#define bCA7Reg_CTRL2_cpu1_nisolate_cpu 1
#define MSK32CA7Reg_CTRL2_cpu1_nisolate_cpu 0x00001000
#define BA_CA7Reg_CTRL2_mp_nisolate_cpu 0x0009
#define B16CA7Reg_CTRL2_mp_nisolate_cpu 0x0008
#define LSb32CA7Reg_CTRL2_mp_nisolate_cpu 13
#define LSb16CA7Reg_CTRL2_mp_nisolate_cpu 13
#define bCA7Reg_CTRL2_mp_nisolate_cpu 1
#define MSK32CA7Reg_CTRL2_mp_nisolate_cpu 0x00002000
#define BA_CA7Reg_CTRL2_l2_sram_pdwn 0x0009
#define B16CA7Reg_CTRL2_l2_sram_pdwn 0x0008
#define LSb32CA7Reg_CTRL2_l2_sram_pdwn 14
#define LSb16CA7Reg_CTRL2_l2_sram_pdwn 14
#define bCA7Reg_CTRL2_l2_sram_pdwn 1
#define MSK32CA7Reg_CTRL2_l2_sram_pdwn 0x00004000
///////////////////////////////////////////////////////////
#define RA_CA7Reg_CTRL3 0x000C
#define BA_CA7Reg_CTRL3_dbgen 0x000C
#define B16CA7Reg_CTRL3_dbgen 0x000C
#define LSb32CA7Reg_CTRL3_dbgen 0
#define LSb16CA7Reg_CTRL3_dbgen 0
#define bCA7Reg_CTRL3_dbgen 2
#define MSK32CA7Reg_CTRL3_dbgen 0x00000003
#define BA_CA7Reg_CTRL3_spiden 0x000C
#define B16CA7Reg_CTRL3_spiden 0x000C
#define LSb32CA7Reg_CTRL3_spiden 2
#define LSb16CA7Reg_CTRL3_spiden 2
#define bCA7Reg_CTRL3_spiden 2
#define MSK32CA7Reg_CTRL3_spiden 0x0000000C
#define BA_CA7Reg_CTRL3_niden 0x000C
#define B16CA7Reg_CTRL3_niden 0x000C
#define LSb32CA7Reg_CTRL3_niden 4
#define LSb16CA7Reg_CTRL3_niden 4
#define bCA7Reg_CTRL3_niden 2
#define MSK32CA7Reg_CTRL3_niden 0x00000030
#define BA_CA7Reg_CTRL3_spniden 0x000C
#define B16CA7Reg_CTRL3_spniden 0x000C
#define LSb32CA7Reg_CTRL3_spniden 6
#define LSb16CA7Reg_CTRL3_spniden 6
#define bCA7Reg_CTRL3_spniden 2
#define MSK32CA7Reg_CTRL3_spniden 0x000000C0
///////////////////////////////////////////////////////////
#define RA_CA7Reg_CTRL4 0x0010
#define BA_CA7Reg_CTRL4_ACINACTM 0x0010
#define B16CA7Reg_CTRL4_ACINACTM 0x0010
#define LSb32CA7Reg_CTRL4_ACINACTM 0
#define LSb16CA7Reg_CTRL4_ACINACTM 0
#define bCA7Reg_CTRL4_ACINACTM 1
#define MSK32CA7Reg_CTRL4_ACINACTM 0x00000001
#define BA_CA7Reg_CTRL4_BROADCASTCACHEMAINT 0x0010
#define B16CA7Reg_CTRL4_BROADCASTCACHEMAINT 0x0010
#define LSb32CA7Reg_CTRL4_BROADCASTCACHEMAINT 1
#define LSb16CA7Reg_CTRL4_BROADCASTCACHEMAINT 1
#define bCA7Reg_CTRL4_BROADCASTCACHEMAINT 1
#define MSK32CA7Reg_CTRL4_BROADCASTCACHEMAINT 0x00000002
#define BA_CA7Reg_CTRL4_BROADCASTINNER 0x0010
#define B16CA7Reg_CTRL4_BROADCASTINNER 0x0010
#define LSb32CA7Reg_CTRL4_BROADCASTINNER 2
#define LSb16CA7Reg_CTRL4_BROADCASTINNER 2
#define bCA7Reg_CTRL4_BROADCASTINNER 1
#define MSK32CA7Reg_CTRL4_BROADCASTINNER 0x00000004
#define BA_CA7Reg_CTRL4_BROADCASTOUTER 0x0010
#define B16CA7Reg_CTRL4_BROADCASTOUTER 0x0010
#define LSb32CA7Reg_CTRL4_BROADCASTOUTER 3
#define LSb16CA7Reg_CTRL4_BROADCASTOUTER 3
#define bCA7Reg_CTRL4_BROADCASTOUTER 1
#define MSK32CA7Reg_CTRL4_BROADCASTOUTER 0x00000008
#define BA_CA7Reg_CTRL4_SYSBARDISABLE 0x0010
#define B16CA7Reg_CTRL4_SYSBARDISABLE 0x0010
#define LSb32CA7Reg_CTRL4_SYSBARDISABLE 4
#define LSb16CA7Reg_CTRL4_SYSBARDISABLE 4
#define bCA7Reg_CTRL4_SYSBARDISABLE 1
#define MSK32CA7Reg_CTRL4_SYSBARDISABLE 0x00000010
///////////////////////////////////////////////////////////
#define RA_CA7Reg_CTRL5 0x0014
#define BA_CA7Reg_CTRL5_IDATA_WTC 0x0014
#define B16CA7Reg_CTRL5_IDATA_WTC 0x0014
#define LSb32CA7Reg_CTRL5_IDATA_WTC 0
#define LSb16CA7Reg_CTRL5_IDATA_WTC 0
#define bCA7Reg_CTRL5_IDATA_WTC 2
#define MSK32CA7Reg_CTRL5_IDATA_WTC 0x00000003
#define BA_CA7Reg_CTRL5_IDATA_RTC 0x0014
#define B16CA7Reg_CTRL5_IDATA_RTC 0x0014
#define LSb32CA7Reg_CTRL5_IDATA_RTC 2
#define LSb16CA7Reg_CTRL5_IDATA_RTC 2
#define bCA7Reg_CTRL5_IDATA_RTC 2
#define MSK32CA7Reg_CTRL5_IDATA_RTC 0x0000000C
#define BA_CA7Reg_CTRL5_ITAG_WTC 0x0014
#define B16CA7Reg_CTRL5_ITAG_WTC 0x0014
#define LSb32CA7Reg_CTRL5_ITAG_WTC 4
#define LSb16CA7Reg_CTRL5_ITAG_WTC 4
#define bCA7Reg_CTRL5_ITAG_WTC 2
#define MSK32CA7Reg_CTRL5_ITAG_WTC 0x00000030
#define BA_CA7Reg_CTRL5_ITAG_RTC 0x0014
#define B16CA7Reg_CTRL5_ITAG_RTC 0x0014
#define LSb32CA7Reg_CTRL5_ITAG_RTC 6
#define LSb16CA7Reg_CTRL5_ITAG_RTC 6
#define bCA7Reg_CTRL5_ITAG_RTC 2
#define MSK32CA7Reg_CTRL5_ITAG_RTC 0x000000C0
#define BA_CA7Reg_CTRL5_DDATA_WTC 0x0015
#define B16CA7Reg_CTRL5_DDATA_WTC 0x0014
#define LSb32CA7Reg_CTRL5_DDATA_WTC 8
#define LSb16CA7Reg_CTRL5_DDATA_WTC 8
#define bCA7Reg_CTRL5_DDATA_WTC 2
#define MSK32CA7Reg_CTRL5_DDATA_WTC 0x00000300
#define BA_CA7Reg_CTRL5_DDATA_RTC 0x0015
#define B16CA7Reg_CTRL5_DDATA_RTC 0x0014
#define LSb32CA7Reg_CTRL5_DDATA_RTC 10
#define LSb16CA7Reg_CTRL5_DDATA_RTC 10
#define bCA7Reg_CTRL5_DDATA_RTC 2
#define MSK32CA7Reg_CTRL5_DDATA_RTC 0x00000C00
#define BA_CA7Reg_CTRL5_DTAG_WTC 0x0015
#define B16CA7Reg_CTRL5_DTAG_WTC 0x0014
#define LSb32CA7Reg_CTRL5_DTAG_WTC 12
#define LSb16CA7Reg_CTRL5_DTAG_WTC 12
#define bCA7Reg_CTRL5_DTAG_WTC 2
#define MSK32CA7Reg_CTRL5_DTAG_WTC 0x00003000
#define BA_CA7Reg_CTRL5_DTAG_RTC 0x0015
#define B16CA7Reg_CTRL5_DTAG_RTC 0x0014
#define LSb32CA7Reg_CTRL5_DTAG_RTC 14
#define LSb16CA7Reg_CTRL5_DTAG_RTC 14
#define bCA7Reg_CTRL5_DTAG_RTC 2
#define MSK32CA7Reg_CTRL5_DTAG_RTC 0x0000C000
#define BA_CA7Reg_CTRL5_DDIRTY_WTC 0x0016
#define B16CA7Reg_CTRL5_DDIRTY_WTC 0x0016
#define LSb32CA7Reg_CTRL5_DDIRTY_WTC 16
#define LSb16CA7Reg_CTRL5_DDIRTY_WTC 0
#define bCA7Reg_CTRL5_DDIRTY_WTC 2
#define MSK32CA7Reg_CTRL5_DDIRTY_WTC 0x00030000
#define BA_CA7Reg_CTRL5_DDIRTY_RTC 0x0016
#define B16CA7Reg_CTRL5_DDIRTY_RTC 0x0016
#define LSb32CA7Reg_CTRL5_DDIRTY_RTC 18
#define LSb16CA7Reg_CTRL5_DDIRTY_RTC 2
#define bCA7Reg_CTRL5_DDIRTY_RTC 2
#define MSK32CA7Reg_CTRL5_DDIRTY_RTC 0x000C0000
#define BA_CA7Reg_CTRL5_TLB_WTC 0x0016
#define B16CA7Reg_CTRL5_TLB_WTC 0x0016
#define LSb32CA7Reg_CTRL5_TLB_WTC 20
#define LSb16CA7Reg_CTRL5_TLB_WTC 4
#define bCA7Reg_CTRL5_TLB_WTC 2
#define MSK32CA7Reg_CTRL5_TLB_WTC 0x00300000
#define BA_CA7Reg_CTRL5_TLB_RTC 0x0016
#define B16CA7Reg_CTRL5_TLB_RTC 0x0016
#define LSb32CA7Reg_CTRL5_TLB_RTC 22
#define LSb16CA7Reg_CTRL5_TLB_RTC 6
#define bCA7Reg_CTRL5_TLB_RTC 2
#define MSK32CA7Reg_CTRL5_TLB_RTC 0x00C00000
#define BA_CA7Reg_CTRL5_SCU_TAG_WTC 0x0017
#define B16CA7Reg_CTRL5_SCU_TAG_WTC 0x0016
#define LSb32CA7Reg_CTRL5_SCU_TAG_WTC 24
#define LSb16CA7Reg_CTRL5_SCU_TAG_WTC 8
#define bCA7Reg_CTRL5_SCU_TAG_WTC 2
#define MSK32CA7Reg_CTRL5_SCU_TAG_WTC 0x03000000
#define BA_CA7Reg_CTRL5_SCU_TAG_RTC 0x0017
#define B16CA7Reg_CTRL5_SCU_TAG_RTC 0x0016
#define LSb32CA7Reg_CTRL5_SCU_TAG_RTC 26
#define LSb16CA7Reg_CTRL5_SCU_TAG_RTC 10
#define bCA7Reg_CTRL5_SCU_TAG_RTC 2
#define MSK32CA7Reg_CTRL5_SCU_TAG_RTC 0x0C000000
#define BA_CA7Reg_CTRL5_L2_DATA_WTC 0x0017
#define B16CA7Reg_CTRL5_L2_DATA_WTC 0x0016
#define LSb32CA7Reg_CTRL5_L2_DATA_WTC 28
#define LSb16CA7Reg_CTRL5_L2_DATA_WTC 12
#define bCA7Reg_CTRL5_L2_DATA_WTC 2
#define MSK32CA7Reg_CTRL5_L2_DATA_WTC 0x30000000
#define BA_CA7Reg_CTRL5_L2_DATA_RTC 0x0017
#define B16CA7Reg_CTRL5_L2_DATA_RTC 0x0016
#define LSb32CA7Reg_CTRL5_L2_DATA_RTC 30
#define LSb16CA7Reg_CTRL5_L2_DATA_RTC 14
#define bCA7Reg_CTRL5_L2_DATA_RTC 2
#define MSK32CA7Reg_CTRL5_L2_DATA_RTC 0xC0000000
#define RA_CA7Reg_CTRL51 0x0018
#define BA_CA7Reg_CTRL5_L2_TAG_WTC 0x0018
#define B16CA7Reg_CTRL5_L2_TAG_WTC 0x0018
#define LSb32CA7Reg_CTRL5_L2_TAG_WTC 0
#define LSb16CA7Reg_CTRL5_L2_TAG_WTC 0
#define bCA7Reg_CTRL5_L2_TAG_WTC 2
#define MSK32CA7Reg_CTRL5_L2_TAG_WTC 0x00000003
#define BA_CA7Reg_CTRL5_L2_TAG_RTC 0x0018
#define B16CA7Reg_CTRL5_L2_TAG_RTC 0x0018
#define LSb32CA7Reg_CTRL5_L2_TAG_RTC 2
#define LSb16CA7Reg_CTRL5_L2_TAG_RTC 2
#define bCA7Reg_CTRL5_L2_TAG_RTC 2
#define MSK32CA7Reg_CTRL5_L2_TAG_RTC 0x0000000C
///////////////////////////////////////////////////////////
#define RA_CA7Reg_CPUPwrCtrl 0x001C
#define BA_CA7Reg_CPUPwrCtrl_DBGPWRDUP 0x001C
#define B16CA7Reg_CPUPwrCtrl_DBGPWRDUP 0x001C
#define LSb32CA7Reg_CPUPwrCtrl_DBGPWRDUP 0
#define LSb16CA7Reg_CPUPwrCtrl_DBGPWRDUP 0
#define bCA7Reg_CPUPwrCtrl_DBGPWRDUP 2
#define MSK32CA7Reg_CPUPwrCtrl_DBGPWRDUP 0x00000003
///////////////////////////////////////////////////////////
#define RA_CA7Reg_CPU_Status 0x0020
#define BA_CA7Reg_CPU_Status_standby_wfe 0x0020
#define B16CA7Reg_CPU_Status_standby_wfe 0x0020
#define LSb32CA7Reg_CPU_Status_standby_wfe 0
#define LSb16CA7Reg_CPU_Status_standby_wfe 0
#define bCA7Reg_CPU_Status_standby_wfe 2
#define MSK32CA7Reg_CPU_Status_standby_wfe 0x00000003
#define BA_CA7Reg_CPU_Status_standby_wfi 0x0020
#define B16CA7Reg_CPU_Status_standby_wfi 0x0020
#define LSb32CA7Reg_CPU_Status_standby_wfi 2
#define LSb16CA7Reg_CPU_Status_standby_wfi 2
#define bCA7Reg_CPU_Status_standby_wfi 2
#define MSK32CA7Reg_CPU_Status_standby_wfi 0x0000000C
#define BA_CA7Reg_CPU_Status_L2standby_wfi 0x0020
#define B16CA7Reg_CPU_Status_L2standby_wfi 0x0020
#define LSb32CA7Reg_CPU_Status_L2standby_wfi 4
#define LSb16CA7Reg_CPU_Status_L2standby_wfi 4
#define bCA7Reg_CPU_Status_L2standby_wfi 1
#define MSK32CA7Reg_CPU_Status_L2standby_wfi 0x00000010
#define BA_CA7Reg_CPU_Status_ETMSTANDBYWFX 0x0020
#define B16CA7Reg_CPU_Status_ETMSTANDBYWFX 0x0020
#define LSb32CA7Reg_CPU_Status_ETMSTANDBYWFX 5
#define LSb16CA7Reg_CPU_Status_ETMSTANDBYWFX 5
#define bCA7Reg_CPU_Status_ETMSTANDBYWFX 2
#define MSK32CA7Reg_CPU_Status_ETMSTANDBYWFX 0x00000060
#define BA_CA7Reg_CPU_Status_DBGPWRUPREQ 0x0020
#define B16CA7Reg_CPU_Status_DBGPWRUPREQ 0x0020
#define LSb32CA7Reg_CPU_Status_DBGPWRUPREQ 7
#define LSb16CA7Reg_CPU_Status_DBGPWRUPREQ 7
#define bCA7Reg_CPU_Status_DBGPWRUPREQ 2
#define MSK32CA7Reg_CPU_Status_DBGPWRUPREQ 0x00000180
#define BA_CA7Reg_CPU_Status_DBGNOPWRDWN 0x0021
#define B16CA7Reg_CPU_Status_DBGNOPWRDWN 0x0020
#define LSb32CA7Reg_CPU_Status_DBGNOPWRDWN 9
#define LSb16CA7Reg_CPU_Status_DBGNOPWRDWN 9
#define bCA7Reg_CPU_Status_DBGNOPWRDWN 2
#define MSK32CA7Reg_CPU_Status_DBGNOPWRDWN 0x00000600
///////////////////////////////////////////////////////////
#define RA_CA7Reg_ETM_REG 0x0024
#define BA_CA7Reg_ETM_REG_MAXEXTIN 0x0024
#define B16CA7Reg_ETM_REG_MAXEXTIN 0x0024
#define LSb32CA7Reg_ETM_REG_MAXEXTIN 0
#define LSb16CA7Reg_ETM_REG_MAXEXTIN 0
#define bCA7Reg_ETM_REG_MAXEXTIN 3
#define MSK32CA7Reg_ETM_REG_MAXEXTIN 0x00000007
#define BA_CA7Reg_ETM_REG_MAXEXTOUT 0x0024
#define B16CA7Reg_ETM_REG_MAXEXTOUT 0x0024
#define LSb32CA7Reg_ETM_REG_MAXEXTOUT 3
#define LSb16CA7Reg_ETM_REG_MAXEXTOUT 3
#define bCA7Reg_ETM_REG_MAXEXTOUT 2
#define MSK32CA7Reg_ETM_REG_MAXEXTOUT 0x00000018
///////////////////////////////////////////////////////////
#define RA_CA7Reg_PowerStatus 0x0028
#define BA_CA7Reg_PowerStatus_l2ram_pwrsw_ack1 0x0028
#define B16CA7Reg_PowerStatus_l2ram_pwrsw_ack1 0x0028
#define LSb32CA7Reg_PowerStatus_l2ram_pwrsw_ack1 0
#define LSb16CA7Reg_PowerStatus_l2ram_pwrsw_ack1 0
#define bCA7Reg_PowerStatus_l2ram_pwrsw_ack1 1
#define MSK32CA7Reg_PowerStatus_l2ram_pwrsw_ack1 0x00000001
#define BA_CA7Reg_PowerStatus_l2ram_pwrsw_ack2 0x0028
#define B16CA7Reg_PowerStatus_l2ram_pwrsw_ack2 0x0028
#define LSb32CA7Reg_PowerStatus_l2ram_pwrsw_ack2 1
#define LSb16CA7Reg_PowerStatus_l2ram_pwrsw_ack2 1
#define bCA7Reg_PowerStatus_l2ram_pwrsw_ack2 1
#define MSK32CA7Reg_PowerStatus_l2ram_pwrsw_ack2 0x00000002
#define BA_CA7Reg_PowerStatus_mp_pwrsw_ack1 0x0028
#define B16CA7Reg_PowerStatus_mp_pwrsw_ack1 0x0028
#define LSb32CA7Reg_PowerStatus_mp_pwrsw_ack1 2
#define LSb16CA7Reg_PowerStatus_mp_pwrsw_ack1 2
#define bCA7Reg_PowerStatus_mp_pwrsw_ack1 1
#define MSK32CA7Reg_PowerStatus_mp_pwrsw_ack1 0x00000004
#define BA_CA7Reg_PowerStatus_mp_pwrsw_ack2 0x0028
#define B16CA7Reg_PowerStatus_mp_pwrsw_ack2 0x0028
#define LSb32CA7Reg_PowerStatus_mp_pwrsw_ack2 3
#define LSb16CA7Reg_PowerStatus_mp_pwrsw_ack2 3
#define bCA7Reg_PowerStatus_mp_pwrsw_ack2 1
#define MSK32CA7Reg_PowerStatus_mp_pwrsw_ack2 0x00000008
#define BA_CA7Reg_PowerStatus_cpu0_pwrsw_ack1 0x0028
#define B16CA7Reg_PowerStatus_cpu0_pwrsw_ack1 0x0028
#define LSb32CA7Reg_PowerStatus_cpu0_pwrsw_ack1 4
#define LSb16CA7Reg_PowerStatus_cpu0_pwrsw_ack1 4
#define bCA7Reg_PowerStatus_cpu0_pwrsw_ack1 1
#define MSK32CA7Reg_PowerStatus_cpu0_pwrsw_ack1 0x00000010
#define BA_CA7Reg_PowerStatus_cpu1_pwrsw_ack1 0x0028
#define B16CA7Reg_PowerStatus_cpu1_pwrsw_ack1 0x0028
#define LSb32CA7Reg_PowerStatus_cpu1_pwrsw_ack1 5
#define LSb16CA7Reg_PowerStatus_cpu1_pwrsw_ack1 5
#define bCA7Reg_PowerStatus_cpu1_pwrsw_ack1 1
#define MSK32CA7Reg_PowerStatus_cpu1_pwrsw_ack1 0x00000020
#define BA_CA7Reg_PowerStatus_cpu0_pwrsw_ack2 0x0028
#define B16CA7Reg_PowerStatus_cpu0_pwrsw_ack2 0x0028
#define LSb32CA7Reg_PowerStatus_cpu0_pwrsw_ack2 6
#define LSb16CA7Reg_PowerStatus_cpu0_pwrsw_ack2 6
#define bCA7Reg_PowerStatus_cpu0_pwrsw_ack2 1
#define MSK32CA7Reg_PowerStatus_cpu0_pwrsw_ack2 0x00000040
#define BA_CA7Reg_PowerStatus_cpu1_pwrsw_ack2 0x0028
#define B16CA7Reg_PowerStatus_cpu1_pwrsw_ack2 0x0028
#define LSb32CA7Reg_PowerStatus_cpu1_pwrsw_ack2 7
#define LSb16CA7Reg_PowerStatus_cpu1_pwrsw_ack2 7
#define bCA7Reg_PowerStatus_cpu1_pwrsw_ack2 1
#define MSK32CA7Reg_PowerStatus_cpu1_pwrsw_ack2 0x00000080
///////////////////////////////////////////////////////////
#define RA_CA7Reg_SRSoftResetn 0x002C
#define BA_CA7Reg_SRSoftResetn_SRCPURESETALL 0x002C
#define B16CA7Reg_SRSoftResetn_SRCPURESETALL 0x002C
#define LSb32CA7Reg_SRSoftResetn_SRCPURESETALL 0
#define LSb16CA7Reg_SRSoftResetn_SRCPURESETALL 0
#define bCA7Reg_SRSoftResetn_SRCPURESETALL 1
#define MSK32CA7Reg_SRSoftResetn_SRCPURESETALL 0x00000001
#define BA_CA7Reg_SRSoftResetn_SRCOREPORESET0 0x002C
#define B16CA7Reg_SRSoftResetn_SRCOREPORESET0 0x002C
#define LSb32CA7Reg_SRSoftResetn_SRCOREPORESET0 1
#define LSb16CA7Reg_SRSoftResetn_SRCOREPORESET0 1
#define bCA7Reg_SRSoftResetn_SRCOREPORESET0 1
#define MSK32CA7Reg_SRSoftResetn_SRCOREPORESET0 0x00000002
#define BA_CA7Reg_SRSoftResetn_SRCOREPORESET1 0x002C
#define B16CA7Reg_SRSoftResetn_SRCOREPORESET1 0x002C
#define LSb32CA7Reg_SRSoftResetn_SRCOREPORESET1 2
#define LSb16CA7Reg_SRSoftResetn_SRCOREPORESET1 2
#define bCA7Reg_SRSoftResetn_SRCOREPORESET1 1
#define MSK32CA7Reg_SRSoftResetn_SRCOREPORESET1 0x00000004
#define BA_CA7Reg_SRSoftResetn_SRCORERESET0 0x002C
#define B16CA7Reg_SRSoftResetn_SRCORERESET0 0x002C
#define LSb32CA7Reg_SRSoftResetn_SRCORERESET0 3
#define LSb16CA7Reg_SRSoftResetn_SRCORERESET0 3
#define bCA7Reg_SRSoftResetn_SRCORERESET0 1
#define MSK32CA7Reg_SRSoftResetn_SRCORERESET0 0x00000008
#define BA_CA7Reg_SRSoftResetn_SRCORERESET1 0x002C
#define B16CA7Reg_SRSoftResetn_SRCORERESET1 0x002C
#define LSb32CA7Reg_SRSoftResetn_SRCORERESET1 4
#define LSb16CA7Reg_SRSoftResetn_SRCORERESET1 4
#define bCA7Reg_SRSoftResetn_SRCORERESET1 1
#define MSK32CA7Reg_SRSoftResetn_SRCORERESET1 0x00000010
#define BA_CA7Reg_SRSoftResetn_SRDBGRESET0 0x002C
#define B16CA7Reg_SRSoftResetn_SRDBGRESET0 0x002C
#define LSb32CA7Reg_SRSoftResetn_SRDBGRESET0 5
#define LSb16CA7Reg_SRSoftResetn_SRDBGRESET0 5
#define bCA7Reg_SRSoftResetn_SRDBGRESET0 1
#define MSK32CA7Reg_SRSoftResetn_SRDBGRESET0 0x00000020
#define BA_CA7Reg_SRSoftResetn_SRDBGRESET1 0x002C
#define B16CA7Reg_SRSoftResetn_SRDBGRESET1 0x002C
#define LSb32CA7Reg_SRSoftResetn_SRDBGRESET1 6
#define LSb16CA7Reg_SRSoftResetn_SRDBGRESET1 6
#define bCA7Reg_SRSoftResetn_SRDBGRESET1 1
#define MSK32CA7Reg_SRSoftResetn_SRDBGRESET1 0x00000040
#define BA_CA7Reg_SRSoftResetn_SRETMRESET0 0x002C
#define B16CA7Reg_SRSoftResetn_SRETMRESET0 0x002C
#define LSb32CA7Reg_SRSoftResetn_SRETMRESET0 7
#define LSb16CA7Reg_SRSoftResetn_SRETMRESET0 7
#define bCA7Reg_SRSoftResetn_SRETMRESET0 1
#define MSK32CA7Reg_SRSoftResetn_SRETMRESET0 0x00000080
#define BA_CA7Reg_SRSoftResetn_SRETMRESET1 0x002D
#define B16CA7Reg_SRSoftResetn_SRETMRESET1 0x002C
#define LSb32CA7Reg_SRSoftResetn_SRETMRESET1 8
#define LSb16CA7Reg_SRSoftResetn_SRETMRESET1 8
#define bCA7Reg_SRSoftResetn_SRETMRESET1 1
#define MSK32CA7Reg_SRSoftResetn_SRETMRESET1 0x00000100
#define BA_CA7Reg_SRSoftResetn_SRL2RESET 0x002D
#define B16CA7Reg_SRSoftResetn_SRL2RESET 0x002C
#define LSb32CA7Reg_SRSoftResetn_SRL2RESET 9
#define LSb16CA7Reg_SRSoftResetn_SRL2RESET 9
#define bCA7Reg_SRSoftResetn_SRL2RESET 1
#define MSK32CA7Reg_SRSoftResetn_SRL2RESET 0x00000200
#define BA_CA7Reg_SRSoftResetn_SRSOCDBGRESET 0x002D
#define B16CA7Reg_SRSoftResetn_SRSOCDBGRESET 0x002C
#define LSb32CA7Reg_SRSoftResetn_SRSOCDBGRESET 10
#define LSb16CA7Reg_SRSoftResetn_SRSOCDBGRESET 10
#define bCA7Reg_SRSoftResetn_SRSOCDBGRESET 1
#define MSK32CA7Reg_SRSoftResetn_SRSOCDBGRESET 0x00000400
///////////////////////////////////////////////////////////
#define RA_CA7Reg_SoftResetn 0x0030
#define BA_CA7Reg_SoftResetn_CA7RESETALL 0x0030
#define B16CA7Reg_SoftResetn_CA7RESETALL 0x0030
#define LSb32CA7Reg_SoftResetn_CA7RESETALL 0
#define LSb16CA7Reg_SoftResetn_CA7RESETALL 0
#define bCA7Reg_SoftResetn_CA7RESETALL 1
#define MSK32CA7Reg_SoftResetn_CA7RESETALL 0x00000001
#define BA_CA7Reg_SoftResetn_COREPORESET0 0x0030
#define B16CA7Reg_SoftResetn_COREPORESET0 0x0030
#define LSb32CA7Reg_SoftResetn_COREPORESET0 1
#define LSb16CA7Reg_SoftResetn_COREPORESET0 1
#define bCA7Reg_SoftResetn_COREPORESET0 1
#define MSK32CA7Reg_SoftResetn_COREPORESET0 0x00000002
#define BA_CA7Reg_SoftResetn_COREPORESET1 0x0030
#define B16CA7Reg_SoftResetn_COREPORESET1 0x0030
#define LSb32CA7Reg_SoftResetn_COREPORESET1 2
#define LSb16CA7Reg_SoftResetn_COREPORESET1 2
#define bCA7Reg_SoftResetn_COREPORESET1 1
#define MSK32CA7Reg_SoftResetn_COREPORESET1 0x00000004
#define BA_CA7Reg_SoftResetn_CORERESET0 0x0030
#define B16CA7Reg_SoftResetn_CORERESET0 0x0030
#define LSb32CA7Reg_SoftResetn_CORERESET0 3
#define LSb16CA7Reg_SoftResetn_CORERESET0 3
#define bCA7Reg_SoftResetn_CORERESET0 1
#define MSK32CA7Reg_SoftResetn_CORERESET0 0x00000008
#define BA_CA7Reg_SoftResetn_CORERESET1 0x0030
#define B16CA7Reg_SoftResetn_CORERESET1 0x0030
#define LSb32CA7Reg_SoftResetn_CORERESET1 4
#define LSb16CA7Reg_SoftResetn_CORERESET1 4
#define bCA7Reg_SoftResetn_CORERESET1 1
#define MSK32CA7Reg_SoftResetn_CORERESET1 0x00000010
#define BA_CA7Reg_SoftResetn_DBGRESET0 0x0030
#define B16CA7Reg_SoftResetn_DBGRESET0 0x0030
#define LSb32CA7Reg_SoftResetn_DBGRESET0 5
#define LSb16CA7Reg_SoftResetn_DBGRESET0 5
#define bCA7Reg_SoftResetn_DBGRESET0 1
#define MSK32CA7Reg_SoftResetn_DBGRESET0 0x00000020
#define BA_CA7Reg_SoftResetn_DBGRESET1 0x0030
#define B16CA7Reg_SoftResetn_DBGRESET1 0x0030
#define LSb32CA7Reg_SoftResetn_DBGRESET1 6
#define LSb16CA7Reg_SoftResetn_DBGRESET1 6
#define bCA7Reg_SoftResetn_DBGRESET1 1
#define MSK32CA7Reg_SoftResetn_DBGRESET1 0x00000040
#define BA_CA7Reg_SoftResetn_ETMRESET0 0x0030
#define B16CA7Reg_SoftResetn_ETMRESET0 0x0030
#define LSb32CA7Reg_SoftResetn_ETMRESET0 7
#define LSb16CA7Reg_SoftResetn_ETMRESET0 7
#define bCA7Reg_SoftResetn_ETMRESET0 1
#define MSK32CA7Reg_SoftResetn_ETMRESET0 0x00000080
#define BA_CA7Reg_SoftResetn_ETMRESET1 0x0031
#define B16CA7Reg_SoftResetn_ETMRESET1 0x0030
#define LSb32CA7Reg_SoftResetn_ETMRESET1 8
#define LSb16CA7Reg_SoftResetn_ETMRESET1 8
#define bCA7Reg_SoftResetn_ETMRESET1 1
#define MSK32CA7Reg_SoftResetn_ETMRESET1 0x00000100
#define BA_CA7Reg_SoftResetn_SOCDBGRESET 0x0031
#define B16CA7Reg_SoftResetn_SOCDBGRESET 0x0030
#define LSb32CA7Reg_SoftResetn_SOCDBGRESET 9
#define LSb16CA7Reg_SoftResetn_SOCDBGRESET 9
#define bCA7Reg_SoftResetn_SOCDBGRESET 1
#define MSK32CA7Reg_SoftResetn_SOCDBGRESET 0x00000200
#define BA_CA7Reg_SoftResetn_L2RESET 0x0031
#define B16CA7Reg_SoftResetn_L2RESET 0x0030
#define LSb32CA7Reg_SoftResetn_L2RESET 10
#define LSb16CA7Reg_SoftResetn_L2RESET 10
#define bCA7Reg_SoftResetn_L2RESET 1
#define MSK32CA7Reg_SoftResetn_L2RESET 0x00000400
#define BA_CA7Reg_SoftResetn_MBISTRESET 0x0031
#define B16CA7Reg_SoftResetn_MBISTRESET 0x0030
#define LSb32CA7Reg_SoftResetn_MBISTRESET 11
#define LSb16CA7Reg_SoftResetn_MBISTRESET 11
#define bCA7Reg_SoftResetn_MBISTRESET 1
#define MSK32CA7Reg_SoftResetn_MBISTRESET 0x00000800
#define BA_CA7Reg_SoftResetn_CPUTimer 0x0031
#define B16CA7Reg_SoftResetn_CPUTimer 0x0030
#define LSb32CA7Reg_SoftResetn_CPUTimer 12
#define LSb16CA7Reg_SoftResetn_CPUTimer 12
#define bCA7Reg_SoftResetn_CPUTimer 1
#define MSK32CA7Reg_SoftResetn_CPUTimer 0x00001000
#define BA_CA7Reg_SoftResetn_PTMTimer 0x0031
#define B16CA7Reg_SoftResetn_PTMTimer 0x0030
#define LSb32CA7Reg_SoftResetn_PTMTimer 13
#define LSb16CA7Reg_SoftResetn_PTMTimer 13
#define bCA7Reg_SoftResetn_PTMTimer 1
#define MSK32CA7Reg_SoftResetn_PTMTimer 0x00002000
#define BA_CA7Reg_SoftResetn_CA7_SYNC_FARM 0x0031
#define B16CA7Reg_SoftResetn_CA7_SYNC_FARM 0x0030
#define LSb32CA7Reg_SoftResetn_CA7_SYNC_FARM 14
#define LSb16CA7Reg_SoftResetn_CA7_SYNC_FARM 14
#define bCA7Reg_SoftResetn_CA7_SYNC_FARM 1
#define MSK32CA7Reg_SoftResetn_CA7_SYNC_FARM 0x00004000
#define BA_CA7Reg_SoftResetn_SRAM_FNRST 0x0031
#define B16CA7Reg_SoftResetn_SRAM_FNRST 0x0030
#define LSb32CA7Reg_SoftResetn_SRAM_FNRST 15
#define LSb16CA7Reg_SoftResetn_SRAM_FNRST 15
#define bCA7Reg_SoftResetn_SRAM_FNRST 1
#define MSK32CA7Reg_SoftResetn_SRAM_FNRST 0x00008000
///////////////////////////////////////////////////////////
#define RA_CA7Reg_TimerCtrl 0x0034
#define BA_CA7Reg_TimerCtrl_CPUTimerEn 0x0034
#define B16CA7Reg_TimerCtrl_CPUTimerEn 0x0034
#define LSb32CA7Reg_TimerCtrl_CPUTimerEn 0
#define LSb16CA7Reg_TimerCtrl_CPUTimerEn 0
#define bCA7Reg_TimerCtrl_CPUTimerEn 1
#define MSK32CA7Reg_TimerCtrl_CPUTimerEn 0x00000001
#define BA_CA7Reg_TimerCtrl_CPUTimerLoad 0x0034
#define B16CA7Reg_TimerCtrl_CPUTimerLoad 0x0034
#define LSb32CA7Reg_TimerCtrl_CPUTimerLoad 1
#define LSb16CA7Reg_TimerCtrl_CPUTimerLoad 1
#define bCA7Reg_TimerCtrl_CPUTimerLoad 1
#define MSK32CA7Reg_TimerCtrl_CPUTimerLoad 0x00000002
#define RA_CA7Reg_TimerCtrl1 0x0038
#define BA_CA7Reg_TimerCtrl_CPUTimerLoadValueHi 0x0038
#define B16CA7Reg_TimerCtrl_CPUTimerLoadValueHi 0x0038
#define LSb32CA7Reg_TimerCtrl_CPUTimerLoadValueHi 0
#define LSb16CA7Reg_TimerCtrl_CPUTimerLoadValueHi 0
#define bCA7Reg_TimerCtrl_CPUTimerLoadValueHi 32
#define MSK32CA7Reg_TimerCtrl_CPUTimerLoadValueHi 0xFFFFFFFF
#define RA_CA7Reg_TimerCtrl2 0x003C
#define BA_CA7Reg_TimerCtrl_CPUTimerLoadValueLo 0x003C
#define B16CA7Reg_TimerCtrl_CPUTimerLoadValueLo 0x003C
#define LSb32CA7Reg_TimerCtrl_CPUTimerLoadValueLo 0
#define LSb16CA7Reg_TimerCtrl_CPUTimerLoadValueLo 0
#define bCA7Reg_TimerCtrl_CPUTimerLoadValueLo 32
#define MSK32CA7Reg_TimerCtrl_CPUTimerLoadValueLo 0xFFFFFFFF
#define RA_CA7Reg_TimerCtrl3 0x0040
#define BA_CA7Reg_TimerCtrl_PTMTimerEn 0x0040
#define B16CA7Reg_TimerCtrl_PTMTimerEn 0x0040
#define LSb32CA7Reg_TimerCtrl_PTMTimerEn 0
#define LSb16CA7Reg_TimerCtrl_PTMTimerEn 0
#define bCA7Reg_TimerCtrl_PTMTimerEn 1
#define MSK32CA7Reg_TimerCtrl_PTMTimerEn 0x00000001
#define BA_CA7Reg_TimerCtrl_PTMTimerLoad 0x0040
#define B16CA7Reg_TimerCtrl_PTMTimerLoad 0x0040
#define LSb32CA7Reg_TimerCtrl_PTMTimerLoad 1
#define LSb16CA7Reg_TimerCtrl_PTMTimerLoad 1
#define bCA7Reg_TimerCtrl_PTMTimerLoad 1
#define MSK32CA7Reg_TimerCtrl_PTMTimerLoad 0x00000002
#define RA_CA7Reg_TimerCtrl4 0x0044
#define BA_CA7Reg_TimerCtrl_PTMTimerLoadValueHi 0x0044
#define B16CA7Reg_TimerCtrl_PTMTimerLoadValueHi 0x0044
#define LSb32CA7Reg_TimerCtrl_PTMTimerLoadValueHi 0
#define LSb16CA7Reg_TimerCtrl_PTMTimerLoadValueHi 0
#define bCA7Reg_TimerCtrl_PTMTimerLoadValueHi 32
#define MSK32CA7Reg_TimerCtrl_PTMTimerLoadValueHi 0xFFFFFFFF
#define RA_CA7Reg_TimerCtrl5 0x0048
#define BA_CA7Reg_TimerCtrl_PTMTimerLoadValueLo 0x0048
#define B16CA7Reg_TimerCtrl_PTMTimerLoadValueLo 0x0048
#define LSb32CA7Reg_TimerCtrl_PTMTimerLoadValueLo 0
#define LSb16CA7Reg_TimerCtrl_PTMTimerLoadValueLo 0
#define bCA7Reg_TimerCtrl_PTMTimerLoadValueLo 32
#define MSK32CA7Reg_TimerCtrl_PTMTimerLoadValueLo 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_CA7Reg_TimerValue 0x004C
#define BA_CA7Reg_TimerValue_CPUTimerValueHi 0x004C
#define B16CA7Reg_TimerValue_CPUTimerValueHi 0x004C
#define LSb32CA7Reg_TimerValue_CPUTimerValueHi 0
#define LSb16CA7Reg_TimerValue_CPUTimerValueHi 0
#define bCA7Reg_TimerValue_CPUTimerValueHi 32
#define MSK32CA7Reg_TimerValue_CPUTimerValueHi 0xFFFFFFFF
#define RA_CA7Reg_TimerValue1 0x0050
#define BA_CA7Reg_TimerValue_CPUTimerValueLo 0x0050
#define B16CA7Reg_TimerValue_CPUTimerValueLo 0x0050
#define LSb32CA7Reg_TimerValue_CPUTimerValueLo 0
#define LSb16CA7Reg_TimerValue_CPUTimerValueLo 0
#define bCA7Reg_TimerValue_CPUTimerValueLo 32
#define MSK32CA7Reg_TimerValue_CPUTimerValueLo 0xFFFFFFFF
#define RA_CA7Reg_TimerValue2 0x0054
#define BA_CA7Reg_TimerValue_PTMTimerValueHi 0x0054
#define B16CA7Reg_TimerValue_PTMTimerValueHi 0x0054
#define LSb32CA7Reg_TimerValue_PTMTimerValueHi 0
#define LSb16CA7Reg_TimerValue_PTMTimerValueHi 0
#define bCA7Reg_TimerValue_PTMTimerValueHi 32
#define MSK32CA7Reg_TimerValue_PTMTimerValueHi 0xFFFFFFFF
#define RA_CA7Reg_TimerValue3 0x0058
#define BA_CA7Reg_TimerValue_PTMTimerValueLo 0x0058
#define B16CA7Reg_TimerValue_PTMTimerValueLo 0x0058
#define LSb32CA7Reg_TimerValue_PTMTimerValueLo 0
#define LSb16CA7Reg_TimerValue_PTMTimerValueLo 0
#define bCA7Reg_TimerValue_PTMTimerValueLo 32
#define MSK32CA7Reg_TimerValue_PTMTimerValueLo 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_CA7Reg_mbisr_Ctrl 0x005C
#define BA_CA7Reg_mbisr_Ctrl_efuse_TEST 0x005C
#define B16CA7Reg_mbisr_Ctrl_efuse_TEST 0x005C
#define LSb32CA7Reg_mbisr_Ctrl_efuse_TEST 0
#define LSb16CA7Reg_mbisr_Ctrl_efuse_TEST 0
#define bCA7Reg_mbisr_Ctrl_efuse_TEST 4
#define MSK32CA7Reg_mbisr_Ctrl_efuse_TEST 0x0000000F
///////////////////////////////////////////////////////////
#define RA_CA7Reg_CSSY_RWTC 0x0060
#define BA_CA7Reg_CSSY_RWTC_31to0 0x0060
#define B16CA7Reg_CSSY_RWTC_31to0 0x0060
#define LSb32CA7Reg_CSSY_RWTC_31to0 0
#define LSb16CA7Reg_CSSY_RWTC_31to0 0
#define bCA7Reg_CSSY_RWTC_31to0 32
#define MSK32CA7Reg_CSSY_RWTC_31to0 0xFFFFFFFF
#define RA_CA7Reg_CSSY_RWTC1 0x0064
#define BA_CA7Reg_CSSY_RWTC_57to32 0x0064
#define B16CA7Reg_CSSY_RWTC_57to32 0x0064
#define LSb32CA7Reg_CSSY_RWTC_57to32 0
#define LSb16CA7Reg_CSSY_RWTC_57to32 0
#define bCA7Reg_CSSY_RWTC_57to32 26
#define MSK32CA7Reg_CSSY_RWTC_57to32 0x03FFFFFF
///////////////////////////////////////////////////////////
#define RA_CA7Reg_CSSY_Ctrl 0x0068
#define BA_CA7Reg_CSSY_Ctrl_dbgen 0x0068
#define B16CA7Reg_CSSY_Ctrl_dbgen 0x0068
#define LSb32CA7Reg_CSSY_Ctrl_dbgen 0
#define LSb16CA7Reg_CSSY_Ctrl_dbgen 0
#define bCA7Reg_CSSY_Ctrl_dbgen 1
#define MSK32CA7Reg_CSSY_Ctrl_dbgen 0x00000001
#define BA_CA7Reg_CSSY_Ctrl_spiden 0x0068
#define B16CA7Reg_CSSY_Ctrl_spiden 0x0068
#define LSb32CA7Reg_CSSY_Ctrl_spiden 1
#define LSb16CA7Reg_CSSY_Ctrl_spiden 1
#define bCA7Reg_CSSY_Ctrl_spiden 1
#define MSK32CA7Reg_CSSY_Ctrl_spiden 0x00000002
#define BA_CA7Reg_CSSY_Ctrl_niden 0x0068
#define B16CA7Reg_CSSY_Ctrl_niden 0x0068
#define LSb32CA7Reg_CSSY_Ctrl_niden 2
#define LSb16CA7Reg_CSSY_Ctrl_niden 2
#define bCA7Reg_CSSY_Ctrl_niden 1
#define MSK32CA7Reg_CSSY_Ctrl_niden 0x00000004
#define BA_CA7Reg_CSSY_Ctrl_spniden 0x0068
#define B16CA7Reg_CSSY_Ctrl_spniden 0x0068
#define LSb32CA7Reg_CSSY_Ctrl_spniden 3
#define LSb16CA7Reg_CSSY_Ctrl_spniden 3
#define bCA7Reg_CSSY_Ctrl_spniden 1
#define MSK32CA7Reg_CSSY_Ctrl_spniden 0x00000008
#define BA_CA7Reg_CSSY_Ctrl_DEVICEEN 0x0068
#define B16CA7Reg_CSSY_Ctrl_DEVICEEN 0x0068
#define LSb32CA7Reg_CSSY_Ctrl_DEVICEEN 4
#define LSb16CA7Reg_CSSY_Ctrl_DEVICEEN 4
#define bCA7Reg_CSSY_Ctrl_DEVICEEN 1
#define MSK32CA7Reg_CSSY_Ctrl_DEVICEEN 0x00000010
///////////////////////////////////////////////////////////
#define RA_CA7Reg_dummy 0x006C
#define BA_CA7Reg_dummy_dummy 0x006C
#define B16CA7Reg_dummy_dummy 0x006C
#define LSb32CA7Reg_dummy_dummy 0
#define LSb16CA7Reg_dummy_dummy 0
#define bCA7Reg_dummy_dummy 32
#define MSK32CA7Reg_dummy_dummy 0xFFFFFFFF
///////////////////////////////////////////////////////////
typedef struct SIE_CA7Reg {
///////////////////////////////////////////////////////////
#define GET32CA7Reg_CTRL0_PLLBypassClkSel(r32) _BFGET_(r32, 0, 0)
#define SET32CA7Reg_CTRL0_PLLBypassClkSel(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16CA7Reg_CTRL0_PLLBypassClkSel(r16) _BFGET_(r16, 0, 0)
#define SET16CA7Reg_CTRL0_PLLBypassClkSel(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32CA7Reg_CTRL0_PW_STR(r32) _BFGET_(r32, 1, 1)
#define SET32CA7Reg_CTRL0_PW_STR(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16CA7Reg_CTRL0_PW_STR(r16) _BFGET_(r16, 1, 1)
#define SET16CA7Reg_CTRL0_PW_STR(r16,v) _BFSET_(r16, 1, 1,v)
#define w32CA7Reg_CTRL0 {\
UNSG32 uCTRL0_PLLBypassClkSel : 1;\
UNSG32 uCTRL0_PW_STR : 1;\
UNSG32 RSVDx0_b2 : 30;\
}
union { UNSG32 u32CA7Reg_CTRL0;
struct w32CA7Reg_CTRL0;
};
///////////////////////////////////////////////////////////
#define GET32CA7Reg_CTRL1_CFGEND(r32) _BFGET_(r32, 1, 0)
#define SET32CA7Reg_CTRL1_CFGEND(r32,v) _BFSET_(r32, 1, 0,v)
#define GET16CA7Reg_CTRL1_CFGEND(r16) _BFGET_(r16, 1, 0)
#define SET16CA7Reg_CTRL1_CFGEND(r16,v) _BFSET_(r16, 1, 0,v)
#define GET32CA7Reg_CTRL1_CFGTE(r32) _BFGET_(r32, 3, 2)
#define SET32CA7Reg_CTRL1_CFGTE(r32,v) _BFSET_(r32, 3, 2,v)
#define GET16CA7Reg_CTRL1_CFGTE(r16) _BFGET_(r16, 3, 2)
#define SET16CA7Reg_CTRL1_CFGTE(r16,v) _BFSET_(r16, 3, 2,v)
#define GET32CA7Reg_CTRL1_CLUSTERID(r32) _BFGET_(r32, 7, 4)
#define SET32CA7Reg_CTRL1_CLUSTERID(r32,v) _BFSET_(r32, 7, 4,v)
#define GET16CA7Reg_CTRL1_CLUSTERID(r16) _BFGET_(r16, 7, 4)
#define SET16CA7Reg_CTRL1_CLUSTERID(r16,v) _BFSET_(r16, 7, 4,v)
#define GET32CA7Reg_CTRL1_VINITHI(r32) _BFGET_(r32, 9, 8)
#define SET32CA7Reg_CTRL1_VINITHI(r32,v) _BFSET_(r32, 9, 8,v)
#define GET16CA7Reg_CTRL1_VINITHI(r16) _BFGET_(r16, 9, 8)
#define SET16CA7Reg_CTRL1_VINITHI(r16,v) _BFSET_(r16, 9, 8,v)
#define GET32CA7Reg_CTRL1_CP15SDISABLE(r32) _BFGET_(r32,11,10)
#define SET32CA7Reg_CTRL1_CP15SDISABLE(r32,v) _BFSET_(r32,11,10,v)
#define GET16CA7Reg_CTRL1_CP15SDISABLE(r16) _BFGET_(r16,11,10)
#define SET16CA7Reg_CTRL1_CP15SDISABLE(r16,v) _BFSET_(r16,11,10,v)
#define GET32CA7Reg_CTRL1_CFGSDISABLE(r32) _BFGET_(r32,12,12)
#define SET32CA7Reg_CTRL1_CFGSDISABLE(r32,v) _BFSET_(r32,12,12,v)
#define GET16CA7Reg_CTRL1_CFGSDISABLE(r16) _BFGET_(r16,12,12)
#define SET16CA7Reg_CTRL1_CFGSDISABLE(r16,v) _BFSET_(r16,12,12,v)
#define GET32CA7Reg_CTRL1_L1RSTDISABLE(r32) _BFGET_(r32,14,13)
#define SET32CA7Reg_CTRL1_L1RSTDISABLE(r32,v) _BFSET_(r32,14,13,v)
#define GET16CA7Reg_CTRL1_L1RSTDISABLE(r16) _BFGET_(r16,14,13)
#define SET16CA7Reg_CTRL1_L1RSTDISABLE(r16,v) _BFSET_(r16,14,13,v)
#define GET32CA7Reg_CTRL1_L2RSTDISABLE(r32) _BFGET_(r32,15,15)
#define SET32CA7Reg_CTRL1_L2RSTDISABLE(r32,v) _BFSET_(r32,15,15,v)
#define GET16CA7Reg_CTRL1_L2RSTDISABLE(r16) _BFGET_(r16,15,15)
#define SET16CA7Reg_CTRL1_L2RSTDISABLE(r16,v) _BFSET_(r16,15,15,v)
#define GET32CA7Reg_CTRL1_DFTRAMHOLD(r32) _BFGET_(r32,16,16)
#define SET32CA7Reg_CTRL1_DFTRAMHOLD(r32,v) _BFSET_(r32,16,16,v)
#define GET16CA7Reg_CTRL1_DFTRAMHOLD(r16) _BFGET_(r16, 0, 0)
#define SET16CA7Reg_CTRL1_DFTRAMHOLD(r16,v) _BFSET_(r16, 0, 0,v)
#define w32CA7Reg_CTRL1 {\
UNSG32 uCTRL1_CFGEND : 2;\
UNSG32 uCTRL1_CFGTE : 2;\
UNSG32 uCTRL1_CLUSTERID : 4;\
UNSG32 uCTRL1_VINITHI : 2;\
UNSG32 uCTRL1_CP15SDISABLE : 2;\
UNSG32 uCTRL1_CFGSDISABLE : 1;\
UNSG32 uCTRL1_L1RSTDISABLE : 2;\
UNSG32 uCTRL1_L2RSTDISABLE : 1;\
UNSG32 uCTRL1_DFTRAMHOLD : 1;\
UNSG32 RSVDx4_b17 : 15;\
}
union { UNSG32 u32CA7Reg_CTRL1;
struct w32CA7Reg_CTRL1;
};
///////////////////////////////////////////////////////////
#define GET32CA7Reg_CTRL2_l2ram_cntrl1_i(r32) _BFGET_(r32, 0, 0)
#define SET32CA7Reg_CTRL2_l2ram_cntrl1_i(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16CA7Reg_CTRL2_l2ram_cntrl1_i(r16) _BFGET_(r16, 0, 0)
#define SET16CA7Reg_CTRL2_l2ram_cntrl1_i(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32CA7Reg_CTRL2_l2ram_cntrl2_i(r32) _BFGET_(r32, 1, 1)
#define SET32CA7Reg_CTRL2_l2ram_cntrl2_i(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16CA7Reg_CTRL2_l2ram_cntrl2_i(r16) _BFGET_(r16, 1, 1)
#define SET16CA7Reg_CTRL2_l2ram_cntrl2_i(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32CA7Reg_CTRL2_mp_cntrl1_i(r32) _BFGET_(r32, 2, 2)
#define SET32CA7Reg_CTRL2_mp_cntrl1_i(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16CA7Reg_CTRL2_mp_cntrl1_i(r16) _BFGET_(r16, 2, 2)
#define SET16CA7Reg_CTRL2_mp_cntrl1_i(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32CA7Reg_CTRL2_mp_cntrl2_i(r32) _BFGET_(r32, 3, 3)
#define SET32CA7Reg_CTRL2_mp_cntrl2_i(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16CA7Reg_CTRL2_mp_cntrl2_i(r16) _BFGET_(r16, 3, 3)
#define SET16CA7Reg_CTRL2_mp_cntrl2_i(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32CA7Reg_CTRL2_dist_pwrsw_mp_cntrl_i(r32) _BFGET_(r32, 4, 4)
#define SET32CA7Reg_CTRL2_dist_pwrsw_mp_cntrl_i(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16CA7Reg_CTRL2_dist_pwrsw_mp_cntrl_i(r16) _BFGET_(r16, 4, 4)
#define SET16CA7Reg_CTRL2_dist_pwrsw_mp_cntrl_i(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32CA7Reg_CTRL2_cpu0_pwrsw_cntrl1_i(r32) _BFGET_(r32, 5, 5)
#define SET32CA7Reg_CTRL2_cpu0_pwrsw_cntrl1_i(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16CA7Reg_CTRL2_cpu0_pwrsw_cntrl1_i(r16) _BFGET_(r16, 5, 5)
#define SET16CA7Reg_CTRL2_cpu0_pwrsw_cntrl1_i(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32CA7Reg_CTRL2_cpu1_pwrsw_cntrl1_i(r32) _BFGET_(r32, 6, 6)
#define SET32CA7Reg_CTRL2_cpu1_pwrsw_cntrl1_i(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16CA7Reg_CTRL2_cpu1_pwrsw_cntrl1_i(r16) _BFGET_(r16, 6, 6)
#define SET16CA7Reg_CTRL2_cpu1_pwrsw_cntrl1_i(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32CA7Reg_CTRL2_cpu0_pwrsw_cntrl2_i(r32) _BFGET_(r32, 7, 7)
#define SET32CA7Reg_CTRL2_cpu0_pwrsw_cntrl2_i(r32,v) _BFSET_(r32, 7, 7,v)
#define GET16CA7Reg_CTRL2_cpu0_pwrsw_cntrl2_i(r16) _BFGET_(r16, 7, 7)
#define SET16CA7Reg_CTRL2_cpu0_pwrsw_cntrl2_i(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32CA7Reg_CTRL2_cpu1_pwrsw_cntrl2_i(r32) _BFGET_(r32, 8, 8)
#define SET32CA7Reg_CTRL2_cpu1_pwrsw_cntrl2_i(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16CA7Reg_CTRL2_cpu1_pwrsw_cntrl2_i(r16) _BFGET_(r16, 8, 8)
#define SET16CA7Reg_CTRL2_cpu1_pwrsw_cntrl2_i(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32CA7Reg_CTRL2_cpu0_dist_pwrsw_cntrl1_i(r32) _BFGET_(r32, 9, 9)
#define SET32CA7Reg_CTRL2_cpu0_dist_pwrsw_cntrl1_i(r32,v) _BFSET_(r32, 9, 9,v)
#define GET16CA7Reg_CTRL2_cpu0_dist_pwrsw_cntrl1_i(r16) _BFGET_(r16, 9, 9)
#define SET16CA7Reg_CTRL2_cpu0_dist_pwrsw_cntrl1_i(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32CA7Reg_CTRL2_cpu1_dist_pwrsw_cntrl1_i(r32) _BFGET_(r32,10,10)
#define SET32CA7Reg_CTRL2_cpu1_dist_pwrsw_cntrl1_i(r32,v) _BFSET_(r32,10,10,v)
#define GET16CA7Reg_CTRL2_cpu1_dist_pwrsw_cntrl1_i(r16) _BFGET_(r16,10,10)
#define SET16CA7Reg_CTRL2_cpu1_dist_pwrsw_cntrl1_i(r16,v) _BFSET_(r16,10,10,v)
#define GET32CA7Reg_CTRL2_cpu0_nisolate_cpu(r32) _BFGET_(r32,11,11)
#define SET32CA7Reg_CTRL2_cpu0_nisolate_cpu(r32,v) _BFSET_(r32,11,11,v)
#define GET16CA7Reg_CTRL2_cpu0_nisolate_cpu(r16) _BFGET_(r16,11,11)
#define SET16CA7Reg_CTRL2_cpu0_nisolate_cpu(r16,v) _BFSET_(r16,11,11,v)
#define GET32CA7Reg_CTRL2_cpu1_nisolate_cpu(r32) _BFGET_(r32,12,12)
#define SET32CA7Reg_CTRL2_cpu1_nisolate_cpu(r32,v) _BFSET_(r32,12,12,v)
#define GET16CA7Reg_CTRL2_cpu1_nisolate_cpu(r16) _BFGET_(r16,12,12)
#define SET16CA7Reg_CTRL2_cpu1_nisolate_cpu(r16,v) _BFSET_(r16,12,12,v)
#define GET32CA7Reg_CTRL2_mp_nisolate_cpu(r32) _BFGET_(r32,13,13)
#define SET32CA7Reg_CTRL2_mp_nisolate_cpu(r32,v) _BFSET_(r32,13,13,v)
#define GET16CA7Reg_CTRL2_mp_nisolate_cpu(r16) _BFGET_(r16,13,13)
#define SET16CA7Reg_CTRL2_mp_nisolate_cpu(r16,v) _BFSET_(r16,13,13,v)
#define GET32CA7Reg_CTRL2_l2_sram_pdwn(r32) _BFGET_(r32,14,14)
#define SET32CA7Reg_CTRL2_l2_sram_pdwn(r32,v) _BFSET_(r32,14,14,v)
#define GET16CA7Reg_CTRL2_l2_sram_pdwn(r16) _BFGET_(r16,14,14)
#define SET16CA7Reg_CTRL2_l2_sram_pdwn(r16,v) _BFSET_(r16,14,14,v)
#define w32CA7Reg_CTRL2 {\
UNSG32 uCTRL2_l2ram_cntrl1_i : 1;\
UNSG32 uCTRL2_l2ram_cntrl2_i : 1;\
UNSG32 uCTRL2_mp_cntrl1_i : 1;\
UNSG32 uCTRL2_mp_cntrl2_i : 1;\
UNSG32 uCTRL2_dist_pwrsw_mp_cntrl_i : 1;\
UNSG32 uCTRL2_cpu0_pwrsw_cntrl1_i : 1;\
UNSG32 uCTRL2_cpu1_pwrsw_cntrl1_i : 1;\
UNSG32 uCTRL2_cpu0_pwrsw_cntrl2_i : 1;\
UNSG32 uCTRL2_cpu1_pwrsw_cntrl2_i : 1;\
UNSG32 uCTRL2_cpu0_dist_pwrsw_cntrl1_i : 1;\
UNSG32 uCTRL2_cpu1_dist_pwrsw_cntrl1_i : 1;\
UNSG32 uCTRL2_cpu0_nisolate_cpu : 1;\
UNSG32 uCTRL2_cpu1_nisolate_cpu : 1;\
UNSG32 uCTRL2_mp_nisolate_cpu : 1;\
UNSG32 uCTRL2_l2_sram_pdwn : 1;\
UNSG32 RSVDx8_b15 : 17;\
}
union { UNSG32 u32CA7Reg_CTRL2;
struct w32CA7Reg_CTRL2;
};
///////////////////////////////////////////////////////////
#define GET32CA7Reg_CTRL3_dbgen(r32) _BFGET_(r32, 1, 0)
#define SET32CA7Reg_CTRL3_dbgen(r32,v) _BFSET_(r32, 1, 0,v)
#define GET16CA7Reg_CTRL3_dbgen(r16) _BFGET_(r16, 1, 0)
#define SET16CA7Reg_CTRL3_dbgen(r16,v) _BFSET_(r16, 1, 0,v)
#define GET32CA7Reg_CTRL3_spiden(r32) _BFGET_(r32, 3, 2)
#define SET32CA7Reg_CTRL3_spiden(r32,v) _BFSET_(r32, 3, 2,v)
#define GET16CA7Reg_CTRL3_spiden(r16) _BFGET_(r16, 3, 2)
#define SET16CA7Reg_CTRL3_spiden(r16,v) _BFSET_(r16, 3, 2,v)
#define GET32CA7Reg_CTRL3_niden(r32) _BFGET_(r32, 5, 4)
#define SET32CA7Reg_CTRL3_niden(r32,v) _BFSET_(r32, 5, 4,v)
#define GET16CA7Reg_CTRL3_niden(r16) _BFGET_(r16, 5, 4)
#define SET16CA7Reg_CTRL3_niden(r16,v) _BFSET_(r16, 5, 4,v)
#define GET32CA7Reg_CTRL3_spniden(r32) _BFGET_(r32, 7, 6)
#define SET32CA7Reg_CTRL3_spniden(r32,v) _BFSET_(r32, 7, 6,v)
#define GET16CA7Reg_CTRL3_spniden(r16) _BFGET_(r16, 7, 6)
#define SET16CA7Reg_CTRL3_spniden(r16,v) _BFSET_(r16, 7, 6,v)
#define w32CA7Reg_CTRL3 {\
UNSG32 uCTRL3_dbgen : 2;\
UNSG32 uCTRL3_spiden : 2;\
UNSG32 uCTRL3_niden : 2;\
UNSG32 uCTRL3_spniden : 2;\
UNSG32 RSVDxC_b8 : 24;\
}
union { UNSG32 u32CA7Reg_CTRL3;
struct w32CA7Reg_CTRL3;
};
///////////////////////////////////////////////////////////
#define GET32CA7Reg_CTRL4_ACINACTM(r32) _BFGET_(r32, 0, 0)
#define SET32CA7Reg_CTRL4_ACINACTM(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16CA7Reg_CTRL4_ACINACTM(r16) _BFGET_(r16, 0, 0)
#define SET16CA7Reg_CTRL4_ACINACTM(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32CA7Reg_CTRL4_BROADCASTCACHEMAINT(r32) _BFGET_(r32, 1, 1)
#define SET32CA7Reg_CTRL4_BROADCASTCACHEMAINT(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16CA7Reg_CTRL4_BROADCASTCACHEMAINT(r16) _BFGET_(r16, 1, 1)
#define SET16CA7Reg_CTRL4_BROADCASTCACHEMAINT(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32CA7Reg_CTRL4_BROADCASTINNER(r32) _BFGET_(r32, 2, 2)
#define SET32CA7Reg_CTRL4_BROADCASTINNER(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16CA7Reg_CTRL4_BROADCASTINNER(r16) _BFGET_(r16, 2, 2)
#define SET16CA7Reg_CTRL4_BROADCASTINNER(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32CA7Reg_CTRL4_BROADCASTOUTER(r32) _BFGET_(r32, 3, 3)
#define SET32CA7Reg_CTRL4_BROADCASTOUTER(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16CA7Reg_CTRL4_BROADCASTOUTER(r16) _BFGET_(r16, 3, 3)
#define SET16CA7Reg_CTRL4_BROADCASTOUTER(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32CA7Reg_CTRL4_SYSBARDISABLE(r32) _BFGET_(r32, 4, 4)
#define SET32CA7Reg_CTRL4_SYSBARDISABLE(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16CA7Reg_CTRL4_SYSBARDISABLE(r16) _BFGET_(r16, 4, 4)
#define SET16CA7Reg_CTRL4_SYSBARDISABLE(r16,v) _BFSET_(r16, 4, 4,v)
#define w32CA7Reg_CTRL4 {\
UNSG32 uCTRL4_ACINACTM : 1;\
UNSG32 uCTRL4_BROADCASTCACHEMAINT : 1;\
UNSG32 uCTRL4_BROADCASTINNER : 1;\
UNSG32 uCTRL4_BROADCASTOUTER : 1;\
UNSG32 uCTRL4_SYSBARDISABLE : 1;\
UNSG32 RSVDx10_b5 : 27;\
}
union { UNSG32 u32CA7Reg_CTRL4;
struct w32CA7Reg_CTRL4;
};
///////////////////////////////////////////////////////////
#define GET32CA7Reg_CTRL5_IDATA_WTC(r32) _BFGET_(r32, 1, 0)
#define SET32CA7Reg_CTRL5_IDATA_WTC(r32,v) _BFSET_(r32, 1, 0,v)
#define GET16CA7Reg_CTRL5_IDATA_WTC(r16) _BFGET_(r16, 1, 0)
#define SET16CA7Reg_CTRL5_IDATA_WTC(r16,v) _BFSET_(r16, 1, 0,v)
#define GET32CA7Reg_CTRL5_IDATA_RTC(r32) _BFGET_(r32, 3, 2)
#define SET32CA7Reg_CTRL5_IDATA_RTC(r32,v) _BFSET_(r32, 3, 2,v)
#define GET16CA7Reg_CTRL5_IDATA_RTC(r16) _BFGET_(r16, 3, 2)
#define SET16CA7Reg_CTRL5_IDATA_RTC(r16,v) _BFSET_(r16, 3, 2,v)
#define GET32CA7Reg_CTRL5_ITAG_WTC(r32) _BFGET_(r32, 5, 4)
#define SET32CA7Reg_CTRL5_ITAG_WTC(r32,v) _BFSET_(r32, 5, 4,v)
#define GET16CA7Reg_CTRL5_ITAG_WTC(r16) _BFGET_(r16, 5, 4)
#define SET16CA7Reg_CTRL5_ITAG_WTC(r16,v) _BFSET_(r16, 5, 4,v)
#define GET32CA7Reg_CTRL5_ITAG_RTC(r32) _BFGET_(r32, 7, 6)
#define SET32CA7Reg_CTRL5_ITAG_RTC(r32,v) _BFSET_(r32, 7, 6,v)
#define GET16CA7Reg_CTRL5_ITAG_RTC(r16) _BFGET_(r16, 7, 6)
#define SET16CA7Reg_CTRL5_ITAG_RTC(r16,v) _BFSET_(r16, 7, 6,v)
#define GET32CA7Reg_CTRL5_DDATA_WTC(r32) _BFGET_(r32, 9, 8)
#define SET32CA7Reg_CTRL5_DDATA_WTC(r32,v) _BFSET_(r32, 9, 8,v)
#define GET16CA7Reg_CTRL5_DDATA_WTC(r16) _BFGET_(r16, 9, 8)
#define SET16CA7Reg_CTRL5_DDATA_WTC(r16,v) _BFSET_(r16, 9, 8,v)
#define GET32CA7Reg_CTRL5_DDATA_RTC(r32) _BFGET_(r32,11,10)
#define SET32CA7Reg_CTRL5_DDATA_RTC(r32,v) _BFSET_(r32,11,10,v)
#define GET16CA7Reg_CTRL5_DDATA_RTC(r16) _BFGET_(r16,11,10)
#define SET16CA7Reg_CTRL5_DDATA_RTC(r16,v) _BFSET_(r16,11,10,v)
#define GET32CA7Reg_CTRL5_DTAG_WTC(r32) _BFGET_(r32,13,12)
#define SET32CA7Reg_CTRL5_DTAG_WTC(r32,v) _BFSET_(r32,13,12,v)
#define GET16CA7Reg_CTRL5_DTAG_WTC(r16) _BFGET_(r16,13,12)
#define SET16CA7Reg_CTRL5_DTAG_WTC(r16,v) _BFSET_(r16,13,12,v)
#define GET32CA7Reg_CTRL5_DTAG_RTC(r32) _BFGET_(r32,15,14)
#define SET32CA7Reg_CTRL5_DTAG_RTC(r32,v) _BFSET_(r32,15,14,v)
#define GET16CA7Reg_CTRL5_DTAG_RTC(r16) _BFGET_(r16,15,14)
#define SET16CA7Reg_CTRL5_DTAG_RTC(r16,v) _BFSET_(r16,15,14,v)
#define GET32CA7Reg_CTRL5_DDIRTY_WTC(r32) _BFGET_(r32,17,16)
#define SET32CA7Reg_CTRL5_DDIRTY_WTC(r32,v) _BFSET_(r32,17,16,v)
#define GET16CA7Reg_CTRL5_DDIRTY_WTC(r16) _BFGET_(r16, 1, 0)
#define SET16CA7Reg_CTRL5_DDIRTY_WTC(r16,v) _BFSET_(r16, 1, 0,v)
#define GET32CA7Reg_CTRL5_DDIRTY_RTC(r32) _BFGET_(r32,19,18)
#define SET32CA7Reg_CTRL5_DDIRTY_RTC(r32,v) _BFSET_(r32,19,18,v)
#define GET16CA7Reg_CTRL5_DDIRTY_RTC(r16) _BFGET_(r16, 3, 2)
#define SET16CA7Reg_CTRL5_DDIRTY_RTC(r16,v) _BFSET_(r16, 3, 2,v)
#define GET32CA7Reg_CTRL5_TLB_WTC(r32) _BFGET_(r32,21,20)
#define SET32CA7Reg_CTRL5_TLB_WTC(r32,v) _BFSET_(r32,21,20,v)
#define GET16CA7Reg_CTRL5_TLB_WTC(r16) _BFGET_(r16, 5, 4)
#define SET16CA7Reg_CTRL5_TLB_WTC(r16,v) _BFSET_(r16, 5, 4,v)
#define GET32CA7Reg_CTRL5_TLB_RTC(r32) _BFGET_(r32,23,22)
#define SET32CA7Reg_CTRL5_TLB_RTC(r32,v) _BFSET_(r32,23,22,v)
#define GET16CA7Reg_CTRL5_TLB_RTC(r16) _BFGET_(r16, 7, 6)
#define SET16CA7Reg_CTRL5_TLB_RTC(r16,v) _BFSET_(r16, 7, 6,v)
#define GET32CA7Reg_CTRL5_SCU_TAG_WTC(r32) _BFGET_(r32,25,24)
#define SET32CA7Reg_CTRL5_SCU_TAG_WTC(r32,v) _BFSET_(r32,25,24,v)
#define GET16CA7Reg_CTRL5_SCU_TAG_WTC(r16) _BFGET_(r16, 9, 8)
#define SET16CA7Reg_CTRL5_SCU_TAG_WTC(r16,v) _BFSET_(r16, 9, 8,v)
#define GET32CA7Reg_CTRL5_SCU_TAG_RTC(r32) _BFGET_(r32,27,26)
#define SET32CA7Reg_CTRL5_SCU_TAG_RTC(r32,v) _BFSET_(r32,27,26,v)
#define GET16CA7Reg_CTRL5_SCU_TAG_RTC(r16) _BFGET_(r16,11,10)
#define SET16CA7Reg_CTRL5_SCU_TAG_RTC(r16,v) _BFSET_(r16,11,10,v)
#define GET32CA7Reg_CTRL5_L2_DATA_WTC(r32) _BFGET_(r32,29,28)
#define SET32CA7Reg_CTRL5_L2_DATA_WTC(r32,v) _BFSET_(r32,29,28,v)
#define GET16CA7Reg_CTRL5_L2_DATA_WTC(r16) _BFGET_(r16,13,12)
#define SET16CA7Reg_CTRL5_L2_DATA_WTC(r16,v) _BFSET_(r16,13,12,v)
#define GET32CA7Reg_CTRL5_L2_DATA_RTC(r32) _BFGET_(r32,31,30)
#define SET32CA7Reg_CTRL5_L2_DATA_RTC(r32,v) _BFSET_(r32,31,30,v)
#define GET16CA7Reg_CTRL5_L2_DATA_RTC(r16) _BFGET_(r16,15,14)
#define SET16CA7Reg_CTRL5_L2_DATA_RTC(r16,v) _BFSET_(r16,15,14,v)
#define w32CA7Reg_CTRL5 {\
UNSG32 uCTRL5_IDATA_WTC : 2;\
UNSG32 uCTRL5_IDATA_RTC : 2;\
UNSG32 uCTRL5_ITAG_WTC : 2;\
UNSG32 uCTRL5_ITAG_RTC : 2;\
UNSG32 uCTRL5_DDATA_WTC : 2;\
UNSG32 uCTRL5_DDATA_RTC : 2;\
UNSG32 uCTRL5_DTAG_WTC : 2;\
UNSG32 uCTRL5_DTAG_RTC : 2;\
UNSG32 uCTRL5_DDIRTY_WTC : 2;\
UNSG32 uCTRL5_DDIRTY_RTC : 2;\
UNSG32 uCTRL5_TLB_WTC : 2;\
UNSG32 uCTRL5_TLB_RTC : 2;\
UNSG32 uCTRL5_SCU_TAG_WTC : 2;\
UNSG32 uCTRL5_SCU_TAG_RTC : 2;\
UNSG32 uCTRL5_L2_DATA_WTC : 2;\
UNSG32 uCTRL5_L2_DATA_RTC : 2;\
}
union { UNSG32 u32CA7Reg_CTRL5;
struct w32CA7Reg_CTRL5;
};
#define GET32CA7Reg_CTRL5_L2_TAG_WTC(r32) _BFGET_(r32, 1, 0)
#define SET32CA7Reg_CTRL5_L2_TAG_WTC(r32,v) _BFSET_(r32, 1, 0,v)
#define GET16CA7Reg_CTRL5_L2_TAG_WTC(r16) _BFGET_(r16, 1, 0)
#define SET16CA7Reg_CTRL5_L2_TAG_WTC(r16,v) _BFSET_(r16, 1, 0,v)
#define GET32CA7Reg_CTRL5_L2_TAG_RTC(r32) _BFGET_(r32, 3, 2)
#define SET32CA7Reg_CTRL5_L2_TAG_RTC(r32,v) _BFSET_(r32, 3, 2,v)
#define GET16CA7Reg_CTRL5_L2_TAG_RTC(r16) _BFGET_(r16, 3, 2)
#define SET16CA7Reg_CTRL5_L2_TAG_RTC(r16,v) _BFSET_(r16, 3, 2,v)
#define w32CA7Reg_CTRL51 {\
UNSG32 uCTRL5_L2_TAG_WTC : 2;\
UNSG32 uCTRL5_L2_TAG_RTC : 2;\
UNSG32 RSVDx18_b4 : 28;\
}
union { UNSG32 u32CA7Reg_CTRL51;
struct w32CA7Reg_CTRL51;
};
///////////////////////////////////////////////////////////
#define GET32CA7Reg_CPUPwrCtrl_DBGPWRDUP(r32) _BFGET_(r32, 1, 0)
#define SET32CA7Reg_CPUPwrCtrl_DBGPWRDUP(r32,v) _BFSET_(r32, 1, 0,v)
#define GET16CA7Reg_CPUPwrCtrl_DBGPWRDUP(r16) _BFGET_(r16, 1, 0)
#define SET16CA7Reg_CPUPwrCtrl_DBGPWRDUP(r16,v) _BFSET_(r16, 1, 0,v)
#define w32CA7Reg_CPUPwrCtrl {\
UNSG32 uCPUPwrCtrl_DBGPWRDUP : 2;\
UNSG32 RSVDx1C_b2 : 30;\
}
union { UNSG32 u32CA7Reg_CPUPwrCtrl;
struct w32CA7Reg_CPUPwrCtrl;
};
///////////////////////////////////////////////////////////
#define GET32CA7Reg_CPU_Status_standby_wfe(r32) _BFGET_(r32, 1, 0)
#define SET32CA7Reg_CPU_Status_standby_wfe(r32,v) _BFSET_(r32, 1, 0,v)
#define GET16CA7Reg_CPU_Status_standby_wfe(r16) _BFGET_(r16, 1, 0)
#define SET16CA7Reg_CPU_Status_standby_wfe(r16,v) _BFSET_(r16, 1, 0,v)
#define GET32CA7Reg_CPU_Status_standby_wfi(r32) _BFGET_(r32, 3, 2)
#define SET32CA7Reg_CPU_Status_standby_wfi(r32,v) _BFSET_(r32, 3, 2,v)
#define GET16CA7Reg_CPU_Status_standby_wfi(r16) _BFGET_(r16, 3, 2)
#define SET16CA7Reg_CPU_Status_standby_wfi(r16,v) _BFSET_(r16, 3, 2,v)
#define GET32CA7Reg_CPU_Status_L2standby_wfi(r32) _BFGET_(r32, 4, 4)
#define SET32CA7Reg_CPU_Status_L2standby_wfi(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16CA7Reg_CPU_Status_L2standby_wfi(r16) _BFGET_(r16, 4, 4)
#define SET16CA7Reg_CPU_Status_L2standby_wfi(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32CA7Reg_CPU_Status_ETMSTANDBYWFX(r32) _BFGET_(r32, 6, 5)
#define SET32CA7Reg_CPU_Status_ETMSTANDBYWFX(r32,v) _BFSET_(r32, 6, 5,v)
#define GET16CA7Reg_CPU_Status_ETMSTANDBYWFX(r16) _BFGET_(r16, 6, 5)
#define SET16CA7Reg_CPU_Status_ETMSTANDBYWFX(r16,v) _BFSET_(r16, 6, 5,v)
#define GET32CA7Reg_CPU_Status_DBGPWRUPREQ(r32) _BFGET_(r32, 8, 7)
#define SET32CA7Reg_CPU_Status_DBGPWRUPREQ(r32,v) _BFSET_(r32, 8, 7,v)
#define GET16CA7Reg_CPU_Status_DBGPWRUPREQ(r16) _BFGET_(r16, 8, 7)
#define SET16CA7Reg_CPU_Status_DBGPWRUPREQ(r16,v) _BFSET_(r16, 8, 7,v)
#define GET32CA7Reg_CPU_Status_DBGNOPWRDWN(r32) _BFGET_(r32,10, 9)
#define SET32CA7Reg_CPU_Status_DBGNOPWRDWN(r32,v) _BFSET_(r32,10, 9,v)
#define GET16CA7Reg_CPU_Status_DBGNOPWRDWN(r16) _BFGET_(r16,10, 9)
#define SET16CA7Reg_CPU_Status_DBGNOPWRDWN(r16,v) _BFSET_(r16,10, 9,v)
#define w32CA7Reg_CPU_Status {\
UNSG32 uCPU_Status_standby_wfe : 2;\
UNSG32 uCPU_Status_standby_wfi : 2;\
UNSG32 uCPU_Status_L2standby_wfi : 1;\
UNSG32 uCPU_Status_ETMSTANDBYWFX : 2;\
UNSG32 uCPU_Status_DBGPWRUPREQ : 2;\
UNSG32 uCPU_Status_DBGNOPWRDWN : 2;\
UNSG32 RSVDx20_b11 : 21;\
}
union { UNSG32 u32CA7Reg_CPU_Status;
struct w32CA7Reg_CPU_Status;
};
///////////////////////////////////////////////////////////
#define GET32CA7Reg_ETM_REG_MAXEXTIN(r32) _BFGET_(r32, 2, 0)
#define SET32CA7Reg_ETM_REG_MAXEXTIN(r32,v) _BFSET_(r32, 2, 0,v)
#define GET16CA7Reg_ETM_REG_MAXEXTIN(r16) _BFGET_(r16, 2, 0)
#define SET16CA7Reg_ETM_REG_MAXEXTIN(r16,v) _BFSET_(r16, 2, 0,v)
#define GET32CA7Reg_ETM_REG_MAXEXTOUT(r32) _BFGET_(r32, 4, 3)
#define SET32CA7Reg_ETM_REG_MAXEXTOUT(r32,v) _BFSET_(r32, 4, 3,v)
#define GET16CA7Reg_ETM_REG_MAXEXTOUT(r16) _BFGET_(r16, 4, 3)
#define SET16CA7Reg_ETM_REG_MAXEXTOUT(r16,v) _BFSET_(r16, 4, 3,v)
#define w32CA7Reg_ETM_REG {\
UNSG32 uETM_REG_MAXEXTIN : 3;\
UNSG32 uETM_REG_MAXEXTOUT : 2;\
UNSG32 RSVDx24_b5 : 27;\
}
union { UNSG32 u32CA7Reg_ETM_REG;
struct w32CA7Reg_ETM_REG;
};
///////////////////////////////////////////////////////////
#define GET32CA7Reg_PowerStatus_l2ram_pwrsw_ack1(r32) _BFGET_(r32, 0, 0)
#define SET32CA7Reg_PowerStatus_l2ram_pwrsw_ack1(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16CA7Reg_PowerStatus_l2ram_pwrsw_ack1(r16) _BFGET_(r16, 0, 0)
#define SET16CA7Reg_PowerStatus_l2ram_pwrsw_ack1(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32CA7Reg_PowerStatus_l2ram_pwrsw_ack2(r32) _BFGET_(r32, 1, 1)
#define SET32CA7Reg_PowerStatus_l2ram_pwrsw_ack2(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16CA7Reg_PowerStatus_l2ram_pwrsw_ack2(r16) _BFGET_(r16, 1, 1)
#define SET16CA7Reg_PowerStatus_l2ram_pwrsw_ack2(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32CA7Reg_PowerStatus_mp_pwrsw_ack1(r32) _BFGET_(r32, 2, 2)
#define SET32CA7Reg_PowerStatus_mp_pwrsw_ack1(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16CA7Reg_PowerStatus_mp_pwrsw_ack1(r16) _BFGET_(r16, 2, 2)
#define SET16CA7Reg_PowerStatus_mp_pwrsw_ack1(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32CA7Reg_PowerStatus_mp_pwrsw_ack2(r32) _BFGET_(r32, 3, 3)
#define SET32CA7Reg_PowerStatus_mp_pwrsw_ack2(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16CA7Reg_PowerStatus_mp_pwrsw_ack2(r16) _BFGET_(r16, 3, 3)
#define SET16CA7Reg_PowerStatus_mp_pwrsw_ack2(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32CA7Reg_PowerStatus_cpu0_pwrsw_ack1(r32) _BFGET_(r32, 4, 4)
#define SET32CA7Reg_PowerStatus_cpu0_pwrsw_ack1(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16CA7Reg_PowerStatus_cpu0_pwrsw_ack1(r16) _BFGET_(r16, 4, 4)
#define SET16CA7Reg_PowerStatus_cpu0_pwrsw_ack1(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32CA7Reg_PowerStatus_cpu1_pwrsw_ack1(r32) _BFGET_(r32, 5, 5)
#define SET32CA7Reg_PowerStatus_cpu1_pwrsw_ack1(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16CA7Reg_PowerStatus_cpu1_pwrsw_ack1(r16) _BFGET_(r16, 5, 5)
#define SET16CA7Reg_PowerStatus_cpu1_pwrsw_ack1(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32CA7Reg_PowerStatus_cpu0_pwrsw_ack2(r32) _BFGET_(r32, 6, 6)
#define SET32CA7Reg_PowerStatus_cpu0_pwrsw_ack2(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16CA7Reg_PowerStatus_cpu0_pwrsw_ack2(r16) _BFGET_(r16, 6, 6)
#define SET16CA7Reg_PowerStatus_cpu0_pwrsw_ack2(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32CA7Reg_PowerStatus_cpu1_pwrsw_ack2(r32) _BFGET_(r32, 7, 7)
#define SET32CA7Reg_PowerStatus_cpu1_pwrsw_ack2(r32,v) _BFSET_(r32, 7, 7,v)
#define GET16CA7Reg_PowerStatus_cpu1_pwrsw_ack2(r16) _BFGET_(r16, 7, 7)
#define SET16CA7Reg_PowerStatus_cpu1_pwrsw_ack2(r16,v) _BFSET_(r16, 7, 7,v)
#define w32CA7Reg_PowerStatus {\
UNSG32 uPowerStatus_l2ram_pwrsw_ack1 : 1;\
UNSG32 uPowerStatus_l2ram_pwrsw_ack2 : 1;\
UNSG32 uPowerStatus_mp_pwrsw_ack1 : 1;\
UNSG32 uPowerStatus_mp_pwrsw_ack2 : 1;\
UNSG32 uPowerStatus_cpu0_pwrsw_ack1 : 1;\
UNSG32 uPowerStatus_cpu1_pwrsw_ack1 : 1;\
UNSG32 uPowerStatus_cpu0_pwrsw_ack2 : 1;\
UNSG32 uPowerStatus_cpu1_pwrsw_ack2 : 1;\
UNSG32 RSVDx28_b8 : 24;\
}
union { UNSG32 u32CA7Reg_PowerStatus;
struct w32CA7Reg_PowerStatus;
};
///////////////////////////////////////////////////////////
#define GET32CA7Reg_SRSoftResetn_SRCPURESETALL(r32) _BFGET_(r32, 0, 0)
#define SET32CA7Reg_SRSoftResetn_SRCPURESETALL(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16CA7Reg_SRSoftResetn_SRCPURESETALL(r16) _BFGET_(r16, 0, 0)
#define SET16CA7Reg_SRSoftResetn_SRCPURESETALL(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32CA7Reg_SRSoftResetn_SRCOREPORESET0(r32) _BFGET_(r32, 1, 1)
#define SET32CA7Reg_SRSoftResetn_SRCOREPORESET0(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16CA7Reg_SRSoftResetn_SRCOREPORESET0(r16) _BFGET_(r16, 1, 1)
#define SET16CA7Reg_SRSoftResetn_SRCOREPORESET0(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32CA7Reg_SRSoftResetn_SRCOREPORESET1(r32) _BFGET_(r32, 2, 2)
#define SET32CA7Reg_SRSoftResetn_SRCOREPORESET1(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16CA7Reg_SRSoftResetn_SRCOREPORESET1(r16) _BFGET_(r16, 2, 2)
#define SET16CA7Reg_SRSoftResetn_SRCOREPORESET1(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32CA7Reg_SRSoftResetn_SRCORERESET0(r32) _BFGET_(r32, 3, 3)
#define SET32CA7Reg_SRSoftResetn_SRCORERESET0(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16CA7Reg_SRSoftResetn_SRCORERESET0(r16) _BFGET_(r16, 3, 3)
#define SET16CA7Reg_SRSoftResetn_SRCORERESET0(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32CA7Reg_SRSoftResetn_SRCORERESET1(r32) _BFGET_(r32, 4, 4)
#define SET32CA7Reg_SRSoftResetn_SRCORERESET1(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16CA7Reg_SRSoftResetn_SRCORERESET1(r16) _BFGET_(r16, 4, 4)
#define SET16CA7Reg_SRSoftResetn_SRCORERESET1(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32CA7Reg_SRSoftResetn_SRDBGRESET0(r32) _BFGET_(r32, 5, 5)
#define SET32CA7Reg_SRSoftResetn_SRDBGRESET0(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16CA7Reg_SRSoftResetn_SRDBGRESET0(r16) _BFGET_(r16, 5, 5)
#define SET16CA7Reg_SRSoftResetn_SRDBGRESET0(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32CA7Reg_SRSoftResetn_SRDBGRESET1(r32) _BFGET_(r32, 6, 6)
#define SET32CA7Reg_SRSoftResetn_SRDBGRESET1(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16CA7Reg_SRSoftResetn_SRDBGRESET1(r16) _BFGET_(r16, 6, 6)
#define SET16CA7Reg_SRSoftResetn_SRDBGRESET1(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32CA7Reg_SRSoftResetn_SRETMRESET0(r32) _BFGET_(r32, 7, 7)
#define SET32CA7Reg_SRSoftResetn_SRETMRESET0(r32,v) _BFSET_(r32, 7, 7,v)
#define GET16CA7Reg_SRSoftResetn_SRETMRESET0(r16) _BFGET_(r16, 7, 7)
#define SET16CA7Reg_SRSoftResetn_SRETMRESET0(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32CA7Reg_SRSoftResetn_SRETMRESET1(r32) _BFGET_(r32, 8, 8)
#define SET32CA7Reg_SRSoftResetn_SRETMRESET1(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16CA7Reg_SRSoftResetn_SRETMRESET1(r16) _BFGET_(r16, 8, 8)
#define SET16CA7Reg_SRSoftResetn_SRETMRESET1(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32CA7Reg_SRSoftResetn_SRL2RESET(r32) _BFGET_(r32, 9, 9)
#define SET32CA7Reg_SRSoftResetn_SRL2RESET(r32,v) _BFSET_(r32, 9, 9,v)
#define GET16CA7Reg_SRSoftResetn_SRL2RESET(r16) _BFGET_(r16, 9, 9)
#define SET16CA7Reg_SRSoftResetn_SRL2RESET(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32CA7Reg_SRSoftResetn_SRSOCDBGRESET(r32) _BFGET_(r32,10,10)
#define SET32CA7Reg_SRSoftResetn_SRSOCDBGRESET(r32,v) _BFSET_(r32,10,10,v)
#define GET16CA7Reg_SRSoftResetn_SRSOCDBGRESET(r16) _BFGET_(r16,10,10)
#define SET16CA7Reg_SRSoftResetn_SRSOCDBGRESET(r16,v) _BFSET_(r16,10,10,v)
#define w32CA7Reg_SRSoftResetn {\
UNSG32 uSRSoftResetn_SRCPURESETALL : 1;\
UNSG32 uSRSoftResetn_SRCOREPORESET0 : 1;\
UNSG32 uSRSoftResetn_SRCOREPORESET1 : 1;\
UNSG32 uSRSoftResetn_SRCORERESET0 : 1;\
UNSG32 uSRSoftResetn_SRCORERESET1 : 1;\
UNSG32 uSRSoftResetn_SRDBGRESET0 : 1;\
UNSG32 uSRSoftResetn_SRDBGRESET1 : 1;\
UNSG32 uSRSoftResetn_SRETMRESET0 : 1;\
UNSG32 uSRSoftResetn_SRETMRESET1 : 1;\
UNSG32 uSRSoftResetn_SRL2RESET : 1;\
UNSG32 uSRSoftResetn_SRSOCDBGRESET : 1;\
UNSG32 RSVDx2C_b11 : 21;\
}
union { UNSG32 u32CA7Reg_SRSoftResetn;
struct w32CA7Reg_SRSoftResetn;
};
///////////////////////////////////////////////////////////
#define GET32CA7Reg_SoftResetn_CA7RESETALL(r32) _BFGET_(r32, 0, 0)
#define SET32CA7Reg_SoftResetn_CA7RESETALL(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16CA7Reg_SoftResetn_CA7RESETALL(r16) _BFGET_(r16, 0, 0)
#define SET16CA7Reg_SoftResetn_CA7RESETALL(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32CA7Reg_SoftResetn_COREPORESET0(r32) _BFGET_(r32, 1, 1)
#define SET32CA7Reg_SoftResetn_COREPORESET0(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16CA7Reg_SoftResetn_COREPORESET0(r16) _BFGET_(r16, 1, 1)
#define SET16CA7Reg_SoftResetn_COREPORESET0(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32CA7Reg_SoftResetn_COREPORESET1(r32) _BFGET_(r32, 2, 2)
#define SET32CA7Reg_SoftResetn_COREPORESET1(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16CA7Reg_SoftResetn_COREPORESET1(r16) _BFGET_(r16, 2, 2)
#define SET16CA7Reg_SoftResetn_COREPORESET1(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32CA7Reg_SoftResetn_CORERESET0(r32) _BFGET_(r32, 3, 3)
#define SET32CA7Reg_SoftResetn_CORERESET0(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16CA7Reg_SoftResetn_CORERESET0(r16) _BFGET_(r16, 3, 3)
#define SET16CA7Reg_SoftResetn_CORERESET0(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32CA7Reg_SoftResetn_CORERESET1(r32) _BFGET_(r32, 4, 4)
#define SET32CA7Reg_SoftResetn_CORERESET1(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16CA7Reg_SoftResetn_CORERESET1(r16) _BFGET_(r16, 4, 4)
#define SET16CA7Reg_SoftResetn_CORERESET1(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32CA7Reg_SoftResetn_DBGRESET0(r32) _BFGET_(r32, 5, 5)
#define SET32CA7Reg_SoftResetn_DBGRESET0(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16CA7Reg_SoftResetn_DBGRESET0(r16) _BFGET_(r16, 5, 5)
#define SET16CA7Reg_SoftResetn_DBGRESET0(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32CA7Reg_SoftResetn_DBGRESET1(r32) _BFGET_(r32, 6, 6)
#define SET32CA7Reg_SoftResetn_DBGRESET1(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16CA7Reg_SoftResetn_DBGRESET1(r16) _BFGET_(r16, 6, 6)
#define SET16CA7Reg_SoftResetn_DBGRESET1(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32CA7Reg_SoftResetn_ETMRESET0(r32) _BFGET_(r32, 7, 7)
#define SET32CA7Reg_SoftResetn_ETMRESET0(r32,v) _BFSET_(r32, 7, 7,v)
#define GET16CA7Reg_SoftResetn_ETMRESET0(r16) _BFGET_(r16, 7, 7)
#define SET16CA7Reg_SoftResetn_ETMRESET0(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32CA7Reg_SoftResetn_ETMRESET1(r32) _BFGET_(r32, 8, 8)
#define SET32CA7Reg_SoftResetn_ETMRESET1(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16CA7Reg_SoftResetn_ETMRESET1(r16) _BFGET_(r16, 8, 8)
#define SET16CA7Reg_SoftResetn_ETMRESET1(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32CA7Reg_SoftResetn_SOCDBGRESET(r32) _BFGET_(r32, 9, 9)
#define SET32CA7Reg_SoftResetn_SOCDBGRESET(r32,v) _BFSET_(r32, 9, 9,v)
#define GET16CA7Reg_SoftResetn_SOCDBGRESET(r16) _BFGET_(r16, 9, 9)
#define SET16CA7Reg_SoftResetn_SOCDBGRESET(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32CA7Reg_SoftResetn_L2RESET(r32) _BFGET_(r32,10,10)
#define SET32CA7Reg_SoftResetn_L2RESET(r32,v) _BFSET_(r32,10,10,v)
#define GET16CA7Reg_SoftResetn_L2RESET(r16) _BFGET_(r16,10,10)
#define SET16CA7Reg_SoftResetn_L2RESET(r16,v) _BFSET_(r16,10,10,v)
#define GET32CA7Reg_SoftResetn_MBISTRESET(r32) _BFGET_(r32,11,11)
#define SET32CA7Reg_SoftResetn_MBISTRESET(r32,v) _BFSET_(r32,11,11,v)
#define GET16CA7Reg_SoftResetn_MBISTRESET(r16) _BFGET_(r16,11,11)
#define SET16CA7Reg_SoftResetn_MBISTRESET(r16,v) _BFSET_(r16,11,11,v)
#define GET32CA7Reg_SoftResetn_CPUTimer(r32) _BFGET_(r32,12,12)
#define SET32CA7Reg_SoftResetn_CPUTimer(r32,v) _BFSET_(r32,12,12,v)
#define GET16CA7Reg_SoftResetn_CPUTimer(r16) _BFGET_(r16,12,12)
#define SET16CA7Reg_SoftResetn_CPUTimer(r16,v) _BFSET_(r16,12,12,v)
#define GET32CA7Reg_SoftResetn_PTMTimer(r32) _BFGET_(r32,13,13)
#define SET32CA7Reg_SoftResetn_PTMTimer(r32,v) _BFSET_(r32,13,13,v)
#define GET16CA7Reg_SoftResetn_PTMTimer(r16) _BFGET_(r16,13,13)
#define SET16CA7Reg_SoftResetn_PTMTimer(r16,v) _BFSET_(r16,13,13,v)
#define GET32CA7Reg_SoftResetn_CA7_SYNC_FARM(r32) _BFGET_(r32,14,14)
#define SET32CA7Reg_SoftResetn_CA7_SYNC_FARM(r32,v) _BFSET_(r32,14,14,v)
#define GET16CA7Reg_SoftResetn_CA7_SYNC_FARM(r16) _BFGET_(r16,14,14)
#define SET16CA7Reg_SoftResetn_CA7_SYNC_FARM(r16,v) _BFSET_(r16,14,14,v)
#define GET32CA7Reg_SoftResetn_SRAM_FNRST(r32) _BFGET_(r32,15,15)
#define SET32CA7Reg_SoftResetn_SRAM_FNRST(r32,v) _BFSET_(r32,15,15,v)
#define GET16CA7Reg_SoftResetn_SRAM_FNRST(r16) _BFGET_(r16,15,15)
#define SET16CA7Reg_SoftResetn_SRAM_FNRST(r16,v) _BFSET_(r16,15,15,v)
#define w32CA7Reg_SoftResetn {\
UNSG32 uSoftResetn_CA7RESETALL : 1;\
UNSG32 uSoftResetn_COREPORESET0 : 1;\
UNSG32 uSoftResetn_COREPORESET1 : 1;\
UNSG32 uSoftResetn_CORERESET0 : 1;\
UNSG32 uSoftResetn_CORERESET1 : 1;\
UNSG32 uSoftResetn_DBGRESET0 : 1;\
UNSG32 uSoftResetn_DBGRESET1 : 1;\
UNSG32 uSoftResetn_ETMRESET0 : 1;\
UNSG32 uSoftResetn_ETMRESET1 : 1;\
UNSG32 uSoftResetn_SOCDBGRESET : 1;\
UNSG32 uSoftResetn_L2RESET : 1;\
UNSG32 uSoftResetn_MBISTRESET : 1;\
UNSG32 uSoftResetn_CPUTimer : 1;\
UNSG32 uSoftResetn_PTMTimer : 1;\
UNSG32 uSoftResetn_CA7_SYNC_FARM : 1;\
UNSG32 uSoftResetn_SRAM_FNRST : 1;\
UNSG32 RSVDx30_b16 : 16;\
}
union { UNSG32 u32CA7Reg_SoftResetn;
struct w32CA7Reg_SoftResetn;
};
///////////////////////////////////////////////////////////
#define GET32CA7Reg_TimerCtrl_CPUTimerEn(r32) _BFGET_(r32, 0, 0)
#define SET32CA7Reg_TimerCtrl_CPUTimerEn(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16CA7Reg_TimerCtrl_CPUTimerEn(r16) _BFGET_(r16, 0, 0)
#define SET16CA7Reg_TimerCtrl_CPUTimerEn(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32CA7Reg_TimerCtrl_CPUTimerLoad(r32) _BFGET_(r32, 1, 1)
#define SET32CA7Reg_TimerCtrl_CPUTimerLoad(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16CA7Reg_TimerCtrl_CPUTimerLoad(r16) _BFGET_(r16, 1, 1)
#define SET16CA7Reg_TimerCtrl_CPUTimerLoad(r16,v) _BFSET_(r16, 1, 1,v)
#define w32CA7Reg_TimerCtrl {\
UNSG32 uTimerCtrl_CPUTimerEn : 1;\
UNSG32 uTimerCtrl_CPUTimerLoad : 1;\
UNSG32 RSVDx34_b2 : 30;\
}
union { UNSG32 u32CA7Reg_TimerCtrl;
struct w32CA7Reg_TimerCtrl;
};
#define GET32CA7Reg_TimerCtrl_CPUTimerLoadValueHi(r32) _BFGET_(r32,31, 0)
#define SET32CA7Reg_TimerCtrl_CPUTimerLoadValueHi(r32,v) _BFSET_(r32,31, 0,v)
#define w32CA7Reg_TimerCtrl1 {\
UNSG32 uTimerCtrl_CPUTimerLoadValueHi : 32;\
}
union { UNSG32 u32CA7Reg_TimerCtrl1;
struct w32CA7Reg_TimerCtrl1;
};
#define GET32CA7Reg_TimerCtrl_CPUTimerLoadValueLo(r32) _BFGET_(r32,31, 0)
#define SET32CA7Reg_TimerCtrl_CPUTimerLoadValueLo(r32,v) _BFSET_(r32,31, 0,v)
#define w32CA7Reg_TimerCtrl2 {\
UNSG32 uTimerCtrl_CPUTimerLoadValueLo : 32;\
}
union { UNSG32 u32CA7Reg_TimerCtrl2;
struct w32CA7Reg_TimerCtrl2;
};
#define GET32CA7Reg_TimerCtrl_PTMTimerEn(r32) _BFGET_(r32, 0, 0)
#define SET32CA7Reg_TimerCtrl_PTMTimerEn(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16CA7Reg_TimerCtrl_PTMTimerEn(r16) _BFGET_(r16, 0, 0)
#define SET16CA7Reg_TimerCtrl_PTMTimerEn(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32CA7Reg_TimerCtrl_PTMTimerLoad(r32) _BFGET_(r32, 1, 1)
#define SET32CA7Reg_TimerCtrl_PTMTimerLoad(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16CA7Reg_TimerCtrl_PTMTimerLoad(r16) _BFGET_(r16, 1, 1)
#define SET16CA7Reg_TimerCtrl_PTMTimerLoad(r16,v) _BFSET_(r16, 1, 1,v)
#define w32CA7Reg_TimerCtrl3 {\
UNSG32 uTimerCtrl_PTMTimerEn : 1;\
UNSG32 uTimerCtrl_PTMTimerLoad : 1;\
UNSG32 RSVDx40_b2 : 30;\
}
union { UNSG32 u32CA7Reg_TimerCtrl3;
struct w32CA7Reg_TimerCtrl3;
};
#define GET32CA7Reg_TimerCtrl_PTMTimerLoadValueHi(r32) _BFGET_(r32,31, 0)
#define SET32CA7Reg_TimerCtrl_PTMTimerLoadValueHi(r32,v) _BFSET_(r32,31, 0,v)
#define w32CA7Reg_TimerCtrl4 {\
UNSG32 uTimerCtrl_PTMTimerLoadValueHi : 32;\
}
union { UNSG32 u32CA7Reg_TimerCtrl4;
struct w32CA7Reg_TimerCtrl4;
};
#define GET32CA7Reg_TimerCtrl_PTMTimerLoadValueLo(r32) _BFGET_(r32,31, 0)
#define SET32CA7Reg_TimerCtrl_PTMTimerLoadValueLo(r32,v) _BFSET_(r32,31, 0,v)
#define w32CA7Reg_TimerCtrl5 {\
UNSG32 uTimerCtrl_PTMTimerLoadValueLo : 32;\
}
union { UNSG32 u32CA7Reg_TimerCtrl5;
struct w32CA7Reg_TimerCtrl5;
};
///////////////////////////////////////////////////////////
#define GET32CA7Reg_TimerValue_CPUTimerValueHi(r32) _BFGET_(r32,31, 0)
#define SET32CA7Reg_TimerValue_CPUTimerValueHi(r32,v) _BFSET_(r32,31, 0,v)
#define w32CA7Reg_TimerValue {\
UNSG32 uTimerValue_CPUTimerValueHi : 32;\
}
union { UNSG32 u32CA7Reg_TimerValue;
struct w32CA7Reg_TimerValue;
};
#define GET32CA7Reg_TimerValue_CPUTimerValueLo(r32) _BFGET_(r32,31, 0)
#define SET32CA7Reg_TimerValue_CPUTimerValueLo(r32,v) _BFSET_(r32,31, 0,v)
#define w32CA7Reg_TimerValue1 {\
UNSG32 uTimerValue_CPUTimerValueLo : 32;\
}
union { UNSG32 u32CA7Reg_TimerValue1;
struct w32CA7Reg_TimerValue1;
};
#define GET32CA7Reg_TimerValue_PTMTimerValueHi(r32) _BFGET_(r32,31, 0)
#define SET32CA7Reg_TimerValue_PTMTimerValueHi(r32,v) _BFSET_(r32,31, 0,v)
#define w32CA7Reg_TimerValue2 {\
UNSG32 uTimerValue_PTMTimerValueHi : 32;\
}
union { UNSG32 u32CA7Reg_TimerValue2;
struct w32CA7Reg_TimerValue2;
};
#define GET32CA7Reg_TimerValue_PTMTimerValueLo(r32) _BFGET_(r32,31, 0)
#define SET32CA7Reg_TimerValue_PTMTimerValueLo(r32,v) _BFSET_(r32,31, 0,v)
#define w32CA7Reg_TimerValue3 {\
UNSG32 uTimerValue_PTMTimerValueLo : 32;\
}
union { UNSG32 u32CA7Reg_TimerValue3;
struct w32CA7Reg_TimerValue3;
};
///////////////////////////////////////////////////////////
#define GET32CA7Reg_mbisr_Ctrl_efuse_TEST(r32) _BFGET_(r32, 3, 0)
#define SET32CA7Reg_mbisr_Ctrl_efuse_TEST(r32,v) _BFSET_(r32, 3, 0,v)
#define GET16CA7Reg_mbisr_Ctrl_efuse_TEST(r16) _BFGET_(r16, 3, 0)
#define SET16CA7Reg_mbisr_Ctrl_efuse_TEST(r16,v) _BFSET_(r16, 3, 0,v)
#define w32CA7Reg_mbisr_Ctrl {\
UNSG32 umbisr_Ctrl_efuse_TEST : 4;\
UNSG32 RSVDx5C_b4 : 28;\
}
union { UNSG32 u32CA7Reg_mbisr_Ctrl;
struct w32CA7Reg_mbisr_Ctrl;
};
///////////////////////////////////////////////////////////
#define GET32CA7Reg_CSSY_RWTC_31to0(r32) _BFGET_(r32,31, 0)
#define SET32CA7Reg_CSSY_RWTC_31to0(r32,v) _BFSET_(r32,31, 0,v)
#define w32CA7Reg_CSSY_RWTC {\
UNSG32 uCSSY_RWTC_31to0 : 32;\
}
union { UNSG32 u32CA7Reg_CSSY_RWTC;
struct w32CA7Reg_CSSY_RWTC;
};
#define GET32CA7Reg_CSSY_RWTC_57to32(r32) _BFGET_(r32,25, 0)
#define SET32CA7Reg_CSSY_RWTC_57to32(r32,v) _BFSET_(r32,25, 0,v)
#define w32CA7Reg_CSSY_RWTC1 {\
UNSG32 uCSSY_RWTC_57to32 : 26;\
UNSG32 RSVDx64_b26 : 6;\
}
union { UNSG32 u32CA7Reg_CSSY_RWTC1;
struct w32CA7Reg_CSSY_RWTC1;
};
///////////////////////////////////////////////////////////
#define GET32CA7Reg_CSSY_Ctrl_dbgen(r32) _BFGET_(r32, 0, 0)
#define SET32CA7Reg_CSSY_Ctrl_dbgen(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16CA7Reg_CSSY_Ctrl_dbgen(r16) _BFGET_(r16, 0, 0)
#define SET16CA7Reg_CSSY_Ctrl_dbgen(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32CA7Reg_CSSY_Ctrl_spiden(r32) _BFGET_(r32, 1, 1)
#define SET32CA7Reg_CSSY_Ctrl_spiden(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16CA7Reg_CSSY_Ctrl_spiden(r16) _BFGET_(r16, 1, 1)
#define SET16CA7Reg_CSSY_Ctrl_spiden(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32CA7Reg_CSSY_Ctrl_niden(r32) _BFGET_(r32, 2, 2)
#define SET32CA7Reg_CSSY_Ctrl_niden(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16CA7Reg_CSSY_Ctrl_niden(r16) _BFGET_(r16, 2, 2)
#define SET16CA7Reg_CSSY_Ctrl_niden(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32CA7Reg_CSSY_Ctrl_spniden(r32) _BFGET_(r32, 3, 3)
#define SET32CA7Reg_CSSY_Ctrl_spniden(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16CA7Reg_CSSY_Ctrl_spniden(r16) _BFGET_(r16, 3, 3)
#define SET16CA7Reg_CSSY_Ctrl_spniden(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32CA7Reg_CSSY_Ctrl_DEVICEEN(r32) _BFGET_(r32, 4, 4)
#define SET32CA7Reg_CSSY_Ctrl_DEVICEEN(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16CA7Reg_CSSY_Ctrl_DEVICEEN(r16) _BFGET_(r16, 4, 4)
#define SET16CA7Reg_CSSY_Ctrl_DEVICEEN(r16,v) _BFSET_(r16, 4, 4,v)
#define w32CA7Reg_CSSY_Ctrl {\
UNSG32 uCSSY_Ctrl_dbgen : 1;\
UNSG32 uCSSY_Ctrl_spiden : 1;\
UNSG32 uCSSY_Ctrl_niden : 1;\
UNSG32 uCSSY_Ctrl_spniden : 1;\
UNSG32 uCSSY_Ctrl_DEVICEEN : 1;\
UNSG32 RSVDx68_b5 : 27;\
}
union { UNSG32 u32CA7Reg_CSSY_Ctrl;
struct w32CA7Reg_CSSY_Ctrl;
};
///////////////////////////////////////////////////////////
#define GET32CA7Reg_dummy_dummy(r32) _BFGET_(r32,31, 0)
#define SET32CA7Reg_dummy_dummy(r32,v) _BFSET_(r32,31, 0,v)
#define w32CA7Reg_dummy {\
UNSG32 udummy_dummy : 32;\
}
union { UNSG32 u32CA7Reg_dummy;
struct w32CA7Reg_dummy;
};
///////////////////////////////////////////////////////////
} SIE_CA7Reg;
typedef union T32CA7Reg_CTRL0
{ UNSG32 u32;
struct w32CA7Reg_CTRL0;
} T32CA7Reg_CTRL0;
typedef union T32CA7Reg_CTRL1
{ UNSG32 u32;
struct w32CA7Reg_CTRL1;
} T32CA7Reg_CTRL1;
typedef union T32CA7Reg_CTRL2
{ UNSG32 u32;
struct w32CA7Reg_CTRL2;
} T32CA7Reg_CTRL2;
typedef union T32CA7Reg_CTRL3
{ UNSG32 u32;
struct w32CA7Reg_CTRL3;
} T32CA7Reg_CTRL3;
typedef union T32CA7Reg_CTRL4
{ UNSG32 u32;
struct w32CA7Reg_CTRL4;
} T32CA7Reg_CTRL4;
typedef union T32CA7Reg_CTRL5
{ UNSG32 u32;
struct w32CA7Reg_CTRL5;
} T32CA7Reg_CTRL5;
typedef union T32CA7Reg_CTRL51
{ UNSG32 u32;
struct w32CA7Reg_CTRL51;
} T32CA7Reg_CTRL51;
typedef union T32CA7Reg_CPUPwrCtrl
{ UNSG32 u32;
struct w32CA7Reg_CPUPwrCtrl;
} T32CA7Reg_CPUPwrCtrl;
typedef union T32CA7Reg_CPU_Status
{ UNSG32 u32;
struct w32CA7Reg_CPU_Status;
} T32CA7Reg_CPU_Status;
typedef union T32CA7Reg_ETM_REG
{ UNSG32 u32;
struct w32CA7Reg_ETM_REG;
} T32CA7Reg_ETM_REG;
typedef union T32CA7Reg_PowerStatus
{ UNSG32 u32;
struct w32CA7Reg_PowerStatus;
} T32CA7Reg_PowerStatus;
typedef union T32CA7Reg_SRSoftResetn
{ UNSG32 u32;
struct w32CA7Reg_SRSoftResetn;
} T32CA7Reg_SRSoftResetn;
typedef union T32CA7Reg_SoftResetn
{ UNSG32 u32;
struct w32CA7Reg_SoftResetn;
} T32CA7Reg_SoftResetn;
typedef union T32CA7Reg_TimerCtrl
{ UNSG32 u32;
struct w32CA7Reg_TimerCtrl;
} T32CA7Reg_TimerCtrl;
typedef union T32CA7Reg_TimerCtrl1
{ UNSG32 u32;
struct w32CA7Reg_TimerCtrl1;
} T32CA7Reg_TimerCtrl1;
typedef union T32CA7Reg_TimerCtrl2
{ UNSG32 u32;
struct w32CA7Reg_TimerCtrl2;
} T32CA7Reg_TimerCtrl2;
typedef union T32CA7Reg_TimerCtrl3
{ UNSG32 u32;
struct w32CA7Reg_TimerCtrl3;
} T32CA7Reg_TimerCtrl3;
typedef union T32CA7Reg_TimerCtrl4
{ UNSG32 u32;
struct w32CA7Reg_TimerCtrl4;
} T32CA7Reg_TimerCtrl4;
typedef union T32CA7Reg_TimerCtrl5
{ UNSG32 u32;
struct w32CA7Reg_TimerCtrl5;
} T32CA7Reg_TimerCtrl5;
typedef union T32CA7Reg_TimerValue
{ UNSG32 u32;
struct w32CA7Reg_TimerValue;
} T32CA7Reg_TimerValue;
typedef union T32CA7Reg_TimerValue1
{ UNSG32 u32;
struct w32CA7Reg_TimerValue1;
} T32CA7Reg_TimerValue1;
typedef union T32CA7Reg_TimerValue2
{ UNSG32 u32;
struct w32CA7Reg_TimerValue2;
} T32CA7Reg_TimerValue2;
typedef union T32CA7Reg_TimerValue3
{ UNSG32 u32;
struct w32CA7Reg_TimerValue3;
} T32CA7Reg_TimerValue3;
typedef union T32CA7Reg_mbisr_Ctrl
{ UNSG32 u32;
struct w32CA7Reg_mbisr_Ctrl;
} T32CA7Reg_mbisr_Ctrl;
typedef union T32CA7Reg_CSSY_RWTC
{ UNSG32 u32;
struct w32CA7Reg_CSSY_RWTC;
} T32CA7Reg_CSSY_RWTC;
typedef union T32CA7Reg_CSSY_RWTC1
{ UNSG32 u32;
struct w32CA7Reg_CSSY_RWTC1;
} T32CA7Reg_CSSY_RWTC1;
typedef union T32CA7Reg_CSSY_Ctrl
{ UNSG32 u32;
struct w32CA7Reg_CSSY_Ctrl;
} T32CA7Reg_CSSY_Ctrl;
typedef union T32CA7Reg_dummy
{ UNSG32 u32;
struct w32CA7Reg_dummy;
} T32CA7Reg_dummy;
///////////////////////////////////////////////////////////
typedef union TCA7Reg_CTRL0
{ UNSG32 u32[1];
struct {
struct w32CA7Reg_CTRL0;
};
} TCA7Reg_CTRL0;
typedef union TCA7Reg_CTRL1
{ UNSG32 u32[1];
struct {
struct w32CA7Reg_CTRL1;
};
} TCA7Reg_CTRL1;
typedef union TCA7Reg_CTRL2
{ UNSG32 u32[1];
struct {
struct w32CA7Reg_CTRL2;
};
} TCA7Reg_CTRL2;
typedef union TCA7Reg_CTRL3
{ UNSG32 u32[1];
struct {
struct w32CA7Reg_CTRL3;
};
} TCA7Reg_CTRL3;
typedef union TCA7Reg_CTRL4
{ UNSG32 u32[1];
struct {
struct w32CA7Reg_CTRL4;
};
} TCA7Reg_CTRL4;
typedef union TCA7Reg_CTRL5
{ UNSG32 u32[2];
struct {
struct w32CA7Reg_CTRL5;
struct w32CA7Reg_CTRL51;
};
} TCA7Reg_CTRL5;
typedef union TCA7Reg_CPUPwrCtrl
{ UNSG32 u32[1];
struct {
struct w32CA7Reg_CPUPwrCtrl;
};
} TCA7Reg_CPUPwrCtrl;
typedef union TCA7Reg_CPU_Status
{ UNSG32 u32[1];
struct {
struct w32CA7Reg_CPU_Status;
};
} TCA7Reg_CPU_Status;
typedef union TCA7Reg_ETM_REG
{ UNSG32 u32[1];
struct {
struct w32CA7Reg_ETM_REG;
};
} TCA7Reg_ETM_REG;
typedef union TCA7Reg_PowerStatus
{ UNSG32 u32[1];
struct {
struct w32CA7Reg_PowerStatus;
};
} TCA7Reg_PowerStatus;
typedef union TCA7Reg_SRSoftResetn
{ UNSG32 u32[1];
struct {
struct w32CA7Reg_SRSoftResetn;
};
} TCA7Reg_SRSoftResetn;
typedef union TCA7Reg_SoftResetn
{ UNSG32 u32[1];
struct {
struct w32CA7Reg_SoftResetn;
};
} TCA7Reg_SoftResetn;
typedef union TCA7Reg_TimerCtrl
{ UNSG32 u32[6];
struct {
struct w32CA7Reg_TimerCtrl;
struct w32CA7Reg_TimerCtrl1;
struct w32CA7Reg_TimerCtrl2;
struct w32CA7Reg_TimerCtrl3;
struct w32CA7Reg_TimerCtrl4;
struct w32CA7Reg_TimerCtrl5;
};
} TCA7Reg_TimerCtrl;
typedef union TCA7Reg_TimerValue
{ UNSG32 u32[4];
struct {
struct w32CA7Reg_TimerValue;
struct w32CA7Reg_TimerValue1;
struct w32CA7Reg_TimerValue2;
struct w32CA7Reg_TimerValue3;
};
} TCA7Reg_TimerValue;
typedef union TCA7Reg_mbisr_Ctrl
{ UNSG32 u32[1];
struct {
struct w32CA7Reg_mbisr_Ctrl;
};
} TCA7Reg_mbisr_Ctrl;
typedef union TCA7Reg_CSSY_RWTC
{ UNSG32 u32[2];
struct {
struct w32CA7Reg_CSSY_RWTC;
struct w32CA7Reg_CSSY_RWTC1;
};
} TCA7Reg_CSSY_RWTC;
typedef union TCA7Reg_CSSY_Ctrl
{ UNSG32 u32[1];
struct {
struct w32CA7Reg_CSSY_Ctrl;
};
} TCA7Reg_CSSY_Ctrl;
typedef union TCA7Reg_dummy
{ UNSG32 u32[1];
struct {
struct w32CA7Reg_dummy;
};
} TCA7Reg_dummy;
///////////////////////////////////////////////////////////
SIGN32 CA7Reg_drvrd(SIE_CA7Reg *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 CA7Reg_drvwr(SIE_CA7Reg *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void CA7Reg_reset(SIE_CA7Reg *p);
SIGN32 CA7Reg_cmp (SIE_CA7Reg *p, SIE_CA7Reg *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define CA7Reg_check(p,pie,pfx,hLOG) CA7Reg_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define CA7Reg_print(p, pfx,hLOG) CA7Reg_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: CA7Reg
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE pll (4,4)
/// ###
/// * SSPLL is a differential, wide range, and low power spread-spectrum PLL that is also capable of
/// * adding in a fixed frequency offset in about 1 ppm/step resolution.
/// * .. Input Frequency: Fref: 8 MHz ~ 2 GHz
/// * Output Frequency: Fout: 9 MHz ~ 3GHz for differential outputs CLKOUTP and CLKOUTN;
/// * 9 MHz ~ 2.1 GHz for single -ended output CLKOUT.
/// * .. Fout(CLKOUT) = Fref *(4*N/M) / CLKOUT_SE_DIV_SEL
/// * Fout(CLKOUTP, CLKOUTN) = Fref*(4*N/M) / CLKOUT_DIFF_DIV_SEL
/// * M: Reference Divider: 1 to 511.
/// * N: Feedback Divider: 1 to 511.
/// * VCODIV: VCO differential divider is controlled by CLKOUT_DIFF_DIV_SEL.
/// * VCO single-ended divider is controlled by CLKOUT_SE_DIV_SEL.
/// * Divider value = 1 1,2,3,4….128.
/// * Update Rate: Fref / M = 8 to 32 MHz (to maintain the PLL stability).
/// * NOTE: Although VCO can be operated between 12 ~ 3 GHz, the 1 ~ 1.5 GHz range is
/// * applicable only in the low power mode and cannot be used with the SSC function. In order to
/// * use the SSC function VCO must be operated above 1.5GHz.
/// * .. Cycle to Cycle Jitter (max): <30 ps.
/// * .. Programmable Reference and Feedback Divider.
/// * .. 1 ppm/step frequency offset resolution. Up to 50,000 ppm without changing the Feedback
/// * Divider setting.
/// * .. SSC frequency range: 30 KHz ~ 100 KHz
/// * .. SSC amplitude range: up to +/-5%. (SSC function is disabled by default.)
/// * .. Supporting both down-spread and center-spread modes.
/// * .. Current consumption( typical corner, AVDD=1.8 V, DVDD=1.05V): see sspll document
/// * .. Locking time: < 50 us
/// * .. Process Node: 28 nm LP
/// * .. Analog Power Supply: 1.8 V (+10%, -5%)
/// * .. Digital Power Supply: 1.05 V (±10%)
/// * Support Low DVDD Mode: Digtial Power Supply = 0.75V ~ 1.32V. See section 2.1 for detail.
/// * .. Output Duty Cycle: 45% - 55% for any post divider ratio
/// * .. Built-in Bandgap circuit.
/// ###
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (P-)
/// ###
/// * PLL Control register
/// ###
/// %unsigned 1 PU 0x1
/// ###
/// * PLL Power-Up
/// * 1: power up.
/// * 0: power down.
/// ###
/// %unsigned 1 RESET 0x0
/// ###
/// * Power On Reset. Active high, reset PLL and all logic.
/// * 1: reset.
/// * 0: no reset.
/// ###
/// %unsigned 1 AVDD1815_SEL 0x1
/// ###
/// * AVDD Select.
/// * Selects whether AVDD is 1.8V
/// * or 1.5V.
/// * 1: 1.8V
/// * 0: 1.5V
/// ###
/// %unsigned 9 REFDIV 0x2
/// ###
/// * Reference Clock Divider
/// * Select.
/// * Divider = REFDIV[8:0]
/// * 9’h000 = divide by 1
/// * 9’h001 = divide by 1
/// * 9’h002 = divide by 2
/// * 9’h003 = divide by 3
/// * ...
/// * 9’h1FF = divide by 511.
/// * REFDIV[8:0] range is 1~250
/// ###
/// %unsigned 9 FBDIV 0x20
/// ###
/// * Feedback Clock Divider Select.
/// * Divider= FBDIV [8:0]
/// * 9’h000 = divide by 1
/// * 9’h001 = divide by 1
/// * 9’h002 = divide by 2
/// * 9’h003 = divide by 3
/// * ...
/// * 9’h1FF = divide by 511.
/// * FBDIV range is 9 to 94
/// ###
/// %unsigned 2 VDDM 0x1
/// ###
/// * VCO Supply Control.
/// * 11: 1.3 V
/// * 10: 1.25 V
/// * 01: 1.2 V
/// * 00: 1.15 V.
/// ###
/// %unsigned 3 VDDL 0x4
/// ###
/// * Internal VDD Supply
/// * Control.
/// * 000:0.9V
/// * 001:0.95V
/// * 010:1V
/// * 011:1.05V
/// * 100:1.1V
/// * 101:1.15V
/// * 110:1.2V
/// * 111:1.2V.
/// ###
/// %unsigned 4 ICP 0x1
/// ###
/// * Charge-pump Current Control Bits.
/// * 0000: 3 uA
/// * 0001: 3.75 uA
/// * 0010: 4.5 uA
/// * 0011: 5.25 uA
/// * 0100: 6 uA
/// * 0101: 7.5 uA
/// * 0110: 9 uA
/// * 0111: 10.5 uA
/// * 1000: 12 uA
/// * 1001: 15 uA
/// * 1010: 18 uA
/// * 1011: 21 uA
/// * 1100: 24 uA
/// * 1101: 30 uA
/// * 1110: 36 uA
/// * 1111: 42 uA.
/// * Note : ICP[3:0] = (10 MHz / Update Rate) * Default.
/// * If PU_BW_SEL = 1, then increase ICP value by 2x
/// ###
/// %unsigned 1 PLL_BW_SEL 0x0
/// ###
/// * PLL Bandwidth Select.
/// * 1: BW x 2
/// * 0: Normal PLL bandwidth.
/// * Note: Use bandwidth x 2 only if update rate is between 16 - 32 MHz.
/// * NOTE: Bandwidth x 2 is for special cases only. If used, the update rate must be between 16 MHz - 32 MHz.
/// ###
/// %% 1 # Stuffing bits...
/// # 0x00004 ctrl1
/// %unsigned 4 KVCO 0xA
/// ###
/// * KVCO Frequency Range
/// * Select.
/// * 0000~0111: Reserved.
/// * 1000:1.2GHz ~ 1.35GHz
/// * 1001:1.35GHz ~ 1.5GHz
/// * 1010:1.5GHz ~ 1.75GHz
/// * 1011:1.75GHz ~ 2.00GHz
/// * 1100: 2GHz ~ 2.2GHz
/// * 1101: 2.2GHz ~ 2.4GHz
/// * 1110: 2.4GHz ~ 2.6GHz
/// * 1111: 2.6GHz ~ 3GHz
/// * SSC mode is only supported for frequency >=2 GHz
/// * FVCO=((4*REFCLK/M)*N)/(1+OFFSET_PERCENT)
/// ###
/// %unsigned 2 CTUNE 0x1
/// ###
/// * VCO Capacitor Select.
/// * 00: No Cap Loading
/// * 01: One Unit Cap Loading
/// * 10: Two Unit Cap Loading
/// * 11: Three Unit Cap Loading.
/// ###
/// %unsigned 3 CLKOUT_DIFF_DIV_SEL 0x2
/// ###
/// * Post Divider For Differential
/// * Output Clock.
/// * 000: 1
/// * 001: 2
/// * 010: 4
/// * 011: 8
/// * 100: 16
/// * 101: 32
/// * 110: 64
/// * 111:128
/// ###
/// %unsigned 3 CLKOUT_SE_DIV_SEL 0x2
/// ###
/// * Post Divider For
/// * Single-ended Output Clock.
/// * 000: 1
/// * 001: 2
/// * 010: 4
/// * 011: 8
/// * 100: 16
/// * 101: 32
/// * 110: 64
/// * 111:128
/// ###
/// %unsigned 1 CLKOUT_SOURCE_SEL 0x1
/// ###
/// * Differential Clock And
/// * Single-ended Clock Source Control.
/// * 0: from the phase interpolator.
/// * 1: from VCO directly.
/// * Note: This is used in test mode only. Select ‘1’ for normal operation.
/// ###
/// %unsigned 1 CLKOUT_DIFF_EN 0x1
/// ###
/// * Differential Clock Enable.
/// * 0:Disable differential clock
/// * 1:Enable differential clock
/// ###
/// %unsigned 1 BYPASS_EN 0x0
/// ###
/// * PLL Clock Bypass Enable.
/// * 1: The PLL is bypassed. CLKOUT is derived from REFCLK.
/// * 0: CLKOUT is derived from the PLL clock.
/// * NOTE: Bypass only works for the single ended clock.
/// * If BYPASS_EN==1. CLKOUT= REFCLK.
/// * Make sure Fvco/CLKOUT_SE_DIV_SEL< 2.1 GHz, when using the bypass function.
/// ###
/// %unsigned 1 CLKOUT_SE_GATING_EN 0x0
/// ###
/// * Clock Output Gating Control.
/// * Selection for using the PLL lock signal to gate the output clock.
/// * 0: The PLL_LOCK signal won't affect the output clock, CLKOUT
/// * 1: Use PLL_LOCK signal to gate the output clock, CLKOUT.
/// ###
/// %unsigned 1 FBCLK_EXT_SEL 0x0
/// ###
/// * External Or Internal Feedback
/// * Clock Select.
/// * 0: select internal feedback clock
/// * 1: select external feedback clock.
/// * Note: For most applications the external feedback clock is not used. In these cases use the default selection "0".
/// ###
/// %unsigned 6 FBCDLY 0x0
/// ###
/// * Fine Tune Delay Select
/// * Between REFCLK And FBCLK_EXT When FBCLK_EXT_SEL = 1.
/// * FBCDLY[5] is the sign bit.
/// * 1 = FBCLK_EXT will lag REFCLK.
/// * 0 = FBCLK_EXT will lead REFCLK.
/// * FBCDLY[4:0] decides the actual amount of delay.
/// * 00000: No delay.
/// * Each additional step has these
/// * delays:
/// * 00h = No delay
/// * 01h = 15 - 50 ps phase difference
/// * 02h = 30 - 100 ps phase difference
/// * 03h = 45 - 150 ps phase difference
/// * ...
/// * 3Fh = 945 ps - 3150 ps phase difference.
/// * Note: Used in DSPLL application, do not use in regular PLL application.
/// ###
/// %unsigned 3 FD 0x4
/// ###
/// * Tune Frequency Detector Precision
/// * FD[0]: Reserved.
/// * FD[2:1] FD precision
/// * 00 +/- 0.1%
/// * 01 +/- 0.2%
/// * 10 +/- 0.4%
/// * 11 +/- 0.8%.
/// ###
/// %unsigned 4 INTPI 0x6
/// ###
/// * Phase Interpolator Bias Current Select.
/// * 1.2 ~ 1.5 GHz NOT SUPPORTED
/// * 0101: (VCO:1.5 ~ 2 GHz)
/// * 0110: (VCO:2 ~ 2.5 GHz)
/// * 1000: (VCO:2.5 ~ 3GHz).
/// * NOTE: VCO running frequency below 1.5 GHz not supported.
/// ###
/// %% 2 # Stuffing bits...
/// # 0x00008 ctrl2
/// %unsigned 3 INTPR 0x4
/// ###
/// * Phase Interpolator Resistor Select.
/// * NOTE: VCO running frequency below 1.5 GHz not supported.
/// ###
/// %unsigned 1 PI_EN 0x0
/// ###
/// * Phase Interpolator Enable.
/// * 1: Enable phase interpolator
/// * 0: Disable phase interpolator.
/// ###
/// %unsigned 1 PI_LOOP_MODE 0x0
/// ###
/// * Phase Interpolator Loop Control.
/// * 1: PI is in the PLL loop.
/// * 0: PI is out of the PLL loop
/// ###
/// %unsigned 1 CLK_DET_EN 0x1
/// ###
/// * PI Output Clock Enable. This selection enables the PI output clock for the internal reset circuit
/// ###
/// %unsigned 1 RESET_PI 0x0
/// ###
/// * External Interpolator Reset.
/// * 1: reset.
/// * 0: no reset.
/// ###
/// %unsigned 1 RESET_SSC 0x0
/// ###
/// * SSC reset
/// * 0 : No reset
/// * 1 : Reset
/// ###
/// %unsigned 1 FREQ_OFFSET_EN 0x0
/// ###
/// * Frequency Offset Enable.
/// * 0: Disable
/// * 1: Enable.
/// ###
/// %unsigned 17 FREQ_OFFSET 0x0
/// ###
/// * Frequency Offset Value
/// * Control.
/// * [16]: Sign-Bit.
/// * 0: Frequency down
/// * 1: Frequency up
/// * [15:0] : 1 LSB 1 ppm, upto 5%
/// * 1LSB=10e6/(4*128 *2048) ppm
/// * [16]=0--->Sign= 1
/// * [16]=1--->Sign= -1
/// * Fout = Fvco/ (1 + Sign* FREQ_OFFSET[15:0] *1LSB)
/// ###
/// %unsigned 1 FREQ_OFFSET_MODE_SELECTION 0x0
/// ###
/// * Frequency Offset Mode Select.
/// * 0: FREQ_OFFSET[16:0] is updated by FREQ_OFFSET_VALID
/// * 1: FREQ_OFFSET[16:0] is sampled by CK_DIV64_OUT
/// * (It has to be valid at the rising edge of CK_DIV64_OUT).
/// * Note: For special application only. Use FREQ_OFFSET_VALID to update FREQ_OFFSET[16:0] by default.
/// ###
/// %unsigned 1 FREQ_OFFSET_VALID 0x0
/// ###
/// * Frequency Offset Value Valid.
/// * Indicates that frequency offset value (FREQ_OFFSET[16:0]) is valid.
/// * Note:
/// * 1) A rising edge will trigger the frequency offset generation circuit to read in the FREQ_OFFSET [16:0] value. The pulse width has to be no less than 50 ns.
/// * 2) This signal is only needed when FREQ_OFFSET_MODE_SELECTION=0.
/// ###
/// %unsigned 1 SSC_CLK_EN 0x0
/// ###
/// * SSC Clock Enable.
/// * This selection enables the PI output clock for SSC digital logic.
/// ###
/// %unsigned 1 SSC_MODE 0x1
/// ###
/// * SSC Mode Select.
/// * 0: center spread
/// * 1: down spread.
/// ###
/// %% 2 # Stuffing bits...
/// # 0x0000C ctrl3
/// %unsigned 16 SSC_FREQ_DIV 0x0
/// ###
/// * SSC Frequency Select.
/// ###
/// %unsigned 11 SSC_RNGE 0x0
/// ###
/// * SSC Range Select. SSC_RNGE[10:0] = Desired SSC amplitude /(SSC_FREQ_DIV[14:0]*2^(-28)).
/// * Rounding to integer required.
/// ###
/// %unsigned 4 TEST_ANA 0x0
/// ###
/// * Analog test point
/// ###
/// %% 1 # Stuffing bits...
/// # 0x00010 ctrl4
/// %unsigned 8 RESERVE_IN 0x0
/// ###
/// * Reserved input pins
/// ###
/// %% 24 # Stuffing bits...
/// @ 0x00014 status (R-)
/// ###
/// * PLL status register
/// ###
/// %unsigned 1 PLL_LOCK
/// ###
/// * PLL Lock Detect.
/// * 1: PLL locked.
/// * 0: PLL not locked.
/// * Note:
/// * After PLL is powered up, wait for 50 us to check for the lock status.
/// * In normal operation, when PLL_LOCK signal is detected low, sample the signal again after 100 us to confirm the status.
/// * This signal is for testing purpose only, do not use it for any functional use.
/// ###
/// %unsigned 1 CLK_CFMOD
/// ###
/// * Clock Mode Output.
/// * • For down spread and
/// * PI_LOOP_MODE = 0, output
/// * is 0.
/// * • For down spread and
/// * PI_LOOP_MODE = 1, output
/// * is 1.
/// * • For center spread, output a
/// * clock with SSC modulation
/// * frequency.
/// ###
/// %unsigned 1 CLK_FMOD
/// ###
/// * Clock Output And Modulation
/// * Frequency.
/// * For down spread, output a clock
/// * with SSC modulation frequency.
/// * For center spread, output a clock
/// * with double SSC modulation
/// * frequency.
/// ###
/// %unsigned 8 RESERVE_OUT
/// ###
/// * Reserve Output Register pins.
/// ###
/// %% 21 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 24B, bits: 141b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_pll
#define h_pll (){}
#define RA_pll_ctrl 0x0000
#define BA_pll_ctrl_PU 0x0000
#define B16pll_ctrl_PU 0x0000
#define LSb32pll_ctrl_PU 0
#define LSb16pll_ctrl_PU 0
#define bpll_ctrl_PU 1
#define MSK32pll_ctrl_PU 0x00000001
#define BA_pll_ctrl_RESET 0x0000
#define B16pll_ctrl_RESET 0x0000
#define LSb32pll_ctrl_RESET 1
#define LSb16pll_ctrl_RESET 1
#define bpll_ctrl_RESET 1
#define MSK32pll_ctrl_RESET 0x00000002
#define BA_pll_ctrl_AVDD1815_SEL 0x0000
#define B16pll_ctrl_AVDD1815_SEL 0x0000
#define LSb32pll_ctrl_AVDD1815_SEL 2
#define LSb16pll_ctrl_AVDD1815_SEL 2
#define bpll_ctrl_AVDD1815_SEL 1
#define MSK32pll_ctrl_AVDD1815_SEL 0x00000004
#define BA_pll_ctrl_REFDIV 0x0000
#define B16pll_ctrl_REFDIV 0x0000
#define LSb32pll_ctrl_REFDIV 3
#define LSb16pll_ctrl_REFDIV 3
#define bpll_ctrl_REFDIV 9
#define MSK32pll_ctrl_REFDIV 0x00000FF8
#define BA_pll_ctrl_FBDIV 0x0001
#define B16pll_ctrl_FBDIV 0x0000
#define LSb32pll_ctrl_FBDIV 12
#define LSb16pll_ctrl_FBDIV 12
#define bpll_ctrl_FBDIV 9
#define MSK32pll_ctrl_FBDIV 0x001FF000
#define BA_pll_ctrl_VDDM 0x0002
#define B16pll_ctrl_VDDM 0x0002
#define LSb32pll_ctrl_VDDM 21
#define LSb16pll_ctrl_VDDM 5
#define bpll_ctrl_VDDM 2
#define MSK32pll_ctrl_VDDM 0x00600000
#define BA_pll_ctrl_VDDL 0x0002
#define B16pll_ctrl_VDDL 0x0002
#define LSb32pll_ctrl_VDDL 23
#define LSb16pll_ctrl_VDDL 7
#define bpll_ctrl_VDDL 3
#define MSK32pll_ctrl_VDDL 0x03800000
#define BA_pll_ctrl_ICP 0x0003
#define B16pll_ctrl_ICP 0x0002
#define LSb32pll_ctrl_ICP 26
#define LSb16pll_ctrl_ICP 10
#define bpll_ctrl_ICP 4
#define MSK32pll_ctrl_ICP 0x3C000000
#define BA_pll_ctrl_PLL_BW_SEL 0x0003
#define B16pll_ctrl_PLL_BW_SEL 0x0002
#define LSb32pll_ctrl_PLL_BW_SEL 30
#define LSb16pll_ctrl_PLL_BW_SEL 14
#define bpll_ctrl_PLL_BW_SEL 1
#define MSK32pll_ctrl_PLL_BW_SEL 0x40000000
#define RA_pll_ctrl1 0x0004
#define BA_pll_ctrl_KVCO 0x0004
#define B16pll_ctrl_KVCO 0x0004
#define LSb32pll_ctrl_KVCO 0
#define LSb16pll_ctrl_KVCO 0
#define bpll_ctrl_KVCO 4
#define MSK32pll_ctrl_KVCO 0x0000000F
#define BA_pll_ctrl_CTUNE 0x0004
#define B16pll_ctrl_CTUNE 0x0004
#define LSb32pll_ctrl_CTUNE 4
#define LSb16pll_ctrl_CTUNE 4
#define bpll_ctrl_CTUNE 2
#define MSK32pll_ctrl_CTUNE 0x00000030
#define BA_pll_ctrl_CLKOUT_DIFF_DIV_SEL 0x0004
#define B16pll_ctrl_CLKOUT_DIFF_DIV_SEL 0x0004
#define LSb32pll_ctrl_CLKOUT_DIFF_DIV_SEL 6
#define LSb16pll_ctrl_CLKOUT_DIFF_DIV_SEL 6
#define bpll_ctrl_CLKOUT_DIFF_DIV_SEL 3
#define MSK32pll_ctrl_CLKOUT_DIFF_DIV_SEL 0x000001C0
#define BA_pll_ctrl_CLKOUT_SE_DIV_SEL 0x0005
#define B16pll_ctrl_CLKOUT_SE_DIV_SEL 0x0004
#define LSb32pll_ctrl_CLKOUT_SE_DIV_SEL 9
#define LSb16pll_ctrl_CLKOUT_SE_DIV_SEL 9
#define bpll_ctrl_CLKOUT_SE_DIV_SEL 3
#define MSK32pll_ctrl_CLKOUT_SE_DIV_SEL 0x00000E00
#define BA_pll_ctrl_CLKOUT_SOURCE_SEL 0x0005
#define B16pll_ctrl_CLKOUT_SOURCE_SEL 0x0004
#define LSb32pll_ctrl_CLKOUT_SOURCE_SEL 12
#define LSb16pll_ctrl_CLKOUT_SOURCE_SEL 12
#define bpll_ctrl_CLKOUT_SOURCE_SEL 1
#define MSK32pll_ctrl_CLKOUT_SOURCE_SEL 0x00001000
#define BA_pll_ctrl_CLKOUT_DIFF_EN 0x0005
#define B16pll_ctrl_CLKOUT_DIFF_EN 0x0004
#define LSb32pll_ctrl_CLKOUT_DIFF_EN 13
#define LSb16pll_ctrl_CLKOUT_DIFF_EN 13
#define bpll_ctrl_CLKOUT_DIFF_EN 1
#define MSK32pll_ctrl_CLKOUT_DIFF_EN 0x00002000
#define BA_pll_ctrl_BYPASS_EN 0x0005
#define B16pll_ctrl_BYPASS_EN 0x0004
#define LSb32pll_ctrl_BYPASS_EN 14
#define LSb16pll_ctrl_BYPASS_EN 14
#define bpll_ctrl_BYPASS_EN 1
#define MSK32pll_ctrl_BYPASS_EN 0x00004000
#define BA_pll_ctrl_CLKOUT_SE_GATING_EN 0x0005
#define B16pll_ctrl_CLKOUT_SE_GATING_EN 0x0004
#define LSb32pll_ctrl_CLKOUT_SE_GATING_EN 15
#define LSb16pll_ctrl_CLKOUT_SE_GATING_EN 15
#define bpll_ctrl_CLKOUT_SE_GATING_EN 1
#define MSK32pll_ctrl_CLKOUT_SE_GATING_EN 0x00008000
#define BA_pll_ctrl_FBCLK_EXT_SEL 0x0006
#define B16pll_ctrl_FBCLK_EXT_SEL 0x0006
#define LSb32pll_ctrl_FBCLK_EXT_SEL 16
#define LSb16pll_ctrl_FBCLK_EXT_SEL 0
#define bpll_ctrl_FBCLK_EXT_SEL 1
#define MSK32pll_ctrl_FBCLK_EXT_SEL 0x00010000
#define BA_pll_ctrl_FBCDLY 0x0006
#define B16pll_ctrl_FBCDLY 0x0006
#define LSb32pll_ctrl_FBCDLY 17
#define LSb16pll_ctrl_FBCDLY 1
#define bpll_ctrl_FBCDLY 6
#define MSK32pll_ctrl_FBCDLY 0x007E0000
#define BA_pll_ctrl_FD 0x0006
#define B16pll_ctrl_FD 0x0006
#define LSb32pll_ctrl_FD 23
#define LSb16pll_ctrl_FD 7
#define bpll_ctrl_FD 3
#define MSK32pll_ctrl_FD 0x03800000
#define BA_pll_ctrl_INTPI 0x0007
#define B16pll_ctrl_INTPI 0x0006
#define LSb32pll_ctrl_INTPI 26
#define LSb16pll_ctrl_INTPI 10
#define bpll_ctrl_INTPI 4
#define MSK32pll_ctrl_INTPI 0x3C000000
#define RA_pll_ctrl2 0x0008
#define BA_pll_ctrl_INTPR 0x0008
#define B16pll_ctrl_INTPR 0x0008
#define LSb32pll_ctrl_INTPR 0
#define LSb16pll_ctrl_INTPR 0
#define bpll_ctrl_INTPR 3
#define MSK32pll_ctrl_INTPR 0x00000007
#define BA_pll_ctrl_PI_EN 0x0008
#define B16pll_ctrl_PI_EN 0x0008
#define LSb32pll_ctrl_PI_EN 3
#define LSb16pll_ctrl_PI_EN 3
#define bpll_ctrl_PI_EN 1
#define MSK32pll_ctrl_PI_EN 0x00000008
#define BA_pll_ctrl_PI_LOOP_MODE 0x0008
#define B16pll_ctrl_PI_LOOP_MODE 0x0008
#define LSb32pll_ctrl_PI_LOOP_MODE 4
#define LSb16pll_ctrl_PI_LOOP_MODE 4
#define bpll_ctrl_PI_LOOP_MODE 1
#define MSK32pll_ctrl_PI_LOOP_MODE 0x00000010
#define BA_pll_ctrl_CLK_DET_EN 0x0008
#define B16pll_ctrl_CLK_DET_EN 0x0008
#define LSb32pll_ctrl_CLK_DET_EN 5
#define LSb16pll_ctrl_CLK_DET_EN 5
#define bpll_ctrl_CLK_DET_EN 1
#define MSK32pll_ctrl_CLK_DET_EN 0x00000020
#define BA_pll_ctrl_RESET_PI 0x0008
#define B16pll_ctrl_RESET_PI 0x0008
#define LSb32pll_ctrl_RESET_PI 6
#define LSb16pll_ctrl_RESET_PI 6
#define bpll_ctrl_RESET_PI 1
#define MSK32pll_ctrl_RESET_PI 0x00000040
#define BA_pll_ctrl_RESET_SSC 0x0008
#define B16pll_ctrl_RESET_SSC 0x0008
#define LSb32pll_ctrl_RESET_SSC 7
#define LSb16pll_ctrl_RESET_SSC 7
#define bpll_ctrl_RESET_SSC 1
#define MSK32pll_ctrl_RESET_SSC 0x00000080
#define BA_pll_ctrl_FREQ_OFFSET_EN 0x0009
#define B16pll_ctrl_FREQ_OFFSET_EN 0x0008
#define LSb32pll_ctrl_FREQ_OFFSET_EN 8
#define LSb16pll_ctrl_FREQ_OFFSET_EN 8
#define bpll_ctrl_FREQ_OFFSET_EN 1
#define MSK32pll_ctrl_FREQ_OFFSET_EN 0x00000100
#define BA_pll_ctrl_FREQ_OFFSET 0x0009
#define B16pll_ctrl_FREQ_OFFSET 0x0008
#define LSb32pll_ctrl_FREQ_OFFSET 9
#define LSb16pll_ctrl_FREQ_OFFSET 9
#define bpll_ctrl_FREQ_OFFSET 17
#define MSK32pll_ctrl_FREQ_OFFSET 0x03FFFE00
#define BA_pll_ctrl_FREQ_OFFSET_MODE_SELECTION 0x000B
#define B16pll_ctrl_FREQ_OFFSET_MODE_SELECTION 0x000A
#define LSb32pll_ctrl_FREQ_OFFSET_MODE_SELECTION 26
#define LSb16pll_ctrl_FREQ_OFFSET_MODE_SELECTION 10
#define bpll_ctrl_FREQ_OFFSET_MODE_SELECTION 1
#define MSK32pll_ctrl_FREQ_OFFSET_MODE_SELECTION 0x04000000
#define BA_pll_ctrl_FREQ_OFFSET_VALID 0x000B
#define B16pll_ctrl_FREQ_OFFSET_VALID 0x000A
#define LSb32pll_ctrl_FREQ_OFFSET_VALID 27
#define LSb16pll_ctrl_FREQ_OFFSET_VALID 11
#define bpll_ctrl_FREQ_OFFSET_VALID 1
#define MSK32pll_ctrl_FREQ_OFFSET_VALID 0x08000000
#define BA_pll_ctrl_SSC_CLK_EN 0x000B
#define B16pll_ctrl_SSC_CLK_EN 0x000A
#define LSb32pll_ctrl_SSC_CLK_EN 28
#define LSb16pll_ctrl_SSC_CLK_EN 12
#define bpll_ctrl_SSC_CLK_EN 1
#define MSK32pll_ctrl_SSC_CLK_EN 0x10000000
#define BA_pll_ctrl_SSC_MODE 0x000B
#define B16pll_ctrl_SSC_MODE 0x000A
#define LSb32pll_ctrl_SSC_MODE 29
#define LSb16pll_ctrl_SSC_MODE 13
#define bpll_ctrl_SSC_MODE 1
#define MSK32pll_ctrl_SSC_MODE 0x20000000
#define RA_pll_ctrl3 0x000C
#define BA_pll_ctrl_SSC_FREQ_DIV 0x000C
#define B16pll_ctrl_SSC_FREQ_DIV 0x000C
#define LSb32pll_ctrl_SSC_FREQ_DIV 0
#define LSb16pll_ctrl_SSC_FREQ_DIV 0
#define bpll_ctrl_SSC_FREQ_DIV 16
#define MSK32pll_ctrl_SSC_FREQ_DIV 0x0000FFFF
#define BA_pll_ctrl_SSC_RNGE 0x000E
#define B16pll_ctrl_SSC_RNGE 0x000E
#define LSb32pll_ctrl_SSC_RNGE 16
#define LSb16pll_ctrl_SSC_RNGE 0
#define bpll_ctrl_SSC_RNGE 11
#define MSK32pll_ctrl_SSC_RNGE 0x07FF0000
#define BA_pll_ctrl_TEST_ANA 0x000F
#define B16pll_ctrl_TEST_ANA 0x000E
#define LSb32pll_ctrl_TEST_ANA 27
#define LSb16pll_ctrl_TEST_ANA 11
#define bpll_ctrl_TEST_ANA 4
#define MSK32pll_ctrl_TEST_ANA 0x78000000
#define RA_pll_ctrl4 0x0010
#define BA_pll_ctrl_RESERVE_IN 0x0010
#define B16pll_ctrl_RESERVE_IN 0x0010
#define LSb32pll_ctrl_RESERVE_IN 0
#define LSb16pll_ctrl_RESERVE_IN 0
#define bpll_ctrl_RESERVE_IN 8
#define MSK32pll_ctrl_RESERVE_IN 0x000000FF
///////////////////////////////////////////////////////////
#define RA_pll_status 0x0014
#define BA_pll_status_PLL_LOCK 0x0014
#define B16pll_status_PLL_LOCK 0x0014
#define LSb32pll_status_PLL_LOCK 0
#define LSb16pll_status_PLL_LOCK 0
#define bpll_status_PLL_LOCK 1
#define MSK32pll_status_PLL_LOCK 0x00000001
#define BA_pll_status_CLK_CFMOD 0x0014
#define B16pll_status_CLK_CFMOD 0x0014
#define LSb32pll_status_CLK_CFMOD 1
#define LSb16pll_status_CLK_CFMOD 1
#define bpll_status_CLK_CFMOD 1
#define MSK32pll_status_CLK_CFMOD 0x00000002
#define BA_pll_status_CLK_FMOD 0x0014
#define B16pll_status_CLK_FMOD 0x0014
#define LSb32pll_status_CLK_FMOD 2
#define LSb16pll_status_CLK_FMOD 2
#define bpll_status_CLK_FMOD 1
#define MSK32pll_status_CLK_FMOD 0x00000004
#define BA_pll_status_RESERVE_OUT 0x0014
#define B16pll_status_RESERVE_OUT 0x0014
#define LSb32pll_status_RESERVE_OUT 3
#define LSb16pll_status_RESERVE_OUT 3
#define bpll_status_RESERVE_OUT 8
#define MSK32pll_status_RESERVE_OUT 0x000007F8
///////////////////////////////////////////////////////////
typedef struct SIE_pll {
///////////////////////////////////////////////////////////
#define GET32pll_ctrl_PU(r32) _BFGET_(r32, 0, 0)
#define SET32pll_ctrl_PU(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16pll_ctrl_PU(r16) _BFGET_(r16, 0, 0)
#define SET16pll_ctrl_PU(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32pll_ctrl_RESET(r32) _BFGET_(r32, 1, 1)
#define SET32pll_ctrl_RESET(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16pll_ctrl_RESET(r16) _BFGET_(r16, 1, 1)
#define SET16pll_ctrl_RESET(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32pll_ctrl_AVDD1815_SEL(r32) _BFGET_(r32, 2, 2)
#define SET32pll_ctrl_AVDD1815_SEL(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16pll_ctrl_AVDD1815_SEL(r16) _BFGET_(r16, 2, 2)
#define SET16pll_ctrl_AVDD1815_SEL(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32pll_ctrl_REFDIV(r32) _BFGET_(r32,11, 3)
#define SET32pll_ctrl_REFDIV(r32,v) _BFSET_(r32,11, 3,v)
#define GET16pll_ctrl_REFDIV(r16) _BFGET_(r16,11, 3)
#define SET16pll_ctrl_REFDIV(r16,v) _BFSET_(r16,11, 3,v)
#define GET32pll_ctrl_FBDIV(r32) _BFGET_(r32,20,12)
#define SET32pll_ctrl_FBDIV(r32,v) _BFSET_(r32,20,12,v)
#define GET32pll_ctrl_VDDM(r32) _BFGET_(r32,22,21)
#define SET32pll_ctrl_VDDM(r32,v) _BFSET_(r32,22,21,v)
#define GET16pll_ctrl_VDDM(r16) _BFGET_(r16, 6, 5)
#define SET16pll_ctrl_VDDM(r16,v) _BFSET_(r16, 6, 5,v)
#define GET32pll_ctrl_VDDL(r32) _BFGET_(r32,25,23)
#define SET32pll_ctrl_VDDL(r32,v) _BFSET_(r32,25,23,v)
#define GET16pll_ctrl_VDDL(r16) _BFGET_(r16, 9, 7)
#define SET16pll_ctrl_VDDL(r16,v) _BFSET_(r16, 9, 7,v)
#define GET32pll_ctrl_ICP(r32) _BFGET_(r32,29,26)
#define SET32pll_ctrl_ICP(r32,v) _BFSET_(r32,29,26,v)
#define GET16pll_ctrl_ICP(r16) _BFGET_(r16,13,10)
#define SET16pll_ctrl_ICP(r16,v) _BFSET_(r16,13,10,v)
#define GET32pll_ctrl_PLL_BW_SEL(r32) _BFGET_(r32,30,30)
#define SET32pll_ctrl_PLL_BW_SEL(r32,v) _BFSET_(r32,30,30,v)
#define GET16pll_ctrl_PLL_BW_SEL(r16) _BFGET_(r16,14,14)
#define SET16pll_ctrl_PLL_BW_SEL(r16,v) _BFSET_(r16,14,14,v)
#define w32pll_ctrl {\
UNSG32 uctrl_PU : 1;\
UNSG32 uctrl_RESET : 1;\
UNSG32 uctrl_AVDD1815_SEL : 1;\
UNSG32 uctrl_REFDIV : 9;\
UNSG32 uctrl_FBDIV : 9;\
UNSG32 uctrl_VDDM : 2;\
UNSG32 uctrl_VDDL : 3;\
UNSG32 uctrl_ICP : 4;\
UNSG32 uctrl_PLL_BW_SEL : 1;\
UNSG32 RSVDx0_b31 : 1;\
}
union { UNSG32 u32pll_ctrl;
struct w32pll_ctrl;
};
#define GET32pll_ctrl_KVCO(r32) _BFGET_(r32, 3, 0)
#define SET32pll_ctrl_KVCO(r32,v) _BFSET_(r32, 3, 0,v)
#define GET16pll_ctrl_KVCO(r16) _BFGET_(r16, 3, 0)
#define SET16pll_ctrl_KVCO(r16,v) _BFSET_(r16, 3, 0,v)
#define GET32pll_ctrl_CTUNE(r32) _BFGET_(r32, 5, 4)
#define SET32pll_ctrl_CTUNE(r32,v) _BFSET_(r32, 5, 4,v)
#define GET16pll_ctrl_CTUNE(r16) _BFGET_(r16, 5, 4)
#define SET16pll_ctrl_CTUNE(r16,v) _BFSET_(r16, 5, 4,v)
#define GET32pll_ctrl_CLKOUT_DIFF_DIV_SEL(r32) _BFGET_(r32, 8, 6)
#define SET32pll_ctrl_CLKOUT_DIFF_DIV_SEL(r32,v) _BFSET_(r32, 8, 6,v)
#define GET16pll_ctrl_CLKOUT_DIFF_DIV_SEL(r16) _BFGET_(r16, 8, 6)
#define SET16pll_ctrl_CLKOUT_DIFF_DIV_SEL(r16,v) _BFSET_(r16, 8, 6,v)
#define GET32pll_ctrl_CLKOUT_SE_DIV_SEL(r32) _BFGET_(r32,11, 9)
#define SET32pll_ctrl_CLKOUT_SE_DIV_SEL(r32,v) _BFSET_(r32,11, 9,v)
#define GET16pll_ctrl_CLKOUT_SE_DIV_SEL(r16) _BFGET_(r16,11, 9)
#define SET16pll_ctrl_CLKOUT_SE_DIV_SEL(r16,v) _BFSET_(r16,11, 9,v)
#define GET32pll_ctrl_CLKOUT_SOURCE_SEL(r32) _BFGET_(r32,12,12)
#define SET32pll_ctrl_CLKOUT_SOURCE_SEL(r32,v) _BFSET_(r32,12,12,v)
#define GET16pll_ctrl_CLKOUT_SOURCE_SEL(r16) _BFGET_(r16,12,12)
#define SET16pll_ctrl_CLKOUT_SOURCE_SEL(r16,v) _BFSET_(r16,12,12,v)
#define GET32pll_ctrl_CLKOUT_DIFF_EN(r32) _BFGET_(r32,13,13)
#define SET32pll_ctrl_CLKOUT_DIFF_EN(r32,v) _BFSET_(r32,13,13,v)
#define GET16pll_ctrl_CLKOUT_DIFF_EN(r16) _BFGET_(r16,13,13)
#define SET16pll_ctrl_CLKOUT_DIFF_EN(r16,v) _BFSET_(r16,13,13,v)
#define GET32pll_ctrl_BYPASS_EN(r32) _BFGET_(r32,14,14)
#define SET32pll_ctrl_BYPASS_EN(r32,v) _BFSET_(r32,14,14,v)
#define GET16pll_ctrl_BYPASS_EN(r16) _BFGET_(r16,14,14)
#define SET16pll_ctrl_BYPASS_EN(r16,v) _BFSET_(r16,14,14,v)
#define GET32pll_ctrl_CLKOUT_SE_GATING_EN(r32) _BFGET_(r32,15,15)
#define SET32pll_ctrl_CLKOUT_SE_GATING_EN(r32,v) _BFSET_(r32,15,15,v)
#define GET16pll_ctrl_CLKOUT_SE_GATING_EN(r16) _BFGET_(r16,15,15)
#define SET16pll_ctrl_CLKOUT_SE_GATING_EN(r16,v) _BFSET_(r16,15,15,v)
#define GET32pll_ctrl_FBCLK_EXT_SEL(r32) _BFGET_(r32,16,16)
#define SET32pll_ctrl_FBCLK_EXT_SEL(r32,v) _BFSET_(r32,16,16,v)
#define GET16pll_ctrl_FBCLK_EXT_SEL(r16) _BFGET_(r16, 0, 0)
#define SET16pll_ctrl_FBCLK_EXT_SEL(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32pll_ctrl_FBCDLY(r32) _BFGET_(r32,22,17)
#define SET32pll_ctrl_FBCDLY(r32,v) _BFSET_(r32,22,17,v)
#define GET16pll_ctrl_FBCDLY(r16) _BFGET_(r16, 6, 1)
#define SET16pll_ctrl_FBCDLY(r16,v) _BFSET_(r16, 6, 1,v)
#define GET32pll_ctrl_FD(r32) _BFGET_(r32,25,23)
#define SET32pll_ctrl_FD(r32,v) _BFSET_(r32,25,23,v)
#define GET16pll_ctrl_FD(r16) _BFGET_(r16, 9, 7)
#define SET16pll_ctrl_FD(r16,v) _BFSET_(r16, 9, 7,v)
#define GET32pll_ctrl_INTPI(r32) _BFGET_(r32,29,26)
#define SET32pll_ctrl_INTPI(r32,v) _BFSET_(r32,29,26,v)
#define GET16pll_ctrl_INTPI(r16) _BFGET_(r16,13,10)
#define SET16pll_ctrl_INTPI(r16,v) _BFSET_(r16,13,10,v)
#define w32pll_ctrl1 {\
UNSG32 uctrl_KVCO : 4;\
UNSG32 uctrl_CTUNE : 2;\
UNSG32 uctrl_CLKOUT_DIFF_DIV_SEL : 3;\
UNSG32 uctrl_CLKOUT_SE_DIV_SEL : 3;\
UNSG32 uctrl_CLKOUT_SOURCE_SEL : 1;\
UNSG32 uctrl_CLKOUT_DIFF_EN : 1;\
UNSG32 uctrl_BYPASS_EN : 1;\
UNSG32 uctrl_CLKOUT_SE_GATING_EN : 1;\
UNSG32 uctrl_FBCLK_EXT_SEL : 1;\
UNSG32 uctrl_FBCDLY : 6;\
UNSG32 uctrl_FD : 3;\
UNSG32 uctrl_INTPI : 4;\
UNSG32 RSVDx4_b30 : 2;\
}
union { UNSG32 u32pll_ctrl1;
struct w32pll_ctrl1;
};
#define GET32pll_ctrl_INTPR(r32) _BFGET_(r32, 2, 0)
#define SET32pll_ctrl_INTPR(r32,v) _BFSET_(r32, 2, 0,v)
#define GET16pll_ctrl_INTPR(r16) _BFGET_(r16, 2, 0)
#define SET16pll_ctrl_INTPR(r16,v) _BFSET_(r16, 2, 0,v)
#define GET32pll_ctrl_PI_EN(r32) _BFGET_(r32, 3, 3)
#define SET32pll_ctrl_PI_EN(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16pll_ctrl_PI_EN(r16) _BFGET_(r16, 3, 3)
#define SET16pll_ctrl_PI_EN(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32pll_ctrl_PI_LOOP_MODE(r32) _BFGET_(r32, 4, 4)
#define SET32pll_ctrl_PI_LOOP_MODE(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16pll_ctrl_PI_LOOP_MODE(r16) _BFGET_(r16, 4, 4)
#define SET16pll_ctrl_PI_LOOP_MODE(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32pll_ctrl_CLK_DET_EN(r32) _BFGET_(r32, 5, 5)
#define SET32pll_ctrl_CLK_DET_EN(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16pll_ctrl_CLK_DET_EN(r16) _BFGET_(r16, 5, 5)
#define SET16pll_ctrl_CLK_DET_EN(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32pll_ctrl_RESET_PI(r32) _BFGET_(r32, 6, 6)
#define SET32pll_ctrl_RESET_PI(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16pll_ctrl_RESET_PI(r16) _BFGET_(r16, 6, 6)
#define SET16pll_ctrl_RESET_PI(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32pll_ctrl_RESET_SSC(r32) _BFGET_(r32, 7, 7)
#define SET32pll_ctrl_RESET_SSC(r32,v) _BFSET_(r32, 7, 7,v)
#define GET16pll_ctrl_RESET_SSC(r16) _BFGET_(r16, 7, 7)
#define SET16pll_ctrl_RESET_SSC(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32pll_ctrl_FREQ_OFFSET_EN(r32) _BFGET_(r32, 8, 8)
#define SET32pll_ctrl_FREQ_OFFSET_EN(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16pll_ctrl_FREQ_OFFSET_EN(r16) _BFGET_(r16, 8, 8)
#define SET16pll_ctrl_FREQ_OFFSET_EN(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32pll_ctrl_FREQ_OFFSET(r32) _BFGET_(r32,25, 9)
#define SET32pll_ctrl_FREQ_OFFSET(r32,v) _BFSET_(r32,25, 9,v)
#define GET32pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r32) _BFGET_(r32,26,26)
#define SET32pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r32,v) _BFSET_(r32,26,26,v)
#define GET16pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r16) _BFGET_(r16,10,10)
#define SET16pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r16,v) _BFSET_(r16,10,10,v)
#define GET32pll_ctrl_FREQ_OFFSET_VALID(r32) _BFGET_(r32,27,27)
#define SET32pll_ctrl_FREQ_OFFSET_VALID(r32,v) _BFSET_(r32,27,27,v)
#define GET16pll_ctrl_FREQ_OFFSET_VALID(r16) _BFGET_(r16,11,11)
#define SET16pll_ctrl_FREQ_OFFSET_VALID(r16,v) _BFSET_(r16,11,11,v)
#define GET32pll_ctrl_SSC_CLK_EN(r32) _BFGET_(r32,28,28)
#define SET32pll_ctrl_SSC_CLK_EN(r32,v) _BFSET_(r32,28,28,v)
#define GET16pll_ctrl_SSC_CLK_EN(r16) _BFGET_(r16,12,12)
#define SET16pll_ctrl_SSC_CLK_EN(r16,v) _BFSET_(r16,12,12,v)
#define GET32pll_ctrl_SSC_MODE(r32) _BFGET_(r32,29,29)
#define SET32pll_ctrl_SSC_MODE(r32,v) _BFSET_(r32,29,29,v)
#define GET16pll_ctrl_SSC_MODE(r16) _BFGET_(r16,13,13)
#define SET16pll_ctrl_SSC_MODE(r16,v) _BFSET_(r16,13,13,v)
#define w32pll_ctrl2 {\
UNSG32 uctrl_INTPR : 3;\
UNSG32 uctrl_PI_EN : 1;\
UNSG32 uctrl_PI_LOOP_MODE : 1;\
UNSG32 uctrl_CLK_DET_EN : 1;\
UNSG32 uctrl_RESET_PI : 1;\
UNSG32 uctrl_RESET_SSC : 1;\
UNSG32 uctrl_FREQ_OFFSET_EN : 1;\
UNSG32 uctrl_FREQ_OFFSET : 17;\
UNSG32 uctrl_FREQ_OFFSET_MODE_SELECTION : 1;\
UNSG32 uctrl_FREQ_OFFSET_VALID : 1;\
UNSG32 uctrl_SSC_CLK_EN : 1;\
UNSG32 uctrl_SSC_MODE : 1;\
UNSG32 RSVDx8_b30 : 2;\
}
union { UNSG32 u32pll_ctrl2;
struct w32pll_ctrl2;
};
#define GET32pll_ctrl_SSC_FREQ_DIV(r32) _BFGET_(r32,15, 0)
#define SET32pll_ctrl_SSC_FREQ_DIV(r32,v) _BFSET_(r32,15, 0,v)
#define GET16pll_ctrl_SSC_FREQ_DIV(r16) _BFGET_(r16,15, 0)
#define SET16pll_ctrl_SSC_FREQ_DIV(r16,v) _BFSET_(r16,15, 0,v)
#define GET32pll_ctrl_SSC_RNGE(r32) _BFGET_(r32,26,16)
#define SET32pll_ctrl_SSC_RNGE(r32,v) _BFSET_(r32,26,16,v)
#define GET16pll_ctrl_SSC_RNGE(r16) _BFGET_(r16,10, 0)
#define SET16pll_ctrl_SSC_RNGE(r16,v) _BFSET_(r16,10, 0,v)
#define GET32pll_ctrl_TEST_ANA(r32) _BFGET_(r32,30,27)
#define SET32pll_ctrl_TEST_ANA(r32,v) _BFSET_(r32,30,27,v)
#define GET16pll_ctrl_TEST_ANA(r16) _BFGET_(r16,14,11)
#define SET16pll_ctrl_TEST_ANA(r16,v) _BFSET_(r16,14,11,v)
#define w32pll_ctrl3 {\
UNSG32 uctrl_SSC_FREQ_DIV : 16;\
UNSG32 uctrl_SSC_RNGE : 11;\
UNSG32 uctrl_TEST_ANA : 4;\
UNSG32 RSVDxC_b31 : 1;\
}
union { UNSG32 u32pll_ctrl3;
struct w32pll_ctrl3;
};
#define GET32pll_ctrl_RESERVE_IN(r32) _BFGET_(r32, 7, 0)
#define SET32pll_ctrl_RESERVE_IN(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16pll_ctrl_RESERVE_IN(r16) _BFGET_(r16, 7, 0)
#define SET16pll_ctrl_RESERVE_IN(r16,v) _BFSET_(r16, 7, 0,v)
#define w32pll_ctrl4 {\
UNSG32 uctrl_RESERVE_IN : 8;\
UNSG32 RSVDx10_b8 : 24;\
}
union { UNSG32 u32pll_ctrl4;
struct w32pll_ctrl4;
};
///////////////////////////////////////////////////////////
#define GET32pll_status_PLL_LOCK(r32) _BFGET_(r32, 0, 0)
#define SET32pll_status_PLL_LOCK(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16pll_status_PLL_LOCK(r16) _BFGET_(r16, 0, 0)
#define SET16pll_status_PLL_LOCK(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32pll_status_CLK_CFMOD(r32) _BFGET_(r32, 1, 1)
#define SET32pll_status_CLK_CFMOD(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16pll_status_CLK_CFMOD(r16) _BFGET_(r16, 1, 1)
#define SET16pll_status_CLK_CFMOD(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32pll_status_CLK_FMOD(r32) _BFGET_(r32, 2, 2)
#define SET32pll_status_CLK_FMOD(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16pll_status_CLK_FMOD(r16) _BFGET_(r16, 2, 2)
#define SET16pll_status_CLK_FMOD(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32pll_status_RESERVE_OUT(r32) _BFGET_(r32,10, 3)
#define SET32pll_status_RESERVE_OUT(r32,v) _BFSET_(r32,10, 3,v)
#define GET16pll_status_RESERVE_OUT(r16) _BFGET_(r16,10, 3)
#define SET16pll_status_RESERVE_OUT(r16,v) _BFSET_(r16,10, 3,v)
#define w32pll_status {\
UNSG32 ustatus_PLL_LOCK : 1;\
UNSG32 ustatus_CLK_CFMOD : 1;\
UNSG32 ustatus_CLK_FMOD : 1;\
UNSG32 ustatus_RESERVE_OUT : 8;\
UNSG32 RSVDx14_b11 : 21;\
}
union { UNSG32 u32pll_status;
struct w32pll_status;
};
///////////////////////////////////////////////////////////
} SIE_pll;
typedef union T32pll_ctrl
{ UNSG32 u32;
struct w32pll_ctrl;
} T32pll_ctrl;
typedef union T32pll_ctrl1
{ UNSG32 u32;
struct w32pll_ctrl1;
} T32pll_ctrl1;
typedef union T32pll_ctrl2
{ UNSG32 u32;
struct w32pll_ctrl2;
} T32pll_ctrl2;
typedef union T32pll_ctrl3
{ UNSG32 u32;
struct w32pll_ctrl3;
} T32pll_ctrl3;
typedef union T32pll_ctrl4
{ UNSG32 u32;
struct w32pll_ctrl4;
} T32pll_ctrl4;
typedef union T32pll_status
{ UNSG32 u32;
struct w32pll_status;
} T32pll_status;
///////////////////////////////////////////////////////////
typedef union Tpll_ctrl
{ UNSG32 u32[5];
struct {
struct w32pll_ctrl;
struct w32pll_ctrl1;
struct w32pll_ctrl2;
struct w32pll_ctrl3;
struct w32pll_ctrl4;
};
} Tpll_ctrl;
typedef union Tpll_status
{ UNSG32 u32[1];
struct {
struct w32pll_status;
};
} Tpll_status;
///////////////////////////////////////////////////////////
SIGN32 pll_drvrd(SIE_pll *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 pll_drvwr(SIE_pll *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void pll_reset(SIE_pll *p);
SIGN32 pll_cmp (SIE_pll *p, SIE_pll *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define pll_check(p,pie,pfx,hLOG) pll_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define pll_print(p, pfx,hLOG) pll_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: pll
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE pwrOff (4,4)
/// ###
/// * Register for the Power domain which is OFF by default
/// ###
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (RW-)
/// ###
/// * Power Domain Control Register
/// ###
/// %unsigned 1 iso_eN 0x0
/// : enable 0x0
/// : disable 0x1
/// ###
/// * Isolation control bit. Active low
/// * 0 : Isolation is enabled
/// * 1 : Isolation is disabled (default)
/// ###
/// %unsigned 2 pwrSwitchCtrl 0x0
/// : PWROFF 0x0
/// : PWRON 0x3
/// ###
/// * Power Switch control
/// * Bit 1 : SLP1B
/// * Bit 0 : SLP2B
/// * SLP1B SLP2B
/// * 0 X Switch is turned off
/// * 1 0 PMOS switch in current mirror configuration. Constant current charging to limit in-rush current
/// * 1 1 PMOS switch is fully turned on to reduce Ron
/// ###
/// %unsigned 1 pwrDomainRstN 0x0
/// : enable 0x0
/// : disable 0x1
/// ###
/// * Power Domain Reset. Active low.
/// * 0 : Reset the power domain
/// * 1: De-assert the reset for the power domain
/// ###
/// %% 28 # Stuffing bits...
/// @ 0x00004 status (R-)
/// %unsigned 2 pwrStatus
/// ###
/// * Power domain Status output from the power domain module
/// * Bit 1 : SLP1B
/// * Bit 0 : SLP2B
/// * SLP1B SLP2B
/// * 0 X Switch is turned off
/// * 1 0 PMOS switch in current mirror configuration. Constant current charging to limit in-rush current
/// * 1 1 PMOS switch is fully turned on to reduce Ron
/// ###
/// %% 30 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 8B, bits: 6b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_pwrOff
#define h_pwrOff (){}
#define RA_pwrOff_ctrl 0x0000
#define BA_pwrOff_ctrl_iso_eN 0x0000
#define B16pwrOff_ctrl_iso_eN 0x0000
#define LSb32pwrOff_ctrl_iso_eN 0
#define LSb16pwrOff_ctrl_iso_eN 0
#define bpwrOff_ctrl_iso_eN 1
#define MSK32pwrOff_ctrl_iso_eN 0x00000001
#define pwrOff_ctrl_iso_eN_enable 0x0
#define pwrOff_ctrl_iso_eN_disable 0x1
#define BA_pwrOff_ctrl_pwrSwitchCtrl 0x0000
#define B16pwrOff_ctrl_pwrSwitchCtrl 0x0000
#define LSb32pwrOff_ctrl_pwrSwitchCtrl 1
#define LSb16pwrOff_ctrl_pwrSwitchCtrl 1
#define bpwrOff_ctrl_pwrSwitchCtrl 2
#define MSK32pwrOff_ctrl_pwrSwitchCtrl 0x00000006
#define pwrOff_ctrl_pwrSwitchCtrl_PWROFF 0x0
#define pwrOff_ctrl_pwrSwitchCtrl_PWRON 0x3
#define BA_pwrOff_ctrl_pwrDomainRstN 0x0000
#define B16pwrOff_ctrl_pwrDomainRstN 0x0000
#define LSb32pwrOff_ctrl_pwrDomainRstN 3
#define LSb16pwrOff_ctrl_pwrDomainRstN 3
#define bpwrOff_ctrl_pwrDomainRstN 1
#define MSK32pwrOff_ctrl_pwrDomainRstN 0x00000008
#define pwrOff_ctrl_pwrDomainRstN_enable 0x0
#define pwrOff_ctrl_pwrDomainRstN_disable 0x1
///////////////////////////////////////////////////////////
#define RA_pwrOff_status 0x0004
#define BA_pwrOff_status_pwrStatus 0x0004
#define B16pwrOff_status_pwrStatus 0x0004
#define LSb32pwrOff_status_pwrStatus 0
#define LSb16pwrOff_status_pwrStatus 0
#define bpwrOff_status_pwrStatus 2
#define MSK32pwrOff_status_pwrStatus 0x00000003
///////////////////////////////////////////////////////////
typedef struct SIE_pwrOff {
///////////////////////////////////////////////////////////
#define GET32pwrOff_ctrl_iso_eN(r32) _BFGET_(r32, 0, 0)
#define SET32pwrOff_ctrl_iso_eN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16pwrOff_ctrl_iso_eN(r16) _BFGET_(r16, 0, 0)
#define SET16pwrOff_ctrl_iso_eN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32pwrOff_ctrl_pwrSwitchCtrl(r32) _BFGET_(r32, 2, 1)
#define SET32pwrOff_ctrl_pwrSwitchCtrl(r32,v) _BFSET_(r32, 2, 1,v)
#define GET16pwrOff_ctrl_pwrSwitchCtrl(r16) _BFGET_(r16, 2, 1)
#define SET16pwrOff_ctrl_pwrSwitchCtrl(r16,v) _BFSET_(r16, 2, 1,v)
#define GET32pwrOff_ctrl_pwrDomainRstN(r32) _BFGET_(r32, 3, 3)
#define SET32pwrOff_ctrl_pwrDomainRstN(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16pwrOff_ctrl_pwrDomainRstN(r16) _BFGET_(r16, 3, 3)
#define SET16pwrOff_ctrl_pwrDomainRstN(r16,v) _BFSET_(r16, 3, 3,v)
#define w32pwrOff_ctrl {\
UNSG32 uctrl_iso_eN : 1;\
UNSG32 uctrl_pwrSwitchCtrl : 2;\
UNSG32 uctrl_pwrDomainRstN : 1;\
UNSG32 RSVDx0_b4 : 28;\
}
union { UNSG32 u32pwrOff_ctrl;
struct w32pwrOff_ctrl;
};
///////////////////////////////////////////////////////////
#define GET32pwrOff_status_pwrStatus(r32) _BFGET_(r32, 1, 0)
#define SET32pwrOff_status_pwrStatus(r32,v) _BFSET_(r32, 1, 0,v)
#define GET16pwrOff_status_pwrStatus(r16) _BFGET_(r16, 1, 0)
#define SET16pwrOff_status_pwrStatus(r16,v) _BFSET_(r16, 1, 0,v)
#define w32pwrOff_status {\
UNSG32 ustatus_pwrStatus : 2;\
UNSG32 RSVDx4_b2 : 30;\
}
union { UNSG32 u32pwrOff_status;
struct w32pwrOff_status;
};
///////////////////////////////////////////////////////////
} SIE_pwrOff;
typedef union T32pwrOff_ctrl
{ UNSG32 u32;
struct w32pwrOff_ctrl;
} T32pwrOff_ctrl;
typedef union T32pwrOff_status
{ UNSG32 u32;
struct w32pwrOff_status;
} T32pwrOff_status;
///////////////////////////////////////////////////////////
typedef union TpwrOff_ctrl
{ UNSG32 u32[1];
struct {
struct w32pwrOff_ctrl;
};
} TpwrOff_ctrl;
typedef union TpwrOff_status
{ UNSG32 u32[1];
struct {
struct w32pwrOff_status;
};
} TpwrOff_status;
///////////////////////////////////////////////////////////
SIGN32 pwrOff_drvrd(SIE_pwrOff *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 pwrOff_drvwr(SIE_pwrOff *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void pwrOff_reset(SIE_pwrOff *p);
SIGN32 pwrOff_cmp (SIE_pwrOff *p, SIE_pwrOff *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define pwrOff_check(p,pie,pfx,hLOG) pwrOff_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define pwrOff_print(p, pfx,hLOG) pwrOff_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: pwrOff
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE pwrOn (4,4)
/// ###
/// * Register for the Power domain which is ON by default
/// ###
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (RW-)
/// ###
/// * Power Domain Control Register
/// ###
/// %unsigned 1 iso_eN 0x1
/// : enable 0x0
/// : disable 0x1
/// ###
/// * Isolation control bit. Active low
/// * 0 : Isolation is enabled
/// * 1 : Isolation is disabled (default)
/// ###
/// %unsigned 2 pwrSwitchCtrl 0x3
/// ###
/// * Power Switch control
/// * Bit 1 : SLP1B
/// * Bit 0 : SLP2B
/// * SLP1B SLP2B
/// * 0 X Switch is turned off
/// * 1 0 PMOS switch in current mirror configuration. Constant current charging to limit in-rush current
/// * 1 1 PMOS switch is fully turned on to reduce Ron
/// ###
/// %unsigned 1 pwrDomainRstN 0x1
/// ###
/// * Power Domain Reset. Active low.
/// * 0 : Reset the power domain
/// * 1: De-assert the reset for the power domain
/// ###
/// %% 28 # Stuffing bits...
/// @ 0x00004 status (R-)
/// %unsigned 2 pwrStatus
/// ###
/// * Power domain Status output from the power domain module
/// * Bit 1 : SLP1B
/// * Bit 0 : SLP2B
/// * SLP1B SLP2B
/// * 0 X Switch is turned off
/// * 1 0 PMOS switch in current mirror configuration. Constant current charging to limit in-rush current
/// * 1 1 PMOS switch is fully turned on to reduce Ron
/// ###
/// %% 30 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 8B, bits: 6b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_pwrOn
#define h_pwrOn (){}
#define RA_pwrOn_ctrl 0x0000
#define BA_pwrOn_ctrl_iso_eN 0x0000
#define B16pwrOn_ctrl_iso_eN 0x0000
#define LSb32pwrOn_ctrl_iso_eN 0
#define LSb16pwrOn_ctrl_iso_eN 0
#define bpwrOn_ctrl_iso_eN 1
#define MSK32pwrOn_ctrl_iso_eN 0x00000001
#define pwrOn_ctrl_iso_eN_enable 0x0
#define pwrOn_ctrl_iso_eN_disable 0x1
#define BA_pwrOn_ctrl_pwrSwitchCtrl 0x0000
#define B16pwrOn_ctrl_pwrSwitchCtrl 0x0000
#define LSb32pwrOn_ctrl_pwrSwitchCtrl 1
#define LSb16pwrOn_ctrl_pwrSwitchCtrl 1
#define bpwrOn_ctrl_pwrSwitchCtrl 2
#define MSK32pwrOn_ctrl_pwrSwitchCtrl 0x00000006
#define BA_pwrOn_ctrl_pwrDomainRstN 0x0000
#define B16pwrOn_ctrl_pwrDomainRstN 0x0000
#define LSb32pwrOn_ctrl_pwrDomainRstN 3
#define LSb16pwrOn_ctrl_pwrDomainRstN 3
#define bpwrOn_ctrl_pwrDomainRstN 1
#define MSK32pwrOn_ctrl_pwrDomainRstN 0x00000008
///////////////////////////////////////////////////////////
#define RA_pwrOn_status 0x0004
#define BA_pwrOn_status_pwrStatus 0x0004
#define B16pwrOn_status_pwrStatus 0x0004
#define LSb32pwrOn_status_pwrStatus 0
#define LSb16pwrOn_status_pwrStatus 0
#define bpwrOn_status_pwrStatus 2
#define MSK32pwrOn_status_pwrStatus 0x00000003
///////////////////////////////////////////////////////////
typedef struct SIE_pwrOn {
///////////////////////////////////////////////////////////
#define GET32pwrOn_ctrl_iso_eN(r32) _BFGET_(r32, 0, 0)
#define SET32pwrOn_ctrl_iso_eN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16pwrOn_ctrl_iso_eN(r16) _BFGET_(r16, 0, 0)
#define SET16pwrOn_ctrl_iso_eN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32pwrOn_ctrl_pwrSwitchCtrl(r32) _BFGET_(r32, 2, 1)
#define SET32pwrOn_ctrl_pwrSwitchCtrl(r32,v) _BFSET_(r32, 2, 1,v)
#define GET16pwrOn_ctrl_pwrSwitchCtrl(r16) _BFGET_(r16, 2, 1)
#define SET16pwrOn_ctrl_pwrSwitchCtrl(r16,v) _BFSET_(r16, 2, 1,v)
#define GET32pwrOn_ctrl_pwrDomainRstN(r32) _BFGET_(r32, 3, 3)
#define SET32pwrOn_ctrl_pwrDomainRstN(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16pwrOn_ctrl_pwrDomainRstN(r16) _BFGET_(r16, 3, 3)
#define SET16pwrOn_ctrl_pwrDomainRstN(r16,v) _BFSET_(r16, 3, 3,v)
#define w32pwrOn_ctrl {\
UNSG32 uctrl_iso_eN : 1;\
UNSG32 uctrl_pwrSwitchCtrl : 2;\
UNSG32 uctrl_pwrDomainRstN : 1;\
UNSG32 RSVDx0_b4 : 28;\
}
union { UNSG32 u32pwrOn_ctrl;
struct w32pwrOn_ctrl;
};
///////////////////////////////////////////////////////////
#define GET32pwrOn_status_pwrStatus(r32) _BFGET_(r32, 1, 0)
#define SET32pwrOn_status_pwrStatus(r32,v) _BFSET_(r32, 1, 0,v)
#define GET16pwrOn_status_pwrStatus(r16) _BFGET_(r16, 1, 0)
#define SET16pwrOn_status_pwrStatus(r16,v) _BFSET_(r16, 1, 0,v)
#define w32pwrOn_status {\
UNSG32 ustatus_pwrStatus : 2;\
UNSG32 RSVDx4_b2 : 30;\
}
union { UNSG32 u32pwrOn_status;
struct w32pwrOn_status;
};
///////////////////////////////////////////////////////////
} SIE_pwrOn;
typedef union T32pwrOn_ctrl
{ UNSG32 u32;
struct w32pwrOn_ctrl;
} T32pwrOn_ctrl;
typedef union T32pwrOn_status
{ UNSG32 u32;
struct w32pwrOn_status;
} T32pwrOn_status;
///////////////////////////////////////////////////////////
typedef union TpwrOn_ctrl
{ UNSG32 u32[1];
struct {
struct w32pwrOn_ctrl;
};
} TpwrOn_ctrl;
typedef union TpwrOn_status
{ UNSG32 u32[1];
struct {
struct w32pwrOn_status;
};
} TpwrOn_status;
///////////////////////////////////////////////////////////
SIGN32 pwrOn_drvrd(SIE_pwrOn *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 pwrOn_drvwr(SIE_pwrOn *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void pwrOn_reset(SIE_pwrOn *p);
SIGN32 pwrOn_cmp (SIE_pwrOn *p, SIE_pwrOn *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define pwrOn_check(p,pie,pfx,hLOG) pwrOn_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define pwrOn_print(p, pfx,hLOG) pwrOn_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: pwrOn
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE clkgen (4,4)
/// ###
/// * Controls for clkgen_vddtrk
/// ###
/// # # ----------------------------------------------------------
/// @ 0x00000 CTRL (P)
/// %unsigned 1 PU 0x1
/// ###
/// * Power up signal
/// * 0: Power down
/// * 1: Power Up
/// ###
/// %unsigned 1 RST 0x0
/// ###
/// * Active when RST = 1.
/// * When RST=1, CLKGEN_VDDTRACK outputs lowerst frequency
/// ###
/// %unsigned 1 BAND_EN 0x1
/// %unsigned 1 BCTRL 0x0
/// ###
/// * Bias_Control
/// * 0: Frequency change due to DVDD change is instantaneous
/// * 1: Frequency change due to DVDD change is band limited at 50MHz
/// ###
/// %unsigned 3 CADDR 0x1
/// ###
/// * This clock generator is composed of 7 stages. CADDR[2:0] select which stage to select. It works together with CCTRL (Coarse_Ctrl)
/// * 001: 1st stage
/// * 010: 2nd stage
/// * 011: 3rd stage
/// * 100: 4th stage
/// * 101: 5th stage
/// * 110: 6th stage
/// * 111: 7th stage
/// ###
/// %unsigned 1 CCLK 0x0
/// ###
/// * Control clock to latch in CCLK and CCTRL
/// ###
/// %unsigned 3 CCTRL 0x0
/// ###
/// * Course target frequency
/// * 000 : Maximum frequency
/// * ...
/// * 111 : Minimum frequency
/// ###
/// %unsigned 1 FCLK 0x0
/// ###
/// * Control clock to latch in FCTRL
/// ###
/// %unsigned 6 FCTRL 0x0
/// ###
/// * Fine tune frequency control
/// * 0x00: Fastest frequency
/// * ...
/// * 0x3F: Slowest frequency
/// ###
/// %unsigned 1 FSCLK 0x0
/// ###
/// * Control clock to latch in FSCLK and FSCTRL
/// ###
/// %unsigned 3 FSCTRL 0x0
/// ###
/// * Freq_Slop_Ctrl
/// * Control the frequency sensitivity of the clk generator to DVDD
/// * 000: higher sensitivity
/// * ...
/// * 111: lower sensitivity
/// ###
/// %unsigned 4 IPP_IPTAT_DAC 0x0
/// ###
/// * Control the frequency sensitivity to temperature when bias_control = 0
/// * IPP_IPTAT_DAC[3]=1: higher frequency at higher temperature
/// * IPP_IPTAT_DAC[3]=0: lower frequency at higher temperature
/// * IPP_IPTAT_DAC[2:0] =
/// * 000: 0
/// * 001: 2.5u
/// * 010: 5u
/// * 011: 7.5u
/// * 100: 10u
/// * 101: 12.5u
/// * 110: 15u
/// * 111: 17.5u
/// ###
/// %% 6 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 4B, bits: 26b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_clkgen
#define h_clkgen (){}
#define RA_clkgen_CTRL 0x0000
#define BA_clkgen_CTRL_PU 0x0000
#define B16clkgen_CTRL_PU 0x0000
#define LSb32clkgen_CTRL_PU 0
#define LSb16clkgen_CTRL_PU 0
#define bclkgen_CTRL_PU 1
#define MSK32clkgen_CTRL_PU 0x00000001
#define BA_clkgen_CTRL_RST 0x0000
#define B16clkgen_CTRL_RST 0x0000
#define LSb32clkgen_CTRL_RST 1
#define LSb16clkgen_CTRL_RST 1
#define bclkgen_CTRL_RST 1
#define MSK32clkgen_CTRL_RST 0x00000002
#define BA_clkgen_CTRL_BAND_EN 0x0000
#define B16clkgen_CTRL_BAND_EN 0x0000
#define LSb32clkgen_CTRL_BAND_EN 2
#define LSb16clkgen_CTRL_BAND_EN 2
#define bclkgen_CTRL_BAND_EN 1
#define MSK32clkgen_CTRL_BAND_EN 0x00000004
#define BA_clkgen_CTRL_BCTRL 0x0000
#define B16clkgen_CTRL_BCTRL 0x0000
#define LSb32clkgen_CTRL_BCTRL 3
#define LSb16clkgen_CTRL_BCTRL 3
#define bclkgen_CTRL_BCTRL 1
#define MSK32clkgen_CTRL_BCTRL 0x00000008
#define BA_clkgen_CTRL_CADDR 0x0000
#define B16clkgen_CTRL_CADDR 0x0000
#define LSb32clkgen_CTRL_CADDR 4
#define LSb16clkgen_CTRL_CADDR 4
#define bclkgen_CTRL_CADDR 3
#define MSK32clkgen_CTRL_CADDR 0x00000070
#define BA_clkgen_CTRL_CCLK 0x0000
#define B16clkgen_CTRL_CCLK 0x0000
#define LSb32clkgen_CTRL_CCLK 7
#define LSb16clkgen_CTRL_CCLK 7
#define bclkgen_CTRL_CCLK 1
#define MSK32clkgen_CTRL_CCLK 0x00000080
#define BA_clkgen_CTRL_CCTRL 0x0001
#define B16clkgen_CTRL_CCTRL 0x0000
#define LSb32clkgen_CTRL_CCTRL 8
#define LSb16clkgen_CTRL_CCTRL 8
#define bclkgen_CTRL_CCTRL 3
#define MSK32clkgen_CTRL_CCTRL 0x00000700
#define BA_clkgen_CTRL_FCLK 0x0001
#define B16clkgen_CTRL_FCLK 0x0000
#define LSb32clkgen_CTRL_FCLK 11
#define LSb16clkgen_CTRL_FCLK 11
#define bclkgen_CTRL_FCLK 1
#define MSK32clkgen_CTRL_FCLK 0x00000800
#define BA_clkgen_CTRL_FCTRL 0x0001
#define B16clkgen_CTRL_FCTRL 0x0000
#define LSb32clkgen_CTRL_FCTRL 12
#define LSb16clkgen_CTRL_FCTRL 12
#define bclkgen_CTRL_FCTRL 6
#define MSK32clkgen_CTRL_FCTRL 0x0003F000
#define BA_clkgen_CTRL_FSCLK 0x0002
#define B16clkgen_CTRL_FSCLK 0x0002
#define LSb32clkgen_CTRL_FSCLK 18
#define LSb16clkgen_CTRL_FSCLK 2
#define bclkgen_CTRL_FSCLK 1
#define MSK32clkgen_CTRL_FSCLK 0x00040000
#define BA_clkgen_CTRL_FSCTRL 0x0002
#define B16clkgen_CTRL_FSCTRL 0x0002
#define LSb32clkgen_CTRL_FSCTRL 19
#define LSb16clkgen_CTRL_FSCTRL 3
#define bclkgen_CTRL_FSCTRL 3
#define MSK32clkgen_CTRL_FSCTRL 0x00380000
#define BA_clkgen_CTRL_IPP_IPTAT_DAC 0x0002
#define B16clkgen_CTRL_IPP_IPTAT_DAC 0x0002
#define LSb32clkgen_CTRL_IPP_IPTAT_DAC 22
#define LSb16clkgen_CTRL_IPP_IPTAT_DAC 6
#define bclkgen_CTRL_IPP_IPTAT_DAC 4
#define MSK32clkgen_CTRL_IPP_IPTAT_DAC 0x03C00000
///////////////////////////////////////////////////////////
typedef struct SIE_clkgen {
///////////////////////////////////////////////////////////
#define GET32clkgen_CTRL_PU(r32) _BFGET_(r32, 0, 0)
#define SET32clkgen_CTRL_PU(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16clkgen_CTRL_PU(r16) _BFGET_(r16, 0, 0)
#define SET16clkgen_CTRL_PU(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32clkgen_CTRL_RST(r32) _BFGET_(r32, 1, 1)
#define SET32clkgen_CTRL_RST(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16clkgen_CTRL_RST(r16) _BFGET_(r16, 1, 1)
#define SET16clkgen_CTRL_RST(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32clkgen_CTRL_BAND_EN(r32) _BFGET_(r32, 2, 2)
#define SET32clkgen_CTRL_BAND_EN(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16clkgen_CTRL_BAND_EN(r16) _BFGET_(r16, 2, 2)
#define SET16clkgen_CTRL_BAND_EN(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32clkgen_CTRL_BCTRL(r32) _BFGET_(r32, 3, 3)
#define SET32clkgen_CTRL_BCTRL(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16clkgen_CTRL_BCTRL(r16) _BFGET_(r16, 3, 3)
#define SET16clkgen_CTRL_BCTRL(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32clkgen_CTRL_CADDR(r32) _BFGET_(r32, 6, 4)
#define SET32clkgen_CTRL_CADDR(r32,v) _BFSET_(r32, 6, 4,v)
#define GET16clkgen_CTRL_CADDR(r16) _BFGET_(r16, 6, 4)
#define SET16clkgen_CTRL_CADDR(r16,v) _BFSET_(r16, 6, 4,v)
#define GET32clkgen_CTRL_CCLK(r32) _BFGET_(r32, 7, 7)
#define SET32clkgen_CTRL_CCLK(r32,v) _BFSET_(r32, 7, 7,v)
#define GET16clkgen_CTRL_CCLK(r16) _BFGET_(r16, 7, 7)
#define SET16clkgen_CTRL_CCLK(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32clkgen_CTRL_CCTRL(r32) _BFGET_(r32,10, 8)
#define SET32clkgen_CTRL_CCTRL(r32,v) _BFSET_(r32,10, 8,v)
#define GET16clkgen_CTRL_CCTRL(r16) _BFGET_(r16,10, 8)
#define SET16clkgen_CTRL_CCTRL(r16,v) _BFSET_(r16,10, 8,v)
#define GET32clkgen_CTRL_FCLK(r32) _BFGET_(r32,11,11)
#define SET32clkgen_CTRL_FCLK(r32,v) _BFSET_(r32,11,11,v)
#define GET16clkgen_CTRL_FCLK(r16) _BFGET_(r16,11,11)
#define SET16clkgen_CTRL_FCLK(r16,v) _BFSET_(r16,11,11,v)
#define GET32clkgen_CTRL_FCTRL(r32) _BFGET_(r32,17,12)
#define SET32clkgen_CTRL_FCTRL(r32,v) _BFSET_(r32,17,12,v)
#define GET32clkgen_CTRL_FSCLK(r32) _BFGET_(r32,18,18)
#define SET32clkgen_CTRL_FSCLK(r32,v) _BFSET_(r32,18,18,v)
#define GET16clkgen_CTRL_FSCLK(r16) _BFGET_(r16, 2, 2)
#define SET16clkgen_CTRL_FSCLK(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32clkgen_CTRL_FSCTRL(r32) _BFGET_(r32,21,19)
#define SET32clkgen_CTRL_FSCTRL(r32,v) _BFSET_(r32,21,19,v)
#define GET16clkgen_CTRL_FSCTRL(r16) _BFGET_(r16, 5, 3)
#define SET16clkgen_CTRL_FSCTRL(r16,v) _BFSET_(r16, 5, 3,v)
#define GET32clkgen_CTRL_IPP_IPTAT_DAC(r32) _BFGET_(r32,25,22)
#define SET32clkgen_CTRL_IPP_IPTAT_DAC(r32,v) _BFSET_(r32,25,22,v)
#define GET16clkgen_CTRL_IPP_IPTAT_DAC(r16) _BFGET_(r16, 9, 6)
#define SET16clkgen_CTRL_IPP_IPTAT_DAC(r16,v) _BFSET_(r16, 9, 6,v)
#define w32clkgen_CTRL {\
UNSG32 uCTRL_PU : 1;\
UNSG32 uCTRL_RST : 1;\
UNSG32 uCTRL_BAND_EN : 1;\
UNSG32 uCTRL_BCTRL : 1;\
UNSG32 uCTRL_CADDR : 3;\
UNSG32 uCTRL_CCLK : 1;\
UNSG32 uCTRL_CCTRL : 3;\
UNSG32 uCTRL_FCLK : 1;\
UNSG32 uCTRL_FCTRL : 6;\
UNSG32 uCTRL_FSCLK : 1;\
UNSG32 uCTRL_FSCTRL : 3;\
UNSG32 uCTRL_IPP_IPTAT_DAC : 4;\
UNSG32 RSVDx0_b26 : 6;\
}
union { UNSG32 u32clkgen_CTRL;
struct w32clkgen_CTRL;
};
///////////////////////////////////////////////////////////
} SIE_clkgen;
typedef union T32clkgen_CTRL
{ UNSG32 u32;
struct w32clkgen_CTRL;
} T32clkgen_CTRL;
///////////////////////////////////////////////////////////
typedef union Tclkgen_CTRL
{ UNSG32 u32[1];
struct {
struct w32clkgen_CTRL;
};
} Tclkgen_CTRL;
///////////////////////////////////////////////////////////
SIGN32 clkgen_drvrd(SIE_clkgen *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 clkgen_drvwr(SIE_clkgen *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void clkgen_reset(SIE_clkgen *p);
SIGN32 clkgen_cmp (SIE_clkgen *p, SIE_clkgen *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define clkgen_check(p,pie,pfx,hLOG) clkgen_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define clkgen_print(p, pfx,hLOG) clkgen_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: clkgen
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE fvsCtrl (4,4)
/// ###
/// * Controls for Frequency and Voltage Scaler.
/// * Direct connects into IP ports of the same name.
/// ###
/// # # ----------------------------------------------------------
/// @ 0x00000 rstn (P)
/// %unsigned 1 all 0x0
/// ###
/// * 1'b0: Reset activity monitor and clock rate controller
/// * 1'b1: Normal operations
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x00004 CTRL0 (P)
/// %unsigned 11 lcd0_dactivity 0x0
/// %unsigned 1 lcd0_ddat_vld 0x0
/// %unsigned 1 lcd0_off 0x0
/// %% 19 # Stuffing bits...
/// @ 0x00008 CTRL1 (P)
/// %unsigned 11 lcd1_dactivity 0x0
/// %unsigned 1 lcd1_ddat_vld 0x0
/// %unsigned 1 lcd1_off 0x0
/// %% 19 # Stuffing bits...
/// @ 0x0000C CTRL2 (P)
/// %unsigned 1 m1_pm_assert_apps2main_fw_n 0x0
/// %unsigned 5 block_idle 0x0
/// %unsigned 1 over_heat 0x0
/// %unsigned 8 norm_int 0x0
/// %unsigned 8 prio_int 0x0
/// %% 9 # Stuffing bits...
/// @ 0x00010 CTRL3 (P)
/// %unsigned 1 vscaleloadrten 0x0
/// %unsigned 4 vscaleloadrtin 0x0
/// %unsigned 4 vscalepor 0x0
/// %% 23 # Stuffing bits...
/// @ 0x00014 CTRL4 (P)
/// %unsigned 1 fscalealoadrten 0x0
/// %unsigned 6 fscalealoadrtin 0x0
/// %unsigned 6 fscaleapor 0x0
/// %unsigned 1 fscaledloadrten 0x0
/// %unsigned 8 fscaledloadrtin 0x0
/// %unsigned 8 fscaledpor 0x0
/// %% 2 # Stuffing bits...
/// @ 0x00018 CTRL5 (P)
/// %unsigned 16 adc_sensor 0x0
/// %unsigned 1 adc_drdy 0x0
/// %% 15 # Stuffing bits...
/// @ 0x0001C CRC_SD_REQ (P)
/// %unsigned 1 SD_REQ 0x0
/// %% 31 # Stuffing bits...
/// @ 0x00020 CRC_SD_ACK (R-)
/// %unsigned 1 SD_ACK 0x0
/// %% 31 # Stuffing bits...
/// @ 0x00024 V_CTRL (R-)
/// %unsigned 4 V_CTRL 0x0
/// %% 28 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 40B, bits: 112b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_fvsCtrl
#define h_fvsCtrl (){}
#define RA_fvsCtrl_rstn 0x0000
#define BA_fvsCtrl_rstn_all 0x0000
#define B16fvsCtrl_rstn_all 0x0000
#define LSb32fvsCtrl_rstn_all 0
#define LSb16fvsCtrl_rstn_all 0
#define bfvsCtrl_rstn_all 1
#define MSK32fvsCtrl_rstn_all 0x00000001
///////////////////////////////////////////////////////////
#define RA_fvsCtrl_CTRL0 0x0004
#define BA_fvsCtrl_CTRL0_lcd0_dactivity 0x0004
#define B16fvsCtrl_CTRL0_lcd0_dactivity 0x0004
#define LSb32fvsCtrl_CTRL0_lcd0_dactivity 0
#define LSb16fvsCtrl_CTRL0_lcd0_dactivity 0
#define bfvsCtrl_CTRL0_lcd0_dactivity 11
#define MSK32fvsCtrl_CTRL0_lcd0_dactivity 0x000007FF
#define BA_fvsCtrl_CTRL0_lcd0_ddat_vld 0x0005
#define B16fvsCtrl_CTRL0_lcd0_ddat_vld 0x0004
#define LSb32fvsCtrl_CTRL0_lcd0_ddat_vld 11
#define LSb16fvsCtrl_CTRL0_lcd0_ddat_vld 11
#define bfvsCtrl_CTRL0_lcd0_ddat_vld 1
#define MSK32fvsCtrl_CTRL0_lcd0_ddat_vld 0x00000800
#define BA_fvsCtrl_CTRL0_lcd0_off 0x0005
#define B16fvsCtrl_CTRL0_lcd0_off 0x0004
#define LSb32fvsCtrl_CTRL0_lcd0_off 12
#define LSb16fvsCtrl_CTRL0_lcd0_off 12
#define bfvsCtrl_CTRL0_lcd0_off 1
#define MSK32fvsCtrl_CTRL0_lcd0_off 0x00001000
///////////////////////////////////////////////////////////
#define RA_fvsCtrl_CTRL1 0x0008
#define BA_fvsCtrl_CTRL1_lcd1_dactivity 0x0008
#define B16fvsCtrl_CTRL1_lcd1_dactivity 0x0008
#define LSb32fvsCtrl_CTRL1_lcd1_dactivity 0
#define LSb16fvsCtrl_CTRL1_lcd1_dactivity 0
#define bfvsCtrl_CTRL1_lcd1_dactivity 11
#define MSK32fvsCtrl_CTRL1_lcd1_dactivity 0x000007FF
#define BA_fvsCtrl_CTRL1_lcd1_ddat_vld 0x0009
#define B16fvsCtrl_CTRL1_lcd1_ddat_vld 0x0008
#define LSb32fvsCtrl_CTRL1_lcd1_ddat_vld 11
#define LSb16fvsCtrl_CTRL1_lcd1_ddat_vld 11
#define bfvsCtrl_CTRL1_lcd1_ddat_vld 1
#define MSK32fvsCtrl_CTRL1_lcd1_ddat_vld 0x00000800
#define BA_fvsCtrl_CTRL1_lcd1_off 0x0009
#define B16fvsCtrl_CTRL1_lcd1_off 0x0008
#define LSb32fvsCtrl_CTRL1_lcd1_off 12
#define LSb16fvsCtrl_CTRL1_lcd1_off 12
#define bfvsCtrl_CTRL1_lcd1_off 1
#define MSK32fvsCtrl_CTRL1_lcd1_off 0x00001000
///////////////////////////////////////////////////////////
#define RA_fvsCtrl_CTRL2 0x000C
#define BA_fvsCtrl_CTRL2_m1_pm_assert_apps2main_fw_n 0x000C
#define B16fvsCtrl_CTRL2_m1_pm_assert_apps2main_fw_n 0x000C
#define LSb32fvsCtrl_CTRL2_m1_pm_assert_apps2main_fw_n 0
#define LSb16fvsCtrl_CTRL2_m1_pm_assert_apps2main_fw_n 0
#define bfvsCtrl_CTRL2_m1_pm_assert_apps2main_fw_n 1
#define MSK32fvsCtrl_CTRL2_m1_pm_assert_apps2main_fw_n 0x00000001
#define BA_fvsCtrl_CTRL2_block_idle 0x000C
#define B16fvsCtrl_CTRL2_block_idle 0x000C
#define LSb32fvsCtrl_CTRL2_block_idle 1
#define LSb16fvsCtrl_CTRL2_block_idle 1
#define bfvsCtrl_CTRL2_block_idle 5
#define MSK32fvsCtrl_CTRL2_block_idle 0x0000003E
#define BA_fvsCtrl_CTRL2_over_heat 0x000C
#define B16fvsCtrl_CTRL2_over_heat 0x000C
#define LSb32fvsCtrl_CTRL2_over_heat 6
#define LSb16fvsCtrl_CTRL2_over_heat 6
#define bfvsCtrl_CTRL2_over_heat 1
#define MSK32fvsCtrl_CTRL2_over_heat 0x00000040
#define BA_fvsCtrl_CTRL2_norm_int 0x000C
#define B16fvsCtrl_CTRL2_norm_int 0x000C
#define LSb32fvsCtrl_CTRL2_norm_int 7
#define LSb16fvsCtrl_CTRL2_norm_int 7
#define bfvsCtrl_CTRL2_norm_int 8
#define MSK32fvsCtrl_CTRL2_norm_int 0x00007F80
#define BA_fvsCtrl_CTRL2_prio_int 0x000D
#define B16fvsCtrl_CTRL2_prio_int 0x000C
#define LSb32fvsCtrl_CTRL2_prio_int 15
#define LSb16fvsCtrl_CTRL2_prio_int 15
#define bfvsCtrl_CTRL2_prio_int 8
#define MSK32fvsCtrl_CTRL2_prio_int 0x007F8000
///////////////////////////////////////////////////////////
#define RA_fvsCtrl_CTRL3 0x0010
#define BA_fvsCtrl_CTRL3_vscaleloadrten 0x0010
#define B16fvsCtrl_CTRL3_vscaleloadrten 0x0010
#define LSb32fvsCtrl_CTRL3_vscaleloadrten 0
#define LSb16fvsCtrl_CTRL3_vscaleloadrten 0
#define bfvsCtrl_CTRL3_vscaleloadrten 1
#define MSK32fvsCtrl_CTRL3_vscaleloadrten 0x00000001
#define BA_fvsCtrl_CTRL3_vscaleloadrtin 0x0010
#define B16fvsCtrl_CTRL3_vscaleloadrtin 0x0010
#define LSb32fvsCtrl_CTRL3_vscaleloadrtin 1
#define LSb16fvsCtrl_CTRL3_vscaleloadrtin 1
#define bfvsCtrl_CTRL3_vscaleloadrtin 4
#define MSK32fvsCtrl_CTRL3_vscaleloadrtin 0x0000001E
#define BA_fvsCtrl_CTRL3_vscalepor 0x0010
#define B16fvsCtrl_CTRL3_vscalepor 0x0010
#define LSb32fvsCtrl_CTRL3_vscalepor 5
#define LSb16fvsCtrl_CTRL3_vscalepor 5
#define bfvsCtrl_CTRL3_vscalepor 4
#define MSK32fvsCtrl_CTRL3_vscalepor 0x000001E0
///////////////////////////////////////////////////////////
#define RA_fvsCtrl_CTRL4 0x0014
#define BA_fvsCtrl_CTRL4_fscalealoadrten 0x0014
#define B16fvsCtrl_CTRL4_fscalealoadrten 0x0014
#define LSb32fvsCtrl_CTRL4_fscalealoadrten 0
#define LSb16fvsCtrl_CTRL4_fscalealoadrten 0
#define bfvsCtrl_CTRL4_fscalealoadrten 1
#define MSK32fvsCtrl_CTRL4_fscalealoadrten 0x00000001
#define BA_fvsCtrl_CTRL4_fscalealoadrtin 0x0014
#define B16fvsCtrl_CTRL4_fscalealoadrtin 0x0014
#define LSb32fvsCtrl_CTRL4_fscalealoadrtin 1
#define LSb16fvsCtrl_CTRL4_fscalealoadrtin 1
#define bfvsCtrl_CTRL4_fscalealoadrtin 6
#define MSK32fvsCtrl_CTRL4_fscalealoadrtin 0x0000007E
#define BA_fvsCtrl_CTRL4_fscaleapor 0x0014
#define B16fvsCtrl_CTRL4_fscaleapor 0x0014
#define LSb32fvsCtrl_CTRL4_fscaleapor 7
#define LSb16fvsCtrl_CTRL4_fscaleapor 7
#define bfvsCtrl_CTRL4_fscaleapor 6
#define MSK32fvsCtrl_CTRL4_fscaleapor 0x00001F80
#define BA_fvsCtrl_CTRL4_fscaledloadrten 0x0015
#define B16fvsCtrl_CTRL4_fscaledloadrten 0x0014
#define LSb32fvsCtrl_CTRL4_fscaledloadrten 13
#define LSb16fvsCtrl_CTRL4_fscaledloadrten 13
#define bfvsCtrl_CTRL4_fscaledloadrten 1
#define MSK32fvsCtrl_CTRL4_fscaledloadrten 0x00002000
#define BA_fvsCtrl_CTRL4_fscaledloadrtin 0x0015
#define B16fvsCtrl_CTRL4_fscaledloadrtin 0x0014
#define LSb32fvsCtrl_CTRL4_fscaledloadrtin 14
#define LSb16fvsCtrl_CTRL4_fscaledloadrtin 14
#define bfvsCtrl_CTRL4_fscaledloadrtin 8
#define MSK32fvsCtrl_CTRL4_fscaledloadrtin 0x003FC000
#define BA_fvsCtrl_CTRL4_fscaledpor 0x0016
#define B16fvsCtrl_CTRL4_fscaledpor 0x0016
#define LSb32fvsCtrl_CTRL4_fscaledpor 22
#define LSb16fvsCtrl_CTRL4_fscaledpor 6
#define bfvsCtrl_CTRL4_fscaledpor 8
#define MSK32fvsCtrl_CTRL4_fscaledpor 0x3FC00000
///////////////////////////////////////////////////////////
#define RA_fvsCtrl_CTRL5 0x0018
#define BA_fvsCtrl_CTRL5_adc_sensor 0x0018
#define B16fvsCtrl_CTRL5_adc_sensor 0x0018
#define LSb32fvsCtrl_CTRL5_adc_sensor 0
#define LSb16fvsCtrl_CTRL5_adc_sensor 0
#define bfvsCtrl_CTRL5_adc_sensor 16
#define MSK32fvsCtrl_CTRL5_adc_sensor 0x0000FFFF
#define BA_fvsCtrl_CTRL5_adc_drdy 0x001A
#define B16fvsCtrl_CTRL5_adc_drdy 0x001A
#define LSb32fvsCtrl_CTRL5_adc_drdy 16
#define LSb16fvsCtrl_CTRL5_adc_drdy 0
#define bfvsCtrl_CTRL5_adc_drdy 1
#define MSK32fvsCtrl_CTRL5_adc_drdy 0x00010000
///////////////////////////////////////////////////////////
#define RA_fvsCtrl_CRC_SD_REQ 0x001C
#define BA_fvsCtrl_CRC_SD_REQ_SD_REQ 0x001C
#define B16fvsCtrl_CRC_SD_REQ_SD_REQ 0x001C
#define LSb32fvsCtrl_CRC_SD_REQ_SD_REQ 0
#define LSb16fvsCtrl_CRC_SD_REQ_SD_REQ 0
#define bfvsCtrl_CRC_SD_REQ_SD_REQ 1
#define MSK32fvsCtrl_CRC_SD_REQ_SD_REQ 0x00000001
///////////////////////////////////////////////////////////
#define RA_fvsCtrl_CRC_SD_ACK 0x0020
#define BA_fvsCtrl_CRC_SD_ACK_SD_ACK 0x0020
#define B16fvsCtrl_CRC_SD_ACK_SD_ACK 0x0020
#define LSb32fvsCtrl_CRC_SD_ACK_SD_ACK 0
#define LSb16fvsCtrl_CRC_SD_ACK_SD_ACK 0
#define bfvsCtrl_CRC_SD_ACK_SD_ACK 1
#define MSK32fvsCtrl_CRC_SD_ACK_SD_ACK 0x00000001
///////////////////////////////////////////////////////////
#define RA_fvsCtrl_V_CTRL 0x0024
#define BA_fvsCtrl_V_CTRL_V_CTRL 0x0024
#define B16fvsCtrl_V_CTRL_V_CTRL 0x0024
#define LSb32fvsCtrl_V_CTRL_V_CTRL 0
#define LSb16fvsCtrl_V_CTRL_V_CTRL 0
#define bfvsCtrl_V_CTRL_V_CTRL 4
#define MSK32fvsCtrl_V_CTRL_V_CTRL 0x0000000F
///////////////////////////////////////////////////////////
typedef struct SIE_fvsCtrl {
///////////////////////////////////////////////////////////
#define GET32fvsCtrl_rstn_all(r32) _BFGET_(r32, 0, 0)
#define SET32fvsCtrl_rstn_all(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16fvsCtrl_rstn_all(r16) _BFGET_(r16, 0, 0)
#define SET16fvsCtrl_rstn_all(r16,v) _BFSET_(r16, 0, 0,v)
#define w32fvsCtrl_rstn {\
UNSG32 urstn_all : 1;\
UNSG32 RSVDx0_b1 : 31;\
}
union { UNSG32 u32fvsCtrl_rstn;
struct w32fvsCtrl_rstn;
};
///////////////////////////////////////////////////////////
#define GET32fvsCtrl_CTRL0_lcd0_dactivity(r32) _BFGET_(r32,10, 0)
#define SET32fvsCtrl_CTRL0_lcd0_dactivity(r32,v) _BFSET_(r32,10, 0,v)
#define GET16fvsCtrl_CTRL0_lcd0_dactivity(r16) _BFGET_(r16,10, 0)
#define SET16fvsCtrl_CTRL0_lcd0_dactivity(r16,v) _BFSET_(r16,10, 0,v)
#define GET32fvsCtrl_CTRL0_lcd0_ddat_vld(r32) _BFGET_(r32,11,11)
#define SET32fvsCtrl_CTRL0_lcd0_ddat_vld(r32,v) _BFSET_(r32,11,11,v)
#define GET16fvsCtrl_CTRL0_lcd0_ddat_vld(r16) _BFGET_(r16,11,11)
#define SET16fvsCtrl_CTRL0_lcd0_ddat_vld(r16,v) _BFSET_(r16,11,11,v)
#define GET32fvsCtrl_CTRL0_lcd0_off(r32) _BFGET_(r32,12,12)
#define SET32fvsCtrl_CTRL0_lcd0_off(r32,v) _BFSET_(r32,12,12,v)
#define GET16fvsCtrl_CTRL0_lcd0_off(r16) _BFGET_(r16,12,12)
#define SET16fvsCtrl_CTRL0_lcd0_off(r16,v) _BFSET_(r16,12,12,v)
#define w32fvsCtrl_CTRL0 {\
UNSG32 uCTRL0_lcd0_dactivity : 11;\
UNSG32 uCTRL0_lcd0_ddat_vld : 1;\
UNSG32 uCTRL0_lcd0_off : 1;\
UNSG32 RSVDx4_b13 : 19;\
}
union { UNSG32 u32fvsCtrl_CTRL0;
struct w32fvsCtrl_CTRL0;
};
///////////////////////////////////////////////////////////
#define GET32fvsCtrl_CTRL1_lcd1_dactivity(r32) _BFGET_(r32,10, 0)
#define SET32fvsCtrl_CTRL1_lcd1_dactivity(r32,v) _BFSET_(r32,10, 0,v)
#define GET16fvsCtrl_CTRL1_lcd1_dactivity(r16) _BFGET_(r16,10, 0)
#define SET16fvsCtrl_CTRL1_lcd1_dactivity(r16,v) _BFSET_(r16,10, 0,v)
#define GET32fvsCtrl_CTRL1_lcd1_ddat_vld(r32) _BFGET_(r32,11,11)
#define SET32fvsCtrl_CTRL1_lcd1_ddat_vld(r32,v) _BFSET_(r32,11,11,v)
#define GET16fvsCtrl_CTRL1_lcd1_ddat_vld(r16) _BFGET_(r16,11,11)
#define SET16fvsCtrl_CTRL1_lcd1_ddat_vld(r16,v) _BFSET_(r16,11,11,v)
#define GET32fvsCtrl_CTRL1_lcd1_off(r32) _BFGET_(r32,12,12)
#define SET32fvsCtrl_CTRL1_lcd1_off(r32,v) _BFSET_(r32,12,12,v)
#define GET16fvsCtrl_CTRL1_lcd1_off(r16) _BFGET_(r16,12,12)
#define SET16fvsCtrl_CTRL1_lcd1_off(r16,v) _BFSET_(r16,12,12,v)
#define w32fvsCtrl_CTRL1 {\
UNSG32 uCTRL1_lcd1_dactivity : 11;\
UNSG32 uCTRL1_lcd1_ddat_vld : 1;\
UNSG32 uCTRL1_lcd1_off : 1;\
UNSG32 RSVDx8_b13 : 19;\
}
union { UNSG32 u32fvsCtrl_CTRL1;
struct w32fvsCtrl_CTRL1;
};
///////////////////////////////////////////////////////////
#define GET32fvsCtrl_CTRL2_m1_pm_assert_apps2main_fw_n(r32) _BFGET_(r32, 0, 0)
#define SET32fvsCtrl_CTRL2_m1_pm_assert_apps2main_fw_n(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16fvsCtrl_CTRL2_m1_pm_assert_apps2main_fw_n(r16) _BFGET_(r16, 0, 0)
#define SET16fvsCtrl_CTRL2_m1_pm_assert_apps2main_fw_n(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32fvsCtrl_CTRL2_block_idle(r32) _BFGET_(r32, 5, 1)
#define SET32fvsCtrl_CTRL2_block_idle(r32,v) _BFSET_(r32, 5, 1,v)
#define GET16fvsCtrl_CTRL2_block_idle(r16) _BFGET_(r16, 5, 1)
#define SET16fvsCtrl_CTRL2_block_idle(r16,v) _BFSET_(r16, 5, 1,v)
#define GET32fvsCtrl_CTRL2_over_heat(r32) _BFGET_(r32, 6, 6)
#define SET32fvsCtrl_CTRL2_over_heat(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16fvsCtrl_CTRL2_over_heat(r16) _BFGET_(r16, 6, 6)
#define SET16fvsCtrl_CTRL2_over_heat(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32fvsCtrl_CTRL2_norm_int(r32) _BFGET_(r32,14, 7)
#define SET32fvsCtrl_CTRL2_norm_int(r32,v) _BFSET_(r32,14, 7,v)
#define GET16fvsCtrl_CTRL2_norm_int(r16) _BFGET_(r16,14, 7)
#define SET16fvsCtrl_CTRL2_norm_int(r16,v) _BFSET_(r16,14, 7,v)
#define GET32fvsCtrl_CTRL2_prio_int(r32) _BFGET_(r32,22,15)
#define SET32fvsCtrl_CTRL2_prio_int(r32,v) _BFSET_(r32,22,15,v)
#define w32fvsCtrl_CTRL2 {\
UNSG32 uCTRL2_m1_pm_assert_apps2main_fw_n : 1;\
UNSG32 uCTRL2_block_idle : 5;\
UNSG32 uCTRL2_over_heat : 1;\
UNSG32 uCTRL2_norm_int : 8;\
UNSG32 uCTRL2_prio_int : 8;\
UNSG32 RSVDxC_b23 : 9;\
}
union { UNSG32 u32fvsCtrl_CTRL2;
struct w32fvsCtrl_CTRL2;
};
///////////////////////////////////////////////////////////
#define GET32fvsCtrl_CTRL3_vscaleloadrten(r32) _BFGET_(r32, 0, 0)
#define SET32fvsCtrl_CTRL3_vscaleloadrten(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16fvsCtrl_CTRL3_vscaleloadrten(r16) _BFGET_(r16, 0, 0)
#define SET16fvsCtrl_CTRL3_vscaleloadrten(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32fvsCtrl_CTRL3_vscaleloadrtin(r32) _BFGET_(r32, 4, 1)
#define SET32fvsCtrl_CTRL3_vscaleloadrtin(r32,v) _BFSET_(r32, 4, 1,v)
#define GET16fvsCtrl_CTRL3_vscaleloadrtin(r16) _BFGET_(r16, 4, 1)
#define SET16fvsCtrl_CTRL3_vscaleloadrtin(r16,v) _BFSET_(r16, 4, 1,v)
#define GET32fvsCtrl_CTRL3_vscalepor(r32) _BFGET_(r32, 8, 5)
#define SET32fvsCtrl_CTRL3_vscalepor(r32,v) _BFSET_(r32, 8, 5,v)
#define GET16fvsCtrl_CTRL3_vscalepor(r16) _BFGET_(r16, 8, 5)
#define SET16fvsCtrl_CTRL3_vscalepor(r16,v) _BFSET_(r16, 8, 5,v)
#define w32fvsCtrl_CTRL3 {\
UNSG32 uCTRL3_vscaleloadrten : 1;\
UNSG32 uCTRL3_vscaleloadrtin : 4;\
UNSG32 uCTRL3_vscalepor : 4;\
UNSG32 RSVDx10_b9 : 23;\
}
union { UNSG32 u32fvsCtrl_CTRL3;
struct w32fvsCtrl_CTRL3;
};
///////////////////////////////////////////////////////////
#define GET32fvsCtrl_CTRL4_fscalealoadrten(r32) _BFGET_(r32, 0, 0)
#define SET32fvsCtrl_CTRL4_fscalealoadrten(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16fvsCtrl_CTRL4_fscalealoadrten(r16) _BFGET_(r16, 0, 0)
#define SET16fvsCtrl_CTRL4_fscalealoadrten(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32fvsCtrl_CTRL4_fscalealoadrtin(r32) _BFGET_(r32, 6, 1)
#define SET32fvsCtrl_CTRL4_fscalealoadrtin(r32,v) _BFSET_(r32, 6, 1,v)
#define GET16fvsCtrl_CTRL4_fscalealoadrtin(r16) _BFGET_(r16, 6, 1)
#define SET16fvsCtrl_CTRL4_fscalealoadrtin(r16,v) _BFSET_(r16, 6, 1,v)
#define GET32fvsCtrl_CTRL4_fscaleapor(r32) _BFGET_(r32,12, 7)
#define SET32fvsCtrl_CTRL4_fscaleapor(r32,v) _BFSET_(r32,12, 7,v)
#define GET16fvsCtrl_CTRL4_fscaleapor(r16) _BFGET_(r16,12, 7)
#define SET16fvsCtrl_CTRL4_fscaleapor(r16,v) _BFSET_(r16,12, 7,v)
#define GET32fvsCtrl_CTRL4_fscaledloadrten(r32) _BFGET_(r32,13,13)
#define SET32fvsCtrl_CTRL4_fscaledloadrten(r32,v) _BFSET_(r32,13,13,v)
#define GET16fvsCtrl_CTRL4_fscaledloadrten(r16) _BFGET_(r16,13,13)
#define SET16fvsCtrl_CTRL4_fscaledloadrten(r16,v) _BFSET_(r16,13,13,v)
#define GET32fvsCtrl_CTRL4_fscaledloadrtin(r32) _BFGET_(r32,21,14)
#define SET32fvsCtrl_CTRL4_fscaledloadrtin(r32,v) _BFSET_(r32,21,14,v)
#define GET32fvsCtrl_CTRL4_fscaledpor(r32) _BFGET_(r32,29,22)
#define SET32fvsCtrl_CTRL4_fscaledpor(r32,v) _BFSET_(r32,29,22,v)
#define GET16fvsCtrl_CTRL4_fscaledpor(r16) _BFGET_(r16,13, 6)
#define SET16fvsCtrl_CTRL4_fscaledpor(r16,v) _BFSET_(r16,13, 6,v)
#define w32fvsCtrl_CTRL4 {\
UNSG32 uCTRL4_fscalealoadrten : 1;\
UNSG32 uCTRL4_fscalealoadrtin : 6;\
UNSG32 uCTRL4_fscaleapor : 6;\
UNSG32 uCTRL4_fscaledloadrten : 1;\
UNSG32 uCTRL4_fscaledloadrtin : 8;\
UNSG32 uCTRL4_fscaledpor : 8;\
UNSG32 RSVDx14_b30 : 2;\
}
union { UNSG32 u32fvsCtrl_CTRL4;
struct w32fvsCtrl_CTRL4;
};
///////////////////////////////////////////////////////////
#define GET32fvsCtrl_CTRL5_adc_sensor(r32) _BFGET_(r32,15, 0)
#define SET32fvsCtrl_CTRL5_adc_sensor(r32,v) _BFSET_(r32,15, 0,v)
#define GET16fvsCtrl_CTRL5_adc_sensor(r16) _BFGET_(r16,15, 0)
#define SET16fvsCtrl_CTRL5_adc_sensor(r16,v) _BFSET_(r16,15, 0,v)
#define GET32fvsCtrl_CTRL5_adc_drdy(r32) _BFGET_(r32,16,16)
#define SET32fvsCtrl_CTRL5_adc_drdy(r32,v) _BFSET_(r32,16,16,v)
#define GET16fvsCtrl_CTRL5_adc_drdy(r16) _BFGET_(r16, 0, 0)
#define SET16fvsCtrl_CTRL5_adc_drdy(r16,v) _BFSET_(r16, 0, 0,v)
#define w32fvsCtrl_CTRL5 {\
UNSG32 uCTRL5_adc_sensor : 16;\
UNSG32 uCTRL5_adc_drdy : 1;\
UNSG32 RSVDx18_b17 : 15;\
}
union { UNSG32 u32fvsCtrl_CTRL5;
struct w32fvsCtrl_CTRL5;
};
///////////////////////////////////////////////////////////
#define GET32fvsCtrl_CRC_SD_REQ_SD_REQ(r32) _BFGET_(r32, 0, 0)
#define SET32fvsCtrl_CRC_SD_REQ_SD_REQ(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16fvsCtrl_CRC_SD_REQ_SD_REQ(r16) _BFGET_(r16, 0, 0)
#define SET16fvsCtrl_CRC_SD_REQ_SD_REQ(r16,v) _BFSET_(r16, 0, 0,v)
#define w32fvsCtrl_CRC_SD_REQ {\
UNSG32 uCRC_SD_REQ_SD_REQ : 1;\
UNSG32 RSVDx1C_b1 : 31;\
}
union { UNSG32 u32fvsCtrl_CRC_SD_REQ;
struct w32fvsCtrl_CRC_SD_REQ;
};
///////////////////////////////////////////////////////////
#define GET32fvsCtrl_CRC_SD_ACK_SD_ACK(r32) _BFGET_(r32, 0, 0)
#define SET32fvsCtrl_CRC_SD_ACK_SD_ACK(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16fvsCtrl_CRC_SD_ACK_SD_ACK(r16) _BFGET_(r16, 0, 0)
#define SET16fvsCtrl_CRC_SD_ACK_SD_ACK(r16,v) _BFSET_(r16, 0, 0,v)
#define w32fvsCtrl_CRC_SD_ACK {\
UNSG32 uCRC_SD_ACK_SD_ACK : 1;\
UNSG32 RSVDx20_b1 : 31;\
}
union { UNSG32 u32fvsCtrl_CRC_SD_ACK;
struct w32fvsCtrl_CRC_SD_ACK;
};
///////////////////////////////////////////////////////////
#define GET32fvsCtrl_V_CTRL_V_CTRL(r32) _BFGET_(r32, 3, 0)
#define SET32fvsCtrl_V_CTRL_V_CTRL(r32,v) _BFSET_(r32, 3, 0,v)
#define GET16fvsCtrl_V_CTRL_V_CTRL(r16) _BFGET_(r16, 3, 0)
#define SET16fvsCtrl_V_CTRL_V_CTRL(r16,v) _BFSET_(r16, 3, 0,v)
#define w32fvsCtrl_V_CTRL {\
UNSG32 uV_CTRL_V_CTRL : 4;\
UNSG32 RSVDx24_b4 : 28;\
}
union { UNSG32 u32fvsCtrl_V_CTRL;
struct w32fvsCtrl_V_CTRL;
};
///////////////////////////////////////////////////////////
} SIE_fvsCtrl;
typedef union T32fvsCtrl_rstn
{ UNSG32 u32;
struct w32fvsCtrl_rstn;
} T32fvsCtrl_rstn;
typedef union T32fvsCtrl_CTRL0
{ UNSG32 u32;
struct w32fvsCtrl_CTRL0;
} T32fvsCtrl_CTRL0;
typedef union T32fvsCtrl_CTRL1
{ UNSG32 u32;
struct w32fvsCtrl_CTRL1;
} T32fvsCtrl_CTRL1;
typedef union T32fvsCtrl_CTRL2
{ UNSG32 u32;
struct w32fvsCtrl_CTRL2;
} T32fvsCtrl_CTRL2;
typedef union T32fvsCtrl_CTRL3
{ UNSG32 u32;
struct w32fvsCtrl_CTRL3;
} T32fvsCtrl_CTRL3;
typedef union T32fvsCtrl_CTRL4
{ UNSG32 u32;
struct w32fvsCtrl_CTRL4;
} T32fvsCtrl_CTRL4;
typedef union T32fvsCtrl_CTRL5
{ UNSG32 u32;
struct w32fvsCtrl_CTRL5;
} T32fvsCtrl_CTRL5;
typedef union T32fvsCtrl_CRC_SD_REQ
{ UNSG32 u32;
struct w32fvsCtrl_CRC_SD_REQ;
} T32fvsCtrl_CRC_SD_REQ;
typedef union T32fvsCtrl_CRC_SD_ACK
{ UNSG32 u32;
struct w32fvsCtrl_CRC_SD_ACK;
} T32fvsCtrl_CRC_SD_ACK;
typedef union T32fvsCtrl_V_CTRL
{ UNSG32 u32;
struct w32fvsCtrl_V_CTRL;
} T32fvsCtrl_V_CTRL;
///////////////////////////////////////////////////////////
typedef union TfvsCtrl_rstn
{ UNSG32 u32[1];
struct {
struct w32fvsCtrl_rstn;
};
} TfvsCtrl_rstn;
typedef union TfvsCtrl_CTRL0
{ UNSG32 u32[1];
struct {
struct w32fvsCtrl_CTRL0;
};
} TfvsCtrl_CTRL0;
typedef union TfvsCtrl_CTRL1
{ UNSG32 u32[1];
struct {
struct w32fvsCtrl_CTRL1;
};
} TfvsCtrl_CTRL1;
typedef union TfvsCtrl_CTRL2
{ UNSG32 u32[1];
struct {
struct w32fvsCtrl_CTRL2;
};
} TfvsCtrl_CTRL2;
typedef union TfvsCtrl_CTRL3
{ UNSG32 u32[1];
struct {
struct w32fvsCtrl_CTRL3;
};
} TfvsCtrl_CTRL3;
typedef union TfvsCtrl_CTRL4
{ UNSG32 u32[1];
struct {
struct w32fvsCtrl_CTRL4;
};
} TfvsCtrl_CTRL4;
typedef union TfvsCtrl_CTRL5
{ UNSG32 u32[1];
struct {
struct w32fvsCtrl_CTRL5;
};
} TfvsCtrl_CTRL5;
typedef union TfvsCtrl_CRC_SD_REQ
{ UNSG32 u32[1];
struct {
struct w32fvsCtrl_CRC_SD_REQ;
};
} TfvsCtrl_CRC_SD_REQ;
typedef union TfvsCtrl_CRC_SD_ACK
{ UNSG32 u32[1];
struct {
struct w32fvsCtrl_CRC_SD_ACK;
};
} TfvsCtrl_CRC_SD_ACK;
typedef union TfvsCtrl_V_CTRL
{ UNSG32 u32[1];
struct {
struct w32fvsCtrl_V_CTRL;
};
} TfvsCtrl_V_CTRL;
///////////////////////////////////////////////////////////
SIGN32 fvsCtrl_drvrd(SIE_fvsCtrl *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 fvsCtrl_drvwr(SIE_fvsCtrl *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void fvsCtrl_reset(SIE_fvsCtrl *p);
SIGN32 fvsCtrl_cmp (SIE_fvsCtrl *p, SIE_fvsCtrl *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define fvsCtrl_check(p,pie,pfx,hLOG) fvsCtrl_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define fvsCtrl_print(p, pfx,hLOG) fvsCtrl_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: fvsCtrl
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE fvsReg (4,4)
/// ###
/// * Define the fvs Regbase
/// ###
/// # # ----------------------------------------------------------
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 0B, bits: 0b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_fvsReg
#define h_fvsReg (){}
typedef struct SIE_fvsReg
{
} SIE_fvsReg;
#endif
//////
/// ENDOFINTERFACE: fvsReg
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE AVSReg (4,4)
/// ###
/// * All the controls for Adaptive Voltage Scaling (AVS)
/// ###
/// # # ----------------------------------------------------------
/// @ 0x00000 CTRL0 (P)
/// ###
/// * AVS Control Register 0
/// ###
/// %unsigned 1 avs_sw_rstn 0x1
/// ###
/// * Software reset signal for AVS
/// * 1: Not Asserted
/// * 0: Asserted
/// ###
/// %unsigned 1 min_max_val_rst 0x0
/// ###
/// * Reset value for the following signals:
/// * max_dro_count, min_dro_count, max_avs_delta, max_avs_delta.
/// * 0: Normal operation
/// * 1: Reset the above signals
/// ###
/// %unsigned 1 en_avdd_det 0x1
/// ###
/// * Enable the detection of AVDD power down. When enabled, the AVS will be disabled once AVDD drops below a present threshold.
/// * 0: avdd power down detection is disabled
/// * 1: avdd power down detection is enabled.
/// ###
/// %unsigned 1 enable 0x0
/// ###
/// * Enable the AVS mechanism and controls power consumption
/// * 1'b0: AVS is off, vddfb floats
/// * 1'b1: AVS is on, vddfb is driven
/// * During constant operation mode, after reset sequence has ended, AVS will start its functional operation 150 clock cycles after enable has been asserted
/// ###
/// %unsigned 1 avs_pause 0x0
/// ###
/// * Causes AVS to “pause”
/// * 0: Normal operation mode
/// * 1: Keep last avs_delta values. vddfb follow vdd level + delta level.
/// ###
/// %unsigned 1 manual 0x0
/// ###
/// * Manual setting of delta voltage (open loop control)
/// * 0: Auto operation
/// * 1: Manual operation
/// * For debug mode, change manual to 1'b0 at least 50000 cycles(2ms in 25MHz clock after enable is asserted)
/// * Manual must be set to 1'b0 during powerup
/// ###
/// %unsigned 8 manual_delta 0x80
/// ###
/// * Manual setting for delta voltage. This value is effective while manual = 1'b1
/// ###
/// %unsigned 1 vsense_sel 0x0
/// ###
/// * Select between avs_vdd_sense0 and avs_vdd_sense1
/// * 1'b1 => avs_vdd_sense0 is selected
/// * 1'b0 => avs_vdd_sense1 is selected
/// ###
/// %unsigned 2 vt_sel 0x0
/// ###
/// * Select dro
/// * 2'b00 => NVT(SZD), 2'b01 => LVT, 2'b10 => NLVT(LND)
/// * 2'b11 => reserved
/// ###
/// %% 15 # Stuffing bits...
/// @ 0x00004 CTRL1 (P)
/// ###
/// * AVS Control Register 1
/// ###
/// %unsigned 6 low_vdd_limit 0x0
/// ###
/// * (Step Number * Step) + Min Limit
/// * Step~12mv, Min Limit = 747mv
/// * Please refer to VDD limits table in SPEC
/// ###
/// %unsigned 6 high_vdd_limit 0x33
/// ###
/// * (Step Number * Step) + Min Limit
/// * Step~12mv, Min Limit = 747mv
/// * Please refer to VDD limits table in SPEC
/// ###
/// %unsigned 3 div_cal 0x3
/// ###
/// * Adjust internal voltage divider
/// ###
/// %unsigned 2 bg_trim 0x2
/// ###
/// * Adjusting internal reference voltage by 18mV intervals.
/// * 2'b00: +36mv
/// * 2'b01: +18mV change
/// * 2'b10: 0mV change
/// * 2'b11: -18mV change
/// ###
/// %unsigned 3 bg_cfg 0x4
/// ###
/// * Configurable bits which change the temperature curves of the Band-Gap circuit
/// ###
/// %unsigned 4 tp_cfg 0x0
/// ###
/// * Analog test point selection control
/// * 0000: High-Z
/// * 0001: avs_vdd_sense0
/// * 0010: BG output
/// * 0011: PORST VDD input
/// * 0100: avs_vdd_sense1
/// * 0101: vdd limit
/// * 0110: output buffer enable
/// * 0111: Not connected
/// * 1000: FW voltage
/// * 1001: current gen amp_out
/// * 1010: ana_enable_h
/// * 1011: Not connected
/// * 1100: porst enable
/// * 1101: porst_rst_b
/// * 1110: Not connected
/// * 1111: avdd_detection threshold
/// ###
/// %unsigned 3 avg 0x0
/// ###
/// * Average DRO readout for
/// * 3'b000: 1
/// * 3'b001: 2
/// * …
/// * 3'b111: 128
/// ###
/// %% 5 # Stuffing bits...
/// @ 0x00008 CTRL2 (P)
/// ###
/// * AVS Control Register 2
/// ###
/// %unsigned 16 speed_target 0x0
/// ###
/// * Target DRO Readout. The AVS IP will control the voltage to achieve this DRO readout(unless voltage cross high or low limits)
/// ###
/// %unsigned 16 dro_count_interval 0x1DD
/// ###
/// * Number of clk cycles for which the DRO is enabled
/// ###
/// @ 0x0000C CTRL3 (P)
/// ###
/// * AVS Control Register 3
/// ###
/// %unsigned 4 offset_discharge_rate 0x2
/// ###
/// * Define the AVS discharge rate (in number of clk cycles between AVS steps) during power down which is caused by AVDD fall. This value is valid only if en_avdd_det = 1'b1
/// ###
/// %unsigned 6 bg_cal_ext 0x20
/// ###
/// * 6 external bit to be configured for manual band-gap calibration
/// ###
/// %unsigned 1 bg_cal_man 0x0
/// ###
/// * When this bit is high, Bandag calibration machine is disabled and calibration value is taken externally via bg_cal_ext[5:0]
/// ###
/// %unsigned 1 fast_voltage_change_trigger 0x0
/// ###
/// * Edge triggered (both sides), indicating to start travel to the new voltage defined in target_delta[7:0]. Minimum time between successive edge is 2 AVS clk cycle
/// * To be asserted not less than 150 cycles after enable is asserted
/// ###
/// %unsigned 10 voltage_change_rate 0x1E1
/// ###
/// * Defines the voltage change rate (in number of clk cycles between AVS steps) when fast_voltage_change_trigger input change. This value is also used for discharging the AVS delta when the enable input changes 1'b1 -> 1'b0
/// * Must be valid when fast_volatege_change_trigger is asserted and not change for 5 cycles(AVS clock)
/// ###
/// %unsigned 8 target_delta 0x80
/// ###
/// * Specifies the new offset/delta to travel to when fast_voltage_change_trigger input change
/// * Must be valid when fast_volatege_change_trigger is asserted and not change for 5 cyclse(AVS clock)
/// ###
/// %% 2 # Stuffing bits...
/// @ 0x00010 CTRL4 (P)
/// ###
/// * AVS Control Register 4
/// ###
/// %unsigned 1 master 0x1
/// ###
/// * Define whether the AVS should behave as master or slave.
/// * 1'b0 – slave
/// * 1'b1 – master
/// * If no Master/Slave option is uesd, AVS must be defined as master and in_slave_avs_voltage_up must be set to 1'b0
/// ###
/// %unsigned 1 in_slave_avs_voltage_up 0x0
/// ###
/// * Indication from Slave AVS, whether to increase or decrease AS delta.
/// * 1'b0: Decrease voltage
/// * 1'b1: Increase voltage
/// * If no Master/Slave option is used, AVS should be defined as master and in_slave_avs_voltage_up must be set to 1'b0
/// ###
/// %unsigned 1 inc_offset_range 0x0
/// ###
/// * Increase AVS offset range to +/-325mV (min/max)
/// * Default is +/- 200 mV
/// ###
/// %unsigned 4 driver_bias_cfg 0xF
/// ###
/// * Control output drive power and driving strength
/// * 4'b0000 → min strength
/// * 4'b1111 → max strength
/// ###
/// %unsigned 3 avs_porst_out_sel 0x0
/// ###
/// * Select the avs_porst_out_b pins
/// * 3'b000: avs_porst_rst_out_b[0]
/// * 3'b001: avs_porst_rst_out_b[1]
/// * 3'b002: avs_porst_rst_out_b[2]
/// * 3'b003: avs_porst_rst_out_b[3]
/// * 3'b004: avs_porst_rst_out_b[4]
/// * 3'b005: avs_porst_rst_out_b[5]
/// * Other values are reserved
/// ###
/// %% 22 # Stuffing bits...
/// @ 0x00014 MiscStatus (R-)
/// ###
/// * Miscellaneous Status
/// ###
/// %unsigned 1 out_slave_avs_voltage_up 0x0
/// %unsigned 1 above_limit 0x0
/// %unsigned 1 below_limit 0x0
/// %unsigned 1 above_limit_sticky 0x0
/// %unsigned 1 below_limit_sticky 0x0
/// %unsigned 6 bg_cal_value 0x0
/// %unsigned 1 fast_travel_indication 0x0
/// ###
/// * Indicates when AVS is performing fast travel operation.
/// * 1'b0 – AVS is not in fast travel or fast travel operation has ended
/// * 1'b1 – AVS is performing fast travel operation
/// * During fast travel (in case of two or more consecutive triggers, it will go low ONLY after the last travel is completed)
/// ###
/// %% 20 # Stuffing bits...
/// @ 0x00018 DROStatus (R-)
/// ###
/// * DRO Status
/// ###
/// %unsigned 16 inter_dro_count 0x0
/// ###
/// * Intermediate DRO count value
/// ###
/// %unsigned 8 avs_delta 0x0
/// ###
/// * Delta control status
/// ###
/// %% 8 # Stuffing bits...
/// @ 0x0001C DROMinMax (R-)
/// ###
/// * Statistics of dro_count
/// ###
/// %unsigned 16 max_dro_count 0x0
/// ###
/// * Max dro count after initiating min_max_val_rst
/// ###
/// %unsigned 16 min_dro_count 0x0
/// ###
/// * Min dro count after initiating min_max_val_rst
/// ###
/// @ 0x00020 AVSMinMax (R-)
/// ###
/// * Statistics of avs_delta
/// ###
/// %unsigned 16 max_avs_delta 0x0
/// ###
/// * Max avs_delta after initiating min_max_val_rst
/// ###
/// %unsigned 16 min_avs_delta 0x0
/// ###
/// * Min avs_delta after initiating min_max_val_rst
/// ###
/// @ 0x00024 dummy (P)
/// %unsigned 32 dummy 0x0
/// ###
/// * Not used. May be used for ECO
/// ###
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 40B, bits: 248b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_AVSReg
#define h_AVSReg (){}
#define RA_AVSReg_CTRL0 0x0000
#define BA_AVSReg_CTRL0_avs_sw_rstn 0x0000
#define B16AVSReg_CTRL0_avs_sw_rstn 0x0000
#define LSb32AVSReg_CTRL0_avs_sw_rstn 0
#define LSb16AVSReg_CTRL0_avs_sw_rstn 0
#define bAVSReg_CTRL0_avs_sw_rstn 1
#define MSK32AVSReg_CTRL0_avs_sw_rstn 0x00000001
#define BA_AVSReg_CTRL0_min_max_val_rst 0x0000
#define B16AVSReg_CTRL0_min_max_val_rst 0x0000
#define LSb32AVSReg_CTRL0_min_max_val_rst 1
#define LSb16AVSReg_CTRL0_min_max_val_rst 1
#define bAVSReg_CTRL0_min_max_val_rst 1
#define MSK32AVSReg_CTRL0_min_max_val_rst 0x00000002
#define BA_AVSReg_CTRL0_en_avdd_det 0x0000
#define B16AVSReg_CTRL0_en_avdd_det 0x0000
#define LSb32AVSReg_CTRL0_en_avdd_det 2
#define LSb16AVSReg_CTRL0_en_avdd_det 2
#define bAVSReg_CTRL0_en_avdd_det 1
#define MSK32AVSReg_CTRL0_en_avdd_det 0x00000004
#define BA_AVSReg_CTRL0_enable 0x0000
#define B16AVSReg_CTRL0_enable 0x0000
#define LSb32AVSReg_CTRL0_enable 3
#define LSb16AVSReg_CTRL0_enable 3
#define bAVSReg_CTRL0_enable 1
#define MSK32AVSReg_CTRL0_enable 0x00000008
#define BA_AVSReg_CTRL0_avs_pause 0x0000
#define B16AVSReg_CTRL0_avs_pause 0x0000
#define LSb32AVSReg_CTRL0_avs_pause 4
#define LSb16AVSReg_CTRL0_avs_pause 4
#define bAVSReg_CTRL0_avs_pause 1
#define MSK32AVSReg_CTRL0_avs_pause 0x00000010
#define BA_AVSReg_CTRL0_manual 0x0000
#define B16AVSReg_CTRL0_manual 0x0000
#define LSb32AVSReg_CTRL0_manual 5
#define LSb16AVSReg_CTRL0_manual 5
#define bAVSReg_CTRL0_manual 1
#define MSK32AVSReg_CTRL0_manual 0x00000020
#define BA_AVSReg_CTRL0_manual_delta 0x0000
#define B16AVSReg_CTRL0_manual_delta 0x0000
#define LSb32AVSReg_CTRL0_manual_delta 6
#define LSb16AVSReg_CTRL0_manual_delta 6
#define bAVSReg_CTRL0_manual_delta 8
#define MSK32AVSReg_CTRL0_manual_delta 0x00003FC0
#define BA_AVSReg_CTRL0_vsense_sel 0x0001
#define B16AVSReg_CTRL0_vsense_sel 0x0000
#define LSb32AVSReg_CTRL0_vsense_sel 14
#define LSb16AVSReg_CTRL0_vsense_sel 14
#define bAVSReg_CTRL0_vsense_sel 1
#define MSK32AVSReg_CTRL0_vsense_sel 0x00004000
#define BA_AVSReg_CTRL0_vt_sel 0x0001
#define B16AVSReg_CTRL0_vt_sel 0x0000
#define LSb32AVSReg_CTRL0_vt_sel 15
#define LSb16AVSReg_CTRL0_vt_sel 15
#define bAVSReg_CTRL0_vt_sel 2
#define MSK32AVSReg_CTRL0_vt_sel 0x00018000
///////////////////////////////////////////////////////////
#define RA_AVSReg_CTRL1 0x0004
#define BA_AVSReg_CTRL1_low_vdd_limit 0x0004
#define B16AVSReg_CTRL1_low_vdd_limit 0x0004
#define LSb32AVSReg_CTRL1_low_vdd_limit 0
#define LSb16AVSReg_CTRL1_low_vdd_limit 0
#define bAVSReg_CTRL1_low_vdd_limit 6
#define MSK32AVSReg_CTRL1_low_vdd_limit 0x0000003F
#define BA_AVSReg_CTRL1_high_vdd_limit 0x0004
#define B16AVSReg_CTRL1_high_vdd_limit 0x0004
#define LSb32AVSReg_CTRL1_high_vdd_limit 6
#define LSb16AVSReg_CTRL1_high_vdd_limit 6
#define bAVSReg_CTRL1_high_vdd_limit 6
#define MSK32AVSReg_CTRL1_high_vdd_limit 0x00000FC0
#define BA_AVSReg_CTRL1_div_cal 0x0005
#define B16AVSReg_CTRL1_div_cal 0x0004
#define LSb32AVSReg_CTRL1_div_cal 12
#define LSb16AVSReg_CTRL1_div_cal 12
#define bAVSReg_CTRL1_div_cal 3
#define MSK32AVSReg_CTRL1_div_cal 0x00007000
#define BA_AVSReg_CTRL1_bg_trim 0x0005
#define B16AVSReg_CTRL1_bg_trim 0x0004
#define LSb32AVSReg_CTRL1_bg_trim 15
#define LSb16AVSReg_CTRL1_bg_trim 15
#define bAVSReg_CTRL1_bg_trim 2
#define MSK32AVSReg_CTRL1_bg_trim 0x00018000
#define BA_AVSReg_CTRL1_bg_cfg 0x0006
#define B16AVSReg_CTRL1_bg_cfg 0x0006
#define LSb32AVSReg_CTRL1_bg_cfg 17
#define LSb16AVSReg_CTRL1_bg_cfg 1
#define bAVSReg_CTRL1_bg_cfg 3
#define MSK32AVSReg_CTRL1_bg_cfg 0x000E0000
#define BA_AVSReg_CTRL1_tp_cfg 0x0006
#define B16AVSReg_CTRL1_tp_cfg 0x0006
#define LSb32AVSReg_CTRL1_tp_cfg 20
#define LSb16AVSReg_CTRL1_tp_cfg 4
#define bAVSReg_CTRL1_tp_cfg 4
#define MSK32AVSReg_CTRL1_tp_cfg 0x00F00000
#define BA_AVSReg_CTRL1_avg 0x0007
#define B16AVSReg_CTRL1_avg 0x0006
#define LSb32AVSReg_CTRL1_avg 24
#define LSb16AVSReg_CTRL1_avg 8
#define bAVSReg_CTRL1_avg 3
#define MSK32AVSReg_CTRL1_avg 0x07000000
///////////////////////////////////////////////////////////
#define RA_AVSReg_CTRL2 0x0008
#define BA_AVSReg_CTRL2_speed_target 0x0008
#define B16AVSReg_CTRL2_speed_target 0x0008
#define LSb32AVSReg_CTRL2_speed_target 0
#define LSb16AVSReg_CTRL2_speed_target 0
#define bAVSReg_CTRL2_speed_target 16
#define MSK32AVSReg_CTRL2_speed_target 0x0000FFFF
#define BA_AVSReg_CTRL2_dro_count_interval 0x000A
#define B16AVSReg_CTRL2_dro_count_interval 0x000A
#define LSb32AVSReg_CTRL2_dro_count_interval 16
#define LSb16AVSReg_CTRL2_dro_count_interval 0
#define bAVSReg_CTRL2_dro_count_interval 16
#define MSK32AVSReg_CTRL2_dro_count_interval 0xFFFF0000
///////////////////////////////////////////////////////////
#define RA_AVSReg_CTRL3 0x000C
#define BA_AVSReg_CTRL3_offset_discharge_rate 0x000C
#define B16AVSReg_CTRL3_offset_discharge_rate 0x000C
#define LSb32AVSReg_CTRL3_offset_discharge_rate 0
#define LSb16AVSReg_CTRL3_offset_discharge_rate 0
#define bAVSReg_CTRL3_offset_discharge_rate 4
#define MSK32AVSReg_CTRL3_offset_discharge_rate 0x0000000F
#define BA_AVSReg_CTRL3_bg_cal_ext 0x000C
#define B16AVSReg_CTRL3_bg_cal_ext 0x000C
#define LSb32AVSReg_CTRL3_bg_cal_ext 4
#define LSb16AVSReg_CTRL3_bg_cal_ext 4
#define bAVSReg_CTRL3_bg_cal_ext 6
#define MSK32AVSReg_CTRL3_bg_cal_ext 0x000003F0
#define BA_AVSReg_CTRL3_bg_cal_man 0x000D
#define B16AVSReg_CTRL3_bg_cal_man 0x000C
#define LSb32AVSReg_CTRL3_bg_cal_man 10
#define LSb16AVSReg_CTRL3_bg_cal_man 10
#define bAVSReg_CTRL3_bg_cal_man 1
#define MSK32AVSReg_CTRL3_bg_cal_man 0x00000400
#define BA_AVSReg_CTRL3_fast_voltage_change_trigger 0x000D
#define B16AVSReg_CTRL3_fast_voltage_change_trigger 0x000C
#define LSb32AVSReg_CTRL3_fast_voltage_change_trigger 11
#define LSb16AVSReg_CTRL3_fast_voltage_change_trigger 11
#define bAVSReg_CTRL3_fast_voltage_change_trigger 1
#define MSK32AVSReg_CTRL3_fast_voltage_change_trigger 0x00000800
#define BA_AVSReg_CTRL3_voltage_change_rate 0x000D
#define B16AVSReg_CTRL3_voltage_change_rate 0x000C
#define LSb32AVSReg_CTRL3_voltage_change_rate 12
#define LSb16AVSReg_CTRL3_voltage_change_rate 12
#define bAVSReg_CTRL3_voltage_change_rate 10
#define MSK32AVSReg_CTRL3_voltage_change_rate 0x003FF000
#define BA_AVSReg_CTRL3_target_delta 0x000E
#define B16AVSReg_CTRL3_target_delta 0x000E
#define LSb32AVSReg_CTRL3_target_delta 22
#define LSb16AVSReg_CTRL3_target_delta 6
#define bAVSReg_CTRL3_target_delta 8
#define MSK32AVSReg_CTRL3_target_delta 0x3FC00000
///////////////////////////////////////////////////////////
#define RA_AVSReg_CTRL4 0x0010
#define BA_AVSReg_CTRL4_master 0x0010
#define B16AVSReg_CTRL4_master 0x0010
#define LSb32AVSReg_CTRL4_master 0
#define LSb16AVSReg_CTRL4_master 0
#define bAVSReg_CTRL4_master 1
#define MSK32AVSReg_CTRL4_master 0x00000001
#define BA_AVSReg_CTRL4_in_slave_avs_voltage_up 0x0010
#define B16AVSReg_CTRL4_in_slave_avs_voltage_up 0x0010
#define LSb32AVSReg_CTRL4_in_slave_avs_voltage_up 1
#define LSb16AVSReg_CTRL4_in_slave_avs_voltage_up 1
#define bAVSReg_CTRL4_in_slave_avs_voltage_up 1
#define MSK32AVSReg_CTRL4_in_slave_avs_voltage_up 0x00000002
#define BA_AVSReg_CTRL4_inc_offset_range 0x0010
#define B16AVSReg_CTRL4_inc_offset_range 0x0010
#define LSb32AVSReg_CTRL4_inc_offset_range 2
#define LSb16AVSReg_CTRL4_inc_offset_range 2
#define bAVSReg_CTRL4_inc_offset_range 1
#define MSK32AVSReg_CTRL4_inc_offset_range 0x00000004
#define BA_AVSReg_CTRL4_driver_bias_cfg 0x0010
#define B16AVSReg_CTRL4_driver_bias_cfg 0x0010
#define LSb32AVSReg_CTRL4_driver_bias_cfg 3
#define LSb16AVSReg_CTRL4_driver_bias_cfg 3
#define bAVSReg_CTRL4_driver_bias_cfg 4
#define MSK32AVSReg_CTRL4_driver_bias_cfg 0x00000078
#define BA_AVSReg_CTRL4_avs_porst_out_sel 0x0010
#define B16AVSReg_CTRL4_avs_porst_out_sel 0x0010
#define LSb32AVSReg_CTRL4_avs_porst_out_sel 7
#define LSb16AVSReg_CTRL4_avs_porst_out_sel 7
#define bAVSReg_CTRL4_avs_porst_out_sel 3
#define MSK32AVSReg_CTRL4_avs_porst_out_sel 0x00000380
///////////////////////////////////////////////////////////
#define RA_AVSReg_MiscStatus 0x0014
#define BA_AVSReg_MiscStatus_out_slave_avs_voltage_up 0x0014
#define B16AVSReg_MiscStatus_out_slave_avs_voltage_up 0x0014
#define LSb32AVSReg_MiscStatus_out_slave_avs_voltage_up 0
#define LSb16AVSReg_MiscStatus_out_slave_avs_voltage_up 0
#define bAVSReg_MiscStatus_out_slave_avs_voltage_up 1
#define MSK32AVSReg_MiscStatus_out_slave_avs_voltage_up 0x00000001
#define BA_AVSReg_MiscStatus_above_limit 0x0014
#define B16AVSReg_MiscStatus_above_limit 0x0014
#define LSb32AVSReg_MiscStatus_above_limit 1
#define LSb16AVSReg_MiscStatus_above_limit 1
#define bAVSReg_MiscStatus_above_limit 1
#define MSK32AVSReg_MiscStatus_above_limit 0x00000002
#define BA_AVSReg_MiscStatus_below_limit 0x0014
#define B16AVSReg_MiscStatus_below_limit 0x0014
#define LSb32AVSReg_MiscStatus_below_limit 2
#define LSb16AVSReg_MiscStatus_below_limit 2
#define bAVSReg_MiscStatus_below_limit 1
#define MSK32AVSReg_MiscStatus_below_limit 0x00000004
#define BA_AVSReg_MiscStatus_above_limit_sticky 0x0014
#define B16AVSReg_MiscStatus_above_limit_sticky 0x0014
#define LSb32AVSReg_MiscStatus_above_limit_sticky 3
#define LSb16AVSReg_MiscStatus_above_limit_sticky 3
#define bAVSReg_MiscStatus_above_limit_sticky 1
#define MSK32AVSReg_MiscStatus_above_limit_sticky 0x00000008
#define BA_AVSReg_MiscStatus_below_limit_sticky 0x0014
#define B16AVSReg_MiscStatus_below_limit_sticky 0x0014
#define LSb32AVSReg_MiscStatus_below_limit_sticky 4
#define LSb16AVSReg_MiscStatus_below_limit_sticky 4
#define bAVSReg_MiscStatus_below_limit_sticky 1
#define MSK32AVSReg_MiscStatus_below_limit_sticky 0x00000010
#define BA_AVSReg_MiscStatus_bg_cal_value 0x0014
#define B16AVSReg_MiscStatus_bg_cal_value 0x0014
#define LSb32AVSReg_MiscStatus_bg_cal_value 5
#define LSb16AVSReg_MiscStatus_bg_cal_value 5
#define bAVSReg_MiscStatus_bg_cal_value 6
#define MSK32AVSReg_MiscStatus_bg_cal_value 0x000007E0
#define BA_AVSReg_MiscStatus_fast_travel_indication 0x0015
#define B16AVSReg_MiscStatus_fast_travel_indication 0x0014
#define LSb32AVSReg_MiscStatus_fast_travel_indication 11
#define LSb16AVSReg_MiscStatus_fast_travel_indication 11
#define bAVSReg_MiscStatus_fast_travel_indication 1
#define MSK32AVSReg_MiscStatus_fast_travel_indication 0x00000800
///////////////////////////////////////////////////////////
#define RA_AVSReg_DROStatus 0x0018
#define BA_AVSReg_DROStatus_inter_dro_count 0x0018
#define B16AVSReg_DROStatus_inter_dro_count 0x0018
#define LSb32AVSReg_DROStatus_inter_dro_count 0
#define LSb16AVSReg_DROStatus_inter_dro_count 0
#define bAVSReg_DROStatus_inter_dro_count 16
#define MSK32AVSReg_DROStatus_inter_dro_count 0x0000FFFF
#define BA_AVSReg_DROStatus_avs_delta 0x001A
#define B16AVSReg_DROStatus_avs_delta 0x001A
#define LSb32AVSReg_DROStatus_avs_delta 16
#define LSb16AVSReg_DROStatus_avs_delta 0
#define bAVSReg_DROStatus_avs_delta 8
#define MSK32AVSReg_DROStatus_avs_delta 0x00FF0000
///////////////////////////////////////////////////////////
#define RA_AVSReg_DROMinMax 0x001C
#define BA_AVSReg_DROMinMax_max_dro_count 0x001C
#define B16AVSReg_DROMinMax_max_dro_count 0x001C
#define LSb32AVSReg_DROMinMax_max_dro_count 0
#define LSb16AVSReg_DROMinMax_max_dro_count 0
#define bAVSReg_DROMinMax_max_dro_count 16
#define MSK32AVSReg_DROMinMax_max_dro_count 0x0000FFFF
#define BA_AVSReg_DROMinMax_min_dro_count 0x001E
#define B16AVSReg_DROMinMax_min_dro_count 0x001E
#define LSb32AVSReg_DROMinMax_min_dro_count 16
#define LSb16AVSReg_DROMinMax_min_dro_count 0
#define bAVSReg_DROMinMax_min_dro_count 16
#define MSK32AVSReg_DROMinMax_min_dro_count 0xFFFF0000
///////////////////////////////////////////////////////////
#define RA_AVSReg_AVSMinMax 0x0020
#define BA_AVSReg_AVSMinMax_max_avs_delta 0x0020
#define B16AVSReg_AVSMinMax_max_avs_delta 0x0020
#define LSb32AVSReg_AVSMinMax_max_avs_delta 0
#define LSb16AVSReg_AVSMinMax_max_avs_delta 0
#define bAVSReg_AVSMinMax_max_avs_delta 16
#define MSK32AVSReg_AVSMinMax_max_avs_delta 0x0000FFFF
#define BA_AVSReg_AVSMinMax_min_avs_delta 0x0022
#define B16AVSReg_AVSMinMax_min_avs_delta 0x0022
#define LSb32AVSReg_AVSMinMax_min_avs_delta 16
#define LSb16AVSReg_AVSMinMax_min_avs_delta 0
#define bAVSReg_AVSMinMax_min_avs_delta 16
#define MSK32AVSReg_AVSMinMax_min_avs_delta 0xFFFF0000
///////////////////////////////////////////////////////////
#define RA_AVSReg_dummy 0x0024
#define BA_AVSReg_dummy_dummy 0x0024
#define B16AVSReg_dummy_dummy 0x0024
#define LSb32AVSReg_dummy_dummy 0
#define LSb16AVSReg_dummy_dummy 0
#define bAVSReg_dummy_dummy 32
#define MSK32AVSReg_dummy_dummy 0xFFFFFFFF
///////////////////////////////////////////////////////////
typedef struct SIE_AVSReg {
///////////////////////////////////////////////////////////
#define GET32AVSReg_CTRL0_avs_sw_rstn(r32) _BFGET_(r32, 0, 0)
#define SET32AVSReg_CTRL0_avs_sw_rstn(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16AVSReg_CTRL0_avs_sw_rstn(r16) _BFGET_(r16, 0, 0)
#define SET16AVSReg_CTRL0_avs_sw_rstn(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32AVSReg_CTRL0_min_max_val_rst(r32) _BFGET_(r32, 1, 1)
#define SET32AVSReg_CTRL0_min_max_val_rst(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16AVSReg_CTRL0_min_max_val_rst(r16) _BFGET_(r16, 1, 1)
#define SET16AVSReg_CTRL0_min_max_val_rst(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32AVSReg_CTRL0_en_avdd_det(r32) _BFGET_(r32, 2, 2)
#define SET32AVSReg_CTRL0_en_avdd_det(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16AVSReg_CTRL0_en_avdd_det(r16) _BFGET_(r16, 2, 2)
#define SET16AVSReg_CTRL0_en_avdd_det(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32AVSReg_CTRL0_enable(r32) _BFGET_(r32, 3, 3)
#define SET32AVSReg_CTRL0_enable(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16AVSReg_CTRL0_enable(r16) _BFGET_(r16, 3, 3)
#define SET16AVSReg_CTRL0_enable(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32AVSReg_CTRL0_avs_pause(r32) _BFGET_(r32, 4, 4)
#define SET32AVSReg_CTRL0_avs_pause(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16AVSReg_CTRL0_avs_pause(r16) _BFGET_(r16, 4, 4)
#define SET16AVSReg_CTRL0_avs_pause(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32AVSReg_CTRL0_manual(r32) _BFGET_(r32, 5, 5)
#define SET32AVSReg_CTRL0_manual(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16AVSReg_CTRL0_manual(r16) _BFGET_(r16, 5, 5)
#define SET16AVSReg_CTRL0_manual(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32AVSReg_CTRL0_manual_delta(r32) _BFGET_(r32,13, 6)
#define SET32AVSReg_CTRL0_manual_delta(r32,v) _BFSET_(r32,13, 6,v)
#define GET16AVSReg_CTRL0_manual_delta(r16) _BFGET_(r16,13, 6)
#define SET16AVSReg_CTRL0_manual_delta(r16,v) _BFSET_(r16,13, 6,v)
#define GET32AVSReg_CTRL0_vsense_sel(r32) _BFGET_(r32,14,14)
#define SET32AVSReg_CTRL0_vsense_sel(r32,v) _BFSET_(r32,14,14,v)
#define GET16AVSReg_CTRL0_vsense_sel(r16) _BFGET_(r16,14,14)
#define SET16AVSReg_CTRL0_vsense_sel(r16,v) _BFSET_(r16,14,14,v)
#define GET32AVSReg_CTRL0_vt_sel(r32) _BFGET_(r32,16,15)
#define SET32AVSReg_CTRL0_vt_sel(r32,v) _BFSET_(r32,16,15,v)
#define w32AVSReg_CTRL0 {\
UNSG32 uCTRL0_avs_sw_rstn : 1;\
UNSG32 uCTRL0_min_max_val_rst : 1;\
UNSG32 uCTRL0_en_avdd_det : 1;\
UNSG32 uCTRL0_enable : 1;\
UNSG32 uCTRL0_avs_pause : 1;\
UNSG32 uCTRL0_manual : 1;\
UNSG32 uCTRL0_manual_delta : 8;\
UNSG32 uCTRL0_vsense_sel : 1;\
UNSG32 uCTRL0_vt_sel : 2;\
UNSG32 RSVDx0_b17 : 15;\
}
union { UNSG32 u32AVSReg_CTRL0;
struct w32AVSReg_CTRL0;
};
///////////////////////////////////////////////////////////
#define GET32AVSReg_CTRL1_low_vdd_limit(r32) _BFGET_(r32, 5, 0)
#define SET32AVSReg_CTRL1_low_vdd_limit(r32,v) _BFSET_(r32, 5, 0,v)
#define GET16AVSReg_CTRL1_low_vdd_limit(r16) _BFGET_(r16, 5, 0)
#define SET16AVSReg_CTRL1_low_vdd_limit(r16,v) _BFSET_(r16, 5, 0,v)
#define GET32AVSReg_CTRL1_high_vdd_limit(r32) _BFGET_(r32,11, 6)
#define SET32AVSReg_CTRL1_high_vdd_limit(r32,v) _BFSET_(r32,11, 6,v)
#define GET16AVSReg_CTRL1_high_vdd_limit(r16) _BFGET_(r16,11, 6)
#define SET16AVSReg_CTRL1_high_vdd_limit(r16,v) _BFSET_(r16,11, 6,v)
#define GET32AVSReg_CTRL1_div_cal(r32) _BFGET_(r32,14,12)
#define SET32AVSReg_CTRL1_div_cal(r32,v) _BFSET_(r32,14,12,v)
#define GET16AVSReg_CTRL1_div_cal(r16) _BFGET_(r16,14,12)
#define SET16AVSReg_CTRL1_div_cal(r16,v) _BFSET_(r16,14,12,v)
#define GET32AVSReg_CTRL1_bg_trim(r32) _BFGET_(r32,16,15)
#define SET32AVSReg_CTRL1_bg_trim(r32,v) _BFSET_(r32,16,15,v)
#define GET32AVSReg_CTRL1_bg_cfg(r32) _BFGET_(r32,19,17)
#define SET32AVSReg_CTRL1_bg_cfg(r32,v) _BFSET_(r32,19,17,v)
#define GET16AVSReg_CTRL1_bg_cfg(r16) _BFGET_(r16, 3, 1)
#define SET16AVSReg_CTRL1_bg_cfg(r16,v) _BFSET_(r16, 3, 1,v)
#define GET32AVSReg_CTRL1_tp_cfg(r32) _BFGET_(r32,23,20)
#define SET32AVSReg_CTRL1_tp_cfg(r32,v) _BFSET_(r32,23,20,v)
#define GET16AVSReg_CTRL1_tp_cfg(r16) _BFGET_(r16, 7, 4)
#define SET16AVSReg_CTRL1_tp_cfg(r16,v) _BFSET_(r16, 7, 4,v)
#define GET32AVSReg_CTRL1_avg(r32) _BFGET_(r32,26,24)
#define SET32AVSReg_CTRL1_avg(r32,v) _BFSET_(r32,26,24,v)
#define GET16AVSReg_CTRL1_avg(r16) _BFGET_(r16,10, 8)
#define SET16AVSReg_CTRL1_avg(r16,v) _BFSET_(r16,10, 8,v)
#define w32AVSReg_CTRL1 {\
UNSG32 uCTRL1_low_vdd_limit : 6;\
UNSG32 uCTRL1_high_vdd_limit : 6;\
UNSG32 uCTRL1_div_cal : 3;\
UNSG32 uCTRL1_bg_trim : 2;\
UNSG32 uCTRL1_bg_cfg : 3;\
UNSG32 uCTRL1_tp_cfg : 4;\
UNSG32 uCTRL1_avg : 3;\
UNSG32 RSVDx4_b27 : 5;\
}
union { UNSG32 u32AVSReg_CTRL1;
struct w32AVSReg_CTRL1;
};
///////////////////////////////////////////////////////////
#define GET32AVSReg_CTRL2_speed_target(r32) _BFGET_(r32,15, 0)
#define SET32AVSReg_CTRL2_speed_target(r32,v) _BFSET_(r32,15, 0,v)
#define GET16AVSReg_CTRL2_speed_target(r16) _BFGET_(r16,15, 0)
#define SET16AVSReg_CTRL2_speed_target(r16,v) _BFSET_(r16,15, 0,v)
#define GET32AVSReg_CTRL2_dro_count_interval(r32) _BFGET_(r32,31,16)
#define SET32AVSReg_CTRL2_dro_count_interval(r32,v) _BFSET_(r32,31,16,v)
#define GET16AVSReg_CTRL2_dro_count_interval(r16) _BFGET_(r16,15, 0)
#define SET16AVSReg_CTRL2_dro_count_interval(r16,v) _BFSET_(r16,15, 0,v)
#define w32AVSReg_CTRL2 {\
UNSG32 uCTRL2_speed_target : 16;\
UNSG32 uCTRL2_dro_count_interval : 16;\
}
union { UNSG32 u32AVSReg_CTRL2;
struct w32AVSReg_CTRL2;
};
///////////////////////////////////////////////////////////
#define GET32AVSReg_CTRL3_offset_discharge_rate(r32) _BFGET_(r32, 3, 0)
#define SET32AVSReg_CTRL3_offset_discharge_rate(r32,v) _BFSET_(r32, 3, 0,v)
#define GET16AVSReg_CTRL3_offset_discharge_rate(r16) _BFGET_(r16, 3, 0)
#define SET16AVSReg_CTRL3_offset_discharge_rate(r16,v) _BFSET_(r16, 3, 0,v)
#define GET32AVSReg_CTRL3_bg_cal_ext(r32) _BFGET_(r32, 9, 4)
#define SET32AVSReg_CTRL3_bg_cal_ext(r32,v) _BFSET_(r32, 9, 4,v)
#define GET16AVSReg_CTRL3_bg_cal_ext(r16) _BFGET_(r16, 9, 4)
#define SET16AVSReg_CTRL3_bg_cal_ext(r16,v) _BFSET_(r16, 9, 4,v)
#define GET32AVSReg_CTRL3_bg_cal_man(r32) _BFGET_(r32,10,10)
#define SET32AVSReg_CTRL3_bg_cal_man(r32,v) _BFSET_(r32,10,10,v)
#define GET16AVSReg_CTRL3_bg_cal_man(r16) _BFGET_(r16,10,10)
#define SET16AVSReg_CTRL3_bg_cal_man(r16,v) _BFSET_(r16,10,10,v)
#define GET32AVSReg_CTRL3_fast_voltage_change_trigger(r32) _BFGET_(r32,11,11)
#define SET32AVSReg_CTRL3_fast_voltage_change_trigger(r32,v) _BFSET_(r32,11,11,v)
#define GET16AVSReg_CTRL3_fast_voltage_change_trigger(r16) _BFGET_(r16,11,11)
#define SET16AVSReg_CTRL3_fast_voltage_change_trigger(r16,v) _BFSET_(r16,11,11,v)
#define GET32AVSReg_CTRL3_voltage_change_rate(r32) _BFGET_(r32,21,12)
#define SET32AVSReg_CTRL3_voltage_change_rate(r32,v) _BFSET_(r32,21,12,v)
#define GET32AVSReg_CTRL3_target_delta(r32) _BFGET_(r32,29,22)
#define SET32AVSReg_CTRL3_target_delta(r32,v) _BFSET_(r32,29,22,v)
#define GET16AVSReg_CTRL3_target_delta(r16) _BFGET_(r16,13, 6)
#define SET16AVSReg_CTRL3_target_delta(r16,v) _BFSET_(r16,13, 6,v)
#define w32AVSReg_CTRL3 {\
UNSG32 uCTRL3_offset_discharge_rate : 4;\
UNSG32 uCTRL3_bg_cal_ext : 6;\
UNSG32 uCTRL3_bg_cal_man : 1;\
UNSG32 uCTRL3_fast_voltage_change_trigger : 1;\
UNSG32 uCTRL3_voltage_change_rate : 10;\
UNSG32 uCTRL3_target_delta : 8;\
UNSG32 RSVDxC_b30 : 2;\
}
union { UNSG32 u32AVSReg_CTRL3;
struct w32AVSReg_CTRL3;
};
///////////////////////////////////////////////////////////
#define GET32AVSReg_CTRL4_master(r32) _BFGET_(r32, 0, 0)
#define SET32AVSReg_CTRL4_master(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16AVSReg_CTRL4_master(r16) _BFGET_(r16, 0, 0)
#define SET16AVSReg_CTRL4_master(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32AVSReg_CTRL4_in_slave_avs_voltage_up(r32) _BFGET_(r32, 1, 1)
#define SET32AVSReg_CTRL4_in_slave_avs_voltage_up(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16AVSReg_CTRL4_in_slave_avs_voltage_up(r16) _BFGET_(r16, 1, 1)
#define SET16AVSReg_CTRL4_in_slave_avs_voltage_up(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32AVSReg_CTRL4_inc_offset_range(r32) _BFGET_(r32, 2, 2)
#define SET32AVSReg_CTRL4_inc_offset_range(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16AVSReg_CTRL4_inc_offset_range(r16) _BFGET_(r16, 2, 2)
#define SET16AVSReg_CTRL4_inc_offset_range(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32AVSReg_CTRL4_driver_bias_cfg(r32) _BFGET_(r32, 6, 3)
#define SET32AVSReg_CTRL4_driver_bias_cfg(r32,v) _BFSET_(r32, 6, 3,v)
#define GET16AVSReg_CTRL4_driver_bias_cfg(r16) _BFGET_(r16, 6, 3)
#define SET16AVSReg_CTRL4_driver_bias_cfg(r16,v) _BFSET_(r16, 6, 3,v)
#define GET32AVSReg_CTRL4_avs_porst_out_sel(r32) _BFGET_(r32, 9, 7)
#define SET32AVSReg_CTRL4_avs_porst_out_sel(r32,v) _BFSET_(r32, 9, 7,v)
#define GET16AVSReg_CTRL4_avs_porst_out_sel(r16) _BFGET_(r16, 9, 7)
#define SET16AVSReg_CTRL4_avs_porst_out_sel(r16,v) _BFSET_(r16, 9, 7,v)
#define w32AVSReg_CTRL4 {\
UNSG32 uCTRL4_master : 1;\
UNSG32 uCTRL4_in_slave_avs_voltage_up : 1;\
UNSG32 uCTRL4_inc_offset_range : 1;\
UNSG32 uCTRL4_driver_bias_cfg : 4;\
UNSG32 uCTRL4_avs_porst_out_sel : 3;\
UNSG32 RSVDx10_b10 : 22;\
}
union { UNSG32 u32AVSReg_CTRL4;
struct w32AVSReg_CTRL4;
};
///////////////////////////////////////////////////////////
#define GET32AVSReg_MiscStatus_out_slave_avs_voltage_up(r32) _BFGET_(r32, 0, 0)
#define SET32AVSReg_MiscStatus_out_slave_avs_voltage_up(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16AVSReg_MiscStatus_out_slave_avs_voltage_up(r16) _BFGET_(r16, 0, 0)
#define SET16AVSReg_MiscStatus_out_slave_avs_voltage_up(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32AVSReg_MiscStatus_above_limit(r32) _BFGET_(r32, 1, 1)
#define SET32AVSReg_MiscStatus_above_limit(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16AVSReg_MiscStatus_above_limit(r16) _BFGET_(r16, 1, 1)
#define SET16AVSReg_MiscStatus_above_limit(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32AVSReg_MiscStatus_below_limit(r32) _BFGET_(r32, 2, 2)
#define SET32AVSReg_MiscStatus_below_limit(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16AVSReg_MiscStatus_below_limit(r16) _BFGET_(r16, 2, 2)
#define SET16AVSReg_MiscStatus_below_limit(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32AVSReg_MiscStatus_above_limit_sticky(r32) _BFGET_(r32, 3, 3)
#define SET32AVSReg_MiscStatus_above_limit_sticky(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16AVSReg_MiscStatus_above_limit_sticky(r16) _BFGET_(r16, 3, 3)
#define SET16AVSReg_MiscStatus_above_limit_sticky(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32AVSReg_MiscStatus_below_limit_sticky(r32) _BFGET_(r32, 4, 4)
#define SET32AVSReg_MiscStatus_below_limit_sticky(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16AVSReg_MiscStatus_below_limit_sticky(r16) _BFGET_(r16, 4, 4)
#define SET16AVSReg_MiscStatus_below_limit_sticky(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32AVSReg_MiscStatus_bg_cal_value(r32) _BFGET_(r32,10, 5)
#define SET32AVSReg_MiscStatus_bg_cal_value(r32,v) _BFSET_(r32,10, 5,v)
#define GET16AVSReg_MiscStatus_bg_cal_value(r16) _BFGET_(r16,10, 5)
#define SET16AVSReg_MiscStatus_bg_cal_value(r16,v) _BFSET_(r16,10, 5,v)
#define GET32AVSReg_MiscStatus_fast_travel_indication(r32) _BFGET_(r32,11,11)
#define SET32AVSReg_MiscStatus_fast_travel_indication(r32,v) _BFSET_(r32,11,11,v)
#define GET16AVSReg_MiscStatus_fast_travel_indication(r16) _BFGET_(r16,11,11)
#define SET16AVSReg_MiscStatus_fast_travel_indication(r16,v) _BFSET_(r16,11,11,v)
#define w32AVSReg_MiscStatus {\
UNSG32 uMiscStatus_out_slave_avs_voltage_up : 1;\
UNSG32 uMiscStatus_above_limit : 1;\
UNSG32 uMiscStatus_below_limit : 1;\
UNSG32 uMiscStatus_above_limit_sticky : 1;\
UNSG32 uMiscStatus_below_limit_sticky : 1;\
UNSG32 uMiscStatus_bg_cal_value : 6;\
UNSG32 uMiscStatus_fast_travel_indication : 1;\
UNSG32 RSVDx14_b12 : 20;\
}
union { UNSG32 u32AVSReg_MiscStatus;
struct w32AVSReg_MiscStatus;
};
///////////////////////////////////////////////////////////
#define GET32AVSReg_DROStatus_inter_dro_count(r32) _BFGET_(r32,15, 0)
#define SET32AVSReg_DROStatus_inter_dro_count(r32,v) _BFSET_(r32,15, 0,v)
#define GET16AVSReg_DROStatus_inter_dro_count(r16) _BFGET_(r16,15, 0)
#define SET16AVSReg_DROStatus_inter_dro_count(r16,v) _BFSET_(r16,15, 0,v)
#define GET32AVSReg_DROStatus_avs_delta(r32) _BFGET_(r32,23,16)
#define SET32AVSReg_DROStatus_avs_delta(r32,v) _BFSET_(r32,23,16,v)
#define GET16AVSReg_DROStatus_avs_delta(r16) _BFGET_(r16, 7, 0)
#define SET16AVSReg_DROStatus_avs_delta(r16,v) _BFSET_(r16, 7, 0,v)
#define w32AVSReg_DROStatus {\
UNSG32 uDROStatus_inter_dro_count : 16;\
UNSG32 uDROStatus_avs_delta : 8;\
UNSG32 RSVDx18_b24 : 8;\
}
union { UNSG32 u32AVSReg_DROStatus;
struct w32AVSReg_DROStatus;
};
///////////////////////////////////////////////////////////
#define GET32AVSReg_DROMinMax_max_dro_count(r32) _BFGET_(r32,15, 0)
#define SET32AVSReg_DROMinMax_max_dro_count(r32,v) _BFSET_(r32,15, 0,v)
#define GET16AVSReg_DROMinMax_max_dro_count(r16) _BFGET_(r16,15, 0)
#define SET16AVSReg_DROMinMax_max_dro_count(r16,v) _BFSET_(r16,15, 0,v)
#define GET32AVSReg_DROMinMax_min_dro_count(r32) _BFGET_(r32,31,16)
#define SET32AVSReg_DROMinMax_min_dro_count(r32,v) _BFSET_(r32,31,16,v)
#define GET16AVSReg_DROMinMax_min_dro_count(r16) _BFGET_(r16,15, 0)
#define SET16AVSReg_DROMinMax_min_dro_count(r16,v) _BFSET_(r16,15, 0,v)
#define w32AVSReg_DROMinMax {\
UNSG32 uDROMinMax_max_dro_count : 16;\
UNSG32 uDROMinMax_min_dro_count : 16;\
}
union { UNSG32 u32AVSReg_DROMinMax;
struct w32AVSReg_DROMinMax;
};
///////////////////////////////////////////////////////////
#define GET32AVSReg_AVSMinMax_max_avs_delta(r32) _BFGET_(r32,15, 0)
#define SET32AVSReg_AVSMinMax_max_avs_delta(r32,v) _BFSET_(r32,15, 0,v)
#define GET16AVSReg_AVSMinMax_max_avs_delta(r16) _BFGET_(r16,15, 0)
#define SET16AVSReg_AVSMinMax_max_avs_delta(r16,v) _BFSET_(r16,15, 0,v)
#define GET32AVSReg_AVSMinMax_min_avs_delta(r32) _BFGET_(r32,31,16)
#define SET32AVSReg_AVSMinMax_min_avs_delta(r32,v) _BFSET_(r32,31,16,v)
#define GET16AVSReg_AVSMinMax_min_avs_delta(r16) _BFGET_(r16,15, 0)
#define SET16AVSReg_AVSMinMax_min_avs_delta(r16,v) _BFSET_(r16,15, 0,v)
#define w32AVSReg_AVSMinMax {\
UNSG32 uAVSMinMax_max_avs_delta : 16;\
UNSG32 uAVSMinMax_min_avs_delta : 16;\
}
union { UNSG32 u32AVSReg_AVSMinMax;
struct w32AVSReg_AVSMinMax;
};
///////////////////////////////////////////////////////////
#define GET32AVSReg_dummy_dummy(r32) _BFGET_(r32,31, 0)
#define SET32AVSReg_dummy_dummy(r32,v) _BFSET_(r32,31, 0,v)
#define w32AVSReg_dummy {\
UNSG32 udummy_dummy : 32;\
}
union { UNSG32 u32AVSReg_dummy;
struct w32AVSReg_dummy;
};
///////////////////////////////////////////////////////////
} SIE_AVSReg;
typedef union T32AVSReg_CTRL0
{ UNSG32 u32;
struct w32AVSReg_CTRL0;
} T32AVSReg_CTRL0;
typedef union T32AVSReg_CTRL1
{ UNSG32 u32;
struct w32AVSReg_CTRL1;
} T32AVSReg_CTRL1;
typedef union T32AVSReg_CTRL2
{ UNSG32 u32;
struct w32AVSReg_CTRL2;
} T32AVSReg_CTRL2;
typedef union T32AVSReg_CTRL3
{ UNSG32 u32;
struct w32AVSReg_CTRL3;
} T32AVSReg_CTRL3;
typedef union T32AVSReg_CTRL4
{ UNSG32 u32;
struct w32AVSReg_CTRL4;
} T32AVSReg_CTRL4;
typedef union T32AVSReg_MiscStatus
{ UNSG32 u32;
struct w32AVSReg_MiscStatus;
} T32AVSReg_MiscStatus;
typedef union T32AVSReg_DROStatus
{ UNSG32 u32;
struct w32AVSReg_DROStatus;
} T32AVSReg_DROStatus;
typedef union T32AVSReg_DROMinMax
{ UNSG32 u32;
struct w32AVSReg_DROMinMax;
} T32AVSReg_DROMinMax;
typedef union T32AVSReg_AVSMinMax
{ UNSG32 u32;
struct w32AVSReg_AVSMinMax;
} T32AVSReg_AVSMinMax;
typedef union T32AVSReg_dummy
{ UNSG32 u32;
struct w32AVSReg_dummy;
} T32AVSReg_dummy;
///////////////////////////////////////////////////////////
typedef union TAVSReg_CTRL0
{ UNSG32 u32[1];
struct {
struct w32AVSReg_CTRL0;
};
} TAVSReg_CTRL0;
typedef union TAVSReg_CTRL1
{ UNSG32 u32[1];
struct {
struct w32AVSReg_CTRL1;
};
} TAVSReg_CTRL1;
typedef union TAVSReg_CTRL2
{ UNSG32 u32[1];
struct {
struct w32AVSReg_CTRL2;
};
} TAVSReg_CTRL2;
typedef union TAVSReg_CTRL3
{ UNSG32 u32[1];
struct {
struct w32AVSReg_CTRL3;
};
} TAVSReg_CTRL3;
typedef union TAVSReg_CTRL4
{ UNSG32 u32[1];
struct {
struct w32AVSReg_CTRL4;
};
} TAVSReg_CTRL4;
typedef union TAVSReg_MiscStatus
{ UNSG32 u32[1];
struct {
struct w32AVSReg_MiscStatus;
};
} TAVSReg_MiscStatus;
typedef union TAVSReg_DROStatus
{ UNSG32 u32[1];
struct {
struct w32AVSReg_DROStatus;
};
} TAVSReg_DROStatus;
typedef union TAVSReg_DROMinMax
{ UNSG32 u32[1];
struct {
struct w32AVSReg_DROMinMax;
};
} TAVSReg_DROMinMax;
typedef union TAVSReg_AVSMinMax
{ UNSG32 u32[1];
struct {
struct w32AVSReg_AVSMinMax;
};
} TAVSReg_AVSMinMax;
typedef union TAVSReg_dummy
{ UNSG32 u32[1];
struct {
struct w32AVSReg_dummy;
};
} TAVSReg_dummy;
///////////////////////////////////////////////////////////
SIGN32 AVSReg_drvrd(SIE_AVSReg *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 AVSReg_drvwr(SIE_AVSReg *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void AVSReg_reset(SIE_AVSReg *p);
SIGN32 AVSReg_cmp (SIE_AVSReg *p, SIE_AVSReg *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define AVSReg_check(p,pie,pfx,hLOG) AVSReg_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define AVSReg_print(p, pfx,hLOG) AVSReg_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: AVSReg
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE CA7PllReg biu (4,4)
/// ###
/// * All the controls for CA7_PLL Wrapper
/// ###
/// # # ----------------------------------------------------------
/// @ 0x00000 (P)
/// # 0x00000 CA7Reg
/// $CA7Reg CA7Reg REG
/// @ 0x00070 (P)
/// # 0x00070 PllReg
/// $pll PllReg REG
/// @ 0x00088 (P)
/// # 0x00088 FVSReg
/// $fvsCtrl FVSReg REG
/// @ 0x000B0 (P)
/// # 0x000B0 mc5PwrCtrl
/// $pwrOff mc5PwrCtrl REG
/// @ 0x000B8 DDRPHY_PD_Ctrl (P)
/// %unsigned 1 pd_core 0x1
/// ###
/// * For BG2CD+ A0 power switches are removed programming this register will not have any effect
/// * 1'b1 : Isolation enable for DDRPHY Pads
/// * 1'b0 : Isolation disabled for DDRPHY Pads
/// ###
/// %unsigned 1 pdb_core 0x0
/// ###
/// * For BG2CD+ A0 power switches are removed programming this register will not have any effect
/// * 1'b0 : Isolation enable for DDRPHY Pads
/// * 1'b1 : Isolation disabled for DDRPHY Pads
/// ###
/// %% 30 # Stuffing bits...
/// @ 0x000BC (W-)
/// # # Stuffing bytes...
/// %% 260640
/// @ 0x08000 (P)
/// # 0x08000 fvsReg
/// $fvsReg fvsReg REG
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 32768B, bits: 756b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_CA7PllReg
#define h_CA7PllReg (){}
#define RA_CA7PllReg_CA7Reg 0x0000
///////////////////////////////////////////////////////////
#define RA_CA7PllReg_PllReg 0x0070
///////////////////////////////////////////////////////////
#define RA_CA7PllReg_FVSReg 0x0088
///////////////////////////////////////////////////////////
#define RA_CA7PllReg_mc5PwrCtrl 0x00B0
///////////////////////////////////////////////////////////
#define RA_CA7PllReg_DDRPHY_PD_Ctrl 0x00B8
#define BA_CA7PllReg_DDRPHY_PD_Ctrl_pd_core 0x00B8
#define B16CA7PllReg_DDRPHY_PD_Ctrl_pd_core 0x00B8
#define LSb32CA7PllReg_DDRPHY_PD_Ctrl_pd_core 0
#define LSb16CA7PllReg_DDRPHY_PD_Ctrl_pd_core 0
#define bCA7PllReg_DDRPHY_PD_Ctrl_pd_core 1
#define MSK32CA7PllReg_DDRPHY_PD_Ctrl_pd_core 0x00000001
#define BA_CA7PllReg_DDRPHY_PD_Ctrl_pdb_core 0x00B8
#define B16CA7PllReg_DDRPHY_PD_Ctrl_pdb_core 0x00B8
#define LSb32CA7PllReg_DDRPHY_PD_Ctrl_pdb_core 1
#define LSb16CA7PllReg_DDRPHY_PD_Ctrl_pdb_core 1
#define bCA7PllReg_DDRPHY_PD_Ctrl_pdb_core 1
#define MSK32CA7PllReg_DDRPHY_PD_Ctrl_pdb_core 0x00000002
///////////////////////////////////////////////////////////
#define RA_CA7PllReg_fvsReg 0x8000
///////////////////////////////////////////////////////////
typedef struct SIE_CA7PllReg {
///////////////////////////////////////////////////////////
SIE_CA7Reg ie_CA7Reg;
///////////////////////////////////////////////////////////
SIE_pll ie_PllReg;
///////////////////////////////////////////////////////////
SIE_fvsCtrl ie_FVSReg;
///////////////////////////////////////////////////////////
SIE_pwrOff ie_mc5PwrCtrl;
///////////////////////////////////////////////////////////
#define GET32CA7PllReg_DDRPHY_PD_Ctrl_pd_core(r32) _BFGET_(r32, 0, 0)
#define SET32CA7PllReg_DDRPHY_PD_Ctrl_pd_core(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16CA7PllReg_DDRPHY_PD_Ctrl_pd_core(r16) _BFGET_(r16, 0, 0)
#define SET16CA7PllReg_DDRPHY_PD_Ctrl_pd_core(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32CA7PllReg_DDRPHY_PD_Ctrl_pdb_core(r32) _BFGET_(r32, 1, 1)
#define SET32CA7PllReg_DDRPHY_PD_Ctrl_pdb_core(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16CA7PllReg_DDRPHY_PD_Ctrl_pdb_core(r16) _BFGET_(r16, 1, 1)
#define SET16CA7PllReg_DDRPHY_PD_Ctrl_pdb_core(r16,v) _BFSET_(r16, 1, 1,v)
#define w32CA7PllReg_DDRPHY_PD_Ctrl {\
UNSG32 uDDRPHY_PD_Ctrl_pd_core : 1;\
UNSG32 uDDRPHY_PD_Ctrl_pdb_core : 1;\
UNSG32 RSVDxB8_b2 : 30;\
}
union { UNSG32 u32CA7PllReg_DDRPHY_PD_Ctrl;
struct w32CA7PllReg_DDRPHY_PD_Ctrl;
};
///////////////////////////////////////////////////////////
UNSG8 RSVDxBC [32580];
///////////////////////////////////////////////////////////
SIE_fvsReg ie_fvsReg;
///////////////////////////////////////////////////////////
} SIE_CA7PllReg;
typedef union T32CA7PllReg_DDRPHY_PD_Ctrl
{ UNSG32 u32;
struct w32CA7PllReg_DDRPHY_PD_Ctrl;
} T32CA7PllReg_DDRPHY_PD_Ctrl;
///////////////////////////////////////////////////////////
typedef union TCA7PllReg_DDRPHY_PD_Ctrl
{ UNSG32 u32[1];
struct {
struct w32CA7PllReg_DDRPHY_PD_Ctrl;
};
} TCA7PllReg_DDRPHY_PD_Ctrl;
///////////////////////////////////////////////////////////
SIGN32 CA7PllReg_drvrd(SIE_CA7PllReg *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 CA7PllReg_drvwr(SIE_CA7PllReg *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void CA7PllReg_reset(SIE_CA7PllReg *p);
SIGN32 CA7PllReg_cmp (SIE_CA7PllReg *p, SIE_CA7PllReg *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define CA7PllReg_check(p,pie,pfx,hLOG) CA7PllReg_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define CA7PllReg_print(p, pfx,hLOG) CA7PllReg_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: CA7PllReg
////////////////////////////////////////////////////////////
#ifdef __cplusplus
}
#endif
#pragma pack()
#endif
//////
/// ENDOFFILE: cpu_ca7.h
////////////////////////////////////////////////////////////