| /******************************************************************************** |
| * Marvell GPL License Option |
| * |
| * If you received this File from Marvell, you may opt to use, redistribute and/or |
| * modify this File in accordance with the terms and conditions of the General |
| * Public License Version 2, June 1991 (the "GPL License"), a copy of which is |
| * available along with the File in the license.txt file or by writing to the Free |
| * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or |
| * on the worldwide web at http://www.gnu.org/licenses/gpl.txt. |
| * |
| * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED |
| * WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY |
| * DISCLAIMED. The GPL License provides additional details about this warranty |
| * disclaimer. |
| ******************************************************************************/ |
| |
| ////// |
| /// don't edit! auto-generated by docc: lpRegs.h |
| //////////////////////////////////////////////////////////// |
| #ifndef lpRegs_h |
| #define lpRegs_h (){} |
| |
| |
| #include "ctypes.h" |
| |
| #pragma pack(1) |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| |
| #ifndef _DOCC_H_BITOPS_ |
| #define _DOCC_H_BITOPS_ (){} |
| |
| #define _bSETMASK_(b) ((b)<32 ? (1<<((b)&31)) : 0) |
| #define _NSETMASK_(msb,lsb) (_bSETMASK_((msb)+1)-_bSETMASK_(lsb)) |
| #define _bCLRMASK_(b) (~_bSETMASK_(b)) |
| #define _NCLRMASK_(msb,lsb) (~_NSETMASK_(msb,lsb)) |
| #define _BFGET_(r,msb,lsb) (_NSETMASK_((msb)-(lsb),0)&((r)>>(lsb))) |
| #define _BFSET_(r,msb,lsb,v) do{ (r)&=_NCLRMASK_(msb,lsb); (r)|=_NSETMASK_(msb,lsb)&((v)<<(lsb)); }while(0) |
| |
| #endif |
| |
| |
| |
| ////// |
| /// |
| /// $INTERFACE pwrOff (4,4) |
| /// ### |
| /// * Register for the Power domain which is OFF by default |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 ctrl (RW-) |
| /// ### |
| /// * Power Domain Control Register |
| /// ### |
| /// %unsigned 1 iso_eN 0x0 |
| /// : enable 0x0 |
| /// : disable 0x1 |
| /// ### |
| /// * Isolation control bit. Active low |
| /// * 0 : Isolation is enabled |
| /// * 1 : Isolation is disabled (default) |
| /// ### |
| /// %unsigned 2 pwrSwitchCtrl 0x0 |
| /// : PWROFF 0x0 |
| /// : PWRON 0x3 |
| /// ### |
| /// * Power Switch control |
| /// * Bit 1 : SLP1B |
| /// * Bit 0 : SLP2B |
| /// * SLP1B SLP2B |
| /// * 0 X Switch is turned off |
| /// * 1 0 PMOS switch in current mirror configuration. Constant current charging to limit in-rush current |
| /// * 1 1 PMOS switch is fully turned on to reduce Ron |
| /// ### |
| /// %unsigned 1 pwrDomainRstN 0x0 |
| /// : enable 0x0 |
| /// : disable 0x1 |
| /// ### |
| /// * Power Domain Reset. Active low. |
| /// * 0 : Reset the power domain |
| /// * 1: De-assert the reset for the power domain |
| /// ### |
| /// %% 28 # Stuffing bits... |
| /// @ 0x00004 status (R-) |
| /// %unsigned 2 pwrStatus |
| /// ### |
| /// * Power domain Status output from the power domain module |
| /// * Bit 1 : SLP1B |
| /// * Bit 0 : SLP2B |
| /// * SLP1B SLP2B |
| /// * 0 X Switch is turned off |
| /// * 1 0 PMOS switch in current mirror configuration. Constant current charging to limit in-rush current |
| /// * 1 1 PMOS switch is fully turned on to reduce Ron |
| /// ### |
| /// %% 30 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 6b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_pwrOff |
| #define h_pwrOff (){} |
| |
| #define RA_pwrOff_ctrl 0x0000 |
| |
| #define BA_pwrOff_ctrl_iso_eN 0x0000 |
| #define B16pwrOff_ctrl_iso_eN 0x0000 |
| #define LSb32pwrOff_ctrl_iso_eN 0 |
| #define LSb16pwrOff_ctrl_iso_eN 0 |
| #define bpwrOff_ctrl_iso_eN 1 |
| #define MSK32pwrOff_ctrl_iso_eN 0x00000001 |
| #define pwrOff_ctrl_iso_eN_enable 0x0 |
| #define pwrOff_ctrl_iso_eN_disable 0x1 |
| |
| #define BA_pwrOff_ctrl_pwrSwitchCtrl 0x0000 |
| #define B16pwrOff_ctrl_pwrSwitchCtrl 0x0000 |
| #define LSb32pwrOff_ctrl_pwrSwitchCtrl 1 |
| #define LSb16pwrOff_ctrl_pwrSwitchCtrl 1 |
| #define bpwrOff_ctrl_pwrSwitchCtrl 2 |
| #define MSK32pwrOff_ctrl_pwrSwitchCtrl 0x00000006 |
| #define pwrOff_ctrl_pwrSwitchCtrl_PWROFF 0x0 |
| #define pwrOff_ctrl_pwrSwitchCtrl_PWRON 0x3 |
| |
| #define BA_pwrOff_ctrl_pwrDomainRstN 0x0000 |
| #define B16pwrOff_ctrl_pwrDomainRstN 0x0000 |
| #define LSb32pwrOff_ctrl_pwrDomainRstN 3 |
| #define LSb16pwrOff_ctrl_pwrDomainRstN 3 |
| #define bpwrOff_ctrl_pwrDomainRstN 1 |
| #define MSK32pwrOff_ctrl_pwrDomainRstN 0x00000008 |
| #define pwrOff_ctrl_pwrDomainRstN_enable 0x0 |
| #define pwrOff_ctrl_pwrDomainRstN_disable 0x1 |
| /////////////////////////////////////////////////////////// |
| #define RA_pwrOff_status 0x0004 |
| |
| #define BA_pwrOff_status_pwrStatus 0x0004 |
| #define B16pwrOff_status_pwrStatus 0x0004 |
| #define LSb32pwrOff_status_pwrStatus 0 |
| #define LSb16pwrOff_status_pwrStatus 0 |
| #define bpwrOff_status_pwrStatus 2 |
| #define MSK32pwrOff_status_pwrStatus 0x00000003 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_pwrOff { |
| /////////////////////////////////////////////////////////// |
| #define GET32pwrOff_ctrl_iso_eN(r32) _BFGET_(r32, 0, 0) |
| #define SET32pwrOff_ctrl_iso_eN(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16pwrOff_ctrl_iso_eN(r16) _BFGET_(r16, 0, 0) |
| #define SET16pwrOff_ctrl_iso_eN(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32pwrOff_ctrl_pwrSwitchCtrl(r32) _BFGET_(r32, 2, 1) |
| #define SET32pwrOff_ctrl_pwrSwitchCtrl(r32,v) _BFSET_(r32, 2, 1,v) |
| #define GET16pwrOff_ctrl_pwrSwitchCtrl(r16) _BFGET_(r16, 2, 1) |
| #define SET16pwrOff_ctrl_pwrSwitchCtrl(r16,v) _BFSET_(r16, 2, 1,v) |
| |
| #define GET32pwrOff_ctrl_pwrDomainRstN(r32) _BFGET_(r32, 3, 3) |
| #define SET32pwrOff_ctrl_pwrDomainRstN(r32,v) _BFSET_(r32, 3, 3,v) |
| #define GET16pwrOff_ctrl_pwrDomainRstN(r16) _BFGET_(r16, 3, 3) |
| #define SET16pwrOff_ctrl_pwrDomainRstN(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define w32pwrOff_ctrl {\ |
| UNSG32 uctrl_iso_eN : 1;\ |
| UNSG32 uctrl_pwrSwitchCtrl : 2;\ |
| UNSG32 uctrl_pwrDomainRstN : 1;\ |
| UNSG32 RSVDx0_b4 : 28;\ |
| } |
| union { UNSG32 u32pwrOff_ctrl; |
| struct w32pwrOff_ctrl; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32pwrOff_status_pwrStatus(r32) _BFGET_(r32, 1, 0) |
| #define SET32pwrOff_status_pwrStatus(r32,v) _BFSET_(r32, 1, 0,v) |
| #define GET16pwrOff_status_pwrStatus(r16) _BFGET_(r16, 1, 0) |
| #define SET16pwrOff_status_pwrStatus(r16,v) _BFSET_(r16, 1, 0,v) |
| |
| #define w32pwrOff_status {\ |
| UNSG32 ustatus_pwrStatus : 2;\ |
| UNSG32 RSVDx4_b2 : 30;\ |
| } |
| union { UNSG32 u32pwrOff_status; |
| struct w32pwrOff_status; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_pwrOff; |
| |
| typedef union T32pwrOff_ctrl |
| { UNSG32 u32; |
| struct w32pwrOff_ctrl; |
| } T32pwrOff_ctrl; |
| typedef union T32pwrOff_status |
| { UNSG32 u32; |
| struct w32pwrOff_status; |
| } T32pwrOff_status; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TpwrOff_ctrl |
| { UNSG32 u32[1]; |
| struct { |
| struct w32pwrOff_ctrl; |
| }; |
| } TpwrOff_ctrl; |
| typedef union TpwrOff_status |
| { UNSG32 u32[1]; |
| struct { |
| struct w32pwrOff_status; |
| }; |
| } TpwrOff_status; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 pwrOff_drvrd(SIE_pwrOff *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 pwrOff_drvwr(SIE_pwrOff *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void pwrOff_reset(SIE_pwrOff *p); |
| SIGN32 pwrOff_cmp (SIE_pwrOff *p, SIE_pwrOff *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define pwrOff_check(p,pie,pfx,hLOG) pwrOff_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define pwrOff_print(p, pfx,hLOG) pwrOff_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: pwrOff |
| //////////////////////////////////////////////////////////// |
| |
| ////// |
| /// |
| /// $INTERFACE pwrOn (4,4) |
| /// ### |
| /// * Register for the Power domain which is ON by default |
| /// ### |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 ctrl (RW-) |
| /// ### |
| /// * Power Domain Control Register |
| /// ### |
| /// %unsigned 1 iso_eN 0x1 |
| /// : enable 0x0 |
| /// : disable 0x1 |
| /// ### |
| /// * Isolation control bit. Active low |
| /// * 0 : Isolation is enabled |
| /// * 1 : Isolation is disabled (default) |
| /// ### |
| /// %unsigned 2 pwrSwitchCtrl 0x3 |
| /// ### |
| /// * Power Switch control |
| /// * Bit 1 : SLP1B |
| /// * Bit 0 : SLP2B |
| /// * SLP1B SLP2B |
| /// * 0 X Switch is turned off |
| /// * 1 0 PMOS switch in current mirror configuration. Constant current charging to limit in-rush current |
| /// * 1 1 PMOS switch is fully turned on to reduce Ron |
| /// ### |
| /// %unsigned 1 pwrDomainRstN 0x1 |
| /// ### |
| /// * Power Domain Reset. Active low. |
| /// * 0 : Reset the power domain |
| /// * 1: De-assert the reset for the power domain |
| /// ### |
| /// %% 28 # Stuffing bits... |
| /// @ 0x00004 status (R-) |
| /// %unsigned 2 pwrStatus |
| /// ### |
| /// * Power domain Status output from the power domain module |
| /// * Bit 1 : SLP1B |
| /// * Bit 0 : SLP2B |
| /// * SLP1B SLP2B |
| /// * 0 X Switch is turned off |
| /// * 1 0 PMOS switch in current mirror configuration. Constant current charging to limit in-rush current |
| /// * 1 1 PMOS switch is fully turned on to reduce Ron |
| /// ### |
| /// %% 30 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 8B, bits: 6b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_pwrOn |
| #define h_pwrOn (){} |
| |
| #define RA_pwrOn_ctrl 0x0000 |
| |
| #define BA_pwrOn_ctrl_iso_eN 0x0000 |
| #define B16pwrOn_ctrl_iso_eN 0x0000 |
| #define LSb32pwrOn_ctrl_iso_eN 0 |
| #define LSb16pwrOn_ctrl_iso_eN 0 |
| #define bpwrOn_ctrl_iso_eN 1 |
| #define MSK32pwrOn_ctrl_iso_eN 0x00000001 |
| #define pwrOn_ctrl_iso_eN_enable 0x0 |
| #define pwrOn_ctrl_iso_eN_disable 0x1 |
| |
| #define BA_pwrOn_ctrl_pwrSwitchCtrl 0x0000 |
| #define B16pwrOn_ctrl_pwrSwitchCtrl 0x0000 |
| #define LSb32pwrOn_ctrl_pwrSwitchCtrl 1 |
| #define LSb16pwrOn_ctrl_pwrSwitchCtrl 1 |
| #define bpwrOn_ctrl_pwrSwitchCtrl 2 |
| #define MSK32pwrOn_ctrl_pwrSwitchCtrl 0x00000006 |
| |
| #define BA_pwrOn_ctrl_pwrDomainRstN 0x0000 |
| #define B16pwrOn_ctrl_pwrDomainRstN 0x0000 |
| #define LSb32pwrOn_ctrl_pwrDomainRstN 3 |
| #define LSb16pwrOn_ctrl_pwrDomainRstN 3 |
| #define bpwrOn_ctrl_pwrDomainRstN 1 |
| #define MSK32pwrOn_ctrl_pwrDomainRstN 0x00000008 |
| /////////////////////////////////////////////////////////// |
| #define RA_pwrOn_status 0x0004 |
| |
| #define BA_pwrOn_status_pwrStatus 0x0004 |
| #define B16pwrOn_status_pwrStatus 0x0004 |
| #define LSb32pwrOn_status_pwrStatus 0 |
| #define LSb16pwrOn_status_pwrStatus 0 |
| #define bpwrOn_status_pwrStatus 2 |
| #define MSK32pwrOn_status_pwrStatus 0x00000003 |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_pwrOn { |
| /////////////////////////////////////////////////////////// |
| #define GET32pwrOn_ctrl_iso_eN(r32) _BFGET_(r32, 0, 0) |
| #define SET32pwrOn_ctrl_iso_eN(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16pwrOn_ctrl_iso_eN(r16) _BFGET_(r16, 0, 0) |
| #define SET16pwrOn_ctrl_iso_eN(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32pwrOn_ctrl_pwrSwitchCtrl(r32) _BFGET_(r32, 2, 1) |
| #define SET32pwrOn_ctrl_pwrSwitchCtrl(r32,v) _BFSET_(r32, 2, 1,v) |
| #define GET16pwrOn_ctrl_pwrSwitchCtrl(r16) _BFGET_(r16, 2, 1) |
| #define SET16pwrOn_ctrl_pwrSwitchCtrl(r16,v) _BFSET_(r16, 2, 1,v) |
| |
| #define GET32pwrOn_ctrl_pwrDomainRstN(r32) _BFGET_(r32, 3, 3) |
| #define SET32pwrOn_ctrl_pwrDomainRstN(r32,v) _BFSET_(r32, 3, 3,v) |
| #define GET16pwrOn_ctrl_pwrDomainRstN(r16) _BFGET_(r16, 3, 3) |
| #define SET16pwrOn_ctrl_pwrDomainRstN(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define w32pwrOn_ctrl {\ |
| UNSG32 uctrl_iso_eN : 1;\ |
| UNSG32 uctrl_pwrSwitchCtrl : 2;\ |
| UNSG32 uctrl_pwrDomainRstN : 1;\ |
| UNSG32 RSVDx0_b4 : 28;\ |
| } |
| union { UNSG32 u32pwrOn_ctrl; |
| struct w32pwrOn_ctrl; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32pwrOn_status_pwrStatus(r32) _BFGET_(r32, 1, 0) |
| #define SET32pwrOn_status_pwrStatus(r32,v) _BFSET_(r32, 1, 0,v) |
| #define GET16pwrOn_status_pwrStatus(r16) _BFGET_(r16, 1, 0) |
| #define SET16pwrOn_status_pwrStatus(r16,v) _BFSET_(r16, 1, 0,v) |
| |
| #define w32pwrOn_status {\ |
| UNSG32 ustatus_pwrStatus : 2;\ |
| UNSG32 RSVDx4_b2 : 30;\ |
| } |
| union { UNSG32 u32pwrOn_status; |
| struct w32pwrOn_status; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_pwrOn; |
| |
| typedef union T32pwrOn_ctrl |
| { UNSG32 u32; |
| struct w32pwrOn_ctrl; |
| } T32pwrOn_ctrl; |
| typedef union T32pwrOn_status |
| { UNSG32 u32; |
| struct w32pwrOn_status; |
| } T32pwrOn_status; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TpwrOn_ctrl |
| { UNSG32 u32[1]; |
| struct { |
| struct w32pwrOn_ctrl; |
| }; |
| } TpwrOn_ctrl; |
| typedef union TpwrOn_status |
| { UNSG32 u32[1]; |
| struct { |
| struct w32pwrOn_status; |
| }; |
| } TpwrOn_status; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 pwrOn_drvrd(SIE_pwrOn *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 pwrOn_drvwr(SIE_pwrOn *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void pwrOn_reset(SIE_pwrOn *p); |
| SIGN32 pwrOn_cmp (SIE_pwrOn *p, SIE_pwrOn *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define pwrOn_check(p,pie,pfx,hLOG) pwrOn_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define pwrOn_print(p, pfx,hLOG) pwrOn_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: pwrOn |
| //////////////////////////////////////////////////////////// |
| |
| |
| |
| #ifdef __cplusplus |
| } |
| #endif |
| #pragma pack() |
| |
| #endif |
| ////// |
| /// ENDOFFILE: lpRegs.h |
| //////////////////////////////////////////////////////////// |
| |
