| /******************************************************************************** |
| * Marvell GPL License Option |
| * |
| * If you received this File from Marvell, you may opt to use, redistribute and/or |
| * modify this File in accordance with the terms and conditions of the General |
| * Public License Version 2, June 1991 (the "GPL License"), a copy of which is |
| * available along with the File in the license.txt file or by writing to the Free |
| * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or |
| * on the worldwide web at http://www.gnu.org/licenses/gpl.txt. |
| * |
| * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED |
| * WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY |
| * DISCLAIMED. The GPL License provides additional details about this warranty |
| * disclaimer. |
| ******************************************************************************/ |
| |
| #ifndef MC5_DEFINES_H
|
| #define MC5_DEFINES_H
|
|
|
| #define MC5_MC_ID 0x000
|
| #define MC5_MC_STATUS 0x004
|
| #define MC5_DRAM_STATUS 0x008
|
| #define MC5_USER_COMMAND_0 0x020
|
| #define MC5_SRAM_control 0x040
|
| #define MC5_MC_Control_0 0x044
|
| #define MC5_Exclusive_Monitor 0x048
|
| #define MC5_Coherency 0x04C
|
| #define MC5_RZ_access_ctl 0x050
|
| #define MC5_PHY_pwr_ctl 0x054
|
| #define MC5_WCB_Control 0x058
|
| #define MC5_BQ_Control 0x05C
|
| #define MC5_ROB_Control 0x060
|
| #define MC5_Port_Weight 0x080
|
| #define MC5_Port_priority 0x084
|
| #define MC5_RRB_Starvation_0 0x088
|
| #define MC5_RRB_Starvation_1 0x08C
|
| #define MC5_RegTable_Control 0x0C0
|
| #define MC5_RegTable_Data_0 0x0C4
|
| #define MC5_RegTable_Data_1 0x0C8
|
| #define MC5_PC_config0 0x100
|
| #define MC5_PC_config1 0x104
|
| #define MC5_PC_status 0x108
|
| #define MC5_PC_Control 0x10C
|
| #define MC5_PC0 0x110
|
| #define MC5_PC1 0x114
|
| #define MC5_PC2 0x118
|
| #define MC5_PC3 0x11C
|
| #define MC5_PC4 0x120
|
| #define MC5_PC5 0x124
|
| #define MC5_PC6 0x128
|
| #define MC5_PC7 0x12C
|
| #define MC5_ISR 0x140
|
| #define MC5_IER 0x144
|
| #define MC5_ADC_ERR_ID 0x150
|
| #define MC5_ADC_ERR_ADR_L 0x154
|
| #define MC5_ADC_ERR_ADR_H 0x158
|
| #define MC5_AM_PERIOD 0x160
|
| #define MC5_AM_TH 0x164
|
| #define MC5_Test_Control_0 0x1C4
|
| #define MC5_Test_Control_1 0x1C8
|
| #define MC5_CH0_MMAP0 0x200
|
| #define MC5_CH0_PMAP0 0x210
|
| #define MC5_CH0_MC_Control_1 0x2C0
|
| #define MC5_CH0_MC_Control_2 0x2C4
|
| #define MC5_CH0_MC_Control_3 0x2C8
|
| #define MC5_CH0_DRAM_Config_1 0x300
|
| #define MC5_CH0_DRAM_Config_2 0x304
|
| #define MC5_CH0_DRAM_Config_5_CS0 0x310
|
| #define MC5_CH0_DRAM_Control_1 0x340
|
| #define MC5_CH0_DRAM_Control_2 0x344
|
| #define MC5_CH0_DRAM_Control_3 0x348
|
| #define MC5_CH0_DDR_init_timing_control_0 0x380
|
| #define MC5_CH0_DDR_init_timing_control_1 0x384
|
| #define MC5_CH0_ZQC_Timing_0 0x388
|
| #define MC5_CH0_ZQC_Timing_1 0x38C
|
| #define MC5_CH0_Refresh_timing 0x390
|
| #define MC5_CH0_SelfRefresh_timing 0x394
|
| #define MC5_CH0_PowerDown_timing 0x398
|
| #define MC5_CH0_MRS_timing 0x39C
|
| #define MC5_CH0_ACT_timing 0x3A0
|
| #define MC5_CH0_PreCharge_Timing 0x3A4
|
| #define MC5_CH0_CAS_RAS_timing 0x3A8
|
| #define MC5_CH0_Off_spec_timing 0x3AC
|
| #define MC5_CH0_PHY_Control_1 0x400
|
| #define MC5_CH0_PHY_Control_2 0x404
|
| #define MC5_CH0_PHY_Control_3 0x408
|
| #define MC5_CH0_PHY_Control_4 0x40C
|
| #define MC5_CH0_PHY_Control_5 0x410
|
| #define MC5_CH0_PHY_Control_6 0x414
|
| #define MC5_CH0_PHY_Control_8 0x41C
|
| #define MC5_CH0_PHY_Control_9 0x420
|
| #define MC5_CH0_PHY_Control_10 0x424
|
| #define MC5_CH0_PHY_Control_11 0x428
|
| #define MC5_CH0_PHY_Control_12 0x42C
|
| #define MC5_CH0_PHY_Control_13 0x430
|
| #define MC5_CH0_PHY_Control_14 0x434
|
| #define MC5_CH0_PHY_Control_15 0x438
|
| #define MC5_CH0_PHY_DLL_control_B0 0x500
|
| #define MC5_CH0_PHY_DLL_control_B1 0x504
|
| #define MC5_CH0_PHY_DLL_control_B2 0x508
|
| #define MC5_CH0_PHY_DLL_control_B3 0x50C
|
| #define MC5_CH0_PHY_DLL_BYTE_SELECT 0x528
|
| #define MC5_CH0_PHY_DLL_DLY 0x52C
|
| #define MC5_CH0_PHY_Data_Byte_Control_B0 0x540
|
| #define MC5_CH0_PHY_Data_Byte_Control_B1 0x544
|
| #define MC5_CH0_PHY_Data_Byte_Control_B2 0x548
|
| #define MC5_CH0_PHY_Data_Byte_Control_B3 0x54C
|
| #define MC5_CH0_PHY_WL_RL_Control 0x570
|
| #define MC5_CH0_PHY_WL_DATA_Control_CS0_B0 0x580
|
| #define MC5_CH0_PHY_WL_DATA_Control_CS0_B1 0x584
|
| #define MC5_CH0_PHY_WL_DATA_Control_CS0_B2 0x588
|
| #define MC5_CH0_PHY_WL_DATA_Control_CS0_B3 0x58C
|
| #define MC5_CH0_PHY_WL_CLK_Control_CS0 0x610
|
| #define MC5_CH0_PHY_WL_AC_Control_0 0x620
|
| #define MC5_CH0_PHY_WL_AC_Control_1 0x624
|
| #define MC5_CH0_PHY_WL_AC_Control_2 0x628
|
| #define MC5_CH0_PHY_RL_Control_CS0_B0 0x640
|
| #define MC5_CH0_PHY_RL_Control_CS0_B1 0x644
|
| #define MC5_CH0_PHY_RL_Control_CS0_B2 0x648
|
| #define MC5_CH0_PHY_RL_Control_CS0_B3 0x64C
|
| #define MC5_TZ_Range0_Low 0x800
|
| #define MC5_TZ_Range0_High 0x804
|
| #define MC5_TZ_Range1_Low 0x808
|
| #define MC5_TZ_Range1_High 0x80C
|
| #define MC5_TZ_Range2_Low 0x810
|
| #define MC5_TZ_Range2_High 0x814
|
| #define MC5_TZ_Range3_Low 0x818
|
| #define MC5_TZ_Range3_High 0x81C
|
| #define MC5_TZ_Range4_Low 0x820
|
| #define MC5_TZ_Range4_High 0x824
|
| #define MC5_TZ_Range5_Low 0x828
|
| #define MC5_TZ_Range5_High 0x82C
|
| #define MC5_TZ_Range6_Low 0x830
|
| #define MC5_TZ_Range6_High 0x834
|
| #define MC5_TZ_Range7_Low 0x838
|
| #define MC5_TZ_Range7_High 0x83C
|
| #define MC5_TZ_Range8_Low 0x840
|
| #define MC5_TZ_Range8_High 0x844
|
| #define MC5_TZ_Range9_Low 0x848
|
| #define MC5_TZ_Range9_High 0x84C
|
| #define MC5_TZ_Range10_Low 0x850
|
| #define MC5_TZ_Range10_High 0x854
|
| #define MC5_TZ_Range11_Low 0x858
|
| #define MC5_TZ_Range11_High 0x85C
|
| #define MC5_TZ_Range12_Low 0x860
|
| #define MC5_TZ_Range12_High 0x864
|
| #define MC5_TZ_Range13_Low 0x868
|
| #define MC5_TZ_Range13_High 0x86C
|
| #define MC5_TZ_Range14_Low 0x870
|
| #define MC5_TZ_Range14_High 0x874
|
| #define MC5_TZ_Range15_Low 0x878
|
| #define MC5_TZ_Range15_High 0x87C
|
| #define MC5_CH1_MMAP0 0xA00
|
| #define MC5_CH1_MMAP0_int 0xA00
|
| #define MC5_CH1_PMAP0 0xA10
|
| #define MC5_CH1_TZ_Range0_CS0 0xA40
|
| #define MC5_CH1_TZ_Range1_CS0 0xA44
|
| #define MC5_CH1_TZ_Range2_CS0 0xA48
|
| #define MC5_CH1_TZ_Range3_CS0 0xA4C
|
| #define MC5_CH1_MC_Control_1 0xAC0
|
| #define MC5_CH1_MC_Control_2 0xAC4
|
| #define MC5_CH1_MC_Control_3 0xAC8
|
| #define MC5_CH1_DRAM_Config_1 0xB00
|
| #define MC5_CH1_DRAM_Config_2 0xB04
|
| #define MC5_CH1_DRAM_Config_5_CS0 0xB10
|
| #define MC5_CH1_DRAM_Control_1 0xB40
|
| #define MC5_CH1_DRAM_Control_2 0xB44
|
| #define MC5_CH1_DRAM_Control_3 0xB48
|
| #define MC5_CH1_DDR_init_timing_control_0 0xB80
|
| #define MC5_CH1_DDR_init_timing_control_1 0xB84
|
| #define MC5_CH1_ZQC_Timing_0 0xB88
|
| #define MC5_CH1_ZQC_Timing_1 0xB8C
|
| #define MC5_CH1_Refresh_timing 0xB90
|
| #define MC5_CH1_SelfRefresh_timing 0xB94
|
| #define MC5_CH1_PowerDown_timing 0xB98
|
| #define MC5_CH1_MRS_timing 0xB9C
|
| #define MC5_CH1_ACT_timing 0xBA0
|
| #define MC5_CH1_PreCharge_Timing 0xBA4
|
| #define MC5_CH1_CAS_RAS_timing 0xBA8
|
| #define MC5_CH1_Off_spec_timing 0xBAC
|
| #define MC5_CH1_PHY_Control_1 0xC00
|
| #define MC5_CH1_PHY_Control_2 0xC04
|
| #define MC5_CH1_PHY_Control_3 0xC08
|
| #define MC5_CH1_PHY_Control_4 0xC0C
|
| #define MC5_CH1_PHY_Control_5 0xC10
|
| #define MC5_CH1_PHY_Control_6 0xC14
|
| #define MC5_CH1_PHY_Control_8 0xC1C
|
| #define MC5_CH1_PHY_Control_9 0xC20
|
| #define MC5_CH1_PHY_Control_10 0xC24
|
| #define MC5_CH1_PHY_Control_11 0xC28
|
| #define MC5_CH1_PHY_Control_12 0xC2C
|
| #define MC5_CH1_PHY_Control_13 0xC30
|
| #define MC5_CH1_PHY_Control_14 0xC34
|
| #define MC5_CH1_PHY_Control_15 0xC38
|
| #define MC5_CH1_PHY_DLL_control_B0 0xD00
|
| #define MC5_CH1_PHY_DLL_control_B1 0xD04
|
| #define MC5_CH1_PHY_DLL_control_B2 0xD08
|
| #define MC5_CH1_PHY_DLL_control_B3 0xD0C
|
| #define MC5_CH1_PHY_DLL_BYTE_SELECT 0xD28
|
| #define MC5_CH1_PHY_DLL_DLY 0xD2C
|
| #define MC5_CH1_PHY_Data_Byte_Control_B0 0xD40
|
| #define MC5_CH1_PHY_Data_Byte_Control_B1 0xD44
|
| #define MC5_CH1_PHY_Data_Byte_Control_B2 0xD48
|
| #define MC5_CH1_PHY_Data_Byte_Control_B3 0xD4C
|
| #define MC5_CH1_PHY_WL_RL_Control 0xD70
|
| #define MC5_CH1_PHY_WL_DATA_Control_CS0_B0 0xD80
|
| #define MC5_CH1_PHY_WL_DATA_Control_CS0_B1 0xD84
|
| #define MC5_CH1_PHY_WL_DATA_Control_CS0_B2 0xD88
|
| #define MC5_CH1_PHY_WL_DATA_Control_CS0_B3 0xD8C
|
| #define MC5_CH1_PHY_WL_CLK_Control_CS0 0xE10
|
| #define MC5_CH1_PHY_WL_AC_Control_0 0xE20
|
| #define MC5_CH1_PHY_WL_AC_Control_1 0xE24
|
| #define MC5_CH1_PHY_WL_AC_Control_2 0xE28
|
| #define MC5_CH1_PHY_RL_Control_CS0_B0 0xE40
|
| #define MC5_CH1_PHY_RL_Control_CS0_B1 0xE44
|
| #define MC5_CH1_PHY_RL_Control_CS0_B2 0xE48
|
| #define MC5_CH1_PHY_RL_Control_CS0_B3 0xE4C
|
| #endif |
