Google Git
Sign in
nest-open-source / manifest_repos / bootloader / 836ad32e08388e0e4ce8d03fe4f14d2c3ea8ba13 / . / berlin_tools / bootloader / include / Firmware_Berlin_BG2CDP_A0 / soc.h
blob: 1c04f088fa58ebfecfc365d71c8590eff0758fc6 [file] [log] [blame]
/********************************************************************************
* Marvell GPL License Option
*
* If you received this File from Marvell, you may opt to use, redistribute and/or
* modify this File in accordance with the terms and conditions of the General
* Public License Version 2, June 1991 (the "GPL License"), a copy of which is
* available along with the File in the license.txt file or by writing to the Free
* Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
* on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
*
* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
* WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
* DISCLAIMED. The GPL License provides additional details about this warranty
* disclaimer.
******************************************************************************/
//////
/// don't edit! auto-generated by docc: soc.h
////////////////////////////////////////////////////////////
#ifndef soc_h
#define soc_h (){}
#include "ctypes.h"
#pragma pack(1)
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _DOCC_H_BITOPS_
#define _DOCC_H_BITOPS_ (){}
#define _bSETMASK_(b) ((b)<32 ? (1<<((b)&31)) : 0)
#define _NSETMASK_(msb,lsb) (_bSETMASK_((msb)+1)-_bSETMASK_(lsb))
#define _bCLRMASK_(b) (~_bSETMASK_(b))
#define _NCLRMASK_(msb,lsb) (~_NSETMASK_(msb,lsb))
#define _BFGET_(r,msb,lsb) (_NSETMASK_((msb)-(lsb),0)&((r)>>(lsb)))
#define _BFSET_(r,msb,lsb,v) do{ (r)&=_NCLRMASK_(msb,lsb); (r)|=_NSETMASK_(msb,lsb)&((v)<<(lsb)); }while(0)
#endif
//////
///
/// $INTERFACE IRQ (4,4)
/// # # ----------------------------------------------------------
/// : mc_irq 0x0
/// : v2gInt 0x1
/// : IntrFigo 0x2
/// : IntrHwBlk 0x3
/// : bcmIntr 0x4
/// : intrPb0 0x5
/// : intrPb1 0x6
/// : intrPb2 0x7
/// : ictlInst0CPUIrq 0x8
/// : ictlInst1CPUIrq 0x9
/// : ictlInst2CPUIrq 0xA
/// : usb0Intr 0xB
/// : nanfIntr 0xC
/// : emmc_int 0xD
/// : ptp1Irq 0xE
/// : sdio_interrupt 0xF
/// : eth1Irq 0x10
/// : sm2socHwInt0 0x11
/// : sm2socHwInt1 0x12
/// : sm2socSwInt 0x13
/// : intrGfx3D 0x14
/// : nCTIIRQ0 0x15
/// : nCTIIRQ1 0x16
/// : nPMUIRQ0 0x17
/// : nPMUIRQ1 0x18
/// : nPMUIRQ2 0x19
/// : nPMUIRQ3 0x1A
/// : nAXIERRIRQ 0x1B
/// : fvs_crc2icu_intr 0x1C
/// : XINTdec 0x1D
/// : intrAhbTrc 0x1E
/// : AxiErrMonIntr 0x1F
/// : AxiWrFiltIntr 0x20
/// : dHubIntrAvio0 0x21
/// : dHubIntrAvio1 0x22
/// : zspInt 0x23
/// : TOTAL_IRQ 0x24
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 0B, bits: 0b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_IRQ
#define h_IRQ (){}
#define IRQ_mc_irq 0x0
#define IRQ_v2gInt 0x1
#define IRQ_IntrFigo 0x2
#define IRQ_IntrHwBlk 0x3
#define IRQ_bcmIntr 0x4
#define IRQ_intrPb0 0x5
#define IRQ_intrPb1 0x6
#define IRQ_intrPb2 0x7
#define IRQ_ictlInst0CPUIrq 0x8
#define IRQ_ictlInst1CPUIrq 0x9
#define IRQ_ictlInst2CPUIrq 0xA
#define IRQ_usb0Intr 0xB
#define IRQ_nanfIntr 0xC
#define IRQ_emmc_int 0xD
#define IRQ_ptp1Irq 0xE
#define IRQ_sdio_interrupt 0xF
#define IRQ_eth1Irq 0x10
#define IRQ_sm2socHwInt0 0x11
#define IRQ_sm2socHwInt1 0x12
#define IRQ_sm2socSwInt 0x13
#define IRQ_intrGfx3D 0x14
#define IRQ_nCTIIRQ0 0x15
#define IRQ_nCTIIRQ1 0x16
#define IRQ_nPMUIRQ0 0x17
#define IRQ_nPMUIRQ1 0x18
#define IRQ_nPMUIRQ2 0x19
#define IRQ_nPMUIRQ3 0x1A
#define IRQ_nAXIERRIRQ 0x1B
#define IRQ_fvs_crc2icu_intr 0x1C
#define IRQ_XINTdec 0x1D
#define IRQ_intrAhbTrc 0x1E
#define IRQ_AxiErrMonIntr 0x1F
#define IRQ_AxiWrFiltIntr 0x20
#define IRQ_dHubIntrAvio0 0x21
#define IRQ_dHubIntrAvio1 0x22
#define IRQ_zspInt 0x23
#define IRQ_TOTAL_IRQ 0x24
///////////////////////////////////////////////////////////
#endif
//////
/// ENDOFINTERFACE: IRQ
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE pll (4,4)
/// ###
/// * SSPLL is a differential, wide range, and low power spread-spectrum PLL that is also capable of
/// * adding in a fixed frequency offset in about 1 ppm/step resolution.
/// * .. Input Frequency: Fref: 8 MHz ~ 2 GHz
/// * Output Frequency: Fout: 9 MHz ~ 3GHz for differential outputs CLKOUTP and CLKOUTN;
/// * 9 MHz ~ 2.1 GHz for single -ended output CLKOUT.
/// * .. Fout(CLKOUT) = Fref *(4*N/M) / CLKOUT_SE_DIV_SEL
/// * Fout(CLKOUTP, CLKOUTN) = Fref*(4*N/M) / CLKOUT_DIFF_DIV_SEL
/// * M: Reference Divider: 1 to 511.
/// * N: Feedback Divider: 1 to 511.
/// * VCODIV: VCO differential divider is controlled by CLKOUT_DIFF_DIV_SEL.
/// * VCO single-ended divider is controlled by CLKOUT_SE_DIV_SEL.
/// * Divider value = 1 1,2,3,4….128.
/// * Update Rate: Fref / M = 8 to 32 MHz (to maintain the PLL stability).
/// * NOTE: Although VCO can be operated between 12 ~ 3 GHz, the 1 ~ 1.5 GHz range is
/// * applicable only in the low power mode and cannot be used with the SSC function. In order to
/// * use the SSC function VCO must be operated above 1.5GHz.
/// * .. Cycle to Cycle Jitter (max): <30 ps.
/// * .. Programmable Reference and Feedback Divider.
/// * .. 1 ppm/step frequency offset resolution. Up to 50,000 ppm without changing the Feedback
/// * Divider setting.
/// * .. SSC frequency range: 30 KHz ~ 100 KHz
/// * .. SSC amplitude range: up to +/-5%. (SSC function is disabled by default.)
/// * .. Supporting both down-spread and center-spread modes.
/// * .. Current consumption( typical corner, AVDD=1.8 V, DVDD=1.05V): see sspll document
/// * .. Locking time: < 50 us
/// * .. Process Node: 28 nm LP
/// * .. Analog Power Supply: 1.8 V (+10%, -5%)
/// * .. Digital Power Supply: 1.05 V (±10%)
/// * Support Low DVDD Mode: Digtial Power Supply = 0.75V ~ 1.32V. See section 2.1 for detail.
/// * .. Output Duty Cycle: 45% - 55% for any post divider ratio
/// * .. Built-in Bandgap circuit.
/// ###
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (P-)
/// ###
/// * PLL Control register
/// ###
/// %unsigned 1 PU 0x1
/// ###
/// * PLL Power-Up
/// * 1: power up.
/// * 0: power down.
/// ###
/// %unsigned 1 RESET 0x0
/// ###
/// * Power On Reset. Active high, reset PLL and all logic.
/// * 1: reset.
/// * 0: no reset.
/// ###
/// %unsigned 1 AVDD1815_SEL 0x1
/// ###
/// * AVDD Select.
/// * Selects whether AVDD is 1.8V
/// * or 1.5V.
/// * 1: 1.8V
/// * 0: 1.5V
/// ###
/// %unsigned 9 REFDIV 0x2
/// ###
/// * Reference Clock Divider
/// * Select.
/// * Divider = REFDIV[8:0]
/// * 9’h000 = divide by 1
/// * 9’h001 = divide by 1
/// * 9’h002 = divide by 2
/// * 9’h003 = divide by 3
/// * ...
/// * 9’h1FF = divide by 511.
/// * REFDIV[8:0] range is 1~250
/// ###
/// %unsigned 9 FBDIV 0x20
/// ###
/// * Feedback Clock Divider Select.
/// * Divider= FBDIV [8:0]
/// * 9’h000 = divide by 1
/// * 9’h001 = divide by 1
/// * 9’h002 = divide by 2
/// * 9’h003 = divide by 3
/// * ...
/// * 9’h1FF = divide by 511.
/// * FBDIV range is 9 to 94
/// ###
/// %unsigned 2 VDDM 0x1
/// ###
/// * VCO Supply Control.
/// * 11: 1.3 V
/// * 10: 1.25 V
/// * 01: 1.2 V
/// * 00: 1.15 V.
/// ###
/// %unsigned 3 VDDL 0x4
/// ###
/// * Internal VDD Supply
/// * Control.
/// * 000:0.9V
/// * 001:0.95V
/// * 010:1V
/// * 011:1.05V
/// * 100:1.1V
/// * 101:1.15V
/// * 110:1.2V
/// * 111:1.2V.
/// ###
/// %unsigned 4 ICP 0x1
/// ###
/// * Charge-pump Current Control Bits.
/// * 0000: 3 uA
/// * 0001: 3.75 uA
/// * 0010: 4.5 uA
/// * 0011: 5.25 uA
/// * 0100: 6 uA
/// * 0101: 7.5 uA
/// * 0110: 9 uA
/// * 0111: 10.5 uA
/// * 1000: 12 uA
/// * 1001: 15 uA
/// * 1010: 18 uA
/// * 1011: 21 uA
/// * 1100: 24 uA
/// * 1101: 30 uA
/// * 1110: 36 uA
/// * 1111: 42 uA.
/// * Note : ICP[3:0] = (10 MHz / Update Rate) * Default.
/// * If PU_BW_SEL = 1, then increase ICP value by 2x
/// ###
/// %unsigned 1 PLL_BW_SEL 0x0
/// ###
/// * PLL Bandwidth Select.
/// * 1: BW x 2
/// * 0: Normal PLL bandwidth.
/// * Note: Use bandwidth x 2 only if update rate is between 16 - 32 MHz.
/// * NOTE: Bandwidth x 2 is for special cases only. If used, the update rate must be between 16 MHz - 32 MHz.
/// ###
/// %% 1 # Stuffing bits...
/// # 0x00004 ctrl1
/// %unsigned 4 KVCO 0xA
/// ###
/// * KVCO Frequency Range
/// * Select.
/// * 0000~0111: Reserved.
/// * 1000:1.2GHz ~ 1.35GHz
/// * 1001:1.35GHz ~ 1.5GHz
/// * 1010:1.5GHz ~ 1.75GHz
/// * 1011:1.75GHz ~ 2.00GHz
/// * 1100: 2GHz ~ 2.2GHz
/// * 1101: 2.2GHz ~ 2.4GHz
/// * 1110: 2.4GHz ~ 2.6GHz
/// * 1111: 2.6GHz ~ 3GHz
/// * SSC mode is only supported for frequency >=2 GHz
/// * FVCO=((4*REFCLK/M)*N)/(1+OFFSET_PERCENT)
/// ###
/// %unsigned 2 CTUNE 0x1
/// ###
/// * VCO Capacitor Select.
/// * 00: No Cap Loading
/// * 01: One Unit Cap Loading
/// * 10: Two Unit Cap Loading
/// * 11: Three Unit Cap Loading.
/// ###
/// %unsigned 3 CLKOUT_DIFF_DIV_SEL 0x2
/// ###
/// * Post Divider For Differential
/// * Output Clock.
/// * 000: 1
/// * 001: 2
/// * 010: 4
/// * 011: 8
/// * 100: 16
/// * 101: 32
/// * 110: 64
/// * 111:128
/// ###
/// %unsigned 3 CLKOUT_SE_DIV_SEL 0x2
/// ###
/// * Post Divider For
/// * Single-ended Output Clock.
/// * 000: 1
/// * 001: 2
/// * 010: 4
/// * 011: 8
/// * 100: 16
/// * 101: 32
/// * 110: 64
/// * 111:128
/// ###
/// %unsigned 1 CLKOUT_SOURCE_SEL 0x1
/// ###
/// * Differential Clock And
/// * Single-ended Clock Source Control.
/// * 0: from the phase interpolator.
/// * 1: from VCO directly.
/// * Note: This is used in test mode only. Select ‘1’ for normal operation.
/// ###
/// %unsigned 1 CLKOUT_DIFF_EN 0x1
/// ###
/// * Differential Clock Enable.
/// * 0:Disable differential clock
/// * 1:Enable differential clock
/// ###
/// %unsigned 1 BYPASS_EN 0x0
/// ###
/// * PLL Clock Bypass Enable.
/// * 1: The PLL is bypassed. CLKOUT is derived from REFCLK.
/// * 0: CLKOUT is derived from the PLL clock.
/// * NOTE: Bypass only works for the single ended clock.
/// * If BYPASS_EN==1. CLKOUT= REFCLK.
/// * Make sure Fvco/CLKOUT_SE_DIV_SEL< 2.1 GHz, when using the bypass function.
/// ###
/// %unsigned 1 CLKOUT_SE_GATING_EN 0x0
/// ###
/// * Clock Output Gating Control.
/// * Selection for using the PLL lock signal to gate the output clock.
/// * 0: The PLL_LOCK signal won't affect the output clock, CLKOUT
/// * 1: Use PLL_LOCK signal to gate the output clock, CLKOUT.
/// ###
/// %unsigned 1 FBCLK_EXT_SEL 0x0
/// ###
/// * External Or Internal Feedback
/// * Clock Select.
/// * 0: select internal feedback clock
/// * 1: select external feedback clock.
/// * Note: For most applications the external feedback clock is not used. In these cases use the default selection "0".
/// ###
/// %unsigned 6 FBCDLY 0x0
/// ###
/// * Fine Tune Delay Select
/// * Between REFCLK And FBCLK_EXT When FBCLK_EXT_SEL = 1.
/// * FBCDLY[5] is the sign bit.
/// * 1 = FBCLK_EXT will lag REFCLK.
/// * 0 = FBCLK_EXT will lead REFCLK.
/// * FBCDLY[4:0] decides the actual amount of delay.
/// * 00000: No delay.
/// * Each additional step has these
/// * delays:
/// * 00h = No delay
/// * 01h = 15 - 50 ps phase difference
/// * 02h = 30 - 100 ps phase difference
/// * 03h = 45 - 150 ps phase difference
/// * ...
/// * 3Fh = 945 ps - 3150 ps phase difference.
/// * Note: Used in DSPLL application, do not use in regular PLL application.
/// ###
/// %unsigned 3 FD 0x4
/// ###
/// * Tune Frequency Detector Precision
/// * FD[0]: Reserved.
/// * FD[2:1] FD precision
/// * 00 +/- 0.1%
/// * 01 +/- 0.2%
/// * 10 +/- 0.4%
/// * 11 +/- 0.8%.
/// ###
/// %unsigned 4 INTPI 0x6
/// ###
/// * Phase Interpolator Bias Current Select.
/// * 1.2 ~ 1.5 GHz NOT SUPPORTED
/// * 0101: (VCO:1.5 ~ 2 GHz)
/// * 0110: (VCO:2 ~ 2.5 GHz)
/// * 1000: (VCO:2.5 ~ 3GHz).
/// * NOTE: VCO running frequency below 1.5 GHz not supported.
/// ###
/// %% 2 # Stuffing bits...
/// # 0x00008 ctrl2
/// %unsigned 3 INTPR 0x4
/// ###
/// * Phase Interpolator Resistor Select.
/// * NOTE: VCO running frequency below 1.5 GHz not supported.
/// ###
/// %unsigned 1 PI_EN 0x0
/// ###
/// * Phase Interpolator Enable.
/// * 1: Enable phase interpolator
/// * 0: Disable phase interpolator.
/// ###
/// %unsigned 1 PI_LOOP_MODE 0x0
/// ###
/// * Phase Interpolator Loop Control.
/// * 1: PI is in the PLL loop.
/// * 0: PI is out of the PLL loop
/// ###
/// %unsigned 1 CLK_DET_EN 0x1
/// ###
/// * PI Output Clock Enable. This selection enables the PI output clock for the internal reset circuit
/// ###
/// %unsigned 1 RESET_PI 0x0
/// ###
/// * External Interpolator Reset.
/// * 1: reset.
/// * 0: no reset.
/// ###
/// %unsigned 1 RESET_SSC 0x0
/// ###
/// * SSC reset
/// * 0 : No reset
/// * 1 : Reset
/// ###
/// %unsigned 1 FREQ_OFFSET_EN 0x0
/// ###
/// * Frequency Offset Enable.
/// * 0: Disable
/// * 1: Enable.
/// ###
/// %unsigned 17 FREQ_OFFSET 0x0
/// ###
/// * Frequency Offset Value
/// * Control.
/// * [16]: Sign-Bit.
/// * 0: Frequency down
/// * 1: Frequency up
/// * [15:0] : 1 LSB 1 ppm, upto 5%
/// * 1LSB=10e6/(4*128 *2048) ppm
/// * [16]=0--->Sign= 1
/// * [16]=1--->Sign= -1
/// * Fout = Fvco/ (1 + Sign* FREQ_OFFSET[15:0] *1LSB)
/// ###
/// %unsigned 1 FREQ_OFFSET_MODE_SELECTION 0x0
/// ###
/// * Frequency Offset Mode Select.
/// * 0: FREQ_OFFSET[16:0] is updated by FREQ_OFFSET_VALID
/// * 1: FREQ_OFFSET[16:0] is sampled by CK_DIV64_OUT
/// * (It has to be valid at the rising edge of CK_DIV64_OUT).
/// * Note: For special application only. Use FREQ_OFFSET_VALID to update FREQ_OFFSET[16:0] by default.
/// ###
/// %unsigned 1 FREQ_OFFSET_VALID 0x0
/// ###
/// * Frequency Offset Value Valid.
/// * Indicates that frequency offset value (FREQ_OFFSET[16:0]) is valid.
/// * Note:
/// * 1) A rising edge will trigger the frequency offset generation circuit to read in the FREQ_OFFSET [16:0] value. The pulse width has to be no less than 50 ns.
/// * 2) This signal is only needed when FREQ_OFFSET_MODE_SELECTION=0.
/// ###
/// %unsigned 1 SSC_CLK_EN 0x0
/// ###
/// * SSC Clock Enable.
/// * This selection enables the PI output clock for SSC digital logic.
/// ###
/// %unsigned 1 SSC_MODE 0x1
/// ###
/// * SSC Mode Select.
/// * 0: center spread
/// * 1: down spread.
/// ###
/// %% 2 # Stuffing bits...
/// # 0x0000C ctrl3
/// %unsigned 16 SSC_FREQ_DIV 0x0
/// ###
/// * SSC Frequency Select.
/// ###
/// %unsigned 11 SSC_RNGE 0x0
/// ###
/// * SSC Range Select. SSC_RNGE[10:0] = Desired SSC amplitude /(SSC_FREQ_DIV[14:0]*2^(-28)).
/// * Rounding to integer required.
/// ###
/// %unsigned 4 TEST_ANA 0x0
/// ###
/// * Analog test point
/// ###
/// %% 1 # Stuffing bits...
/// # 0x00010 ctrl4
/// %unsigned 8 RESERVE_IN 0x0
/// ###
/// * Reserved input pins
/// ###
/// %% 24 # Stuffing bits...
/// @ 0x00014 status (R-)
/// ###
/// * PLL status register
/// ###
/// %unsigned 1 PLL_LOCK
/// ###
/// * PLL Lock Detect.
/// * 1: PLL locked.
/// * 0: PLL not locked.
/// * Note:
/// * After PLL is powered up, wait for 50 us to check for the lock status.
/// * In normal operation, when PLL_LOCK signal is detected low, sample the signal again after 100 us to confirm the status.
/// * This signal is for testing purpose only, do not use it for any functional use.
/// ###
/// %unsigned 1 CLK_CFMOD
/// ###
/// * Clock Mode Output.
/// * • For down spread and
/// * PI_LOOP_MODE = 0, output
/// * is 0.
/// * • For down spread and
/// * PI_LOOP_MODE = 1, output
/// * is 1.
/// * • For center spread, output a
/// * clock with SSC modulation
/// * frequency.
/// ###
/// %unsigned 1 CLK_FMOD
/// ###
/// * Clock Output And Modulation
/// * Frequency.
/// * For down spread, output a clock
/// * with SSC modulation frequency.
/// * For center spread, output a clock
/// * with double SSC modulation
/// * frequency.
/// ###
/// %unsigned 8 RESERVE_OUT
/// ###
/// * Reserve Output Register pins.
/// ###
/// %% 21 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 24B, bits: 141b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_pll
#define h_pll (){}
#define RA_pll_ctrl 0x0000
#define BA_pll_ctrl_PU 0x0000
#define B16pll_ctrl_PU 0x0000
#define LSb32pll_ctrl_PU 0
#define LSb16pll_ctrl_PU 0
#define bpll_ctrl_PU 1
#define MSK32pll_ctrl_PU 0x00000001
#define BA_pll_ctrl_RESET 0x0000
#define B16pll_ctrl_RESET 0x0000
#define LSb32pll_ctrl_RESET 1
#define LSb16pll_ctrl_RESET 1
#define bpll_ctrl_RESET 1
#define MSK32pll_ctrl_RESET 0x00000002
#define BA_pll_ctrl_AVDD1815_SEL 0x0000
#define B16pll_ctrl_AVDD1815_SEL 0x0000
#define LSb32pll_ctrl_AVDD1815_SEL 2
#define LSb16pll_ctrl_AVDD1815_SEL 2
#define bpll_ctrl_AVDD1815_SEL 1
#define MSK32pll_ctrl_AVDD1815_SEL 0x00000004
#define BA_pll_ctrl_REFDIV 0x0000
#define B16pll_ctrl_REFDIV 0x0000
#define LSb32pll_ctrl_REFDIV 3
#define LSb16pll_ctrl_REFDIV 3
#define bpll_ctrl_REFDIV 9
#define MSK32pll_ctrl_REFDIV 0x00000FF8
#define BA_pll_ctrl_FBDIV 0x0001
#define B16pll_ctrl_FBDIV 0x0000
#define LSb32pll_ctrl_FBDIV 12
#define LSb16pll_ctrl_FBDIV 12
#define bpll_ctrl_FBDIV 9
#define MSK32pll_ctrl_FBDIV 0x001FF000
#define BA_pll_ctrl_VDDM 0x0002
#define B16pll_ctrl_VDDM 0x0002
#define LSb32pll_ctrl_VDDM 21
#define LSb16pll_ctrl_VDDM 5
#define bpll_ctrl_VDDM 2
#define MSK32pll_ctrl_VDDM 0x00600000
#define BA_pll_ctrl_VDDL 0x0002
#define B16pll_ctrl_VDDL 0x0002
#define LSb32pll_ctrl_VDDL 23
#define LSb16pll_ctrl_VDDL 7
#define bpll_ctrl_VDDL 3
#define MSK32pll_ctrl_VDDL 0x03800000
#define BA_pll_ctrl_ICP 0x0003
#define B16pll_ctrl_ICP 0x0002
#define LSb32pll_ctrl_ICP 26
#define LSb16pll_ctrl_ICP 10
#define bpll_ctrl_ICP 4
#define MSK32pll_ctrl_ICP 0x3C000000
#define BA_pll_ctrl_PLL_BW_SEL 0x0003
#define B16pll_ctrl_PLL_BW_SEL 0x0002
#define LSb32pll_ctrl_PLL_BW_SEL 30
#define LSb16pll_ctrl_PLL_BW_SEL 14
#define bpll_ctrl_PLL_BW_SEL 1
#define MSK32pll_ctrl_PLL_BW_SEL 0x40000000
#define RA_pll_ctrl1 0x0004
#define BA_pll_ctrl_KVCO 0x0004
#define B16pll_ctrl_KVCO 0x0004
#define LSb32pll_ctrl_KVCO 0
#define LSb16pll_ctrl_KVCO 0
#define bpll_ctrl_KVCO 4
#define MSK32pll_ctrl_KVCO 0x0000000F
#define BA_pll_ctrl_CTUNE 0x0004
#define B16pll_ctrl_CTUNE 0x0004
#define LSb32pll_ctrl_CTUNE 4
#define LSb16pll_ctrl_CTUNE 4
#define bpll_ctrl_CTUNE 2
#define MSK32pll_ctrl_CTUNE 0x00000030
#define BA_pll_ctrl_CLKOUT_DIFF_DIV_SEL 0x0004
#define B16pll_ctrl_CLKOUT_DIFF_DIV_SEL 0x0004
#define LSb32pll_ctrl_CLKOUT_DIFF_DIV_SEL 6
#define LSb16pll_ctrl_CLKOUT_DIFF_DIV_SEL 6
#define bpll_ctrl_CLKOUT_DIFF_DIV_SEL 3
#define MSK32pll_ctrl_CLKOUT_DIFF_DIV_SEL 0x000001C0
#define BA_pll_ctrl_CLKOUT_SE_DIV_SEL 0x0005
#define B16pll_ctrl_CLKOUT_SE_DIV_SEL 0x0004
#define LSb32pll_ctrl_CLKOUT_SE_DIV_SEL 9
#define LSb16pll_ctrl_CLKOUT_SE_DIV_SEL 9
#define bpll_ctrl_CLKOUT_SE_DIV_SEL 3
#define MSK32pll_ctrl_CLKOUT_SE_DIV_SEL 0x00000E00
#define BA_pll_ctrl_CLKOUT_SOURCE_SEL 0x0005
#define B16pll_ctrl_CLKOUT_SOURCE_SEL 0x0004
#define LSb32pll_ctrl_CLKOUT_SOURCE_SEL 12
#define LSb16pll_ctrl_CLKOUT_SOURCE_SEL 12
#define bpll_ctrl_CLKOUT_SOURCE_SEL 1
#define MSK32pll_ctrl_CLKOUT_SOURCE_SEL 0x00001000
#define BA_pll_ctrl_CLKOUT_DIFF_EN 0x0005
#define B16pll_ctrl_CLKOUT_DIFF_EN 0x0004
#define LSb32pll_ctrl_CLKOUT_DIFF_EN 13
#define LSb16pll_ctrl_CLKOUT_DIFF_EN 13
#define bpll_ctrl_CLKOUT_DIFF_EN 1
#define MSK32pll_ctrl_CLKOUT_DIFF_EN 0x00002000
#define BA_pll_ctrl_BYPASS_EN 0x0005
#define B16pll_ctrl_BYPASS_EN 0x0004
#define LSb32pll_ctrl_BYPASS_EN 14
#define LSb16pll_ctrl_BYPASS_EN 14
#define bpll_ctrl_BYPASS_EN 1
#define MSK32pll_ctrl_BYPASS_EN 0x00004000
#define BA_pll_ctrl_CLKOUT_SE_GATING_EN 0x0005
#define B16pll_ctrl_CLKOUT_SE_GATING_EN 0x0004
#define LSb32pll_ctrl_CLKOUT_SE_GATING_EN 15
#define LSb16pll_ctrl_CLKOUT_SE_GATING_EN 15
#define bpll_ctrl_CLKOUT_SE_GATING_EN 1
#define MSK32pll_ctrl_CLKOUT_SE_GATING_EN 0x00008000
#define BA_pll_ctrl_FBCLK_EXT_SEL 0x0006
#define B16pll_ctrl_FBCLK_EXT_SEL 0x0006
#define LSb32pll_ctrl_FBCLK_EXT_SEL 16
#define LSb16pll_ctrl_FBCLK_EXT_SEL 0
#define bpll_ctrl_FBCLK_EXT_SEL 1
#define MSK32pll_ctrl_FBCLK_EXT_SEL 0x00010000
#define BA_pll_ctrl_FBCDLY 0x0006
#define B16pll_ctrl_FBCDLY 0x0006
#define LSb32pll_ctrl_FBCDLY 17
#define LSb16pll_ctrl_FBCDLY 1
#define bpll_ctrl_FBCDLY 6
#define MSK32pll_ctrl_FBCDLY 0x007E0000
#define BA_pll_ctrl_FD 0x0006
#define B16pll_ctrl_FD 0x0006
#define LSb32pll_ctrl_FD 23
#define LSb16pll_ctrl_FD 7
#define bpll_ctrl_FD 3
#define MSK32pll_ctrl_FD 0x03800000
#define BA_pll_ctrl_INTPI 0x0007
#define B16pll_ctrl_INTPI 0x0006
#define LSb32pll_ctrl_INTPI 26
#define LSb16pll_ctrl_INTPI 10
#define bpll_ctrl_INTPI 4
#define MSK32pll_ctrl_INTPI 0x3C000000
#define RA_pll_ctrl2 0x0008
#define BA_pll_ctrl_INTPR 0x0008
#define B16pll_ctrl_INTPR 0x0008
#define LSb32pll_ctrl_INTPR 0
#define LSb16pll_ctrl_INTPR 0
#define bpll_ctrl_INTPR 3
#define MSK32pll_ctrl_INTPR 0x00000007
#define BA_pll_ctrl_PI_EN 0x0008
#define B16pll_ctrl_PI_EN 0x0008
#define LSb32pll_ctrl_PI_EN 3
#define LSb16pll_ctrl_PI_EN 3
#define bpll_ctrl_PI_EN 1
#define MSK32pll_ctrl_PI_EN 0x00000008
#define BA_pll_ctrl_PI_LOOP_MODE 0x0008
#define B16pll_ctrl_PI_LOOP_MODE 0x0008
#define LSb32pll_ctrl_PI_LOOP_MODE 4
#define LSb16pll_ctrl_PI_LOOP_MODE 4
#define bpll_ctrl_PI_LOOP_MODE 1
#define MSK32pll_ctrl_PI_LOOP_MODE 0x00000010
#define BA_pll_ctrl_CLK_DET_EN 0x0008
#define B16pll_ctrl_CLK_DET_EN 0x0008
#define LSb32pll_ctrl_CLK_DET_EN 5
#define LSb16pll_ctrl_CLK_DET_EN 5
#define bpll_ctrl_CLK_DET_EN 1
#define MSK32pll_ctrl_CLK_DET_EN 0x00000020
#define BA_pll_ctrl_RESET_PI 0x0008
#define B16pll_ctrl_RESET_PI 0x0008
#define LSb32pll_ctrl_RESET_PI 6
#define LSb16pll_ctrl_RESET_PI 6
#define bpll_ctrl_RESET_PI 1
#define MSK32pll_ctrl_RESET_PI 0x00000040
#define BA_pll_ctrl_RESET_SSC 0x0008
#define B16pll_ctrl_RESET_SSC 0x0008
#define LSb32pll_ctrl_RESET_SSC 7
#define LSb16pll_ctrl_RESET_SSC 7
#define bpll_ctrl_RESET_SSC 1
#define MSK32pll_ctrl_RESET_SSC 0x00000080
#define BA_pll_ctrl_FREQ_OFFSET_EN 0x0009
#define B16pll_ctrl_FREQ_OFFSET_EN 0x0008
#define LSb32pll_ctrl_FREQ_OFFSET_EN 8
#define LSb16pll_ctrl_FREQ_OFFSET_EN 8
#define bpll_ctrl_FREQ_OFFSET_EN 1
#define MSK32pll_ctrl_FREQ_OFFSET_EN 0x00000100
#define BA_pll_ctrl_FREQ_OFFSET 0x0009
#define B16pll_ctrl_FREQ_OFFSET 0x0008
#define LSb32pll_ctrl_FREQ_OFFSET 9
#define LSb16pll_ctrl_FREQ_OFFSET 9
#define bpll_ctrl_FREQ_OFFSET 17
#define MSK32pll_ctrl_FREQ_OFFSET 0x03FFFE00
#define BA_pll_ctrl_FREQ_OFFSET_MODE_SELECTION 0x000B
#define B16pll_ctrl_FREQ_OFFSET_MODE_SELECTION 0x000A
#define LSb32pll_ctrl_FREQ_OFFSET_MODE_SELECTION 26
#define LSb16pll_ctrl_FREQ_OFFSET_MODE_SELECTION 10
#define bpll_ctrl_FREQ_OFFSET_MODE_SELECTION 1
#define MSK32pll_ctrl_FREQ_OFFSET_MODE_SELECTION 0x04000000
#define BA_pll_ctrl_FREQ_OFFSET_VALID 0x000B
#define B16pll_ctrl_FREQ_OFFSET_VALID 0x000A
#define LSb32pll_ctrl_FREQ_OFFSET_VALID 27
#define LSb16pll_ctrl_FREQ_OFFSET_VALID 11
#define bpll_ctrl_FREQ_OFFSET_VALID 1
#define MSK32pll_ctrl_FREQ_OFFSET_VALID 0x08000000
#define BA_pll_ctrl_SSC_CLK_EN 0x000B
#define B16pll_ctrl_SSC_CLK_EN 0x000A
#define LSb32pll_ctrl_SSC_CLK_EN 28
#define LSb16pll_ctrl_SSC_CLK_EN 12
#define bpll_ctrl_SSC_CLK_EN 1
#define MSK32pll_ctrl_SSC_CLK_EN 0x10000000
#define BA_pll_ctrl_SSC_MODE 0x000B
#define B16pll_ctrl_SSC_MODE 0x000A
#define LSb32pll_ctrl_SSC_MODE 29
#define LSb16pll_ctrl_SSC_MODE 13
#define bpll_ctrl_SSC_MODE 1
#define MSK32pll_ctrl_SSC_MODE 0x20000000
#define RA_pll_ctrl3 0x000C
#define BA_pll_ctrl_SSC_FREQ_DIV 0x000C
#define B16pll_ctrl_SSC_FREQ_DIV 0x000C
#define LSb32pll_ctrl_SSC_FREQ_DIV 0
#define LSb16pll_ctrl_SSC_FREQ_DIV 0
#define bpll_ctrl_SSC_FREQ_DIV 16
#define MSK32pll_ctrl_SSC_FREQ_DIV 0x0000FFFF
#define BA_pll_ctrl_SSC_RNGE 0x000E
#define B16pll_ctrl_SSC_RNGE 0x000E
#define LSb32pll_ctrl_SSC_RNGE 16
#define LSb16pll_ctrl_SSC_RNGE 0
#define bpll_ctrl_SSC_RNGE 11
#define MSK32pll_ctrl_SSC_RNGE 0x07FF0000
#define BA_pll_ctrl_TEST_ANA 0x000F
#define B16pll_ctrl_TEST_ANA 0x000E
#define LSb32pll_ctrl_TEST_ANA 27
#define LSb16pll_ctrl_TEST_ANA 11
#define bpll_ctrl_TEST_ANA 4
#define MSK32pll_ctrl_TEST_ANA 0x78000000
#define RA_pll_ctrl4 0x0010
#define BA_pll_ctrl_RESERVE_IN 0x0010
#define B16pll_ctrl_RESERVE_IN 0x0010
#define LSb32pll_ctrl_RESERVE_IN 0
#define LSb16pll_ctrl_RESERVE_IN 0
#define bpll_ctrl_RESERVE_IN 8
#define MSK32pll_ctrl_RESERVE_IN 0x000000FF
///////////////////////////////////////////////////////////
#define RA_pll_status 0x0014
#define BA_pll_status_PLL_LOCK 0x0014
#define B16pll_status_PLL_LOCK 0x0014
#define LSb32pll_status_PLL_LOCK 0
#define LSb16pll_status_PLL_LOCK 0
#define bpll_status_PLL_LOCK 1
#define MSK32pll_status_PLL_LOCK 0x00000001
#define BA_pll_status_CLK_CFMOD 0x0014
#define B16pll_status_CLK_CFMOD 0x0014
#define LSb32pll_status_CLK_CFMOD 1
#define LSb16pll_status_CLK_CFMOD 1
#define bpll_status_CLK_CFMOD 1
#define MSK32pll_status_CLK_CFMOD 0x00000002
#define BA_pll_status_CLK_FMOD 0x0014
#define B16pll_status_CLK_FMOD 0x0014
#define LSb32pll_status_CLK_FMOD 2
#define LSb16pll_status_CLK_FMOD 2
#define bpll_status_CLK_FMOD 1
#define MSK32pll_status_CLK_FMOD 0x00000004
#define BA_pll_status_RESERVE_OUT 0x0014
#define B16pll_status_RESERVE_OUT 0x0014
#define LSb32pll_status_RESERVE_OUT 3
#define LSb16pll_status_RESERVE_OUT 3
#define bpll_status_RESERVE_OUT 8
#define MSK32pll_status_RESERVE_OUT 0x000007F8
///////////////////////////////////////////////////////////
typedef struct SIE_pll {
///////////////////////////////////////////////////////////
#define GET32pll_ctrl_PU(r32) _BFGET_(r32, 0, 0)
#define SET32pll_ctrl_PU(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16pll_ctrl_PU(r16) _BFGET_(r16, 0, 0)
#define SET16pll_ctrl_PU(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32pll_ctrl_RESET(r32) _BFGET_(r32, 1, 1)
#define SET32pll_ctrl_RESET(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16pll_ctrl_RESET(r16) _BFGET_(r16, 1, 1)
#define SET16pll_ctrl_RESET(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32pll_ctrl_AVDD1815_SEL(r32) _BFGET_(r32, 2, 2)
#define SET32pll_ctrl_AVDD1815_SEL(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16pll_ctrl_AVDD1815_SEL(r16) _BFGET_(r16, 2, 2)
#define SET16pll_ctrl_AVDD1815_SEL(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32pll_ctrl_REFDIV(r32) _BFGET_(r32,11, 3)
#define SET32pll_ctrl_REFDIV(r32,v) _BFSET_(r32,11, 3,v)
#define GET16pll_ctrl_REFDIV(r16) _BFGET_(r16,11, 3)
#define SET16pll_ctrl_REFDIV(r16,v) _BFSET_(r16,11, 3,v)
#define GET32pll_ctrl_FBDIV(r32) _BFGET_(r32,20,12)
#define SET32pll_ctrl_FBDIV(r32,v) _BFSET_(r32,20,12,v)
#define GET32pll_ctrl_VDDM(r32) _BFGET_(r32,22,21)
#define SET32pll_ctrl_VDDM(r32,v) _BFSET_(r32,22,21,v)
#define GET16pll_ctrl_VDDM(r16) _BFGET_(r16, 6, 5)
#define SET16pll_ctrl_VDDM(r16,v) _BFSET_(r16, 6, 5,v)
#define GET32pll_ctrl_VDDL(r32) _BFGET_(r32,25,23)
#define SET32pll_ctrl_VDDL(r32,v) _BFSET_(r32,25,23,v)
#define GET16pll_ctrl_VDDL(r16) _BFGET_(r16, 9, 7)
#define SET16pll_ctrl_VDDL(r16,v) _BFSET_(r16, 9, 7,v)
#define GET32pll_ctrl_ICP(r32) _BFGET_(r32,29,26)
#define SET32pll_ctrl_ICP(r32,v) _BFSET_(r32,29,26,v)
#define GET16pll_ctrl_ICP(r16) _BFGET_(r16,13,10)
#define SET16pll_ctrl_ICP(r16,v) _BFSET_(r16,13,10,v)
#define GET32pll_ctrl_PLL_BW_SEL(r32) _BFGET_(r32,30,30)
#define SET32pll_ctrl_PLL_BW_SEL(r32,v) _BFSET_(r32,30,30,v)
#define GET16pll_ctrl_PLL_BW_SEL(r16) _BFGET_(r16,14,14)
#define SET16pll_ctrl_PLL_BW_SEL(r16,v) _BFSET_(r16,14,14,v)
#define w32pll_ctrl {\
UNSG32 uctrl_PU : 1;\
UNSG32 uctrl_RESET : 1;\
UNSG32 uctrl_AVDD1815_SEL : 1;\
UNSG32 uctrl_REFDIV : 9;\
UNSG32 uctrl_FBDIV : 9;\
UNSG32 uctrl_VDDM : 2;\
UNSG32 uctrl_VDDL : 3;\
UNSG32 uctrl_ICP : 4;\
UNSG32 uctrl_PLL_BW_SEL : 1;\
UNSG32 RSVDx0_b31 : 1;\
}
union { UNSG32 u32pll_ctrl;
struct w32pll_ctrl;
};
#define GET32pll_ctrl_KVCO(r32) _BFGET_(r32, 3, 0)
#define SET32pll_ctrl_KVCO(r32,v) _BFSET_(r32, 3, 0,v)
#define GET16pll_ctrl_KVCO(r16) _BFGET_(r16, 3, 0)
#define SET16pll_ctrl_KVCO(r16,v) _BFSET_(r16, 3, 0,v)
#define GET32pll_ctrl_CTUNE(r32) _BFGET_(r32, 5, 4)
#define SET32pll_ctrl_CTUNE(r32,v) _BFSET_(r32, 5, 4,v)
#define GET16pll_ctrl_CTUNE(r16) _BFGET_(r16, 5, 4)
#define SET16pll_ctrl_CTUNE(r16,v) _BFSET_(r16, 5, 4,v)
#define GET32pll_ctrl_CLKOUT_DIFF_DIV_SEL(r32) _BFGET_(r32, 8, 6)
#define SET32pll_ctrl_CLKOUT_DIFF_DIV_SEL(r32,v) _BFSET_(r32, 8, 6,v)
#define GET16pll_ctrl_CLKOUT_DIFF_DIV_SEL(r16) _BFGET_(r16, 8, 6)
#define SET16pll_ctrl_CLKOUT_DIFF_DIV_SEL(r16,v) _BFSET_(r16, 8, 6,v)
#define GET32pll_ctrl_CLKOUT_SE_DIV_SEL(r32) _BFGET_(r32,11, 9)
#define SET32pll_ctrl_CLKOUT_SE_DIV_SEL(r32,v) _BFSET_(r32,11, 9,v)
#define GET16pll_ctrl_CLKOUT_SE_DIV_SEL(r16) _BFGET_(r16,11, 9)
#define SET16pll_ctrl_CLKOUT_SE_DIV_SEL(r16,v) _BFSET_(r16,11, 9,v)
#define GET32pll_ctrl_CLKOUT_SOURCE_SEL(r32) _BFGET_(r32,12,12)
#define SET32pll_ctrl_CLKOUT_SOURCE_SEL(r32,v) _BFSET_(r32,12,12,v)
#define GET16pll_ctrl_CLKOUT_SOURCE_SEL(r16) _BFGET_(r16,12,12)
#define SET16pll_ctrl_CLKOUT_SOURCE_SEL(r16,v) _BFSET_(r16,12,12,v)
#define GET32pll_ctrl_CLKOUT_DIFF_EN(r32) _BFGET_(r32,13,13)
#define SET32pll_ctrl_CLKOUT_DIFF_EN(r32,v) _BFSET_(r32,13,13,v)
#define GET16pll_ctrl_CLKOUT_DIFF_EN(r16) _BFGET_(r16,13,13)
#define SET16pll_ctrl_CLKOUT_DIFF_EN(r16,v) _BFSET_(r16,13,13,v)
#define GET32pll_ctrl_BYPASS_EN(r32) _BFGET_(r32,14,14)
#define SET32pll_ctrl_BYPASS_EN(r32,v) _BFSET_(r32,14,14,v)
#define GET16pll_ctrl_BYPASS_EN(r16) _BFGET_(r16,14,14)
#define SET16pll_ctrl_BYPASS_EN(r16,v) _BFSET_(r16,14,14,v)
#define GET32pll_ctrl_CLKOUT_SE_GATING_EN(r32) _BFGET_(r32,15,15)
#define SET32pll_ctrl_CLKOUT_SE_GATING_EN(r32,v) _BFSET_(r32,15,15,v)
#define GET16pll_ctrl_CLKOUT_SE_GATING_EN(r16) _BFGET_(r16,15,15)
#define SET16pll_ctrl_CLKOUT_SE_GATING_EN(r16,v) _BFSET_(r16,15,15,v)
#define GET32pll_ctrl_FBCLK_EXT_SEL(r32) _BFGET_(r32,16,16)
#define SET32pll_ctrl_FBCLK_EXT_SEL(r32,v) _BFSET_(r32,16,16,v)
#define GET16pll_ctrl_FBCLK_EXT_SEL(r16) _BFGET_(r16, 0, 0)
#define SET16pll_ctrl_FBCLK_EXT_SEL(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32pll_ctrl_FBCDLY(r32) _BFGET_(r32,22,17)
#define SET32pll_ctrl_FBCDLY(r32,v) _BFSET_(r32,22,17,v)
#define GET16pll_ctrl_FBCDLY(r16) _BFGET_(r16, 6, 1)
#define SET16pll_ctrl_FBCDLY(r16,v) _BFSET_(r16, 6, 1,v)
#define GET32pll_ctrl_FD(r32) _BFGET_(r32,25,23)
#define SET32pll_ctrl_FD(r32,v) _BFSET_(r32,25,23,v)
#define GET16pll_ctrl_FD(r16) _BFGET_(r16, 9, 7)
#define SET16pll_ctrl_FD(r16,v) _BFSET_(r16, 9, 7,v)
#define GET32pll_ctrl_INTPI(r32) _BFGET_(r32,29,26)
#define SET32pll_ctrl_INTPI(r32,v) _BFSET_(r32,29,26,v)
#define GET16pll_ctrl_INTPI(r16) _BFGET_(r16,13,10)
#define SET16pll_ctrl_INTPI(r16,v) _BFSET_(r16,13,10,v)
#define w32pll_ctrl1 {\
UNSG32 uctrl_KVCO : 4;\
UNSG32 uctrl_CTUNE : 2;\
UNSG32 uctrl_CLKOUT_DIFF_DIV_SEL : 3;\
UNSG32 uctrl_CLKOUT_SE_DIV_SEL : 3;\
UNSG32 uctrl_CLKOUT_SOURCE_SEL : 1;\
UNSG32 uctrl_CLKOUT_DIFF_EN : 1;\
UNSG32 uctrl_BYPASS_EN : 1;\
UNSG32 uctrl_CLKOUT_SE_GATING_EN : 1;\
UNSG32 uctrl_FBCLK_EXT_SEL : 1;\
UNSG32 uctrl_FBCDLY : 6;\
UNSG32 uctrl_FD : 3;\
UNSG32 uctrl_INTPI : 4;\
UNSG32 RSVDx4_b30 : 2;\
}
union { UNSG32 u32pll_ctrl1;
struct w32pll_ctrl1;
};
#define GET32pll_ctrl_INTPR(r32) _BFGET_(r32, 2, 0)
#define SET32pll_ctrl_INTPR(r32,v) _BFSET_(r32, 2, 0,v)
#define GET16pll_ctrl_INTPR(r16) _BFGET_(r16, 2, 0)
#define SET16pll_ctrl_INTPR(r16,v) _BFSET_(r16, 2, 0,v)
#define GET32pll_ctrl_PI_EN(r32) _BFGET_(r32, 3, 3)
#define SET32pll_ctrl_PI_EN(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16pll_ctrl_PI_EN(r16) _BFGET_(r16, 3, 3)
#define SET16pll_ctrl_PI_EN(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32pll_ctrl_PI_LOOP_MODE(r32) _BFGET_(r32, 4, 4)
#define SET32pll_ctrl_PI_LOOP_MODE(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16pll_ctrl_PI_LOOP_MODE(r16) _BFGET_(r16, 4, 4)
#define SET16pll_ctrl_PI_LOOP_MODE(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32pll_ctrl_CLK_DET_EN(r32) _BFGET_(r32, 5, 5)
#define SET32pll_ctrl_CLK_DET_EN(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16pll_ctrl_CLK_DET_EN(r16) _BFGET_(r16, 5, 5)
#define SET16pll_ctrl_CLK_DET_EN(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32pll_ctrl_RESET_PI(r32) _BFGET_(r32, 6, 6)
#define SET32pll_ctrl_RESET_PI(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16pll_ctrl_RESET_PI(r16) _BFGET_(r16, 6, 6)
#define SET16pll_ctrl_RESET_PI(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32pll_ctrl_RESET_SSC(r32) _BFGET_(r32, 7, 7)
#define SET32pll_ctrl_RESET_SSC(r32,v) _BFSET_(r32, 7, 7,v)
#define GET16pll_ctrl_RESET_SSC(r16) _BFGET_(r16, 7, 7)
#define SET16pll_ctrl_RESET_SSC(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32pll_ctrl_FREQ_OFFSET_EN(r32) _BFGET_(r32, 8, 8)
#define SET32pll_ctrl_FREQ_OFFSET_EN(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16pll_ctrl_FREQ_OFFSET_EN(r16) _BFGET_(r16, 8, 8)
#define SET16pll_ctrl_FREQ_OFFSET_EN(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32pll_ctrl_FREQ_OFFSET(r32) _BFGET_(r32,25, 9)
#define SET32pll_ctrl_FREQ_OFFSET(r32,v) _BFSET_(r32,25, 9,v)
#define GET32pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r32) _BFGET_(r32,26,26)
#define SET32pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r32,v) _BFSET_(r32,26,26,v)
#define GET16pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r16) _BFGET_(r16,10,10)
#define SET16pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r16,v) _BFSET_(r16,10,10,v)
#define GET32pll_ctrl_FREQ_OFFSET_VALID(r32) _BFGET_(r32,27,27)
#define SET32pll_ctrl_FREQ_OFFSET_VALID(r32,v) _BFSET_(r32,27,27,v)
#define GET16pll_ctrl_FREQ_OFFSET_VALID(r16) _BFGET_(r16,11,11)
#define SET16pll_ctrl_FREQ_OFFSET_VALID(r16,v) _BFSET_(r16,11,11,v)
#define GET32pll_ctrl_SSC_CLK_EN(r32) _BFGET_(r32,28,28)
#define SET32pll_ctrl_SSC_CLK_EN(r32,v) _BFSET_(r32,28,28,v)
#define GET16pll_ctrl_SSC_CLK_EN(r16) _BFGET_(r16,12,12)
#define SET16pll_ctrl_SSC_CLK_EN(r16,v) _BFSET_(r16,12,12,v)
#define GET32pll_ctrl_SSC_MODE(r32) _BFGET_(r32,29,29)
#define SET32pll_ctrl_SSC_MODE(r32,v) _BFSET_(r32,29,29,v)
#define GET16pll_ctrl_SSC_MODE(r16) _BFGET_(r16,13,13)
#define SET16pll_ctrl_SSC_MODE(r16,v) _BFSET_(r16,13,13,v)
#define w32pll_ctrl2 {\
UNSG32 uctrl_INTPR : 3;\
UNSG32 uctrl_PI_EN : 1;\
UNSG32 uctrl_PI_LOOP_MODE : 1;\
UNSG32 uctrl_CLK_DET_EN : 1;\
UNSG32 uctrl_RESET_PI : 1;\
UNSG32 uctrl_RESET_SSC : 1;\
UNSG32 uctrl_FREQ_OFFSET_EN : 1;\
UNSG32 uctrl_FREQ_OFFSET : 17;\
UNSG32 uctrl_FREQ_OFFSET_MODE_SELECTION : 1;\
UNSG32 uctrl_FREQ_OFFSET_VALID : 1;\
UNSG32 uctrl_SSC_CLK_EN : 1;\
UNSG32 uctrl_SSC_MODE : 1;\
UNSG32 RSVDx8_b30 : 2;\
}
union { UNSG32 u32pll_ctrl2;
struct w32pll_ctrl2;
};
#define GET32pll_ctrl_SSC_FREQ_DIV(r32) _BFGET_(r32,15, 0)
#define SET32pll_ctrl_SSC_FREQ_DIV(r32,v) _BFSET_(r32,15, 0,v)
#define GET16pll_ctrl_SSC_FREQ_DIV(r16) _BFGET_(r16,15, 0)
#define SET16pll_ctrl_SSC_FREQ_DIV(r16,v) _BFSET_(r16,15, 0,v)
#define GET32pll_ctrl_SSC_RNGE(r32) _BFGET_(r32,26,16)
#define SET32pll_ctrl_SSC_RNGE(r32,v) _BFSET_(r32,26,16,v)
#define GET16pll_ctrl_SSC_RNGE(r16) _BFGET_(r16,10, 0)
#define SET16pll_ctrl_SSC_RNGE(r16,v) _BFSET_(r16,10, 0,v)
#define GET32pll_ctrl_TEST_ANA(r32) _BFGET_(r32,30,27)
#define SET32pll_ctrl_TEST_ANA(r32,v) _BFSET_(r32,30,27,v)
#define GET16pll_ctrl_TEST_ANA(r16) _BFGET_(r16,14,11)
#define SET16pll_ctrl_TEST_ANA(r16,v) _BFSET_(r16,14,11,v)
#define w32pll_ctrl3 {\
UNSG32 uctrl_SSC_FREQ_DIV : 16;\
UNSG32 uctrl_SSC_RNGE : 11;\
UNSG32 uctrl_TEST_ANA : 4;\
UNSG32 RSVDxC_b31 : 1;\
}
union { UNSG32 u32pll_ctrl3;
struct w32pll_ctrl3;
};
#define GET32pll_ctrl_RESERVE_IN(r32) _BFGET_(r32, 7, 0)
#define SET32pll_ctrl_RESERVE_IN(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16pll_ctrl_RESERVE_IN(r16) _BFGET_(r16, 7, 0)
#define SET16pll_ctrl_RESERVE_IN(r16,v) _BFSET_(r16, 7, 0,v)
#define w32pll_ctrl4 {\
UNSG32 uctrl_RESERVE_IN : 8;\
UNSG32 RSVDx10_b8 : 24;\
}
union { UNSG32 u32pll_ctrl4;
struct w32pll_ctrl4;
};
///////////////////////////////////////////////////////////
#define GET32pll_status_PLL_LOCK(r32) _BFGET_(r32, 0, 0)
#define SET32pll_status_PLL_LOCK(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16pll_status_PLL_LOCK(r16) _BFGET_(r16, 0, 0)
#define SET16pll_status_PLL_LOCK(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32pll_status_CLK_CFMOD(r32) _BFGET_(r32, 1, 1)
#define SET32pll_status_CLK_CFMOD(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16pll_status_CLK_CFMOD(r16) _BFGET_(r16, 1, 1)
#define SET16pll_status_CLK_CFMOD(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32pll_status_CLK_FMOD(r32) _BFGET_(r32, 2, 2)
#define SET32pll_status_CLK_FMOD(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16pll_status_CLK_FMOD(r16) _BFGET_(r16, 2, 2)
#define SET16pll_status_CLK_FMOD(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32pll_status_RESERVE_OUT(r32) _BFGET_(r32,10, 3)
#define SET32pll_status_RESERVE_OUT(r32,v) _BFSET_(r32,10, 3,v)
#define GET16pll_status_RESERVE_OUT(r16) _BFGET_(r16,10, 3)
#define SET16pll_status_RESERVE_OUT(r16,v) _BFSET_(r16,10, 3,v)
#define w32pll_status {\
UNSG32 ustatus_PLL_LOCK : 1;\
UNSG32 ustatus_CLK_CFMOD : 1;\
UNSG32 ustatus_CLK_FMOD : 1;\
UNSG32 ustatus_RESERVE_OUT : 8;\
UNSG32 RSVDx14_b11 : 21;\
}
union { UNSG32 u32pll_status;
struct w32pll_status;
};
///////////////////////////////////////////////////////////
} SIE_pll;
typedef union T32pll_ctrl
{ UNSG32 u32;
struct w32pll_ctrl;
} T32pll_ctrl;
typedef union T32pll_ctrl1
{ UNSG32 u32;
struct w32pll_ctrl1;
} T32pll_ctrl1;
typedef union T32pll_ctrl2
{ UNSG32 u32;
struct w32pll_ctrl2;
} T32pll_ctrl2;
typedef union T32pll_ctrl3
{ UNSG32 u32;
struct w32pll_ctrl3;
} T32pll_ctrl3;
typedef union T32pll_ctrl4
{ UNSG32 u32;
struct w32pll_ctrl4;
} T32pll_ctrl4;
typedef union T32pll_status
{ UNSG32 u32;
struct w32pll_status;
} T32pll_status;
///////////////////////////////////////////////////////////
typedef union Tpll_ctrl
{ UNSG32 u32[5];
struct {
struct w32pll_ctrl;
struct w32pll_ctrl1;
struct w32pll_ctrl2;
struct w32pll_ctrl3;
struct w32pll_ctrl4;
};
} Tpll_ctrl;
typedef union Tpll_status
{ UNSG32 u32[1];
struct {
struct w32pll_status;
};
} Tpll_status;
///////////////////////////////////////////////////////////
SIGN32 pll_drvrd(SIE_pll *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 pll_drvwr(SIE_pll *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void pll_reset(SIE_pll *p);
SIGN32 pll_cmp (SIE_pll *p, SIE_pll *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define pll_check(p,pie,pfx,hLOG) pll_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define pll_print(p, pfx,hLOG) pll_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: pll
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE MoltresReg biu (4,4)
/// ###
/// * All the controls for Moltres (PJ4-MP) sub-system (moltres_mp_ip).
/// ###
/// # # ----------------------------------------------------------
/// @ 0x00000 CTRL5 (RW-)
/// ###
/// * CoreSight related controls
/// ###
/// %unsigned 1 dbgen 0x1
/// ###
/// * Invasive Debug Enable.
/// ###
/// %unsigned 1 spiden 0x1
/// ###
/// * Secure Invasive Debug Enable
/// ###
/// %unsigned 1 niden 0x1
/// ###
/// * Non Invasive Debug Enable
/// ###
/// %unsigned 1 spniden 0x1
/// ###
/// * Secure Non Invasive Debug Enable
/// ###
/// %unsigned 1 dbgrq 0x0
/// ###
/// * Always write as 0.
/// ###
/// %unsigned 1 TPCTL 0x0
/// ###
/// * report the presence of TRACECTL pin.
/// ###
/// %unsigned 5 TPMAXDATASIZE 0x0
/// ###
/// * indicates the maximum TRACEDATA width.
/// ###
/// %unsigned 1 DEVICEEN 0x1
/// ###
/// * Enables APB-AP interface
/// ###
/// %% 20 # Stuffing bits...
/// @ 0x00004 SoftResetn (P)
/// ###
/// * Controls various reset inputs of moltres_mp_ip
/// ###
/// %unsigned 1 CPUAxi 0x1
/// ###
/// * Active low reset for CPU's AXI bus. Connected to HRESETn input of moltres_mp_ip.
/// ###
/// %unsigned 1 MpSubSys 0x1
/// ###
/// * Active low reset for MP sub-system (peripherals, timers, watchdogs, AXI, ATB).
/// * Controls subsys_awake_nreset input of moltres_mp_ip
/// ###
/// %unsigned 1 CoreSight 0x1
/// ###
/// * Active low reset for CoreSight module. Resets APB , ATB & CTM interfaces.
/// ###
/// %% 29 # Stuffing bits...
/// @ 0x00008 sysIntPol (P)
/// %unsigned 32 invert 0x0
/// ###
/// * one bit per each interrupt source, interrupt position follow IRQ table defined in pic.sxw.txt
/// * 0 : Don't invert before sending to GIC inside PJ4-MP
/// * 1 : Invert before sending to GIC inside PJ4B-MP
/// ###
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 12B, bits: 47b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_MoltresReg
#define h_MoltresReg (){}
#define RA_MoltresReg_CTRL5 0x0000
#define BA_MoltresReg_CTRL5_dbgen 0x0000
#define B16MoltresReg_CTRL5_dbgen 0x0000
#define LSb32MoltresReg_CTRL5_dbgen 0
#define LSb16MoltresReg_CTRL5_dbgen 0
#define bMoltresReg_CTRL5_dbgen 1
#define MSK32MoltresReg_CTRL5_dbgen 0x00000001
#define BA_MoltresReg_CTRL5_spiden 0x0000
#define B16MoltresReg_CTRL5_spiden 0x0000
#define LSb32MoltresReg_CTRL5_spiden 1
#define LSb16MoltresReg_CTRL5_spiden 1
#define bMoltresReg_CTRL5_spiden 1
#define MSK32MoltresReg_CTRL5_spiden 0x00000002
#define BA_MoltresReg_CTRL5_niden 0x0000
#define B16MoltresReg_CTRL5_niden 0x0000
#define LSb32MoltresReg_CTRL5_niden 2
#define LSb16MoltresReg_CTRL5_niden 2
#define bMoltresReg_CTRL5_niden 1
#define MSK32MoltresReg_CTRL5_niden 0x00000004
#define BA_MoltresReg_CTRL5_spniden 0x0000
#define B16MoltresReg_CTRL5_spniden 0x0000
#define LSb32MoltresReg_CTRL5_spniden 3
#define LSb16MoltresReg_CTRL5_spniden 3
#define bMoltresReg_CTRL5_spniden 1
#define MSK32MoltresReg_CTRL5_spniden 0x00000008
#define BA_MoltresReg_CTRL5_dbgrq 0x0000
#define B16MoltresReg_CTRL5_dbgrq 0x0000
#define LSb32MoltresReg_CTRL5_dbgrq 4
#define LSb16MoltresReg_CTRL5_dbgrq 4
#define bMoltresReg_CTRL5_dbgrq 1
#define MSK32MoltresReg_CTRL5_dbgrq 0x00000010
#define BA_MoltresReg_CTRL5_TPCTL 0x0000
#define B16MoltresReg_CTRL5_TPCTL 0x0000
#define LSb32MoltresReg_CTRL5_TPCTL 5
#define LSb16MoltresReg_CTRL5_TPCTL 5
#define bMoltresReg_CTRL5_TPCTL 1
#define MSK32MoltresReg_CTRL5_TPCTL 0x00000020
#define BA_MoltresReg_CTRL5_TPMAXDATASIZE 0x0000
#define B16MoltresReg_CTRL5_TPMAXDATASIZE 0x0000
#define LSb32MoltresReg_CTRL5_TPMAXDATASIZE 6
#define LSb16MoltresReg_CTRL5_TPMAXDATASIZE 6
#define bMoltresReg_CTRL5_TPMAXDATASIZE 5
#define MSK32MoltresReg_CTRL5_TPMAXDATASIZE 0x000007C0
#define BA_MoltresReg_CTRL5_DEVICEEN 0x0001
#define B16MoltresReg_CTRL5_DEVICEEN 0x0000
#define LSb32MoltresReg_CTRL5_DEVICEEN 11
#define LSb16MoltresReg_CTRL5_DEVICEEN 11
#define bMoltresReg_CTRL5_DEVICEEN 1
#define MSK32MoltresReg_CTRL5_DEVICEEN 0x00000800
///////////////////////////////////////////////////////////
#define RA_MoltresReg_SoftResetn 0x0004
#define BA_MoltresReg_SoftResetn_CPUAxi 0x0004
#define B16MoltresReg_SoftResetn_CPUAxi 0x0004
#define LSb32MoltresReg_SoftResetn_CPUAxi 0
#define LSb16MoltresReg_SoftResetn_CPUAxi 0
#define bMoltresReg_SoftResetn_CPUAxi 1
#define MSK32MoltresReg_SoftResetn_CPUAxi 0x00000001
#define BA_MoltresReg_SoftResetn_MpSubSys 0x0004
#define B16MoltresReg_SoftResetn_MpSubSys 0x0004
#define LSb32MoltresReg_SoftResetn_MpSubSys 1
#define LSb16MoltresReg_SoftResetn_MpSubSys 1
#define bMoltresReg_SoftResetn_MpSubSys 1
#define MSK32MoltresReg_SoftResetn_MpSubSys 0x00000002
#define BA_MoltresReg_SoftResetn_CoreSight 0x0004
#define B16MoltresReg_SoftResetn_CoreSight 0x0004
#define LSb32MoltresReg_SoftResetn_CoreSight 2
#define LSb16MoltresReg_SoftResetn_CoreSight 2
#define bMoltresReg_SoftResetn_CoreSight 1
#define MSK32MoltresReg_SoftResetn_CoreSight 0x00000004
///////////////////////////////////////////////////////////
#define RA_MoltresReg_sysIntPol 0x0008
#define BA_MoltresReg_sysIntPol_invert 0x0008
#define B16MoltresReg_sysIntPol_invert 0x0008
#define LSb32MoltresReg_sysIntPol_invert 0
#define LSb16MoltresReg_sysIntPol_invert 0
#define bMoltresReg_sysIntPol_invert 32
#define MSK32MoltresReg_sysIntPol_invert 0xFFFFFFFF
///////////////////////////////////////////////////////////
typedef struct SIE_MoltresReg {
///////////////////////////////////////////////////////////
#define GET32MoltresReg_CTRL5_dbgen(r32) _BFGET_(r32, 0, 0)
#define SET32MoltresReg_CTRL5_dbgen(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16MoltresReg_CTRL5_dbgen(r16) _BFGET_(r16, 0, 0)
#define SET16MoltresReg_CTRL5_dbgen(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32MoltresReg_CTRL5_spiden(r32) _BFGET_(r32, 1, 1)
#define SET32MoltresReg_CTRL5_spiden(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16MoltresReg_CTRL5_spiden(r16) _BFGET_(r16, 1, 1)
#define SET16MoltresReg_CTRL5_spiden(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32MoltresReg_CTRL5_niden(r32) _BFGET_(r32, 2, 2)
#define SET32MoltresReg_CTRL5_niden(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16MoltresReg_CTRL5_niden(r16) _BFGET_(r16, 2, 2)
#define SET16MoltresReg_CTRL5_niden(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32MoltresReg_CTRL5_spniden(r32) _BFGET_(r32, 3, 3)
#define SET32MoltresReg_CTRL5_spniden(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16MoltresReg_CTRL5_spniden(r16) _BFGET_(r16, 3, 3)
#define SET16MoltresReg_CTRL5_spniden(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32MoltresReg_CTRL5_dbgrq(r32) _BFGET_(r32, 4, 4)
#define SET32MoltresReg_CTRL5_dbgrq(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16MoltresReg_CTRL5_dbgrq(r16) _BFGET_(r16, 4, 4)
#define SET16MoltresReg_CTRL5_dbgrq(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32MoltresReg_CTRL5_TPCTL(r32) _BFGET_(r32, 5, 5)
#define SET32MoltresReg_CTRL5_TPCTL(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16MoltresReg_CTRL5_TPCTL(r16) _BFGET_(r16, 5, 5)
#define SET16MoltresReg_CTRL5_TPCTL(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32MoltresReg_CTRL5_TPMAXDATASIZE(r32) _BFGET_(r32,10, 6)
#define SET32MoltresReg_CTRL5_TPMAXDATASIZE(r32,v) _BFSET_(r32,10, 6,v)
#define GET16MoltresReg_CTRL5_TPMAXDATASIZE(r16) _BFGET_(r16,10, 6)
#define SET16MoltresReg_CTRL5_TPMAXDATASIZE(r16,v) _BFSET_(r16,10, 6,v)
#define GET32MoltresReg_CTRL5_DEVICEEN(r32) _BFGET_(r32,11,11)
#define SET32MoltresReg_CTRL5_DEVICEEN(r32,v) _BFSET_(r32,11,11,v)
#define GET16MoltresReg_CTRL5_DEVICEEN(r16) _BFGET_(r16,11,11)
#define SET16MoltresReg_CTRL5_DEVICEEN(r16,v) _BFSET_(r16,11,11,v)
#define w32MoltresReg_CTRL5 {\
UNSG32 uCTRL5_dbgen : 1;\
UNSG32 uCTRL5_spiden : 1;\
UNSG32 uCTRL5_niden : 1;\
UNSG32 uCTRL5_spniden : 1;\
UNSG32 uCTRL5_dbgrq : 1;\
UNSG32 uCTRL5_TPCTL : 1;\
UNSG32 uCTRL5_TPMAXDATASIZE : 5;\
UNSG32 uCTRL5_DEVICEEN : 1;\
UNSG32 RSVDx0_b12 : 20;\
}
union { UNSG32 u32MoltresReg_CTRL5;
struct w32MoltresReg_CTRL5;
};
///////////////////////////////////////////////////////////
#define GET32MoltresReg_SoftResetn_CPUAxi(r32) _BFGET_(r32, 0, 0)
#define SET32MoltresReg_SoftResetn_CPUAxi(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16MoltresReg_SoftResetn_CPUAxi(r16) _BFGET_(r16, 0, 0)
#define SET16MoltresReg_SoftResetn_CPUAxi(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32MoltresReg_SoftResetn_MpSubSys(r32) _BFGET_(r32, 1, 1)
#define SET32MoltresReg_SoftResetn_MpSubSys(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16MoltresReg_SoftResetn_MpSubSys(r16) _BFGET_(r16, 1, 1)
#define SET16MoltresReg_SoftResetn_MpSubSys(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32MoltresReg_SoftResetn_CoreSight(r32) _BFGET_(r32, 2, 2)
#define SET32MoltresReg_SoftResetn_CoreSight(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16MoltresReg_SoftResetn_CoreSight(r16) _BFGET_(r16, 2, 2)
#define SET16MoltresReg_SoftResetn_CoreSight(r16,v) _BFSET_(r16, 2, 2,v)
#define w32MoltresReg_SoftResetn {\
UNSG32 uSoftResetn_CPUAxi : 1;\
UNSG32 uSoftResetn_MpSubSys : 1;\
UNSG32 uSoftResetn_CoreSight : 1;\
UNSG32 RSVDx4_b3 : 29;\
}
union { UNSG32 u32MoltresReg_SoftResetn;
struct w32MoltresReg_SoftResetn;
};
///////////////////////////////////////////////////////////
#define GET32MoltresReg_sysIntPol_invert(r32) _BFGET_(r32,31, 0)
#define SET32MoltresReg_sysIntPol_invert(r32,v) _BFSET_(r32,31, 0,v)
#define w32MoltresReg_sysIntPol {\
UNSG32 usysIntPol_invert : 32;\
}
union { UNSG32 u32MoltresReg_sysIntPol;
struct w32MoltresReg_sysIntPol;
};
///////////////////////////////////////////////////////////
} SIE_MoltresReg;
typedef union T32MoltresReg_CTRL5
{ UNSG32 u32;
struct w32MoltresReg_CTRL5;
} T32MoltresReg_CTRL5;
typedef union T32MoltresReg_SoftResetn
{ UNSG32 u32;
struct w32MoltresReg_SoftResetn;
} T32MoltresReg_SoftResetn;
typedef union T32MoltresReg_sysIntPol
{ UNSG32 u32;
struct w32MoltresReg_sysIntPol;
} T32MoltresReg_sysIntPol;
///////////////////////////////////////////////////////////
typedef union TMoltresReg_CTRL5
{ UNSG32 u32[1];
struct {
struct w32MoltresReg_CTRL5;
};
} TMoltresReg_CTRL5;
typedef union TMoltresReg_SoftResetn
{ UNSG32 u32[1];
struct {
struct w32MoltresReg_SoftResetn;
};
} TMoltresReg_SoftResetn;
typedef union TMoltresReg_sysIntPol
{ UNSG32 u32[1];
struct {
struct w32MoltresReg_sysIntPol;
};
} TMoltresReg_sysIntPol;
///////////////////////////////////////////////////////////
SIGN32 MoltresReg_drvrd(SIE_MoltresReg *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 MoltresReg_drvwr(SIE_MoltresReg *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void MoltresReg_reset(SIE_MoltresReg *p);
SIGN32 MoltresReg_cmp (SIE_MoltresReg *p, SIE_MoltresReg *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define MoltresReg_check(p,pie,pfx,hLOG) MoltresReg_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define MoltresReg_print(p, pfx,hLOG) MoltresReg_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: MoltresReg
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE IDReg biu (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 CTRL (P)
/// ###
/// * ID to {AxUSER, AxCACHE} mapping. Transaction is routed to IOB if (AxUSER | AxCACHE[1]) is true.
/// ###
/// %unsigned 4 AWCAHE 0x0
/// ###
/// * AWCAHE corresponding to this ID.
/// ###
/// %unsigned 1 AWUSER 0x0
/// ###
/// * AWUSER corresponding to this ID.
/// ###
/// %unsigned 4 ARCAHE 0x0
/// ###
/// * ARCAHE corresponding to this ID.
/// ###
/// %unsigned 1 ARUSER 0x0
/// ###
/// * ARUSER corresponding to this ID.
/// ###
/// %% 22 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 4B, bits: 10b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_IDReg
#define h_IDReg (){}
#define RA_IDReg_CTRL 0x0000
#define BA_IDReg_CTRL_AWCAHE 0x0000
#define B16IDReg_CTRL_AWCAHE 0x0000
#define LSb32IDReg_CTRL_AWCAHE 0
#define LSb16IDReg_CTRL_AWCAHE 0
#define bIDReg_CTRL_AWCAHE 4
#define MSK32IDReg_CTRL_AWCAHE 0x0000000F
#define BA_IDReg_CTRL_AWUSER 0x0000
#define B16IDReg_CTRL_AWUSER 0x0000
#define LSb32IDReg_CTRL_AWUSER 4
#define LSb16IDReg_CTRL_AWUSER 4
#define bIDReg_CTRL_AWUSER 1
#define MSK32IDReg_CTRL_AWUSER 0x00000010
#define BA_IDReg_CTRL_ARCAHE 0x0000
#define B16IDReg_CTRL_ARCAHE 0x0000
#define LSb32IDReg_CTRL_ARCAHE 5
#define LSb16IDReg_CTRL_ARCAHE 5
#define bIDReg_CTRL_ARCAHE 4
#define MSK32IDReg_CTRL_ARCAHE 0x000001E0
#define BA_IDReg_CTRL_ARUSER 0x0001
#define B16IDReg_CTRL_ARUSER 0x0000
#define LSb32IDReg_CTRL_ARUSER 9
#define LSb16IDReg_CTRL_ARUSER 9
#define bIDReg_CTRL_ARUSER 1
#define MSK32IDReg_CTRL_ARUSER 0x00000200
///////////////////////////////////////////////////////////
typedef struct SIE_IDReg {
///////////////////////////////////////////////////////////
#define GET32IDReg_CTRL_AWCAHE(r32) _BFGET_(r32, 3, 0)
#define SET32IDReg_CTRL_AWCAHE(r32,v) _BFSET_(r32, 3, 0,v)
#define GET16IDReg_CTRL_AWCAHE(r16) _BFGET_(r16, 3, 0)
#define SET16IDReg_CTRL_AWCAHE(r16,v) _BFSET_(r16, 3, 0,v)
#define GET32IDReg_CTRL_AWUSER(r32) _BFGET_(r32, 4, 4)
#define SET32IDReg_CTRL_AWUSER(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16IDReg_CTRL_AWUSER(r16) _BFGET_(r16, 4, 4)
#define SET16IDReg_CTRL_AWUSER(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32IDReg_CTRL_ARCAHE(r32) _BFGET_(r32, 8, 5)
#define SET32IDReg_CTRL_ARCAHE(r32,v) _BFSET_(r32, 8, 5,v)
#define GET16IDReg_CTRL_ARCAHE(r16) _BFGET_(r16, 8, 5)
#define SET16IDReg_CTRL_ARCAHE(r16,v) _BFSET_(r16, 8, 5,v)
#define GET32IDReg_CTRL_ARUSER(r32) _BFGET_(r32, 9, 9)
#define SET32IDReg_CTRL_ARUSER(r32,v) _BFSET_(r32, 9, 9,v)
#define GET16IDReg_CTRL_ARUSER(r16) _BFGET_(r16, 9, 9)
#define SET16IDReg_CTRL_ARUSER(r16,v) _BFSET_(r16, 9, 9,v)
#define w32IDReg_CTRL {\
UNSG32 uCTRL_AWCAHE : 4;\
UNSG32 uCTRL_AWUSER : 1;\
UNSG32 uCTRL_ARCAHE : 4;\
UNSG32 uCTRL_ARUSER : 1;\
UNSG32 RSVDx0_b10 : 22;\
}
union { UNSG32 u32IDReg_CTRL;
struct w32IDReg_CTRL;
};
///////////////////////////////////////////////////////////
} SIE_IDReg;
typedef union T32IDReg_CTRL
{ UNSG32 u32;
struct w32IDReg_CTRL;
} T32IDReg_CTRL;
///////////////////////////////////////////////////////////
typedef union TIDReg_CTRL
{ UNSG32 u32[1];
struct {
struct w32IDReg_CTRL;
};
} TIDReg_CTRL;
///////////////////////////////////////////////////////////
SIGN32 IDReg_drvrd(SIE_IDReg *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 IDReg_drvwr(SIE_IDReg *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void IDReg_reset(SIE_IDReg *p);
SIGN32 IDReg_cmp (SIE_IDReg *p, SIE_IDReg *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define IDReg_check(p,pie,pfx,hLOG) IDReg_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define IDReg_print(p, pfx,hLOG) IDReg_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: IDReg
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE AxiErrorMon (4,4)
/// ###
/// * AXI Bus Error Response Monitor
/// ###
/// # # ----------------------------------------------------------
/// @ 0x00000 WriteID (R-)
/// %unsigned 32 berrID 0x0
/// ###
/// * ID of AXI Write Transaction that caused an error response
/// ###
/// @ 0x00004 WriteStat (R-)
/// %unsigned 1 berrType 0x0
/// ###
/// * Error Response Type
/// * 0: SLVERR
/// * 1: DECERR
/// ###
/// %unsigned 1 berrValid 0x0
/// ###
/// * When asserted, an error response is detected and the information are captured into berrID and berrType.
/// * Monitoring is stopped
/// ###
/// %% 30 # Stuffing bits...
/// @ 0x00008 WriteCtrl (RW)
/// %unsigned 1 berrClear 0x0
/// ###
/// * Writing 1 will clear berrValid and resume the monitoring.
/// * This bit self clears.
/// ###
/// %unsigned 1 berrIntrEn 0x0
/// ###
/// * 1: Monitor generates an active high interrupt when berrValid = 1
/// * 0: Interrupt is masked.
/// * Note: To clear interrupt, write 1 to berrClear
/// ###
/// %% 30 # Stuffing bits...
/// @ 0x0000C ReadID (R-)
/// %unsigned 32 rerrID 0x0
/// ###
/// * ID of AXI Read Transaction that caused an error response
/// ###
/// @ 0x00010 ReadStat (R-)
/// %unsigned 1 rerrType 0x0
/// ###
/// * Error Response Type
/// * 0: SLVERR
/// * 1: DECERR
/// ###
/// %unsigned 1 rerrValid 0x0
/// ###
/// * When asserted, an error response is detected and the information are captured into rerrID and rerrType.
/// * Monitoring is stopped
/// ###
/// %% 30 # Stuffing bits...
/// @ 0x00014 ReadCtrl (RW)
/// %unsigned 1 rerrClear 0x0
/// ###
/// * Writing 1 will clear rerrValid and resume the monitoring.
/// * This bit self clears.
/// ###
/// %unsigned 1 rerrIntrEn 0x0
/// ###
/// * 1: Monitor generates an active high interrupt when berrValid = 1
/// * 0: Interrupt is masked.
/// * Note: To clear interrupt, write 1 to berrClear
/// ###
/// %% 30 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 24B, bits: 72b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_AxiErrorMon
#define h_AxiErrorMon (){}
#define RA_AxiErrorMon_WriteID 0x0000
#define BA_AxiErrorMon_WriteID_berrID 0x0000
#define B16AxiErrorMon_WriteID_berrID 0x0000
#define LSb32AxiErrorMon_WriteID_berrID 0
#define LSb16AxiErrorMon_WriteID_berrID 0
#define bAxiErrorMon_WriteID_berrID 32
#define MSK32AxiErrorMon_WriteID_berrID 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_AxiErrorMon_WriteStat 0x0004
#define BA_AxiErrorMon_WriteStat_berrType 0x0004
#define B16AxiErrorMon_WriteStat_berrType 0x0004
#define LSb32AxiErrorMon_WriteStat_berrType 0
#define LSb16AxiErrorMon_WriteStat_berrType 0
#define bAxiErrorMon_WriteStat_berrType 1
#define MSK32AxiErrorMon_WriteStat_berrType 0x00000001
#define BA_AxiErrorMon_WriteStat_berrValid 0x0004
#define B16AxiErrorMon_WriteStat_berrValid 0x0004
#define LSb32AxiErrorMon_WriteStat_berrValid 1
#define LSb16AxiErrorMon_WriteStat_berrValid 1
#define bAxiErrorMon_WriteStat_berrValid 1
#define MSK32AxiErrorMon_WriteStat_berrValid 0x00000002
///////////////////////////////////////////////////////////
#define RA_AxiErrorMon_WriteCtrl 0x0008
#define BA_AxiErrorMon_WriteCtrl_berrClear 0x0008
#define B16AxiErrorMon_WriteCtrl_berrClear 0x0008
#define LSb32AxiErrorMon_WriteCtrl_berrClear 0
#define LSb16AxiErrorMon_WriteCtrl_berrClear 0
#define bAxiErrorMon_WriteCtrl_berrClear 1
#define MSK32AxiErrorMon_WriteCtrl_berrClear 0x00000001
#define BA_AxiErrorMon_WriteCtrl_berrIntrEn 0x0008
#define B16AxiErrorMon_WriteCtrl_berrIntrEn 0x0008
#define LSb32AxiErrorMon_WriteCtrl_berrIntrEn 1
#define LSb16AxiErrorMon_WriteCtrl_berrIntrEn 1
#define bAxiErrorMon_WriteCtrl_berrIntrEn 1
#define MSK32AxiErrorMon_WriteCtrl_berrIntrEn 0x00000002
///////////////////////////////////////////////////////////
#define RA_AxiErrorMon_ReadID 0x000C
#define BA_AxiErrorMon_ReadID_rerrID 0x000C
#define B16AxiErrorMon_ReadID_rerrID 0x000C
#define LSb32AxiErrorMon_ReadID_rerrID 0
#define LSb16AxiErrorMon_ReadID_rerrID 0
#define bAxiErrorMon_ReadID_rerrID 32
#define MSK32AxiErrorMon_ReadID_rerrID 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_AxiErrorMon_ReadStat 0x0010
#define BA_AxiErrorMon_ReadStat_rerrType 0x0010
#define B16AxiErrorMon_ReadStat_rerrType 0x0010
#define LSb32AxiErrorMon_ReadStat_rerrType 0
#define LSb16AxiErrorMon_ReadStat_rerrType 0
#define bAxiErrorMon_ReadStat_rerrType 1
#define MSK32AxiErrorMon_ReadStat_rerrType 0x00000001
#define BA_AxiErrorMon_ReadStat_rerrValid 0x0010
#define B16AxiErrorMon_ReadStat_rerrValid 0x0010
#define LSb32AxiErrorMon_ReadStat_rerrValid 1
#define LSb16AxiErrorMon_ReadStat_rerrValid 1
#define bAxiErrorMon_ReadStat_rerrValid 1
#define MSK32AxiErrorMon_ReadStat_rerrValid 0x00000002
///////////////////////////////////////////////////////////
#define RA_AxiErrorMon_ReadCtrl 0x0014
#define BA_AxiErrorMon_ReadCtrl_rerrClear 0x0014
#define B16AxiErrorMon_ReadCtrl_rerrClear 0x0014
#define LSb32AxiErrorMon_ReadCtrl_rerrClear 0
#define LSb16AxiErrorMon_ReadCtrl_rerrClear 0
#define bAxiErrorMon_ReadCtrl_rerrClear 1
#define MSK32AxiErrorMon_ReadCtrl_rerrClear 0x00000001
#define BA_AxiErrorMon_ReadCtrl_rerrIntrEn 0x0014
#define B16AxiErrorMon_ReadCtrl_rerrIntrEn 0x0014
#define LSb32AxiErrorMon_ReadCtrl_rerrIntrEn 1
#define LSb16AxiErrorMon_ReadCtrl_rerrIntrEn 1
#define bAxiErrorMon_ReadCtrl_rerrIntrEn 1
#define MSK32AxiErrorMon_ReadCtrl_rerrIntrEn 0x00000002
///////////////////////////////////////////////////////////
typedef struct SIE_AxiErrorMon {
///////////////////////////////////////////////////////////
#define GET32AxiErrorMon_WriteID_berrID(r32) _BFGET_(r32,31, 0)
#define SET32AxiErrorMon_WriteID_berrID(r32,v) _BFSET_(r32,31, 0,v)
#define w32AxiErrorMon_WriteID {\
UNSG32 uWriteID_berrID : 32;\
}
union { UNSG32 u32AxiErrorMon_WriteID;
struct w32AxiErrorMon_WriteID;
};
///////////////////////////////////////////////////////////
#define GET32AxiErrorMon_WriteStat_berrType(r32) _BFGET_(r32, 0, 0)
#define SET32AxiErrorMon_WriteStat_berrType(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16AxiErrorMon_WriteStat_berrType(r16) _BFGET_(r16, 0, 0)
#define SET16AxiErrorMon_WriteStat_berrType(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32AxiErrorMon_WriteStat_berrValid(r32) _BFGET_(r32, 1, 1)
#define SET32AxiErrorMon_WriteStat_berrValid(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16AxiErrorMon_WriteStat_berrValid(r16) _BFGET_(r16, 1, 1)
#define SET16AxiErrorMon_WriteStat_berrValid(r16,v) _BFSET_(r16, 1, 1,v)
#define w32AxiErrorMon_WriteStat {\
UNSG32 uWriteStat_berrType : 1;\
UNSG32 uWriteStat_berrValid : 1;\
UNSG32 RSVDx4_b2 : 30;\
}
union { UNSG32 u32AxiErrorMon_WriteStat;
struct w32AxiErrorMon_WriteStat;
};
///////////////////////////////////////////////////////////
#define GET32AxiErrorMon_WriteCtrl_berrClear(r32) _BFGET_(r32, 0, 0)
#define SET32AxiErrorMon_WriteCtrl_berrClear(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16AxiErrorMon_WriteCtrl_berrClear(r16) _BFGET_(r16, 0, 0)
#define SET16AxiErrorMon_WriteCtrl_berrClear(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32AxiErrorMon_WriteCtrl_berrIntrEn(r32) _BFGET_(r32, 1, 1)
#define SET32AxiErrorMon_WriteCtrl_berrIntrEn(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16AxiErrorMon_WriteCtrl_berrIntrEn(r16) _BFGET_(r16, 1, 1)
#define SET16AxiErrorMon_WriteCtrl_berrIntrEn(r16,v) _BFSET_(r16, 1, 1,v)
#define w32AxiErrorMon_WriteCtrl {\
UNSG32 uWriteCtrl_berrClear : 1;\
UNSG32 uWriteCtrl_berrIntrEn : 1;\
UNSG32 RSVDx8_b2 : 30;\
}
union { UNSG32 u32AxiErrorMon_WriteCtrl;
struct w32AxiErrorMon_WriteCtrl;
};
///////////////////////////////////////////////////////////
#define GET32AxiErrorMon_ReadID_rerrID(r32) _BFGET_(r32,31, 0)
#define SET32AxiErrorMon_ReadID_rerrID(r32,v) _BFSET_(r32,31, 0,v)
#define w32AxiErrorMon_ReadID {\
UNSG32 uReadID_rerrID : 32;\
}
union { UNSG32 u32AxiErrorMon_ReadID;
struct w32AxiErrorMon_ReadID;
};
///////////////////////////////////////////////////////////
#define GET32AxiErrorMon_ReadStat_rerrType(r32) _BFGET_(r32, 0, 0)
#define SET32AxiErrorMon_ReadStat_rerrType(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16AxiErrorMon_ReadStat_rerrType(r16) _BFGET_(r16, 0, 0)
#define SET16AxiErrorMon_ReadStat_rerrType(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32AxiErrorMon_ReadStat_rerrValid(r32) _BFGET_(r32, 1, 1)
#define SET32AxiErrorMon_ReadStat_rerrValid(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16AxiErrorMon_ReadStat_rerrValid(r16) _BFGET_(r16, 1, 1)
#define SET16AxiErrorMon_ReadStat_rerrValid(r16,v) _BFSET_(r16, 1, 1,v)
#define w32AxiErrorMon_ReadStat {\
UNSG32 uReadStat_rerrType : 1;\
UNSG32 uReadStat_rerrValid : 1;\
UNSG32 RSVDx10_b2 : 30;\
}
union { UNSG32 u32AxiErrorMon_ReadStat;
struct w32AxiErrorMon_ReadStat;
};
///////////////////////////////////////////////////////////
#define GET32AxiErrorMon_ReadCtrl_rerrClear(r32) _BFGET_(r32, 0, 0)
#define SET32AxiErrorMon_ReadCtrl_rerrClear(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16AxiErrorMon_ReadCtrl_rerrClear(r16) _BFGET_(r16, 0, 0)
#define SET16AxiErrorMon_ReadCtrl_rerrClear(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32AxiErrorMon_ReadCtrl_rerrIntrEn(r32) _BFGET_(r32, 1, 1)
#define SET32AxiErrorMon_ReadCtrl_rerrIntrEn(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16AxiErrorMon_ReadCtrl_rerrIntrEn(r16) _BFGET_(r16, 1, 1)
#define SET16AxiErrorMon_ReadCtrl_rerrIntrEn(r16,v) _BFSET_(r16, 1, 1,v)
#define w32AxiErrorMon_ReadCtrl {\
UNSG32 uReadCtrl_rerrClear : 1;\
UNSG32 uReadCtrl_rerrIntrEn : 1;\
UNSG32 RSVDx14_b2 : 30;\
}
union { UNSG32 u32AxiErrorMon_ReadCtrl;
struct w32AxiErrorMon_ReadCtrl;
};
///////////////////////////////////////////////////////////
} SIE_AxiErrorMon;
typedef union T32AxiErrorMon_WriteID
{ UNSG32 u32;
struct w32AxiErrorMon_WriteID;
} T32AxiErrorMon_WriteID;
typedef union T32AxiErrorMon_WriteStat
{ UNSG32 u32;
struct w32AxiErrorMon_WriteStat;
} T32AxiErrorMon_WriteStat;
typedef union T32AxiErrorMon_WriteCtrl
{ UNSG32 u32;
struct w32AxiErrorMon_WriteCtrl;
} T32AxiErrorMon_WriteCtrl;
typedef union T32AxiErrorMon_ReadID
{ UNSG32 u32;
struct w32AxiErrorMon_ReadID;
} T32AxiErrorMon_ReadID;
typedef union T32AxiErrorMon_ReadStat
{ UNSG32 u32;
struct w32AxiErrorMon_ReadStat;
} T32AxiErrorMon_ReadStat;
typedef union T32AxiErrorMon_ReadCtrl
{ UNSG32 u32;
struct w32AxiErrorMon_ReadCtrl;
} T32AxiErrorMon_ReadCtrl;
///////////////////////////////////////////////////////////
typedef union TAxiErrorMon_WriteID
{ UNSG32 u32[1];
struct {
struct w32AxiErrorMon_WriteID;
};
} TAxiErrorMon_WriteID;
typedef union TAxiErrorMon_WriteStat
{ UNSG32 u32[1];
struct {
struct w32AxiErrorMon_WriteStat;
};
} TAxiErrorMon_WriteStat;
typedef union TAxiErrorMon_WriteCtrl
{ UNSG32 u32[1];
struct {
struct w32AxiErrorMon_WriteCtrl;
};
} TAxiErrorMon_WriteCtrl;
typedef union TAxiErrorMon_ReadID
{ UNSG32 u32[1];
struct {
struct w32AxiErrorMon_ReadID;
};
} TAxiErrorMon_ReadID;
typedef union TAxiErrorMon_ReadStat
{ UNSG32 u32[1];
struct {
struct w32AxiErrorMon_ReadStat;
};
} TAxiErrorMon_ReadStat;
typedef union TAxiErrorMon_ReadCtrl
{ UNSG32 u32[1];
struct {
struct w32AxiErrorMon_ReadCtrl;
};
} TAxiErrorMon_ReadCtrl;
///////////////////////////////////////////////////////////
SIGN32 AxiErrorMon_drvrd(SIE_AxiErrorMon *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 AxiErrorMon_drvwr(SIE_AxiErrorMon *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void AxiErrorMon_reset(SIE_AxiErrorMon *p);
SIGN32 AxiErrorMon_cmp (SIE_AxiErrorMon *p, SIE_AxiErrorMon *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define AxiErrorMon_check(p,pie,pfx,hLOG) AxiErrorMon_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define AxiErrorMon_print(p, pfx,hLOG) AxiErrorMon_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: AxiErrorMon
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE seSettingX (4,4)
/// ###
/// * Config Space Secure Region Registers
/// ###
/// # # ----------------------------------------------------------
/// @ 0x00000 seW (P)
/// %unsigned 1 seW 0x0
/// ###
/// * 1: Only Secure Masters can write to this region
/// * 0: Any masters can write to this region
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x00004 seR (P)
/// %unsigned 1 seR 0x0
/// ###
/// * 1: Only Secure Masters can read from this region
/// * 0: Any masters can read from this region
/// * In combination with seW the access to the region is fully secure if seW and seR are 1 and non-secure when seW and seR are 0
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x00008 seBase (P)
/// %unsigned 32 seBase 0x0
/// ###
/// * Base or Start address of the region
/// * Bits [1:0] unused.
/// ###
/// @ 0x0000C seMask (P)
/// %unsigned 32 seMask 0x0
/// ###
/// * Used in conjunction with seBase to define region size
/// * Bits [1:0] unused
/// ###
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 16B, bits: 66b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_seSettingX
#define h_seSettingX (){}
#define RA_seSettingX_seW 0x0000
#define BA_seSettingX_seW_seW 0x0000
#define B16seSettingX_seW_seW 0x0000
#define LSb32seSettingX_seW_seW 0
#define LSb16seSettingX_seW_seW 0
#define bseSettingX_seW_seW 1
#define MSK32seSettingX_seW_seW 0x00000001
///////////////////////////////////////////////////////////
#define RA_seSettingX_seR 0x0004
#define BA_seSettingX_seR_seR 0x0004
#define B16seSettingX_seR_seR 0x0004
#define LSb32seSettingX_seR_seR 0
#define LSb16seSettingX_seR_seR 0
#define bseSettingX_seR_seR 1
#define MSK32seSettingX_seR_seR 0x00000001
///////////////////////////////////////////////////////////
#define RA_seSettingX_seBase 0x0008
#define BA_seSettingX_seBase_seBase 0x0008
#define B16seSettingX_seBase_seBase 0x0008
#define LSb32seSettingX_seBase_seBase 0
#define LSb16seSettingX_seBase_seBase 0
#define bseSettingX_seBase_seBase 32
#define MSK32seSettingX_seBase_seBase 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_seSettingX_seMask 0x000C
#define BA_seSettingX_seMask_seMask 0x000C
#define B16seSettingX_seMask_seMask 0x000C
#define LSb32seSettingX_seMask_seMask 0
#define LSb16seSettingX_seMask_seMask 0
#define bseSettingX_seMask_seMask 32
#define MSK32seSettingX_seMask_seMask 0xFFFFFFFF
///////////////////////////////////////////////////////////
typedef struct SIE_seSettingX {
///////////////////////////////////////////////////////////
#define GET32seSettingX_seW_seW(r32) _BFGET_(r32, 0, 0)
#define SET32seSettingX_seW_seW(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16seSettingX_seW_seW(r16) _BFGET_(r16, 0, 0)
#define SET16seSettingX_seW_seW(r16,v) _BFSET_(r16, 0, 0,v)
#define w32seSettingX_seW {\
UNSG32 useW_seW : 1;\
UNSG32 RSVDx0_b1 : 31;\
}
union { UNSG32 u32seSettingX_seW;
struct w32seSettingX_seW;
};
///////////////////////////////////////////////////////////
#define GET32seSettingX_seR_seR(r32) _BFGET_(r32, 0, 0)
#define SET32seSettingX_seR_seR(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16seSettingX_seR_seR(r16) _BFGET_(r16, 0, 0)
#define SET16seSettingX_seR_seR(r16,v) _BFSET_(r16, 0, 0,v)
#define w32seSettingX_seR {\
UNSG32 useR_seR : 1;\
UNSG32 RSVDx4_b1 : 31;\
}
union { UNSG32 u32seSettingX_seR;
struct w32seSettingX_seR;
};
///////////////////////////////////////////////////////////
#define GET32seSettingX_seBase_seBase(r32) _BFGET_(r32,31, 0)
#define SET32seSettingX_seBase_seBase(r32,v) _BFSET_(r32,31, 0,v)
#define w32seSettingX_seBase {\
UNSG32 useBase_seBase : 32;\
}
union { UNSG32 u32seSettingX_seBase;
struct w32seSettingX_seBase;
};
///////////////////////////////////////////////////////////
#define GET32seSettingX_seMask_seMask(r32) _BFGET_(r32,31, 0)
#define SET32seSettingX_seMask_seMask(r32,v) _BFSET_(r32,31, 0,v)
#define w32seSettingX_seMask {\
UNSG32 useMask_seMask : 32;\
}
union { UNSG32 u32seSettingX_seMask;
struct w32seSettingX_seMask;
};
///////////////////////////////////////////////////////////
} SIE_seSettingX;
typedef union T32seSettingX_seW
{ UNSG32 u32;
struct w32seSettingX_seW;
} T32seSettingX_seW;
typedef union T32seSettingX_seR
{ UNSG32 u32;
struct w32seSettingX_seR;
} T32seSettingX_seR;
typedef union T32seSettingX_seBase
{ UNSG32 u32;
struct w32seSettingX_seBase;
} T32seSettingX_seBase;
typedef union T32seSettingX_seMask
{ UNSG32 u32;
struct w32seSettingX_seMask;
} T32seSettingX_seMask;
///////////////////////////////////////////////////////////
typedef union TseSettingX_seW
{ UNSG32 u32[1];
struct {
struct w32seSettingX_seW;
};
} TseSettingX_seW;
typedef union TseSettingX_seR
{ UNSG32 u32[1];
struct {
struct w32seSettingX_seR;
};
} TseSettingX_seR;
typedef union TseSettingX_seBase
{ UNSG32 u32[1];
struct {
struct w32seSettingX_seBase;
};
} TseSettingX_seBase;
typedef union TseSettingX_seMask
{ UNSG32 u32[1];
struct {
struct w32seSettingX_seMask;
};
} TseSettingX_seMask;
///////////////////////////////////////////////////////////
SIGN32 seSettingX_drvrd(SIE_seSettingX *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 seSettingX_drvwr(SIE_seSettingX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void seSettingX_reset(SIE_seSettingX *p);
SIGN32 seSettingX_cmp (SIE_seSettingX *p, SIE_seSettingX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define seSettingX_check(p,pie,pfx,hLOG) seSettingX_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define seSettingX_print(p, pfx,hLOG) seSettingX_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: seSettingX
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE seRegionX (4,4)
/// ###
/// * Config Space Secure Regions
/// ###
/// # # ----------------------------------------------------------
/// @ 0x00000 (P)
/// # 0x00000 CTRL0
/// $seSettingX CTRL0 REG
/// ###
/// * Region 0 access control register
/// ###
/// @ 0x00010 (P)
/// # 0x00010 CTRL1
/// $seSettingX CTRL1 REG
/// ###
/// * Region 1 access control register
/// ###
/// @ 0x00020 (P)
/// # 0x00020 CTRL2
/// $seSettingX CTRL2 REG
/// ###
/// * Region 2 access control register
/// ###
/// @ 0x00030 (P)
/// # 0x00030 CTRL3
/// $seSettingX CTRL3 REG
/// ###
/// * Region 3 access control register
/// ###
/// @ 0x00040 (P)
/// # 0x00040 CTRL4
/// $seSettingX CTRL4 REG
/// ###
/// * Region 4 access control register
/// ###
/// @ 0x00050 (P)
/// # 0x00050 CTRL5
/// $seSettingX CTRL5 REG
/// ###
/// * Region 5 access control register
/// ###
/// @ 0x00060 (P)
/// # 0x00060 CTRL6
/// $seSettingX CTRL6 REG
/// ###
/// * Region 6 access control register
/// ###
/// @ 0x00070 (P)
/// # 0x00070 CTRL7
/// $seSettingX CTRL7 REG
/// ###
/// * Region 7 access control register
/// ###
/// @ 0x00080 (P)
/// # 0x00080 CTRL8
/// $seSettingX CTRL8 REG
/// ###
/// * Region 8 access control register
/// ###
/// @ 0x00090 (P)
/// # 0x00090 CTRL9
/// $seSettingX CTRL9 REG
/// ###
/// * Region 9 access control register
/// ###
/// @ 0x000A0 (P)
/// # 0x000A0 CTRL10
/// $seSettingX CTRL10 REG
/// ###
/// * Region 10 access control register
/// ###
/// @ 0x000B0 (P)
/// # 0x000B0 CTRL11
/// $seSettingX CTRL11 REG
/// ###
/// * Region 11 access control register
/// ###
/// @ 0x000C0 (P)
/// # 0x000C0 CTRL12
/// $seSettingX CTRL12 REG
/// ###
/// * Region 12 access control register
/// ###
/// @ 0x000D0 (P)
/// # 0x000D0 CTRL13
/// $seSettingX CTRL13 REG
/// ###
/// * Region 13 access control register
/// ###
/// @ 0x000E0 (P)
/// # 0x000E0 CTRL14
/// $seSettingX CTRL14 REG
/// ###
/// * Region 14 access control register
/// ###
/// @ 0x000F0 (P)
/// # 0x000F0 CTRL15
/// $seSettingX CTRL15 REG
/// ###
/// * Region 15 access control register
/// ###
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 256B, bits: 1056b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_seRegionX
#define h_seRegionX (){}
#define RA_seRegionX_CTRL0 0x0000
///////////////////////////////////////////////////////////
#define RA_seRegionX_CTRL1 0x0010
///////////////////////////////////////////////////////////
#define RA_seRegionX_CTRL2 0x0020
///////////////////////////////////////////////////////////
#define RA_seRegionX_CTRL3 0x0030
///////////////////////////////////////////////////////////
#define RA_seRegionX_CTRL4 0x0040
///////////////////////////////////////////////////////////
#define RA_seRegionX_CTRL5 0x0050
///////////////////////////////////////////////////////////
#define RA_seRegionX_CTRL6 0x0060
///////////////////////////////////////////////////////////
#define RA_seRegionX_CTRL7 0x0070
///////////////////////////////////////////////////////////
#define RA_seRegionX_CTRL8 0x0080
///////////////////////////////////////////////////////////
#define RA_seRegionX_CTRL9 0x0090
///////////////////////////////////////////////////////////
#define RA_seRegionX_CTRL10 0x00A0
///////////////////////////////////////////////////////////
#define RA_seRegionX_CTRL11 0x00B0
///////////////////////////////////////////////////////////
#define RA_seRegionX_CTRL12 0x00C0
///////////////////////////////////////////////////////////
#define RA_seRegionX_CTRL13 0x00D0
///////////////////////////////////////////////////////////
#define RA_seRegionX_CTRL14 0x00E0
///////////////////////////////////////////////////////////
#define RA_seRegionX_CTRL15 0x00F0
///////////////////////////////////////////////////////////
typedef struct SIE_seRegionX {
///////////////////////////////////////////////////////////
SIE_seSettingX ie_CTRL0;
///////////////////////////////////////////////////////////
SIE_seSettingX ie_CTRL1;
///////////////////////////////////////////////////////////
SIE_seSettingX ie_CTRL2;
///////////////////////////////////////////////////////////
SIE_seSettingX ie_CTRL3;
///////////////////////////////////////////////////////////
SIE_seSettingX ie_CTRL4;
///////////////////////////////////////////////////////////
SIE_seSettingX ie_CTRL5;
///////////////////////////////////////////////////////////
SIE_seSettingX ie_CTRL6;
///////////////////////////////////////////////////////////
SIE_seSettingX ie_CTRL7;
///////////////////////////////////////////////////////////
SIE_seSettingX ie_CTRL8;
///////////////////////////////////////////////////////////
SIE_seSettingX ie_CTRL9;
///////////////////////////////////////////////////////////
SIE_seSettingX ie_CTRL10;
///////////////////////////////////////////////////////////
SIE_seSettingX ie_CTRL11;
///////////////////////////////////////////////////////////
SIE_seSettingX ie_CTRL12;
///////////////////////////////////////////////////////////
SIE_seSettingX ie_CTRL13;
///////////////////////////////////////////////////////////
SIE_seSettingX ie_CTRL14;
///////////////////////////////////////////////////////////
SIE_seSettingX ie_CTRL15;
///////////////////////////////////////////////////////////
} SIE_seRegionX;
///////////////////////////////////////////////////////////
SIGN32 seRegionX_drvrd(SIE_seRegionX *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 seRegionX_drvwr(SIE_seRegionX *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void seRegionX_reset(SIE_seRegionX *p);
SIGN32 seRegionX_cmp (SIE_seRegionX *p, SIE_seRegionX *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define seRegionX_check(p,pie,pfx,hLOG) seRegionX_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define seRegionX_print(p, pfx,hLOG) seRegionX_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: seRegionX
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE seAccess (4,4)
/// ###
/// * AXI Secure Access
/// ###
/// # # ----------------------------------------------------------
/// @ 0x00000 seAxi (P)
/// %unsigned 1 ProtOverrideW 0x0
/// ###
/// * 1: Overrides AWPROT with ProtValW
/// * 0: AWPROT passes through
/// ###
/// %unsigned 1 ProtValW 0x0
/// ###
/// * 0: AWPROT is 0
/// * 1: AWPROT is 1
/// ###
/// %unsigned 1 ProtOverrideR 0x0
/// ###
/// * 1: Overrides ARPROT with ProtValR
/// * 0: ARPROT passes through
/// ###
/// %unsigned 1 ProtValR 0x0
/// ###
/// * 0: ARPROT is 0
/// * 1: ARPROT is 1
/// ###
/// %% 28 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 4B, bits: 4b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_seAccess
#define h_seAccess (){}
#define RA_seAccess_seAxi 0x0000
#define BA_seAccess_seAxi_ProtOverrideW 0x0000
#define B16seAccess_seAxi_ProtOverrideW 0x0000
#define LSb32seAccess_seAxi_ProtOverrideW 0
#define LSb16seAccess_seAxi_ProtOverrideW 0
#define bseAccess_seAxi_ProtOverrideW 1
#define MSK32seAccess_seAxi_ProtOverrideW 0x00000001
#define BA_seAccess_seAxi_ProtValW 0x0000
#define B16seAccess_seAxi_ProtValW 0x0000
#define LSb32seAccess_seAxi_ProtValW 1
#define LSb16seAccess_seAxi_ProtValW 1
#define bseAccess_seAxi_ProtValW 1
#define MSK32seAccess_seAxi_ProtValW 0x00000002
#define BA_seAccess_seAxi_ProtOverrideR 0x0000
#define B16seAccess_seAxi_ProtOverrideR 0x0000
#define LSb32seAccess_seAxi_ProtOverrideR 2
#define LSb16seAccess_seAxi_ProtOverrideR 2
#define bseAccess_seAxi_ProtOverrideR 1
#define MSK32seAccess_seAxi_ProtOverrideR 0x00000004
#define BA_seAccess_seAxi_ProtValR 0x0000
#define B16seAccess_seAxi_ProtValR 0x0000
#define LSb32seAccess_seAxi_ProtValR 3
#define LSb16seAccess_seAxi_ProtValR 3
#define bseAccess_seAxi_ProtValR 1
#define MSK32seAccess_seAxi_ProtValR 0x00000008
///////////////////////////////////////////////////////////
typedef struct SIE_seAccess {
///////////////////////////////////////////////////////////
#define GET32seAccess_seAxi_ProtOverrideW(r32) _BFGET_(r32, 0, 0)
#define SET32seAccess_seAxi_ProtOverrideW(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16seAccess_seAxi_ProtOverrideW(r16) _BFGET_(r16, 0, 0)
#define SET16seAccess_seAxi_ProtOverrideW(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32seAccess_seAxi_ProtValW(r32) _BFGET_(r32, 1, 1)
#define SET32seAccess_seAxi_ProtValW(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16seAccess_seAxi_ProtValW(r16) _BFGET_(r16, 1, 1)
#define SET16seAccess_seAxi_ProtValW(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32seAccess_seAxi_ProtOverrideR(r32) _BFGET_(r32, 2, 2)
#define SET32seAccess_seAxi_ProtOverrideR(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16seAccess_seAxi_ProtOverrideR(r16) _BFGET_(r16, 2, 2)
#define SET16seAccess_seAxi_ProtOverrideR(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32seAccess_seAxi_ProtValR(r32) _BFGET_(r32, 3, 3)
#define SET32seAccess_seAxi_ProtValR(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16seAccess_seAxi_ProtValR(r16) _BFGET_(r16, 3, 3)
#define SET16seAccess_seAxi_ProtValR(r16,v) _BFSET_(r16, 3, 3,v)
#define w32seAccess_seAxi {\
UNSG32 useAxi_ProtOverrideW : 1;\
UNSG32 useAxi_ProtValW : 1;\
UNSG32 useAxi_ProtOverrideR : 1;\
UNSG32 useAxi_ProtValR : 1;\
UNSG32 RSVDx0_b4 : 28;\
}
union { UNSG32 u32seAccess_seAxi;
struct w32seAccess_seAxi;
};
///////////////////////////////////////////////////////////
} SIE_seAccess;
typedef union T32seAccess_seAxi
{ UNSG32 u32;
struct w32seAccess_seAxi;
} T32seAccess_seAxi;
///////////////////////////////////////////////////////////
typedef union TseAccess_seAxi
{ UNSG32 u32[1];
struct {
struct w32seAccess_seAxi;
};
} TseAccess_seAxi;
///////////////////////////////////////////////////////////
SIGN32 seAccess_drvrd(SIE_seAccess *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 seAccess_drvwr(SIE_seAccess *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void seAccess_reset(SIE_seAccess *p);
SIGN32 seAccess_cmp (SIE_seAccess *p, SIE_seAccess *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define seAccess_check(p,pie,pfx,hLOG) seAccess_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define seAccess_print(p, pfx,hLOG) seAccess_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: seAccess
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE protOR biu (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 (P)
/// # 0x00000 SecureCPU
/// $seAccess SecureCPU REG
/// @ 0x00004 (P)
/// # 0x00004 SecureAVIOM0
/// $seAccess SecureAVIOM0 REG
/// @ 0x00008 (P)
/// # 0x00008 SecureAVIOM1
/// $seAccess SecureAVIOM1 REG
/// @ 0x0000C (P)
/// # 0x0000C SecureZSP
/// $seAccess SecureZSP REG
/// @ 0x00010 (P)
/// # 0x00010 SecureGFX3D
/// $seAccess SecureGFX3D REG
/// @ 0x00014 (P)
/// # 0x00014 SecureV2G
/// $seAccess SecureV2G REG
/// @ 0x00018 (P)
/// # 0x00018 SecureHTRO0
/// $seAccess SecureHTRO0 REG
/// @ 0x0001C (P)
/// # 0x0001C SecureMTEST
/// $seAccess SecureMTEST REG
/// @ 0x00020 (P)
/// # 0x00020 SecureBMON
/// $seAccess SecureBMON REG
/// ###
/// * The following are secured based on decoding of the PXBAR AxID values
/// ###
/// @ 0x00024 (P)
/// # 0x00024 SecureNAND
/// $seAccess SecureNAND REG
/// @ 0x00028 (P)
/// # 0x00028 SecureUSBM0
/// $seAccess SecureUSBM0 REG
/// @ 0x0002C (P)
/// # 0x0002C SecureSDIO
/// $seAccess SecureSDIO REG
/// @ 0x00030 (P)
/// # 0x00030 SecureTSP
/// $seAccess SecureTSP REG
/// @ 0x00034 (P)
/// # 0x00034 SecureBCMCPU
/// $seAccess SecureBCMCPU REG
/// @ 0x00038 (P)
/// # 0x00038 SecureBCMDMA
/// $seAccess SecureBCMDMA REG
/// @ 0x0003C (P)
/// # 0x0003C SecureBCMDIR
/// $seAccess SecureBCMDIR REG
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 64B, bits: 64b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_protOR
#define h_protOR (){}
#define RA_protOR_SecureCPU 0x0000
///////////////////////////////////////////////////////////
#define RA_protOR_SecureAVIOM0 0x0004
///////////////////////////////////////////////////////////
#define RA_protOR_SecureAVIOM1 0x0008
///////////////////////////////////////////////////////////
#define RA_protOR_SecureZSP 0x000C
///////////////////////////////////////////////////////////
#define RA_protOR_SecureGFX3D 0x0010
///////////////////////////////////////////////////////////
#define RA_protOR_SecureV2G 0x0014
///////////////////////////////////////////////////////////
#define RA_protOR_SecureHTRO0 0x0018
///////////////////////////////////////////////////////////
#define RA_protOR_SecureMTEST 0x001C
///////////////////////////////////////////////////////////
#define RA_protOR_SecureBMON 0x0020
///////////////////////////////////////////////////////////
#define RA_protOR_SecureNAND 0x0024
///////////////////////////////////////////////////////////
#define RA_protOR_SecureUSBM0 0x0028
///////////////////////////////////////////////////////////
#define RA_protOR_SecureSDIO 0x002C
///////////////////////////////////////////////////////////
#define RA_protOR_SecureTSP 0x0030
///////////////////////////////////////////////////////////
#define RA_protOR_SecureBCMCPU 0x0034
///////////////////////////////////////////////////////////
#define RA_protOR_SecureBCMDMA 0x0038
///////////////////////////////////////////////////////////
#define RA_protOR_SecureBCMDIR 0x003C
///////////////////////////////////////////////////////////
typedef struct SIE_protOR {
///////////////////////////////////////////////////////////
SIE_seAccess ie_SecureCPU;
///////////////////////////////////////////////////////////
SIE_seAccess ie_SecureAVIOM0;
///////////////////////////////////////////////////////////
SIE_seAccess ie_SecureAVIOM1;
///////////////////////////////////////////////////////////
SIE_seAccess ie_SecureZSP;
///////////////////////////////////////////////////////////
SIE_seAccess ie_SecureGFX3D;
///////////////////////////////////////////////////////////
SIE_seAccess ie_SecureV2G;
///////////////////////////////////////////////////////////
SIE_seAccess ie_SecureHTRO0;
///////////////////////////////////////////////////////////
SIE_seAccess ie_SecureMTEST;
///////////////////////////////////////////////////////////
SIE_seAccess ie_SecureBMON;
///////////////////////////////////////////////////////////
SIE_seAccess ie_SecureNAND;
///////////////////////////////////////////////////////////
SIE_seAccess ie_SecureUSBM0;
///////////////////////////////////////////////////////////
SIE_seAccess ie_SecureSDIO;
///////////////////////////////////////////////////////////
SIE_seAccess ie_SecureTSP;
///////////////////////////////////////////////////////////
SIE_seAccess ie_SecureBCMCPU;
///////////////////////////////////////////////////////////
SIE_seAccess ie_SecureBCMDMA;
///////////////////////////////////////////////////////////
SIE_seAccess ie_SecureBCMDIR;
///////////////////////////////////////////////////////////
} SIE_protOR;
///////////////////////////////////////////////////////////
SIGN32 protOR_drvrd(SIE_protOR *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 protOR_drvwr(SIE_protOR *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void protOR_reset(SIE_protOR *p);
SIGN32 protOR_cmp (SIE_protOR *p, SIE_protOR *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define protOR_check(p,pie,pfx,hLOG) protOR_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define protOR_print(p, pfx,hLOG) protOR_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: protOR
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE AxiWrFilt (4,4)
/// ###
/// * AXI Write Strobe Filter
/// ###
/// # # ----------------------------------------------------------
/// @ 0x00000 CTRL (RW-)
/// %unsigned 1 En 0x0
/// ###
/// * Write filtering is enabled. Checks against all regions will start.
/// ###
/// %unsigned 1 Clear 0x0
/// ###
/// * Writing 1 to this bit will clear the status and interrupt.
/// * This bit self clears
/// ###
/// %% 30 # Stuffing bits...
/// @ 0x00004 STATUS (R-)
/// %unsigned 1 Intr 0x0
/// ###
/// * 0: No match to the regions has occurred
/// * 1: A region was hit and the WSTRB of the transaction is masked.
/// * This bit stays high and the WSTRB stays masked until a 1 is written to CTRL.Clear.
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x00008 ProtAddr0 (P)
/// %unsigned 32 Addr 0x0
/// ###
/// * Base or Start address of the region
/// * Bits [1:0] unused.
/// ###
/// @ 0x0000C ProtMask0 (P)
/// %unsigned 32 Mask 0x0
/// ###
/// * Used in conjunction with Addr to define region size
/// * Bits [1:0] unused
/// ###
/// @ 0x00010 ProtAddr1 (P)
/// %unsigned 32 Addr 0x0
/// ###
/// * Base or Start address of the region
/// * Bits [1:0] unused.
/// ###
/// @ 0x00014 ProtMask1 (P)
/// %unsigned 32 Mask 0x0
/// ###
/// * Used in conjunction with Addr to define region size
/// * Bits [1:0] unused
/// ###
/// @ 0x00018 ProtAddr2 (P)
/// %unsigned 32 Addr 0x0
/// ###
/// * Base or Start address of the region
/// * Bits [1:0] unused.
/// ###
/// @ 0x0001C ProtMask2 (P)
/// %unsigned 32 Mask 0x0
/// ###
/// * Used in conjunction with Addr to define region size
/// * Bits [1:0] unused
/// ###
/// @ 0x00020 ProtAddr3 (P)
/// %unsigned 32 Addr 0x0
/// ###
/// * Base or Start address of the region
/// * Bits [1:0] unused.
/// ###
/// @ 0x00024 ProtMask3 (P)
/// %unsigned 32 Mask 0x0
/// ###
/// * Used in conjunction with Addr to define region size
/// * Bits [1:0] unused
/// ###
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 40B, bits: 259b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_AxiWrFilt
#define h_AxiWrFilt (){}
#define RA_AxiWrFilt_CTRL 0x0000
#define BA_AxiWrFilt_CTRL_En 0x0000
#define B16AxiWrFilt_CTRL_En 0x0000
#define LSb32AxiWrFilt_CTRL_En 0
#define LSb16AxiWrFilt_CTRL_En 0
#define bAxiWrFilt_CTRL_En 1
#define MSK32AxiWrFilt_CTRL_En 0x00000001
#define BA_AxiWrFilt_CTRL_Clear 0x0000
#define B16AxiWrFilt_CTRL_Clear 0x0000
#define LSb32AxiWrFilt_CTRL_Clear 1
#define LSb16AxiWrFilt_CTRL_Clear 1
#define bAxiWrFilt_CTRL_Clear 1
#define MSK32AxiWrFilt_CTRL_Clear 0x00000002
///////////////////////////////////////////////////////////
#define RA_AxiWrFilt_STATUS 0x0004
#define BA_AxiWrFilt_STATUS_Intr 0x0004
#define B16AxiWrFilt_STATUS_Intr 0x0004
#define LSb32AxiWrFilt_STATUS_Intr 0
#define LSb16AxiWrFilt_STATUS_Intr 0
#define bAxiWrFilt_STATUS_Intr 1
#define MSK32AxiWrFilt_STATUS_Intr 0x00000001
///////////////////////////////////////////////////////////
#define RA_AxiWrFilt_ProtAddr0 0x0008
#define BA_AxiWrFilt_ProtAddr0_Addr 0x0008
#define B16AxiWrFilt_ProtAddr0_Addr 0x0008
#define LSb32AxiWrFilt_ProtAddr0_Addr 0
#define LSb16AxiWrFilt_ProtAddr0_Addr 0
#define bAxiWrFilt_ProtAddr0_Addr 32
#define MSK32AxiWrFilt_ProtAddr0_Addr 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_AxiWrFilt_ProtMask0 0x000C
#define BA_AxiWrFilt_ProtMask0_Mask 0x000C
#define B16AxiWrFilt_ProtMask0_Mask 0x000C
#define LSb32AxiWrFilt_ProtMask0_Mask 0
#define LSb16AxiWrFilt_ProtMask0_Mask 0
#define bAxiWrFilt_ProtMask0_Mask 32
#define MSK32AxiWrFilt_ProtMask0_Mask 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_AxiWrFilt_ProtAddr1 0x0010
#define BA_AxiWrFilt_ProtAddr1_Addr 0x0010
#define B16AxiWrFilt_ProtAddr1_Addr 0x0010
#define LSb32AxiWrFilt_ProtAddr1_Addr 0
#define LSb16AxiWrFilt_ProtAddr1_Addr 0
#define bAxiWrFilt_ProtAddr1_Addr 32
#define MSK32AxiWrFilt_ProtAddr1_Addr 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_AxiWrFilt_ProtMask1 0x0014
#define BA_AxiWrFilt_ProtMask1_Mask 0x0014
#define B16AxiWrFilt_ProtMask1_Mask 0x0014
#define LSb32AxiWrFilt_ProtMask1_Mask 0
#define LSb16AxiWrFilt_ProtMask1_Mask 0
#define bAxiWrFilt_ProtMask1_Mask 32
#define MSK32AxiWrFilt_ProtMask1_Mask 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_AxiWrFilt_ProtAddr2 0x0018
#define BA_AxiWrFilt_ProtAddr2_Addr 0x0018
#define B16AxiWrFilt_ProtAddr2_Addr 0x0018
#define LSb32AxiWrFilt_ProtAddr2_Addr 0
#define LSb16AxiWrFilt_ProtAddr2_Addr 0
#define bAxiWrFilt_ProtAddr2_Addr 32
#define MSK32AxiWrFilt_ProtAddr2_Addr 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_AxiWrFilt_ProtMask2 0x001C
#define BA_AxiWrFilt_ProtMask2_Mask 0x001C
#define B16AxiWrFilt_ProtMask2_Mask 0x001C
#define LSb32AxiWrFilt_ProtMask2_Mask 0
#define LSb16AxiWrFilt_ProtMask2_Mask 0
#define bAxiWrFilt_ProtMask2_Mask 32
#define MSK32AxiWrFilt_ProtMask2_Mask 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_AxiWrFilt_ProtAddr3 0x0020
#define BA_AxiWrFilt_ProtAddr3_Addr 0x0020
#define B16AxiWrFilt_ProtAddr3_Addr 0x0020
#define LSb32AxiWrFilt_ProtAddr3_Addr 0
#define LSb16AxiWrFilt_ProtAddr3_Addr 0
#define bAxiWrFilt_ProtAddr3_Addr 32
#define MSK32AxiWrFilt_ProtAddr3_Addr 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_AxiWrFilt_ProtMask3 0x0024
#define BA_AxiWrFilt_ProtMask3_Mask 0x0024
#define B16AxiWrFilt_ProtMask3_Mask 0x0024
#define LSb32AxiWrFilt_ProtMask3_Mask 0
#define LSb16AxiWrFilt_ProtMask3_Mask 0
#define bAxiWrFilt_ProtMask3_Mask 32
#define MSK32AxiWrFilt_ProtMask3_Mask 0xFFFFFFFF
///////////////////////////////////////////////////////////
typedef struct SIE_AxiWrFilt {
///////////////////////////////////////////////////////////
#define GET32AxiWrFilt_CTRL_En(r32) _BFGET_(r32, 0, 0)
#define SET32AxiWrFilt_CTRL_En(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16AxiWrFilt_CTRL_En(r16) _BFGET_(r16, 0, 0)
#define SET16AxiWrFilt_CTRL_En(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32AxiWrFilt_CTRL_Clear(r32) _BFGET_(r32, 1, 1)
#define SET32AxiWrFilt_CTRL_Clear(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16AxiWrFilt_CTRL_Clear(r16) _BFGET_(r16, 1, 1)
#define SET16AxiWrFilt_CTRL_Clear(r16,v) _BFSET_(r16, 1, 1,v)
#define w32AxiWrFilt_CTRL {\
UNSG32 uCTRL_En : 1;\
UNSG32 uCTRL_Clear : 1;\
UNSG32 RSVDx0_b2 : 30;\
}
union { UNSG32 u32AxiWrFilt_CTRL;
struct w32AxiWrFilt_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32AxiWrFilt_STATUS_Intr(r32) _BFGET_(r32, 0, 0)
#define SET32AxiWrFilt_STATUS_Intr(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16AxiWrFilt_STATUS_Intr(r16) _BFGET_(r16, 0, 0)
#define SET16AxiWrFilt_STATUS_Intr(r16,v) _BFSET_(r16, 0, 0,v)
#define w32AxiWrFilt_STATUS {\
UNSG32 uSTATUS_Intr : 1;\
UNSG32 RSVDx4_b1 : 31;\
}
union { UNSG32 u32AxiWrFilt_STATUS;
struct w32AxiWrFilt_STATUS;
};
///////////////////////////////////////////////////////////
#define GET32AxiWrFilt_ProtAddr0_Addr(r32) _BFGET_(r32,31, 0)
#define SET32AxiWrFilt_ProtAddr0_Addr(r32,v) _BFSET_(r32,31, 0,v)
#define w32AxiWrFilt_ProtAddr0 {\
UNSG32 uProtAddr0_Addr : 32;\
}
union { UNSG32 u32AxiWrFilt_ProtAddr0;
struct w32AxiWrFilt_ProtAddr0;
};
///////////////////////////////////////////////////////////
#define GET32AxiWrFilt_ProtMask0_Mask(r32) _BFGET_(r32,31, 0)
#define SET32AxiWrFilt_ProtMask0_Mask(r32,v) _BFSET_(r32,31, 0,v)
#define w32AxiWrFilt_ProtMask0 {\
UNSG32 uProtMask0_Mask : 32;\
}
union { UNSG32 u32AxiWrFilt_ProtMask0;
struct w32AxiWrFilt_ProtMask0;
};
///////////////////////////////////////////////////////////
#define GET32AxiWrFilt_ProtAddr1_Addr(r32) _BFGET_(r32,31, 0)
#define SET32AxiWrFilt_ProtAddr1_Addr(r32,v) _BFSET_(r32,31, 0,v)
#define w32AxiWrFilt_ProtAddr1 {\
UNSG32 uProtAddr1_Addr : 32;\
}
union { UNSG32 u32AxiWrFilt_ProtAddr1;
struct w32AxiWrFilt_ProtAddr1;
};
///////////////////////////////////////////////////////////
#define GET32AxiWrFilt_ProtMask1_Mask(r32) _BFGET_(r32,31, 0)
#define SET32AxiWrFilt_ProtMask1_Mask(r32,v) _BFSET_(r32,31, 0,v)
#define w32AxiWrFilt_ProtMask1 {\
UNSG32 uProtMask1_Mask : 32;\
}
union { UNSG32 u32AxiWrFilt_ProtMask1;
struct w32AxiWrFilt_ProtMask1;
};
///////////////////////////////////////////////////////////
#define GET32AxiWrFilt_ProtAddr2_Addr(r32) _BFGET_(r32,31, 0)
#define SET32AxiWrFilt_ProtAddr2_Addr(r32,v) _BFSET_(r32,31, 0,v)
#define w32AxiWrFilt_ProtAddr2 {\
UNSG32 uProtAddr2_Addr : 32;\
}
union { UNSG32 u32AxiWrFilt_ProtAddr2;
struct w32AxiWrFilt_ProtAddr2;
};
///////////////////////////////////////////////////////////
#define GET32AxiWrFilt_ProtMask2_Mask(r32) _BFGET_(r32,31, 0)
#define SET32AxiWrFilt_ProtMask2_Mask(r32,v) _BFSET_(r32,31, 0,v)
#define w32AxiWrFilt_ProtMask2 {\
UNSG32 uProtMask2_Mask : 32;\
}
union { UNSG32 u32AxiWrFilt_ProtMask2;
struct w32AxiWrFilt_ProtMask2;
};
///////////////////////////////////////////////////////////
#define GET32AxiWrFilt_ProtAddr3_Addr(r32) _BFGET_(r32,31, 0)
#define SET32AxiWrFilt_ProtAddr3_Addr(r32,v) _BFSET_(r32,31, 0,v)
#define w32AxiWrFilt_ProtAddr3 {\
UNSG32 uProtAddr3_Addr : 32;\
}
union { UNSG32 u32AxiWrFilt_ProtAddr3;
struct w32AxiWrFilt_ProtAddr3;
};
///////////////////////////////////////////////////////////
#define GET32AxiWrFilt_ProtMask3_Mask(r32) _BFGET_(r32,31, 0)
#define SET32AxiWrFilt_ProtMask3_Mask(r32,v) _BFSET_(r32,31, 0,v)
#define w32AxiWrFilt_ProtMask3 {\
UNSG32 uProtMask3_Mask : 32;\
}
union { UNSG32 u32AxiWrFilt_ProtMask3;
struct w32AxiWrFilt_ProtMask3;
};
///////////////////////////////////////////////////////////
} SIE_AxiWrFilt;
typedef union T32AxiWrFilt_CTRL
{ UNSG32 u32;
struct w32AxiWrFilt_CTRL;
} T32AxiWrFilt_CTRL;
typedef union T32AxiWrFilt_STATUS
{ UNSG32 u32;
struct w32AxiWrFilt_STATUS;
} T32AxiWrFilt_STATUS;
typedef union T32AxiWrFilt_ProtAddr0
{ UNSG32 u32;
struct w32AxiWrFilt_ProtAddr0;
} T32AxiWrFilt_ProtAddr0;
typedef union T32AxiWrFilt_ProtMask0
{ UNSG32 u32;
struct w32AxiWrFilt_ProtMask0;
} T32AxiWrFilt_ProtMask0;
typedef union T32AxiWrFilt_ProtAddr1
{ UNSG32 u32;
struct w32AxiWrFilt_ProtAddr1;
} T32AxiWrFilt_ProtAddr1;
typedef union T32AxiWrFilt_ProtMask1
{ UNSG32 u32;
struct w32AxiWrFilt_ProtMask1;
} T32AxiWrFilt_ProtMask1;
typedef union T32AxiWrFilt_ProtAddr2
{ UNSG32 u32;
struct w32AxiWrFilt_ProtAddr2;
} T32AxiWrFilt_ProtAddr2;
typedef union T32AxiWrFilt_ProtMask2
{ UNSG32 u32;
struct w32AxiWrFilt_ProtMask2;
} T32AxiWrFilt_ProtMask2;
typedef union T32AxiWrFilt_ProtAddr3
{ UNSG32 u32;
struct w32AxiWrFilt_ProtAddr3;
} T32AxiWrFilt_ProtAddr3;
typedef union T32AxiWrFilt_ProtMask3
{ UNSG32 u32;
struct w32AxiWrFilt_ProtMask3;
} T32AxiWrFilt_ProtMask3;
///////////////////////////////////////////////////////////
typedef union TAxiWrFilt_CTRL
{ UNSG32 u32[1];
struct {
struct w32AxiWrFilt_CTRL;
};
} TAxiWrFilt_CTRL;
typedef union TAxiWrFilt_STATUS
{ UNSG32 u32[1];
struct {
struct w32AxiWrFilt_STATUS;
};
} TAxiWrFilt_STATUS;
typedef union TAxiWrFilt_ProtAddr0
{ UNSG32 u32[1];
struct {
struct w32AxiWrFilt_ProtAddr0;
};
} TAxiWrFilt_ProtAddr0;
typedef union TAxiWrFilt_ProtMask0
{ UNSG32 u32[1];
struct {
struct w32AxiWrFilt_ProtMask0;
};
} TAxiWrFilt_ProtMask0;
typedef union TAxiWrFilt_ProtAddr1
{ UNSG32 u32[1];
struct {
struct w32AxiWrFilt_ProtAddr1;
};
} TAxiWrFilt_ProtAddr1;
typedef union TAxiWrFilt_ProtMask1
{ UNSG32 u32[1];
struct {
struct w32AxiWrFilt_ProtMask1;
};
} TAxiWrFilt_ProtMask1;
typedef union TAxiWrFilt_ProtAddr2
{ UNSG32 u32[1];
struct {
struct w32AxiWrFilt_ProtAddr2;
};
} TAxiWrFilt_ProtAddr2;
typedef union TAxiWrFilt_ProtMask2
{ UNSG32 u32[1];
struct {
struct w32AxiWrFilt_ProtMask2;
};
} TAxiWrFilt_ProtMask2;
typedef union TAxiWrFilt_ProtAddr3
{ UNSG32 u32[1];
struct {
struct w32AxiWrFilt_ProtAddr3;
};
} TAxiWrFilt_ProtAddr3;
typedef union TAxiWrFilt_ProtMask3
{ UNSG32 u32[1];
struct {
struct w32AxiWrFilt_ProtMask3;
};
} TAxiWrFilt_ProtMask3;
///////////////////////////////////////////////////////////
SIGN32 AxiWrFilt_drvrd(SIE_AxiWrFilt *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 AxiWrFilt_drvwr(SIE_AxiWrFilt *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void AxiWrFilt_reset(SIE_AxiWrFilt *p);
SIGN32 AxiWrFilt_cmp (SIE_AxiWrFilt *p, SIE_AxiWrFilt *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define AxiWrFilt_check(p,pie,pfx,hLOG) AxiWrFilt_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define AxiWrFilt_print(p, pfx,hLOG) AxiWrFilt_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: AxiWrFilt
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE AxiPCnt biu (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 CTRL (P)
/// %unsigned 1 clear 0x0
/// ###
/// * Clears the counters
/// ###
/// %unsigned 1 enable 0x0
/// ###
/// * Enable counter increment. SW can make enable = 0 to temporarily disable counter increment.
/// ###
/// %% 30 # Stuffing bits...
/// @ 0x00004 TOTAL_CNT (R-)
/// %unsigned 32 cnt 0x0
/// ###
/// * Total no. of AXI clocks
/// ###
/// @ 0x00008 RWAIT_CNT (R-)
/// %unsigned 32 cnt 0x0
/// ###
/// * Counts the no.of clocks aRValid = 1 & aRReady = 0
/// ###
/// @ 0x0000C RDATA_CNT (R-)
/// %unsigned 32 cnt 0x0
/// ###
/// * Counts the no.of clocks rValid = 1 & rReady = 1
/// ###
/// @ 0x00010 WWAIT_CNT (R-)
/// %unsigned 32 cnt 0x0
/// ###
/// * Counts the no.of clocks aWValid = 1 & aWReady = 0
/// ###
/// @ 0x00014 WDATA_CNT (R-)
/// %unsigned 32 cnt 0x0
/// ###
/// * Counts the no.of clocks wValid = 1 & wReady = 1
/// ###
/// @ 0x00018 OF_STATUS (R-)
/// %unsigned 1 total 0x0
/// %unsigned 1 rwait 0x0
/// %unsigned 1 rdata 0x0
/// %unsigned 1 wwait 0x0
/// %unsigned 1 wdata 0x0
/// ###
/// * Overflow status of total, wait and data counters. Clear will clear the overflow status as well.
/// ###
/// %% 27 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 28B, bits: 167b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_AxiPCnt
#define h_AxiPCnt (){}
#define RA_AxiPCnt_CTRL 0x0000
#define BA_AxiPCnt_CTRL_clear 0x0000
#define B16AxiPCnt_CTRL_clear 0x0000
#define LSb32AxiPCnt_CTRL_clear 0
#define LSb16AxiPCnt_CTRL_clear 0
#define bAxiPCnt_CTRL_clear 1
#define MSK32AxiPCnt_CTRL_clear 0x00000001
#define BA_AxiPCnt_CTRL_enable 0x0000
#define B16AxiPCnt_CTRL_enable 0x0000
#define LSb32AxiPCnt_CTRL_enable 1
#define LSb16AxiPCnt_CTRL_enable 1
#define bAxiPCnt_CTRL_enable 1
#define MSK32AxiPCnt_CTRL_enable 0x00000002
///////////////////////////////////////////////////////////
#define RA_AxiPCnt_TOTAL_CNT 0x0004
#define BA_AxiPCnt_TOTAL_CNT_cnt 0x0004
#define B16AxiPCnt_TOTAL_CNT_cnt 0x0004
#define LSb32AxiPCnt_TOTAL_CNT_cnt 0
#define LSb16AxiPCnt_TOTAL_CNT_cnt 0
#define bAxiPCnt_TOTAL_CNT_cnt 32
#define MSK32AxiPCnt_TOTAL_CNT_cnt 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_AxiPCnt_RWAIT_CNT 0x0008
#define BA_AxiPCnt_RWAIT_CNT_cnt 0x0008
#define B16AxiPCnt_RWAIT_CNT_cnt 0x0008
#define LSb32AxiPCnt_RWAIT_CNT_cnt 0
#define LSb16AxiPCnt_RWAIT_CNT_cnt 0
#define bAxiPCnt_RWAIT_CNT_cnt 32
#define MSK32AxiPCnt_RWAIT_CNT_cnt 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_AxiPCnt_RDATA_CNT 0x000C
#define BA_AxiPCnt_RDATA_CNT_cnt 0x000C
#define B16AxiPCnt_RDATA_CNT_cnt 0x000C
#define LSb32AxiPCnt_RDATA_CNT_cnt 0
#define LSb16AxiPCnt_RDATA_CNT_cnt 0
#define bAxiPCnt_RDATA_CNT_cnt 32
#define MSK32AxiPCnt_RDATA_CNT_cnt 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_AxiPCnt_WWAIT_CNT 0x0010
#define BA_AxiPCnt_WWAIT_CNT_cnt 0x0010
#define B16AxiPCnt_WWAIT_CNT_cnt 0x0010
#define LSb32AxiPCnt_WWAIT_CNT_cnt 0
#define LSb16AxiPCnt_WWAIT_CNT_cnt 0
#define bAxiPCnt_WWAIT_CNT_cnt 32
#define MSK32AxiPCnt_WWAIT_CNT_cnt 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_AxiPCnt_WDATA_CNT 0x0014
#define BA_AxiPCnt_WDATA_CNT_cnt 0x0014
#define B16AxiPCnt_WDATA_CNT_cnt 0x0014
#define LSb32AxiPCnt_WDATA_CNT_cnt 0
#define LSb16AxiPCnt_WDATA_CNT_cnt 0
#define bAxiPCnt_WDATA_CNT_cnt 32
#define MSK32AxiPCnt_WDATA_CNT_cnt 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_AxiPCnt_OF_STATUS 0x0018
#define BA_AxiPCnt_OF_STATUS_total 0x0018
#define B16AxiPCnt_OF_STATUS_total 0x0018
#define LSb32AxiPCnt_OF_STATUS_total 0
#define LSb16AxiPCnt_OF_STATUS_total 0
#define bAxiPCnt_OF_STATUS_total 1
#define MSK32AxiPCnt_OF_STATUS_total 0x00000001
#define BA_AxiPCnt_OF_STATUS_rwait 0x0018
#define B16AxiPCnt_OF_STATUS_rwait 0x0018
#define LSb32AxiPCnt_OF_STATUS_rwait 1
#define LSb16AxiPCnt_OF_STATUS_rwait 1
#define bAxiPCnt_OF_STATUS_rwait 1
#define MSK32AxiPCnt_OF_STATUS_rwait 0x00000002
#define BA_AxiPCnt_OF_STATUS_rdata 0x0018
#define B16AxiPCnt_OF_STATUS_rdata 0x0018
#define LSb32AxiPCnt_OF_STATUS_rdata 2
#define LSb16AxiPCnt_OF_STATUS_rdata 2
#define bAxiPCnt_OF_STATUS_rdata 1
#define MSK32AxiPCnt_OF_STATUS_rdata 0x00000004
#define BA_AxiPCnt_OF_STATUS_wwait 0x0018
#define B16AxiPCnt_OF_STATUS_wwait 0x0018
#define LSb32AxiPCnt_OF_STATUS_wwait 3
#define LSb16AxiPCnt_OF_STATUS_wwait 3
#define bAxiPCnt_OF_STATUS_wwait 1
#define MSK32AxiPCnt_OF_STATUS_wwait 0x00000008
#define BA_AxiPCnt_OF_STATUS_wdata 0x0018
#define B16AxiPCnt_OF_STATUS_wdata 0x0018
#define LSb32AxiPCnt_OF_STATUS_wdata 4
#define LSb16AxiPCnt_OF_STATUS_wdata 4
#define bAxiPCnt_OF_STATUS_wdata 1
#define MSK32AxiPCnt_OF_STATUS_wdata 0x00000010
///////////////////////////////////////////////////////////
typedef struct SIE_AxiPCnt {
///////////////////////////////////////////////////////////
#define GET32AxiPCnt_CTRL_clear(r32) _BFGET_(r32, 0, 0)
#define SET32AxiPCnt_CTRL_clear(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16AxiPCnt_CTRL_clear(r16) _BFGET_(r16, 0, 0)
#define SET16AxiPCnt_CTRL_clear(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32AxiPCnt_CTRL_enable(r32) _BFGET_(r32, 1, 1)
#define SET32AxiPCnt_CTRL_enable(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16AxiPCnt_CTRL_enable(r16) _BFGET_(r16, 1, 1)
#define SET16AxiPCnt_CTRL_enable(r16,v) _BFSET_(r16, 1, 1,v)
#define w32AxiPCnt_CTRL {\
UNSG32 uCTRL_clear : 1;\
UNSG32 uCTRL_enable : 1;\
UNSG32 RSVDx0_b2 : 30;\
}
union { UNSG32 u32AxiPCnt_CTRL;
struct w32AxiPCnt_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32AxiPCnt_TOTAL_CNT_cnt(r32) _BFGET_(r32,31, 0)
#define SET32AxiPCnt_TOTAL_CNT_cnt(r32,v) _BFSET_(r32,31, 0,v)
#define w32AxiPCnt_TOTAL_CNT {\
UNSG32 uTOTAL_CNT_cnt : 32;\
}
union { UNSG32 u32AxiPCnt_TOTAL_CNT;
struct w32AxiPCnt_TOTAL_CNT;
};
///////////////////////////////////////////////////////////
#define GET32AxiPCnt_RWAIT_CNT_cnt(r32) _BFGET_(r32,31, 0)
#define SET32AxiPCnt_RWAIT_CNT_cnt(r32,v) _BFSET_(r32,31, 0,v)
#define w32AxiPCnt_RWAIT_CNT {\
UNSG32 uRWAIT_CNT_cnt : 32;\
}
union { UNSG32 u32AxiPCnt_RWAIT_CNT;
struct w32AxiPCnt_RWAIT_CNT;
};
///////////////////////////////////////////////////////////
#define GET32AxiPCnt_RDATA_CNT_cnt(r32) _BFGET_(r32,31, 0)
#define SET32AxiPCnt_RDATA_CNT_cnt(r32,v) _BFSET_(r32,31, 0,v)
#define w32AxiPCnt_RDATA_CNT {\
UNSG32 uRDATA_CNT_cnt : 32;\
}
union { UNSG32 u32AxiPCnt_RDATA_CNT;
struct w32AxiPCnt_RDATA_CNT;
};
///////////////////////////////////////////////////////////
#define GET32AxiPCnt_WWAIT_CNT_cnt(r32) _BFGET_(r32,31, 0)
#define SET32AxiPCnt_WWAIT_CNT_cnt(r32,v) _BFSET_(r32,31, 0,v)
#define w32AxiPCnt_WWAIT_CNT {\
UNSG32 uWWAIT_CNT_cnt : 32;\
}
union { UNSG32 u32AxiPCnt_WWAIT_CNT;
struct w32AxiPCnt_WWAIT_CNT;
};
///////////////////////////////////////////////////////////
#define GET32AxiPCnt_WDATA_CNT_cnt(r32) _BFGET_(r32,31, 0)
#define SET32AxiPCnt_WDATA_CNT_cnt(r32,v) _BFSET_(r32,31, 0,v)
#define w32AxiPCnt_WDATA_CNT {\
UNSG32 uWDATA_CNT_cnt : 32;\
}
union { UNSG32 u32AxiPCnt_WDATA_CNT;
struct w32AxiPCnt_WDATA_CNT;
};
///////////////////////////////////////////////////////////
#define GET32AxiPCnt_OF_STATUS_total(r32) _BFGET_(r32, 0, 0)
#define SET32AxiPCnt_OF_STATUS_total(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16AxiPCnt_OF_STATUS_total(r16) _BFGET_(r16, 0, 0)
#define SET16AxiPCnt_OF_STATUS_total(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32AxiPCnt_OF_STATUS_rwait(r32) _BFGET_(r32, 1, 1)
#define SET32AxiPCnt_OF_STATUS_rwait(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16AxiPCnt_OF_STATUS_rwait(r16) _BFGET_(r16, 1, 1)
#define SET16AxiPCnt_OF_STATUS_rwait(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32AxiPCnt_OF_STATUS_rdata(r32) _BFGET_(r32, 2, 2)
#define SET32AxiPCnt_OF_STATUS_rdata(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16AxiPCnt_OF_STATUS_rdata(r16) _BFGET_(r16, 2, 2)
#define SET16AxiPCnt_OF_STATUS_rdata(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32AxiPCnt_OF_STATUS_wwait(r32) _BFGET_(r32, 3, 3)
#define SET32AxiPCnt_OF_STATUS_wwait(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16AxiPCnt_OF_STATUS_wwait(r16) _BFGET_(r16, 3, 3)
#define SET16AxiPCnt_OF_STATUS_wwait(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32AxiPCnt_OF_STATUS_wdata(r32) _BFGET_(r32, 4, 4)
#define SET32AxiPCnt_OF_STATUS_wdata(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16AxiPCnt_OF_STATUS_wdata(r16) _BFGET_(r16, 4, 4)
#define SET16AxiPCnt_OF_STATUS_wdata(r16,v) _BFSET_(r16, 4, 4,v)
#define w32AxiPCnt_OF_STATUS {\
UNSG32 uOF_STATUS_total : 1;\
UNSG32 uOF_STATUS_rwait : 1;\
UNSG32 uOF_STATUS_rdata : 1;\
UNSG32 uOF_STATUS_wwait : 1;\
UNSG32 uOF_STATUS_wdata : 1;\
UNSG32 RSVDx18_b5 : 27;\
}
union { UNSG32 u32AxiPCnt_OF_STATUS;
struct w32AxiPCnt_OF_STATUS;
};
///////////////////////////////////////////////////////////
} SIE_AxiPCnt;
typedef union T32AxiPCnt_CTRL
{ UNSG32 u32;
struct w32AxiPCnt_CTRL;
} T32AxiPCnt_CTRL;
typedef union T32AxiPCnt_TOTAL_CNT
{ UNSG32 u32;
struct w32AxiPCnt_TOTAL_CNT;
} T32AxiPCnt_TOTAL_CNT;
typedef union T32AxiPCnt_RWAIT_CNT
{ UNSG32 u32;
struct w32AxiPCnt_RWAIT_CNT;
} T32AxiPCnt_RWAIT_CNT;
typedef union T32AxiPCnt_RDATA_CNT
{ UNSG32 u32;
struct w32AxiPCnt_RDATA_CNT;
} T32AxiPCnt_RDATA_CNT;
typedef union T32AxiPCnt_WWAIT_CNT
{ UNSG32 u32;
struct w32AxiPCnt_WWAIT_CNT;
} T32AxiPCnt_WWAIT_CNT;
typedef union T32AxiPCnt_WDATA_CNT
{ UNSG32 u32;
struct w32AxiPCnt_WDATA_CNT;
} T32AxiPCnt_WDATA_CNT;
typedef union T32AxiPCnt_OF_STATUS
{ UNSG32 u32;
struct w32AxiPCnt_OF_STATUS;
} T32AxiPCnt_OF_STATUS;
///////////////////////////////////////////////////////////
typedef union TAxiPCnt_CTRL
{ UNSG32 u32[1];
struct {
struct w32AxiPCnt_CTRL;
};
} TAxiPCnt_CTRL;
typedef union TAxiPCnt_TOTAL_CNT
{ UNSG32 u32[1];
struct {
struct w32AxiPCnt_TOTAL_CNT;
};
} TAxiPCnt_TOTAL_CNT;
typedef union TAxiPCnt_RWAIT_CNT
{ UNSG32 u32[1];
struct {
struct w32AxiPCnt_RWAIT_CNT;
};
} TAxiPCnt_RWAIT_CNT;
typedef union TAxiPCnt_RDATA_CNT
{ UNSG32 u32[1];
struct {
struct w32AxiPCnt_RDATA_CNT;
};
} TAxiPCnt_RDATA_CNT;
typedef union TAxiPCnt_WWAIT_CNT
{ UNSG32 u32[1];
struct {
struct w32AxiPCnt_WWAIT_CNT;
};
} TAxiPCnt_WWAIT_CNT;
typedef union TAxiPCnt_WDATA_CNT
{ UNSG32 u32[1];
struct {
struct w32AxiPCnt_WDATA_CNT;
};
} TAxiPCnt_WDATA_CNT;
typedef union TAxiPCnt_OF_STATUS
{ UNSG32 u32[1];
struct {
struct w32AxiPCnt_OF_STATUS;
};
} TAxiPCnt_OF_STATUS;
///////////////////////////////////////////////////////////
SIGN32 AxiPCnt_drvrd(SIE_AxiPCnt *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 AxiPCnt_drvwr(SIE_AxiPCnt *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void AxiPCnt_reset(SIE_AxiPCnt *p);
SIGN32 AxiPCnt_cmp (SIE_AxiPCnt *p, SIE_AxiPCnt *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define AxiPCnt_check(p,pie,pfx,hLOG) AxiPCnt_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define AxiPCnt_print(p, pfx,hLOG) AxiPCnt_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: AxiPCnt
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE SOC biu (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 Configuration (P)
/// ###
/// * SoC miscellaneous control register
/// ###
/// %unsigned 1 blockIFetch 0x0
/// ###
/// * 1: block instruction access except SDRAM, DRM TCM, ROM, SPI
/// * 0: allow instruction access to all region.
/// ###
/// %unsigned 1 AhbTrcEn 0x0
/// ###
/// * 0: Disables the AHB Trace Monitor (Bmon)
/// * 1: Enables the AHB Trace Monitor (Bmon)
/// ###
/// %% 30 # Stuffing bits...
/// @ 0x00004 sysIntPol0 (P)
/// %unsigned 32 Invert 0x0
/// ###
/// * One bit per interrupt source, interrupt position follows IRQ table defined.
/// * Controls bit [31:0] of interrupt sources
/// * 0: Don't invert before sending to GIC
/// * 1: Invert before sending to GIC
/// ###
/// @ 0x00008 sysIntPol1 (P)
/// %unsigned 32 Invert 0x0
/// ###
/// * One bit per interrupt source, interrupt position follows IRQ table defined.
/// * Controls bit [63:32] of interrupt sources
/// * 0: Don't invert before sending to GIC
/// * 1: Invert before sending to GIC
/// ###
/// @ 0x0000C sysIntPol2 (P)
/// %unsigned 32 Invert 0x0
/// ###
/// * One bit per interrupt source, interrupt position follows IRQ table defined.
/// * Controls bit [95:64] of interrupt sources
/// * 0: Don't invert before sending to GIC
/// * 1: Invert before sending to GIC
/// ###
/// @ 0x00010 sysIntPol3 (P)
/// %unsigned 32 Invert 0x0
/// ###
/// * One bit per interrupt source, interrupt position follows IRQ table defined.
/// * Controls bit [127:96] of interrupt sources
/// * 0: Don't invert before sending to GIC
/// * 1: Invert before sending to GIC
/// ###
/// @ 0x00014 (W-)
/// # # Stuffing bytes...
/// %% 1888
/// @ 0x00100 (P)
/// # 0x00100 protOR
/// $protOR protOR REG
/// ###
/// * AxPROT override controls
/// ###
/// @ 0x00140 (P)
/// # 0x00140 GFX3D_PC
/// $AxiPCnt GFX3D_PC REG
/// ###
/// * Performance Counters for GFX3D AXI.
/// * *INTERNAL_ONLY**
/// ###
/// @ 0x0015C (W-)
/// # # Stuffing bytes...
/// %% 1312
/// @ 0x00200 (P)
/// # 0x00200 SecureRegionCtrl0
/// $seRegionX SecureRegionCtrl0 REG
/// @ 0x00300 (P)
/// # 0x00300 SecureRegionCtrl1
/// $seRegionX SecureRegionCtrl1 REG
/// @ 0x00400 (P)
/// # 0x00400 SecureRegionCtrl2
/// $seRegionX SecureRegionCtrl2 REG
/// @ 0x00500 (P)
/// # 0x00500 SecureRegionCtrl3
/// $seRegionX SecureRegionCtrl3 REG
/// ###
/// * Secure Region Registers
/// ###
/// @ 0x00600 AHB_RESP_CTRL (P)
/// %unsigned 1 MaskHrespDef 0x0
/// ###
/// * Config register access that does not decode into a valid AHB slave (a “hole”) will
/// * 0: Return an ERROR response.
/// * 1: Return an OKAY response
/// ###
/// %unsigned 1 MaskHrespSe 0x0
/// %% 30 # Stuffing bits...
/// @ 0x00604 AXI_BRESP_CTRL (P)
/// %unsigned 1 CA7 0x0
/// ###
/// * 0: bresp[1] is passed to AXI master unaltered
/// * 1: force bresp[1] to 0
/// ###
/// %unsigned 1 AVIOM0 0x0
/// ###
/// * 0: bresp[1] is passed to AXI master unaltered
/// * 1: force bresp[1] to 0
/// ###
/// %unsigned 1 AVIOM1 0x0
/// ###
/// * 0: bresp[1] is passed to AXI master unaltered
/// * 1: force bresp[1] to 0
/// ###
/// %unsigned 1 GFX3D 0x0
/// ###
/// * 0: bresp[1] is passed to AXI master unaltered
/// * 1: force bresp[1] to 0
/// ###
/// %unsigned 1 HTRO 0x0
/// ###
/// * 0: bresp[1] is passed to AXI master unaltered
/// * 1: force bresp[1] to 0
/// ###
/// %unsigned 1 MTEST 0x0
/// ###
/// * 0: bresp[1] is passed to AXI master unaltered
/// * 1: force bresp[1] to 0
/// ###
/// %unsigned 1 BMON 0x0
/// ###
/// * 0: bresp[1] is passed to AXI master unaltered
/// * 1: force bresp[1] to 0
/// ###
/// %unsigned 1 NAND 0x0
/// ###
/// * 0: bresp[1] is passed to AXI master unaltered
/// * 1: force bresp[1] to 0
/// ###
/// %unsigned 1 USBM0 0x0
/// ###
/// * 0: bresp[1] is passed to AXI master unaltered
/// * 1: force bresp[1] to 0
/// ###
/// %unsigned 1 SDIO 0x0
/// ###
/// * 0: bresp[1] is passed to AXI master unaltered
/// * 1: force bresp[1] to 0
/// ###
/// %unsigned 1 TSP 0x0
/// ###
/// * 0: bresp[1] is passed to AXI master unaltered
/// * 1: force bresp[1] to 0
/// ###
/// %unsigned 1 BCMCPU 0x0
/// ###
/// * 0: bresp[1] is passed to AXI master unaltered
/// * 1: force bresp[1] to 0
/// ###
/// %unsigned 1 BCMDMA 0x0
/// ###
/// * 0: bresp[1] is passed to AXI master unaltered
/// * 1: force bresp[1] to 0
/// ###
/// %unsigned 1 BCMDIR 0x0
/// ###
/// * 0: bresp[1] is passed to AXI master unaltered
/// * 1: force bresp[1] to 0
/// ###
/// %% 18 # Stuffing bits...
/// @ 0x00608 AXI_RRESP_CTRL (P)
/// %unsigned 1 CA7 0x0
/// ###
/// * 0: rresp[1] is passed to AXI master unaltered
/// * 1: force rresp[1] to 0
/// ###
/// %unsigned 1 AVIOM0 0x0
/// ###
/// * 0: rresp[1] is passed to AXI master unaltered
/// * 1: force rresp[1] to 0
/// ###
/// %unsigned 1 AVIOM1 0x0
/// ###
/// * 0: rresp[1] is passed to AXI master unaltered
/// * 1: force rresp[1] to 0
/// ###
/// %unsigned 1 GFX3D 0x0
/// ###
/// * 0: rresp[1] is passed to AXI master unaltered
/// * 1: force rresp[1] to 0
/// ###
/// %unsigned 1 HTRO 0x0
/// ###
/// * 0: rresp[1] is passed to AXI master unaltered
/// * 1: force rresp[1] to 0
/// ###
/// %unsigned 1 MTEST 0x0
/// ###
/// * 0: rresp[1] is passed to AXI master unaltered
/// * 1: force rresp[1] to 0
/// ###
/// %unsigned 1 NAND 0x0
/// ###
/// * 0: rresp[1] is passed to AXI master unaltered
/// * 1: force rresp[1] to 0
/// ###
/// %unsigned 1 USBM0 0x0
/// ###
/// * 0: rresp[1] is passed to AXI master unaltered
/// * 1: force rresp[1] to 0
/// ###
/// %unsigned 1 SDIO 0x0
/// ###
/// * 0: rresp[1] is passed to AXI master unaltered
/// * 1: force rresp[1] to 0
/// ###
/// %unsigned 1 TSP 0x0
/// ###
/// * 0: rresp[1] is passed to AXI master unaltered
/// * 1: force rresp[1] to 0
/// ###
/// %unsigned 1 BCMCPU 0x0
/// ###
/// * 0: rresp[1] is passed to AXI master unaltered
/// * 1: force rresp[1] to 0
/// ###
/// %unsigned 1 BCMDMA 0x0
/// ###
/// * 0: rresp[1] is passed to AXI master unaltered
/// * 1: force rresp[1] to 0
/// ###
/// %unsigned 1 BCMDIR 0x0
/// ###
/// * 0: rresp[1] is passed to AXI master unaltered
/// * 1: force rresp[1] to 0
/// ###
/// %% 19 # Stuffing bits...
/// @ 0x0060C (W-)
/// # # Stuffing bytes...
/// %% 4000
/// @ 0x00800 (P)
/// # 0x00800 AxiErrMon1
/// $AxiErrorMon AxiErrMon1 REG
/// ###
/// * AXI Error Response Monitor for mstr1 (AVIOM0)
/// ###
/// @ 0x00818 (P)
/// # 0x00818 AxiErrMon2
/// $AxiErrorMon AxiErrMon2 REG
/// ###
/// * AXI Error Response Monitor for mstr2 (AVIOM1)
/// ###
/// @ 0x00830 (P)
/// # 0x00830 AxiErrMon4
/// $AxiErrorMon AxiErrMon4 REG
/// ###
/// * AXI Error Response Monitor for mstr4 (DXBAR)
/// ###
/// @ 0x00848 (P)
/// # 0x00848 AxiErrMon5
/// $AxiErrorMon AxiErrMon5 REG
/// ###
/// * AXI Error Response Monitor for mstr5 (GFX3D)
/// ###
/// @ 0x00860 (P)
/// # 0x00860 AxiErrMon6
/// $AxiErrorMon AxiErrMon6 REG
/// ###
/// * AXI Error Response Monitor for mstr6 (HTRO0)
/// ###
/// @ 0x00878 (W-)
/// # # Stuffing bytes...
/// %% 1088
/// @ 0x00900 (P)
/// # 0x00900 AxiWrFiltAVIO0
/// $AxiWrFilt AxiWrFiltAVIO0 REG
/// ###
/// * AXI WSTRB Filter for AVIO0
/// ###
/// @ 0x00928 (P)
/// # 0x00928 AxiWrFiltAVIO1
/// $AxiWrFilt AxiWrFiltAVIO1 REG
/// ###
/// * AXI WSTRB Filter for AVIO1
/// ###
/// @ 0x00950 (P)
/// # 0x00950 AxiWrFiltHTRO0
/// $AxiWrFilt AxiWrFiltHTRO0 REG
/// ###
/// * AXI WSTRB Filter for HTRO0
/// ###
/// @ 0x00978 (P)
/// # 0x00978 AxiWrFiltTSP
/// $AxiWrFilt AxiWrFiltTSP REG
/// ###
/// * AXI WSTRB Filter for TSP
/// ###
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 2464B, bits: 6010b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_SOC
#define h_SOC (){}
#define RA_SOC_Configuration 0x0000
#define BA_SOC_Configuration_blockIFetch 0x0000
#define B16SOC_Configuration_blockIFetch 0x0000
#define LSb32SOC_Configuration_blockIFetch 0
#define LSb16SOC_Configuration_blockIFetch 0
#define bSOC_Configuration_blockIFetch 1
#define MSK32SOC_Configuration_blockIFetch 0x00000001
#define BA_SOC_Configuration_AhbTrcEn 0x0000
#define B16SOC_Configuration_AhbTrcEn 0x0000
#define LSb32SOC_Configuration_AhbTrcEn 1
#define LSb16SOC_Configuration_AhbTrcEn 1
#define bSOC_Configuration_AhbTrcEn 1
#define MSK32SOC_Configuration_AhbTrcEn 0x00000002
///////////////////////////////////////////////////////////
#define RA_SOC_sysIntPol0 0x0004
#define BA_SOC_sysIntPol0_Invert 0x0004
#define B16SOC_sysIntPol0_Invert 0x0004
#define LSb32SOC_sysIntPol0_Invert 0
#define LSb16SOC_sysIntPol0_Invert 0
#define bSOC_sysIntPol0_Invert 32
#define MSK32SOC_sysIntPol0_Invert 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_SOC_sysIntPol1 0x0008
#define BA_SOC_sysIntPol1_Invert 0x0008
#define B16SOC_sysIntPol1_Invert 0x0008
#define LSb32SOC_sysIntPol1_Invert 0
#define LSb16SOC_sysIntPol1_Invert 0
#define bSOC_sysIntPol1_Invert 32
#define MSK32SOC_sysIntPol1_Invert 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_SOC_sysIntPol2 0x000C
#define BA_SOC_sysIntPol2_Invert 0x000C
#define B16SOC_sysIntPol2_Invert 0x000C
#define LSb32SOC_sysIntPol2_Invert 0
#define LSb16SOC_sysIntPol2_Invert 0
#define bSOC_sysIntPol2_Invert 32
#define MSK32SOC_sysIntPol2_Invert 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_SOC_sysIntPol3 0x0010
#define BA_SOC_sysIntPol3_Invert 0x0010
#define B16SOC_sysIntPol3_Invert 0x0010
#define LSb32SOC_sysIntPol3_Invert 0
#define LSb16SOC_sysIntPol3_Invert 0
#define bSOC_sysIntPol3_Invert 32
#define MSK32SOC_sysIntPol3_Invert 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_SOC_protOR 0x0100
///////////////////////////////////////////////////////////
#define RA_SOC_GFX3D_PC 0x0140
///////////////////////////////////////////////////////////
#define RA_SOC_SecureRegionCtrl0 0x0200
///////////////////////////////////////////////////////////
#define RA_SOC_SecureRegionCtrl1 0x0300
///////////////////////////////////////////////////////////
#define RA_SOC_SecureRegionCtrl2 0x0400
///////////////////////////////////////////////////////////
#define RA_SOC_SecureRegionCtrl3 0x0500
///////////////////////////////////////////////////////////
#define RA_SOC_AHB_RESP_CTRL 0x0600
#define BA_SOC_AHB_RESP_CTRL_MaskHrespDef 0x0600
#define B16SOC_AHB_RESP_CTRL_MaskHrespDef 0x0600
#define LSb32SOC_AHB_RESP_CTRL_MaskHrespDef 0
#define LSb16SOC_AHB_RESP_CTRL_MaskHrespDef 0
#define bSOC_AHB_RESP_CTRL_MaskHrespDef 1
#define MSK32SOC_AHB_RESP_CTRL_MaskHrespDef 0x00000001
#define BA_SOC_AHB_RESP_CTRL_MaskHrespSe 0x0600
#define B16SOC_AHB_RESP_CTRL_MaskHrespSe 0x0600
#define LSb32SOC_AHB_RESP_CTRL_MaskHrespSe 1
#define LSb16SOC_AHB_RESP_CTRL_MaskHrespSe 1
#define bSOC_AHB_RESP_CTRL_MaskHrespSe 1
#define MSK32SOC_AHB_RESP_CTRL_MaskHrespSe 0x00000002
///////////////////////////////////////////////////////////
#define RA_SOC_AXI_BRESP_CTRL 0x0604
#define BA_SOC_AXI_BRESP_CTRL_CA7 0x0604
#define B16SOC_AXI_BRESP_CTRL_CA7 0x0604
#define LSb32SOC_AXI_BRESP_CTRL_CA7 0
#define LSb16SOC_AXI_BRESP_CTRL_CA7 0
#define bSOC_AXI_BRESP_CTRL_CA7 1
#define MSK32SOC_AXI_BRESP_CTRL_CA7 0x00000001
#define BA_SOC_AXI_BRESP_CTRL_AVIOM0 0x0604
#define B16SOC_AXI_BRESP_CTRL_AVIOM0 0x0604
#define LSb32SOC_AXI_BRESP_CTRL_AVIOM0 1
#define LSb16SOC_AXI_BRESP_CTRL_AVIOM0 1
#define bSOC_AXI_BRESP_CTRL_AVIOM0 1
#define MSK32SOC_AXI_BRESP_CTRL_AVIOM0 0x00000002
#define BA_SOC_AXI_BRESP_CTRL_AVIOM1 0x0604
#define B16SOC_AXI_BRESP_CTRL_AVIOM1 0x0604
#define LSb32SOC_AXI_BRESP_CTRL_AVIOM1 2
#define LSb16SOC_AXI_BRESP_CTRL_AVIOM1 2
#define bSOC_AXI_BRESP_CTRL_AVIOM1 1
#define MSK32SOC_AXI_BRESP_CTRL_AVIOM1 0x00000004
#define BA_SOC_AXI_BRESP_CTRL_GFX3D 0x0604
#define B16SOC_AXI_BRESP_CTRL_GFX3D 0x0604
#define LSb32SOC_AXI_BRESP_CTRL_GFX3D 3
#define LSb16SOC_AXI_BRESP_CTRL_GFX3D 3
#define bSOC_AXI_BRESP_CTRL_GFX3D 1
#define MSK32SOC_AXI_BRESP_CTRL_GFX3D 0x00000008
#define BA_SOC_AXI_BRESP_CTRL_HTRO 0x0604
#define B16SOC_AXI_BRESP_CTRL_HTRO 0x0604
#define LSb32SOC_AXI_BRESP_CTRL_HTRO 4
#define LSb16SOC_AXI_BRESP_CTRL_HTRO 4
#define bSOC_AXI_BRESP_CTRL_HTRO 1
#define MSK32SOC_AXI_BRESP_CTRL_HTRO 0x00000010
#define BA_SOC_AXI_BRESP_CTRL_MTEST 0x0604
#define B16SOC_AXI_BRESP_CTRL_MTEST 0x0604
#define LSb32SOC_AXI_BRESP_CTRL_MTEST 5
#define LSb16SOC_AXI_BRESP_CTRL_MTEST 5
#define bSOC_AXI_BRESP_CTRL_MTEST 1
#define MSK32SOC_AXI_BRESP_CTRL_MTEST 0x00000020
#define BA_SOC_AXI_BRESP_CTRL_BMON 0x0604
#define B16SOC_AXI_BRESP_CTRL_BMON 0x0604
#define LSb32SOC_AXI_BRESP_CTRL_BMON 6
#define LSb16SOC_AXI_BRESP_CTRL_BMON 6
#define bSOC_AXI_BRESP_CTRL_BMON 1
#define MSK32SOC_AXI_BRESP_CTRL_BMON 0x00000040
#define BA_SOC_AXI_BRESP_CTRL_NAND 0x0604
#define B16SOC_AXI_BRESP_CTRL_NAND 0x0604
#define LSb32SOC_AXI_BRESP_CTRL_NAND 7
#define LSb16SOC_AXI_BRESP_CTRL_NAND 7
#define bSOC_AXI_BRESP_CTRL_NAND 1
#define MSK32SOC_AXI_BRESP_CTRL_NAND 0x00000080
#define BA_SOC_AXI_BRESP_CTRL_USBM0 0x0605
#define B16SOC_AXI_BRESP_CTRL_USBM0 0x0604
#define LSb32SOC_AXI_BRESP_CTRL_USBM0 8
#define LSb16SOC_AXI_BRESP_CTRL_USBM0 8
#define bSOC_AXI_BRESP_CTRL_USBM0 1
#define MSK32SOC_AXI_BRESP_CTRL_USBM0 0x00000100
#define BA_SOC_AXI_BRESP_CTRL_SDIO 0x0605
#define B16SOC_AXI_BRESP_CTRL_SDIO 0x0604
#define LSb32SOC_AXI_BRESP_CTRL_SDIO 9
#define LSb16SOC_AXI_BRESP_CTRL_SDIO 9
#define bSOC_AXI_BRESP_CTRL_SDIO 1
#define MSK32SOC_AXI_BRESP_CTRL_SDIO 0x00000200
#define BA_SOC_AXI_BRESP_CTRL_TSP 0x0605
#define B16SOC_AXI_BRESP_CTRL_TSP 0x0604
#define LSb32SOC_AXI_BRESP_CTRL_TSP 10
#define LSb16SOC_AXI_BRESP_CTRL_TSP 10
#define bSOC_AXI_BRESP_CTRL_TSP 1
#define MSK32SOC_AXI_BRESP_CTRL_TSP 0x00000400
#define BA_SOC_AXI_BRESP_CTRL_BCMCPU 0x0605
#define B16SOC_AXI_BRESP_CTRL_BCMCPU 0x0604
#define LSb32SOC_AXI_BRESP_CTRL_BCMCPU 11
#define LSb16SOC_AXI_BRESP_CTRL_BCMCPU 11
#define bSOC_AXI_BRESP_CTRL_BCMCPU 1
#define MSK32SOC_AXI_BRESP_CTRL_BCMCPU 0x00000800
#define BA_SOC_AXI_BRESP_CTRL_BCMDMA 0x0605
#define B16SOC_AXI_BRESP_CTRL_BCMDMA 0x0604
#define LSb32SOC_AXI_BRESP_CTRL_BCMDMA 12
#define LSb16SOC_AXI_BRESP_CTRL_BCMDMA 12
#define bSOC_AXI_BRESP_CTRL_BCMDMA 1
#define MSK32SOC_AXI_BRESP_CTRL_BCMDMA 0x00001000
#define BA_SOC_AXI_BRESP_CTRL_BCMDIR 0x0605
#define B16SOC_AXI_BRESP_CTRL_BCMDIR 0x0604
#define LSb32SOC_AXI_BRESP_CTRL_BCMDIR 13
#define LSb16SOC_AXI_BRESP_CTRL_BCMDIR 13
#define bSOC_AXI_BRESP_CTRL_BCMDIR 1
#define MSK32SOC_AXI_BRESP_CTRL_BCMDIR 0x00002000
///////////////////////////////////////////////////////////
#define RA_SOC_AXI_RRESP_CTRL 0x0608
#define BA_SOC_AXI_RRESP_CTRL_CA7 0x0608
#define B16SOC_AXI_RRESP_CTRL_CA7 0x0608
#define LSb32SOC_AXI_RRESP_CTRL_CA7 0
#define LSb16SOC_AXI_RRESP_CTRL_CA7 0
#define bSOC_AXI_RRESP_CTRL_CA7 1
#define MSK32SOC_AXI_RRESP_CTRL_CA7 0x00000001
#define BA_SOC_AXI_RRESP_CTRL_AVIOM0 0x0608
#define B16SOC_AXI_RRESP_CTRL_AVIOM0 0x0608
#define LSb32SOC_AXI_RRESP_CTRL_AVIOM0 1
#define LSb16SOC_AXI_RRESP_CTRL_AVIOM0 1
#define bSOC_AXI_RRESP_CTRL_AVIOM0 1
#define MSK32SOC_AXI_RRESP_CTRL_AVIOM0 0x00000002
#define BA_SOC_AXI_RRESP_CTRL_AVIOM1 0x0608
#define B16SOC_AXI_RRESP_CTRL_AVIOM1 0x0608
#define LSb32SOC_AXI_RRESP_CTRL_AVIOM1 2
#define LSb16SOC_AXI_RRESP_CTRL_AVIOM1 2
#define bSOC_AXI_RRESP_CTRL_AVIOM1 1
#define MSK32SOC_AXI_RRESP_CTRL_AVIOM1 0x00000004
#define BA_SOC_AXI_RRESP_CTRL_GFX3D 0x0608
#define B16SOC_AXI_RRESP_CTRL_GFX3D 0x0608
#define LSb32SOC_AXI_RRESP_CTRL_GFX3D 3
#define LSb16SOC_AXI_RRESP_CTRL_GFX3D 3
#define bSOC_AXI_RRESP_CTRL_GFX3D 1
#define MSK32SOC_AXI_RRESP_CTRL_GFX3D 0x00000008
#define BA_SOC_AXI_RRESP_CTRL_HTRO 0x0608
#define B16SOC_AXI_RRESP_CTRL_HTRO 0x0608
#define LSb32SOC_AXI_RRESP_CTRL_HTRO 4
#define LSb16SOC_AXI_RRESP_CTRL_HTRO 4
#define bSOC_AXI_RRESP_CTRL_HTRO 1
#define MSK32SOC_AXI_RRESP_CTRL_HTRO 0x00000010
#define BA_SOC_AXI_RRESP_CTRL_MTEST 0x0608
#define B16SOC_AXI_RRESP_CTRL_MTEST 0x0608
#define LSb32SOC_AXI_RRESP_CTRL_MTEST 5
#define LSb16SOC_AXI_RRESP_CTRL_MTEST 5
#define bSOC_AXI_RRESP_CTRL_MTEST 1
#define MSK32SOC_AXI_RRESP_CTRL_MTEST 0x00000020
#define BA_SOC_AXI_RRESP_CTRL_NAND 0x0608
#define B16SOC_AXI_RRESP_CTRL_NAND 0x0608
#define LSb32SOC_AXI_RRESP_CTRL_NAND 6
#define LSb16SOC_AXI_RRESP_CTRL_NAND 6
#define bSOC_AXI_RRESP_CTRL_NAND 1
#define MSK32SOC_AXI_RRESP_CTRL_NAND 0x00000040
#define BA_SOC_AXI_RRESP_CTRL_USBM0 0x0608
#define B16SOC_AXI_RRESP_CTRL_USBM0 0x0608
#define LSb32SOC_AXI_RRESP_CTRL_USBM0 7
#define LSb16SOC_AXI_RRESP_CTRL_USBM0 7
#define bSOC_AXI_RRESP_CTRL_USBM0 1
#define MSK32SOC_AXI_RRESP_CTRL_USBM0 0x00000080
#define BA_SOC_AXI_RRESP_CTRL_SDIO 0x0609
#define B16SOC_AXI_RRESP_CTRL_SDIO 0x0608
#define LSb32SOC_AXI_RRESP_CTRL_SDIO 8
#define LSb16SOC_AXI_RRESP_CTRL_SDIO 8
#define bSOC_AXI_RRESP_CTRL_SDIO 1
#define MSK32SOC_AXI_RRESP_CTRL_SDIO 0x00000100
#define BA_SOC_AXI_RRESP_CTRL_TSP 0x0609
#define B16SOC_AXI_RRESP_CTRL_TSP 0x0608
#define LSb32SOC_AXI_RRESP_CTRL_TSP 9
#define LSb16SOC_AXI_RRESP_CTRL_TSP 9
#define bSOC_AXI_RRESP_CTRL_TSP 1
#define MSK32SOC_AXI_RRESP_CTRL_TSP 0x00000200
#define BA_SOC_AXI_RRESP_CTRL_BCMCPU 0x0609
#define B16SOC_AXI_RRESP_CTRL_BCMCPU 0x0608
#define LSb32SOC_AXI_RRESP_CTRL_BCMCPU 10
#define LSb16SOC_AXI_RRESP_CTRL_BCMCPU 10
#define bSOC_AXI_RRESP_CTRL_BCMCPU 1
#define MSK32SOC_AXI_RRESP_CTRL_BCMCPU 0x00000400
#define BA_SOC_AXI_RRESP_CTRL_BCMDMA 0x0609
#define B16SOC_AXI_RRESP_CTRL_BCMDMA 0x0608
#define LSb32SOC_AXI_RRESP_CTRL_BCMDMA 11
#define LSb16SOC_AXI_RRESP_CTRL_BCMDMA 11
#define bSOC_AXI_RRESP_CTRL_BCMDMA 1
#define MSK32SOC_AXI_RRESP_CTRL_BCMDMA 0x00000800
#define BA_SOC_AXI_RRESP_CTRL_BCMDIR 0x0609
#define B16SOC_AXI_RRESP_CTRL_BCMDIR 0x0608
#define LSb32SOC_AXI_RRESP_CTRL_BCMDIR 12
#define LSb16SOC_AXI_RRESP_CTRL_BCMDIR 12
#define bSOC_AXI_RRESP_CTRL_BCMDIR 1
#define MSK32SOC_AXI_RRESP_CTRL_BCMDIR 0x00001000
///////////////////////////////////////////////////////////
#define RA_SOC_AxiErrMon1 0x0800
///////////////////////////////////////////////////////////
#define RA_SOC_AxiErrMon2 0x0818
///////////////////////////////////////////////////////////
#define RA_SOC_AxiErrMon4 0x0830
///////////////////////////////////////////////////////////
#define RA_SOC_AxiErrMon5 0x0848
///////////////////////////////////////////////////////////
#define RA_SOC_AxiErrMon6 0x0860
///////////////////////////////////////////////////////////
#define RA_SOC_AxiWrFiltAVIO0 0x0900
///////////////////////////////////////////////////////////
#define RA_SOC_AxiWrFiltAVIO1 0x0928
///////////////////////////////////////////////////////////
#define RA_SOC_AxiWrFiltHTRO0 0x0950
///////////////////////////////////////////////////////////
#define RA_SOC_AxiWrFiltTSP 0x0978
///////////////////////////////////////////////////////////
typedef struct SIE_SOC {
///////////////////////////////////////////////////////////
#define GET32SOC_Configuration_blockIFetch(r32) _BFGET_(r32, 0, 0)
#define SET32SOC_Configuration_blockIFetch(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16SOC_Configuration_blockIFetch(r16) _BFGET_(r16, 0, 0)
#define SET16SOC_Configuration_blockIFetch(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32SOC_Configuration_AhbTrcEn(r32) _BFGET_(r32, 1, 1)
#define SET32SOC_Configuration_AhbTrcEn(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16SOC_Configuration_AhbTrcEn(r16) _BFGET_(r16, 1, 1)
#define SET16SOC_Configuration_AhbTrcEn(r16,v) _BFSET_(r16, 1, 1,v)
#define w32SOC_Configuration {\
UNSG32 uConfiguration_blockIFetch : 1;\
UNSG32 uConfiguration_AhbTrcEn : 1;\
UNSG32 RSVDx0_b2 : 30;\
}
union { UNSG32 u32SOC_Configuration;
struct w32SOC_Configuration;
};
///////////////////////////////////////////////////////////
#define GET32SOC_sysIntPol0_Invert(r32) _BFGET_(r32,31, 0)
#define SET32SOC_sysIntPol0_Invert(r32,v) _BFSET_(r32,31, 0,v)
#define w32SOC_sysIntPol0 {\
UNSG32 usysIntPol0_Invert : 32;\
}
union { UNSG32 u32SOC_sysIntPol0;
struct w32SOC_sysIntPol0;
};
///////////////////////////////////////////////////////////
#define GET32SOC_sysIntPol1_Invert(r32) _BFGET_(r32,31, 0)
#define SET32SOC_sysIntPol1_Invert(r32,v) _BFSET_(r32,31, 0,v)
#define w32SOC_sysIntPol1 {\
UNSG32 usysIntPol1_Invert : 32;\
}
union { UNSG32 u32SOC_sysIntPol1;
struct w32SOC_sysIntPol1;
};
///////////////////////////////////////////////////////////
#define GET32SOC_sysIntPol2_Invert(r32) _BFGET_(r32,31, 0)
#define SET32SOC_sysIntPol2_Invert(r32,v) _BFSET_(r32,31, 0,v)
#define w32SOC_sysIntPol2 {\
UNSG32 usysIntPol2_Invert : 32;\
}
union { UNSG32 u32SOC_sysIntPol2;
struct w32SOC_sysIntPol2;
};
///////////////////////////////////////////////////////////
#define GET32SOC_sysIntPol3_Invert(r32) _BFGET_(r32,31, 0)
#define SET32SOC_sysIntPol3_Invert(r32,v) _BFSET_(r32,31, 0,v)
#define w32SOC_sysIntPol3 {\
UNSG32 usysIntPol3_Invert : 32;\
}
union { UNSG32 u32SOC_sysIntPol3;
struct w32SOC_sysIntPol3;
};
///////////////////////////////////////////////////////////
UNSG8 RSVDx14 [236];
///////////////////////////////////////////////////////////
SIE_protOR ie_protOR;
///////////////////////////////////////////////////////////
SIE_AxiPCnt ie_GFX3D_PC;
///////////////////////////////////////////////////////////
UNSG8 RSVDx15C [164];
///////////////////////////////////////////////////////////
SIE_seRegionX ie_SecureRegionCtrl0;
///////////////////////////////////////////////////////////
SIE_seRegionX ie_SecureRegionCtrl1;
///////////////////////////////////////////////////////////
SIE_seRegionX ie_SecureRegionCtrl2;
///////////////////////////////////////////////////////////
SIE_seRegionX ie_SecureRegionCtrl3;
///////////////////////////////////////////////////////////
#define GET32SOC_AHB_RESP_CTRL_MaskHrespDef(r32) _BFGET_(r32, 0, 0)
#define SET32SOC_AHB_RESP_CTRL_MaskHrespDef(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16SOC_AHB_RESP_CTRL_MaskHrespDef(r16) _BFGET_(r16, 0, 0)
#define SET16SOC_AHB_RESP_CTRL_MaskHrespDef(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32SOC_AHB_RESP_CTRL_MaskHrespSe(r32) _BFGET_(r32, 1, 1)
#define SET32SOC_AHB_RESP_CTRL_MaskHrespSe(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16SOC_AHB_RESP_CTRL_MaskHrespSe(r16) _BFGET_(r16, 1, 1)
#define SET16SOC_AHB_RESP_CTRL_MaskHrespSe(r16,v) _BFSET_(r16, 1, 1,v)
#define w32SOC_AHB_RESP_CTRL {\
UNSG32 uAHB_RESP_CTRL_MaskHrespDef : 1;\
UNSG32 uAHB_RESP_CTRL_MaskHrespSe : 1;\
UNSG32 RSVDx600_b2 : 30;\
}
union { UNSG32 u32SOC_AHB_RESP_CTRL;
struct w32SOC_AHB_RESP_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32SOC_AXI_BRESP_CTRL_CA7(r32) _BFGET_(r32, 0, 0)
#define SET32SOC_AXI_BRESP_CTRL_CA7(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16SOC_AXI_BRESP_CTRL_CA7(r16) _BFGET_(r16, 0, 0)
#define SET16SOC_AXI_BRESP_CTRL_CA7(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32SOC_AXI_BRESP_CTRL_AVIOM0(r32) _BFGET_(r32, 1, 1)
#define SET32SOC_AXI_BRESP_CTRL_AVIOM0(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16SOC_AXI_BRESP_CTRL_AVIOM0(r16) _BFGET_(r16, 1, 1)
#define SET16SOC_AXI_BRESP_CTRL_AVIOM0(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32SOC_AXI_BRESP_CTRL_AVIOM1(r32) _BFGET_(r32, 2, 2)
#define SET32SOC_AXI_BRESP_CTRL_AVIOM1(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16SOC_AXI_BRESP_CTRL_AVIOM1(r16) _BFGET_(r16, 2, 2)
#define SET16SOC_AXI_BRESP_CTRL_AVIOM1(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32SOC_AXI_BRESP_CTRL_GFX3D(r32) _BFGET_(r32, 3, 3)
#define SET32SOC_AXI_BRESP_CTRL_GFX3D(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16SOC_AXI_BRESP_CTRL_GFX3D(r16) _BFGET_(r16, 3, 3)
#define SET16SOC_AXI_BRESP_CTRL_GFX3D(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32SOC_AXI_BRESP_CTRL_HTRO(r32) _BFGET_(r32, 4, 4)
#define SET32SOC_AXI_BRESP_CTRL_HTRO(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16SOC_AXI_BRESP_CTRL_HTRO(r16) _BFGET_(r16, 4, 4)
#define SET16SOC_AXI_BRESP_CTRL_HTRO(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32SOC_AXI_BRESP_CTRL_MTEST(r32) _BFGET_(r32, 5, 5)
#define SET32SOC_AXI_BRESP_CTRL_MTEST(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16SOC_AXI_BRESP_CTRL_MTEST(r16) _BFGET_(r16, 5, 5)
#define SET16SOC_AXI_BRESP_CTRL_MTEST(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32SOC_AXI_BRESP_CTRL_BMON(r32) _BFGET_(r32, 6, 6)
#define SET32SOC_AXI_BRESP_CTRL_BMON(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16SOC_AXI_BRESP_CTRL_BMON(r16) _BFGET_(r16, 6, 6)
#define SET16SOC_AXI_BRESP_CTRL_BMON(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32SOC_AXI_BRESP_CTRL_NAND(r32) _BFGET_(r32, 7, 7)
#define SET32SOC_AXI_BRESP_CTRL_NAND(r32,v) _BFSET_(r32, 7, 7,v)
#define GET16SOC_AXI_BRESP_CTRL_NAND(r16) _BFGET_(r16, 7, 7)
#define SET16SOC_AXI_BRESP_CTRL_NAND(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32SOC_AXI_BRESP_CTRL_USBM0(r32) _BFGET_(r32, 8, 8)
#define SET32SOC_AXI_BRESP_CTRL_USBM0(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16SOC_AXI_BRESP_CTRL_USBM0(r16) _BFGET_(r16, 8, 8)
#define SET16SOC_AXI_BRESP_CTRL_USBM0(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32SOC_AXI_BRESP_CTRL_SDIO(r32) _BFGET_(r32, 9, 9)
#define SET32SOC_AXI_BRESP_CTRL_SDIO(r32,v) _BFSET_(r32, 9, 9,v)
#define GET16SOC_AXI_BRESP_CTRL_SDIO(r16) _BFGET_(r16, 9, 9)
#define SET16SOC_AXI_BRESP_CTRL_SDIO(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32SOC_AXI_BRESP_CTRL_TSP(r32) _BFGET_(r32,10,10)
#define SET32SOC_AXI_BRESP_CTRL_TSP(r32,v) _BFSET_(r32,10,10,v)
#define GET16SOC_AXI_BRESP_CTRL_TSP(r16) _BFGET_(r16,10,10)
#define SET16SOC_AXI_BRESP_CTRL_TSP(r16,v) _BFSET_(r16,10,10,v)
#define GET32SOC_AXI_BRESP_CTRL_BCMCPU(r32) _BFGET_(r32,11,11)
#define SET32SOC_AXI_BRESP_CTRL_BCMCPU(r32,v) _BFSET_(r32,11,11,v)
#define GET16SOC_AXI_BRESP_CTRL_BCMCPU(r16) _BFGET_(r16,11,11)
#define SET16SOC_AXI_BRESP_CTRL_BCMCPU(r16,v) _BFSET_(r16,11,11,v)
#define GET32SOC_AXI_BRESP_CTRL_BCMDMA(r32) _BFGET_(r32,12,12)
#define SET32SOC_AXI_BRESP_CTRL_BCMDMA(r32,v) _BFSET_(r32,12,12,v)
#define GET16SOC_AXI_BRESP_CTRL_BCMDMA(r16) _BFGET_(r16,12,12)
#define SET16SOC_AXI_BRESP_CTRL_BCMDMA(r16,v) _BFSET_(r16,12,12,v)
#define GET32SOC_AXI_BRESP_CTRL_BCMDIR(r32) _BFGET_(r32,13,13)
#define SET32SOC_AXI_BRESP_CTRL_BCMDIR(r32,v) _BFSET_(r32,13,13,v)
#define GET16SOC_AXI_BRESP_CTRL_BCMDIR(r16) _BFGET_(r16,13,13)
#define SET16SOC_AXI_BRESP_CTRL_BCMDIR(r16,v) _BFSET_(r16,13,13,v)
#define w32SOC_AXI_BRESP_CTRL {\
UNSG32 uAXI_BRESP_CTRL_CA7 : 1;\
UNSG32 uAXI_BRESP_CTRL_AVIOM0 : 1;\
UNSG32 uAXI_BRESP_CTRL_AVIOM1 : 1;\
UNSG32 uAXI_BRESP_CTRL_GFX3D : 1;\
UNSG32 uAXI_BRESP_CTRL_HTRO : 1;\
UNSG32 uAXI_BRESP_CTRL_MTEST : 1;\
UNSG32 uAXI_BRESP_CTRL_BMON : 1;\
UNSG32 uAXI_BRESP_CTRL_NAND : 1;\
UNSG32 uAXI_BRESP_CTRL_USBM0 : 1;\
UNSG32 uAXI_BRESP_CTRL_SDIO : 1;\
UNSG32 uAXI_BRESP_CTRL_TSP : 1;\
UNSG32 uAXI_BRESP_CTRL_BCMCPU : 1;\
UNSG32 uAXI_BRESP_CTRL_BCMDMA : 1;\
UNSG32 uAXI_BRESP_CTRL_BCMDIR : 1;\
UNSG32 RSVDx604_b14 : 18;\
}
union { UNSG32 u32SOC_AXI_BRESP_CTRL;
struct w32SOC_AXI_BRESP_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32SOC_AXI_RRESP_CTRL_CA7(r32) _BFGET_(r32, 0, 0)
#define SET32SOC_AXI_RRESP_CTRL_CA7(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16SOC_AXI_RRESP_CTRL_CA7(r16) _BFGET_(r16, 0, 0)
#define SET16SOC_AXI_RRESP_CTRL_CA7(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32SOC_AXI_RRESP_CTRL_AVIOM0(r32) _BFGET_(r32, 1, 1)
#define SET32SOC_AXI_RRESP_CTRL_AVIOM0(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16SOC_AXI_RRESP_CTRL_AVIOM0(r16) _BFGET_(r16, 1, 1)
#define SET16SOC_AXI_RRESP_CTRL_AVIOM0(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32SOC_AXI_RRESP_CTRL_AVIOM1(r32) _BFGET_(r32, 2, 2)
#define SET32SOC_AXI_RRESP_CTRL_AVIOM1(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16SOC_AXI_RRESP_CTRL_AVIOM1(r16) _BFGET_(r16, 2, 2)
#define SET16SOC_AXI_RRESP_CTRL_AVIOM1(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32SOC_AXI_RRESP_CTRL_GFX3D(r32) _BFGET_(r32, 3, 3)
#define SET32SOC_AXI_RRESP_CTRL_GFX3D(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16SOC_AXI_RRESP_CTRL_GFX3D(r16) _BFGET_(r16, 3, 3)
#define SET16SOC_AXI_RRESP_CTRL_GFX3D(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32SOC_AXI_RRESP_CTRL_HTRO(r32) _BFGET_(r32, 4, 4)
#define SET32SOC_AXI_RRESP_CTRL_HTRO(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16SOC_AXI_RRESP_CTRL_HTRO(r16) _BFGET_(r16, 4, 4)
#define SET16SOC_AXI_RRESP_CTRL_HTRO(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32SOC_AXI_RRESP_CTRL_MTEST(r32) _BFGET_(r32, 5, 5)
#define SET32SOC_AXI_RRESP_CTRL_MTEST(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16SOC_AXI_RRESP_CTRL_MTEST(r16) _BFGET_(r16, 5, 5)
#define SET16SOC_AXI_RRESP_CTRL_MTEST(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32SOC_AXI_RRESP_CTRL_NAND(r32) _BFGET_(r32, 6, 6)
#define SET32SOC_AXI_RRESP_CTRL_NAND(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16SOC_AXI_RRESP_CTRL_NAND(r16) _BFGET_(r16, 6, 6)
#define SET16SOC_AXI_RRESP_CTRL_NAND(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32SOC_AXI_RRESP_CTRL_USBM0(r32) _BFGET_(r32, 7, 7)
#define SET32SOC_AXI_RRESP_CTRL_USBM0(r32,v) _BFSET_(r32, 7, 7,v)
#define GET16SOC_AXI_RRESP_CTRL_USBM0(r16) _BFGET_(r16, 7, 7)
#define SET16SOC_AXI_RRESP_CTRL_USBM0(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32SOC_AXI_RRESP_CTRL_SDIO(r32) _BFGET_(r32, 8, 8)
#define SET32SOC_AXI_RRESP_CTRL_SDIO(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16SOC_AXI_RRESP_CTRL_SDIO(r16) _BFGET_(r16, 8, 8)
#define SET16SOC_AXI_RRESP_CTRL_SDIO(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32SOC_AXI_RRESP_CTRL_TSP(r32) _BFGET_(r32, 9, 9)
#define SET32SOC_AXI_RRESP_CTRL_TSP(r32,v) _BFSET_(r32, 9, 9,v)
#define GET16SOC_AXI_RRESP_CTRL_TSP(r16) _BFGET_(r16, 9, 9)
#define SET16SOC_AXI_RRESP_CTRL_TSP(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32SOC_AXI_RRESP_CTRL_BCMCPU(r32) _BFGET_(r32,10,10)
#define SET32SOC_AXI_RRESP_CTRL_BCMCPU(r32,v) _BFSET_(r32,10,10,v)
#define GET16SOC_AXI_RRESP_CTRL_BCMCPU(r16) _BFGET_(r16,10,10)
#define SET16SOC_AXI_RRESP_CTRL_BCMCPU(r16,v) _BFSET_(r16,10,10,v)
#define GET32SOC_AXI_RRESP_CTRL_BCMDMA(r32) _BFGET_(r32,11,11)
#define SET32SOC_AXI_RRESP_CTRL_BCMDMA(r32,v) _BFSET_(r32,11,11,v)
#define GET16SOC_AXI_RRESP_CTRL_BCMDMA(r16) _BFGET_(r16,11,11)
#define SET16SOC_AXI_RRESP_CTRL_BCMDMA(r16,v) _BFSET_(r16,11,11,v)
#define GET32SOC_AXI_RRESP_CTRL_BCMDIR(r32) _BFGET_(r32,12,12)
#define SET32SOC_AXI_RRESP_CTRL_BCMDIR(r32,v) _BFSET_(r32,12,12,v)
#define GET16SOC_AXI_RRESP_CTRL_BCMDIR(r16) _BFGET_(r16,12,12)
#define SET16SOC_AXI_RRESP_CTRL_BCMDIR(r16,v) _BFSET_(r16,12,12,v)
#define w32SOC_AXI_RRESP_CTRL {\
UNSG32 uAXI_RRESP_CTRL_CA7 : 1;\
UNSG32 uAXI_RRESP_CTRL_AVIOM0 : 1;\
UNSG32 uAXI_RRESP_CTRL_AVIOM1 : 1;\
UNSG32 uAXI_RRESP_CTRL_GFX3D : 1;\
UNSG32 uAXI_RRESP_CTRL_HTRO : 1;\
UNSG32 uAXI_RRESP_CTRL_MTEST : 1;\
UNSG32 uAXI_RRESP_CTRL_NAND : 1;\
UNSG32 uAXI_RRESP_CTRL_USBM0 : 1;\
UNSG32 uAXI_RRESP_CTRL_SDIO : 1;\
UNSG32 uAXI_RRESP_CTRL_TSP : 1;\
UNSG32 uAXI_RRESP_CTRL_BCMCPU : 1;\
UNSG32 uAXI_RRESP_CTRL_BCMDMA : 1;\
UNSG32 uAXI_RRESP_CTRL_BCMDIR : 1;\
UNSG32 RSVDx608_b13 : 19;\
}
union { UNSG32 u32SOC_AXI_RRESP_CTRL;
struct w32SOC_AXI_RRESP_CTRL;
};
///////////////////////////////////////////////////////////
UNSG8 RSVDx60C [500];
///////////////////////////////////////////////////////////
SIE_AxiErrorMon ie_AxiErrMon1;
///////////////////////////////////////////////////////////
SIE_AxiErrorMon ie_AxiErrMon2;
///////////////////////////////////////////////////////////
SIE_AxiErrorMon ie_AxiErrMon4;
///////////////////////////////////////////////////////////
SIE_AxiErrorMon ie_AxiErrMon5;
///////////////////////////////////////////////////////////
SIE_AxiErrorMon ie_AxiErrMon6;
///////////////////////////////////////////////////////////
UNSG8 RSVDx878 [136];
///////////////////////////////////////////////////////////
SIE_AxiWrFilt ie_AxiWrFiltAVIO0;
///////////////////////////////////////////////////////////
SIE_AxiWrFilt ie_AxiWrFiltAVIO1;
///////////////////////////////////////////////////////////
SIE_AxiWrFilt ie_AxiWrFiltHTRO0;
///////////////////////////////////////////////////////////
SIE_AxiWrFilt ie_AxiWrFiltTSP;
///////////////////////////////////////////////////////////
} SIE_SOC;
typedef union T32SOC_Configuration
{ UNSG32 u32;
struct w32SOC_Configuration;
} T32SOC_Configuration;
typedef union T32SOC_sysIntPol0
{ UNSG32 u32;
struct w32SOC_sysIntPol0;
} T32SOC_sysIntPol0;
typedef union T32SOC_sysIntPol1
{ UNSG32 u32;
struct w32SOC_sysIntPol1;
} T32SOC_sysIntPol1;
typedef union T32SOC_sysIntPol2
{ UNSG32 u32;
struct w32SOC_sysIntPol2;
} T32SOC_sysIntPol2;
typedef union T32SOC_sysIntPol3
{ UNSG32 u32;
struct w32SOC_sysIntPol3;
} T32SOC_sysIntPol3;
typedef union T32SOC_AHB_RESP_CTRL
{ UNSG32 u32;
struct w32SOC_AHB_RESP_CTRL;
} T32SOC_AHB_RESP_CTRL;
typedef union T32SOC_AXI_BRESP_CTRL
{ UNSG32 u32;
struct w32SOC_AXI_BRESP_CTRL;
} T32SOC_AXI_BRESP_CTRL;
typedef union T32SOC_AXI_RRESP_CTRL
{ UNSG32 u32;
struct w32SOC_AXI_RRESP_CTRL;
} T32SOC_AXI_RRESP_CTRL;
///////////////////////////////////////////////////////////
typedef union TSOC_Configuration
{ UNSG32 u32[1];
struct {
struct w32SOC_Configuration;
};
} TSOC_Configuration;
typedef union TSOC_sysIntPol0
{ UNSG32 u32[1];
struct {
struct w32SOC_sysIntPol0;
};
} TSOC_sysIntPol0;
typedef union TSOC_sysIntPol1
{ UNSG32 u32[1];
struct {
struct w32SOC_sysIntPol1;
};
} TSOC_sysIntPol1;
typedef union TSOC_sysIntPol2
{ UNSG32 u32[1];
struct {
struct w32SOC_sysIntPol2;
};
} TSOC_sysIntPol2;
typedef union TSOC_sysIntPol3
{ UNSG32 u32[1];
struct {
struct w32SOC_sysIntPol3;
};
} TSOC_sysIntPol3;
typedef union TSOC_AHB_RESP_CTRL
{ UNSG32 u32[1];
struct {
struct w32SOC_AHB_RESP_CTRL;
};
} TSOC_AHB_RESP_CTRL;
typedef union TSOC_AXI_BRESP_CTRL
{ UNSG32 u32[1];
struct {
struct w32SOC_AXI_BRESP_CTRL;
};
} TSOC_AXI_BRESP_CTRL;
typedef union TSOC_AXI_RRESP_CTRL
{ UNSG32 u32[1];
struct {
struct w32SOC_AXI_RRESP_CTRL;
};
} TSOC_AXI_RRESP_CTRL;
///////////////////////////////////////////////////////////
SIGN32 SOC_drvrd(SIE_SOC *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 SOC_drvwr(SIE_SOC *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void SOC_reset(SIE_SOC *p);
SIGN32 SOC_cmp (SIE_SOC *p, SIE_SOC *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define SOC_check(p,pie,pfx,hLOG) SOC_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define SOC_print(p, pfx,hLOG) SOC_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: SOC
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE SocCSApbDec (4,4)
/// # # ----------------------------------------------------------
/// : SOCCS_ROM 0x0
/// : SOCCS_ETB 0x1000
/// : SOCCS_CTI 0x2000
/// : SOCCS_FUN 0x4000
/// : CPUINT_ROM 0x20000
/// : CPU0_DBG 0x30000
/// : CPU0_PMU 0x31000
/// : CPU1_DBG 0x32000
/// : CPU1_PMU 0x33000
/// : CPU0_CTI 0x38000
/// : CPU1_CTI 0x39000
/// : CPU0_ETM 0x3C000
/// : CPU1_ETM 0x3D000
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 0B, bits: 0b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_SocCSApbDec
#define h_SocCSApbDec (){}
#define SocCSApbDec_SOCCS_ROM 0x0
#define SocCSApbDec_SOCCS_ETB 0x1000
#define SocCSApbDec_SOCCS_CTI 0x2000
#define SocCSApbDec_SOCCS_FUN 0x4000
#define SocCSApbDec_CPUINT_ROM 0x20000
#define SocCSApbDec_CPU0_DBG 0x30000
#define SocCSApbDec_CPU0_PMU 0x31000
#define SocCSApbDec_CPU1_DBG 0x32000
#define SocCSApbDec_CPU1_PMU 0x33000
#define SocCSApbDec_CPU0_CTI 0x38000
#define SocCSApbDec_CPU1_CTI 0x39000
#define SocCSApbDec_CPU0_ETM 0x3C000
#define SocCSApbDec_CPU1_ETM 0x3D000
///////////////////////////////////////////////////////////
#endif
//////
/// ENDOFINTERFACE: SocCSApbDec
////////////////////////////////////////////////////////////
#ifdef __cplusplus
}
#endif
#pragma pack()
#endif
//////
/// ENDOFFILE: soc.h
////////////////////////////////////////////////////////////