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nest-open-source / manifest_repos / bootloader / 836ad32e08388e0e4ce8d03fe4f14d2c3ea8ba13 / . / berlin_tools / bootloader / include / Firmware_Berlin_BG2CDP_A0 / wol.h
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/********************************************************************************
* Marvell GPL License Option
*
* If you received this File from Marvell, you may opt to use, redistribute and/or
* modify this File in accordance with the terms and conditions of the General
* Public License Version 2, June 1991 (the "GPL License"), a copy of which is
* available along with the File in the license.txt file or by writing to the Free
* Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
* on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
*
* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
* WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
* DISCLAIMED. The GPL License provides additional details about this warranty
* disclaimer.
******************************************************************************/
//////
/// don't edit! auto-generated by docc: wol.h
////////////////////////////////////////////////////////////
#ifndef wol_h
#define wol_h (){}
#include "ctypes.h"
#pragma pack(1)
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _DOCC_H_BITOPS_
#define _DOCC_H_BITOPS_ (){}
#define _bSETMASK_(b) ((b)<32 ? (1<<((b)&31)) : 0)
#define _NSETMASK_(msb,lsb) (_bSETMASK_((msb)+1)-_bSETMASK_(lsb))
#define _bCLRMASK_(b) (~_bSETMASK_(b))
#define _NCLRMASK_(msb,lsb) (~_NSETMASK_(msb,lsb))
#define _BFGET_(r,msb,lsb) (_NSETMASK_((msb)-(lsb),0)&((r)>>(lsb)))
#define _BFSET_(r,msb,lsb,v) do{ (r)&=_NCLRMASK_(msb,lsb); (r)|=_NSETMASK_(msb,lsb)&((v)<<(lsb)); }while(0)
#endif
//////
///
/// $INTERFACE WOL biu (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 CTRL (P)
/// ###
/// * Programs Wake up event and associated DA Filter, RAM Control
/// ###
/// %unsigned 2 WOL_MODE 0x0
/// : DISABLE 0x0
/// : PKT_STORE 0x1
/// : PAT_LOAD 0x2
/// : PAT_READ 0x3
/// ###
/// * Indicates whether WOL RAM is used for Pattern Matching (H/W WOL Event Detection) or Storing incoming packet (128x9) bytes(S/W WOL Event Detection)
/// ###
/// %unsigned 1 RAM_LOAD 0x1
/// ###
/// * 1: CPU loads Patterm RAM; Patterm Match disabled; applicable only in “PAT_LOAD” mode.
/// ###
/// %unsigned 1 LU_EN 0x0
/// ###
/// * Enable Link Up Unit
/// ###
/// %unsigned 1 MP_CMP_EN 0x0
/// ###
/// * Enable Magic Pattern Compare Unit
/// ###
/// %unsigned 2 MP_DA_FILT 0x0
/// : DISABLE 0x0
/// : UCAST 0x1
/// : MCAST 0x2
/// : BCAST 0x3
/// ###
/// * Filter Type
/// ###
/// %unsigned 1 WU_PAT0_CMP_EN 0x0
/// ###
/// * Enable Pattern0 Compare Unit
/// ###
/// %unsigned 2 WU_PAT0_DA_FILT 0x0
/// : DISABLE 0x0
/// : UCAST 0x1
/// : MCAST 0x2
/// : BCAST 0x3
/// ###
/// * Filter Type
/// ###
/// %unsigned 1 WU_PAT1_CMP_EN 0x0
/// ###
/// * Enable Pattern1 Compare Unit
/// ###
/// %unsigned 2 WU_PAT1_DA_FILT 0x0
/// : DISABLE 0x0
/// : UCAST 0x1
/// : MCAST 0x2
/// : BCAST 0x3
/// ###
/// * Filter Type
/// ###
/// %unsigned 1 WU_PAT2_CMP_EN 0x0
/// ###
/// * Enable Pattern2 Compare Unit
/// ###
/// %unsigned 2 WU_PAT2_DA_FILT 0x0
/// : DISABLE 0x0
/// : UCAST 0x1
/// : MCAST 0x2
/// : BCAST 0x3
/// ###
/// * Filter Type
/// ###
/// %unsigned 1 WU_PAT3_CMP_EN 0x0
/// ###
/// * Enable Pattern3 Compare Unit
/// ###
/// %unsigned 2 WU_PAT3_DA_FILT 0x0
/// : DISABLE 0x0
/// : UCAST 0x1
/// : MCAST 0x2
/// : BCAST 0x3
/// ###
/// * Filter Type
/// ###
/// %unsigned 1 WU_PAT4_CMP_EN 0x0
/// ###
/// * Enable Pattern4 Compare Unit
/// ###
/// %unsigned 2 WU_PAT4_DA_FILT 0x0
/// : DISABLE 0x0
/// : UCAST 0x1
/// : MCAST 0x2
/// : BCAST 0x3
/// ###
/// * Filter Type
/// ###
/// %unsigned 1 WU_PAT5_CMP_EN 0x0
/// ###
/// * Enable Pattern5 Compare Unit
/// ###
/// %unsigned 2 WU_PAT5_DA_FILT 0x0
/// : DISABLE 0x0
/// : UCAST 0x1
/// : MCAST 0x2
/// : BCAST 0x3
/// ###
/// * Filter Type
/// ###
/// %unsigned 1 WU_PAT6_CMP_EN 0x0
/// ###
/// * Enable Pattern6 Compare Unit
/// ###
/// %unsigned 2 WU_PAT6_DA_FILT 0x0
/// : DISABLE 0x0
/// : UCAST 0x1
/// : MCAST 0x2
/// : BCAST 0x3
/// ###
/// * Filter Type
/// ###
/// %unsigned 1 WU_PAT7_CMP_EN 0x0
/// ###
/// * Enable Pattern7 Compare Unit
/// ###
/// %unsigned 2 WU_PAT7_DA_FILT 0x0
/// : DISABLE 0x0
/// : UCAST 0x1
/// : MCAST 0x2
/// : BCAST 0x3
/// ###
/// * Filter Type
/// ###
/// %unsigned 1 CRC_IN_REVERSE 0x0
/// ###
/// * Reverses bit order of input to CRC used for MC filter
/// ###
/// @ 0x00004 MAC_ADDR_LO (P)
/// %unsigned 32 DWORD 0x0
/// ###
/// * MAC Address Low Dword [Applicable for UCAST DA Filter]
/// ###
/// @ 0x00008 MAC_ADDR_HI (P)
/// %unsigned 16 WORD 0x0
/// ###
/// * MAC Address High Word [Applicable for UCAST DA Filter]
/// ###
/// %% 16 # Stuffing bits...
/// @ 0x0000C MAGIC_PAT (P)
/// %unsigned 32 WORD0 0x0
/// # 0x00010 MAGIC_PAT1
/// %unsigned 32 WORD1 0x0
/// # 0x00014 MAGIC_PAT2
/// %unsigned 32 WORD2 0x0
/// # 0x00018 MAGIC_PAT3
/// %unsigned 32 WORD3 0x0
/// # 0x0001C MAGIC_PAT4
/// %unsigned 32 WORD4 0x0
/// # 0x00020 MAGIC_PAT5
/// %unsigned 32 WORD5 0x0
/// # 0x00024 MAGIC_PAT6
/// %unsigned 32 WORD6 0x0
/// # 0x00028 MAGIC_PAT7
/// %unsigned 32 WORD7 0x0
/// # 0x0002C MAGIC_PAT8
/// %unsigned 32 WORD8 0x0
/// # 0x00030 MAGIC_PAT9
/// %unsigned 32 WORD9 0x0
/// # 0x00034 MAGIC_PAT10
/// %unsigned 32 WORD10 0x0
/// # 0x00038 MAGIC_PAT11
/// %unsigned 32 WORD11 0x0
/// # 0x0003C MAGIC_PAT12
/// %unsigned 32 WORD12 0x0
/// # 0x00040 MAGIC_PAT13
/// %unsigned 32 WORD13 0x0
/// # 0x00044 MAGIC_PAT14
/// %unsigned 32 WORD14 0x0
/// # 0x00048 MAGIC_PAT15
/// %unsigned 32 WORD15 0x0
/// # 0x0004C MAGIC_PAT16
/// %unsigned 32 WORD16 0x0
/// # 0x00050 MAGIC_PAT17
/// %unsigned 32 WORD17 0x0
/// # 0x00054 MAGIC_PAT18
/// %unsigned 32 WORD18 0x0
/// # 0x00058 MAGIC_PAT19
/// %unsigned 32 WORD19 0x0
/// # 0x0005C MAGIC_PAT20
/// %unsigned 32 WORD20 0x0
/// # 0x00060 MAGIC_PAT21
/// %unsigned 32 WORD21 0x0
/// # 0x00064 MAGIC_PAT22
/// %unsigned 32 WORD22 0x0
/// # 0x00068 MAGIC_PAT23
/// %unsigned 32 WORD23 0x0
/// # 0x0006C MAGIC_PAT24
/// %unsigned 32 WORD24 0x0
/// # 0x00070 MAGIC_PAT25
/// %unsigned 16 WORD25 0x0
/// ###
/// * Programmable Magic Pattern
/// * WORD0-LSB
/// * WORD25-MSB
/// ###
/// %% 16 # Stuffing bits...
/// @ 0x00074 MAGIC_PAT_LEN (P)
/// %unsigned 8 ZERO 0x66
/// ###
/// * Magic Pattern Length (Bytes)
/// ###
/// %% 24 # Stuffing bits...
/// @ 0x00078 MC_ADDR_HASH0 (P)
/// %unsigned 32 LO 0x0
/// ###
/// * Multicast Address Hash Low
/// ###
/// @ 0x0007C MC_ADDR_HASH1 (P)
/// %unsigned 32 HI 0x0
/// ###
/// * Multicast Address Hash High
/// ###
/// @ 0x00080 MIN_STORE_LEN (P)
/// %unsigned 16 BYTES 0x40
/// ###
/// * Minimum size of incoming packet to be qualified to get stored in RAM to generate PKT_STORE WoL event.
/// ###
/// %% 16 # Stuffing bits...
/// @ 0x00084 UP_STORE_LEN (R-)
/// %unsigned 16 BYTES 0x0
/// ###
/// * Number of bytes of Packet stored in RAM
/// ###
/// %% 16 # Stuffing bits...
/// @ 0x00088 PAT_LEN0_3 (P)
/// ###
/// * Pattern Length
/// * Maximum 128 bytes
/// ###
/// %unsigned 8 ZERO 0x0
/// ###
/// * Pattern 0 Length
/// ###
/// %unsigned 8 ONE 0x4
/// ###
/// * Pattern 1 Length
/// ###
/// %unsigned 8 TWO 0x0
/// ###
/// * Pattern 2 Length
/// ###
/// %unsigned 8 THREE 0x0
/// ###
/// * Pattern 3 Length
/// ###
/// @ 0x0008C PAT_LEN4_7 (P)
/// ###
/// * Pattern Length
/// * Maximum 128 bytes
/// ###
/// %unsigned 8 FOUR 0x0
/// ###
/// * Pattern 4 Length
/// ###
/// %unsigned 8 FIVE 0x0
/// ###
/// * Pattern 5 Length
/// ###
/// %unsigned 8 SIX 0x0
/// ###
/// * Pattern 6 Length
/// ###
/// %unsigned 8 SEVEN 0x0
/// ###
/// * Pattern 7 Length
/// ###
/// @ 0x00090 RAM_CTRL (P)
/// ###
/// * Write to this register is used to control read from /write to RAM from CPU.
/// * WOL_MODE, RAM_LOAD needs to set appropriately before writing to this register.
/// ###
/// %unsigned 8 CMD 0x0
/// : WRITE 0x1
/// : READ 0x2
/// ###
/// * If CMD==WRITE, write to this register triggers loading of {BYTE_PAT_8,BYTE_PAT_7_4,BYTE_PAT_3_0} at address location BYTE_NO of Pattern RAM.
/// * Write valid only if RAM_LOAD==1
/// * If CMD==READ, write to this register triggers loading of contents at address location BYTE_NO of Pattern RAM to {BYTE_PAT_8,BYTE_PAT_7_4,BYTE_PAT_3_0} registers.
/// ###
/// %unsigned 8 BYTE_NO 0x0
/// ###
/// * Byte Number
/// ###
/// %% 16 # Stuffing bits...
/// @ 0x00094 RAM_DATA_0 (RW)
/// %unsigned 32 BYTE_PAT_3_0 0x0
/// ###
/// * BYTE_PAT_3_0 of Pattern RAM
/// * Write valid only if RAM_LOAD==1
/// ###
/// @ 0x00098 RAM_DATA_1 (RW)
/// %unsigned 32 BYTE_PAT_7_4 0x0
/// ###
/// * BYTE_PAT_7_4 of Pattern RAM
/// * Write valid only if RAM_LOAD==1
/// ###
/// @ 0x0009C RAM_DATA_2 (P)
/// %unsigned 8 BYTE_PAT_8 0x0
/// ###
/// * BYTE_PAT_8 of Pattern RAM. Mask for Patten<n>
/// * Write valid only if RAM_LOAD==1
/// ###
/// %% 24 # Stuffing bits...
/// @ 0x000A0 RCV_MAC_ADDR_LO (R-)
/// %unsigned 32 DWORD 0x0
/// ###
/// * Received MAC Address Low Dword
/// ###
/// @ 0x000A4 RCV_MAC_ADDR_HI (R-)
/// %unsigned 16 WORD 0x0
/// ###
/// * Received MAC Address High Word
/// ###
/// %% 16 # Stuffing bits...
/// @ 0x000A8 INT_STATUS (WOC-)
/// ###
/// * Interrupt is triggered based on different Wake Up events enabled in CTRL register.
/// * Interrupt status register. SW shall write 1 to clear the particular bit. Write 0 has no effect.
/// ###
/// %unsigned 1 PKT_STORE 0x0
/// ###
/// * Interrupt on Packet (128x8 bytes) Store Event. Applicable only for PKT_STORE mode.
/// ###
/// %unsigned 1 LINK_DOWN 0x0
/// ###
/// * Interrupt on Link Down Event
/// ###
/// %unsigned 1 LINK_UP 0x0
/// ###
/// * Interrupt on Link Up Wake Up Event
/// ###
/// %unsigned 1 MAGIC_PATTERN 0x0
/// ###
/// * Interrupt on Magic Pattern Wake Up Event
/// ###
/// %unsigned 1 WAKE_UP_PAT0 0x0
/// ###
/// * Interrupt on Wake Up Pattern 0 Match Event
/// ###
/// %unsigned 1 WAKE_UP_PAT1 0x0
/// ###
/// * Interrupt on Wake Up Pattern 1 Match Event
/// ###
/// %unsigned 1 WAKE_UP_PAT2 0x0
/// ###
/// * Interrupt on Wake Up Pattern 2 Match Event
/// ###
/// %unsigned 1 WAKE_UP_PAT3 0x0
/// ###
/// * Interrupt on Wake Up Pattern 3 Match Event
/// ###
/// %unsigned 1 WAKE_UP_PAT4 0x0
/// ###
/// * Interrupt on Wake Up Pattern 4 Match Event
/// ###
/// %unsigned 1 WAKE_UP_PAT5 0x0
/// ###
/// * Interrupt on Wake Up Pattern 5 Match Event
/// ###
/// %unsigned 1 WAKE_UP_PAT6 0x0
/// ###
/// * Interrupt on Wake Up Pattern 6 Match Event
/// ###
/// %unsigned 1 WAKE_UP_PAT7 0x0
/// ###
/// * Interrupt on Wake Up Pattern 7 Match Event
/// ###
/// %% 20 # Stuffing bits...
/// @ 0x000AC INT_MASK (P)
/// ###
/// * Interrupt mask register. SW writes 1 to particular bit to mask that interrupt event. 0 enables the interrupt from that event.
/// ###
/// %unsigned 1 PKT_STORE 0x1
/// %unsigned 1 LINK_DOWN 0x1
/// %unsigned 1 LINK_UP 0x0
/// %unsigned 1 MAGIC_PATTERN 0x1
/// %unsigned 1 WAKE_UP_PAT0 0x1
/// %unsigned 1 WAKE_UP_PAT1 0x1
/// %unsigned 1 WAKE_UP_PAT2 0x1
/// %unsigned 1 WAKE_UP_PAT3 0x1
/// %unsigned 1 WAKE_UP_PAT4 0x1
/// %unsigned 1 WAKE_UP_PAT5 0x1
/// %unsigned 1 WAKE_UP_PAT6 0x1
/// %unsigned 1 WAKE_UP_PAT7 0x1
/// %% 20 # Stuffing bits...
/// @ 0x000B0 FEPHY_CTRL (P)
/// ###
/// * This register is not used. The FE-PHY is controlled from CEC BIU.
/// * *INTERNAL_ONLY**
/// * Configuration registers for Fast Ethernet PHY
/// ###
/// %unsigned 5 ext_pwrdn_a 0x0
/// ###
/// * When ext_pwrdn_a transitions from 1 to 0 register
/// * 0.11 set to 1'b0
/// * When ext_pwrdn_a transitions from 0 to 1 register
/// * 0.11 set to 1'b1
/// ###
/// %unsigned 3 pd_aneg_mode_a 0x0
/// ###
/// * Port 0 Autoneg default setup:
/// * 000 = force 10T
/// * 001 = force 100T
/// * 010 = advertise all 10/100 capabilities
/// * 011 = reserved
/// * 1xx = force 100FX
/// ###
/// %unsigned 5 pd_phyadr_a 0x0
/// ###
/// * Starting PHY address for Port0
/// * Port 1 PHY address = Port 0 PHY address + 1
/// * Port 2 PHY address = Port 1 PHY address + 1
/// * Port 3 PHY address = Port 2 PHY address + 1
/// * Port 4 PHY address = Port 3 PHY address + 1
/// ###
/// %unsigned 3 pd_led_config_a 0x0
/// ###
/// * change led registers 24:8:0 default
/// * 000 : 001 000 101
/// * 001 : 000 001 101
/// * 010 : 000 001 101
/// * 011 : 000 000 001
/// * 1xx : 000 000 101
/// * and change register 22.15:0 default
/// * 000: 0100 0100 0101 1000
/// * 001: 0100 0101 0100 1000
/// * 010: 0100 0010 0100 1010
/// * 011: 0100 1000 1010 0100
/// * 100: 0100 0010 0101 1000
/// * 101, 11x: 0100 1010 0100 0100
/// ###
/// %unsigned 5 yy_pecl_sdet_a 0x0
/// ###
/// * 100FX signal detect, only bit 0 for port 0 useful
/// ###
/// %unsigned 1 ps_en_eee10t_s 0x0
/// ###
/// * Enable EEE 10T. Compliant with EEE draft 1.2.
/// ###
/// %unsigned 1 ps_en_eee100t_s 0x0
/// ###
/// * Enable EEE 100T. Compliant with EEE draft 1.2.
/// ###
/// %unsigned 1 pd_burnin_a 0x0
/// ###
/// * 1 : put PHY in burn-in mode
/// * In Burnin a LFSR will drive RX. Hook up RX to TX to make chip in burnin.
/// ###
/// %unsigned 1 pd_ena_edet_a 0x0
/// ###
/// * Enable Energy detect.
/// * It is sampled on the deassertion of hardware reset
/// * and set the default of register 16.14
/// ###
/// %unsigned 1 pd_ena_xc_a 0x0
/// ###
/// * 1 : Enable Auto-Crossover; 0 : Disable
/// * Auto-Crossover
/// * Sets the default of Register 16.5:4
/// ###
/// %% 6 # Stuffing bits...
/// @ 0x000B4 FEPHY_STS (R-)
/// ###
/// * This register is not used. The FE-PHY is controlled from CEC BIU.
/// * *INTERNAL_ONLY**
/// ###
/// %unsigned 1 misc_speed_s 0x0
/// ###
/// * Speed indicator; 1: 100M; 0: 10M
/// ###
/// %unsigned 1 misc_duplex_s 0x0
/// ###
/// * Duplex indicator; 1: full-duplex; 0: half-duplex
/// ###
/// %unsigned 1 misc_hcd_resolved_s 0x0
/// ###
/// * Speed resolved; 1: resolved; 0 : not-resolved
/// ###
/// %unsigned 1 misc_link_s 0x0
/// ###
/// * Link status; 1: up; 0: down
/// ###
/// %unsigned 1 misc_lpi_s 0x0
/// ###
/// * LPI state; 1: in LPI state; 0 : normal state. The
/// * misc_lpi_s signal shows PHY EEE capability status.
/// * Same as register 17.9.
/// ###
/// %unsigned 1 misc_rx_lpi_s 0x0
/// ###
/// * PHY Rx in lpi state
/// ###
/// %unsigned 1 misc_pause_s 0x0
/// ###
/// * Pause indicator; 1: Pause; 0: normal
/// ###
/// %unsigned 1 misc_lp_pause_s 0x0
/// ###
/// * Link partner Pause indicator; 1: Pause; 0: normal
/// ###
/// %unsigned 1 misc_int_s 0x0
/// ###
/// * Port interrupt; 1: interrupt; 0 : no interrupt
/// ###
/// %unsigned 1 misc_edet_status_s 0x0
/// ###
/// * Energy detect status; 1: detected; 0 : no-detected.
/// * Same as register 17.4.
/// ###
/// %unsigned 1 tx_latency_mark_a 0x0
/// ###
/// * transmit enable after TX FIFO
/// ###
/// %unsigned 1 misc_por_reset 0x0
/// ###
/// * Power on reset from analog com
/// ###
/// %% 20 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 184B, bits: 1262b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_WOL
#define h_WOL (){}
#define RA_WOL_CTRL 0x0000
#define BA_WOL_CTRL_WOL_MODE 0x0000
#define B16WOL_CTRL_WOL_MODE 0x0000
#define LSb32WOL_CTRL_WOL_MODE 0
#define LSb16WOL_CTRL_WOL_MODE 0
#define bWOL_CTRL_WOL_MODE 2
#define MSK32WOL_CTRL_WOL_MODE 0x00000003
#define WOL_CTRL_WOL_MODE_DISABLE 0x0
#define WOL_CTRL_WOL_MODE_PKT_STORE 0x1
#define WOL_CTRL_WOL_MODE_PAT_LOAD 0x2
#define WOL_CTRL_WOL_MODE_PAT_READ 0x3
#define BA_WOL_CTRL_RAM_LOAD 0x0000
#define B16WOL_CTRL_RAM_LOAD 0x0000
#define LSb32WOL_CTRL_RAM_LOAD 2
#define LSb16WOL_CTRL_RAM_LOAD 2
#define bWOL_CTRL_RAM_LOAD 1
#define MSK32WOL_CTRL_RAM_LOAD 0x00000004
#define BA_WOL_CTRL_LU_EN 0x0000
#define B16WOL_CTRL_LU_EN 0x0000
#define LSb32WOL_CTRL_LU_EN 3
#define LSb16WOL_CTRL_LU_EN 3
#define bWOL_CTRL_LU_EN 1
#define MSK32WOL_CTRL_LU_EN 0x00000008
#define BA_WOL_CTRL_MP_CMP_EN 0x0000
#define B16WOL_CTRL_MP_CMP_EN 0x0000
#define LSb32WOL_CTRL_MP_CMP_EN 4
#define LSb16WOL_CTRL_MP_CMP_EN 4
#define bWOL_CTRL_MP_CMP_EN 1
#define MSK32WOL_CTRL_MP_CMP_EN 0x00000010
#define BA_WOL_CTRL_MP_DA_FILT 0x0000
#define B16WOL_CTRL_MP_DA_FILT 0x0000
#define LSb32WOL_CTRL_MP_DA_FILT 5
#define LSb16WOL_CTRL_MP_DA_FILT 5
#define bWOL_CTRL_MP_DA_FILT 2
#define MSK32WOL_CTRL_MP_DA_FILT 0x00000060
#define WOL_CTRL_MP_DA_FILT_DISABLE 0x0
#define WOL_CTRL_MP_DA_FILT_UCAST 0x1
#define WOL_CTRL_MP_DA_FILT_MCAST 0x2
#define WOL_CTRL_MP_DA_FILT_BCAST 0x3
#define BA_WOL_CTRL_WU_PAT0_CMP_EN 0x0000
#define B16WOL_CTRL_WU_PAT0_CMP_EN 0x0000
#define LSb32WOL_CTRL_WU_PAT0_CMP_EN 7
#define LSb16WOL_CTRL_WU_PAT0_CMP_EN 7
#define bWOL_CTRL_WU_PAT0_CMP_EN 1
#define MSK32WOL_CTRL_WU_PAT0_CMP_EN 0x00000080
#define BA_WOL_CTRL_WU_PAT0_DA_FILT 0x0001
#define B16WOL_CTRL_WU_PAT0_DA_FILT 0x0000
#define LSb32WOL_CTRL_WU_PAT0_DA_FILT 8
#define LSb16WOL_CTRL_WU_PAT0_DA_FILT 8
#define bWOL_CTRL_WU_PAT0_DA_FILT 2
#define MSK32WOL_CTRL_WU_PAT0_DA_FILT 0x00000300
#define WOL_CTRL_WU_PAT0_DA_FILT_DISABLE 0x0
#define WOL_CTRL_WU_PAT0_DA_FILT_UCAST 0x1
#define WOL_CTRL_WU_PAT0_DA_FILT_MCAST 0x2
#define WOL_CTRL_WU_PAT0_DA_FILT_BCAST 0x3
#define BA_WOL_CTRL_WU_PAT1_CMP_EN 0x0001
#define B16WOL_CTRL_WU_PAT1_CMP_EN 0x0000
#define LSb32WOL_CTRL_WU_PAT1_CMP_EN 10
#define LSb16WOL_CTRL_WU_PAT1_CMP_EN 10
#define bWOL_CTRL_WU_PAT1_CMP_EN 1
#define MSK32WOL_CTRL_WU_PAT1_CMP_EN 0x00000400
#define BA_WOL_CTRL_WU_PAT1_DA_FILT 0x0001
#define B16WOL_CTRL_WU_PAT1_DA_FILT 0x0000
#define LSb32WOL_CTRL_WU_PAT1_DA_FILT 11
#define LSb16WOL_CTRL_WU_PAT1_DA_FILT 11
#define bWOL_CTRL_WU_PAT1_DA_FILT 2
#define MSK32WOL_CTRL_WU_PAT1_DA_FILT 0x00001800
#define WOL_CTRL_WU_PAT1_DA_FILT_DISABLE 0x0
#define WOL_CTRL_WU_PAT1_DA_FILT_UCAST 0x1
#define WOL_CTRL_WU_PAT1_DA_FILT_MCAST 0x2
#define WOL_CTRL_WU_PAT1_DA_FILT_BCAST 0x3
#define BA_WOL_CTRL_WU_PAT2_CMP_EN 0x0001
#define B16WOL_CTRL_WU_PAT2_CMP_EN 0x0000
#define LSb32WOL_CTRL_WU_PAT2_CMP_EN 13
#define LSb16WOL_CTRL_WU_PAT2_CMP_EN 13
#define bWOL_CTRL_WU_PAT2_CMP_EN 1
#define MSK32WOL_CTRL_WU_PAT2_CMP_EN 0x00002000
#define BA_WOL_CTRL_WU_PAT2_DA_FILT 0x0001
#define B16WOL_CTRL_WU_PAT2_DA_FILT 0x0000
#define LSb32WOL_CTRL_WU_PAT2_DA_FILT 14
#define LSb16WOL_CTRL_WU_PAT2_DA_FILT 14
#define bWOL_CTRL_WU_PAT2_DA_FILT 2
#define MSK32WOL_CTRL_WU_PAT2_DA_FILT 0x0000C000
#define WOL_CTRL_WU_PAT2_DA_FILT_DISABLE 0x0
#define WOL_CTRL_WU_PAT2_DA_FILT_UCAST 0x1
#define WOL_CTRL_WU_PAT2_DA_FILT_MCAST 0x2
#define WOL_CTRL_WU_PAT2_DA_FILT_BCAST 0x3
#define BA_WOL_CTRL_WU_PAT3_CMP_EN 0x0002
#define B16WOL_CTRL_WU_PAT3_CMP_EN 0x0002
#define LSb32WOL_CTRL_WU_PAT3_CMP_EN 16
#define LSb16WOL_CTRL_WU_PAT3_CMP_EN 0
#define bWOL_CTRL_WU_PAT3_CMP_EN 1
#define MSK32WOL_CTRL_WU_PAT3_CMP_EN 0x00010000
#define BA_WOL_CTRL_WU_PAT3_DA_FILT 0x0002
#define B16WOL_CTRL_WU_PAT3_DA_FILT 0x0002
#define LSb32WOL_CTRL_WU_PAT3_DA_FILT 17
#define LSb16WOL_CTRL_WU_PAT3_DA_FILT 1
#define bWOL_CTRL_WU_PAT3_DA_FILT 2
#define MSK32WOL_CTRL_WU_PAT3_DA_FILT 0x00060000
#define WOL_CTRL_WU_PAT3_DA_FILT_DISABLE 0x0
#define WOL_CTRL_WU_PAT3_DA_FILT_UCAST 0x1
#define WOL_CTRL_WU_PAT3_DA_FILT_MCAST 0x2
#define WOL_CTRL_WU_PAT3_DA_FILT_BCAST 0x3
#define BA_WOL_CTRL_WU_PAT4_CMP_EN 0x0002
#define B16WOL_CTRL_WU_PAT4_CMP_EN 0x0002
#define LSb32WOL_CTRL_WU_PAT4_CMP_EN 19
#define LSb16WOL_CTRL_WU_PAT4_CMP_EN 3
#define bWOL_CTRL_WU_PAT4_CMP_EN 1
#define MSK32WOL_CTRL_WU_PAT4_CMP_EN 0x00080000
#define BA_WOL_CTRL_WU_PAT4_DA_FILT 0x0002
#define B16WOL_CTRL_WU_PAT4_DA_FILT 0x0002
#define LSb32WOL_CTRL_WU_PAT4_DA_FILT 20
#define LSb16WOL_CTRL_WU_PAT4_DA_FILT 4
#define bWOL_CTRL_WU_PAT4_DA_FILT 2
#define MSK32WOL_CTRL_WU_PAT4_DA_FILT 0x00300000
#define WOL_CTRL_WU_PAT4_DA_FILT_DISABLE 0x0
#define WOL_CTRL_WU_PAT4_DA_FILT_UCAST 0x1
#define WOL_CTRL_WU_PAT4_DA_FILT_MCAST 0x2
#define WOL_CTRL_WU_PAT4_DA_FILT_BCAST 0x3
#define BA_WOL_CTRL_WU_PAT5_CMP_EN 0x0002
#define B16WOL_CTRL_WU_PAT5_CMP_EN 0x0002
#define LSb32WOL_CTRL_WU_PAT5_CMP_EN 22
#define LSb16WOL_CTRL_WU_PAT5_CMP_EN 6
#define bWOL_CTRL_WU_PAT5_CMP_EN 1
#define MSK32WOL_CTRL_WU_PAT5_CMP_EN 0x00400000
#define BA_WOL_CTRL_WU_PAT5_DA_FILT 0x0002
#define B16WOL_CTRL_WU_PAT5_DA_FILT 0x0002
#define LSb32WOL_CTRL_WU_PAT5_DA_FILT 23
#define LSb16WOL_CTRL_WU_PAT5_DA_FILT 7
#define bWOL_CTRL_WU_PAT5_DA_FILT 2
#define MSK32WOL_CTRL_WU_PAT5_DA_FILT 0x01800000
#define WOL_CTRL_WU_PAT5_DA_FILT_DISABLE 0x0
#define WOL_CTRL_WU_PAT5_DA_FILT_UCAST 0x1
#define WOL_CTRL_WU_PAT5_DA_FILT_MCAST 0x2
#define WOL_CTRL_WU_PAT5_DA_FILT_BCAST 0x3
#define BA_WOL_CTRL_WU_PAT6_CMP_EN 0x0003
#define B16WOL_CTRL_WU_PAT6_CMP_EN 0x0002
#define LSb32WOL_CTRL_WU_PAT6_CMP_EN 25
#define LSb16WOL_CTRL_WU_PAT6_CMP_EN 9
#define bWOL_CTRL_WU_PAT6_CMP_EN 1
#define MSK32WOL_CTRL_WU_PAT6_CMP_EN 0x02000000
#define BA_WOL_CTRL_WU_PAT6_DA_FILT 0x0003
#define B16WOL_CTRL_WU_PAT6_DA_FILT 0x0002
#define LSb32WOL_CTRL_WU_PAT6_DA_FILT 26
#define LSb16WOL_CTRL_WU_PAT6_DA_FILT 10
#define bWOL_CTRL_WU_PAT6_DA_FILT 2
#define MSK32WOL_CTRL_WU_PAT6_DA_FILT 0x0C000000
#define WOL_CTRL_WU_PAT6_DA_FILT_DISABLE 0x0
#define WOL_CTRL_WU_PAT6_DA_FILT_UCAST 0x1
#define WOL_CTRL_WU_PAT6_DA_FILT_MCAST 0x2
#define WOL_CTRL_WU_PAT6_DA_FILT_BCAST 0x3
#define BA_WOL_CTRL_WU_PAT7_CMP_EN 0x0003
#define B16WOL_CTRL_WU_PAT7_CMP_EN 0x0002
#define LSb32WOL_CTRL_WU_PAT7_CMP_EN 28
#define LSb16WOL_CTRL_WU_PAT7_CMP_EN 12
#define bWOL_CTRL_WU_PAT7_CMP_EN 1
#define MSK32WOL_CTRL_WU_PAT7_CMP_EN 0x10000000
#define BA_WOL_CTRL_WU_PAT7_DA_FILT 0x0003
#define B16WOL_CTRL_WU_PAT7_DA_FILT 0x0002
#define LSb32WOL_CTRL_WU_PAT7_DA_FILT 29
#define LSb16WOL_CTRL_WU_PAT7_DA_FILT 13
#define bWOL_CTRL_WU_PAT7_DA_FILT 2
#define MSK32WOL_CTRL_WU_PAT7_DA_FILT 0x60000000
#define WOL_CTRL_WU_PAT7_DA_FILT_DISABLE 0x0
#define WOL_CTRL_WU_PAT7_DA_FILT_UCAST 0x1
#define WOL_CTRL_WU_PAT7_DA_FILT_MCAST 0x2
#define WOL_CTRL_WU_PAT7_DA_FILT_BCAST 0x3
#define BA_WOL_CTRL_CRC_IN_REVERSE 0x0003
#define B16WOL_CTRL_CRC_IN_REVERSE 0x0002
#define LSb32WOL_CTRL_CRC_IN_REVERSE 31
#define LSb16WOL_CTRL_CRC_IN_REVERSE 15
#define bWOL_CTRL_CRC_IN_REVERSE 1
#define MSK32WOL_CTRL_CRC_IN_REVERSE 0x80000000
///////////////////////////////////////////////////////////
#define RA_WOL_MAC_ADDR_LO 0x0004
#define BA_WOL_MAC_ADDR_LO_DWORD 0x0004
#define B16WOL_MAC_ADDR_LO_DWORD 0x0004
#define LSb32WOL_MAC_ADDR_LO_DWORD 0
#define LSb16WOL_MAC_ADDR_LO_DWORD 0
#define bWOL_MAC_ADDR_LO_DWORD 32
#define MSK32WOL_MAC_ADDR_LO_DWORD 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_WOL_MAC_ADDR_HI 0x0008
#define BA_WOL_MAC_ADDR_HI_WORD 0x0008
#define B16WOL_MAC_ADDR_HI_WORD 0x0008
#define LSb32WOL_MAC_ADDR_HI_WORD 0
#define LSb16WOL_MAC_ADDR_HI_WORD 0
#define bWOL_MAC_ADDR_HI_WORD 16
#define MSK32WOL_MAC_ADDR_HI_WORD 0x0000FFFF
///////////////////////////////////////////////////////////
#define RA_WOL_MAGIC_PAT 0x000C
#define BA_WOL_MAGIC_PAT_WORD0 0x000C
#define B16WOL_MAGIC_PAT_WORD0 0x000C
#define LSb32WOL_MAGIC_PAT_WORD0 0
#define LSb16WOL_MAGIC_PAT_WORD0 0
#define bWOL_MAGIC_PAT_WORD0 32
#define MSK32WOL_MAGIC_PAT_WORD0 0xFFFFFFFF
#define RA_WOL_MAGIC_PAT1 0x0010
#define BA_WOL_MAGIC_PAT_WORD1 0x0010
#define B16WOL_MAGIC_PAT_WORD1 0x0010
#define LSb32WOL_MAGIC_PAT_WORD1 0
#define LSb16WOL_MAGIC_PAT_WORD1 0
#define bWOL_MAGIC_PAT_WORD1 32
#define MSK32WOL_MAGIC_PAT_WORD1 0xFFFFFFFF
#define RA_WOL_MAGIC_PAT2 0x0014
#define BA_WOL_MAGIC_PAT_WORD2 0x0014
#define B16WOL_MAGIC_PAT_WORD2 0x0014
#define LSb32WOL_MAGIC_PAT_WORD2 0
#define LSb16WOL_MAGIC_PAT_WORD2 0
#define bWOL_MAGIC_PAT_WORD2 32
#define MSK32WOL_MAGIC_PAT_WORD2 0xFFFFFFFF
#define RA_WOL_MAGIC_PAT3 0x0018
#define BA_WOL_MAGIC_PAT_WORD3 0x0018
#define B16WOL_MAGIC_PAT_WORD3 0x0018
#define LSb32WOL_MAGIC_PAT_WORD3 0
#define LSb16WOL_MAGIC_PAT_WORD3 0
#define bWOL_MAGIC_PAT_WORD3 32
#define MSK32WOL_MAGIC_PAT_WORD3 0xFFFFFFFF
#define RA_WOL_MAGIC_PAT4 0x001C
#define BA_WOL_MAGIC_PAT_WORD4 0x001C
#define B16WOL_MAGIC_PAT_WORD4 0x001C
#define LSb32WOL_MAGIC_PAT_WORD4 0
#define LSb16WOL_MAGIC_PAT_WORD4 0
#define bWOL_MAGIC_PAT_WORD4 32
#define MSK32WOL_MAGIC_PAT_WORD4 0xFFFFFFFF
#define RA_WOL_MAGIC_PAT5 0x0020
#define BA_WOL_MAGIC_PAT_WORD5 0x0020
#define B16WOL_MAGIC_PAT_WORD5 0x0020
#define LSb32WOL_MAGIC_PAT_WORD5 0
#define LSb16WOL_MAGIC_PAT_WORD5 0
#define bWOL_MAGIC_PAT_WORD5 32
#define MSK32WOL_MAGIC_PAT_WORD5 0xFFFFFFFF
#define RA_WOL_MAGIC_PAT6 0x0024
#define BA_WOL_MAGIC_PAT_WORD6 0x0024
#define B16WOL_MAGIC_PAT_WORD6 0x0024
#define LSb32WOL_MAGIC_PAT_WORD6 0
#define LSb16WOL_MAGIC_PAT_WORD6 0
#define bWOL_MAGIC_PAT_WORD6 32
#define MSK32WOL_MAGIC_PAT_WORD6 0xFFFFFFFF
#define RA_WOL_MAGIC_PAT7 0x0028
#define BA_WOL_MAGIC_PAT_WORD7 0x0028
#define B16WOL_MAGIC_PAT_WORD7 0x0028
#define LSb32WOL_MAGIC_PAT_WORD7 0
#define LSb16WOL_MAGIC_PAT_WORD7 0
#define bWOL_MAGIC_PAT_WORD7 32
#define MSK32WOL_MAGIC_PAT_WORD7 0xFFFFFFFF
#define RA_WOL_MAGIC_PAT8 0x002C
#define BA_WOL_MAGIC_PAT_WORD8 0x002C
#define B16WOL_MAGIC_PAT_WORD8 0x002C
#define LSb32WOL_MAGIC_PAT_WORD8 0
#define LSb16WOL_MAGIC_PAT_WORD8 0
#define bWOL_MAGIC_PAT_WORD8 32
#define MSK32WOL_MAGIC_PAT_WORD8 0xFFFFFFFF
#define RA_WOL_MAGIC_PAT9 0x0030
#define BA_WOL_MAGIC_PAT_WORD9 0x0030
#define B16WOL_MAGIC_PAT_WORD9 0x0030
#define LSb32WOL_MAGIC_PAT_WORD9 0
#define LSb16WOL_MAGIC_PAT_WORD9 0
#define bWOL_MAGIC_PAT_WORD9 32
#define MSK32WOL_MAGIC_PAT_WORD9 0xFFFFFFFF
#define RA_WOL_MAGIC_PAT10 0x0034
#define BA_WOL_MAGIC_PAT_WORD10 0x0034
#define B16WOL_MAGIC_PAT_WORD10 0x0034
#define LSb32WOL_MAGIC_PAT_WORD10 0
#define LSb16WOL_MAGIC_PAT_WORD10 0
#define bWOL_MAGIC_PAT_WORD10 32
#define MSK32WOL_MAGIC_PAT_WORD10 0xFFFFFFFF
#define RA_WOL_MAGIC_PAT11 0x0038
#define BA_WOL_MAGIC_PAT_WORD11 0x0038
#define B16WOL_MAGIC_PAT_WORD11 0x0038
#define LSb32WOL_MAGIC_PAT_WORD11 0
#define LSb16WOL_MAGIC_PAT_WORD11 0
#define bWOL_MAGIC_PAT_WORD11 32
#define MSK32WOL_MAGIC_PAT_WORD11 0xFFFFFFFF
#define RA_WOL_MAGIC_PAT12 0x003C
#define BA_WOL_MAGIC_PAT_WORD12 0x003C
#define B16WOL_MAGIC_PAT_WORD12 0x003C
#define LSb32WOL_MAGIC_PAT_WORD12 0
#define LSb16WOL_MAGIC_PAT_WORD12 0
#define bWOL_MAGIC_PAT_WORD12 32
#define MSK32WOL_MAGIC_PAT_WORD12 0xFFFFFFFF
#define RA_WOL_MAGIC_PAT13 0x0040
#define BA_WOL_MAGIC_PAT_WORD13 0x0040
#define B16WOL_MAGIC_PAT_WORD13 0x0040
#define LSb32WOL_MAGIC_PAT_WORD13 0
#define LSb16WOL_MAGIC_PAT_WORD13 0
#define bWOL_MAGIC_PAT_WORD13 32
#define MSK32WOL_MAGIC_PAT_WORD13 0xFFFFFFFF
#define RA_WOL_MAGIC_PAT14 0x0044
#define BA_WOL_MAGIC_PAT_WORD14 0x0044
#define B16WOL_MAGIC_PAT_WORD14 0x0044
#define LSb32WOL_MAGIC_PAT_WORD14 0
#define LSb16WOL_MAGIC_PAT_WORD14 0
#define bWOL_MAGIC_PAT_WORD14 32
#define MSK32WOL_MAGIC_PAT_WORD14 0xFFFFFFFF
#define RA_WOL_MAGIC_PAT15 0x0048
#define BA_WOL_MAGIC_PAT_WORD15 0x0048
#define B16WOL_MAGIC_PAT_WORD15 0x0048
#define LSb32WOL_MAGIC_PAT_WORD15 0
#define LSb16WOL_MAGIC_PAT_WORD15 0
#define bWOL_MAGIC_PAT_WORD15 32
#define MSK32WOL_MAGIC_PAT_WORD15 0xFFFFFFFF
#define RA_WOL_MAGIC_PAT16 0x004C
#define BA_WOL_MAGIC_PAT_WORD16 0x004C
#define B16WOL_MAGIC_PAT_WORD16 0x004C
#define LSb32WOL_MAGIC_PAT_WORD16 0
#define LSb16WOL_MAGIC_PAT_WORD16 0
#define bWOL_MAGIC_PAT_WORD16 32
#define MSK32WOL_MAGIC_PAT_WORD16 0xFFFFFFFF
#define RA_WOL_MAGIC_PAT17 0x0050
#define BA_WOL_MAGIC_PAT_WORD17 0x0050
#define B16WOL_MAGIC_PAT_WORD17 0x0050
#define LSb32WOL_MAGIC_PAT_WORD17 0
#define LSb16WOL_MAGIC_PAT_WORD17 0
#define bWOL_MAGIC_PAT_WORD17 32
#define MSK32WOL_MAGIC_PAT_WORD17 0xFFFFFFFF
#define RA_WOL_MAGIC_PAT18 0x0054
#define BA_WOL_MAGIC_PAT_WORD18 0x0054
#define B16WOL_MAGIC_PAT_WORD18 0x0054
#define LSb32WOL_MAGIC_PAT_WORD18 0
#define LSb16WOL_MAGIC_PAT_WORD18 0
#define bWOL_MAGIC_PAT_WORD18 32
#define MSK32WOL_MAGIC_PAT_WORD18 0xFFFFFFFF
#define RA_WOL_MAGIC_PAT19 0x0058
#define BA_WOL_MAGIC_PAT_WORD19 0x0058
#define B16WOL_MAGIC_PAT_WORD19 0x0058
#define LSb32WOL_MAGIC_PAT_WORD19 0
#define LSb16WOL_MAGIC_PAT_WORD19 0
#define bWOL_MAGIC_PAT_WORD19 32
#define MSK32WOL_MAGIC_PAT_WORD19 0xFFFFFFFF
#define RA_WOL_MAGIC_PAT20 0x005C
#define BA_WOL_MAGIC_PAT_WORD20 0x005C
#define B16WOL_MAGIC_PAT_WORD20 0x005C
#define LSb32WOL_MAGIC_PAT_WORD20 0
#define LSb16WOL_MAGIC_PAT_WORD20 0
#define bWOL_MAGIC_PAT_WORD20 32
#define MSK32WOL_MAGIC_PAT_WORD20 0xFFFFFFFF
#define RA_WOL_MAGIC_PAT21 0x0060
#define BA_WOL_MAGIC_PAT_WORD21 0x0060
#define B16WOL_MAGIC_PAT_WORD21 0x0060
#define LSb32WOL_MAGIC_PAT_WORD21 0
#define LSb16WOL_MAGIC_PAT_WORD21 0
#define bWOL_MAGIC_PAT_WORD21 32
#define MSK32WOL_MAGIC_PAT_WORD21 0xFFFFFFFF
#define RA_WOL_MAGIC_PAT22 0x0064
#define BA_WOL_MAGIC_PAT_WORD22 0x0064
#define B16WOL_MAGIC_PAT_WORD22 0x0064
#define LSb32WOL_MAGIC_PAT_WORD22 0
#define LSb16WOL_MAGIC_PAT_WORD22 0
#define bWOL_MAGIC_PAT_WORD22 32
#define MSK32WOL_MAGIC_PAT_WORD22 0xFFFFFFFF
#define RA_WOL_MAGIC_PAT23 0x0068
#define BA_WOL_MAGIC_PAT_WORD23 0x0068
#define B16WOL_MAGIC_PAT_WORD23 0x0068
#define LSb32WOL_MAGIC_PAT_WORD23 0
#define LSb16WOL_MAGIC_PAT_WORD23 0
#define bWOL_MAGIC_PAT_WORD23 32
#define MSK32WOL_MAGIC_PAT_WORD23 0xFFFFFFFF
#define RA_WOL_MAGIC_PAT24 0x006C
#define BA_WOL_MAGIC_PAT_WORD24 0x006C
#define B16WOL_MAGIC_PAT_WORD24 0x006C
#define LSb32WOL_MAGIC_PAT_WORD24 0
#define LSb16WOL_MAGIC_PAT_WORD24 0
#define bWOL_MAGIC_PAT_WORD24 32
#define MSK32WOL_MAGIC_PAT_WORD24 0xFFFFFFFF
#define RA_WOL_MAGIC_PAT25 0x0070
#define BA_WOL_MAGIC_PAT_WORD25 0x0070
#define B16WOL_MAGIC_PAT_WORD25 0x0070
#define LSb32WOL_MAGIC_PAT_WORD25 0
#define LSb16WOL_MAGIC_PAT_WORD25 0
#define bWOL_MAGIC_PAT_WORD25 16
#define MSK32WOL_MAGIC_PAT_WORD25 0x0000FFFF
///////////////////////////////////////////////////////////
#define RA_WOL_MAGIC_PAT_LEN 0x0074
#define BA_WOL_MAGIC_PAT_LEN_ZERO 0x0074
#define B16WOL_MAGIC_PAT_LEN_ZERO 0x0074
#define LSb32WOL_MAGIC_PAT_LEN_ZERO 0
#define LSb16WOL_MAGIC_PAT_LEN_ZERO 0
#define bWOL_MAGIC_PAT_LEN_ZERO 8
#define MSK32WOL_MAGIC_PAT_LEN_ZERO 0x000000FF
///////////////////////////////////////////////////////////
#define RA_WOL_MC_ADDR_HASH0 0x0078
#define BA_WOL_MC_ADDR_HASH0_LO 0x0078
#define B16WOL_MC_ADDR_HASH0_LO 0x0078
#define LSb32WOL_MC_ADDR_HASH0_LO 0
#define LSb16WOL_MC_ADDR_HASH0_LO 0
#define bWOL_MC_ADDR_HASH0_LO 32
#define MSK32WOL_MC_ADDR_HASH0_LO 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_WOL_MC_ADDR_HASH1 0x007C
#define BA_WOL_MC_ADDR_HASH1_HI 0x007C
#define B16WOL_MC_ADDR_HASH1_HI 0x007C
#define LSb32WOL_MC_ADDR_HASH1_HI 0
#define LSb16WOL_MC_ADDR_HASH1_HI 0
#define bWOL_MC_ADDR_HASH1_HI 32
#define MSK32WOL_MC_ADDR_HASH1_HI 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_WOL_MIN_STORE_LEN 0x0080
#define BA_WOL_MIN_STORE_LEN_BYTES 0x0080
#define B16WOL_MIN_STORE_LEN_BYTES 0x0080
#define LSb32WOL_MIN_STORE_LEN_BYTES 0
#define LSb16WOL_MIN_STORE_LEN_BYTES 0
#define bWOL_MIN_STORE_LEN_BYTES 16
#define MSK32WOL_MIN_STORE_LEN_BYTES 0x0000FFFF
///////////////////////////////////////////////////////////
#define RA_WOL_UP_STORE_LEN 0x0084
#define BA_WOL_UP_STORE_LEN_BYTES 0x0084
#define B16WOL_UP_STORE_LEN_BYTES 0x0084
#define LSb32WOL_UP_STORE_LEN_BYTES 0
#define LSb16WOL_UP_STORE_LEN_BYTES 0
#define bWOL_UP_STORE_LEN_BYTES 16
#define MSK32WOL_UP_STORE_LEN_BYTES 0x0000FFFF
///////////////////////////////////////////////////////////
#define RA_WOL_PAT_LEN0_3 0x0088
#define BA_WOL_PAT_LEN0_3_ZERO 0x0088
#define B16WOL_PAT_LEN0_3_ZERO 0x0088
#define LSb32WOL_PAT_LEN0_3_ZERO 0
#define LSb16WOL_PAT_LEN0_3_ZERO 0
#define bWOL_PAT_LEN0_3_ZERO 8
#define MSK32WOL_PAT_LEN0_3_ZERO 0x000000FF
#define BA_WOL_PAT_LEN0_3_ONE 0x0089
#define B16WOL_PAT_LEN0_3_ONE 0x0088
#define LSb32WOL_PAT_LEN0_3_ONE 8
#define LSb16WOL_PAT_LEN0_3_ONE 8
#define bWOL_PAT_LEN0_3_ONE 8
#define MSK32WOL_PAT_LEN0_3_ONE 0x0000FF00
#define BA_WOL_PAT_LEN0_3_TWO 0x008A
#define B16WOL_PAT_LEN0_3_TWO 0x008A
#define LSb32WOL_PAT_LEN0_3_TWO 16
#define LSb16WOL_PAT_LEN0_3_TWO 0
#define bWOL_PAT_LEN0_3_TWO 8
#define MSK32WOL_PAT_LEN0_3_TWO 0x00FF0000
#define BA_WOL_PAT_LEN0_3_THREE 0x008B
#define B16WOL_PAT_LEN0_3_THREE 0x008A
#define LSb32WOL_PAT_LEN0_3_THREE 24
#define LSb16WOL_PAT_LEN0_3_THREE 8
#define bWOL_PAT_LEN0_3_THREE 8
#define MSK32WOL_PAT_LEN0_3_THREE 0xFF000000
///////////////////////////////////////////////////////////
#define RA_WOL_PAT_LEN4_7 0x008C
#define BA_WOL_PAT_LEN4_7_FOUR 0x008C
#define B16WOL_PAT_LEN4_7_FOUR 0x008C
#define LSb32WOL_PAT_LEN4_7_FOUR 0
#define LSb16WOL_PAT_LEN4_7_FOUR 0
#define bWOL_PAT_LEN4_7_FOUR 8
#define MSK32WOL_PAT_LEN4_7_FOUR 0x000000FF
#define BA_WOL_PAT_LEN4_7_FIVE 0x008D
#define B16WOL_PAT_LEN4_7_FIVE 0x008C
#define LSb32WOL_PAT_LEN4_7_FIVE 8
#define LSb16WOL_PAT_LEN4_7_FIVE 8
#define bWOL_PAT_LEN4_7_FIVE 8
#define MSK32WOL_PAT_LEN4_7_FIVE 0x0000FF00
#define BA_WOL_PAT_LEN4_7_SIX 0x008E
#define B16WOL_PAT_LEN4_7_SIX 0x008E
#define LSb32WOL_PAT_LEN4_7_SIX 16
#define LSb16WOL_PAT_LEN4_7_SIX 0
#define bWOL_PAT_LEN4_7_SIX 8
#define MSK32WOL_PAT_LEN4_7_SIX 0x00FF0000
#define BA_WOL_PAT_LEN4_7_SEVEN 0x008F
#define B16WOL_PAT_LEN4_7_SEVEN 0x008E
#define LSb32WOL_PAT_LEN4_7_SEVEN 24
#define LSb16WOL_PAT_LEN4_7_SEVEN 8
#define bWOL_PAT_LEN4_7_SEVEN 8
#define MSK32WOL_PAT_LEN4_7_SEVEN 0xFF000000
///////////////////////////////////////////////////////////
#define RA_WOL_RAM_CTRL 0x0090
#define BA_WOL_RAM_CTRL_CMD 0x0090
#define B16WOL_RAM_CTRL_CMD 0x0090
#define LSb32WOL_RAM_CTRL_CMD 0
#define LSb16WOL_RAM_CTRL_CMD 0
#define bWOL_RAM_CTRL_CMD 8
#define MSK32WOL_RAM_CTRL_CMD 0x000000FF
#define WOL_RAM_CTRL_CMD_WRITE 0x1
#define WOL_RAM_CTRL_CMD_READ 0x2
#define BA_WOL_RAM_CTRL_BYTE_NO 0x0091
#define B16WOL_RAM_CTRL_BYTE_NO 0x0090
#define LSb32WOL_RAM_CTRL_BYTE_NO 8
#define LSb16WOL_RAM_CTRL_BYTE_NO 8
#define bWOL_RAM_CTRL_BYTE_NO 8
#define MSK32WOL_RAM_CTRL_BYTE_NO 0x0000FF00
///////////////////////////////////////////////////////////
#define RA_WOL_RAM_DATA_0 0x0094
#define BA_WOL_RAM_DATA_0_BYTE_PAT_3_0 0x0094
#define B16WOL_RAM_DATA_0_BYTE_PAT_3_0 0x0094
#define LSb32WOL_RAM_DATA_0_BYTE_PAT_3_0 0
#define LSb16WOL_RAM_DATA_0_BYTE_PAT_3_0 0
#define bWOL_RAM_DATA_0_BYTE_PAT_3_0 32
#define MSK32WOL_RAM_DATA_0_BYTE_PAT_3_0 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_WOL_RAM_DATA_1 0x0098
#define BA_WOL_RAM_DATA_1_BYTE_PAT_7_4 0x0098
#define B16WOL_RAM_DATA_1_BYTE_PAT_7_4 0x0098
#define LSb32WOL_RAM_DATA_1_BYTE_PAT_7_4 0
#define LSb16WOL_RAM_DATA_1_BYTE_PAT_7_4 0
#define bWOL_RAM_DATA_1_BYTE_PAT_7_4 32
#define MSK32WOL_RAM_DATA_1_BYTE_PAT_7_4 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_WOL_RAM_DATA_2 0x009C
#define BA_WOL_RAM_DATA_2_BYTE_PAT_8 0x009C
#define B16WOL_RAM_DATA_2_BYTE_PAT_8 0x009C
#define LSb32WOL_RAM_DATA_2_BYTE_PAT_8 0
#define LSb16WOL_RAM_DATA_2_BYTE_PAT_8 0
#define bWOL_RAM_DATA_2_BYTE_PAT_8 8
#define MSK32WOL_RAM_DATA_2_BYTE_PAT_8 0x000000FF
///////////////////////////////////////////////////////////
#define RA_WOL_RCV_MAC_ADDR_LO 0x00A0
#define BA_WOL_RCV_MAC_ADDR_LO_DWORD 0x00A0
#define B16WOL_RCV_MAC_ADDR_LO_DWORD 0x00A0
#define LSb32WOL_RCV_MAC_ADDR_LO_DWORD 0
#define LSb16WOL_RCV_MAC_ADDR_LO_DWORD 0
#define bWOL_RCV_MAC_ADDR_LO_DWORD 32
#define MSK32WOL_RCV_MAC_ADDR_LO_DWORD 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_WOL_RCV_MAC_ADDR_HI 0x00A4
#define BA_WOL_RCV_MAC_ADDR_HI_WORD 0x00A4
#define B16WOL_RCV_MAC_ADDR_HI_WORD 0x00A4
#define LSb32WOL_RCV_MAC_ADDR_HI_WORD 0
#define LSb16WOL_RCV_MAC_ADDR_HI_WORD 0
#define bWOL_RCV_MAC_ADDR_HI_WORD 16
#define MSK32WOL_RCV_MAC_ADDR_HI_WORD 0x0000FFFF
///////////////////////////////////////////////////////////
#define RA_WOL_INT_STATUS 0x00A8
#define BA_WOL_INT_STATUS_PKT_STORE 0x00A8
#define B16WOL_INT_STATUS_PKT_STORE 0x00A8
#define LSb32WOL_INT_STATUS_PKT_STORE 0
#define LSb16WOL_INT_STATUS_PKT_STORE 0
#define bWOL_INT_STATUS_PKT_STORE 1
#define MSK32WOL_INT_STATUS_PKT_STORE 0x00000001
#define BA_WOL_INT_STATUS_LINK_DOWN 0x00A8
#define B16WOL_INT_STATUS_LINK_DOWN 0x00A8
#define LSb32WOL_INT_STATUS_LINK_DOWN 1
#define LSb16WOL_INT_STATUS_LINK_DOWN 1
#define bWOL_INT_STATUS_LINK_DOWN 1
#define MSK32WOL_INT_STATUS_LINK_DOWN 0x00000002
#define BA_WOL_INT_STATUS_LINK_UP 0x00A8
#define B16WOL_INT_STATUS_LINK_UP 0x00A8
#define LSb32WOL_INT_STATUS_LINK_UP 2
#define LSb16WOL_INT_STATUS_LINK_UP 2
#define bWOL_INT_STATUS_LINK_UP 1
#define MSK32WOL_INT_STATUS_LINK_UP 0x00000004
#define BA_WOL_INT_STATUS_MAGIC_PATTERN 0x00A8
#define B16WOL_INT_STATUS_MAGIC_PATTERN 0x00A8
#define LSb32WOL_INT_STATUS_MAGIC_PATTERN 3
#define LSb16WOL_INT_STATUS_MAGIC_PATTERN 3
#define bWOL_INT_STATUS_MAGIC_PATTERN 1
#define MSK32WOL_INT_STATUS_MAGIC_PATTERN 0x00000008
#define BA_WOL_INT_STATUS_WAKE_UP_PAT0 0x00A8
#define B16WOL_INT_STATUS_WAKE_UP_PAT0 0x00A8
#define LSb32WOL_INT_STATUS_WAKE_UP_PAT0 4
#define LSb16WOL_INT_STATUS_WAKE_UP_PAT0 4
#define bWOL_INT_STATUS_WAKE_UP_PAT0 1
#define MSK32WOL_INT_STATUS_WAKE_UP_PAT0 0x00000010
#define BA_WOL_INT_STATUS_WAKE_UP_PAT1 0x00A8
#define B16WOL_INT_STATUS_WAKE_UP_PAT1 0x00A8
#define LSb32WOL_INT_STATUS_WAKE_UP_PAT1 5
#define LSb16WOL_INT_STATUS_WAKE_UP_PAT1 5
#define bWOL_INT_STATUS_WAKE_UP_PAT1 1
#define MSK32WOL_INT_STATUS_WAKE_UP_PAT1 0x00000020
#define BA_WOL_INT_STATUS_WAKE_UP_PAT2 0x00A8
#define B16WOL_INT_STATUS_WAKE_UP_PAT2 0x00A8
#define LSb32WOL_INT_STATUS_WAKE_UP_PAT2 6
#define LSb16WOL_INT_STATUS_WAKE_UP_PAT2 6
#define bWOL_INT_STATUS_WAKE_UP_PAT2 1
#define MSK32WOL_INT_STATUS_WAKE_UP_PAT2 0x00000040
#define BA_WOL_INT_STATUS_WAKE_UP_PAT3 0x00A8
#define B16WOL_INT_STATUS_WAKE_UP_PAT3 0x00A8
#define LSb32WOL_INT_STATUS_WAKE_UP_PAT3 7
#define LSb16WOL_INT_STATUS_WAKE_UP_PAT3 7
#define bWOL_INT_STATUS_WAKE_UP_PAT3 1
#define MSK32WOL_INT_STATUS_WAKE_UP_PAT3 0x00000080
#define BA_WOL_INT_STATUS_WAKE_UP_PAT4 0x00A9
#define B16WOL_INT_STATUS_WAKE_UP_PAT4 0x00A8
#define LSb32WOL_INT_STATUS_WAKE_UP_PAT4 8
#define LSb16WOL_INT_STATUS_WAKE_UP_PAT4 8
#define bWOL_INT_STATUS_WAKE_UP_PAT4 1
#define MSK32WOL_INT_STATUS_WAKE_UP_PAT4 0x00000100
#define BA_WOL_INT_STATUS_WAKE_UP_PAT5 0x00A9
#define B16WOL_INT_STATUS_WAKE_UP_PAT5 0x00A8
#define LSb32WOL_INT_STATUS_WAKE_UP_PAT5 9
#define LSb16WOL_INT_STATUS_WAKE_UP_PAT5 9
#define bWOL_INT_STATUS_WAKE_UP_PAT5 1
#define MSK32WOL_INT_STATUS_WAKE_UP_PAT5 0x00000200
#define BA_WOL_INT_STATUS_WAKE_UP_PAT6 0x00A9
#define B16WOL_INT_STATUS_WAKE_UP_PAT6 0x00A8
#define LSb32WOL_INT_STATUS_WAKE_UP_PAT6 10
#define LSb16WOL_INT_STATUS_WAKE_UP_PAT6 10
#define bWOL_INT_STATUS_WAKE_UP_PAT6 1
#define MSK32WOL_INT_STATUS_WAKE_UP_PAT6 0x00000400
#define BA_WOL_INT_STATUS_WAKE_UP_PAT7 0x00A9
#define B16WOL_INT_STATUS_WAKE_UP_PAT7 0x00A8
#define LSb32WOL_INT_STATUS_WAKE_UP_PAT7 11
#define LSb16WOL_INT_STATUS_WAKE_UP_PAT7 11
#define bWOL_INT_STATUS_WAKE_UP_PAT7 1
#define MSK32WOL_INT_STATUS_WAKE_UP_PAT7 0x00000800
///////////////////////////////////////////////////////////
#define RA_WOL_INT_MASK 0x00AC
#define BA_WOL_INT_MASK_PKT_STORE 0x00AC
#define B16WOL_INT_MASK_PKT_STORE 0x00AC
#define LSb32WOL_INT_MASK_PKT_STORE 0
#define LSb16WOL_INT_MASK_PKT_STORE 0
#define bWOL_INT_MASK_PKT_STORE 1
#define MSK32WOL_INT_MASK_PKT_STORE 0x00000001
#define BA_WOL_INT_MASK_LINK_DOWN 0x00AC
#define B16WOL_INT_MASK_LINK_DOWN 0x00AC
#define LSb32WOL_INT_MASK_LINK_DOWN 1
#define LSb16WOL_INT_MASK_LINK_DOWN 1
#define bWOL_INT_MASK_LINK_DOWN 1
#define MSK32WOL_INT_MASK_LINK_DOWN 0x00000002
#define BA_WOL_INT_MASK_LINK_UP 0x00AC
#define B16WOL_INT_MASK_LINK_UP 0x00AC
#define LSb32WOL_INT_MASK_LINK_UP 2
#define LSb16WOL_INT_MASK_LINK_UP 2
#define bWOL_INT_MASK_LINK_UP 1
#define MSK32WOL_INT_MASK_LINK_UP 0x00000004
#define BA_WOL_INT_MASK_MAGIC_PATTERN 0x00AC
#define B16WOL_INT_MASK_MAGIC_PATTERN 0x00AC
#define LSb32WOL_INT_MASK_MAGIC_PATTERN 3
#define LSb16WOL_INT_MASK_MAGIC_PATTERN 3
#define bWOL_INT_MASK_MAGIC_PATTERN 1
#define MSK32WOL_INT_MASK_MAGIC_PATTERN 0x00000008
#define BA_WOL_INT_MASK_WAKE_UP_PAT0 0x00AC
#define B16WOL_INT_MASK_WAKE_UP_PAT0 0x00AC
#define LSb32WOL_INT_MASK_WAKE_UP_PAT0 4
#define LSb16WOL_INT_MASK_WAKE_UP_PAT0 4
#define bWOL_INT_MASK_WAKE_UP_PAT0 1
#define MSK32WOL_INT_MASK_WAKE_UP_PAT0 0x00000010
#define BA_WOL_INT_MASK_WAKE_UP_PAT1 0x00AC
#define B16WOL_INT_MASK_WAKE_UP_PAT1 0x00AC
#define LSb32WOL_INT_MASK_WAKE_UP_PAT1 5
#define LSb16WOL_INT_MASK_WAKE_UP_PAT1 5
#define bWOL_INT_MASK_WAKE_UP_PAT1 1
#define MSK32WOL_INT_MASK_WAKE_UP_PAT1 0x00000020
#define BA_WOL_INT_MASK_WAKE_UP_PAT2 0x00AC
#define B16WOL_INT_MASK_WAKE_UP_PAT2 0x00AC
#define LSb32WOL_INT_MASK_WAKE_UP_PAT2 6
#define LSb16WOL_INT_MASK_WAKE_UP_PAT2 6
#define bWOL_INT_MASK_WAKE_UP_PAT2 1
#define MSK32WOL_INT_MASK_WAKE_UP_PAT2 0x00000040
#define BA_WOL_INT_MASK_WAKE_UP_PAT3 0x00AC
#define B16WOL_INT_MASK_WAKE_UP_PAT3 0x00AC
#define LSb32WOL_INT_MASK_WAKE_UP_PAT3 7
#define LSb16WOL_INT_MASK_WAKE_UP_PAT3 7
#define bWOL_INT_MASK_WAKE_UP_PAT3 1
#define MSK32WOL_INT_MASK_WAKE_UP_PAT3 0x00000080
#define BA_WOL_INT_MASK_WAKE_UP_PAT4 0x00AD
#define B16WOL_INT_MASK_WAKE_UP_PAT4 0x00AC
#define LSb32WOL_INT_MASK_WAKE_UP_PAT4 8
#define LSb16WOL_INT_MASK_WAKE_UP_PAT4 8
#define bWOL_INT_MASK_WAKE_UP_PAT4 1
#define MSK32WOL_INT_MASK_WAKE_UP_PAT4 0x00000100
#define BA_WOL_INT_MASK_WAKE_UP_PAT5 0x00AD
#define B16WOL_INT_MASK_WAKE_UP_PAT5 0x00AC
#define LSb32WOL_INT_MASK_WAKE_UP_PAT5 9
#define LSb16WOL_INT_MASK_WAKE_UP_PAT5 9
#define bWOL_INT_MASK_WAKE_UP_PAT5 1
#define MSK32WOL_INT_MASK_WAKE_UP_PAT5 0x00000200
#define BA_WOL_INT_MASK_WAKE_UP_PAT6 0x00AD
#define B16WOL_INT_MASK_WAKE_UP_PAT6 0x00AC
#define LSb32WOL_INT_MASK_WAKE_UP_PAT6 10
#define LSb16WOL_INT_MASK_WAKE_UP_PAT6 10
#define bWOL_INT_MASK_WAKE_UP_PAT6 1
#define MSK32WOL_INT_MASK_WAKE_UP_PAT6 0x00000400
#define BA_WOL_INT_MASK_WAKE_UP_PAT7 0x00AD
#define B16WOL_INT_MASK_WAKE_UP_PAT7 0x00AC
#define LSb32WOL_INT_MASK_WAKE_UP_PAT7 11
#define LSb16WOL_INT_MASK_WAKE_UP_PAT7 11
#define bWOL_INT_MASK_WAKE_UP_PAT7 1
#define MSK32WOL_INT_MASK_WAKE_UP_PAT7 0x00000800
///////////////////////////////////////////////////////////
#define RA_WOL_FEPHY_CTRL 0x00B0
#define BA_WOL_FEPHY_CTRL_ext_pwrdn_a 0x00B0
#define B16WOL_FEPHY_CTRL_ext_pwrdn_a 0x00B0
#define LSb32WOL_FEPHY_CTRL_ext_pwrdn_a 0
#define LSb16WOL_FEPHY_CTRL_ext_pwrdn_a 0
#define bWOL_FEPHY_CTRL_ext_pwrdn_a 5
#define MSK32WOL_FEPHY_CTRL_ext_pwrdn_a 0x0000001F
#define BA_WOL_FEPHY_CTRL_pd_aneg_mode_a 0x00B0
#define B16WOL_FEPHY_CTRL_pd_aneg_mode_a 0x00B0
#define LSb32WOL_FEPHY_CTRL_pd_aneg_mode_a 5
#define LSb16WOL_FEPHY_CTRL_pd_aneg_mode_a 5
#define bWOL_FEPHY_CTRL_pd_aneg_mode_a 3
#define MSK32WOL_FEPHY_CTRL_pd_aneg_mode_a 0x000000E0
#define BA_WOL_FEPHY_CTRL_pd_phyadr_a 0x00B1
#define B16WOL_FEPHY_CTRL_pd_phyadr_a 0x00B0
#define LSb32WOL_FEPHY_CTRL_pd_phyadr_a 8
#define LSb16WOL_FEPHY_CTRL_pd_phyadr_a 8
#define bWOL_FEPHY_CTRL_pd_phyadr_a 5
#define MSK32WOL_FEPHY_CTRL_pd_phyadr_a 0x00001F00
#define BA_WOL_FEPHY_CTRL_pd_led_config_a 0x00B1
#define B16WOL_FEPHY_CTRL_pd_led_config_a 0x00B0
#define LSb32WOL_FEPHY_CTRL_pd_led_config_a 13
#define LSb16WOL_FEPHY_CTRL_pd_led_config_a 13
#define bWOL_FEPHY_CTRL_pd_led_config_a 3
#define MSK32WOL_FEPHY_CTRL_pd_led_config_a 0x0000E000
#define BA_WOL_FEPHY_CTRL_yy_pecl_sdet_a 0x00B2
#define B16WOL_FEPHY_CTRL_yy_pecl_sdet_a 0x00B2
#define LSb32WOL_FEPHY_CTRL_yy_pecl_sdet_a 16
#define LSb16WOL_FEPHY_CTRL_yy_pecl_sdet_a 0
#define bWOL_FEPHY_CTRL_yy_pecl_sdet_a 5
#define MSK32WOL_FEPHY_CTRL_yy_pecl_sdet_a 0x001F0000
#define BA_WOL_FEPHY_CTRL_ps_en_eee10t_s 0x00B2
#define B16WOL_FEPHY_CTRL_ps_en_eee10t_s 0x00B2
#define LSb32WOL_FEPHY_CTRL_ps_en_eee10t_s 21
#define LSb16WOL_FEPHY_CTRL_ps_en_eee10t_s 5
#define bWOL_FEPHY_CTRL_ps_en_eee10t_s 1
#define MSK32WOL_FEPHY_CTRL_ps_en_eee10t_s 0x00200000
#define BA_WOL_FEPHY_CTRL_ps_en_eee100t_s 0x00B2
#define B16WOL_FEPHY_CTRL_ps_en_eee100t_s 0x00B2
#define LSb32WOL_FEPHY_CTRL_ps_en_eee100t_s 22
#define LSb16WOL_FEPHY_CTRL_ps_en_eee100t_s 6
#define bWOL_FEPHY_CTRL_ps_en_eee100t_s 1
#define MSK32WOL_FEPHY_CTRL_ps_en_eee100t_s 0x00400000
#define BA_WOL_FEPHY_CTRL_pd_burnin_a 0x00B2
#define B16WOL_FEPHY_CTRL_pd_burnin_a 0x00B2
#define LSb32WOL_FEPHY_CTRL_pd_burnin_a 23
#define LSb16WOL_FEPHY_CTRL_pd_burnin_a 7
#define bWOL_FEPHY_CTRL_pd_burnin_a 1
#define MSK32WOL_FEPHY_CTRL_pd_burnin_a 0x00800000
#define BA_WOL_FEPHY_CTRL_pd_ena_edet_a 0x00B3
#define B16WOL_FEPHY_CTRL_pd_ena_edet_a 0x00B2
#define LSb32WOL_FEPHY_CTRL_pd_ena_edet_a 24
#define LSb16WOL_FEPHY_CTRL_pd_ena_edet_a 8
#define bWOL_FEPHY_CTRL_pd_ena_edet_a 1
#define MSK32WOL_FEPHY_CTRL_pd_ena_edet_a 0x01000000
#define BA_WOL_FEPHY_CTRL_pd_ena_xc_a 0x00B3
#define B16WOL_FEPHY_CTRL_pd_ena_xc_a 0x00B2
#define LSb32WOL_FEPHY_CTRL_pd_ena_xc_a 25
#define LSb16WOL_FEPHY_CTRL_pd_ena_xc_a 9
#define bWOL_FEPHY_CTRL_pd_ena_xc_a 1
#define MSK32WOL_FEPHY_CTRL_pd_ena_xc_a 0x02000000
///////////////////////////////////////////////////////////
#define RA_WOL_FEPHY_STS 0x00B4
#define BA_WOL_FEPHY_STS_misc_speed_s 0x00B4
#define B16WOL_FEPHY_STS_misc_speed_s 0x00B4
#define LSb32WOL_FEPHY_STS_misc_speed_s 0
#define LSb16WOL_FEPHY_STS_misc_speed_s 0
#define bWOL_FEPHY_STS_misc_speed_s 1
#define MSK32WOL_FEPHY_STS_misc_speed_s 0x00000001
#define BA_WOL_FEPHY_STS_misc_duplex_s 0x00B4
#define B16WOL_FEPHY_STS_misc_duplex_s 0x00B4
#define LSb32WOL_FEPHY_STS_misc_duplex_s 1
#define LSb16WOL_FEPHY_STS_misc_duplex_s 1
#define bWOL_FEPHY_STS_misc_duplex_s 1
#define MSK32WOL_FEPHY_STS_misc_duplex_s 0x00000002
#define BA_WOL_FEPHY_STS_misc_hcd_resolved_s 0x00B4
#define B16WOL_FEPHY_STS_misc_hcd_resolved_s 0x00B4
#define LSb32WOL_FEPHY_STS_misc_hcd_resolved_s 2
#define LSb16WOL_FEPHY_STS_misc_hcd_resolved_s 2
#define bWOL_FEPHY_STS_misc_hcd_resolved_s 1
#define MSK32WOL_FEPHY_STS_misc_hcd_resolved_s 0x00000004
#define BA_WOL_FEPHY_STS_misc_link_s 0x00B4
#define B16WOL_FEPHY_STS_misc_link_s 0x00B4
#define LSb32WOL_FEPHY_STS_misc_link_s 3
#define LSb16WOL_FEPHY_STS_misc_link_s 3
#define bWOL_FEPHY_STS_misc_link_s 1
#define MSK32WOL_FEPHY_STS_misc_link_s 0x00000008
#define BA_WOL_FEPHY_STS_misc_lpi_s 0x00B4
#define B16WOL_FEPHY_STS_misc_lpi_s 0x00B4
#define LSb32WOL_FEPHY_STS_misc_lpi_s 4
#define LSb16WOL_FEPHY_STS_misc_lpi_s 4
#define bWOL_FEPHY_STS_misc_lpi_s 1
#define MSK32WOL_FEPHY_STS_misc_lpi_s 0x00000010
#define BA_WOL_FEPHY_STS_misc_rx_lpi_s 0x00B4
#define B16WOL_FEPHY_STS_misc_rx_lpi_s 0x00B4
#define LSb32WOL_FEPHY_STS_misc_rx_lpi_s 5
#define LSb16WOL_FEPHY_STS_misc_rx_lpi_s 5
#define bWOL_FEPHY_STS_misc_rx_lpi_s 1
#define MSK32WOL_FEPHY_STS_misc_rx_lpi_s 0x00000020
#define BA_WOL_FEPHY_STS_misc_pause_s 0x00B4
#define B16WOL_FEPHY_STS_misc_pause_s 0x00B4
#define LSb32WOL_FEPHY_STS_misc_pause_s 6
#define LSb16WOL_FEPHY_STS_misc_pause_s 6
#define bWOL_FEPHY_STS_misc_pause_s 1
#define MSK32WOL_FEPHY_STS_misc_pause_s 0x00000040
#define BA_WOL_FEPHY_STS_misc_lp_pause_s 0x00B4
#define B16WOL_FEPHY_STS_misc_lp_pause_s 0x00B4
#define LSb32WOL_FEPHY_STS_misc_lp_pause_s 7
#define LSb16WOL_FEPHY_STS_misc_lp_pause_s 7
#define bWOL_FEPHY_STS_misc_lp_pause_s 1
#define MSK32WOL_FEPHY_STS_misc_lp_pause_s 0x00000080
#define BA_WOL_FEPHY_STS_misc_int_s 0x00B5
#define B16WOL_FEPHY_STS_misc_int_s 0x00B4
#define LSb32WOL_FEPHY_STS_misc_int_s 8
#define LSb16WOL_FEPHY_STS_misc_int_s 8
#define bWOL_FEPHY_STS_misc_int_s 1
#define MSK32WOL_FEPHY_STS_misc_int_s 0x00000100
#define BA_WOL_FEPHY_STS_misc_edet_status_s 0x00B5
#define B16WOL_FEPHY_STS_misc_edet_status_s 0x00B4
#define LSb32WOL_FEPHY_STS_misc_edet_status_s 9
#define LSb16WOL_FEPHY_STS_misc_edet_status_s 9
#define bWOL_FEPHY_STS_misc_edet_status_s 1
#define MSK32WOL_FEPHY_STS_misc_edet_status_s 0x00000200
#define BA_WOL_FEPHY_STS_tx_latency_mark_a 0x00B5
#define B16WOL_FEPHY_STS_tx_latency_mark_a 0x00B4
#define LSb32WOL_FEPHY_STS_tx_latency_mark_a 10
#define LSb16WOL_FEPHY_STS_tx_latency_mark_a 10
#define bWOL_FEPHY_STS_tx_latency_mark_a 1
#define MSK32WOL_FEPHY_STS_tx_latency_mark_a 0x00000400
#define BA_WOL_FEPHY_STS_misc_por_reset 0x00B5
#define B16WOL_FEPHY_STS_misc_por_reset 0x00B4
#define LSb32WOL_FEPHY_STS_misc_por_reset 11
#define LSb16WOL_FEPHY_STS_misc_por_reset 11
#define bWOL_FEPHY_STS_misc_por_reset 1
#define MSK32WOL_FEPHY_STS_misc_por_reset 0x00000800
///////////////////////////////////////////////////////////
typedef struct SIE_WOL {
///////////////////////////////////////////////////////////
#define GET32WOL_CTRL_WOL_MODE(r32) _BFGET_(r32, 1, 0)
#define SET32WOL_CTRL_WOL_MODE(r32,v) _BFSET_(r32, 1, 0,v)
#define GET16WOL_CTRL_WOL_MODE(r16) _BFGET_(r16, 1, 0)
#define SET16WOL_CTRL_WOL_MODE(r16,v) _BFSET_(r16, 1, 0,v)
#define GET32WOL_CTRL_RAM_LOAD(r32) _BFGET_(r32, 2, 2)
#define SET32WOL_CTRL_RAM_LOAD(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16WOL_CTRL_RAM_LOAD(r16) _BFGET_(r16, 2, 2)
#define SET16WOL_CTRL_RAM_LOAD(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32WOL_CTRL_LU_EN(r32) _BFGET_(r32, 3, 3)
#define SET32WOL_CTRL_LU_EN(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16WOL_CTRL_LU_EN(r16) _BFGET_(r16, 3, 3)
#define SET16WOL_CTRL_LU_EN(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32WOL_CTRL_MP_CMP_EN(r32) _BFGET_(r32, 4, 4)
#define SET32WOL_CTRL_MP_CMP_EN(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16WOL_CTRL_MP_CMP_EN(r16) _BFGET_(r16, 4, 4)
#define SET16WOL_CTRL_MP_CMP_EN(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32WOL_CTRL_MP_DA_FILT(r32) _BFGET_(r32, 6, 5)
#define SET32WOL_CTRL_MP_DA_FILT(r32,v) _BFSET_(r32, 6, 5,v)
#define GET16WOL_CTRL_MP_DA_FILT(r16) _BFGET_(r16, 6, 5)
#define SET16WOL_CTRL_MP_DA_FILT(r16,v) _BFSET_(r16, 6, 5,v)
#define GET32WOL_CTRL_WU_PAT0_CMP_EN(r32) _BFGET_(r32, 7, 7)
#define SET32WOL_CTRL_WU_PAT0_CMP_EN(r32,v) _BFSET_(r32, 7, 7,v)
#define GET16WOL_CTRL_WU_PAT0_CMP_EN(r16) _BFGET_(r16, 7, 7)
#define SET16WOL_CTRL_WU_PAT0_CMP_EN(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32WOL_CTRL_WU_PAT0_DA_FILT(r32) _BFGET_(r32, 9, 8)
#define SET32WOL_CTRL_WU_PAT0_DA_FILT(r32,v) _BFSET_(r32, 9, 8,v)
#define GET16WOL_CTRL_WU_PAT0_DA_FILT(r16) _BFGET_(r16, 9, 8)
#define SET16WOL_CTRL_WU_PAT0_DA_FILT(r16,v) _BFSET_(r16, 9, 8,v)
#define GET32WOL_CTRL_WU_PAT1_CMP_EN(r32) _BFGET_(r32,10,10)
#define SET32WOL_CTRL_WU_PAT1_CMP_EN(r32,v) _BFSET_(r32,10,10,v)
#define GET16WOL_CTRL_WU_PAT1_CMP_EN(r16) _BFGET_(r16,10,10)
#define SET16WOL_CTRL_WU_PAT1_CMP_EN(r16,v) _BFSET_(r16,10,10,v)
#define GET32WOL_CTRL_WU_PAT1_DA_FILT(r32) _BFGET_(r32,12,11)
#define SET32WOL_CTRL_WU_PAT1_DA_FILT(r32,v) _BFSET_(r32,12,11,v)
#define GET16WOL_CTRL_WU_PAT1_DA_FILT(r16) _BFGET_(r16,12,11)
#define SET16WOL_CTRL_WU_PAT1_DA_FILT(r16,v) _BFSET_(r16,12,11,v)
#define GET32WOL_CTRL_WU_PAT2_CMP_EN(r32) _BFGET_(r32,13,13)
#define SET32WOL_CTRL_WU_PAT2_CMP_EN(r32,v) _BFSET_(r32,13,13,v)
#define GET16WOL_CTRL_WU_PAT2_CMP_EN(r16) _BFGET_(r16,13,13)
#define SET16WOL_CTRL_WU_PAT2_CMP_EN(r16,v) _BFSET_(r16,13,13,v)
#define GET32WOL_CTRL_WU_PAT2_DA_FILT(r32) _BFGET_(r32,15,14)
#define SET32WOL_CTRL_WU_PAT2_DA_FILT(r32,v) _BFSET_(r32,15,14,v)
#define GET16WOL_CTRL_WU_PAT2_DA_FILT(r16) _BFGET_(r16,15,14)
#define SET16WOL_CTRL_WU_PAT2_DA_FILT(r16,v) _BFSET_(r16,15,14,v)
#define GET32WOL_CTRL_WU_PAT3_CMP_EN(r32) _BFGET_(r32,16,16)
#define SET32WOL_CTRL_WU_PAT3_CMP_EN(r32,v) _BFSET_(r32,16,16,v)
#define GET16WOL_CTRL_WU_PAT3_CMP_EN(r16) _BFGET_(r16, 0, 0)
#define SET16WOL_CTRL_WU_PAT3_CMP_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32WOL_CTRL_WU_PAT3_DA_FILT(r32) _BFGET_(r32,18,17)
#define SET32WOL_CTRL_WU_PAT3_DA_FILT(r32,v) _BFSET_(r32,18,17,v)
#define GET16WOL_CTRL_WU_PAT3_DA_FILT(r16) _BFGET_(r16, 2, 1)
#define SET16WOL_CTRL_WU_PAT3_DA_FILT(r16,v) _BFSET_(r16, 2, 1,v)
#define GET32WOL_CTRL_WU_PAT4_CMP_EN(r32) _BFGET_(r32,19,19)
#define SET32WOL_CTRL_WU_PAT4_CMP_EN(r32,v) _BFSET_(r32,19,19,v)
#define GET16WOL_CTRL_WU_PAT4_CMP_EN(r16) _BFGET_(r16, 3, 3)
#define SET16WOL_CTRL_WU_PAT4_CMP_EN(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32WOL_CTRL_WU_PAT4_DA_FILT(r32) _BFGET_(r32,21,20)
#define SET32WOL_CTRL_WU_PAT4_DA_FILT(r32,v) _BFSET_(r32,21,20,v)
#define GET16WOL_CTRL_WU_PAT4_DA_FILT(r16) _BFGET_(r16, 5, 4)
#define SET16WOL_CTRL_WU_PAT4_DA_FILT(r16,v) _BFSET_(r16, 5, 4,v)
#define GET32WOL_CTRL_WU_PAT5_CMP_EN(r32) _BFGET_(r32,22,22)
#define SET32WOL_CTRL_WU_PAT5_CMP_EN(r32,v) _BFSET_(r32,22,22,v)
#define GET16WOL_CTRL_WU_PAT5_CMP_EN(r16) _BFGET_(r16, 6, 6)
#define SET16WOL_CTRL_WU_PAT5_CMP_EN(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32WOL_CTRL_WU_PAT5_DA_FILT(r32) _BFGET_(r32,24,23)
#define SET32WOL_CTRL_WU_PAT5_DA_FILT(r32,v) _BFSET_(r32,24,23,v)
#define GET16WOL_CTRL_WU_PAT5_DA_FILT(r16) _BFGET_(r16, 8, 7)
#define SET16WOL_CTRL_WU_PAT5_DA_FILT(r16,v) _BFSET_(r16, 8, 7,v)
#define GET32WOL_CTRL_WU_PAT6_CMP_EN(r32) _BFGET_(r32,25,25)
#define SET32WOL_CTRL_WU_PAT6_CMP_EN(r32,v) _BFSET_(r32,25,25,v)
#define GET16WOL_CTRL_WU_PAT6_CMP_EN(r16) _BFGET_(r16, 9, 9)
#define SET16WOL_CTRL_WU_PAT6_CMP_EN(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32WOL_CTRL_WU_PAT6_DA_FILT(r32) _BFGET_(r32,27,26)
#define SET32WOL_CTRL_WU_PAT6_DA_FILT(r32,v) _BFSET_(r32,27,26,v)
#define GET16WOL_CTRL_WU_PAT6_DA_FILT(r16) _BFGET_(r16,11,10)
#define SET16WOL_CTRL_WU_PAT6_DA_FILT(r16,v) _BFSET_(r16,11,10,v)
#define GET32WOL_CTRL_WU_PAT7_CMP_EN(r32) _BFGET_(r32,28,28)
#define SET32WOL_CTRL_WU_PAT7_CMP_EN(r32,v) _BFSET_(r32,28,28,v)
#define GET16WOL_CTRL_WU_PAT7_CMP_EN(r16) _BFGET_(r16,12,12)
#define SET16WOL_CTRL_WU_PAT7_CMP_EN(r16,v) _BFSET_(r16,12,12,v)
#define GET32WOL_CTRL_WU_PAT7_DA_FILT(r32) _BFGET_(r32,30,29)
#define SET32WOL_CTRL_WU_PAT7_DA_FILT(r32,v) _BFSET_(r32,30,29,v)
#define GET16WOL_CTRL_WU_PAT7_DA_FILT(r16) _BFGET_(r16,14,13)
#define SET16WOL_CTRL_WU_PAT7_DA_FILT(r16,v) _BFSET_(r16,14,13,v)
#define GET32WOL_CTRL_CRC_IN_REVERSE(r32) _BFGET_(r32,31,31)
#define SET32WOL_CTRL_CRC_IN_REVERSE(r32,v) _BFSET_(r32,31,31,v)
#define GET16WOL_CTRL_CRC_IN_REVERSE(r16) _BFGET_(r16,15,15)
#define SET16WOL_CTRL_CRC_IN_REVERSE(r16,v) _BFSET_(r16,15,15,v)
#define w32WOL_CTRL {\
UNSG32 uCTRL_WOL_MODE : 2;\
UNSG32 uCTRL_RAM_LOAD : 1;\
UNSG32 uCTRL_LU_EN : 1;\
UNSG32 uCTRL_MP_CMP_EN : 1;\
UNSG32 uCTRL_MP_DA_FILT : 2;\
UNSG32 uCTRL_WU_PAT0_CMP_EN : 1;\
UNSG32 uCTRL_WU_PAT0_DA_FILT : 2;\
UNSG32 uCTRL_WU_PAT1_CMP_EN : 1;\
UNSG32 uCTRL_WU_PAT1_DA_FILT : 2;\
UNSG32 uCTRL_WU_PAT2_CMP_EN : 1;\
UNSG32 uCTRL_WU_PAT2_DA_FILT : 2;\
UNSG32 uCTRL_WU_PAT3_CMP_EN : 1;\
UNSG32 uCTRL_WU_PAT3_DA_FILT : 2;\
UNSG32 uCTRL_WU_PAT4_CMP_EN : 1;\
UNSG32 uCTRL_WU_PAT4_DA_FILT : 2;\
UNSG32 uCTRL_WU_PAT5_CMP_EN : 1;\
UNSG32 uCTRL_WU_PAT5_DA_FILT : 2;\
UNSG32 uCTRL_WU_PAT6_CMP_EN : 1;\
UNSG32 uCTRL_WU_PAT6_DA_FILT : 2;\
UNSG32 uCTRL_WU_PAT7_CMP_EN : 1;\
UNSG32 uCTRL_WU_PAT7_DA_FILT : 2;\
UNSG32 uCTRL_CRC_IN_REVERSE : 1;\
}
union { UNSG32 u32WOL_CTRL;
struct w32WOL_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32WOL_MAC_ADDR_LO_DWORD(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MAC_ADDR_LO_DWORD(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MAC_ADDR_LO {\
UNSG32 uMAC_ADDR_LO_DWORD : 32;\
}
union { UNSG32 u32WOL_MAC_ADDR_LO;
struct w32WOL_MAC_ADDR_LO;
};
///////////////////////////////////////////////////////////
#define GET32WOL_MAC_ADDR_HI_WORD(r32) _BFGET_(r32,15, 0)
#define SET32WOL_MAC_ADDR_HI_WORD(r32,v) _BFSET_(r32,15, 0,v)
#define GET16WOL_MAC_ADDR_HI_WORD(r16) _BFGET_(r16,15, 0)
#define SET16WOL_MAC_ADDR_HI_WORD(r16,v) _BFSET_(r16,15, 0,v)
#define w32WOL_MAC_ADDR_HI {\
UNSG32 uMAC_ADDR_HI_WORD : 16;\
UNSG32 RSVDx8_b16 : 16;\
}
union { UNSG32 u32WOL_MAC_ADDR_HI;
struct w32WOL_MAC_ADDR_HI;
};
///////////////////////////////////////////////////////////
#define GET32WOL_MAGIC_PAT_WORD0(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MAGIC_PAT_WORD0(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MAGIC_PAT {\
UNSG32 uMAGIC_PAT_WORD0 : 32;\
}
union { UNSG32 u32WOL_MAGIC_PAT;
struct w32WOL_MAGIC_PAT;
};
#define GET32WOL_MAGIC_PAT_WORD1(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MAGIC_PAT_WORD1(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MAGIC_PAT1 {\
UNSG32 uMAGIC_PAT_WORD1 : 32;\
}
union { UNSG32 u32WOL_MAGIC_PAT1;
struct w32WOL_MAGIC_PAT1;
};
#define GET32WOL_MAGIC_PAT_WORD2(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MAGIC_PAT_WORD2(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MAGIC_PAT2 {\
UNSG32 uMAGIC_PAT_WORD2 : 32;\
}
union { UNSG32 u32WOL_MAGIC_PAT2;
struct w32WOL_MAGIC_PAT2;
};
#define GET32WOL_MAGIC_PAT_WORD3(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MAGIC_PAT_WORD3(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MAGIC_PAT3 {\
UNSG32 uMAGIC_PAT_WORD3 : 32;\
}
union { UNSG32 u32WOL_MAGIC_PAT3;
struct w32WOL_MAGIC_PAT3;
};
#define GET32WOL_MAGIC_PAT_WORD4(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MAGIC_PAT_WORD4(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MAGIC_PAT4 {\
UNSG32 uMAGIC_PAT_WORD4 : 32;\
}
union { UNSG32 u32WOL_MAGIC_PAT4;
struct w32WOL_MAGIC_PAT4;
};
#define GET32WOL_MAGIC_PAT_WORD5(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MAGIC_PAT_WORD5(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MAGIC_PAT5 {\
UNSG32 uMAGIC_PAT_WORD5 : 32;\
}
union { UNSG32 u32WOL_MAGIC_PAT5;
struct w32WOL_MAGIC_PAT5;
};
#define GET32WOL_MAGIC_PAT_WORD6(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MAGIC_PAT_WORD6(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MAGIC_PAT6 {\
UNSG32 uMAGIC_PAT_WORD6 : 32;\
}
union { UNSG32 u32WOL_MAGIC_PAT6;
struct w32WOL_MAGIC_PAT6;
};
#define GET32WOL_MAGIC_PAT_WORD7(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MAGIC_PAT_WORD7(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MAGIC_PAT7 {\
UNSG32 uMAGIC_PAT_WORD7 : 32;\
}
union { UNSG32 u32WOL_MAGIC_PAT7;
struct w32WOL_MAGIC_PAT7;
};
#define GET32WOL_MAGIC_PAT_WORD8(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MAGIC_PAT_WORD8(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MAGIC_PAT8 {\
UNSG32 uMAGIC_PAT_WORD8 : 32;\
}
union { UNSG32 u32WOL_MAGIC_PAT8;
struct w32WOL_MAGIC_PAT8;
};
#define GET32WOL_MAGIC_PAT_WORD9(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MAGIC_PAT_WORD9(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MAGIC_PAT9 {\
UNSG32 uMAGIC_PAT_WORD9 : 32;\
}
union { UNSG32 u32WOL_MAGIC_PAT9;
struct w32WOL_MAGIC_PAT9;
};
#define GET32WOL_MAGIC_PAT_WORD10(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MAGIC_PAT_WORD10(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MAGIC_PAT10 {\
UNSG32 uMAGIC_PAT_WORD10 : 32;\
}
union { UNSG32 u32WOL_MAGIC_PAT10;
struct w32WOL_MAGIC_PAT10;
};
#define GET32WOL_MAGIC_PAT_WORD11(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MAGIC_PAT_WORD11(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MAGIC_PAT11 {\
UNSG32 uMAGIC_PAT_WORD11 : 32;\
}
union { UNSG32 u32WOL_MAGIC_PAT11;
struct w32WOL_MAGIC_PAT11;
};
#define GET32WOL_MAGIC_PAT_WORD12(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MAGIC_PAT_WORD12(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MAGIC_PAT12 {\
UNSG32 uMAGIC_PAT_WORD12 : 32;\
}
union { UNSG32 u32WOL_MAGIC_PAT12;
struct w32WOL_MAGIC_PAT12;
};
#define GET32WOL_MAGIC_PAT_WORD13(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MAGIC_PAT_WORD13(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MAGIC_PAT13 {\
UNSG32 uMAGIC_PAT_WORD13 : 32;\
}
union { UNSG32 u32WOL_MAGIC_PAT13;
struct w32WOL_MAGIC_PAT13;
};
#define GET32WOL_MAGIC_PAT_WORD14(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MAGIC_PAT_WORD14(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MAGIC_PAT14 {\
UNSG32 uMAGIC_PAT_WORD14 : 32;\
}
union { UNSG32 u32WOL_MAGIC_PAT14;
struct w32WOL_MAGIC_PAT14;
};
#define GET32WOL_MAGIC_PAT_WORD15(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MAGIC_PAT_WORD15(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MAGIC_PAT15 {\
UNSG32 uMAGIC_PAT_WORD15 : 32;\
}
union { UNSG32 u32WOL_MAGIC_PAT15;
struct w32WOL_MAGIC_PAT15;
};
#define GET32WOL_MAGIC_PAT_WORD16(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MAGIC_PAT_WORD16(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MAGIC_PAT16 {\
UNSG32 uMAGIC_PAT_WORD16 : 32;\
}
union { UNSG32 u32WOL_MAGIC_PAT16;
struct w32WOL_MAGIC_PAT16;
};
#define GET32WOL_MAGIC_PAT_WORD17(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MAGIC_PAT_WORD17(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MAGIC_PAT17 {\
UNSG32 uMAGIC_PAT_WORD17 : 32;\
}
union { UNSG32 u32WOL_MAGIC_PAT17;
struct w32WOL_MAGIC_PAT17;
};
#define GET32WOL_MAGIC_PAT_WORD18(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MAGIC_PAT_WORD18(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MAGIC_PAT18 {\
UNSG32 uMAGIC_PAT_WORD18 : 32;\
}
union { UNSG32 u32WOL_MAGIC_PAT18;
struct w32WOL_MAGIC_PAT18;
};
#define GET32WOL_MAGIC_PAT_WORD19(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MAGIC_PAT_WORD19(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MAGIC_PAT19 {\
UNSG32 uMAGIC_PAT_WORD19 : 32;\
}
union { UNSG32 u32WOL_MAGIC_PAT19;
struct w32WOL_MAGIC_PAT19;
};
#define GET32WOL_MAGIC_PAT_WORD20(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MAGIC_PAT_WORD20(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MAGIC_PAT20 {\
UNSG32 uMAGIC_PAT_WORD20 : 32;\
}
union { UNSG32 u32WOL_MAGIC_PAT20;
struct w32WOL_MAGIC_PAT20;
};
#define GET32WOL_MAGIC_PAT_WORD21(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MAGIC_PAT_WORD21(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MAGIC_PAT21 {\
UNSG32 uMAGIC_PAT_WORD21 : 32;\
}
union { UNSG32 u32WOL_MAGIC_PAT21;
struct w32WOL_MAGIC_PAT21;
};
#define GET32WOL_MAGIC_PAT_WORD22(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MAGIC_PAT_WORD22(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MAGIC_PAT22 {\
UNSG32 uMAGIC_PAT_WORD22 : 32;\
}
union { UNSG32 u32WOL_MAGIC_PAT22;
struct w32WOL_MAGIC_PAT22;
};
#define GET32WOL_MAGIC_PAT_WORD23(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MAGIC_PAT_WORD23(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MAGIC_PAT23 {\
UNSG32 uMAGIC_PAT_WORD23 : 32;\
}
union { UNSG32 u32WOL_MAGIC_PAT23;
struct w32WOL_MAGIC_PAT23;
};
#define GET32WOL_MAGIC_PAT_WORD24(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MAGIC_PAT_WORD24(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MAGIC_PAT24 {\
UNSG32 uMAGIC_PAT_WORD24 : 32;\
}
union { UNSG32 u32WOL_MAGIC_PAT24;
struct w32WOL_MAGIC_PAT24;
};
#define GET32WOL_MAGIC_PAT_WORD25(r32) _BFGET_(r32,15, 0)
#define SET32WOL_MAGIC_PAT_WORD25(r32,v) _BFSET_(r32,15, 0,v)
#define GET16WOL_MAGIC_PAT_WORD25(r16) _BFGET_(r16,15, 0)
#define SET16WOL_MAGIC_PAT_WORD25(r16,v) _BFSET_(r16,15, 0,v)
#define w32WOL_MAGIC_PAT25 {\
UNSG32 uMAGIC_PAT_WORD25 : 16;\
UNSG32 RSVDx70_b16 : 16;\
}
union { UNSG32 u32WOL_MAGIC_PAT25;
struct w32WOL_MAGIC_PAT25;
};
///////////////////////////////////////////////////////////
#define GET32WOL_MAGIC_PAT_LEN_ZERO(r32) _BFGET_(r32, 7, 0)
#define SET32WOL_MAGIC_PAT_LEN_ZERO(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16WOL_MAGIC_PAT_LEN_ZERO(r16) _BFGET_(r16, 7, 0)
#define SET16WOL_MAGIC_PAT_LEN_ZERO(r16,v) _BFSET_(r16, 7, 0,v)
#define w32WOL_MAGIC_PAT_LEN {\
UNSG32 uMAGIC_PAT_LEN_ZERO : 8;\
UNSG32 RSVDx74_b8 : 24;\
}
union { UNSG32 u32WOL_MAGIC_PAT_LEN;
struct w32WOL_MAGIC_PAT_LEN;
};
///////////////////////////////////////////////////////////
#define GET32WOL_MC_ADDR_HASH0_LO(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MC_ADDR_HASH0_LO(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MC_ADDR_HASH0 {\
UNSG32 uMC_ADDR_HASH0_LO : 32;\
}
union { UNSG32 u32WOL_MC_ADDR_HASH0;
struct w32WOL_MC_ADDR_HASH0;
};
///////////////////////////////////////////////////////////
#define GET32WOL_MC_ADDR_HASH1_HI(r32) _BFGET_(r32,31, 0)
#define SET32WOL_MC_ADDR_HASH1_HI(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_MC_ADDR_HASH1 {\
UNSG32 uMC_ADDR_HASH1_HI : 32;\
}
union { UNSG32 u32WOL_MC_ADDR_HASH1;
struct w32WOL_MC_ADDR_HASH1;
};
///////////////////////////////////////////////////////////
#define GET32WOL_MIN_STORE_LEN_BYTES(r32) _BFGET_(r32,15, 0)
#define SET32WOL_MIN_STORE_LEN_BYTES(r32,v) _BFSET_(r32,15, 0,v)
#define GET16WOL_MIN_STORE_LEN_BYTES(r16) _BFGET_(r16,15, 0)
#define SET16WOL_MIN_STORE_LEN_BYTES(r16,v) _BFSET_(r16,15, 0,v)
#define w32WOL_MIN_STORE_LEN {\
UNSG32 uMIN_STORE_LEN_BYTES : 16;\
UNSG32 RSVDx80_b16 : 16;\
}
union { UNSG32 u32WOL_MIN_STORE_LEN;
struct w32WOL_MIN_STORE_LEN;
};
///////////////////////////////////////////////////////////
#define GET32WOL_UP_STORE_LEN_BYTES(r32) _BFGET_(r32,15, 0)
#define SET32WOL_UP_STORE_LEN_BYTES(r32,v) _BFSET_(r32,15, 0,v)
#define GET16WOL_UP_STORE_LEN_BYTES(r16) _BFGET_(r16,15, 0)
#define SET16WOL_UP_STORE_LEN_BYTES(r16,v) _BFSET_(r16,15, 0,v)
#define w32WOL_UP_STORE_LEN {\
UNSG32 uUP_STORE_LEN_BYTES : 16;\
UNSG32 RSVDx84_b16 : 16;\
}
union { UNSG32 u32WOL_UP_STORE_LEN;
struct w32WOL_UP_STORE_LEN;
};
///////////////////////////////////////////////////////////
#define GET32WOL_PAT_LEN0_3_ZERO(r32) _BFGET_(r32, 7, 0)
#define SET32WOL_PAT_LEN0_3_ZERO(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16WOL_PAT_LEN0_3_ZERO(r16) _BFGET_(r16, 7, 0)
#define SET16WOL_PAT_LEN0_3_ZERO(r16,v) _BFSET_(r16, 7, 0,v)
#define GET32WOL_PAT_LEN0_3_ONE(r32) _BFGET_(r32,15, 8)
#define SET32WOL_PAT_LEN0_3_ONE(r32,v) _BFSET_(r32,15, 8,v)
#define GET16WOL_PAT_LEN0_3_ONE(r16) _BFGET_(r16,15, 8)
#define SET16WOL_PAT_LEN0_3_ONE(r16,v) _BFSET_(r16,15, 8,v)
#define GET32WOL_PAT_LEN0_3_TWO(r32) _BFGET_(r32,23,16)
#define SET32WOL_PAT_LEN0_3_TWO(r32,v) _BFSET_(r32,23,16,v)
#define GET16WOL_PAT_LEN0_3_TWO(r16) _BFGET_(r16, 7, 0)
#define SET16WOL_PAT_LEN0_3_TWO(r16,v) _BFSET_(r16, 7, 0,v)
#define GET32WOL_PAT_LEN0_3_THREE(r32) _BFGET_(r32,31,24)
#define SET32WOL_PAT_LEN0_3_THREE(r32,v) _BFSET_(r32,31,24,v)
#define GET16WOL_PAT_LEN0_3_THREE(r16) _BFGET_(r16,15, 8)
#define SET16WOL_PAT_LEN0_3_THREE(r16,v) _BFSET_(r16,15, 8,v)
#define w32WOL_PAT_LEN0_3 {\
UNSG32 uPAT_LEN0_3_ZERO : 8;\
UNSG32 uPAT_LEN0_3_ONE : 8;\
UNSG32 uPAT_LEN0_3_TWO : 8;\
UNSG32 uPAT_LEN0_3_THREE : 8;\
}
union { UNSG32 u32WOL_PAT_LEN0_3;
struct w32WOL_PAT_LEN0_3;
};
///////////////////////////////////////////////////////////
#define GET32WOL_PAT_LEN4_7_FOUR(r32) _BFGET_(r32, 7, 0)
#define SET32WOL_PAT_LEN4_7_FOUR(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16WOL_PAT_LEN4_7_FOUR(r16) _BFGET_(r16, 7, 0)
#define SET16WOL_PAT_LEN4_7_FOUR(r16,v) _BFSET_(r16, 7, 0,v)
#define GET32WOL_PAT_LEN4_7_FIVE(r32) _BFGET_(r32,15, 8)
#define SET32WOL_PAT_LEN4_7_FIVE(r32,v) _BFSET_(r32,15, 8,v)
#define GET16WOL_PAT_LEN4_7_FIVE(r16) _BFGET_(r16,15, 8)
#define SET16WOL_PAT_LEN4_7_FIVE(r16,v) _BFSET_(r16,15, 8,v)
#define GET32WOL_PAT_LEN4_7_SIX(r32) _BFGET_(r32,23,16)
#define SET32WOL_PAT_LEN4_7_SIX(r32,v) _BFSET_(r32,23,16,v)
#define GET16WOL_PAT_LEN4_7_SIX(r16) _BFGET_(r16, 7, 0)
#define SET16WOL_PAT_LEN4_7_SIX(r16,v) _BFSET_(r16, 7, 0,v)
#define GET32WOL_PAT_LEN4_7_SEVEN(r32) _BFGET_(r32,31,24)
#define SET32WOL_PAT_LEN4_7_SEVEN(r32,v) _BFSET_(r32,31,24,v)
#define GET16WOL_PAT_LEN4_7_SEVEN(r16) _BFGET_(r16,15, 8)
#define SET16WOL_PAT_LEN4_7_SEVEN(r16,v) _BFSET_(r16,15, 8,v)
#define w32WOL_PAT_LEN4_7 {\
UNSG32 uPAT_LEN4_7_FOUR : 8;\
UNSG32 uPAT_LEN4_7_FIVE : 8;\
UNSG32 uPAT_LEN4_7_SIX : 8;\
UNSG32 uPAT_LEN4_7_SEVEN : 8;\
}
union { UNSG32 u32WOL_PAT_LEN4_7;
struct w32WOL_PAT_LEN4_7;
};
///////////////////////////////////////////////////////////
#define GET32WOL_RAM_CTRL_CMD(r32) _BFGET_(r32, 7, 0)
#define SET32WOL_RAM_CTRL_CMD(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16WOL_RAM_CTRL_CMD(r16) _BFGET_(r16, 7, 0)
#define SET16WOL_RAM_CTRL_CMD(r16,v) _BFSET_(r16, 7, 0,v)
#define GET32WOL_RAM_CTRL_BYTE_NO(r32) _BFGET_(r32,15, 8)
#define SET32WOL_RAM_CTRL_BYTE_NO(r32,v) _BFSET_(r32,15, 8,v)
#define GET16WOL_RAM_CTRL_BYTE_NO(r16) _BFGET_(r16,15, 8)
#define SET16WOL_RAM_CTRL_BYTE_NO(r16,v) _BFSET_(r16,15, 8,v)
#define w32WOL_RAM_CTRL {\
UNSG32 uRAM_CTRL_CMD : 8;\
UNSG32 uRAM_CTRL_BYTE_NO : 8;\
UNSG32 RSVDx90_b16 : 16;\
}
union { UNSG32 u32WOL_RAM_CTRL;
struct w32WOL_RAM_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32WOL_RAM_DATA_0_BYTE_PAT_3_0(r32) _BFGET_(r32,31, 0)
#define SET32WOL_RAM_DATA_0_BYTE_PAT_3_0(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_RAM_DATA_0 {\
UNSG32 uRAM_DATA_0_BYTE_PAT_3_0 : 32;\
}
union { UNSG32 u32WOL_RAM_DATA_0;
struct w32WOL_RAM_DATA_0;
};
///////////////////////////////////////////////////////////
#define GET32WOL_RAM_DATA_1_BYTE_PAT_7_4(r32) _BFGET_(r32,31, 0)
#define SET32WOL_RAM_DATA_1_BYTE_PAT_7_4(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_RAM_DATA_1 {\
UNSG32 uRAM_DATA_1_BYTE_PAT_7_4 : 32;\
}
union { UNSG32 u32WOL_RAM_DATA_1;
struct w32WOL_RAM_DATA_1;
};
///////////////////////////////////////////////////////////
#define GET32WOL_RAM_DATA_2_BYTE_PAT_8(r32) _BFGET_(r32, 7, 0)
#define SET32WOL_RAM_DATA_2_BYTE_PAT_8(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16WOL_RAM_DATA_2_BYTE_PAT_8(r16) _BFGET_(r16, 7, 0)
#define SET16WOL_RAM_DATA_2_BYTE_PAT_8(r16,v) _BFSET_(r16, 7, 0,v)
#define w32WOL_RAM_DATA_2 {\
UNSG32 uRAM_DATA_2_BYTE_PAT_8 : 8;\
UNSG32 RSVDx9C_b8 : 24;\
}
union { UNSG32 u32WOL_RAM_DATA_2;
struct w32WOL_RAM_DATA_2;
};
///////////////////////////////////////////////////////////
#define GET32WOL_RCV_MAC_ADDR_LO_DWORD(r32) _BFGET_(r32,31, 0)
#define SET32WOL_RCV_MAC_ADDR_LO_DWORD(r32,v) _BFSET_(r32,31, 0,v)
#define w32WOL_RCV_MAC_ADDR_LO {\
UNSG32 uRCV_MAC_ADDR_LO_DWORD : 32;\
}
union { UNSG32 u32WOL_RCV_MAC_ADDR_LO;
struct w32WOL_RCV_MAC_ADDR_LO;
};
///////////////////////////////////////////////////////////
#define GET32WOL_RCV_MAC_ADDR_HI_WORD(r32) _BFGET_(r32,15, 0)
#define SET32WOL_RCV_MAC_ADDR_HI_WORD(r32,v) _BFSET_(r32,15, 0,v)
#define GET16WOL_RCV_MAC_ADDR_HI_WORD(r16) _BFGET_(r16,15, 0)
#define SET16WOL_RCV_MAC_ADDR_HI_WORD(r16,v) _BFSET_(r16,15, 0,v)
#define w32WOL_RCV_MAC_ADDR_HI {\
UNSG32 uRCV_MAC_ADDR_HI_WORD : 16;\
UNSG32 RSVDxA4_b16 : 16;\
}
union { UNSG32 u32WOL_RCV_MAC_ADDR_HI;
struct w32WOL_RCV_MAC_ADDR_HI;
};
///////////////////////////////////////////////////////////
#define GET32WOL_INT_STATUS_PKT_STORE(r32) _BFGET_(r32, 0, 0)
#define SET32WOL_INT_STATUS_PKT_STORE(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16WOL_INT_STATUS_PKT_STORE(r16) _BFGET_(r16, 0, 0)
#define SET16WOL_INT_STATUS_PKT_STORE(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32WOL_INT_STATUS_LINK_DOWN(r32) _BFGET_(r32, 1, 1)
#define SET32WOL_INT_STATUS_LINK_DOWN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16WOL_INT_STATUS_LINK_DOWN(r16) _BFGET_(r16, 1, 1)
#define SET16WOL_INT_STATUS_LINK_DOWN(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32WOL_INT_STATUS_LINK_UP(r32) _BFGET_(r32, 2, 2)
#define SET32WOL_INT_STATUS_LINK_UP(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16WOL_INT_STATUS_LINK_UP(r16) _BFGET_(r16, 2, 2)
#define SET16WOL_INT_STATUS_LINK_UP(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32WOL_INT_STATUS_MAGIC_PATTERN(r32) _BFGET_(r32, 3, 3)
#define SET32WOL_INT_STATUS_MAGIC_PATTERN(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16WOL_INT_STATUS_MAGIC_PATTERN(r16) _BFGET_(r16, 3, 3)
#define SET16WOL_INT_STATUS_MAGIC_PATTERN(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32WOL_INT_STATUS_WAKE_UP_PAT0(r32) _BFGET_(r32, 4, 4)
#define SET32WOL_INT_STATUS_WAKE_UP_PAT0(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16WOL_INT_STATUS_WAKE_UP_PAT0(r16) _BFGET_(r16, 4, 4)
#define SET16WOL_INT_STATUS_WAKE_UP_PAT0(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32WOL_INT_STATUS_WAKE_UP_PAT1(r32) _BFGET_(r32, 5, 5)
#define SET32WOL_INT_STATUS_WAKE_UP_PAT1(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16WOL_INT_STATUS_WAKE_UP_PAT1(r16) _BFGET_(r16, 5, 5)
#define SET16WOL_INT_STATUS_WAKE_UP_PAT1(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32WOL_INT_STATUS_WAKE_UP_PAT2(r32) _BFGET_(r32, 6, 6)
#define SET32WOL_INT_STATUS_WAKE_UP_PAT2(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16WOL_INT_STATUS_WAKE_UP_PAT2(r16) _BFGET_(r16, 6, 6)
#define SET16WOL_INT_STATUS_WAKE_UP_PAT2(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32WOL_INT_STATUS_WAKE_UP_PAT3(r32) _BFGET_(r32, 7, 7)
#define SET32WOL_INT_STATUS_WAKE_UP_PAT3(r32,v) _BFSET_(r32, 7, 7,v)
#define GET16WOL_INT_STATUS_WAKE_UP_PAT3(r16) _BFGET_(r16, 7, 7)
#define SET16WOL_INT_STATUS_WAKE_UP_PAT3(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32WOL_INT_STATUS_WAKE_UP_PAT4(r32) _BFGET_(r32, 8, 8)
#define SET32WOL_INT_STATUS_WAKE_UP_PAT4(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16WOL_INT_STATUS_WAKE_UP_PAT4(r16) _BFGET_(r16, 8, 8)
#define SET16WOL_INT_STATUS_WAKE_UP_PAT4(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32WOL_INT_STATUS_WAKE_UP_PAT5(r32) _BFGET_(r32, 9, 9)
#define SET32WOL_INT_STATUS_WAKE_UP_PAT5(r32,v) _BFSET_(r32, 9, 9,v)
#define GET16WOL_INT_STATUS_WAKE_UP_PAT5(r16) _BFGET_(r16, 9, 9)
#define SET16WOL_INT_STATUS_WAKE_UP_PAT5(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32WOL_INT_STATUS_WAKE_UP_PAT6(r32) _BFGET_(r32,10,10)
#define SET32WOL_INT_STATUS_WAKE_UP_PAT6(r32,v) _BFSET_(r32,10,10,v)
#define GET16WOL_INT_STATUS_WAKE_UP_PAT6(r16) _BFGET_(r16,10,10)
#define SET16WOL_INT_STATUS_WAKE_UP_PAT6(r16,v) _BFSET_(r16,10,10,v)
#define GET32WOL_INT_STATUS_WAKE_UP_PAT7(r32) _BFGET_(r32,11,11)
#define SET32WOL_INT_STATUS_WAKE_UP_PAT7(r32,v) _BFSET_(r32,11,11,v)
#define GET16WOL_INT_STATUS_WAKE_UP_PAT7(r16) _BFGET_(r16,11,11)
#define SET16WOL_INT_STATUS_WAKE_UP_PAT7(r16,v) _BFSET_(r16,11,11,v)
#define w32WOL_INT_STATUS {\
UNSG32 uINT_STATUS_PKT_STORE : 1;\
UNSG32 uINT_STATUS_LINK_DOWN : 1;\
UNSG32 uINT_STATUS_LINK_UP : 1;\
UNSG32 uINT_STATUS_MAGIC_PATTERN : 1;\
UNSG32 uINT_STATUS_WAKE_UP_PAT0 : 1;\
UNSG32 uINT_STATUS_WAKE_UP_PAT1 : 1;\
UNSG32 uINT_STATUS_WAKE_UP_PAT2 : 1;\
UNSG32 uINT_STATUS_WAKE_UP_PAT3 : 1;\
UNSG32 uINT_STATUS_WAKE_UP_PAT4 : 1;\
UNSG32 uINT_STATUS_WAKE_UP_PAT5 : 1;\
UNSG32 uINT_STATUS_WAKE_UP_PAT6 : 1;\
UNSG32 uINT_STATUS_WAKE_UP_PAT7 : 1;\
UNSG32 RSVDxA8_b12 : 20;\
}
union { UNSG32 u32WOL_INT_STATUS;
struct w32WOL_INT_STATUS;
};
///////////////////////////////////////////////////////////
#define GET32WOL_INT_MASK_PKT_STORE(r32) _BFGET_(r32, 0, 0)
#define SET32WOL_INT_MASK_PKT_STORE(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16WOL_INT_MASK_PKT_STORE(r16) _BFGET_(r16, 0, 0)
#define SET16WOL_INT_MASK_PKT_STORE(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32WOL_INT_MASK_LINK_DOWN(r32) _BFGET_(r32, 1, 1)
#define SET32WOL_INT_MASK_LINK_DOWN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16WOL_INT_MASK_LINK_DOWN(r16) _BFGET_(r16, 1, 1)
#define SET16WOL_INT_MASK_LINK_DOWN(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32WOL_INT_MASK_LINK_UP(r32) _BFGET_(r32, 2, 2)
#define SET32WOL_INT_MASK_LINK_UP(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16WOL_INT_MASK_LINK_UP(r16) _BFGET_(r16, 2, 2)
#define SET16WOL_INT_MASK_LINK_UP(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32WOL_INT_MASK_MAGIC_PATTERN(r32) _BFGET_(r32, 3, 3)
#define SET32WOL_INT_MASK_MAGIC_PATTERN(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16WOL_INT_MASK_MAGIC_PATTERN(r16) _BFGET_(r16, 3, 3)
#define SET16WOL_INT_MASK_MAGIC_PATTERN(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32WOL_INT_MASK_WAKE_UP_PAT0(r32) _BFGET_(r32, 4, 4)
#define SET32WOL_INT_MASK_WAKE_UP_PAT0(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16WOL_INT_MASK_WAKE_UP_PAT0(r16) _BFGET_(r16, 4, 4)
#define SET16WOL_INT_MASK_WAKE_UP_PAT0(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32WOL_INT_MASK_WAKE_UP_PAT1(r32) _BFGET_(r32, 5, 5)
#define SET32WOL_INT_MASK_WAKE_UP_PAT1(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16WOL_INT_MASK_WAKE_UP_PAT1(r16) _BFGET_(r16, 5, 5)
#define SET16WOL_INT_MASK_WAKE_UP_PAT1(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32WOL_INT_MASK_WAKE_UP_PAT2(r32) _BFGET_(r32, 6, 6)
#define SET32WOL_INT_MASK_WAKE_UP_PAT2(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16WOL_INT_MASK_WAKE_UP_PAT2(r16) _BFGET_(r16, 6, 6)
#define SET16WOL_INT_MASK_WAKE_UP_PAT2(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32WOL_INT_MASK_WAKE_UP_PAT3(r32) _BFGET_(r32, 7, 7)
#define SET32WOL_INT_MASK_WAKE_UP_PAT3(r32,v) _BFSET_(r32, 7, 7,v)
#define GET16WOL_INT_MASK_WAKE_UP_PAT3(r16) _BFGET_(r16, 7, 7)
#define SET16WOL_INT_MASK_WAKE_UP_PAT3(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32WOL_INT_MASK_WAKE_UP_PAT4(r32) _BFGET_(r32, 8, 8)
#define SET32WOL_INT_MASK_WAKE_UP_PAT4(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16WOL_INT_MASK_WAKE_UP_PAT4(r16) _BFGET_(r16, 8, 8)
#define SET16WOL_INT_MASK_WAKE_UP_PAT4(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32WOL_INT_MASK_WAKE_UP_PAT5(r32) _BFGET_(r32, 9, 9)
#define SET32WOL_INT_MASK_WAKE_UP_PAT5(r32,v) _BFSET_(r32, 9, 9,v)
#define GET16WOL_INT_MASK_WAKE_UP_PAT5(r16) _BFGET_(r16, 9, 9)
#define SET16WOL_INT_MASK_WAKE_UP_PAT5(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32WOL_INT_MASK_WAKE_UP_PAT6(r32) _BFGET_(r32,10,10)
#define SET32WOL_INT_MASK_WAKE_UP_PAT6(r32,v) _BFSET_(r32,10,10,v)
#define GET16WOL_INT_MASK_WAKE_UP_PAT6(r16) _BFGET_(r16,10,10)
#define SET16WOL_INT_MASK_WAKE_UP_PAT6(r16,v) _BFSET_(r16,10,10,v)
#define GET32WOL_INT_MASK_WAKE_UP_PAT7(r32) _BFGET_(r32,11,11)
#define SET32WOL_INT_MASK_WAKE_UP_PAT7(r32,v) _BFSET_(r32,11,11,v)
#define GET16WOL_INT_MASK_WAKE_UP_PAT7(r16) _BFGET_(r16,11,11)
#define SET16WOL_INT_MASK_WAKE_UP_PAT7(r16,v) _BFSET_(r16,11,11,v)
#define w32WOL_INT_MASK {\
UNSG32 uINT_MASK_PKT_STORE : 1;\
UNSG32 uINT_MASK_LINK_DOWN : 1;\
UNSG32 uINT_MASK_LINK_UP : 1;\
UNSG32 uINT_MASK_MAGIC_PATTERN : 1;\
UNSG32 uINT_MASK_WAKE_UP_PAT0 : 1;\
UNSG32 uINT_MASK_WAKE_UP_PAT1 : 1;\
UNSG32 uINT_MASK_WAKE_UP_PAT2 : 1;\
UNSG32 uINT_MASK_WAKE_UP_PAT3 : 1;\
UNSG32 uINT_MASK_WAKE_UP_PAT4 : 1;\
UNSG32 uINT_MASK_WAKE_UP_PAT5 : 1;\
UNSG32 uINT_MASK_WAKE_UP_PAT6 : 1;\
UNSG32 uINT_MASK_WAKE_UP_PAT7 : 1;\
UNSG32 RSVDxAC_b12 : 20;\
}
union { UNSG32 u32WOL_INT_MASK;
struct w32WOL_INT_MASK;
};
///////////////////////////////////////////////////////////
#define GET32WOL_FEPHY_CTRL_ext_pwrdn_a(r32) _BFGET_(r32, 4, 0)
#define SET32WOL_FEPHY_CTRL_ext_pwrdn_a(r32,v) _BFSET_(r32, 4, 0,v)
#define GET16WOL_FEPHY_CTRL_ext_pwrdn_a(r16) _BFGET_(r16, 4, 0)
#define SET16WOL_FEPHY_CTRL_ext_pwrdn_a(r16,v) _BFSET_(r16, 4, 0,v)
#define GET32WOL_FEPHY_CTRL_pd_aneg_mode_a(r32) _BFGET_(r32, 7, 5)
#define SET32WOL_FEPHY_CTRL_pd_aneg_mode_a(r32,v) _BFSET_(r32, 7, 5,v)
#define GET16WOL_FEPHY_CTRL_pd_aneg_mode_a(r16) _BFGET_(r16, 7, 5)
#define SET16WOL_FEPHY_CTRL_pd_aneg_mode_a(r16,v) _BFSET_(r16, 7, 5,v)
#define GET32WOL_FEPHY_CTRL_pd_phyadr_a(r32) _BFGET_(r32,12, 8)
#define SET32WOL_FEPHY_CTRL_pd_phyadr_a(r32,v) _BFSET_(r32,12, 8,v)
#define GET16WOL_FEPHY_CTRL_pd_phyadr_a(r16) _BFGET_(r16,12, 8)
#define SET16WOL_FEPHY_CTRL_pd_phyadr_a(r16,v) _BFSET_(r16,12, 8,v)
#define GET32WOL_FEPHY_CTRL_pd_led_config_a(r32) _BFGET_(r32,15,13)
#define SET32WOL_FEPHY_CTRL_pd_led_config_a(r32,v) _BFSET_(r32,15,13,v)
#define GET16WOL_FEPHY_CTRL_pd_led_config_a(r16) _BFGET_(r16,15,13)
#define SET16WOL_FEPHY_CTRL_pd_led_config_a(r16,v) _BFSET_(r16,15,13,v)
#define GET32WOL_FEPHY_CTRL_yy_pecl_sdet_a(r32) _BFGET_(r32,20,16)
#define SET32WOL_FEPHY_CTRL_yy_pecl_sdet_a(r32,v) _BFSET_(r32,20,16,v)
#define GET16WOL_FEPHY_CTRL_yy_pecl_sdet_a(r16) _BFGET_(r16, 4, 0)
#define SET16WOL_FEPHY_CTRL_yy_pecl_sdet_a(r16,v) _BFSET_(r16, 4, 0,v)
#define GET32WOL_FEPHY_CTRL_ps_en_eee10t_s(r32) _BFGET_(r32,21,21)
#define SET32WOL_FEPHY_CTRL_ps_en_eee10t_s(r32,v) _BFSET_(r32,21,21,v)
#define GET16WOL_FEPHY_CTRL_ps_en_eee10t_s(r16) _BFGET_(r16, 5, 5)
#define SET16WOL_FEPHY_CTRL_ps_en_eee10t_s(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32WOL_FEPHY_CTRL_ps_en_eee100t_s(r32) _BFGET_(r32,22,22)
#define SET32WOL_FEPHY_CTRL_ps_en_eee100t_s(r32,v) _BFSET_(r32,22,22,v)
#define GET16WOL_FEPHY_CTRL_ps_en_eee100t_s(r16) _BFGET_(r16, 6, 6)
#define SET16WOL_FEPHY_CTRL_ps_en_eee100t_s(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32WOL_FEPHY_CTRL_pd_burnin_a(r32) _BFGET_(r32,23,23)
#define SET32WOL_FEPHY_CTRL_pd_burnin_a(r32,v) _BFSET_(r32,23,23,v)
#define GET16WOL_FEPHY_CTRL_pd_burnin_a(r16) _BFGET_(r16, 7, 7)
#define SET16WOL_FEPHY_CTRL_pd_burnin_a(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32WOL_FEPHY_CTRL_pd_ena_edet_a(r32) _BFGET_(r32,24,24)
#define SET32WOL_FEPHY_CTRL_pd_ena_edet_a(r32,v) _BFSET_(r32,24,24,v)
#define GET16WOL_FEPHY_CTRL_pd_ena_edet_a(r16) _BFGET_(r16, 8, 8)
#define SET16WOL_FEPHY_CTRL_pd_ena_edet_a(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32WOL_FEPHY_CTRL_pd_ena_xc_a(r32) _BFGET_(r32,25,25)
#define SET32WOL_FEPHY_CTRL_pd_ena_xc_a(r32,v) _BFSET_(r32,25,25,v)
#define GET16WOL_FEPHY_CTRL_pd_ena_xc_a(r16) _BFGET_(r16, 9, 9)
#define SET16WOL_FEPHY_CTRL_pd_ena_xc_a(r16,v) _BFSET_(r16, 9, 9,v)
#define w32WOL_FEPHY_CTRL {\
UNSG32 uFEPHY_CTRL_ext_pwrdn_a : 5;\
UNSG32 uFEPHY_CTRL_pd_aneg_mode_a : 3;\
UNSG32 uFEPHY_CTRL_pd_phyadr_a : 5;\
UNSG32 uFEPHY_CTRL_pd_led_config_a : 3;\
UNSG32 uFEPHY_CTRL_yy_pecl_sdet_a : 5;\
UNSG32 uFEPHY_CTRL_ps_en_eee10t_s : 1;\
UNSG32 uFEPHY_CTRL_ps_en_eee100t_s : 1;\
UNSG32 uFEPHY_CTRL_pd_burnin_a : 1;\
UNSG32 uFEPHY_CTRL_pd_ena_edet_a : 1;\
UNSG32 uFEPHY_CTRL_pd_ena_xc_a : 1;\
UNSG32 RSVDxB0_b26 : 6;\
}
union { UNSG32 u32WOL_FEPHY_CTRL;
struct w32WOL_FEPHY_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32WOL_FEPHY_STS_misc_speed_s(r32) _BFGET_(r32, 0, 0)
#define SET32WOL_FEPHY_STS_misc_speed_s(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16WOL_FEPHY_STS_misc_speed_s(r16) _BFGET_(r16, 0, 0)
#define SET16WOL_FEPHY_STS_misc_speed_s(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32WOL_FEPHY_STS_misc_duplex_s(r32) _BFGET_(r32, 1, 1)
#define SET32WOL_FEPHY_STS_misc_duplex_s(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16WOL_FEPHY_STS_misc_duplex_s(r16) _BFGET_(r16, 1, 1)
#define SET16WOL_FEPHY_STS_misc_duplex_s(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32WOL_FEPHY_STS_misc_hcd_resolved_s(r32) _BFGET_(r32, 2, 2)
#define SET32WOL_FEPHY_STS_misc_hcd_resolved_s(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16WOL_FEPHY_STS_misc_hcd_resolved_s(r16) _BFGET_(r16, 2, 2)
#define SET16WOL_FEPHY_STS_misc_hcd_resolved_s(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32WOL_FEPHY_STS_misc_link_s(r32) _BFGET_(r32, 3, 3)
#define SET32WOL_FEPHY_STS_misc_link_s(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16WOL_FEPHY_STS_misc_link_s(r16) _BFGET_(r16, 3, 3)
#define SET16WOL_FEPHY_STS_misc_link_s(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32WOL_FEPHY_STS_misc_lpi_s(r32) _BFGET_(r32, 4, 4)
#define SET32WOL_FEPHY_STS_misc_lpi_s(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16WOL_FEPHY_STS_misc_lpi_s(r16) _BFGET_(r16, 4, 4)
#define SET16WOL_FEPHY_STS_misc_lpi_s(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32WOL_FEPHY_STS_misc_rx_lpi_s(r32) _BFGET_(r32, 5, 5)
#define SET32WOL_FEPHY_STS_misc_rx_lpi_s(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16WOL_FEPHY_STS_misc_rx_lpi_s(r16) _BFGET_(r16, 5, 5)
#define SET16WOL_FEPHY_STS_misc_rx_lpi_s(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32WOL_FEPHY_STS_misc_pause_s(r32) _BFGET_(r32, 6, 6)
#define SET32WOL_FEPHY_STS_misc_pause_s(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16WOL_FEPHY_STS_misc_pause_s(r16) _BFGET_(r16, 6, 6)
#define SET16WOL_FEPHY_STS_misc_pause_s(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32WOL_FEPHY_STS_misc_lp_pause_s(r32) _BFGET_(r32, 7, 7)
#define SET32WOL_FEPHY_STS_misc_lp_pause_s(r32,v) _BFSET_(r32, 7, 7,v)
#define GET16WOL_FEPHY_STS_misc_lp_pause_s(r16) _BFGET_(r16, 7, 7)
#define SET16WOL_FEPHY_STS_misc_lp_pause_s(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32WOL_FEPHY_STS_misc_int_s(r32) _BFGET_(r32, 8, 8)
#define SET32WOL_FEPHY_STS_misc_int_s(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16WOL_FEPHY_STS_misc_int_s(r16) _BFGET_(r16, 8, 8)
#define SET16WOL_FEPHY_STS_misc_int_s(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32WOL_FEPHY_STS_misc_edet_status_s(r32) _BFGET_(r32, 9, 9)
#define SET32WOL_FEPHY_STS_misc_edet_status_s(r32,v) _BFSET_(r32, 9, 9,v)
#define GET16WOL_FEPHY_STS_misc_edet_status_s(r16) _BFGET_(r16, 9, 9)
#define SET16WOL_FEPHY_STS_misc_edet_status_s(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32WOL_FEPHY_STS_tx_latency_mark_a(r32) _BFGET_(r32,10,10)
#define SET32WOL_FEPHY_STS_tx_latency_mark_a(r32,v) _BFSET_(r32,10,10,v)
#define GET16WOL_FEPHY_STS_tx_latency_mark_a(r16) _BFGET_(r16,10,10)
#define SET16WOL_FEPHY_STS_tx_latency_mark_a(r16,v) _BFSET_(r16,10,10,v)
#define GET32WOL_FEPHY_STS_misc_por_reset(r32) _BFGET_(r32,11,11)
#define SET32WOL_FEPHY_STS_misc_por_reset(r32,v) _BFSET_(r32,11,11,v)
#define GET16WOL_FEPHY_STS_misc_por_reset(r16) _BFGET_(r16,11,11)
#define SET16WOL_FEPHY_STS_misc_por_reset(r16,v) _BFSET_(r16,11,11,v)
#define w32WOL_FEPHY_STS {\
UNSG32 uFEPHY_STS_misc_speed_s : 1;\
UNSG32 uFEPHY_STS_misc_duplex_s : 1;\
UNSG32 uFEPHY_STS_misc_hcd_resolved_s : 1;\
UNSG32 uFEPHY_STS_misc_link_s : 1;\
UNSG32 uFEPHY_STS_misc_lpi_s : 1;\
UNSG32 uFEPHY_STS_misc_rx_lpi_s : 1;\
UNSG32 uFEPHY_STS_misc_pause_s : 1;\
UNSG32 uFEPHY_STS_misc_lp_pause_s : 1;\
UNSG32 uFEPHY_STS_misc_int_s : 1;\
UNSG32 uFEPHY_STS_misc_edet_status_s : 1;\
UNSG32 uFEPHY_STS_tx_latency_mark_a : 1;\
UNSG32 uFEPHY_STS_misc_por_reset : 1;\
UNSG32 RSVDxB4_b12 : 20;\
}
union { UNSG32 u32WOL_FEPHY_STS;
struct w32WOL_FEPHY_STS;
};
///////////////////////////////////////////////////////////
} SIE_WOL;
typedef union T32WOL_CTRL
{ UNSG32 u32;
struct w32WOL_CTRL;
} T32WOL_CTRL;
typedef union T32WOL_MAC_ADDR_LO
{ UNSG32 u32;
struct w32WOL_MAC_ADDR_LO;
} T32WOL_MAC_ADDR_LO;
typedef union T32WOL_MAC_ADDR_HI
{ UNSG32 u32;
struct w32WOL_MAC_ADDR_HI;
} T32WOL_MAC_ADDR_HI;
typedef union T32WOL_MAGIC_PAT
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT;
} T32WOL_MAGIC_PAT;
typedef union T32WOL_MAGIC_PAT1
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT1;
} T32WOL_MAGIC_PAT1;
typedef union T32WOL_MAGIC_PAT2
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT2;
} T32WOL_MAGIC_PAT2;
typedef union T32WOL_MAGIC_PAT3
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT3;
} T32WOL_MAGIC_PAT3;
typedef union T32WOL_MAGIC_PAT4
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT4;
} T32WOL_MAGIC_PAT4;
typedef union T32WOL_MAGIC_PAT5
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT5;
} T32WOL_MAGIC_PAT5;
typedef union T32WOL_MAGIC_PAT6
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT6;
} T32WOL_MAGIC_PAT6;
typedef union T32WOL_MAGIC_PAT7
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT7;
} T32WOL_MAGIC_PAT7;
typedef union T32WOL_MAGIC_PAT8
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT8;
} T32WOL_MAGIC_PAT8;
typedef union T32WOL_MAGIC_PAT9
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT9;
} T32WOL_MAGIC_PAT9;
typedef union T32WOL_MAGIC_PAT10
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT10;
} T32WOL_MAGIC_PAT10;
typedef union T32WOL_MAGIC_PAT11
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT11;
} T32WOL_MAGIC_PAT11;
typedef union T32WOL_MAGIC_PAT12
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT12;
} T32WOL_MAGIC_PAT12;
typedef union T32WOL_MAGIC_PAT13
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT13;
} T32WOL_MAGIC_PAT13;
typedef union T32WOL_MAGIC_PAT14
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT14;
} T32WOL_MAGIC_PAT14;
typedef union T32WOL_MAGIC_PAT15
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT15;
} T32WOL_MAGIC_PAT15;
typedef union T32WOL_MAGIC_PAT16
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT16;
} T32WOL_MAGIC_PAT16;
typedef union T32WOL_MAGIC_PAT17
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT17;
} T32WOL_MAGIC_PAT17;
typedef union T32WOL_MAGIC_PAT18
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT18;
} T32WOL_MAGIC_PAT18;
typedef union T32WOL_MAGIC_PAT19
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT19;
} T32WOL_MAGIC_PAT19;
typedef union T32WOL_MAGIC_PAT20
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT20;
} T32WOL_MAGIC_PAT20;
typedef union T32WOL_MAGIC_PAT21
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT21;
} T32WOL_MAGIC_PAT21;
typedef union T32WOL_MAGIC_PAT22
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT22;
} T32WOL_MAGIC_PAT22;
typedef union T32WOL_MAGIC_PAT23
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT23;
} T32WOL_MAGIC_PAT23;
typedef union T32WOL_MAGIC_PAT24
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT24;
} T32WOL_MAGIC_PAT24;
typedef union T32WOL_MAGIC_PAT25
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT25;
} T32WOL_MAGIC_PAT25;
typedef union T32WOL_MAGIC_PAT_LEN
{ UNSG32 u32;
struct w32WOL_MAGIC_PAT_LEN;
} T32WOL_MAGIC_PAT_LEN;
typedef union T32WOL_MC_ADDR_HASH0
{ UNSG32 u32;
struct w32WOL_MC_ADDR_HASH0;
} T32WOL_MC_ADDR_HASH0;
typedef union T32WOL_MC_ADDR_HASH1
{ UNSG32 u32;
struct w32WOL_MC_ADDR_HASH1;
} T32WOL_MC_ADDR_HASH1;
typedef union T32WOL_MIN_STORE_LEN
{ UNSG32 u32;
struct w32WOL_MIN_STORE_LEN;
} T32WOL_MIN_STORE_LEN;
typedef union T32WOL_UP_STORE_LEN
{ UNSG32 u32;
struct w32WOL_UP_STORE_LEN;
} T32WOL_UP_STORE_LEN;
typedef union T32WOL_PAT_LEN0_3
{ UNSG32 u32;
struct w32WOL_PAT_LEN0_3;
} T32WOL_PAT_LEN0_3;
typedef union T32WOL_PAT_LEN4_7
{ UNSG32 u32;
struct w32WOL_PAT_LEN4_7;
} T32WOL_PAT_LEN4_7;
typedef union T32WOL_RAM_CTRL
{ UNSG32 u32;
struct w32WOL_RAM_CTRL;
} T32WOL_RAM_CTRL;
typedef union T32WOL_RAM_DATA_0
{ UNSG32 u32;
struct w32WOL_RAM_DATA_0;
} T32WOL_RAM_DATA_0;
typedef union T32WOL_RAM_DATA_1
{ UNSG32 u32;
struct w32WOL_RAM_DATA_1;
} T32WOL_RAM_DATA_1;
typedef union T32WOL_RAM_DATA_2
{ UNSG32 u32;
struct w32WOL_RAM_DATA_2;
} T32WOL_RAM_DATA_2;
typedef union T32WOL_RCV_MAC_ADDR_LO
{ UNSG32 u32;
struct w32WOL_RCV_MAC_ADDR_LO;
} T32WOL_RCV_MAC_ADDR_LO;
typedef union T32WOL_RCV_MAC_ADDR_HI
{ UNSG32 u32;
struct w32WOL_RCV_MAC_ADDR_HI;
} T32WOL_RCV_MAC_ADDR_HI;
typedef union T32WOL_INT_STATUS
{ UNSG32 u32;
struct w32WOL_INT_STATUS;
} T32WOL_INT_STATUS;
typedef union T32WOL_INT_MASK
{ UNSG32 u32;
struct w32WOL_INT_MASK;
} T32WOL_INT_MASK;
typedef union T32WOL_FEPHY_CTRL
{ UNSG32 u32;
struct w32WOL_FEPHY_CTRL;
} T32WOL_FEPHY_CTRL;
typedef union T32WOL_FEPHY_STS
{ UNSG32 u32;
struct w32WOL_FEPHY_STS;
} T32WOL_FEPHY_STS;
///////////////////////////////////////////////////////////
typedef union TWOL_CTRL
{ UNSG32 u32[1];
struct {
struct w32WOL_CTRL;
};
} TWOL_CTRL;
typedef union TWOL_MAC_ADDR_LO
{ UNSG32 u32[1];
struct {
struct w32WOL_MAC_ADDR_LO;
};
} TWOL_MAC_ADDR_LO;
typedef union TWOL_MAC_ADDR_HI
{ UNSG32 u32[1];
struct {
struct w32WOL_MAC_ADDR_HI;
};
} TWOL_MAC_ADDR_HI;
typedef union TWOL_MAGIC_PAT
{ UNSG32 u32[26];
struct {
struct w32WOL_MAGIC_PAT;
struct w32WOL_MAGIC_PAT1;
struct w32WOL_MAGIC_PAT2;
struct w32WOL_MAGIC_PAT3;
struct w32WOL_MAGIC_PAT4;
struct w32WOL_MAGIC_PAT5;
struct w32WOL_MAGIC_PAT6;
struct w32WOL_MAGIC_PAT7;
struct w32WOL_MAGIC_PAT8;
struct w32WOL_MAGIC_PAT9;
struct w32WOL_MAGIC_PAT10;
struct w32WOL_MAGIC_PAT11;
struct w32WOL_MAGIC_PAT12;
struct w32WOL_MAGIC_PAT13;
struct w32WOL_MAGIC_PAT14;
struct w32WOL_MAGIC_PAT15;
struct w32WOL_MAGIC_PAT16;
struct w32WOL_MAGIC_PAT17;
struct w32WOL_MAGIC_PAT18;
struct w32WOL_MAGIC_PAT19;
struct w32WOL_MAGIC_PAT20;
struct w32WOL_MAGIC_PAT21;
struct w32WOL_MAGIC_PAT22;
struct w32WOL_MAGIC_PAT23;
struct w32WOL_MAGIC_PAT24;
struct w32WOL_MAGIC_PAT25;
};
} TWOL_MAGIC_PAT;
typedef union TWOL_MAGIC_PAT_LEN
{ UNSG32 u32[1];
struct {
struct w32WOL_MAGIC_PAT_LEN;
};
} TWOL_MAGIC_PAT_LEN;
typedef union TWOL_MC_ADDR_HASH0
{ UNSG32 u32[1];
struct {
struct w32WOL_MC_ADDR_HASH0;
};
} TWOL_MC_ADDR_HASH0;
typedef union TWOL_MC_ADDR_HASH1
{ UNSG32 u32[1];
struct {
struct w32WOL_MC_ADDR_HASH1;
};
} TWOL_MC_ADDR_HASH1;
typedef union TWOL_MIN_STORE_LEN
{ UNSG32 u32[1];
struct {
struct w32WOL_MIN_STORE_LEN;
};
} TWOL_MIN_STORE_LEN;
typedef union TWOL_UP_STORE_LEN
{ UNSG32 u32[1];
struct {
struct w32WOL_UP_STORE_LEN;
};
} TWOL_UP_STORE_LEN;
typedef union TWOL_PAT_LEN0_3
{ UNSG32 u32[1];
struct {
struct w32WOL_PAT_LEN0_3;
};
} TWOL_PAT_LEN0_3;
typedef union TWOL_PAT_LEN4_7
{ UNSG32 u32[1];
struct {
struct w32WOL_PAT_LEN4_7;
};
} TWOL_PAT_LEN4_7;
typedef union TWOL_RAM_CTRL
{ UNSG32 u32[1];
struct {
struct w32WOL_RAM_CTRL;
};
} TWOL_RAM_CTRL;
typedef union TWOL_RAM_DATA_0
{ UNSG32 u32[1];
struct {
struct w32WOL_RAM_DATA_0;
};
} TWOL_RAM_DATA_0;
typedef union TWOL_RAM_DATA_1
{ UNSG32 u32[1];
struct {
struct w32WOL_RAM_DATA_1;
};
} TWOL_RAM_DATA_1;
typedef union TWOL_RAM_DATA_2
{ UNSG32 u32[1];
struct {
struct w32WOL_RAM_DATA_2;
};
} TWOL_RAM_DATA_2;
typedef union TWOL_RCV_MAC_ADDR_LO
{ UNSG32 u32[1];
struct {
struct w32WOL_RCV_MAC_ADDR_LO;
};
} TWOL_RCV_MAC_ADDR_LO;
typedef union TWOL_RCV_MAC_ADDR_HI
{ UNSG32 u32[1];
struct {
struct w32WOL_RCV_MAC_ADDR_HI;
};
} TWOL_RCV_MAC_ADDR_HI;
typedef union TWOL_INT_STATUS
{ UNSG32 u32[1];
struct {
struct w32WOL_INT_STATUS;
};
} TWOL_INT_STATUS;
typedef union TWOL_INT_MASK
{ UNSG32 u32[1];
struct {
struct w32WOL_INT_MASK;
};
} TWOL_INT_MASK;
typedef union TWOL_FEPHY_CTRL
{ UNSG32 u32[1];
struct {
struct w32WOL_FEPHY_CTRL;
};
} TWOL_FEPHY_CTRL;
typedef union TWOL_FEPHY_STS
{ UNSG32 u32[1];
struct {
struct w32WOL_FEPHY_STS;
};
} TWOL_FEPHY_STS;
///////////////////////////////////////////////////////////
SIGN32 WOL_drvrd(SIE_WOL *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 WOL_drvwr(SIE_WOL *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void WOL_reset(SIE_WOL *p);
SIGN32 WOL_cmp (SIE_WOL *p, SIE_WOL *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define WOL_check(p,pie,pfx,hLOG) WOL_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define WOL_print(p, pfx,hLOG) WOL_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: WOL
////////////////////////////////////////////////////////////
#ifdef __cplusplus
}
#endif
#pragma pack()
#endif
//////
/// ENDOFFILE: wol.h
////////////////////////////////////////////////////////////