| /* |
| * Copyright Marvell Semiconductor, Inc. 2006. All rights reserved. |
| * |
| * Register address mapping configure file for rom testing code. |
| */ |
| |
| #ifndef __RA_Gbl__H__ |
| #define __RA_Gbl__H__ |
| |
| #define RA_clkD1_ctrl 0x0000 |
| #define BA_clkD1_ctrl_ClkEn 0x0000 |
| #define B16clkD1_ctrl_ClkEn 0x0000 |
| #define LSb32clkD1_ctrl_ClkEn 0 |
| #define LSb16clkD1_ctrl_ClkEn 0 |
| #define bclkD1_ctrl_ClkEn 1 |
| #define MSK32clkD1_ctrl_ClkEn 0x00000001 |
| #define clkD1_ctrl_ClkEn_enable 0x1 |
| #define clkD1_ctrl_ClkEn_disable 0x0 |
| #define BA_clkD1_ctrl_ClkPllSel 0x0000 |
| #define B16clkD1_ctrl_ClkPllSel 0x0000 |
| #define LSb32clkD1_ctrl_ClkPllSel 1 |
| #define LSb16clkD1_ctrl_ClkPllSel 1 |
| #define bclkD1_ctrl_ClkPllSel 3 |
| #define MSK32clkD1_ctrl_ClkPllSel 0x0000000E |
| #define clkD1_ctrl_ClkPllSel_AVPllB4 0x0 |
| #define clkD1_ctrl_ClkPllSel_AVPllB5 0x1 |
| #define clkD1_ctrl_ClkPllSel_AVPllB6 0x2 |
| #define clkD1_ctrl_ClkPllSel_AVPllB7 0x3 |
| #define clkD1_ctrl_ClkPllSel_SYSPLL 0x4 |
| #define BA_clkD1_ctrl_ClkPllSwitch 0x0000 |
| #define B16clkD1_ctrl_ClkPllSwitch 0x0000 |
| #define LSb32clkD1_ctrl_ClkPllSwitch 4 |
| #define LSb16clkD1_ctrl_ClkPllSwitch 4 |
| #define bclkD1_ctrl_ClkPllSwitch 1 |
| #define MSK32clkD1_ctrl_ClkPllSwitch 0x00000010 |
| #define clkD1_ctrl_ClkPllSwitch_SYSPLL 0x0 |
| #define clkD1_ctrl_ClkPllSwitch_AVPLL 0x1 |
| #define BA_clkD1_ctrl_ClkSwitch 0x0000 |
| #define B16clkD1_ctrl_ClkSwitch 0x0000 |
| #define LSb32clkD1_ctrl_ClkSwitch 5 |
| #define LSb16clkD1_ctrl_ClkSwitch 5 |
| #define bclkD1_ctrl_ClkSwitch 1 |
| #define MSK32clkD1_ctrl_ClkSwitch 0x00000020 |
| #define clkD1_ctrl_ClkSwitch_SrcClk 0x0 |
| #define clkD1_ctrl_ClkSwitch_DivClk 0x1 |
| #define BA_clkD1_ctrl_ClkD3Switch 0x0000 |
| #define B16clkD1_ctrl_ClkD3Switch 0x0000 |
| #define LSb32clkD1_ctrl_ClkD3Switch 6 |
| #define LSb16clkD1_ctrl_ClkD3Switch 6 |
| #define bclkD1_ctrl_ClkD3Switch 1 |
| #define MSK32clkD1_ctrl_ClkD3Switch 0x00000040 |
| #define clkD1_ctrl_ClkD3Switch_NonDiv3Clk 0x0 |
| #define clkD1_ctrl_ClkD3Switch_Div3Clk 0x1 |
| #define BA_clkD1_ctrl_ClkSel 0x0000 |
| #define B16clkD1_ctrl_ClkSel 0x0000 |
| #define LSb32clkD1_ctrl_ClkSel 7 |
| #define LSb16clkD1_ctrl_ClkSel 7 |
| #define bclkD1_ctrl_ClkSel 3 |
| #define MSK32clkD1_ctrl_ClkSel 0x00000380 |
| #define clkD1_ctrl_ClkSel_d2 0x1 |
| #define clkD1_ctrl_ClkSel_d4 0x2 |
| #define clkD1_ctrl_ClkSel_d6 0x3 |
| #define clkD1_ctrl_ClkSel_d8 0x4 |
| #define clkD1_ctrl_ClkSel_d12 0x5 |
| #define RA_clkD2_ctrl 0x0000 |
| #define BA_clkD2_ctrl_ClkEn 0x0000 |
| #define B16clkD2_ctrl_ClkEn 0x0000 |
| #define LSb32clkD2_ctrl_ClkEn 0 |
| #define LSb16clkD2_ctrl_ClkEn 0 |
| #define bclkD2_ctrl_ClkEn 1 |
| #define MSK32clkD2_ctrl_ClkEn 0x00000001 |
| #define clkD2_ctrl_ClkEn_enable 0x1 |
| #define clkD2_ctrl_ClkEn_disable 0x0 |
| #define BA_clkD2_ctrl_ClkPllSel 0x0000 |
| #define B16clkD2_ctrl_ClkPllSel 0x0000 |
| #define LSb32clkD2_ctrl_ClkPllSel 1 |
| #define LSb16clkD2_ctrl_ClkPllSel 1 |
| #define bclkD2_ctrl_ClkPllSel 3 |
| #define MSK32clkD2_ctrl_ClkPllSel 0x0000000E |
| #define clkD2_ctrl_ClkPllSel_AVPllB4 0x0 |
| #define clkD2_ctrl_ClkPllSel_AVPllB5 0x1 |
| #define clkD2_ctrl_ClkPllSel_AVPllB6 0x2 |
| #define clkD2_ctrl_ClkPllSel_AVPllB7 0x3 |
| #define clkD2_ctrl_ClkPllSel_SYSPLL 0x4 |
| #define BA_clkD2_ctrl_ClkPllSwitch 0x0000 |
| #define B16clkD2_ctrl_ClkPllSwitch 0x0000 |
| #define LSb32clkD2_ctrl_ClkPllSwitch 4 |
| #define LSb16clkD2_ctrl_ClkPllSwitch 4 |
| #define bclkD2_ctrl_ClkPllSwitch 1 |
| #define MSK32clkD2_ctrl_ClkPllSwitch 0x00000010 |
| #define clkD2_ctrl_ClkPllSwitch_SYSPLL 0x0 |
| #define clkD2_ctrl_ClkPllSwitch_AVPLL 0x1 |
| #define BA_clkD2_ctrl_ClkSwitch 0x0000 |
| #define B16clkD2_ctrl_ClkSwitch 0x0000 |
| #define LSb32clkD2_ctrl_ClkSwitch 5 |
| #define LSb16clkD2_ctrl_ClkSwitch 5 |
| #define bclkD2_ctrl_ClkSwitch 1 |
| #define MSK32clkD2_ctrl_ClkSwitch 0x00000020 |
| #define clkD2_ctrl_ClkSwitch_SrcClk 0x0 |
| #define clkD2_ctrl_ClkSwitch_DivClk 0x1 |
| #define BA_clkD2_ctrl_ClkD3Switch 0x0000 |
| #define B16clkD2_ctrl_ClkD3Switch 0x0000 |
| #define LSb32clkD2_ctrl_ClkD3Switch 6 |
| #define LSb16clkD2_ctrl_ClkD3Switch 6 |
| #define bclkD2_ctrl_ClkD3Switch 1 |
| #define MSK32clkD2_ctrl_ClkD3Switch 0x00000040 |
| #define clkD2_ctrl_ClkD3Switch_NonDiv3Clk 0x0 |
| #define clkD2_ctrl_ClkD3Switch_Div3Clk 0x1 |
| #define BA_clkD2_ctrl_ClkSel 0x0000 |
| #define B16clkD2_ctrl_ClkSel 0x0000 |
| #define LSb32clkD2_ctrl_ClkSel 7 |
| #define LSb16clkD2_ctrl_ClkSel 7 |
| #define bclkD2_ctrl_ClkSel 3 |
| #define MSK32clkD2_ctrl_ClkSel 0x00000380 |
| #define clkD2_ctrl_ClkSel_d2 0x1 |
| #define clkD2_ctrl_ClkSel_d4 0x2 |
| #define clkD2_ctrl_ClkSel_d6 0x3 |
| #define clkD2_ctrl_ClkSel_d8 0x4 |
| #define clkD2_ctrl_ClkSel_d12 0x5 |
| #define RA_clkD4_ctrl 0x0000 |
| #define BA_clkD4_ctrl_ClkEn 0x0000 |
| #define B16clkD4_ctrl_ClkEn 0x0000 |
| #define LSb32clkD4_ctrl_ClkEn 0 |
| #define LSb16clkD4_ctrl_ClkEn 0 |
| #define bclkD4_ctrl_ClkEn 1 |
| #define MSK32clkD4_ctrl_ClkEn 0x00000001 |
| #define clkD4_ctrl_ClkEn_enable 0x1 |
| #define clkD4_ctrl_ClkEn_disable 0x0 |
| #define BA_clkD4_ctrl_ClkPllSel 0x0000 |
| #define B16clkD4_ctrl_ClkPllSel 0x0000 |
| #define LSb32clkD4_ctrl_ClkPllSel 1 |
| #define LSb16clkD4_ctrl_ClkPllSel 1 |
| #define bclkD4_ctrl_ClkPllSel 3 |
| #define MSK32clkD4_ctrl_ClkPllSel 0x0000000E |
| #define clkD4_ctrl_ClkPllSel_AVPllB4 0x0 |
| #define clkD4_ctrl_ClkPllSel_AVPllB5 0x1 |
| #define clkD4_ctrl_ClkPllSel_AVPllB6 0x2 |
| #define clkD4_ctrl_ClkPllSel_AVPllB7 0x3 |
| #define clkD4_ctrl_ClkPllSel_SYSPLL 0x4 |
| #define BA_clkD4_ctrl_ClkPllSwitch 0x0000 |
| #define B16clkD4_ctrl_ClkPllSwitch 0x0000 |
| #define LSb32clkD4_ctrl_ClkPllSwitch 4 |
| #define LSb16clkD4_ctrl_ClkPllSwitch 4 |
| #define bclkD4_ctrl_ClkPllSwitch 1 |
| #define MSK32clkD4_ctrl_ClkPllSwitch 0x00000010 |
| #define clkD4_ctrl_ClkPllSwitch_SYSPLL 0x0 |
| #define clkD4_ctrl_ClkPllSwitch_AVPLL 0x1 |
| #define BA_clkD4_ctrl_ClkSwitch 0x0000 |
| #define B16clkD4_ctrl_ClkSwitch 0x0000 |
| #define LSb32clkD4_ctrl_ClkSwitch 5 |
| #define LSb16clkD4_ctrl_ClkSwitch 5 |
| #define bclkD4_ctrl_ClkSwitch 1 |
| #define MSK32clkD4_ctrl_ClkSwitch 0x00000020 |
| #define clkD4_ctrl_ClkSwitch_SrcClk 0x0 |
| #define clkD4_ctrl_ClkSwitch_DivClk 0x1 |
| #define BA_clkD4_ctrl_ClkD3Switch 0x0000 |
| #define B16clkD4_ctrl_ClkD3Switch 0x0000 |
| #define LSb32clkD4_ctrl_ClkD3Switch 6 |
| #define LSb16clkD4_ctrl_ClkD3Switch 6 |
| #define bclkD4_ctrl_ClkD3Switch 1 |
| #define MSK32clkD4_ctrl_ClkD3Switch 0x00000040 |
| #define clkD4_ctrl_ClkD3Switch_NonDiv3Clk 0x0 |
| #define clkD4_ctrl_ClkD3Switch_Div3Clk 0x1 |
| #define BA_clkD4_ctrl_ClkSel 0x0000 |
| #define B16clkD4_ctrl_ClkSel 0x0000 |
| #define LSb32clkD4_ctrl_ClkSel 7 |
| #define LSb16clkD4_ctrl_ClkSel 7 |
| #define bclkD4_ctrl_ClkSel 3 |
| #define MSK32clkD4_ctrl_ClkSel 0x00000380 |
| #define clkD4_ctrl_ClkSel_d2 0x1 |
| #define clkD4_ctrl_ClkSel_d4 0x2 |
| #define clkD4_ctrl_ClkSel_d6 0x3 |
| #define clkD4_ctrl_ClkSel_d8 0x4 |
| #define clkD4_ctrl_ClkSel_d12 0x5 |
| #define RA_clkD6_ctrl 0x0000 |
| #define BA_clkD6_ctrl_ClkEn 0x0000 |
| #define B16clkD6_ctrl_ClkEn 0x0000 |
| #define LSb32clkD6_ctrl_ClkEn 0 |
| #define LSb16clkD6_ctrl_ClkEn 0 |
| #define bclkD6_ctrl_ClkEn 1 |
| #define MSK32clkD6_ctrl_ClkEn 0x00000001 |
| #define clkD6_ctrl_ClkEn_enable 0x1 |
| #define clkD6_ctrl_ClkEn_disable 0x0 |
| #define BA_clkD6_ctrl_ClkPllSel 0x0000 |
| #define B16clkD6_ctrl_ClkPllSel 0x0000 |
| #define LSb32clkD6_ctrl_ClkPllSel 1 |
| #define LSb16clkD6_ctrl_ClkPllSel 1 |
| #define bclkD6_ctrl_ClkPllSel 3 |
| #define MSK32clkD6_ctrl_ClkPllSel 0x0000000E |
| #define clkD6_ctrl_ClkPllSel_AVPllB4 0x0 |
| #define clkD6_ctrl_ClkPllSel_AVPllB5 0x1 |
| #define clkD6_ctrl_ClkPllSel_AVPllB6 0x2 |
| #define clkD6_ctrl_ClkPllSel_AVPllB7 0x3 |
| #define clkD6_ctrl_ClkPllSel_SYSPLL 0x4 |
| #define BA_clkD6_ctrl_ClkPllSwitch 0x0000 |
| #define B16clkD6_ctrl_ClkPllSwitch 0x0000 |
| #define LSb32clkD6_ctrl_ClkPllSwitch 4 |
| #define LSb16clkD6_ctrl_ClkPllSwitch 4 |
| #define bclkD6_ctrl_ClkPllSwitch 1 |
| #define MSK32clkD6_ctrl_ClkPllSwitch 0x00000010 |
| #define clkD6_ctrl_ClkPllSwitch_SYSPLL 0x0 |
| #define clkD6_ctrl_ClkPllSwitch_AVPLL 0x1 |
| #define BA_clkD6_ctrl_ClkSwitch 0x0000 |
| #define B16clkD6_ctrl_ClkSwitch 0x0000 |
| #define LSb32clkD6_ctrl_ClkSwitch 5 |
| #define LSb16clkD6_ctrl_ClkSwitch 5 |
| #define bclkD6_ctrl_ClkSwitch 1 |
| #define MSK32clkD6_ctrl_ClkSwitch 0x00000020 |
| #define clkD6_ctrl_ClkSwitch_SrcClk 0x0 |
| #define clkD6_ctrl_ClkSwitch_DivClk 0x1 |
| #define BA_clkD6_ctrl_ClkD3Switch 0x0000 |
| #define B16clkD6_ctrl_ClkD3Switch 0x0000 |
| #define LSb32clkD6_ctrl_ClkD3Switch 6 |
| #define LSb16clkD6_ctrl_ClkD3Switch 6 |
| #define bclkD6_ctrl_ClkD3Switch 1 |
| #define MSK32clkD6_ctrl_ClkD3Switch 0x00000040 |
| #define clkD6_ctrl_ClkD3Switch_NonDiv3Clk 0x0 |
| #define clkD6_ctrl_ClkD3Switch_Div3Clk 0x1 |
| #define BA_clkD6_ctrl_ClkSel 0x0000 |
| #define B16clkD6_ctrl_ClkSel 0x0000 |
| #define LSb32clkD6_ctrl_ClkSel 7 |
| #define LSb16clkD6_ctrl_ClkSel 7 |
| #define bclkD6_ctrl_ClkSel 3 |
| #define MSK32clkD6_ctrl_ClkSel 0x00000380 |
| #define clkD6_ctrl_ClkSel_d2 0x1 |
| #define clkD6_ctrl_ClkSel_d4 0x2 |
| #define clkD6_ctrl_ClkSel_d6 0x3 |
| #define clkD6_ctrl_ClkSel_d8 0x4 |
| #define clkD6_ctrl_ClkSel_d12 0x5 |
| #define RA_clkD8_ctrl 0x0000 |
| #define BA_clkD8_ctrl_ClkEn 0x0000 |
| #define B16clkD8_ctrl_ClkEn 0x0000 |
| #define LSb32clkD8_ctrl_ClkEn 0 |
| #define LSb16clkD8_ctrl_ClkEn 0 |
| #define bclkD8_ctrl_ClkEn 1 |
| #define MSK32clkD8_ctrl_ClkEn 0x00000001 |
| #define clkD8_ctrl_ClkEn_enable 0x1 |
| #define clkD8_ctrl_ClkEn_disable 0x0 |
| #define BA_clkD8_ctrl_ClkPllSel 0x0000 |
| #define B16clkD8_ctrl_ClkPllSel 0x0000 |
| #define LSb32clkD8_ctrl_ClkPllSel 1 |
| #define LSb16clkD8_ctrl_ClkPllSel 1 |
| #define bclkD8_ctrl_ClkPllSel 3 |
| #define MSK32clkD8_ctrl_ClkPllSel 0x0000000E |
| #define clkD8_ctrl_ClkPllSel_AVPllB4 0x0 |
| #define clkD8_ctrl_ClkPllSel_AVPllB5 0x1 |
| #define clkD8_ctrl_ClkPllSel_AVPllB6 0x2 |
| #define clkD8_ctrl_ClkPllSel_AVPllB7 0x3 |
| #define clkD8_ctrl_ClkPllSel_SYSPLL 0x4 |
| #define BA_clkD8_ctrl_ClkPllSwitch 0x0000 |
| #define B16clkD8_ctrl_ClkPllSwitch 0x0000 |
| #define LSb32clkD8_ctrl_ClkPllSwitch 4 |
| #define LSb16clkD8_ctrl_ClkPllSwitch 4 |
| #define bclkD8_ctrl_ClkPllSwitch 1 |
| #define MSK32clkD8_ctrl_ClkPllSwitch 0x00000010 |
| #define clkD8_ctrl_ClkPllSwitch_SYSPLL 0x0 |
| #define clkD8_ctrl_ClkPllSwitch_AVPLL 0x1 |
| #define BA_clkD8_ctrl_ClkSwitch 0x0000 |
| #define B16clkD8_ctrl_ClkSwitch 0x0000 |
| #define LSb32clkD8_ctrl_ClkSwitch 5 |
| #define LSb16clkD8_ctrl_ClkSwitch 5 |
| #define bclkD8_ctrl_ClkSwitch 1 |
| #define MSK32clkD8_ctrl_ClkSwitch 0x00000020 |
| #define clkD8_ctrl_ClkSwitch_SrcClk 0x0 |
| #define clkD8_ctrl_ClkSwitch_DivClk 0x1 |
| #define BA_clkD8_ctrl_ClkD3Switch 0x0000 |
| #define B16clkD8_ctrl_ClkD3Switch 0x0000 |
| #define LSb32clkD8_ctrl_ClkD3Switch 6 |
| #define LSb16clkD8_ctrl_ClkD3Switch 6 |
| #define bclkD8_ctrl_ClkD3Switch 1 |
| #define MSK32clkD8_ctrl_ClkD3Switch 0x00000040 |
| #define clkD8_ctrl_ClkD3Switch_NonDiv3Clk 0x0 |
| #define clkD8_ctrl_ClkD3Switch_Div3Clk 0x1 |
| #define BA_clkD8_ctrl_ClkSel 0x0000 |
| #define B16clkD8_ctrl_ClkSel 0x0000 |
| #define LSb32clkD8_ctrl_ClkSel 7 |
| #define LSb16clkD8_ctrl_ClkSel 7 |
| #define bclkD8_ctrl_ClkSel 3 |
| #define MSK32clkD8_ctrl_ClkSel 0x00000380 |
| #define clkD8_ctrl_ClkSel_d2 0x1 |
| #define clkD8_ctrl_ClkSel_d4 0x2 |
| #define clkD8_ctrl_ClkSel_d6 0x3 |
| #define clkD8_ctrl_ClkSel_d8 0x4 |
| #define clkD8_ctrl_ClkSel_d12 0x5 |
| #define RA_droCount_result 0x0000 |
| #define BA_droCount_result_value 0x0000 |
| #define B16droCount_result_value 0x0000 |
| #define LSb32droCount_result_value 0 |
| #define LSb16droCount_result_value 0 |
| #define bdroCount_result_value 16 |
| #define MSK32droCount_result_value 0x0000FFFF |
| #define RA_efuse_ctrl 0x0000 |
| #define BA_efuse_ctrl_PROG_SEQ_CODE 0x0000 |
| #define B16efuse_ctrl_PROG_SEQ_CODE 0x0000 |
| #define LSb32efuse_ctrl_PROG_SEQ_CODE 0 |
| #define LSb16efuse_ctrl_PROG_SEQ_CODE 0 |
| #define befuse_ctrl_PROG_SEQ_CODE 1 |
| #define MSK32efuse_ctrl_PROG_SEQ_CODE 0x00000001 |
| #define BA_efuse_ctrl_PROG_SEQ_CODE_CLK 0x0000 |
| #define B16efuse_ctrl_PROG_SEQ_CODE_CLK 0x0000 |
| #define LSb32efuse_ctrl_PROG_SEQ_CODE_CLK 1 |
| #define LSb16efuse_ctrl_PROG_SEQ_CODE_CLK 1 |
| #define befuse_ctrl_PROG_SEQ_CODE_CLK 1 |
| #define MSK32efuse_ctrl_PROG_SEQ_CODE_CLK 0x00000002 |
| #define BA_efuse_ctrl_SCLK 0x0000 |
| #define B16efuse_ctrl_SCLK 0x0000 |
| #define LSb32efuse_ctrl_SCLK 2 |
| #define LSb16efuse_ctrl_SCLK 2 |
| #define befuse_ctrl_SCLK 1 |
| #define MSK32efuse_ctrl_SCLK 0x00000004 |
| #define BA_efuse_ctrl_PRDT 0x0000 |
| #define B16efuse_ctrl_PRDT 0x0000 |
| #define LSb32efuse_ctrl_PRDT 3 |
| #define LSb16efuse_ctrl_PRDT 3 |
| #define befuse_ctrl_PRDT 1 |
| #define MSK32efuse_ctrl_PRDT 0x00000008 |
| #define BA_efuse_ctrl_POR_B 0x0000 |
| #define B16efuse_ctrl_POR_B 0x0000 |
| #define LSb32efuse_ctrl_POR_B 4 |
| #define LSb16efuse_ctrl_POR_B 4 |
| #define befuse_ctrl_POR_B 1 |
| #define MSK32efuse_ctrl_POR_B 0x00000010 |
| #define BA_efuse_ctrl_CSB 0x0000 |
| #define B16efuse_ctrl_CSB 0x0000 |
| #define LSb32efuse_ctrl_CSB 5 |
| #define LSb16efuse_ctrl_CSB 5 |
| #define befuse_ctrl_CSB 1 |
| #define MSK32efuse_ctrl_CSB 0x00000020 |
| #define BA_efuse_ctrl_PGM 0x0000 |
| #define B16efuse_ctrl_PGM 0x0000 |
| #define LSb32efuse_ctrl_PGM 6 |
| #define LSb16efuse_ctrl_PGM 6 |
| #define befuse_ctrl_PGM 1 |
| #define MSK32efuse_ctrl_PGM 0x00000040 |
| #define BA_efuse_ctrl_WPROT 0x0000 |
| #define B16efuse_ctrl_WPROT 0x0000 |
| #define LSb32efuse_ctrl_WPROT 7 |
| #define LSb16efuse_ctrl_WPROT 7 |
| #define befuse_ctrl_WPROT 1 |
| #define MSK32efuse_ctrl_WPROT 0x00000080 |
| #define BA_efuse_ctrl_TEST 0x0001 |
| #define B16efuse_ctrl_TEST 0x0000 |
| #define LSb32efuse_ctrl_TEST 8 |
| #define LSb16efuse_ctrl_TEST 8 |
| #define befuse_ctrl_TEST 4 |
| #define MSK32efuse_ctrl_TEST 0x00000F00 |
| #define RA_efuse_status_match 0x0004 |
| #define BA_efuse_status_match_MATCH_VALUE 0x0004 |
| #define B16efuse_status_match_MATCH_VALUE 0x0004 |
| #define LSb32efuse_status_match_MATCH_VALUE 0 |
| #define LSb16efuse_status_match_MATCH_VALUE 0 |
| #define befuse_status_match_MATCH_VALUE 1 |
| #define MSK32efuse_status_match_MATCH_VALUE 0x00000001 |
| #define RA_efuse_status_qout 0x0008 |
| #define BA_efuse_status_qout_QOUT_31_0 0x0008 |
| #define B16efuse_status_qout_QOUT_31_0 0x0008 |
| #define LSb32efuse_status_qout_QOUT_31_0 0 |
| #define LSb16efuse_status_qout_QOUT_31_0 0 |
| #define befuse_status_qout_QOUT_31_0 32 |
| #define MSK32efuse_status_qout_QOUT_31_0 0xFFFFFFFF |
| #define RA_efuse_status_qout1 0x000C |
| #define BA_efuse_status_qout_QOUT_63_32 0x000C |
| #define B16efuse_status_qout_QOUT_63_32 0x000C |
| #define LSb32efuse_status_qout_QOUT_63_32 0 |
| #define LSb16efuse_status_qout_QOUT_63_32 0 |
| #define befuse_status_qout_QOUT_63_32 32 |
| #define MSK32efuse_status_qout_QOUT_63_32 0xFFFFFFFF |
| #define RA_efuse_status_qout2 0x0010 |
| #define BA_efuse_status_qout_QOUT_95_64 0x0010 |
| #define B16efuse_status_qout_QOUT_95_64 0x0010 |
| #define LSb32efuse_status_qout_QOUT_95_64 0 |
| #define LSb16efuse_status_qout_QOUT_95_64 0 |
| #define befuse_status_qout_QOUT_95_64 32 |
| #define MSK32efuse_status_qout_QOUT_95_64 0xFFFFFFFF |
| #define RA_efuse_status_qout3 0x0014 |
| #define BA_efuse_status_qout_QOUT_127_96 0x0014 |
| #define B16efuse_status_qout_QOUT_127_96 0x0014 |
| #define LSb32efuse_status_qout_QOUT_127_96 0 |
| #define LSb16efuse_status_qout_QOUT_127_96 0 |
| #define befuse_status_qout_QOUT_127_96 32 |
| #define MSK32efuse_status_qout_QOUT_127_96 0xFFFFFFFF |
| #define RA_efuse_status_qout4 0x0018 |
| #define BA_efuse_status_qout_QOUT_159_128 0x0018 |
| #define B16efuse_status_qout_QOUT_159_128 0x0018 |
| #define LSb32efuse_status_qout_QOUT_159_128 0 |
| #define LSb16efuse_status_qout_QOUT_159_128 0 |
| #define befuse_status_qout_QOUT_159_128 32 |
| #define MSK32efuse_status_qout_QOUT_159_128 0xFFFFFFFF |
| #define RA_efuse_status_qout5 0x001C |
| #define BA_efuse_status_qout_QOUT_191_160 0x001C |
| #define B16efuse_status_qout_QOUT_191_160 0x001C |
| #define LSb32efuse_status_qout_QOUT_191_160 0 |
| #define LSb16efuse_status_qout_QOUT_191_160 0 |
| #define befuse_status_qout_QOUT_191_160 32 |
| #define MSK32efuse_status_qout_QOUT_191_160 0xFFFFFFFF |
| #define RA_efuse_status_qout6 0x0020 |
| #define BA_efuse_status_qout_QOUT_223_192 0x0020 |
| #define B16efuse_status_qout_QOUT_223_192 0x0020 |
| #define LSb32efuse_status_qout_QOUT_223_192 0 |
| #define LSb16efuse_status_qout_QOUT_223_192 0 |
| #define befuse_status_qout_QOUT_223_192 32 |
| #define MSK32efuse_status_qout_QOUT_223_192 0xFFFFFFFF |
| #define RA_efuse_status_qout7 0x0024 |
| #define BA_efuse_status_qout_QOUT_255_224 0x0024 |
| #define B16efuse_status_qout_QOUT_255_224 0x0024 |
| #define LSb32efuse_status_qout_QOUT_255_224 0 |
| #define LSb16efuse_status_qout_QOUT_255_224 0 |
| #define befuse_status_qout_QOUT_255_224 32 |
| #define MSK32efuse_status_qout_QOUT_255_224 0xFFFFFFFF |
| #define RA_efuse_status_qout8 0x0028 |
| #define BA_efuse_status_qout_QOUT_256 0x0028 |
| #define B16efuse_status_qout_QOUT_256 0x0028 |
| #define LSb32efuse_status_qout_QOUT_256 0 |
| #define LSb16efuse_status_qout_QOUT_256 0 |
| #define befuse_status_qout_QOUT_256 1 |
| #define MSK32efuse_status_qout_QOUT_256 0x00000001 |
| #define RA_Gbl_pinMux 0x0000 |
| #define BA_Gbl_pinMux_gp0 0x0000 |
| #define B16Gbl_pinMux_gp0 0x0000 |
| #define LSb32Gbl_pinMux_gp0 0 |
| #define LSb16Gbl_pinMux_gp0 0 |
| #define bGbl_pinMux_gp0 3 |
| #define MSK32Gbl_pinMux_gp0 0x00000007 |
| #define Gbl_pinMux_gp0_MODE_0 0x0 |
| #define Gbl_pinMux_gp0_MODE_1 0x1 |
| #define Gbl_pinMux_gp0_MODE_2 0x2 |
| #define Gbl_pinMux_gp0_MODE_3 0x3 |
| #define BA_Gbl_pinMux_gp1 0x0000 |
| #define B16Gbl_pinMux_gp1 0x0000 |
| #define LSb32Gbl_pinMux_gp1 3 |
| #define LSb16Gbl_pinMux_gp1 3 |
| #define bGbl_pinMux_gp1 3 |
| #define MSK32Gbl_pinMux_gp1 0x00000038 |
| #define Gbl_pinMux_gp1_MODE_0 0x0 |
| #define Gbl_pinMux_gp1_MODE_1 0x1 |
| #define Gbl_pinMux_gp1_MODE_6 0x6 |
| #define Gbl_pinMux_gp1_MODE_7 0x7 |
| #define BA_Gbl_pinMux_gp2 0x0000 |
| #define B16Gbl_pinMux_gp2 0x0000 |
| #define LSb32Gbl_pinMux_gp2 6 |
| #define LSb16Gbl_pinMux_gp2 6 |
| #define bGbl_pinMux_gp2 3 |
| #define MSK32Gbl_pinMux_gp2 0x000001C0 |
| #define Gbl_pinMux_gp2_MODE_0 0x0 |
| #define Gbl_pinMux_gp2_MODE_1 0x1 |
| #define Gbl_pinMux_gp2_MODE_2 0x2 |
| #define Gbl_pinMux_gp2_MODE_3 0x3 |
| #define Gbl_pinMux_gp2_MODE_6 0x6 |
| #define Gbl_pinMux_gp2_MODE_7 0x7 |
| #define BA_Gbl_pinMux_gp3 0x0001 |
| #define B16Gbl_pinMux_gp3 0x0000 |
| #define LSb32Gbl_pinMux_gp3 9 |
| #define LSb16Gbl_pinMux_gp3 9 |
| #define bGbl_pinMux_gp3 3 |
| #define MSK32Gbl_pinMux_gp3 0x00000E00 |
| #define Gbl_pinMux_gp3_MODE_0 0x0 |
| #define Gbl_pinMux_gp3_MODE_1 0x1 |
| #define Gbl_pinMux_gp3_MODE_2 0x2 |
| #define Gbl_pinMux_gp3_MODE_3 0x3 |
| #define Gbl_pinMux_gp3_MODE_4 0x4 |
| #define Gbl_pinMux_gp3_MODE_6 0x6 |
| #define Gbl_pinMux_gp3_MODE_7 0x7 |
| #define BA_Gbl_pinMux_gp4 0x0001 |
| #define B16Gbl_pinMux_gp4 0x0000 |
| #define LSb32Gbl_pinMux_gp4 12 |
| #define LSb16Gbl_pinMux_gp4 12 |
| #define bGbl_pinMux_gp4 3 |
| #define MSK32Gbl_pinMux_gp4 0x00007000 |
| #define Gbl_pinMux_gp4_MODE_0 0x0 |
| #define Gbl_pinMux_gp4_MODE_1 0x1 |
| #define Gbl_pinMux_gp4_MODE_2 0x2 |
| #define Gbl_pinMux_gp4_MODE_3 0x3 |
| #define Gbl_pinMux_gp4_MODE_4 0x4 |
| #define Gbl_pinMux_gp4_MODE_6 0x6 |
| #define Gbl_pinMux_gp4_MODE_7 0x7 |
| #define BA_Gbl_pinMux_gp5 0x0001 |
| #define B16Gbl_pinMux_gp5 0x0000 |
| #define LSb32Gbl_pinMux_gp5 15 |
| #define LSb16Gbl_pinMux_gp5 15 |
| #define bGbl_pinMux_gp5 3 |
| #define MSK32Gbl_pinMux_gp5 0x00038000 |
| #define Gbl_pinMux_gp5_MODE_0 0x0 |
| #define Gbl_pinMux_gp5_MODE_1 0x1 |
| #define Gbl_pinMux_gp5_MODE_2 0x2 |
| #define Gbl_pinMux_gp5_MODE_3 0x3 |
| #define Gbl_pinMux_gp5_MODE_4 0x4 |
| #define Gbl_pinMux_gp5_MODE_6 0x6 |
| #define Gbl_pinMux_gp5_MODE_7 0x7 |
| #define BA_Gbl_pinMux_gp6 0x0002 |
| #define B16Gbl_pinMux_gp6 0x0002 |
| #define LSb32Gbl_pinMux_gp6 18 |
| #define LSb16Gbl_pinMux_gp6 2 |
| #define bGbl_pinMux_gp6 3 |
| #define MSK32Gbl_pinMux_gp6 0x001C0000 |
| #define Gbl_pinMux_gp6_MODE_0 0x0 |
| #define Gbl_pinMux_gp6_MODE_1 0x1 |
| #define BA_Gbl_pinMux_gp7 0x0002 |
| #define B16Gbl_pinMux_gp7 0x0002 |
| #define LSb32Gbl_pinMux_gp7 21 |
| #define LSb16Gbl_pinMux_gp7 5 |
| #define bGbl_pinMux_gp7 3 |
| #define MSK32Gbl_pinMux_gp7 0x00E00000 |
| #define Gbl_pinMux_gp7_MODE_0 0x0 |
| #define Gbl_pinMux_gp7_MODE_1 0x1 |
| #define Gbl_pinMux_gp7_MODE_2 0x2 |
| #define BA_Gbl_pinMux_gp8 0x0003 |
| #define B16Gbl_pinMux_gp8 0x0002 |
| #define LSb32Gbl_pinMux_gp8 24 |
| #define LSb16Gbl_pinMux_gp8 8 |
| #define bGbl_pinMux_gp8 3 |
| #define MSK32Gbl_pinMux_gp8 0x07000000 |
| #define Gbl_pinMux_gp8_MODE_0 0x0 |
| #define Gbl_pinMux_gp8_MODE_1 0x1 |
| #define BA_Gbl_pinMux_gp9 0x0003 |
| #define B16Gbl_pinMux_gp9 0x0002 |
| #define LSb32Gbl_pinMux_gp9 27 |
| #define LSb16Gbl_pinMux_gp9 11 |
| #define bGbl_pinMux_gp9 3 |
| #define MSK32Gbl_pinMux_gp9 0x38000000 |
| #define Gbl_pinMux_gp9_MODE_0 0x0 |
| #define Gbl_pinMux_gp9_MODE_1 0x1 |
| #define Gbl_pinMux_gp9_MODE_3 0x3 |
| #define BA_Gbl_pinMux_gp10 0x0003 |
| #define B16Gbl_pinMux_gp10 0x0002 |
| #define LSb32Gbl_pinMux_gp10 30 |
| #define LSb16Gbl_pinMux_gp10 14 |
| #define bGbl_pinMux_gp10 2 |
| #define MSK32Gbl_pinMux_gp10 0xC0000000 |
| #define Gbl_pinMux_gp10_MODE_0 0x0 |
| #define Gbl_pinMux_gp10_MODE_1 0x1 |
| #define RA_Gbl_pinMux1 0x0004 |
| #define BA_Gbl_pinMux_gp11 0x0004 |
| #define B16Gbl_pinMux_gp11 0x0004 |
| #define LSb32Gbl_pinMux_gp11 0 |
| #define LSb16Gbl_pinMux_gp11 0 |
| #define bGbl_pinMux_gp11 2 |
| #define MSK32Gbl_pinMux_gp11 0x00000003 |
| #define Gbl_pinMux_gp11_MODE_0 0x0 |
| #define Gbl_pinMux_gp11_MODE_1 0x1 |
| #define BA_Gbl_pinMux_gp12 0x0004 |
| #define B16Gbl_pinMux_gp12 0x0004 |
| #define LSb32Gbl_pinMux_gp12 2 |
| #define LSb16Gbl_pinMux_gp12 2 |
| #define bGbl_pinMux_gp12 3 |
| #define MSK32Gbl_pinMux_gp12 0x0000001C |
| #define Gbl_pinMux_gp12_MODE_0 0x0 |
| #define Gbl_pinMux_gp12_MODE_1 0x1 |
| #define BA_Gbl_pinMux_gp13 0x0004 |
| #define B16Gbl_pinMux_gp13 0x0004 |
| #define LSb32Gbl_pinMux_gp13 5 |
| #define LSb16Gbl_pinMux_gp13 5 |
| #define bGbl_pinMux_gp13 3 |
| #define MSK32Gbl_pinMux_gp13 0x000000E0 |
| #define Gbl_pinMux_gp13_MODE_0 0x0 |
| #define Gbl_pinMux_gp13_MODE_1 0x1 |
| #define Gbl_pinMux_gp13_MODE_2 0x2 |
| #define BA_Gbl_pinMux_gp14 0x0005 |
| #define B16Gbl_pinMux_gp14 0x0004 |
| #define LSb32Gbl_pinMux_gp14 8 |
| #define LSb16Gbl_pinMux_gp14 8 |
| #define bGbl_pinMux_gp14 1 |
| #define MSK32Gbl_pinMux_gp14 0x00000100 |
| #define Gbl_pinMux_gp14_MODE_0 0x0 |
| #define Gbl_pinMux_gp14_MODE_1 0x1 |
| #define BA_Gbl_pinMux_gp15 0x0005 |
| #define B16Gbl_pinMux_gp15 0x0004 |
| #define LSb32Gbl_pinMux_gp15 9 |
| #define LSb16Gbl_pinMux_gp15 9 |
| #define bGbl_pinMux_gp15 3 |
| #define MSK32Gbl_pinMux_gp15 0x00000E00 |
| #define Gbl_pinMux_gp15_MODE_0 0x0 |
| #define Gbl_pinMux_gp15_MODE_1 0x1 |
| #define BA_Gbl_pinMux_gp16 0x0005 |
| #define B16Gbl_pinMux_gp16 0x0004 |
| #define LSb32Gbl_pinMux_gp16 12 |
| #define LSb16Gbl_pinMux_gp16 12 |
| #define bGbl_pinMux_gp16 3 |
| #define MSK32Gbl_pinMux_gp16 0x00007000 |
| #define Gbl_pinMux_gp16_MODE_0 0x0 |
| #define Gbl_pinMux_gp16_MODE_1 0x1 |
| #define Gbl_pinMux_gp16_MODE_2 0x2 |
| #define Gbl_pinMux_gp16_MODE_4 0x4 |
| #define BA_Gbl_pinMux_gp17 0x0005 |
| #define B16Gbl_pinMux_gp17 0x0004 |
| #define LSb32Gbl_pinMux_gp17 15 |
| #define LSb16Gbl_pinMux_gp17 15 |
| #define bGbl_pinMux_gp17 3 |
| #define MSK32Gbl_pinMux_gp17 0x00038000 |
| #define Gbl_pinMux_gp17_MODE_0 0x0 |
| #define Gbl_pinMux_gp17_MODE_1 0x1 |
| #define Gbl_pinMux_gp17_MODE_2 0x2 |
| #define Gbl_pinMux_gp17_MODE_3 0x3 |
| #define Gbl_pinMux_gp17_MODE_4 0x4 |
| #define Gbl_pinMux_gp17_MODE_5 0x5 |
| #define BA_Gbl_pinMux_gp18 0x0006 |
| #define B16Gbl_pinMux_gp18 0x0006 |
| #define LSb32Gbl_pinMux_gp18 18 |
| #define LSb16Gbl_pinMux_gp18 2 |
| #define bGbl_pinMux_gp18 2 |
| #define MSK32Gbl_pinMux_gp18 0x000C0000 |
| #define Gbl_pinMux_gp18_MODE_0 0x0 |
| #define Gbl_pinMux_gp18_MODE_1 0x1 |
| #define Gbl_pinMux_gp18_MODE_2 0x2 |
| #define Gbl_pinMux_gp18_MODE_3 0x3 |
| #define BA_Gbl_pinMux_gp19 0x0006 |
| #define B16Gbl_pinMux_gp19 0x0006 |
| #define LSb32Gbl_pinMux_gp19 20 |
| #define LSb16Gbl_pinMux_gp19 4 |
| #define bGbl_pinMux_gp19 2 |
| #define MSK32Gbl_pinMux_gp19 0x00300000 |
| #define Gbl_pinMux_gp19_MODE_0 0x0 |
| #define Gbl_pinMux_gp19_MODE_1 0x1 |
| #define Gbl_pinMux_gp19_MODE_2 0x2 |
| #define Gbl_pinMux_gp19_MODE_3 0x3 |
| #define BA_Gbl_pinMux_gp20 0x0006 |
| #define B16Gbl_pinMux_gp20 0x0006 |
| #define LSb32Gbl_pinMux_gp20 22 |
| #define LSb16Gbl_pinMux_gp20 6 |
| #define bGbl_pinMux_gp20 2 |
| #define MSK32Gbl_pinMux_gp20 0x00C00000 |
| #define Gbl_pinMux_gp20_MODE_0 0x0 |
| #define Gbl_pinMux_gp20_MODE_1 0x1 |
| #define Gbl_pinMux_gp20_MODE_2 0x2 |
| #define BA_Gbl_pinMux_gp21 0x0007 |
| #define B16Gbl_pinMux_gp21 0x0006 |
| #define LSb32Gbl_pinMux_gp21 24 |
| #define LSb16Gbl_pinMux_gp21 8 |
| #define bGbl_pinMux_gp21 3 |
| #define MSK32Gbl_pinMux_gp21 0x07000000 |
| #define Gbl_pinMux_gp21_MODE_0 0x0 |
| #define Gbl_pinMux_gp21_MODE_1 0x1 |
| #define Gbl_pinMux_gp21_MODE_2 0x2 |
| #define Gbl_pinMux_gp21_MODE_3 0x3 |
| #define Gbl_pinMux_gp21_MODE_7 0x7 |
| #define BA_Gbl_pinMux_gp22 0x0007 |
| #define B16Gbl_pinMux_gp22 0x0006 |
| #define LSb32Gbl_pinMux_gp22 27 |
| #define LSb16Gbl_pinMux_gp22 11 |
| #define bGbl_pinMux_gp22 3 |
| #define MSK32Gbl_pinMux_gp22 0x38000000 |
| #define Gbl_pinMux_gp22_MODE_0 0x0 |
| #define Gbl_pinMux_gp22_MODE_1 0x1 |
| #define Gbl_pinMux_gp22_MODE_2 0x2 |
| #define Gbl_pinMux_gp22_MODE_3 0x3 |
| #define Gbl_pinMux_gp22_MODE_4 0x4 |
| #define RA_Gbl_pinMux2 0x0008 |
| #define BA_Gbl_pinMux_gp23 0x0008 |
| #define B16Gbl_pinMux_gp23 0x0008 |
| #define LSb32Gbl_pinMux_gp23 0 |
| #define LSb16Gbl_pinMux_gp23 0 |
| #define bGbl_pinMux_gp23 3 |
| #define MSK32Gbl_pinMux_gp23 0x00000007 |
| #define Gbl_pinMux_gp23_MODE_0 0x0 |
| #define Gbl_pinMux_gp23_MODE_1 0x1 |
| #define Gbl_pinMux_gp23_MODE_2 0x2 |
| #define Gbl_pinMux_gp23_MODE_3 0x3 |
| #define Gbl_pinMux_gp23_MODE_4 0x4 |
| #define Gbl_pinMux_gp23_MODE_7 0x7 |
| #define BA_Gbl_pinMux_gp24 0x0008 |
| #define B16Gbl_pinMux_gp24 0x0008 |
| #define LSb32Gbl_pinMux_gp24 3 |
| #define LSb16Gbl_pinMux_gp24 3 |
| #define bGbl_pinMux_gp24 2 |
| #define MSK32Gbl_pinMux_gp24 0x00000018 |
| #define Gbl_pinMux_gp24_MODE_0 0x0 |
| #define Gbl_pinMux_gp24_MODE_1 0x1 |
| #define Gbl_pinMux_gp24_MODE_2 0x2 |
| #define BA_Gbl_pinMux_gp25 0x0008 |
| #define B16Gbl_pinMux_gp25 0x0008 |
| #define LSb32Gbl_pinMux_gp25 5 |
| #define LSb16Gbl_pinMux_gp25 5 |
| #define bGbl_pinMux_gp25 2 |
| #define MSK32Gbl_pinMux_gp25 0x00000060 |
| #define Gbl_pinMux_gp25_MODE_0 0x0 |
| #define Gbl_pinMux_gp25_MODE_1 0x1 |
| #define Gbl_pinMux_gp25_MODE_2 0x2 |
| #define Gbl_pinMux_gp25_MODE_3 0x3 |
| #define BA_Gbl_pinMux_gp26 0x0008 |
| #define B16Gbl_pinMux_gp26 0x0008 |
| #define LSb32Gbl_pinMux_gp26 7 |
| #define LSb16Gbl_pinMux_gp26 7 |
| #define bGbl_pinMux_gp26 1 |
| #define MSK32Gbl_pinMux_gp26 0x00000080 |
| #define Gbl_pinMux_gp26_MODE_0 0x0 |
| #define Gbl_pinMux_gp26_MODE_1 0x1 |
| #define BA_Gbl_pinMux_gp27 0x0009 |
| #define B16Gbl_pinMux_gp27 0x0008 |
| #define LSb32Gbl_pinMux_gp27 8 |
| #define LSb16Gbl_pinMux_gp27 8 |
| #define bGbl_pinMux_gp27 2 |
| #define MSK32Gbl_pinMux_gp27 0x00000300 |
| #define Gbl_pinMux_gp27_MODE_0 0x0 |
| #define Gbl_pinMux_gp27_MODE_1 0x1 |
| #define Gbl_pinMux_gp27_MODE_3 0x3 |
| #define BA_Gbl_pinMux_gp28 0x0009 |
| #define B16Gbl_pinMux_gp28 0x0008 |
| #define LSb32Gbl_pinMux_gp28 10 |
| #define LSb16Gbl_pinMux_gp28 10 |
| #define bGbl_pinMux_gp28 3 |
| #define MSK32Gbl_pinMux_gp28 0x00001C00 |
| #define Gbl_pinMux_gp28_MODE_0 0x0 |
| #define Gbl_pinMux_gp28_MODE_1 0x1 |
| #define Gbl_pinMux_gp28_MODE_2 0x2 |
| #define Gbl_pinMux_gp28_MODE_5 0x5 |
| #define BA_Gbl_pinMux_gp29 0x0009 |
| #define B16Gbl_pinMux_gp29 0x0008 |
| #define LSb32Gbl_pinMux_gp29 13 |
| #define LSb16Gbl_pinMux_gp29 13 |
| #define bGbl_pinMux_gp29 3 |
| #define MSK32Gbl_pinMux_gp29 0x0000E000 |
| #define Gbl_pinMux_gp29_MODE_0 0x0 |
| #define Gbl_pinMux_gp29_MODE_2 0x2 |
| #define Gbl_pinMux_gp29_MODE_5 0x5 |
| #define Gbl_pinMux_gp29_MODE_6 0x6 |
| #define RA_Gbl_bootStrap 0x000C |
| #define BA_Gbl_bootStrap_softwareStrap 0x000C |
| #define B16Gbl_bootStrap_softwareStrap 0x000C |
| #define LSb32Gbl_bootStrap_softwareStrap 0 |
| #define LSb16Gbl_bootStrap_softwareStrap 0 |
| #define bGbl_bootStrap_softwareStrap 7 |
| #define MSK32Gbl_bootStrap_softwareStrap 0x0000007F |
| #define BA_Gbl_bootStrap_bootSrc 0x000C |
| #define B16Gbl_bootStrap_bootSrc 0x000C |
| #define LSb32Gbl_bootStrap_bootSrc 7 |
| #define LSb16Gbl_bootStrap_bootSrc 7 |
| #define bGbl_bootStrap_bootSrc 2 |
| #define MSK32Gbl_bootStrap_bootSrc 0x00000180 |
| #define BA_Gbl_bootStrap_sysPllByps 0x000D |
| #define B16Gbl_bootStrap_sysPllByps 0x000C |
| #define LSb32Gbl_bootStrap_sysPllByps 9 |
| #define LSb16Gbl_bootStrap_sysPllByps 9 |
| #define bGbl_bootStrap_sysPllByps 1 |
| #define MSK32Gbl_bootStrap_sysPllByps 0x00000200 |
| #define Gbl_bootStrap_sysPllByps_PLL_OUT 0x0 |
| #define Gbl_bootStrap_sysPllByps_BYPS 0x1 |
| #define BA_Gbl_bootStrap_memPllByps 0x000D |
| #define B16Gbl_bootStrap_memPllByps 0x000C |
| #define LSb32Gbl_bootStrap_memPllByps 10 |
| #define LSb16Gbl_bootStrap_memPllByps 10 |
| #define bGbl_bootStrap_memPllByps 1 |
| #define MSK32Gbl_bootStrap_memPllByps 0x00000400 |
| #define Gbl_bootStrap_memPllByps_PLL_OUT 0x0 |
| #define Gbl_bootStrap_memPllByps_BYPS 0x1 |
| #define BA_Gbl_bootStrap_cpuPllByps 0x000D |
| #define B16Gbl_bootStrap_cpuPllByps 0x000C |
| #define LSb32Gbl_bootStrap_cpuPllByps 11 |
| #define LSb16Gbl_bootStrap_cpuPllByps 11 |
| #define bGbl_bootStrap_cpuPllByps 1 |
| #define MSK32Gbl_bootStrap_cpuPllByps 0x00000800 |
| #define Gbl_bootStrap_cpuPllByps_PLL_OUT 0x0 |
| #define Gbl_bootStrap_cpuPllByps_BYPS 0x1 |
| #define BA_Gbl_bootStrap_pllPwrDown 0x000D |
| #define B16Gbl_bootStrap_pllPwrDown 0x000C |
| #define LSb32Gbl_bootStrap_pllPwrDown 12 |
| #define LSb16Gbl_bootStrap_pllPwrDown 12 |
| #define bGbl_bootStrap_pllPwrDown 1 |
| #define MSK32Gbl_bootStrap_pllPwrDown 0x00001000 |
| #define Gbl_bootStrap_pllPwrDown_POWER_UP 0x0 |
| #define Gbl_bootStrap_pllPwrDown_POWER_DOWN 0x1 |
| #define BA_Gbl_bootStrap_refClk12P5M 0x000D |
| #define B16Gbl_bootStrap_refClk12P5M 0x000C |
| #define LSb32Gbl_bootStrap_refClk12P5M 13 |
| #define LSb16Gbl_bootStrap_refClk12P5M 13 |
| #define bGbl_bootStrap_refClk12P5M 1 |
| #define MSK32Gbl_bootStrap_refClk12P5M 0x00002000 |
| #define Gbl_bootStrap_refClk12P5M_REFCLK25M 0x0 |
| #define Gbl_bootStrap_refClk12P5M_REFCLK12P5M 0x1 |
| #define BA_Gbl_bootStrap_socJtagFromSM 0x000D |
| #define B16Gbl_bootStrap_socJtagFromSM 0x000C |
| #define LSb32Gbl_bootStrap_socJtagFromSM 14 |
| #define LSb16Gbl_bootStrap_socJtagFromSM 14 |
| #define bGbl_bootStrap_socJtagFromSM 1 |
| #define MSK32Gbl_bootStrap_socJtagFromSM 0x00004000 |
| #define Gbl_bootStrap_socJtagFromSM_fromPinMux 0x0 |
| #define Gbl_bootStrap_socJtagFromSM_fromSM 0x1 |
| #define BA_Gbl_bootStrap_nandV18Enable 0x000D |
| #define B16Gbl_bootStrap_nandV18Enable 0x000C |
| #define LSb32Gbl_bootStrap_nandV18Enable 15 |
| #define LSb16Gbl_bootStrap_nandV18Enable 15 |
| #define bGbl_bootStrap_nandV18Enable 1 |
| #define MSK32Gbl_bootStrap_nandV18Enable 0x00008000 |
| #define Gbl_bootStrap_nandV18Enable_V1R8 0x1 |
| #define Gbl_bootStrap_nandV18Enable_V3R3 0x0 |
| #define BA_Gbl_bootStrap_spi1V18Enable 0x000E |
| #define B16Gbl_bootStrap_spi1V18Enable 0x000E |
| #define LSb32Gbl_bootStrap_spi1V18Enable 16 |
| #define LSb16Gbl_bootStrap_spi1V18Enable 0 |
| #define bGbl_bootStrap_spi1V18Enable 1 |
| #define MSK32Gbl_bootStrap_spi1V18Enable 0x00010000 |
| #define Gbl_bootStrap_spi1V18Enable_V1R8 0x0 |
| #define Gbl_bootStrap_spi1V18Enable_V3R3 0x1 |
| #define BA_Gbl_bootStrap_nandV25Enable 0x000E |
| #define B16Gbl_bootStrap_nandV25Enable 0x000E |
| #define LSb32Gbl_bootStrap_nandV25Enable 17 |
| #define LSb16Gbl_bootStrap_nandV25Enable 1 |
| #define bGbl_bootStrap_nandV25Enable 1 |
| #define MSK32Gbl_bootStrap_nandV25Enable 0x00020000 |
| #define BA_Gbl_bootStrap_spi1V25Enable 0x000E |
| #define B16Gbl_bootStrap_spi1V25Enable 0x000E |
| #define LSb32Gbl_bootStrap_spi1V25Enable 18 |
| #define LSb16Gbl_bootStrap_spi1V25Enable 2 |
| #define bGbl_bootStrap_spi1V25Enable 1 |
| #define MSK32Gbl_bootStrap_spi1V25Enable 0x00040000 |
| #define BA_Gbl_bootStrap_ENG_EN 0x000E |
| #define B16Gbl_bootStrap_ENG_EN 0x000E |
| #define LSb32Gbl_bootStrap_ENG_EN 19 |
| #define LSb16Gbl_bootStrap_ENG_EN 3 |
| #define bGbl_bootStrap_ENG_EN 1 |
| #define MSK32Gbl_bootStrap_ENG_EN 0x00080000 |
| #define Gbl_bootStrap_ENG_EN_PRODUCTION_MODE 0x0 |
| #define Gbl_bootStrap_ENG_EN_DEVELOPE_MODE 0x1 |
| #define RA_Gbl_anaGrpCtl 0x0010 |
| #define BA_Gbl_anaGrpCtl_anaGrpPu 0x0010 |
| #define B16Gbl_anaGrpCtl_anaGrpPu 0x0010 |
| #define LSb32Gbl_anaGrpCtl_anaGrpPu 0 |
| #define LSb16Gbl_anaGrpCtl_anaGrpPu 0 |
| #define bGbl_anaGrpCtl_anaGrpPu 1 |
| #define MSK32Gbl_anaGrpCtl_anaGrpPu 0x00000001 |
| #define BA_Gbl_anaGrpCtl_anaGrpBgSel 0x0010 |
| #define B16Gbl_anaGrpCtl_anaGrpBgSel 0x0010 |
| #define LSb32Gbl_anaGrpCtl_anaGrpBgSel 1 |
| #define LSb16Gbl_anaGrpCtl_anaGrpBgSel 1 |
| #define bGbl_anaGrpCtl_anaGrpBgSel 2 |
| #define MSK32Gbl_anaGrpCtl_anaGrpBgSel 0x00000006 |
| #define BA_Gbl_anaGrpCtl_anaGrpPuXtl 0x0010 |
| #define B16Gbl_anaGrpCtl_anaGrpPuXtl 0x0010 |
| #define LSb32Gbl_anaGrpCtl_anaGrpPuXtl 3 |
| #define LSb16Gbl_anaGrpCtl_anaGrpPuXtl 3 |
| #define bGbl_anaGrpCtl_anaGrpPuXtl 1 |
| #define MSK32Gbl_anaGrpCtl_anaGrpPuXtl 0x00000008 |
| #define BA_Gbl_anaGrpCtl_anaGrpGainX2 0x0010 |
| #define B16Gbl_anaGrpCtl_anaGrpGainX2 0x0010 |
| #define LSb32Gbl_anaGrpCtl_anaGrpGainX2 4 |
| #define LSb16Gbl_anaGrpCtl_anaGrpGainX2 4 |
| #define bGbl_anaGrpCtl_anaGrpGainX2 1 |
| #define MSK32Gbl_anaGrpCtl_anaGrpGainX2 0x00000010 |
| #define BA_Gbl_anaGrpCtl_anaGrpSelClkDigDiv1 0x0010 |
| #define B16Gbl_anaGrpCtl_anaGrpSelClkDigDiv1 0x0010 |
| #define LSb32Gbl_anaGrpCtl_anaGrpSelClkDigDiv1 5 |
| #define LSb16Gbl_anaGrpCtl_anaGrpSelClkDigDiv1 5 |
| #define bGbl_anaGrpCtl_anaGrpSelClkDigDiv1 2 |
| #define MSK32Gbl_anaGrpCtl_anaGrpSelClkDigDiv1 0x00000060 |
| #define BA_Gbl_anaGrpCtl_anaGrpSelClkDigDiv2 0x0010 |
| #define B16Gbl_anaGrpCtl_anaGrpSelClkDigDiv2 0x0010 |
| #define LSb32Gbl_anaGrpCtl_anaGrpSelClkDigDiv2 7 |
| #define LSb16Gbl_anaGrpCtl_anaGrpSelClkDigDiv2 7 |
| #define bGbl_anaGrpCtl_anaGrpSelClkDigDiv2 2 |
| #define MSK32Gbl_anaGrpCtl_anaGrpSelClkDigDiv2 0x00000180 |
| #define BA_Gbl_anaGrpCtl_anaGrpSelClkDigDiv3 0x0011 |
| #define B16Gbl_anaGrpCtl_anaGrpSelClkDigDiv3 0x0010 |
| #define LSb32Gbl_anaGrpCtl_anaGrpSelClkDigDiv3 9 |
| #define LSb16Gbl_anaGrpCtl_anaGrpSelClkDigDiv3 9 |
| #define bGbl_anaGrpCtl_anaGrpSelClkDigDiv3 2 |
| #define MSK32Gbl_anaGrpCtl_anaGrpSelClkDigDiv3 0x00000600 |
| #define BA_Gbl_anaGrpCtl_anaGrpSelClkDigDiv4 0x0011 |
| #define B16Gbl_anaGrpCtl_anaGrpSelClkDigDiv4 0x0010 |
| #define LSb32Gbl_anaGrpCtl_anaGrpSelClkDigDiv4 11 |
| #define LSb16Gbl_anaGrpCtl_anaGrpSelClkDigDiv4 11 |
| #define bGbl_anaGrpCtl_anaGrpSelClkDigDiv4 2 |
| #define MSK32Gbl_anaGrpCtl_anaGrpSelClkDigDiv4 0x00001800 |
| #define BA_Gbl_anaGrpCtl_anaGrpPuOsc 0x0011 |
| #define B16Gbl_anaGrpCtl_anaGrpPuOsc 0x0010 |
| #define LSb32Gbl_anaGrpCtl_anaGrpPuOsc 13 |
| #define LSb16Gbl_anaGrpCtl_anaGrpPuOsc 13 |
| #define bGbl_anaGrpCtl_anaGrpPuOsc 1 |
| #define MSK32Gbl_anaGrpCtl_anaGrpPuOsc 0x00002000 |
| #define BA_Gbl_anaGrpCtl_anaGrpSpeedOsc 0x0011 |
| #define B16Gbl_anaGrpCtl_anaGrpSpeedOsc 0x0010 |
| #define LSb32Gbl_anaGrpCtl_anaGrpSpeedOsc 14 |
| #define LSb16Gbl_anaGrpCtl_anaGrpSpeedOsc 14 |
| #define bGbl_anaGrpCtl_anaGrpSpeedOsc 2 |
| #define MSK32Gbl_anaGrpCtl_anaGrpSpeedOsc 0x0000C000 |
| #define BA_Gbl_anaGrpCtl_anaGrpTestAna 0x0012 |
| #define B16Gbl_anaGrpCtl_anaGrpTestAna 0x0012 |
| #define LSb32Gbl_anaGrpCtl_anaGrpTestAna 16 |
| #define LSb16Gbl_anaGrpCtl_anaGrpTestAna 0 |
| #define bGbl_anaGrpCtl_anaGrpTestAna 4 |
| #define MSK32Gbl_anaGrpCtl_anaGrpTestAna 0x000F0000 |
| #define RA_Gbl_sysPllCtl 0x0014 |
| #define BA_Gbl_sysPllCtl_sysPllPu 0x0014 |
| #define B16Gbl_sysPllCtl_sysPllPu 0x0014 |
| #define LSb32Gbl_sysPllCtl_sysPllPu 0 |
| #define LSb16Gbl_sysPllCtl_sysPllPu 0 |
| #define bGbl_sysPllCtl_sysPllPu 1 |
| #define MSK32Gbl_sysPllCtl_sysPllPu 0x00000001 |
| #define BA_Gbl_sysPllCtl_sysPllRfDiv 0x0014 |
| #define B16Gbl_sysPllCtl_sysPllRfDiv 0x0014 |
| #define LSb32Gbl_sysPllCtl_sysPllRfDiv 1 |
| #define LSb16Gbl_sysPllCtl_sysPllRfDiv 1 |
| #define bGbl_sysPllCtl_sysPllRfDiv 5 |
| #define MSK32Gbl_sysPllCtl_sysPllRfDiv 0x0000003E |
| #define BA_Gbl_sysPllCtl_sysPllFbDiv 0x0014 |
| #define B16Gbl_sysPllCtl_sysPllFbDiv 0x0014 |
| #define LSb32Gbl_sysPllCtl_sysPllFbDiv 6 |
| #define LSb16Gbl_sysPllCtl_sysPllFbDiv 6 |
| #define bGbl_sysPllCtl_sysPllFbDiv 9 |
| #define MSK32Gbl_sysPllCtl_sysPllFbDiv 0x00007FC0 |
| #define BA_Gbl_sysPllCtl_sysPllVddm 0x0015 |
| #define B16Gbl_sysPllCtl_sysPllVddm 0x0014 |
| #define LSb32Gbl_sysPllCtl_sysPllVddm 15 |
| #define LSb16Gbl_sysPllCtl_sysPllVddm 15 |
| #define bGbl_sysPllCtl_sysPllVddm 2 |
| #define MSK32Gbl_sysPllCtl_sysPllVddm 0x00018000 |
| #define Gbl_sysPllCtl_sysPllVddm_1R40v 0x0 |
| #define Gbl_sysPllCtl_sysPllVddm_1R45v 0x1 |
| #define Gbl_sysPllCtl_sysPllVddm_1R50v 0x2 |
| #define Gbl_sysPllCtl_sysPllVddm_1R55v 0x3 |
| #define BA_Gbl_sysPllCtl_sysPllVddl 0x0016 |
| #define B16Gbl_sysPllCtl_sysPllVddl 0x0016 |
| #define LSb32Gbl_sysPllCtl_sysPllVddl 17 |
| #define LSb16Gbl_sysPllCtl_sysPllVddl 1 |
| #define bGbl_sysPllCtl_sysPllVddl 4 |
| #define MSK32Gbl_sysPllCtl_sysPllVddl 0x001E0000 |
| #define Gbl_sysPllCtl_sysPllVddl_0R78v 0x1 |
| #define Gbl_sysPllCtl_sysPllVddl_0R82v 0x2 |
| #define Gbl_sysPllCtl_sysPllVddl_0R86v 0x3 |
| #define Gbl_sysPllCtl_sysPllVddl_0R90v 0x4 |
| #define Gbl_sysPllCtl_sysPllVddl_0R94v 0x5 |
| #define Gbl_sysPllCtl_sysPllVddl_0R98v 0x6 |
| #define Gbl_sysPllCtl_sysPllVddl_1R02v 0x7 |
| #define Gbl_sysPllCtl_sysPllVddl_1R06v 0x8 |
| #define Gbl_sysPllCtl_sysPllVddl_1R10v 0x9 |
| #define Gbl_sysPllCtl_sysPllVddl_1R14v 0xA |
| #define Gbl_sysPllCtl_sysPllVddl_1R16v 0xB |
| #define BA_Gbl_sysPllCtl_sysPllVregIVRef 0x0016 |
| #define B16Gbl_sysPllCtl_sysPllVregIVRef 0x0016 |
| #define LSb32Gbl_sysPllCtl_sysPllVregIVRef 21 |
| #define LSb16Gbl_sysPllCtl_sysPllVregIVRef 5 |
| #define bGbl_sysPllCtl_sysPllVregIVRef 2 |
| #define MSK32Gbl_sysPllCtl_sysPllVregIVRef 0x00600000 |
| #define BA_Gbl_sysPllCtl_sysPllIcp 0x0016 |
| #define B16Gbl_sysPllCtl_sysPllIcp 0x0016 |
| #define LSb32Gbl_sysPllCtl_sysPllIcp 23 |
| #define LSb16Gbl_sysPllCtl_sysPllIcp 7 |
| #define bGbl_sysPllCtl_sysPllIcp 3 |
| #define MSK32Gbl_sysPllCtl_sysPllIcp 0x03800000 |
| #define Gbl_sysPllCtl_sysPllIcp_2uA 0x0 |
| #define Gbl_sysPllCtl_sysPllIcp_3uA 0x1 |
| #define Gbl_sysPllCtl_sysPllIcp_4uA 0x2 |
| #define Gbl_sysPllCtl_sysPllIcp_5uA 0x3 |
| #define Gbl_sysPllCtl_sysPllIcp_6uA 0x4 |
| #define Gbl_sysPllCtl_sysPllIcp_7uA 0x5 |
| #define Gbl_sysPllCtl_sysPllIcp_8uA 0x6 |
| #define Gbl_sysPllCtl_sysPllIcp_9uA 0x7 |
| #define BA_Gbl_sysPllCtl_sysPllKvco 0x0017 |
| #define B16Gbl_sysPllCtl_sysPllKvco 0x0016 |
| #define LSb32Gbl_sysPllCtl_sysPllKvco 26 |
| #define LSb16Gbl_sysPllCtl_sysPllKvco 10 |
| #define bGbl_sysPllCtl_sysPllKvco 4 |
| #define MSK32Gbl_sysPllCtl_sysPllKvco 0x3C000000 |
| #define Gbl_sysPllCtl_sysPllKvco_1R25Gto1R35G 0x1 |
| #define Gbl_sysPllCtl_sysPllKvco_1R35Gto1R55G 0x2 |
| #define Gbl_sysPllCtl_sysPllKvco_1R55Gto1R75G 0x3 |
| #define Gbl_sysPllCtl_sysPllKvco_1R75Gto1R95G 0x4 |
| #define Gbl_sysPllCtl_sysPllKvco_1R95Gto2R15G 0x5 |
| #define Gbl_sysPllCtl_sysPllKvco_2R15Gto2R4G 0x6 |
| #define Gbl_sysPllCtl_sysPllKvco_2R4Gto2R5G 0x7 |
| #define BA_Gbl_sysPllCtl_sysPllCtune 0x0017 |
| #define B16Gbl_sysPllCtl_sysPllCtune 0x0016 |
| #define LSb32Gbl_sysPllCtl_sysPllCtune 30 |
| #define LSb16Gbl_sysPllCtl_sysPllCtune 14 |
| #define bGbl_sysPllCtl_sysPllCtune 2 |
| #define MSK32Gbl_sysPllCtl_sysPllCtune 0xC0000000 |
| #define RA_Gbl_sysPllCtl1 0x0018 |
| #define BA_Gbl_sysPllCtl_sysPllVcoRng 0x0018 |
| #define B16Gbl_sysPllCtl_sysPllVcoRng 0x0018 |
| #define LSb32Gbl_sysPllCtl_sysPllVcoRng 0 |
| #define LSb16Gbl_sysPllCtl_sysPllVcoRng 0 |
| #define bGbl_sysPllCtl_sysPllVcoRng 3 |
| #define MSK32Gbl_sysPllCtl_sysPllVcoRng 0x00000007 |
| #define BA_Gbl_sysPllCtl_sysPllVcoDivSelDiff 0x0018 |
| #define B16Gbl_sysPllCtl_sysPllVcoDivSelDiff 0x0018 |
| #define LSb32Gbl_sysPllCtl_sysPllVcoDivSelDiff 3 |
| #define LSb16Gbl_sysPllCtl_sysPllVcoDivSelDiff 3 |
| #define bGbl_sysPllCtl_sysPllVcoDivSelDiff 4 |
| #define MSK32Gbl_sysPllCtl_sysPllVcoDivSelDiff 0x00000078 |
| #define BA_Gbl_sysPllCtl_sysPllVcoDivSelSe 0x0018 |
| #define B16Gbl_sysPllCtl_sysPllVcoDivSelSe 0x0018 |
| #define LSb32Gbl_sysPllCtl_sysPllVcoDivSelSe 7 |
| #define LSb16Gbl_sysPllCtl_sysPllVcoDivSelSe 7 |
| #define bGbl_sysPllCtl_sysPllVcoDivSelSe 4 |
| #define MSK32Gbl_sysPllCtl_sysPllVcoDivSelSe 0x00000780 |
| #define BA_Gbl_sysPllCtl_sysPllDiffClkEn 0x0019 |
| #define B16Gbl_sysPllCtl_sysPllDiffClkEn 0x0018 |
| #define LSb32Gbl_sysPllCtl_sysPllDiffClkEn 11 |
| #define LSb16Gbl_sysPllCtl_sysPllDiffClkEn 11 |
| #define bGbl_sysPllCtl_sysPllDiffClkEn 1 |
| #define MSK32Gbl_sysPllCtl_sysPllDiffClkEn 0x00000800 |
| #define BA_Gbl_sysPllCtl_sysPllSelVcoDiff 0x0019 |
| #define B16Gbl_sysPllCtl_sysPllSelVcoDiff 0x0018 |
| #define LSb32Gbl_sysPllCtl_sysPllSelVcoDiff 12 |
| #define LSb16Gbl_sysPllCtl_sysPllSelVcoDiff 12 |
| #define bGbl_sysPllCtl_sysPllSelVcoDiff 1 |
| #define MSK32Gbl_sysPllCtl_sysPllSelVcoDiff 0x00001000 |
| #define BA_Gbl_sysPllCtl_sysPllSelVcoClkSe 0x0019 |
| #define B16Gbl_sysPllCtl_sysPllSelVcoClkSe 0x0018 |
| #define LSb32Gbl_sysPllCtl_sysPllSelVcoClkSe 13 |
| #define LSb16Gbl_sysPllCtl_sysPllSelVcoClkSe 13 |
| #define bGbl_sysPllCtl_sysPllSelVcoClkSe 1 |
| #define MSK32Gbl_sysPllCtl_sysPllSelVcoClkSe 0x00002000 |
| #define BA_Gbl_sysPllCtl_sysPllBypassFbDiv 0x0019 |
| #define B16Gbl_sysPllCtl_sysPllBypassFbDiv 0x0018 |
| #define LSb32Gbl_sysPllCtl_sysPllBypassFbDiv 14 |
| #define LSb16Gbl_sysPllCtl_sysPllBypassFbDiv 14 |
| #define bGbl_sysPllCtl_sysPllBypassFbDiv 1 |
| #define MSK32Gbl_sysPllCtl_sysPllBypassFbDiv 0x00004000 |
| #define BA_Gbl_sysPllCtl_sysPllBypassEn 0x0019 |
| #define B16Gbl_sysPllCtl_sysPllBypassEn 0x0018 |
| #define LSb32Gbl_sysPllCtl_sysPllBypassEn 15 |
| #define LSb16Gbl_sysPllCtl_sysPllBypassEn 15 |
| #define bGbl_sysPllCtl_sysPllBypassEn 1 |
| #define MSK32Gbl_sysPllCtl_sysPllBypassEn 0x00008000 |
| #define BA_Gbl_sysPllCtl_sysPllGateClkCtrl 0x001A |
| #define B16Gbl_sysPllCtl_sysPllGateClkCtrl 0x001A |
| #define LSb32Gbl_sysPllCtl_sysPllGateClkCtrl 16 |
| #define LSb16Gbl_sysPllCtl_sysPllGateClkCtrl 0 |
| #define bGbl_sysPllCtl_sysPllGateClkCtrl 1 |
| #define MSK32Gbl_sysPllCtl_sysPllGateClkCtrl 0x00010000 |
| #define BA_Gbl_sysPllCtl_sysPllLineUpEn 0x001A |
| #define B16Gbl_sysPllCtl_sysPllLineUpEn 0x001A |
| #define LSb32Gbl_sysPllCtl_sysPllLineUpEn 17 |
| #define LSb16Gbl_sysPllCtl_sysPllLineUpEn 1 |
| #define bGbl_sysPllCtl_sysPllLineUpEn 1 |
| #define MSK32Gbl_sysPllCtl_sysPllLineUpEn 0x00020000 |
| #define BA_Gbl_sysPllCtl_sysPllIntpi 0x001A |
| #define B16Gbl_sysPllCtl_sysPllIntpi 0x001A |
| #define LSb32Gbl_sysPllCtl_sysPllIntpi 18 |
| #define LSb16Gbl_sysPllCtl_sysPllIntpi 2 |
| #define bGbl_sysPllCtl_sysPllIntpi 4 |
| #define MSK32Gbl_sysPllCtl_sysPllIntpi 0x003C0000 |
| #define BA_Gbl_sysPllCtl_sysPllPiEn 0x001A |
| #define B16Gbl_sysPllCtl_sysPllPiEn 0x001A |
| #define LSb32Gbl_sysPllCtl_sysPllPiEn 22 |
| #define LSb16Gbl_sysPllCtl_sysPllPiEn 6 |
| #define bGbl_sysPllCtl_sysPllPiEn 1 |
| #define MSK32Gbl_sysPllCtl_sysPllPiEn 0x00400000 |
| #define BA_Gbl_sysPllCtl_sysPllSscClkEn 0x001A |
| #define B16Gbl_sysPllCtl_sysPllSscClkEn 0x001A |
| #define LSb32Gbl_sysPllCtl_sysPllSscClkEn 23 |
| #define LSb16Gbl_sysPllCtl_sysPllSscClkEn 7 |
| #define bGbl_sysPllCtl_sysPllSscClkEn 1 |
| #define MSK32Gbl_sysPllCtl_sysPllSscClkEn 0x00800000 |
| #define BA_Gbl_sysPllCtl_sysPllClkDetEn 0x001B |
| #define B16Gbl_sysPllCtl_sysPllClkDetEn 0x001A |
| #define LSb32Gbl_sysPllCtl_sysPllClkDetEn 24 |
| #define LSb16Gbl_sysPllCtl_sysPllClkDetEn 8 |
| #define bGbl_sysPllCtl_sysPllClkDetEn 1 |
| #define MSK32Gbl_sysPllCtl_sysPllClkDetEn 0x01000000 |
| #define BA_Gbl_sysPllCtl_sysPllFreqOffsetEn 0x001B |
| #define B16Gbl_sysPllCtl_sysPllFreqOffsetEn 0x001A |
| #define LSb32Gbl_sysPllCtl_sysPllFreqOffsetEn 25 |
| #define LSb16Gbl_sysPllCtl_sysPllFreqOffsetEn 9 |
| #define bGbl_sysPllCtl_sysPllFreqOffsetEn 1 |
| #define MSK32Gbl_sysPllCtl_sysPllFreqOffsetEn 0x02000000 |
| #define RA_Gbl_sysPllCtl2 0x001C |
| #define BA_Gbl_sysPllCtl_sysPllFreqOffset 0x001C |
| #define B16Gbl_sysPllCtl_sysPllFreqOffset 0x001C |
| #define LSb32Gbl_sysPllCtl_sysPllFreqOffset 0 |
| #define LSb16Gbl_sysPllCtl_sysPllFreqOffset 0 |
| #define bGbl_sysPllCtl_sysPllFreqOffset 17 |
| #define MSK32Gbl_sysPllCtl_sysPllFreqOffset 0x0001FFFF |
| #define BA_Gbl_sysPllCtl_sysPllFreqOffsetModeSel 0x001E |
| #define B16Gbl_sysPllCtl_sysPllFreqOffsetModeSel 0x001E |
| #define LSb32Gbl_sysPllCtl_sysPllFreqOffsetModeSel 17 |
| #define LSb16Gbl_sysPllCtl_sysPllFreqOffsetModeSel 1 |
| #define bGbl_sysPllCtl_sysPllFreqOffsetModeSel 1 |
| #define MSK32Gbl_sysPllCtl_sysPllFreqOffsetModeSel 0x00020000 |
| #define BA_Gbl_sysPllCtl_sysPllFreqOffsetValid 0x001E |
| #define B16Gbl_sysPllCtl_sysPllFreqOffsetValid 0x001E |
| #define LSb32Gbl_sysPllCtl_sysPllFreqOffsetValid 18 |
| #define LSb16Gbl_sysPllCtl_sysPllFreqOffsetValid 2 |
| #define bGbl_sysPllCtl_sysPllFreqOffsetValid 1 |
| #define MSK32Gbl_sysPllCtl_sysPllFreqOffsetValid 0x00040000 |
| #define BA_Gbl_sysPllCtl_sysPllSscEn 0x001E |
| #define B16Gbl_sysPllCtl_sysPllSscEn 0x001E |
| #define LSb32Gbl_sysPllCtl_sysPllSscEn 19 |
| #define LSb16Gbl_sysPllCtl_sysPllSscEn 3 |
| #define bGbl_sysPllCtl_sysPllSscEn 1 |
| #define MSK32Gbl_sysPllCtl_sysPllSscEn 0x00080000 |
| #define Gbl_sysPllCtl_sysPllSscEn_Disable 0x0 |
| #define Gbl_sysPllCtl_sysPllSscEn_Enable 0x1 |
| #define BA_Gbl_sysPllCtl_sysPllSscmode 0x001E |
| #define B16Gbl_sysPllCtl_sysPllSscmode 0x001E |
| #define LSb32Gbl_sysPllCtl_sysPllSscmode 20 |
| #define LSb16Gbl_sysPllCtl_sysPllSscmode 4 |
| #define bGbl_sysPllCtl_sysPllSscmode 1 |
| #define MSK32Gbl_sysPllCtl_sysPllSscmode 0x00100000 |
| #define Gbl_sysPllCtl_sysPllSscmode_Centre 0x0 |
| #define Gbl_sysPllCtl_sysPllSscmode_Down 0x1 |
| #define RA_Gbl_sysPllCtl3 0x0020 |
| #define BA_Gbl_sysPllCtl_sysPllSscFdiv 0x0020 |
| #define B16Gbl_sysPllCtl_sysPllSscFdiv 0x0020 |
| #define LSb32Gbl_sysPllCtl_sysPllSscFdiv 0 |
| #define LSb16Gbl_sysPllCtl_sysPllSscFdiv 0 |
| #define bGbl_sysPllCtl_sysPllSscFdiv 16 |
| #define MSK32Gbl_sysPllCtl_sysPllSscFdiv 0x0000FFFF |
| #define BA_Gbl_sysPllCtl_sysPllSscRnge 0x0022 |
| #define B16Gbl_sysPllCtl_sysPllSscRnge 0x0022 |
| #define LSb32Gbl_sysPllCtl_sysPllSscRnge 16 |
| #define LSb16Gbl_sysPllCtl_sysPllSscRnge 0 |
| #define bGbl_sysPllCtl_sysPllSscRnge 11 |
| #define MSK32Gbl_sysPllCtl_sysPllSscRnge 0x07FF0000 |
| #define BA_Gbl_sysPllCtl_sysPllSscResetExt 0x0023 |
| #define B16Gbl_sysPllCtl_sysPllSscResetExt 0x0022 |
| #define LSb32Gbl_sysPllCtl_sysPllSscResetExt 27 |
| #define LSb16Gbl_sysPllCtl_sysPllSscResetExt 11 |
| #define bGbl_sysPllCtl_sysPllSscResetExt 1 |
| #define MSK32Gbl_sysPllCtl_sysPllSscResetExt 0x08000000 |
| #define Gbl_sysPllCtl_sysPllSscResetExt_Int 0x0 |
| #define Gbl_sysPllCtl_sysPllSscResetExt_Ext 0x1 |
| #define BA_Gbl_sysPllCtl_sysPllTestMon 0x0023 |
| #define B16Gbl_sysPllCtl_sysPllTestMon 0x0022 |
| #define LSb32Gbl_sysPllCtl_sysPllTestMon 28 |
| #define LSb16Gbl_sysPllCtl_sysPllTestMon 12 |
| #define bGbl_sysPllCtl_sysPllTestMon 4 |
| #define MSK32Gbl_sysPllCtl_sysPllTestMon 0xF0000000 |
| #define RA_Gbl_sysPllCtl4 0x0024 |
| #define BA_Gbl_sysPllCtl_sysPllRsvdIn 0x0024 |
| #define B16Gbl_sysPllCtl_sysPllRsvdIn 0x0024 |
| #define LSb32Gbl_sysPllCtl_sysPllRsvdIn 0 |
| #define LSb16Gbl_sysPllCtl_sysPllRsvdIn 0 |
| #define bGbl_sysPllCtl_sysPllRsvdIn 4 |
| #define MSK32Gbl_sysPllCtl_sysPllRsvdIn 0x0000000F |
| #define BA_Gbl_sysPllCtl_sysPllExtRst 0x0024 |
| #define B16Gbl_sysPllCtl_sysPllExtRst 0x0024 |
| #define LSb32Gbl_sysPllCtl_sysPllExtRst 4 |
| #define LSb16Gbl_sysPllCtl_sysPllExtRst 4 |
| #define bGbl_sysPllCtl_sysPllExtRst 1 |
| #define MSK32Gbl_sysPllCtl_sysPllExtRst 0x00000010 |
| #define RA_Gbl_memPllCtl 0x0028 |
| #define BA_Gbl_memPllCtl_memPllPu 0x0028 |
| #define B16Gbl_memPllCtl_memPllPu 0x0028 |
| #define LSb32Gbl_memPllCtl_memPllPu 0 |
| #define LSb16Gbl_memPllCtl_memPllPu 0 |
| #define bGbl_memPllCtl_memPllPu 1 |
| #define MSK32Gbl_memPllCtl_memPllPu 0x00000001 |
| #define BA_Gbl_memPllCtl_memPllRfDiv 0x0028 |
| #define B16Gbl_memPllCtl_memPllRfDiv 0x0028 |
| #define LSb32Gbl_memPllCtl_memPllRfDiv 1 |
| #define LSb16Gbl_memPllCtl_memPllRfDiv 1 |
| #define bGbl_memPllCtl_memPllRfDiv 5 |
| #define MSK32Gbl_memPllCtl_memPllRfDiv 0x0000003E |
| #define BA_Gbl_memPllCtl_memPllFbDiv 0x0028 |
| #define B16Gbl_memPllCtl_memPllFbDiv 0x0028 |
| #define LSb32Gbl_memPllCtl_memPllFbDiv 6 |
| #define LSb16Gbl_memPllCtl_memPllFbDiv 6 |
| #define bGbl_memPllCtl_memPllFbDiv 9 |
| #define MSK32Gbl_memPllCtl_memPllFbDiv 0x00007FC0 |
| #define BA_Gbl_memPllCtl_memPllVddm 0x0029 |
| #define B16Gbl_memPllCtl_memPllVddm 0x0028 |
| #define LSb32Gbl_memPllCtl_memPllVddm 15 |
| #define LSb16Gbl_memPllCtl_memPllVddm 15 |
| #define bGbl_memPllCtl_memPllVddm 2 |
| #define MSK32Gbl_memPllCtl_memPllVddm 0x00018000 |
| #define Gbl_memPllCtl_memPllVddm_1R40v 0x0 |
| #define Gbl_memPllCtl_memPllVddm_1R45v 0x1 |
| #define Gbl_memPllCtl_memPllVddm_1R50v 0x2 |
| #define Gbl_memPllCtl_memPllVddm_1R55v 0x3 |
| #define BA_Gbl_memPllCtl_memPllVddl 0x002A |
| #define B16Gbl_memPllCtl_memPllVddl 0x002A |
| #define LSb32Gbl_memPllCtl_memPllVddl 17 |
| #define LSb16Gbl_memPllCtl_memPllVddl 1 |
| #define bGbl_memPllCtl_memPllVddl 4 |
| #define MSK32Gbl_memPllCtl_memPllVddl 0x001E0000 |
| #define Gbl_memPllCtl_memPllVddl_0R78v 0x1 |
| #define Gbl_memPllCtl_memPllVddl_0R82v 0x2 |
| #define Gbl_memPllCtl_memPllVddl_0R86v 0x3 |
| #define Gbl_memPllCtl_memPllVddl_0R90v 0x4 |
| #define BA_Gbl_memPllCtl_memPllVregIVRef 0x002A |
| #define B16Gbl_memPllCtl_memPllVregIVRef 0x002A |
| #define LSb32Gbl_memPllCtl_memPllVregIVRef 21 |
| #define LSb16Gbl_memPllCtl_memPllVregIVRef 5 |
| #define bGbl_memPllCtl_memPllVregIVRef 2 |
| #define MSK32Gbl_memPllCtl_memPllVregIVRef 0x00600000 |
| #define BA_Gbl_memPllCtl_memPllIcp 0x002A |
| #define B16Gbl_memPllCtl_memPllIcp 0x002A |
| #define LSb32Gbl_memPllCtl_memPllIcp 23 |
| #define LSb16Gbl_memPllCtl_memPllIcp 7 |
| #define bGbl_memPllCtl_memPllIcp 3 |
| #define MSK32Gbl_memPllCtl_memPllIcp 0x03800000 |
| #define Gbl_memPllCtl_memPllIcp_2uA 0x0 |
| #define Gbl_memPllCtl_memPllIcp_3uA 0x1 |
| #define Gbl_memPllCtl_memPllIcp_4uA 0x2 |
| #define Gbl_memPllCtl_memPllIcp_5uA 0x3 |
| #define Gbl_memPllCtl_memPllIcp_6uA 0x4 |
| #define Gbl_memPllCtl_memPllIcp_7uA 0x5 |
| #define Gbl_memPllCtl_memPllIcp_8uA 0x6 |
| #define Gbl_memPllCtl_memPllIcp_9uA 0x7 |
| #define BA_Gbl_memPllCtl_memPllKvco 0x002B |
| #define B16Gbl_memPllCtl_memPllKvco 0x002A |
| #define LSb32Gbl_memPllCtl_memPllKvco 26 |
| #define LSb16Gbl_memPllCtl_memPllKvco 10 |
| #define bGbl_memPllCtl_memPllKvco 4 |
| #define MSK32Gbl_memPllCtl_memPllKvco 0x3C000000 |
| #define Gbl_memPllCtl_memPllKvco_1R25Gto1R35G 0x1 |
| #define Gbl_memPllCtl_memPllKvco_1R35Gto1R55G 0x2 |
| #define Gbl_memPllCtl_memPllKvco_1R55Gto1R75G 0x3 |
| #define Gbl_memPllCtl_memPllKvco_1R75Gto1R95G 0x4 |
| #define Gbl_memPllCtl_memPllKvco_1R95Gto2R15G 0x5 |
| #define Gbl_memPllCtl_memPllKvco_2R15Gto2R4G 0x6 |
| #define Gbl_memPllCtl_memPllKvco_2R4Gto2R5G 0x7 |
| #define BA_Gbl_memPllCtl_memPllCtune 0x002B |
| #define B16Gbl_memPllCtl_memPllCtune 0x002A |
| #define LSb32Gbl_memPllCtl_memPllCtune 30 |
| #define LSb16Gbl_memPllCtl_memPllCtune 14 |
| #define bGbl_memPllCtl_memPllCtune 2 |
| #define MSK32Gbl_memPllCtl_memPllCtune 0xC0000000 |
| #define RA_Gbl_memPllCtl1 0x002C |
| #define BA_Gbl_memPllCtl_memPllVcoRng 0x002C |
| #define B16Gbl_memPllCtl_memPllVcoRng 0x002C |
| #define LSb32Gbl_memPllCtl_memPllVcoRng 0 |
| #define LSb16Gbl_memPllCtl_memPllVcoRng 0 |
| #define bGbl_memPllCtl_memPllVcoRng 3 |
| #define MSK32Gbl_memPllCtl_memPllVcoRng 0x00000007 |
| #define BA_Gbl_memPllCtl_memPllVcoDivSelDiff 0x002C |
| #define B16Gbl_memPllCtl_memPllVcoDivSelDiff 0x002C |
| #define LSb32Gbl_memPllCtl_memPllVcoDivSelDiff 3 |
| #define LSb16Gbl_memPllCtl_memPllVcoDivSelDiff 3 |
| #define bGbl_memPllCtl_memPllVcoDivSelDiff 4 |
| #define MSK32Gbl_memPllCtl_memPllVcoDivSelDiff 0x00000078 |
| #define BA_Gbl_memPllCtl_memPllVcoDivSelSe 0x002C |
| #define B16Gbl_memPllCtl_memPllVcoDivSelSe 0x002C |
| #define LSb32Gbl_memPllCtl_memPllVcoDivSelSe 7 |
| #define LSb16Gbl_memPllCtl_memPllVcoDivSelSe 7 |
| #define bGbl_memPllCtl_memPllVcoDivSelSe 4 |
| #define MSK32Gbl_memPllCtl_memPllVcoDivSelSe 0x00000780 |
| #define BA_Gbl_memPllCtl_memPllDiffClkEn 0x002D |
| #define B16Gbl_memPllCtl_memPllDiffClkEn 0x002C |
| #define LSb32Gbl_memPllCtl_memPllDiffClkEn 11 |
| #define LSb16Gbl_memPllCtl_memPllDiffClkEn 11 |
| #define bGbl_memPllCtl_memPllDiffClkEn 1 |
| #define MSK32Gbl_memPllCtl_memPllDiffClkEn 0x00000800 |
| #define BA_Gbl_memPllCtl_memPllSelVcoDiff 0x002D |
| #define B16Gbl_memPllCtl_memPllSelVcoDiff 0x002C |
| #define LSb32Gbl_memPllCtl_memPllSelVcoDiff 12 |
| #define LSb16Gbl_memPllCtl_memPllSelVcoDiff 12 |
| #define bGbl_memPllCtl_memPllSelVcoDiff 1 |
| #define MSK32Gbl_memPllCtl_memPllSelVcoDiff 0x00001000 |
| #define BA_Gbl_memPllCtl_memPllSelVcoClkSe 0x002D |
| #define B16Gbl_memPllCtl_memPllSelVcoClkSe 0x002C |
| #define LSb32Gbl_memPllCtl_memPllSelVcoClkSe 13 |
| #define LSb16Gbl_memPllCtl_memPllSelVcoClkSe 13 |
| #define bGbl_memPllCtl_memPllSelVcoClkSe 1 |
| #define MSK32Gbl_memPllCtl_memPllSelVcoClkSe 0x00002000 |
| #define BA_Gbl_memPllCtl_memPllBypassFbDiv 0x002D |
| #define B16Gbl_memPllCtl_memPllBypassFbDiv 0x002C |
| #define LSb32Gbl_memPllCtl_memPllBypassFbDiv 14 |
| #define LSb16Gbl_memPllCtl_memPllBypassFbDiv 14 |
| #define bGbl_memPllCtl_memPllBypassFbDiv 1 |
| #define MSK32Gbl_memPllCtl_memPllBypassFbDiv 0x00004000 |
| #define BA_Gbl_memPllCtl_memPllBypassEn 0x002D |
| #define B16Gbl_memPllCtl_memPllBypassEn 0x002C |
| #define LSb32Gbl_memPllCtl_memPllBypassEn 15 |
| #define LSb16Gbl_memPllCtl_memPllBypassEn 15 |
| #define bGbl_memPllCtl_memPllBypassEn 1 |
| #define MSK32Gbl_memPllCtl_memPllBypassEn 0x00008000 |
| #define BA_Gbl_memPllCtl_memPllGateClkCtrl 0x002E |
| #define B16Gbl_memPllCtl_memPllGateClkCtrl 0x002E |
| #define LSb32Gbl_memPllCtl_memPllGateClkCtrl 16 |
| #define LSb16Gbl_memPllCtl_memPllGateClkCtrl 0 |
| #define bGbl_memPllCtl_memPllGateClkCtrl 1 |
| #define MSK32Gbl_memPllCtl_memPllGateClkCtrl 0x00010000 |
| #define BA_Gbl_memPllCtl_memPllLineUpEn 0x002E |
| #define B16Gbl_memPllCtl_memPllLineUpEn 0x002E |
| #define LSb32Gbl_memPllCtl_memPllLineUpEn 17 |
| #define LSb16Gbl_memPllCtl_memPllLineUpEn 1 |
| #define bGbl_memPllCtl_memPllLineUpEn 1 |
| #define MSK32Gbl_memPllCtl_memPllLineUpEn 0x00020000 |
| #define BA_Gbl_memPllCtl_memPllIntpi 0x002E |
| #define B16Gbl_memPllCtl_memPllIntpi 0x002E |
| #define LSb32Gbl_memPllCtl_memPllIntpi 18 |
| #define LSb16Gbl_memPllCtl_memPllIntpi 2 |
| #define bGbl_memPllCtl_memPllIntpi 4 |
| #define MSK32Gbl_memPllCtl_memPllIntpi 0x003C0000 |
| #define BA_Gbl_memPllCtl_memPllPiEn 0x002E |
| #define B16Gbl_memPllCtl_memPllPiEn 0x002E |
| #define LSb32Gbl_memPllCtl_memPllPiEn 22 |
| #define LSb16Gbl_memPllCtl_memPllPiEn 6 |
| #define bGbl_memPllCtl_memPllPiEn 1 |
| #define MSK32Gbl_memPllCtl_memPllPiEn 0x00400000 |
| #define BA_Gbl_memPllCtl_memPllSscClkEn 0x002E |
| #define B16Gbl_memPllCtl_memPllSscClkEn 0x002E |
| #define LSb32Gbl_memPllCtl_memPllSscClkEn 23 |
| #define LSb16Gbl_memPllCtl_memPllSscClkEn 7 |
| #define bGbl_memPllCtl_memPllSscClkEn 1 |
| #define MSK32Gbl_memPllCtl_memPllSscClkEn 0x00800000 |
| #define BA_Gbl_memPllCtl_memPllClkDetEn 0x002F |
| #define B16Gbl_memPllCtl_memPllClkDetEn 0x002E |
| #define LSb32Gbl_memPllCtl_memPllClkDetEn 24 |
| #define LSb16Gbl_memPllCtl_memPllClkDetEn 8 |
| #define bGbl_memPllCtl_memPllClkDetEn 1 |
| #define MSK32Gbl_memPllCtl_memPllClkDetEn 0x01000000 |
| #define BA_Gbl_memPllCtl_memPllFreqOffsetEn 0x002F |
| #define B16Gbl_memPllCtl_memPllFreqOffsetEn 0x002E |
| #define LSb32Gbl_memPllCtl_memPllFreqOffsetEn 25 |
| #define LSb16Gbl_memPllCtl_memPllFreqOffsetEn 9 |
| #define bGbl_memPllCtl_memPllFreqOffsetEn 1 |
| #define MSK32Gbl_memPllCtl_memPllFreqOffsetEn 0x02000000 |
| #define RA_Gbl_memPllCtl2 0x0030 |
| #define BA_Gbl_memPllCtl_memPllFreqOffset 0x0030 |
| #define B16Gbl_memPllCtl_memPllFreqOffset 0x0030 |
| #define LSb32Gbl_memPllCtl_memPllFreqOffset 0 |
| #define LSb16Gbl_memPllCtl_memPllFreqOffset 0 |
| #define bGbl_memPllCtl_memPllFreqOffset 17 |
| #define MSK32Gbl_memPllCtl_memPllFreqOffset 0x0001FFFF |
| #define BA_Gbl_memPllCtl_memPllFreqOffsetModeSel 0x0032 |
| #define B16Gbl_memPllCtl_memPllFreqOffsetModeSel 0x0032 |
| #define LSb32Gbl_memPllCtl_memPllFreqOffsetModeSel 17 |
| #define LSb16Gbl_memPllCtl_memPllFreqOffsetModeSel 1 |
| #define bGbl_memPllCtl_memPllFreqOffsetModeSel 1 |
| #define MSK32Gbl_memPllCtl_memPllFreqOffsetModeSel 0x00020000 |
| #define BA_Gbl_memPllCtl_memPllFreqOffsetValid 0x0032 |
| #define B16Gbl_memPllCtl_memPllFreqOffsetValid 0x0032 |
| #define LSb32Gbl_memPllCtl_memPllFreqOffsetValid 18 |
| #define LSb16Gbl_memPllCtl_memPllFreqOffsetValid 2 |
| #define bGbl_memPllCtl_memPllFreqOffsetValid 1 |
| #define MSK32Gbl_memPllCtl_memPllFreqOffsetValid 0x00040000 |
| #define BA_Gbl_memPllCtl_memPllSscEn 0x0032 |
| #define B16Gbl_memPllCtl_memPllSscEn 0x0032 |
| #define LSb32Gbl_memPllCtl_memPllSscEn 19 |
| #define LSb16Gbl_memPllCtl_memPllSscEn 3 |
| #define bGbl_memPllCtl_memPllSscEn 1 |
| #define MSK32Gbl_memPllCtl_memPllSscEn 0x00080000 |
| #define Gbl_memPllCtl_memPllSscEn_Disable 0x0 |
| #define Gbl_memPllCtl_memPllSscEn_Enable 0x1 |
| #define BA_Gbl_memPllCtl_memPllSscmode 0x0032 |
| #define B16Gbl_memPllCtl_memPllSscmode 0x0032 |
| #define LSb32Gbl_memPllCtl_memPllSscmode 20 |
| #define LSb16Gbl_memPllCtl_memPllSscmode 4 |
| #define bGbl_memPllCtl_memPllSscmode 1 |
| #define MSK32Gbl_memPllCtl_memPllSscmode 0x00100000 |
| #define Gbl_memPllCtl_memPllSscmode_Centre 0x0 |
| #define Gbl_memPllCtl_memPllSscmode_Down 0x1 |
| #define RA_Gbl_memPllCtl3 0x0034 |
| #define BA_Gbl_memPllCtl_memPllSscFdiv 0x0034 |
| #define B16Gbl_memPllCtl_memPllSscFdiv 0x0034 |
| #define LSb32Gbl_memPllCtl_memPllSscFdiv 0 |
| #define LSb16Gbl_memPllCtl_memPllSscFdiv 0 |
| #define bGbl_memPllCtl_memPllSscFdiv 16 |
| #define MSK32Gbl_memPllCtl_memPllSscFdiv 0x0000FFFF |
| #define BA_Gbl_memPllCtl_memPllSscRnge 0x0036 |
| #define B16Gbl_memPllCtl_memPllSscRnge 0x0036 |
| #define LSb32Gbl_memPllCtl_memPllSscRnge 16 |
| #define LSb16Gbl_memPllCtl_memPllSscRnge 0 |
| #define bGbl_memPllCtl_memPllSscRnge 11 |
| #define MSK32Gbl_memPllCtl_memPllSscRnge 0x07FF0000 |
| #define BA_Gbl_memPllCtl_memPllSscResetExt 0x0037 |
| #define B16Gbl_memPllCtl_memPllSscResetExt 0x0036 |
| #define LSb32Gbl_memPllCtl_memPllSscResetExt 27 |
| #define LSb16Gbl_memPllCtl_memPllSscResetExt 11 |
| #define bGbl_memPllCtl_memPllSscResetExt 1 |
| #define MSK32Gbl_memPllCtl_memPllSscResetExt 0x08000000 |
| #define Gbl_memPllCtl_memPllSscResetExt_Int 0x0 |
| #define Gbl_memPllCtl_memPllSscResetExt_Ext 0x1 |
| #define BA_Gbl_memPllCtl_memPllTestMon 0x0037 |
| #define B16Gbl_memPllCtl_memPllTestMon 0x0036 |
| #define LSb32Gbl_memPllCtl_memPllTestMon 28 |
| #define LSb16Gbl_memPllCtl_memPllTestMon 12 |
| #define bGbl_memPllCtl_memPllTestMon 4 |
| #define MSK32Gbl_memPllCtl_memPllTestMon 0xF0000000 |
| #define RA_Gbl_memPllCtl4 0x0038 |
| #define BA_Gbl_memPllCtl_memPllRsvdIn 0x0038 |
| #define B16Gbl_memPllCtl_memPllRsvdIn 0x0038 |
| #define LSb32Gbl_memPllCtl_memPllRsvdIn 0 |
| #define LSb16Gbl_memPllCtl_memPllRsvdIn 0 |
| #define bGbl_memPllCtl_memPllRsvdIn 4 |
| #define MSK32Gbl_memPllCtl_memPllRsvdIn 0x0000000F |
| #define BA_Gbl_memPllCtl_memPllExtRst 0x0038 |
| #define B16Gbl_memPllCtl_memPllExtRst 0x0038 |
| #define LSb32Gbl_memPllCtl_memPllExtRst 4 |
| #define LSb16Gbl_memPllCtl_memPllExtRst 4 |
| #define bGbl_memPllCtl_memPllExtRst 1 |
| #define MSK32Gbl_memPllCtl_memPllExtRst 0x00000010 |
| #define RA_Gbl_cpuPllCtl 0x003C |
| #define BA_Gbl_cpuPllCtl_cpuPllPu 0x003C |
| #define B16Gbl_cpuPllCtl_cpuPllPu 0x003C |
| #define LSb32Gbl_cpuPllCtl_cpuPllPu 0 |
| #define LSb16Gbl_cpuPllCtl_cpuPllPu 0 |
| #define bGbl_cpuPllCtl_cpuPllPu 1 |
| #define MSK32Gbl_cpuPllCtl_cpuPllPu 0x00000001 |
| #define BA_Gbl_cpuPllCtl_cpuPllRfDiv 0x003C |
| #define B16Gbl_cpuPllCtl_cpuPllRfDiv 0x003C |
| #define LSb32Gbl_cpuPllCtl_cpuPllRfDiv 1 |
| #define LSb16Gbl_cpuPllCtl_cpuPllRfDiv 1 |
| #define bGbl_cpuPllCtl_cpuPllRfDiv 5 |
| #define MSK32Gbl_cpuPllCtl_cpuPllRfDiv 0x0000003E |
| #define BA_Gbl_cpuPllCtl_cpuPllFbDiv 0x003C |
| #define B16Gbl_cpuPllCtl_cpuPllFbDiv 0x003C |
| #define LSb32Gbl_cpuPllCtl_cpuPllFbDiv 6 |
| #define LSb16Gbl_cpuPllCtl_cpuPllFbDiv 6 |
| #define bGbl_cpuPllCtl_cpuPllFbDiv 9 |
| #define MSK32Gbl_cpuPllCtl_cpuPllFbDiv 0x00007FC0 |
| #define BA_Gbl_cpuPllCtl_cpuPllVddm 0x003D |
| #define B16Gbl_cpuPllCtl_cpuPllVddm 0x003C |
| #define LSb32Gbl_cpuPllCtl_cpuPllVddm 15 |
| #define LSb16Gbl_cpuPllCtl_cpuPllVddm 15 |
| #define bGbl_cpuPllCtl_cpuPllVddm 2 |
| #define MSK32Gbl_cpuPllCtl_cpuPllVddm 0x00018000 |
| #define Gbl_cpuPllCtl_cpuPllVddm_1R40v 0x0 |
| #define Gbl_cpuPllCtl_cpuPllVddm_1R45v 0x1 |
| #define Gbl_cpuPllCtl_cpuPllVddm_1R50v 0x2 |
| #define Gbl_cpuPllCtl_cpuPllVddm_1R55v 0x3 |
| #define BA_Gbl_cpuPllCtl_cpuPllVddl 0x003E |
| #define B16Gbl_cpuPllCtl_cpuPllVddl 0x003E |
| #define LSb32Gbl_cpuPllCtl_cpuPllVddl 17 |
| #define LSb16Gbl_cpuPllCtl_cpuPllVddl 1 |
| #define bGbl_cpuPllCtl_cpuPllVddl 4 |
| #define MSK32Gbl_cpuPllCtl_cpuPllVddl 0x001E0000 |
| #define Gbl_cpuPllCtl_cpuPllVddl_0R78v 0x1 |
| #define Gbl_cpuPllCtl_cpuPllVddl_0R82v 0x2 |
| #define Gbl_cpuPllCtl_cpuPllVddl_0R86v 0x3 |
| #define Gbl_cpuPllCtl_cpuPllVddl_0R90v 0x4 |
| #define Gbl_cpuPllCtl_cpuPllVddl_0R94v 0x5 |
| #define Gbl_cpuPllCtl_cpuPllVddl_0R98v 0x6 |
| #define Gbl_cpuPllCtl_cpuPllVddl_1R02v 0x7 |
| #define Gbl_cpuPllCtl_cpuPllVddl_1R06v 0x8 |
| #define Gbl_cpuPllCtl_cpuPllVddl_1R10v 0x9 |
| #define Gbl_cpuPllCtl_cpuPllVddl_1R14v 0xA |
| #define Gbl_cpuPllCtl_cpuPllVddl_1R16v 0xB |
| #define BA_Gbl_cpuPllCtl_cpuPllVregIVRef 0x003E |
| #define B16Gbl_cpuPllCtl_cpuPllVregIVRef 0x003E |
| #define LSb32Gbl_cpuPllCtl_cpuPllVregIVRef 21 |
| #define LSb16Gbl_cpuPllCtl_cpuPllVregIVRef 5 |
| #define bGbl_cpuPllCtl_cpuPllVregIVRef 2 |
| #define MSK32Gbl_cpuPllCtl_cpuPllVregIVRef 0x00600000 |
| #define BA_Gbl_cpuPllCtl_cpuPllIcp 0x003E |
| #define B16Gbl_cpuPllCtl_cpuPllIcp 0x003E |
| #define LSb32Gbl_cpuPllCtl_cpuPllIcp 23 |
| #define LSb16Gbl_cpuPllCtl_cpuPllIcp 7 |
| #define bGbl_cpuPllCtl_cpuPllIcp 3 |
| #define MSK32Gbl_cpuPllCtl_cpuPllIcp 0x03800000 |
| #define Gbl_cpuPllCtl_cpuPllIcp_2uA 0x0 |
| #define Gbl_cpuPllCtl_cpuPllIcp_3uA 0x1 |
| #define Gbl_cpuPllCtl_cpuPllIcp_4uA 0x2 |
| #define Gbl_cpuPllCtl_cpuPllIcp_5uA 0x3 |
| #define Gbl_cpuPllCtl_cpuPllIcp_6uA 0x4 |
| #define Gbl_cpuPllCtl_cpuPllIcp_7uA 0x5 |
| #define Gbl_cpuPllCtl_cpuPllIcp_8uA 0x6 |
| #define Gbl_cpuPllCtl_cpuPllIcp_9uA 0x7 |
| #define BA_Gbl_cpuPllCtl_cpuPllKvco 0x003F |
| #define B16Gbl_cpuPllCtl_cpuPllKvco 0x003E |
| #define LSb32Gbl_cpuPllCtl_cpuPllKvco 26 |
| #define LSb16Gbl_cpuPllCtl_cpuPllKvco 10 |
| #define bGbl_cpuPllCtl_cpuPllKvco 4 |
| #define MSK32Gbl_cpuPllCtl_cpuPllKvco 0x3C000000 |
| #define Gbl_cpuPllCtl_cpuPllKvco_1R25Gto1R35G 0x1 |
| #define Gbl_cpuPllCtl_cpuPllKvco_1R35Gto1R55G 0x2 |
| #define Gbl_cpuPllCtl_cpuPllKvco_1R55Gto1R75G 0x3 |
| #define Gbl_cpuPllCtl_cpuPllKvco_1R75Gto1R95G 0x4 |
| #define Gbl_cpuPllCtl_cpuPllKvco_1R95Gto2R15G 0x5 |
| #define Gbl_cpuPllCtl_cpuPllKvco_2R15Gto2R4G 0x6 |
| #define Gbl_cpuPllCtl_cpuPllKvco_2R4Gto2R5G 0x7 |
| #define BA_Gbl_cpuPllCtl_cpuPllCtune 0x003F |
| #define B16Gbl_cpuPllCtl_cpuPllCtune 0x003E |
| #define LSb32Gbl_cpuPllCtl_cpuPllCtune 30 |
| #define LSb16Gbl_cpuPllCtl_cpuPllCtune 14 |
| #define bGbl_cpuPllCtl_cpuPllCtune 2 |
| #define MSK32Gbl_cpuPllCtl_cpuPllCtune 0xC0000000 |
| #define RA_Gbl_cpuPllCtl1 0x0040 |
| #define BA_Gbl_cpuPllCtl_cpuPllVcoRng 0x0040 |
| #define B16Gbl_cpuPllCtl_cpuPllVcoRng 0x0040 |
| #define LSb32Gbl_cpuPllCtl_cpuPllVcoRng 0 |
| #define LSb16Gbl_cpuPllCtl_cpuPllVcoRng 0 |
| #define bGbl_cpuPllCtl_cpuPllVcoRng 3 |
| #define MSK32Gbl_cpuPllCtl_cpuPllVcoRng 0x00000007 |
| #define BA_Gbl_cpuPllCtl_cpuPllVcoDivSelDiff 0x0040 |
| #define B16Gbl_cpuPllCtl_cpuPllVcoDivSelDiff 0x0040 |
| #define LSb32Gbl_cpuPllCtl_cpuPllVcoDivSelDiff 3 |
| #define LSb16Gbl_cpuPllCtl_cpuPllVcoDivSelDiff 3 |
| #define bGbl_cpuPllCtl_cpuPllVcoDivSelDiff 4 |
| #define MSK32Gbl_cpuPllCtl_cpuPllVcoDivSelDiff 0x00000078 |
| #define BA_Gbl_cpuPllCtl_cpuPllVcoDivSelSe 0x0040 |
| #define B16Gbl_cpuPllCtl_cpuPllVcoDivSelSe 0x0040 |
| #define LSb32Gbl_cpuPllCtl_cpuPllVcoDivSelSe 7 |
| #define LSb16Gbl_cpuPllCtl_cpuPllVcoDivSelSe 7 |
| #define bGbl_cpuPllCtl_cpuPllVcoDivSelSe 4 |
| #define MSK32Gbl_cpuPllCtl_cpuPllVcoDivSelSe 0x00000780 |
| #define BA_Gbl_cpuPllCtl_cpuPllDiffClkEn 0x0041 |
| #define B16Gbl_cpuPllCtl_cpuPllDiffClkEn 0x0040 |
| #define LSb32Gbl_cpuPllCtl_cpuPllDiffClkEn 11 |
| #define LSb16Gbl_cpuPllCtl_cpuPllDiffClkEn 11 |
| #define bGbl_cpuPllCtl_cpuPllDiffClkEn 1 |
| #define MSK32Gbl_cpuPllCtl_cpuPllDiffClkEn 0x00000800 |
| #define BA_Gbl_cpuPllCtl_cpuPllSelVcoDiff 0x0041 |
| #define B16Gbl_cpuPllCtl_cpuPllSelVcoDiff 0x0040 |
| #define LSb32Gbl_cpuPllCtl_cpuPllSelVcoDiff 12 |
| #define LSb16Gbl_cpuPllCtl_cpuPllSelVcoDiff 12 |
| #define bGbl_cpuPllCtl_cpuPllSelVcoDiff 1 |
| #define MSK32Gbl_cpuPllCtl_cpuPllSelVcoDiff 0x00001000 |
| #define BA_Gbl_cpuPllCtl_cpuPllSelVcoClkSe 0x0041 |
| #define B16Gbl_cpuPllCtl_cpuPllSelVcoClkSe 0x0040 |
| #define LSb32Gbl_cpuPllCtl_cpuPllSelVcoClkSe 13 |
| #define LSb16Gbl_cpuPllCtl_cpuPllSelVcoClkSe 13 |
| #define bGbl_cpuPllCtl_cpuPllSelVcoClkSe 1 |
| #define MSK32Gbl_cpuPllCtl_cpuPllSelVcoClkSe 0x00002000 |
| #define BA_Gbl_cpuPllCtl_cpuPllBypassFbDiv 0x0041 |
| #define B16Gbl_cpuPllCtl_cpuPllBypassFbDiv 0x0040 |
| #define LSb32Gbl_cpuPllCtl_cpuPllBypassFbDiv 14 |
| #define LSb16Gbl_cpuPllCtl_cpuPllBypassFbDiv 14 |
| #define bGbl_cpuPllCtl_cpuPllBypassFbDiv 1 |
| #define MSK32Gbl_cpuPllCtl_cpuPllBypassFbDiv 0x00004000 |
| #define BA_Gbl_cpuPllCtl_cpuPllBypassEn 0x0041 |
| #define B16Gbl_cpuPllCtl_cpuPllBypassEn 0x0040 |
| #define LSb32Gbl_cpuPllCtl_cpuPllBypassEn 15 |
| #define LSb16Gbl_cpuPllCtl_cpuPllBypassEn 15 |
| #define bGbl_cpuPllCtl_cpuPllBypassEn 1 |
| #define MSK32Gbl_cpuPllCtl_cpuPllBypassEn 0x00008000 |
| #define BA_Gbl_cpuPllCtl_cpuPllGateClkCtrl 0x0042 |
| #define B16Gbl_cpuPllCtl_cpuPllGateClkCtrl 0x0042 |
| #define LSb32Gbl_cpuPllCtl_cpuPllGateClkCtrl 16 |
| #define LSb16Gbl_cpuPllCtl_cpuPllGateClkCtrl 0 |
| #define bGbl_cpuPllCtl_cpuPllGateClkCtrl 1 |
| #define MSK32Gbl_cpuPllCtl_cpuPllGateClkCtrl 0x00010000 |
| #define BA_Gbl_cpuPllCtl_cpuPllLineUpEn 0x0042 |
| #define B16Gbl_cpuPllCtl_cpuPllLineUpEn 0x0042 |
| #define LSb32Gbl_cpuPllCtl_cpuPllLineUpEn 17 |
| #define LSb16Gbl_cpuPllCtl_cpuPllLineUpEn 1 |
| #define bGbl_cpuPllCtl_cpuPllLineUpEn 1 |
| #define MSK32Gbl_cpuPllCtl_cpuPllLineUpEn 0x00020000 |
| #define BA_Gbl_cpuPllCtl_cpuPllIntpi 0x0042 |
| #define B16Gbl_cpuPllCtl_cpuPllIntpi 0x0042 |
| #define LSb32Gbl_cpuPllCtl_cpuPllIntpi 18 |
| #define LSb16Gbl_cpuPllCtl_cpuPllIntpi 2 |
| #define bGbl_cpuPllCtl_cpuPllIntpi 4 |
| #define MSK32Gbl_cpuPllCtl_cpuPllIntpi 0x003C0000 |
| #define BA_Gbl_cpuPllCtl_cpuPllPiEn 0x0042 |
| #define B16Gbl_cpuPllCtl_cpuPllPiEn 0x0042 |
| #define LSb32Gbl_cpuPllCtl_cpuPllPiEn 22 |
| #define LSb16Gbl_cpuPllCtl_cpuPllPiEn 6 |
| #define bGbl_cpuPllCtl_cpuPllPiEn 1 |
| #define MSK32Gbl_cpuPllCtl_cpuPllPiEn 0x00400000 |
| #define BA_Gbl_cpuPllCtl_cpuPllSscClkEn 0x0042 |
| #define B16Gbl_cpuPllCtl_cpuPllSscClkEn 0x0042 |
| #define LSb32Gbl_cpuPllCtl_cpuPllSscClkEn 23 |
| #define LSb16Gbl_cpuPllCtl_cpuPllSscClkEn 7 |
| #define bGbl_cpuPllCtl_cpuPllSscClkEn 1 |
| #define MSK32Gbl_cpuPllCtl_cpuPllSscClkEn 0x00800000 |
| #define BA_Gbl_cpuPllCtl_cpuPllClkDetEn 0x0043 |
| #define B16Gbl_cpuPllCtl_cpuPllClkDetEn 0x0042 |
| #define LSb32Gbl_cpuPllCtl_cpuPllClkDetEn 24 |
| #define LSb16Gbl_cpuPllCtl_cpuPllClkDetEn 8 |
| #define bGbl_cpuPllCtl_cpuPllClkDetEn 1 |
| #define MSK32Gbl_cpuPllCtl_cpuPllClkDetEn 0x01000000 |
| #define BA_Gbl_cpuPllCtl_cpuPllFreqOffsetEn 0x0043 |
| #define B16Gbl_cpuPllCtl_cpuPllFreqOffsetEn 0x0042 |
| #define LSb32Gbl_cpuPllCtl_cpuPllFreqOffsetEn 25 |
| #define LSb16Gbl_cpuPllCtl_cpuPllFreqOffsetEn 9 |
| #define bGbl_cpuPllCtl_cpuPllFreqOffsetEn 1 |
| #define MSK32Gbl_cpuPllCtl_cpuPllFreqOffsetEn 0x02000000 |
| #define RA_Gbl_cpuPllCtl2 0x0044 |
| #define BA_Gbl_cpuPllCtl_cpuPllFreqOffset 0x0044 |
| #define B16Gbl_cpuPllCtl_cpuPllFreqOffset 0x0044 |
| #define LSb32Gbl_cpuPllCtl_cpuPllFreqOffset 0 |
| #define LSb16Gbl_cpuPllCtl_cpuPllFreqOffset 0 |
| #define bGbl_cpuPllCtl_cpuPllFreqOffset 17 |
| #define MSK32Gbl_cpuPllCtl_cpuPllFreqOffset 0x0001FFFF |
| #define BA_Gbl_cpuPllCtl_cpuPllFreqOffsetModeSel 0x0046 |
| #define B16Gbl_cpuPllCtl_cpuPllFreqOffsetModeSel 0x0046 |
| #define LSb32Gbl_cpuPllCtl_cpuPllFreqOffsetModeSel 17 |
| #define LSb16Gbl_cpuPllCtl_cpuPllFreqOffsetModeSel 1 |
| #define bGbl_cpuPllCtl_cpuPllFreqOffsetModeSel 1 |
| #define MSK32Gbl_cpuPllCtl_cpuPllFreqOffsetModeSel 0x00020000 |
| #define BA_Gbl_cpuPllCtl_cpuPllFreqOffsetValid 0x0046 |
| #define B16Gbl_cpuPllCtl_cpuPllFreqOffsetValid 0x0046 |
| #define LSb32Gbl_cpuPllCtl_cpuPllFreqOffsetValid 18 |
| #define LSb16Gbl_cpuPllCtl_cpuPllFreqOffsetValid 2 |
| #define bGbl_cpuPllCtl_cpuPllFreqOffsetValid 1 |
| #define MSK32Gbl_cpuPllCtl_cpuPllFreqOffsetValid 0x00040000 |
| #define BA_Gbl_cpuPllCtl_cpuPllSscEn 0x0046 |
| #define B16Gbl_cpuPllCtl_cpuPllSscEn 0x0046 |
| #define LSb32Gbl_cpuPllCtl_cpuPllSscEn 19 |
| #define LSb16Gbl_cpuPllCtl_cpuPllSscEn 3 |
| #define bGbl_cpuPllCtl_cpuPllSscEn 1 |
| #define MSK32Gbl_cpuPllCtl_cpuPllSscEn 0x00080000 |
| #define Gbl_cpuPllCtl_cpuPllSscEn_Disable 0x0 |
| #define Gbl_cpuPllCtl_cpuPllSscEn_Enable 0x1 |
| #define BA_Gbl_cpuPllCtl_cpuPllSscmode 0x0046 |
| #define B16Gbl_cpuPllCtl_cpuPllSscmode 0x0046 |
| #define LSb32Gbl_cpuPllCtl_cpuPllSscmode 20 |
| #define LSb16Gbl_cpuPllCtl_cpuPllSscmode 4 |
| #define bGbl_cpuPllCtl_cpuPllSscmode 1 |
| #define MSK32Gbl_cpuPllCtl_cpuPllSscmode 0x00100000 |
| #define Gbl_cpuPllCtl_cpuPllSscmode_Centre 0x0 |
| #define Gbl_cpuPllCtl_cpuPllSscmode_Down 0x1 |
| #define RA_Gbl_cpuPllCtl3 0x0048 |
| #define BA_Gbl_cpuPllCtl_cpuPllSscFdiv 0x0048 |
| #define B16Gbl_cpuPllCtl_cpuPllSscFdiv 0x0048 |
| #define LSb32Gbl_cpuPllCtl_cpuPllSscFdiv 0 |
| #define LSb16Gbl_cpuPllCtl_cpuPllSscFdiv 0 |
| #define bGbl_cpuPllCtl_cpuPllSscFdiv 16 |
| #define MSK32Gbl_cpuPllCtl_cpuPllSscFdiv 0x0000FFFF |
| #define BA_Gbl_cpuPllCtl_cpuPllSscRnge 0x004A |
| #define B16Gbl_cpuPllCtl_cpuPllSscRnge 0x004A |
| #define LSb32Gbl_cpuPllCtl_cpuPllSscRnge 16 |
| #define LSb16Gbl_cpuPllCtl_cpuPllSscRnge 0 |
| #define bGbl_cpuPllCtl_cpuPllSscRnge 11 |
| #define MSK32Gbl_cpuPllCtl_cpuPllSscRnge 0x07FF0000 |
| #define BA_Gbl_cpuPllCtl_cpuPllSscResetExt 0x004B |
| #define B16Gbl_cpuPllCtl_cpuPllSscResetExt 0x004A |
| #define LSb32Gbl_cpuPllCtl_cpuPllSscResetExt 27 |
| #define LSb16Gbl_cpuPllCtl_cpuPllSscResetExt 11 |
| #define bGbl_cpuPllCtl_cpuPllSscResetExt 1 |
| #define MSK32Gbl_cpuPllCtl_cpuPllSscResetExt 0x08000000 |
| #define Gbl_cpuPllCtl_cpuPllSscResetExt_Int 0x0 |
| #define Gbl_cpuPllCtl_cpuPllSscResetExt_Ext 0x1 |
| #define BA_Gbl_cpuPllCtl_cpuPllTestMon 0x004B |
| #define B16Gbl_cpuPllCtl_cpuPllTestMon 0x004A |
| #define LSb32Gbl_cpuPllCtl_cpuPllTestMon 28 |
| #define LSb16Gbl_cpuPllCtl_cpuPllTestMon 12 |
| #define bGbl_cpuPllCtl_cpuPllTestMon 4 |
| #define MSK32Gbl_cpuPllCtl_cpuPllTestMon 0xF0000000 |
| #define RA_Gbl_cpuPllCtl4 0x004C |
| #define BA_Gbl_cpuPllCtl_cpuPllRsvdIn 0x004C |
| #define B16Gbl_cpuPllCtl_cpuPllRsvdIn 0x004C |
| #define LSb32Gbl_cpuPllCtl_cpuPllRsvdIn 0 |
| #define LSb16Gbl_cpuPllCtl_cpuPllRsvdIn 0 |
| #define bGbl_cpuPllCtl_cpuPllRsvdIn 4 |
| #define MSK32Gbl_cpuPllCtl_cpuPllRsvdIn 0x0000000F |
| #define BA_Gbl_cpuPllCtl_cpuPllExtRst 0x004C |
| #define B16Gbl_cpuPllCtl_cpuPllExtRst 0x004C |
| #define LSb32Gbl_cpuPllCtl_cpuPllExtRst 4 |
| #define LSb16Gbl_cpuPllCtl_cpuPllExtRst 4 |
| #define bGbl_cpuPllCtl_cpuPllExtRst 1 |
| #define MSK32Gbl_cpuPllCtl_cpuPllExtRst 0x00000010 |
| #define RA_Gbl_avPllCtl 0x0050 |
| #define BA_Gbl_avPllCtl_avPllResetPll_A 0x0050 |
| #define B16Gbl_avPllCtl_avPllResetPll_A 0x0050 |
| #define LSb32Gbl_avPllCtl_avPllResetPll_A 0 |
| #define LSb16Gbl_avPllCtl_avPllResetPll_A 0 |
| #define bGbl_avPllCtl_avPllResetPll_A 1 |
| #define MSK32Gbl_avPllCtl_avPllResetPll_A 0x00000001 |
| #define BA_Gbl_avPllCtl_avPllPu_A 0x0050 |
| #define B16Gbl_avPllCtl_avPllPu_A 0x0050 |
| #define LSb32Gbl_avPllCtl_avPllPu_A 1 |
| #define LSb16Gbl_avPllCtl_avPllPu_A 1 |
| #define bGbl_avPllCtl_avPllPu_A 1 |
| #define MSK32Gbl_avPllCtl_avPllPu_A 0x00000002 |
| #define BA_Gbl_avPllCtl_avPllIntpi_A 0x0050 |
| #define B16Gbl_avPllCtl_avPllIntpi_A 0x0050 |
| #define LSb32Gbl_avPllCtl_avPllIntpi_A 2 |
| #define LSb16Gbl_avPllCtl_avPllIntpi_A 2 |
| #define bGbl_avPllCtl_avPllIntpi_A 4 |
| #define MSK32Gbl_avPllCtl_avPllIntpi_A 0x0000003C |
| #define BA_Gbl_avPllCtl_avPllVddr1p45V_A 0x0050 |
| #define B16Gbl_avPllCtl_avPllVddr1p45V_A 0x0050 |
| #define LSb32Gbl_avPllCtl_avPllVddr1p45V_A 6 |
| #define LSb16Gbl_avPllCtl_avPllVddr1p45V_A 6 |
| #define bGbl_avPllCtl_avPllVddr1p45V_A 2 |
| #define MSK32Gbl_avPllCtl_avPllVddr1p45V_A 0x000000C0 |
| #define BA_Gbl_avPllCtl_avPllVddr0p9V_A 0x0051 |
| #define B16Gbl_avPllCtl_avPllVddr0p9V_A 0x0050 |
| #define LSb32Gbl_avPllCtl_avPllVddr0p9V_A 8 |
| #define LSb16Gbl_avPllCtl_avPllVddr0p9V_A 8 |
| #define bGbl_avPllCtl_avPllVddr0p9V_A 4 |
| #define MSK32Gbl_avPllCtl_avPllVddr0p9V_A 0x00000F00 |
| #define BA_Gbl_avPllCtl_avPllVthVcoCal_A 0x0051 |
| #define B16Gbl_avPllCtl_avPllVthVcoCal_A 0x0050 |
| #define LSb32Gbl_avPllCtl_avPllVthVcoCal_A 12 |
| #define LSb16Gbl_avPllCtl_avPllVthVcoCal_A 12 |
| #define bGbl_avPllCtl_avPllVthVcoCal_A 2 |
| #define MSK32Gbl_avPllCtl_avPllVthVcoCal_A 0x00003000 |
| #define BA_Gbl_avPllCtl_avPllKvcoExt_A 0x0051 |
| #define B16Gbl_avPllCtl_avPllKvcoExt_A 0x0050 |
| #define LSb32Gbl_avPllCtl_avPllKvcoExt_A 14 |
| #define LSb16Gbl_avPllCtl_avPllKvcoExt_A 14 |
| #define bGbl_avPllCtl_avPllKvcoExt_A 3 |
| #define MSK32Gbl_avPllCtl_avPllKvcoExt_A 0x0001C000 |
| #define BA_Gbl_avPllCtl_avPllKvcoExtEn_A 0x0052 |
| #define B16Gbl_avPllCtl_avPllKvcoExtEn_A 0x0052 |
| #define LSb32Gbl_avPllCtl_avPllKvcoExtEn_A 17 |
| #define LSb16Gbl_avPllCtl_avPllKvcoExtEn_A 1 |
| #define bGbl_avPllCtl_avPllKvcoExtEn_A 1 |
| #define MSK32Gbl_avPllCtl_avPllKvcoExtEn_A 0x00020000 |
| #define BA_Gbl_avPllCtl_avPllV2iExt_A 0x0052 |
| #define B16Gbl_avPllCtl_avPllV2iExt_A 0x0052 |
| #define LSb32Gbl_avPllCtl_avPllV2iExt_A 18 |
| #define LSb16Gbl_avPllCtl_avPllV2iExt_A 2 |
| #define bGbl_avPllCtl_avPllV2iExt_A 4 |
| #define MSK32Gbl_avPllCtl_avPllV2iExt_A 0x003C0000 |
| #define BA_Gbl_avPllCtl_avPllV2iExtEn_A 0x0052 |
| #define B16Gbl_avPllCtl_avPllV2iExtEn_A 0x0052 |
| #define LSb32Gbl_avPllCtl_avPllV2iExtEn_A 22 |
| #define LSb16Gbl_avPllCtl_avPllV2iExtEn_A 6 |
| #define bGbl_avPllCtl_avPllV2iExtEn_A 1 |
| #define MSK32Gbl_avPllCtl_avPllV2iExtEn_A 0x00400000 |
| #define BA_Gbl_avPllCtl_avPllSpeed_A 0x0052 |
| #define B16Gbl_avPllCtl_avPllSpeed_A 0x0052 |
| #define LSb32Gbl_avPllCtl_avPllSpeed_A 23 |
| #define LSb16Gbl_avPllCtl_avPllSpeed_A 7 |
| #define bGbl_avPllCtl_avPllSpeed_A 3 |
| #define MSK32Gbl_avPllCtl_avPllSpeed_A 0x03800000 |
| #define BA_Gbl_avPllCtl_avPllClkDetEn_A 0x0053 |
| #define B16Gbl_avPllCtl_avPllClkDetEn_A 0x0052 |
| #define LSb32Gbl_avPllCtl_avPllClkDetEn_A 26 |
| #define LSb16Gbl_avPllCtl_avPllClkDetEn_A 10 |
| #define bGbl_avPllCtl_avPllClkDetEn_A 1 |
| #define MSK32Gbl_avPllCtl_avPllClkDetEn_A 0x04000000 |
| #define RA_Gbl_avPllCtl1 0x0054 |
| #define BA_Gbl_avPllCtl_avPllRefDiv_A 0x0054 |
| #define B16Gbl_avPllCtl_avPllRefDiv_A 0x0054 |
| #define LSb32Gbl_avPllCtl_avPllRefDiv_A 0 |
| #define LSb16Gbl_avPllCtl_avPllRefDiv_A 0 |
| #define bGbl_avPllCtl_avPllRefDiv_A 6 |
| #define MSK32Gbl_avPllCtl_avPllRefDiv_A 0x0000003F |
| #define BA_Gbl_avPllCtl_avPllFbDiv_A 0x0054 |
| #define B16Gbl_avPllCtl_avPllFbDiv_A 0x0054 |
| #define LSb32Gbl_avPllCtl_avPllFbDiv_A 6 |
| #define LSb16Gbl_avPllCtl_avPllFbDiv_A 6 |
| #define bGbl_avPllCtl_avPllFbDiv_A 8 |
| #define MSK32Gbl_avPllCtl_avPllFbDiv_A 0x00003FC0 |
| #define BA_Gbl_avPllCtl_avPllIcp_A 0x0055 |
| #define B16Gbl_avPllCtl_avPllIcp_A 0x0054 |
| #define LSb32Gbl_avPllCtl_avPllIcp_A 14 |
| #define LSb16Gbl_avPllCtl_avPllIcp_A 14 |
| #define bGbl_avPllCtl_avPllIcp_A 4 |
| #define MSK32Gbl_avPllCtl_avPllIcp_A 0x0003C000 |
| #define BA_Gbl_avPllCtl_avPllLoadCap_A 0x0056 |
| #define B16Gbl_avPllCtl_avPllLoadCap_A 0x0056 |
| #define LSb32Gbl_avPllCtl_avPllLoadCap_A 18 |
| #define LSb16Gbl_avPllCtl_avPllLoadCap_A 2 |
| #define bGbl_avPllCtl_avPllLoadCap_A 1 |
| #define MSK32Gbl_avPllCtl_avPllLoadCap_A 0x00040000 |
| #define BA_Gbl_avPllCtl_avPllPllCaliStart_A 0x0056 |
| #define B16Gbl_avPllCtl_avPllPllCaliStart_A 0x0056 |
| #define LSb32Gbl_avPllCtl_avPllPllCaliStart_A 19 |
| #define LSb16Gbl_avPllCtl_avPllPllCaliStart_A 3 |
| #define bGbl_avPllCtl_avPllPllCaliStart_A 1 |
| #define MSK32Gbl_avPllCtl_avPllPllCaliStart_A 0x00080000 |
| #define RA_Gbl_avPllCtl2 0x0058 |
| #define BA_Gbl_avPllCtl_avPllFreqOffsetC1_A 0x0058 |
| #define B16Gbl_avPllCtl_avPllFreqOffsetC1_A 0x0058 |
| #define LSb32Gbl_avPllCtl_avPllFreqOffsetC1_A 0 |
| #define LSb16Gbl_avPllCtl_avPllFreqOffsetC1_A 0 |
| #define bGbl_avPllCtl_avPllFreqOffsetC1_A 19 |
| #define MSK32Gbl_avPllCtl_avPllFreqOffsetC1_A 0x0007FFFF |
| #define RA_Gbl_avPllCtl3 0x005C |
| #define BA_Gbl_avPllCtl_avPllFreqOffsetC2_A 0x005C |
| #define B16Gbl_avPllCtl_avPllFreqOffsetC2_A 0x005C |
| #define LSb32Gbl_avPllCtl_avPllFreqOffsetC2_A 0 |
| #define LSb16Gbl_avPllCtl_avPllFreqOffsetC2_A 0 |
| #define bGbl_avPllCtl_avPllFreqOffsetC2_A 19 |
| #define MSK32Gbl_avPllCtl_avPllFreqOffsetC2_A 0x0007FFFF |
| #define RA_Gbl_avPllCtl4 0x0060 |
| #define BA_Gbl_avPllCtl_avPllFreqOffsetC3_A 0x0060 |
| #define B16Gbl_avPllCtl_avPllFreqOffsetC3_A 0x0060 |
| #define LSb32Gbl_avPllCtl_avPllFreqOffsetC3_A 0 |
| #define LSb16Gbl_avPllCtl_avPllFreqOffsetC3_A 0 |
| #define bGbl_avPllCtl_avPllFreqOffsetC3_A 19 |
| #define MSK32Gbl_avPllCtl_avPllFreqOffsetC3_A 0x0007FFFF |
| #define RA_Gbl_avPllCtl5 0x0064 |
| #define BA_Gbl_avPllCtl_avPllFreqOffsetC4_A 0x0064 |
| #define B16Gbl_avPllCtl_avPllFreqOffsetC4_A 0x0064 |
| #define LSb32Gbl_avPllCtl_avPllFreqOffsetC4_A 0 |
| #define LSb16Gbl_avPllCtl_avPllFreqOffsetC4_A 0 |
| #define bGbl_avPllCtl_avPllFreqOffsetC4_A 19 |
| #define MSK32Gbl_avPllCtl_avPllFreqOffsetC4_A 0x0007FFFF |
| #define RA_Gbl_avPllCtl6 0x0068 |
| #define BA_Gbl_avPllCtl_avPllFreqOffsetC5_A 0x0068 |
| #define B16Gbl_avPllCtl_avPllFreqOffsetC5_A 0x0068 |
| #define LSb32Gbl_avPllCtl_avPllFreqOffsetC5_A 0 |
| #define LSb16Gbl_avPllCtl_avPllFreqOffsetC5_A 0 |
| #define bGbl_avPllCtl_avPllFreqOffsetC5_A 19 |
| #define MSK32Gbl_avPllCtl_avPllFreqOffsetC5_A 0x0007FFFF |
| #define RA_Gbl_avPllCtl7 0x006C |
| #define BA_Gbl_avPllCtl_avPllFreqOffsetC6_A 0x006C |
| #define B16Gbl_avPllCtl_avPllFreqOffsetC6_A 0x006C |
| #define LSb32Gbl_avPllCtl_avPllFreqOffsetC6_A 0 |
| #define LSb16Gbl_avPllCtl_avPllFreqOffsetC6_A 0 |
| #define bGbl_avPllCtl_avPllFreqOffsetC6_A 19 |
| #define MSK32Gbl_avPllCtl_avPllFreqOffsetC6_A 0x0007FFFF |
| #define RA_Gbl_avPllCtl8 0x0070 |
| #define BA_Gbl_avPllCtl_avPllFreqOffsetC7_A 0x0070 |
| #define B16Gbl_avPllCtl_avPllFreqOffsetC7_A 0x0070 |
| #define LSb32Gbl_avPllCtl_avPllFreqOffsetC7_A 0 |
| #define LSb16Gbl_avPllCtl_avPllFreqOffsetC7_A 0 |
| #define bGbl_avPllCtl_avPllFreqOffsetC7_A 19 |
| #define MSK32Gbl_avPllCtl_avPllFreqOffsetC7_A 0x0007FFFF |
| #define RA_Gbl_avPllCtl9 0x0074 |
| #define BA_Gbl_avPllCtl_avPllFreqOffsetC8_A 0x0074 |
| #define B16Gbl_avPllCtl_avPllFreqOffsetC8_A 0x0074 |
| #define LSb32Gbl_avPllCtl_avPllFreqOffsetC8_A 0 |
| #define LSb16Gbl_avPllCtl_avPllFreqOffsetC8_A 0 |
| #define bGbl_avPllCtl_avPllFreqOffsetC8_A 19 |
| #define MSK32Gbl_avPllCtl_avPllFreqOffsetC8_A 0x0007FFFF |
| #define BA_Gbl_avPllCtl_avPllFreqOffsetReadyC_A 0x0076 |
| #define B16Gbl_avPllCtl_avPllFreqOffsetReadyC_A 0x0076 |
| #define LSb32Gbl_avPllCtl_avPllFreqOffsetReadyC_A 19 |
| #define LSb16Gbl_avPllCtl_avPllFreqOffsetReadyC_A 3 |
| #define bGbl_avPllCtl_avPllFreqOffsetReadyC_A 8 |
| #define MSK32Gbl_avPllCtl_avPllFreqOffsetReadyC_A 0x07F80000 |
| #define BA_Gbl_avPllCtl_avPllReserveC1_A 0x0077 |
| #define B16Gbl_avPllCtl_avPllReserveC1_A 0x0076 |
| #define LSb32Gbl_avPllCtl_avPllReserveC1_A 27 |
| #define LSb16Gbl_avPllCtl_avPllReserveC1_A 11 |
| #define bGbl_avPllCtl_avPllReserveC1_A 2 |
| #define MSK32Gbl_avPllCtl_avPllReserveC1_A 0x18000000 |
| #define BA_Gbl_avPllCtl_avPllReserveC2_A 0x0077 |
| #define B16Gbl_avPllCtl_avPllReserveC2_A 0x0076 |
| #define LSb32Gbl_avPllCtl_avPllReserveC2_A 29 |
| #define LSb16Gbl_avPllCtl_avPllReserveC2_A 13 |
| #define bGbl_avPllCtl_avPllReserveC2_A 2 |
| #define MSK32Gbl_avPllCtl_avPllReserveC2_A 0x60000000 |
| #define RA_Gbl_avPllCtl10 0x0078 |
| #define BA_Gbl_avPllCtl_avPllReserveC3_A 0x0078 |
| #define B16Gbl_avPllCtl_avPllReserveC3_A 0x0078 |
| #define LSb32Gbl_avPllCtl_avPllReserveC3_A 0 |
| #define LSb16Gbl_avPllCtl_avPllReserveC3_A 0 |
| #define bGbl_avPllCtl_avPllReserveC3_A 2 |
| #define MSK32Gbl_avPllCtl_avPllReserveC3_A 0x00000003 |
| #define BA_Gbl_avPllCtl_avPllReserveC4_A 0x0078 |
| #define B16Gbl_avPllCtl_avPllReserveC4_A 0x0078 |
| #define LSb32Gbl_avPllCtl_avPllReserveC4_A 2 |
| #define LSb16Gbl_avPllCtl_avPllReserveC4_A 2 |
| #define bGbl_avPllCtl_avPllReserveC4_A 2 |
| #define MSK32Gbl_avPllCtl_avPllReserveC4_A 0x0000000C |
| #define BA_Gbl_avPllCtl_avPllReserveC5_A 0x0078 |
| #define B16Gbl_avPllCtl_avPllReserveC5_A 0x0078 |
| #define LSb32Gbl_avPllCtl_avPllReserveC5_A 4 |
| #define LSb16Gbl_avPllCtl_avPllReserveC5_A 4 |
| #define bGbl_avPllCtl_avPllReserveC5_A 2 |
| #define MSK32Gbl_avPllCtl_avPllReserveC5_A 0x00000030 |
| #define BA_Gbl_avPllCtl_avPllReserveC6_A 0x0078 |
| #define B16Gbl_avPllCtl_avPllReserveC6_A 0x0078 |
| #define LSb32Gbl_avPllCtl_avPllReserveC6_A 6 |
| #define LSb16Gbl_avPllCtl_avPllReserveC6_A 6 |
| #define bGbl_avPllCtl_avPllReserveC6_A 2 |
| #define MSK32Gbl_avPllCtl_avPllReserveC6_A 0x000000C0 |
| #define BA_Gbl_avPllCtl_avPllReserveC7_A 0x0079 |
| #define B16Gbl_avPllCtl_avPllReserveC7_A 0x0078 |
| #define LSb32Gbl_avPllCtl_avPllReserveC7_A 8 |
| #define LSb16Gbl_avPllCtl_avPllReserveC7_A 8 |
| #define bGbl_avPllCtl_avPllReserveC7_A 2 |
| #define MSK32Gbl_avPllCtl_avPllReserveC7_A 0x00000300 |
| #define BA_Gbl_avPllCtl_avPllReserveC8_A 0x0079 |
| #define B16Gbl_avPllCtl_avPllReserveC8_A 0x0078 |
| #define LSb32Gbl_avPllCtl_avPllReserveC8_A 10 |
| #define LSb16Gbl_avPllCtl_avPllReserveC8_A 10 |
| #define bGbl_avPllCtl_avPllReserveC8_A 2 |
| #define MSK32Gbl_avPllCtl_avPllReserveC8_A 0x00000C00 |
| #define BA_Gbl_avPllCtl_avPllEnLpC_A 0x0079 |
| #define B16Gbl_avPllCtl_avPllEnLpC_A 0x0078 |
| #define LSb32Gbl_avPllCtl_avPllEnLpC_A 12 |
| #define LSb16Gbl_avPllCtl_avPllEnLpC_A 12 |
| #define bGbl_avPllCtl_avPllEnLpC_A 8 |
| #define MSK32Gbl_avPllCtl_avPllEnLpC_A 0x000FF000 |
| #define BA_Gbl_avPllCtl_avPllPuC_A 0x007A |
| #define B16Gbl_avPllCtl_avPllPuC_A 0x007A |
| #define LSb32Gbl_avPllCtl_avPllPuC_A 20 |
| #define LSb16Gbl_avPllCtl_avPllPuC_A 4 |
| #define bGbl_avPllCtl_avPllPuC_A 7 |
| #define MSK32Gbl_avPllCtl_avPllPuC_A 0x07F00000 |
| #define RA_Gbl_avPllCtl11 0x007C |
| #define BA_Gbl_avPllCtl_avPllResetC_A 0x007C |
| #define B16Gbl_avPllCtl_avPllResetC_A 0x007C |
| #define LSb32Gbl_avPllCtl_avPllResetC_A 0 |
| #define LSb16Gbl_avPllCtl_avPllResetC_A 0 |
| #define bGbl_avPllCtl_avPllResetC_A 7 |
| #define MSK32Gbl_avPllCtl_avPllResetC_A 0x0000007F |
| #define BA_Gbl_avPllCtl_avPllDivHdmiC1_A 0x007C |
| #define B16Gbl_avPllCtl_avPllDivHdmiC1_A 0x007C |
| #define LSb32Gbl_avPllCtl_avPllDivHdmiC1_A 7 |
| #define LSb16Gbl_avPllCtl_avPllDivHdmiC1_A 7 |
| #define bGbl_avPllCtl_avPllDivHdmiC1_A 3 |
| #define MSK32Gbl_avPllCtl_avPllDivHdmiC1_A 0x00000380 |
| #define BA_Gbl_avPllCtl_avPllDivHdmiC2_A 0x007D |
| #define B16Gbl_avPllCtl_avPllDivHdmiC2_A 0x007C |
| #define LSb32Gbl_avPllCtl_avPllDivHdmiC2_A 10 |
| #define LSb16Gbl_avPllCtl_avPllDivHdmiC2_A 10 |
| #define bGbl_avPllCtl_avPllDivHdmiC2_A 3 |
| #define MSK32Gbl_avPllCtl_avPllDivHdmiC2_A 0x00001C00 |
| #define BA_Gbl_avPllCtl_avPllDivHdmiC3_A 0x007D |
| #define B16Gbl_avPllCtl_avPllDivHdmiC3_A 0x007C |
| #define LSb32Gbl_avPllCtl_avPllDivHdmiC3_A 13 |
| #define LSb16Gbl_avPllCtl_avPllDivHdmiC3_A 13 |
| #define bGbl_avPllCtl_avPllDivHdmiC3_A 3 |
| #define MSK32Gbl_avPllCtl_avPllDivHdmiC3_A 0x0000E000 |
| #define BA_Gbl_avPllCtl_avPllDivHdmiC4_A 0x007E |
| #define B16Gbl_avPllCtl_avPllDivHdmiC4_A 0x007E |
| #define LSb32Gbl_avPllCtl_avPllDivHdmiC4_A 16 |
| #define LSb16Gbl_avPllCtl_avPllDivHdmiC4_A 0 |
| #define bGbl_avPllCtl_avPllDivHdmiC4_A 3 |
| #define MSK32Gbl_avPllCtl_avPllDivHdmiC4_A 0x00070000 |
| #define BA_Gbl_avPllCtl_avPllDivHdmiC5_A 0x007E |
| #define B16Gbl_avPllCtl_avPllDivHdmiC5_A 0x007E |
| #define LSb32Gbl_avPllCtl_avPllDivHdmiC5_A 19 |
| #define LSb16Gbl_avPllCtl_avPllDivHdmiC5_A 3 |
| #define bGbl_avPllCtl_avPllDivHdmiC5_A 3 |
| #define MSK32Gbl_avPllCtl_avPllDivHdmiC5_A 0x00380000 |
| #define BA_Gbl_avPllCtl_avPllDivHdmiC6_A 0x007E |
| #define B16Gbl_avPllCtl_avPllDivHdmiC6_A 0x007E |
| #define LSb32Gbl_avPllCtl_avPllDivHdmiC6_A 22 |
| #define LSb16Gbl_avPllCtl_avPllDivHdmiC6_A 6 |
| #define bGbl_avPllCtl_avPllDivHdmiC6_A 3 |
| #define MSK32Gbl_avPllCtl_avPllDivHdmiC6_A 0x01C00000 |
| #define BA_Gbl_avPllCtl_avPllDivHdmiC7_A 0x007F |
| #define B16Gbl_avPllCtl_avPllDivHdmiC7_A 0x007E |
| #define LSb32Gbl_avPllCtl_avPllDivHdmiC7_A 25 |
| #define LSb16Gbl_avPllCtl_avPllDivHdmiC7_A 9 |
| #define bGbl_avPllCtl_avPllDivHdmiC7_A 3 |
| #define MSK32Gbl_avPllCtl_avPllDivHdmiC7_A 0x0E000000 |
| #define BA_Gbl_avPllCtl_avPllDivAv1C1_A 0x007F |
| #define B16Gbl_avPllCtl_avPllDivAv1C1_A 0x007E |
| #define LSb32Gbl_avPllCtl_avPllDivAv1C1_A 28 |
| #define LSb16Gbl_avPllCtl_avPllDivAv1C1_A 12 |
| #define bGbl_avPllCtl_avPllDivAv1C1_A 3 |
| #define MSK32Gbl_avPllCtl_avPllDivAv1C1_A 0x70000000 |
| #define RA_Gbl_avPllCtl12 0x0080 |
| #define BA_Gbl_avPllCtl_avPllDivAv1C2_A 0x0080 |
| #define B16Gbl_avPllCtl_avPllDivAv1C2_A 0x0080 |
| #define LSb32Gbl_avPllCtl_avPllDivAv1C2_A 0 |
| #define LSb16Gbl_avPllCtl_avPllDivAv1C2_A 0 |
| #define bGbl_avPllCtl_avPllDivAv1C2_A 3 |
| #define MSK32Gbl_avPllCtl_avPllDivAv1C2_A 0x00000007 |
| #define BA_Gbl_avPllCtl_avPllDivAv1C3_A 0x0080 |
| #define B16Gbl_avPllCtl_avPllDivAv1C3_A 0x0080 |
| #define LSb32Gbl_avPllCtl_avPllDivAv1C3_A 3 |
| #define LSb16Gbl_avPllCtl_avPllDivAv1C3_A 3 |
| #define bGbl_avPllCtl_avPllDivAv1C3_A 3 |
| #define MSK32Gbl_avPllCtl_avPllDivAv1C3_A 0x00000038 |
| #define BA_Gbl_avPllCtl_avPllDivAv1C4_A 0x0080 |
| #define B16Gbl_avPllCtl_avPllDivAv1C4_A 0x0080 |
| #define LSb32Gbl_avPllCtl_avPllDivAv1C4_A 6 |
| #define LSb16Gbl_avPllCtl_avPllDivAv1C4_A 6 |
| #define bGbl_avPllCtl_avPllDivAv1C4_A 3 |
| #define MSK32Gbl_avPllCtl_avPllDivAv1C4_A 0x000001C0 |
| #define BA_Gbl_avPllCtl_avPllDivAv1C5_A 0x0081 |
| #define B16Gbl_avPllCtl_avPllDivAv1C5_A 0x0080 |
| #define LSb32Gbl_avPllCtl_avPllDivAv1C5_A 9 |
| #define LSb16Gbl_avPllCtl_avPllDivAv1C5_A 9 |
| #define bGbl_avPllCtl_avPllDivAv1C5_A 3 |
| #define MSK32Gbl_avPllCtl_avPllDivAv1C5_A 0x00000E00 |
| #define BA_Gbl_avPllCtl_avPllDivAv1C6_A 0x0081 |
| #define B16Gbl_avPllCtl_avPllDivAv1C6_A 0x0080 |
| #define LSb32Gbl_avPllCtl_avPllDivAv1C6_A 12 |
| #define LSb16Gbl_avPllCtl_avPllDivAv1C6_A 12 |
| #define bGbl_avPllCtl_avPllDivAv1C6_A 3 |
| #define MSK32Gbl_avPllCtl_avPllDivAv1C6_A 0x00007000 |
| #define BA_Gbl_avPllCtl_avPllDivAv1C7_A 0x0081 |
| #define B16Gbl_avPllCtl_avPllDivAv1C7_A 0x0080 |
| #define LSb32Gbl_avPllCtl_avPllDivAv1C7_A 15 |
| #define LSb16Gbl_avPllCtl_avPllDivAv1C7_A 15 |
| #define bGbl_avPllCtl_avPllDivAv1C7_A 3 |
| #define MSK32Gbl_avPllCtl_avPllDivAv1C7_A 0x00038000 |
| #define BA_Gbl_avPllCtl_avPllDivAv2C1_A 0x0082 |
| #define B16Gbl_avPllCtl_avPllDivAv2C1_A 0x0082 |
| #define LSb32Gbl_avPllCtl_avPllDivAv2C1_A 18 |
| #define LSb16Gbl_avPllCtl_avPllDivAv2C1_A 2 |
| #define bGbl_avPllCtl_avPllDivAv2C1_A 7 |
| #define MSK32Gbl_avPllCtl_avPllDivAv2C1_A 0x01FC0000 |
| #define BA_Gbl_avPllCtl_avPllDivAv2C2_A 0x0083 |
| #define B16Gbl_avPllCtl_avPllDivAv2C2_A 0x0082 |
| #define LSb32Gbl_avPllCtl_avPllDivAv2C2_A 25 |
| #define LSb16Gbl_avPllCtl_avPllDivAv2C2_A 9 |
| #define bGbl_avPllCtl_avPllDivAv2C2_A 7 |
| #define MSK32Gbl_avPllCtl_avPllDivAv2C2_A 0xFE000000 |
| #define RA_Gbl_avPllCtl13 0x0084 |
| #define BA_Gbl_avPllCtl_avPllDivAv2C3_A 0x0084 |
| #define B16Gbl_avPllCtl_avPllDivAv2C3_A 0x0084 |
| #define LSb32Gbl_avPllCtl_avPllDivAv2C3_A 0 |
| #define LSb16Gbl_avPllCtl_avPllDivAv2C3_A 0 |
| #define bGbl_avPllCtl_avPllDivAv2C3_A 7 |
| #define MSK32Gbl_avPllCtl_avPllDivAv2C3_A 0x0000007F |
| #define BA_Gbl_avPllCtl_avPllDivAv2C4_A 0x0084 |
| #define B16Gbl_avPllCtl_avPllDivAv2C4_A 0x0084 |
| #define LSb32Gbl_avPllCtl_avPllDivAv2C4_A 7 |
| #define LSb16Gbl_avPllCtl_avPllDivAv2C4_A 7 |
| #define bGbl_avPllCtl_avPllDivAv2C4_A 7 |
| #define MSK32Gbl_avPllCtl_avPllDivAv2C4_A 0x00003F80 |
| #define BA_Gbl_avPllCtl_avPllDivAv2C5_A 0x0085 |
| #define B16Gbl_avPllCtl_avPllDivAv2C5_A 0x0084 |
| #define LSb32Gbl_avPllCtl_avPllDivAv2C5_A 14 |
| #define LSb16Gbl_avPllCtl_avPllDivAv2C5_A 14 |
| #define bGbl_avPllCtl_avPllDivAv2C5_A 7 |
| #define MSK32Gbl_avPllCtl_avPllDivAv2C5_A 0x001FC000 |
| #define BA_Gbl_avPllCtl_avPllDivAv2C6_A 0x0086 |
| #define B16Gbl_avPllCtl_avPllDivAv2C6_A 0x0086 |
| #define LSb32Gbl_avPllCtl_avPllDivAv2C6_A 21 |
| #define LSb16Gbl_avPllCtl_avPllDivAv2C6_A 5 |
| #define bGbl_avPllCtl_avPllDivAv2C6_A 7 |
| #define MSK32Gbl_avPllCtl_avPllDivAv2C6_A 0x0FE00000 |
| #define RA_Gbl_avPllCtl14 0x0088 |
| #define BA_Gbl_avPllCtl_avPllDivAv2C7_A 0x0088 |
| #define B16Gbl_avPllCtl_avPllDivAv2C7_A 0x0088 |
| #define LSb32Gbl_avPllCtl_avPllDivAv2C7_A 0 |
| #define LSb16Gbl_avPllCtl_avPllDivAv2C7_A 0 |
| #define bGbl_avPllCtl_avPllDivAv2C7_A 7 |
| #define MSK32Gbl_avPllCtl_avPllDivAv2C7_A 0x0000007F |
| #define BA_Gbl_avPllCtl_avPllDivAv3C1_A 0x0088 |
| #define B16Gbl_avPllCtl_avPllDivAv3C1_A 0x0088 |
| #define LSb32Gbl_avPllCtl_avPllDivAv3C1_A 7 |
| #define LSb16Gbl_avPllCtl_avPllDivAv3C1_A 7 |
| #define bGbl_avPllCtl_avPllDivAv3C1_A 4 |
| #define MSK32Gbl_avPllCtl_avPllDivAv3C1_A 0x00000780 |
| #define BA_Gbl_avPllCtl_avPllDivAv3C2_A 0x0089 |
| #define B16Gbl_avPllCtl_avPllDivAv3C2_A 0x0088 |
| #define LSb32Gbl_avPllCtl_avPllDivAv3C2_A 11 |
| #define LSb16Gbl_avPllCtl_avPllDivAv3C2_A 11 |
| #define bGbl_avPllCtl_avPllDivAv3C2_A 4 |
| #define MSK32Gbl_avPllCtl_avPllDivAv3C2_A 0x00007800 |
| #define BA_Gbl_avPllCtl_avPllDivAv3C3_A 0x0089 |
| #define B16Gbl_avPllCtl_avPllDivAv3C3_A 0x0088 |
| #define LSb32Gbl_avPllCtl_avPllDivAv3C3_A 15 |
| #define LSb16Gbl_avPllCtl_avPllDivAv3C3_A 15 |
| #define bGbl_avPllCtl_avPllDivAv3C3_A 4 |
| #define MSK32Gbl_avPllCtl_avPllDivAv3C3_A 0x00078000 |
| #define BA_Gbl_avPllCtl_avPllDivAv3C4_A 0x008A |
| #define B16Gbl_avPllCtl_avPllDivAv3C4_A 0x008A |
| #define LSb32Gbl_avPllCtl_avPllDivAv3C4_A 19 |
| #define LSb16Gbl_avPllCtl_avPllDivAv3C4_A 3 |
| #define bGbl_avPllCtl_avPllDivAv3C4_A 4 |
| #define MSK32Gbl_avPllCtl_avPllDivAv3C4_A 0x00780000 |
| #define BA_Gbl_avPllCtl_avPllDivAv3C5_A 0x008A |
| #define B16Gbl_avPllCtl_avPllDivAv3C5_A 0x008A |
| #define LSb32Gbl_avPllCtl_avPllDivAv3C5_A 23 |
| #define LSb16Gbl_avPllCtl_avPllDivAv3C5_A 7 |
| #define bGbl_avPllCtl_avPllDivAv3C5_A 4 |
| #define MSK32Gbl_avPllCtl_avPllDivAv3C5_A 0x07800000 |
| #define BA_Gbl_avPllCtl_avPllDivAv3C6_A 0x008B |
| #define B16Gbl_avPllCtl_avPllDivAv3C6_A 0x008A |
| #define LSb32Gbl_avPllCtl_avPllDivAv3C6_A 27 |
| #define LSb16Gbl_avPllCtl_avPllDivAv3C6_A 11 |
| #define bGbl_avPllCtl_avPllDivAv3C6_A 4 |
| #define MSK32Gbl_avPllCtl_avPllDivAv3C6_A 0x78000000 |
| #define RA_Gbl_avPllCtl15 0x008C |
| #define BA_Gbl_avPllCtl_avPllDivAv3C7_A 0x008C |
| #define B16Gbl_avPllCtl_avPllDivAv3C7_A 0x008C |
| #define LSb32Gbl_avPllCtl_avPllDivAv3C7_A 0 |
| #define LSb16Gbl_avPllCtl_avPllDivAv3C7_A 0 |
| #define bGbl_avPllCtl_avPllDivAv3C7_A 4 |
| #define MSK32Gbl_avPllCtl_avPllDivAv3C7_A 0x0000000F |
| #define BA_Gbl_avPllCtl_avPllPSync1C1_A 0x008C |
| #define B16Gbl_avPllCtl_avPllPSync1C1_A 0x008C |
| #define LSb32Gbl_avPllCtl_avPllPSync1C1_A 4 |
| #define LSb16Gbl_avPllCtl_avPllPSync1C1_A 4 |
| #define bGbl_avPllCtl_avPllPSync1C1_A 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync1C1_A 0x001FFFF0 |
| #define RA_Gbl_avPllCtl16 0x0090 |
| #define BA_Gbl_avPllCtl_avPllPSync1C2_A 0x0090 |
| #define B16Gbl_avPllCtl_avPllPSync1C2_A 0x0090 |
| #define LSb32Gbl_avPllCtl_avPllPSync1C2_A 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync1C2_A 0 |
| #define bGbl_avPllCtl_avPllPSync1C2_A 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync1C2_A 0x0001FFFF |
| #define RA_Gbl_avPllCtl17 0x0094 |
| #define BA_Gbl_avPllCtl_avPllPSync1C3_A 0x0094 |
| #define B16Gbl_avPllCtl_avPllPSync1C3_A 0x0094 |
| #define LSb32Gbl_avPllCtl_avPllPSync1C3_A 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync1C3_A 0 |
| #define bGbl_avPllCtl_avPllPSync1C3_A 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync1C3_A 0x0001FFFF |
| #define RA_Gbl_avPllCtl18 0x0098 |
| #define BA_Gbl_avPllCtl_avPllPSync1C4_A 0x0098 |
| #define B16Gbl_avPllCtl_avPllPSync1C4_A 0x0098 |
| #define LSb32Gbl_avPllCtl_avPllPSync1C4_A 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync1C4_A 0 |
| #define bGbl_avPllCtl_avPllPSync1C4_A 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync1C4_A 0x0001FFFF |
| #define RA_Gbl_avPllCtl19 0x009C |
| #define BA_Gbl_avPllCtl_avPllPSync1C5_A 0x009C |
| #define B16Gbl_avPllCtl_avPllPSync1C5_A 0x009C |
| #define LSb32Gbl_avPllCtl_avPllPSync1C5_A 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync1C5_A 0 |
| #define bGbl_avPllCtl_avPllPSync1C5_A 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync1C5_A 0x0001FFFF |
| #define RA_Gbl_avPllCtl20 0x00A0 |
| #define BA_Gbl_avPllCtl_avPllPSync1C6_A 0x00A0 |
| #define B16Gbl_avPllCtl_avPllPSync1C6_A 0x00A0 |
| #define LSb32Gbl_avPllCtl_avPllPSync1C6_A 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync1C6_A 0 |
| #define bGbl_avPllCtl_avPllPSync1C6_A 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync1C6_A 0x0001FFFF |
| #define RA_Gbl_avPllCtl21 0x00A4 |
| #define BA_Gbl_avPllCtl_avPllPSync1C7_A 0x00A4 |
| #define B16Gbl_avPllCtl_avPllPSync1C7_A 0x00A4 |
| #define LSb32Gbl_avPllCtl_avPllPSync1C7_A 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync1C7_A 0 |
| #define bGbl_avPllCtl_avPllPSync1C7_A 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync1C7_A 0x0001FFFF |
| #define RA_Gbl_avPllCtl22 0x00A8 |
| #define BA_Gbl_avPllCtl_avPllPSync1C8_A 0x00A8 |
| #define B16Gbl_avPllCtl_avPllPSync1C8_A 0x00A8 |
| #define LSb32Gbl_avPllCtl_avPllPSync1C8_A 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync1C8_A 0 |
| #define bGbl_avPllCtl_avPllPSync1C8_A 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync1C8_A 0x0001FFFF |
| #define RA_Gbl_avPllCtl23 0x00AC |
| #define BA_Gbl_avPllCtl_avPllPSync2C1_A 0x00AC |
| #define B16Gbl_avPllCtl_avPllPSync2C1_A 0x00AC |
| #define LSb32Gbl_avPllCtl_avPllPSync2C1_A 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync2C1_A 0 |
| #define bGbl_avPllCtl_avPllPSync2C1_A 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync2C1_A 0x0001FFFF |
| #define RA_Gbl_avPllCtl24 0x00B0 |
| #define BA_Gbl_avPllCtl_avPllPSync2C2_A 0x00B0 |
| #define B16Gbl_avPllCtl_avPllPSync2C2_A 0x00B0 |
| #define LSb32Gbl_avPllCtl_avPllPSync2C2_A 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync2C2_A 0 |
| #define bGbl_avPllCtl_avPllPSync2C2_A 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync2C2_A 0x0001FFFF |
| #define RA_Gbl_avPllCtl25 0x00B4 |
| #define BA_Gbl_avPllCtl_avPllPSync2C3_A 0x00B4 |
| #define B16Gbl_avPllCtl_avPllPSync2C3_A 0x00B4 |
| #define LSb32Gbl_avPllCtl_avPllPSync2C3_A 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync2C3_A 0 |
| #define bGbl_avPllCtl_avPllPSync2C3_A 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync2C3_A 0x0001FFFF |
| #define RA_Gbl_avPllCtl26 0x00B8 |
| #define BA_Gbl_avPllCtl_avPllPSync2C4_A 0x00B8 |
| #define B16Gbl_avPllCtl_avPllPSync2C4_A 0x00B8 |
| #define LSb32Gbl_avPllCtl_avPllPSync2C4_A 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync2C4_A 0 |
| #define bGbl_avPllCtl_avPllPSync2C4_A 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync2C4_A 0x0001FFFF |
| #define RA_Gbl_avPllCtl27 0x00BC |
| #define BA_Gbl_avPllCtl_avPllPSync2C5_A 0x00BC |
| #define B16Gbl_avPllCtl_avPllPSync2C5_A 0x00BC |
| #define LSb32Gbl_avPllCtl_avPllPSync2C5_A 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync2C5_A 0 |
| #define bGbl_avPllCtl_avPllPSync2C5_A 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync2C5_A 0x0001FFFF |
| #define RA_Gbl_avPllCtl28 0x00C0 |
| #define BA_Gbl_avPllCtl_avPllPSync2C6_A 0x00C0 |
| #define B16Gbl_avPllCtl_avPllPSync2C6_A 0x00C0 |
| #define LSb32Gbl_avPllCtl_avPllPSync2C6_A 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync2C6_A 0 |
| #define bGbl_avPllCtl_avPllPSync2C6_A 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync2C6_A 0x0001FFFF |
| #define RA_Gbl_avPllCtl29 0x00C4 |
| #define BA_Gbl_avPllCtl_avPllPSync2C7_A 0x00C4 |
| #define B16Gbl_avPllCtl_avPllPSync2C7_A 0x00C4 |
| #define LSb32Gbl_avPllCtl_avPllPSync2C7_A 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync2C7_A 0 |
| #define bGbl_avPllCtl_avPllPSync2C7_A 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync2C7_A 0x0001FFFF |
| #define RA_Gbl_avPllCtl30 0x00C8 |
| #define BA_Gbl_avPllCtl_avPllPSync2C8_A 0x00C8 |
| #define B16Gbl_avPllCtl_avPllPSync2C8_A 0x00C8 |
| #define LSb32Gbl_avPllCtl_avPllPSync2C8_A 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync2C8_A 0 |
| #define bGbl_avPllCtl_avPllPSync2C8_A 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync2C8_A 0x0001FFFF |
| #define BA_Gbl_avPllCtl_avPllEnDpllC_A 0x00CA |
| #define B16Gbl_avPllCtl_avPllEnDpllC_A 0x00CA |
| #define LSb32Gbl_avPllCtl_avPllEnDpllC_A 17 |
| #define LSb16Gbl_avPllCtl_avPllEnDpllC_A 1 |
| #define bGbl_avPllCtl_avPllEnDpllC_A 8 |
| #define MSK32Gbl_avPllCtl_avPllEnDpllC_A 0x01FE0000 |
| #define BA_Gbl_avPllCtl_avPllMasterSlaveB_A 0x00CB |
| #define B16Gbl_avPllCtl_avPllMasterSlaveB_A 0x00CA |
| #define LSb32Gbl_avPllCtl_avPllMasterSlaveB_A 25 |
| #define LSb16Gbl_avPllCtl_avPllMasterSlaveB_A 9 |
| #define bGbl_avPllCtl_avPllMasterSlaveB_A 1 |
| #define MSK32Gbl_avPllCtl_avPllMasterSlaveB_A 0x02000000 |
| #define BA_Gbl_avPllCtl_avPllTestAna_A 0x00CB |
| #define B16Gbl_avPllCtl_avPllTestAna_A 0x00CA |
| #define LSb32Gbl_avPllCtl_avPllTestAna_A 26 |
| #define LSb16Gbl_avPllCtl_avPllTestAna_A 10 |
| #define bGbl_avPllCtl_avPllTestAna_A 6 |
| #define MSK32Gbl_avPllCtl_avPllTestAna_A 0xFC000000 |
| #define RA_Gbl_avPllCtl31 0x00CC |
| #define BA_Gbl_avPllCtl_avPllReservePll_A 0x00CC |
| #define B16Gbl_avPllCtl_avPllReservePll_A 0x00CC |
| #define LSb32Gbl_avPllCtl_avPllReservePll_A 0 |
| #define LSb16Gbl_avPllCtl_avPllReservePll_A 0 |
| #define bGbl_avPllCtl_avPllReservePll_A 4 |
| #define MSK32Gbl_avPllCtl_avPllReservePll_A 0x0000000F |
| #define BA_Gbl_avPllCtl_avPllResetPll_B 0x00CC |
| #define B16Gbl_avPllCtl_avPllResetPll_B 0x00CC |
| #define LSb32Gbl_avPllCtl_avPllResetPll_B 4 |
| #define LSb16Gbl_avPllCtl_avPllResetPll_B 4 |
| #define bGbl_avPllCtl_avPllResetPll_B 1 |
| #define MSK32Gbl_avPllCtl_avPllResetPll_B 0x00000010 |
| #define BA_Gbl_avPllCtl_avPllPu_B 0x00CC |
| #define B16Gbl_avPllCtl_avPllPu_B 0x00CC |
| #define LSb32Gbl_avPllCtl_avPllPu_B 5 |
| #define LSb16Gbl_avPllCtl_avPllPu_B 5 |
| #define bGbl_avPllCtl_avPllPu_B 1 |
| #define MSK32Gbl_avPllCtl_avPllPu_B 0x00000020 |
| #define BA_Gbl_avPllCtl_avPllIntpi_B 0x00CC |
| #define B16Gbl_avPllCtl_avPllIntpi_B 0x00CC |
| #define LSb32Gbl_avPllCtl_avPllIntpi_B 6 |
| #define LSb16Gbl_avPllCtl_avPllIntpi_B 6 |
| #define bGbl_avPllCtl_avPllIntpi_B 4 |
| #define MSK32Gbl_avPllCtl_avPllIntpi_B 0x000003C0 |
| #define BA_Gbl_avPllCtl_avPllVddr1p45V_B 0x00CD |
| #define B16Gbl_avPllCtl_avPllVddr1p45V_B 0x00CC |
| #define LSb32Gbl_avPllCtl_avPllVddr1p45V_B 10 |
| #define LSb16Gbl_avPllCtl_avPllVddr1p45V_B 10 |
| #define bGbl_avPllCtl_avPllVddr1p45V_B 2 |
| #define MSK32Gbl_avPllCtl_avPllVddr1p45V_B 0x00000C00 |
| #define BA_Gbl_avPllCtl_avPllVddr0p9V_B 0x00CD |
| #define B16Gbl_avPllCtl_avPllVddr0p9V_B 0x00CC |
| #define LSb32Gbl_avPllCtl_avPllVddr0p9V_B 12 |
| #define LSb16Gbl_avPllCtl_avPllVddr0p9V_B 12 |
| #define bGbl_avPllCtl_avPllVddr0p9V_B 4 |
| #define MSK32Gbl_avPllCtl_avPllVddr0p9V_B 0x0000F000 |
| #define BA_Gbl_avPllCtl_avPllVthVcoCal_B 0x00CE |
| #define B16Gbl_avPllCtl_avPllVthVcoCal_B 0x00CE |
| #define LSb32Gbl_avPllCtl_avPllVthVcoCal_B 16 |
| #define LSb16Gbl_avPllCtl_avPllVthVcoCal_B 0 |
| #define bGbl_avPllCtl_avPllVthVcoCal_B 2 |
| #define MSK32Gbl_avPllCtl_avPllVthVcoCal_B 0x00030000 |
| #define BA_Gbl_avPllCtl_avPllKvcoExt_B 0x00CE |
| #define B16Gbl_avPllCtl_avPllKvcoExt_B 0x00CE |
| #define LSb32Gbl_avPllCtl_avPllKvcoExt_B 18 |
| #define LSb16Gbl_avPllCtl_avPllKvcoExt_B 2 |
| #define bGbl_avPllCtl_avPllKvcoExt_B 3 |
| #define MSK32Gbl_avPllCtl_avPllKvcoExt_B 0x001C0000 |
| #define BA_Gbl_avPllCtl_avPllKvcoExtEn_B 0x00CE |
| #define B16Gbl_avPllCtl_avPllKvcoExtEn_B 0x00CE |
| #define LSb32Gbl_avPllCtl_avPllKvcoExtEn_B 21 |
| #define LSb16Gbl_avPllCtl_avPllKvcoExtEn_B 5 |
| #define bGbl_avPllCtl_avPllKvcoExtEn_B 1 |
| #define MSK32Gbl_avPllCtl_avPllKvcoExtEn_B 0x00200000 |
| #define BA_Gbl_avPllCtl_avPllV2iExt_B 0x00CE |
| #define B16Gbl_avPllCtl_avPllV2iExt_B 0x00CE |
| #define LSb32Gbl_avPllCtl_avPllV2iExt_B 22 |
| #define LSb16Gbl_avPllCtl_avPllV2iExt_B 6 |
| #define bGbl_avPllCtl_avPllV2iExt_B 4 |
| #define MSK32Gbl_avPllCtl_avPllV2iExt_B 0x03C00000 |
| #define BA_Gbl_avPllCtl_avPllV2iExtEn_B 0x00CF |
| #define B16Gbl_avPllCtl_avPllV2iExtEn_B 0x00CE |
| #define LSb32Gbl_avPllCtl_avPllV2iExtEn_B 26 |
| #define LSb16Gbl_avPllCtl_avPllV2iExtEn_B 10 |
| #define bGbl_avPllCtl_avPllV2iExtEn_B 1 |
| #define MSK32Gbl_avPllCtl_avPllV2iExtEn_B 0x04000000 |
| #define BA_Gbl_avPllCtl_avPllSpeed_B 0x00CF |
| #define B16Gbl_avPllCtl_avPllSpeed_B 0x00CE |
| #define LSb32Gbl_avPllCtl_avPllSpeed_B 27 |
| #define LSb16Gbl_avPllCtl_avPllSpeed_B 11 |
| #define bGbl_avPllCtl_avPllSpeed_B 3 |
| #define MSK32Gbl_avPllCtl_avPllSpeed_B 0x38000000 |
| #define BA_Gbl_avPllCtl_avPllClkDetEn_B 0x00CF |
| #define B16Gbl_avPllCtl_avPllClkDetEn_B 0x00CE |
| #define LSb32Gbl_avPllCtl_avPllClkDetEn_B 30 |
| #define LSb16Gbl_avPllCtl_avPllClkDetEn_B 14 |
| #define bGbl_avPllCtl_avPllClkDetEn_B 1 |
| #define MSK32Gbl_avPllCtl_avPllClkDetEn_B 0x40000000 |
| #define RA_Gbl_avPllCtl32 0x00D0 |
| #define BA_Gbl_avPllCtl_avPllRefDiv_B 0x00D0 |
| #define B16Gbl_avPllCtl_avPllRefDiv_B 0x00D0 |
| #define LSb32Gbl_avPllCtl_avPllRefDiv_B 0 |
| #define LSb16Gbl_avPllCtl_avPllRefDiv_B 0 |
| #define bGbl_avPllCtl_avPllRefDiv_B 6 |
| #define MSK32Gbl_avPllCtl_avPllRefDiv_B 0x0000003F |
| #define BA_Gbl_avPllCtl_avPllFbDiv_B 0x00D0 |
| #define B16Gbl_avPllCtl_avPllFbDiv_B 0x00D0 |
| #define LSb32Gbl_avPllCtl_avPllFbDiv_B 6 |
| #define LSb16Gbl_avPllCtl_avPllFbDiv_B 6 |
| #define bGbl_avPllCtl_avPllFbDiv_B 8 |
| #define MSK32Gbl_avPllCtl_avPllFbDiv_B 0x00003FC0 |
| #define BA_Gbl_avPllCtl_avPllIcp_B 0x00D1 |
| #define B16Gbl_avPllCtl_avPllIcp_B 0x00D0 |
| #define LSb32Gbl_avPllCtl_avPllIcp_B 14 |
| #define LSb16Gbl_avPllCtl_avPllIcp_B 14 |
| #define bGbl_avPllCtl_avPllIcp_B 4 |
| #define MSK32Gbl_avPllCtl_avPllIcp_B 0x0003C000 |
| #define BA_Gbl_avPllCtl_avPllLoadCap_B 0x00D2 |
| #define B16Gbl_avPllCtl_avPllLoadCap_B 0x00D2 |
| #define LSb32Gbl_avPllCtl_avPllLoadCap_B 18 |
| #define LSb16Gbl_avPllCtl_avPllLoadCap_B 2 |
| #define bGbl_avPllCtl_avPllLoadCap_B 1 |
| #define MSK32Gbl_avPllCtl_avPllLoadCap_B 0x00040000 |
| #define BA_Gbl_avPllCtl_avPllPllCaliStart_B 0x00D2 |
| #define B16Gbl_avPllCtl_avPllPllCaliStart_B 0x00D2 |
| #define LSb32Gbl_avPllCtl_avPllPllCaliStart_B 19 |
| #define LSb16Gbl_avPllCtl_avPllPllCaliStart_B 3 |
| #define bGbl_avPllCtl_avPllPllCaliStart_B 1 |
| #define MSK32Gbl_avPllCtl_avPllPllCaliStart_B 0x00080000 |
| #define RA_Gbl_avPllCtl33 0x00D4 |
| #define BA_Gbl_avPllCtl_avPllFreqOffsetC1_B 0x00D4 |
| #define B16Gbl_avPllCtl_avPllFreqOffsetC1_B 0x00D4 |
| #define LSb32Gbl_avPllCtl_avPllFreqOffsetC1_B 0 |
| #define LSb16Gbl_avPllCtl_avPllFreqOffsetC1_B 0 |
| #define bGbl_avPllCtl_avPllFreqOffsetC1_B 19 |
| #define MSK32Gbl_avPllCtl_avPllFreqOffsetC1_B 0x0007FFFF |
| #define RA_Gbl_avPllCtl34 0x00D8 |
| #define BA_Gbl_avPllCtl_avPllFreqOffsetC2_B 0x00D8 |
| #define B16Gbl_avPllCtl_avPllFreqOffsetC2_B 0x00D8 |
| #define LSb32Gbl_avPllCtl_avPllFreqOffsetC2_B 0 |
| #define LSb16Gbl_avPllCtl_avPllFreqOffsetC2_B 0 |
| #define bGbl_avPllCtl_avPllFreqOffsetC2_B 19 |
| #define MSK32Gbl_avPllCtl_avPllFreqOffsetC2_B 0x0007FFFF |
| #define RA_Gbl_avPllCtl35 0x00DC |
| #define BA_Gbl_avPllCtl_avPllFreqOffsetC3_B 0x00DC |
| #define B16Gbl_avPllCtl_avPllFreqOffsetC3_B 0x00DC |
| #define LSb32Gbl_avPllCtl_avPllFreqOffsetC3_B 0 |
| #define LSb16Gbl_avPllCtl_avPllFreqOffsetC3_B 0 |
| #define bGbl_avPllCtl_avPllFreqOffsetC3_B 19 |
| #define MSK32Gbl_avPllCtl_avPllFreqOffsetC3_B 0x0007FFFF |
| #define RA_Gbl_avPllCtl36 0x00E0 |
| #define BA_Gbl_avPllCtl_avPllFreqOffsetC4_B 0x00E0 |
| #define B16Gbl_avPllCtl_avPllFreqOffsetC4_B 0x00E0 |
| #define LSb32Gbl_avPllCtl_avPllFreqOffsetC4_B 0 |
| #define LSb16Gbl_avPllCtl_avPllFreqOffsetC4_B 0 |
| #define bGbl_avPllCtl_avPllFreqOffsetC4_B 19 |
| #define MSK32Gbl_avPllCtl_avPllFreqOffsetC4_B 0x0007FFFF |
| #define RA_Gbl_avPllCtl37 0x00E4 |
| #define BA_Gbl_avPllCtl_avPllFreqOffsetC5_B 0x00E4 |
| #define B16Gbl_avPllCtl_avPllFreqOffsetC5_B 0x00E4 |
| #define LSb32Gbl_avPllCtl_avPllFreqOffsetC5_B 0 |
| #define LSb16Gbl_avPllCtl_avPllFreqOffsetC5_B 0 |
| #define bGbl_avPllCtl_avPllFreqOffsetC5_B 19 |
| #define MSK32Gbl_avPllCtl_avPllFreqOffsetC5_B 0x0007FFFF |
| #define RA_Gbl_avPllCtl38 0x00E8 |
| #define BA_Gbl_avPllCtl_avPllFreqOffsetC6_B 0x00E8 |
| #define B16Gbl_avPllCtl_avPllFreqOffsetC6_B 0x00E8 |
| #define LSb32Gbl_avPllCtl_avPllFreqOffsetC6_B 0 |
| #define LSb16Gbl_avPllCtl_avPllFreqOffsetC6_B 0 |
| #define bGbl_avPllCtl_avPllFreqOffsetC6_B 19 |
| #define MSK32Gbl_avPllCtl_avPllFreqOffsetC6_B 0x0007FFFF |
| #define RA_Gbl_avPllCtl39 0x00EC |
| #define BA_Gbl_avPllCtl_avPllFreqOffsetC7_B 0x00EC |
| #define B16Gbl_avPllCtl_avPllFreqOffsetC7_B 0x00EC |
| #define LSb32Gbl_avPllCtl_avPllFreqOffsetC7_B 0 |
| #define LSb16Gbl_avPllCtl_avPllFreqOffsetC7_B 0 |
| #define bGbl_avPllCtl_avPllFreqOffsetC7_B 19 |
| #define MSK32Gbl_avPllCtl_avPllFreqOffsetC7_B 0x0007FFFF |
| #define RA_Gbl_avPllCtl40 0x00F0 |
| #define BA_Gbl_avPllCtl_avPllFreqOffsetC8_B 0x00F0 |
| #define B16Gbl_avPllCtl_avPllFreqOffsetC8_B 0x00F0 |
| #define LSb32Gbl_avPllCtl_avPllFreqOffsetC8_B 0 |
| #define LSb16Gbl_avPllCtl_avPllFreqOffsetC8_B 0 |
| #define bGbl_avPllCtl_avPllFreqOffsetC8_B 19 |
| #define MSK32Gbl_avPllCtl_avPllFreqOffsetC8_B 0x0007FFFF |
| #define BA_Gbl_avPllCtl_avPllFreqOffsetReadyC_B 0x00F2 |
| #define B16Gbl_avPllCtl_avPllFreqOffsetReadyC_B 0x00F2 |
| #define LSb32Gbl_avPllCtl_avPllFreqOffsetReadyC_B 19 |
| #define LSb16Gbl_avPllCtl_avPllFreqOffsetReadyC_B 3 |
| #define bGbl_avPllCtl_avPllFreqOffsetReadyC_B 8 |
| #define MSK32Gbl_avPllCtl_avPllFreqOffsetReadyC_B 0x07F80000 |
| #define BA_Gbl_avPllCtl_avPllReserveC1_B 0x00F3 |
| #define B16Gbl_avPllCtl_avPllReserveC1_B 0x00F2 |
| #define LSb32Gbl_avPllCtl_avPllReserveC1_B 27 |
| #define LSb16Gbl_avPllCtl_avPllReserveC1_B 11 |
| #define bGbl_avPllCtl_avPllReserveC1_B 2 |
| #define MSK32Gbl_avPllCtl_avPllReserveC1_B 0x18000000 |
| #define BA_Gbl_avPllCtl_avPllReserveC2_B 0x00F3 |
| #define B16Gbl_avPllCtl_avPllReserveC2_B 0x00F2 |
| #define LSb32Gbl_avPllCtl_avPllReserveC2_B 29 |
| #define LSb16Gbl_avPllCtl_avPllReserveC2_B 13 |
| #define bGbl_avPllCtl_avPllReserveC2_B 2 |
| #define MSK32Gbl_avPllCtl_avPllReserveC2_B 0x60000000 |
| #define RA_Gbl_avPllCtl41 0x00F4 |
| #define BA_Gbl_avPllCtl_avPllReserveC3_B 0x00F4 |
| #define B16Gbl_avPllCtl_avPllReserveC3_B 0x00F4 |
| #define LSb32Gbl_avPllCtl_avPllReserveC3_B 0 |
| #define LSb16Gbl_avPllCtl_avPllReserveC3_B 0 |
| #define bGbl_avPllCtl_avPllReserveC3_B 2 |
| #define MSK32Gbl_avPllCtl_avPllReserveC3_B 0x00000003 |
| #define BA_Gbl_avPllCtl_avPllReserveC4_B 0x00F4 |
| #define B16Gbl_avPllCtl_avPllReserveC4_B 0x00F4 |
| #define LSb32Gbl_avPllCtl_avPllReserveC4_B 2 |
| #define LSb16Gbl_avPllCtl_avPllReserveC4_B 2 |
| #define bGbl_avPllCtl_avPllReserveC4_B 2 |
| #define MSK32Gbl_avPllCtl_avPllReserveC4_B 0x0000000C |
| #define BA_Gbl_avPllCtl_avPllReserveC5_B 0x00F4 |
| #define B16Gbl_avPllCtl_avPllReserveC5_B 0x00F4 |
| #define LSb32Gbl_avPllCtl_avPllReserveC5_B 4 |
| #define LSb16Gbl_avPllCtl_avPllReserveC5_B 4 |
| #define bGbl_avPllCtl_avPllReserveC5_B 2 |
| #define MSK32Gbl_avPllCtl_avPllReserveC5_B 0x00000030 |
| #define BA_Gbl_avPllCtl_avPllReserveC6_B 0x00F4 |
| #define B16Gbl_avPllCtl_avPllReserveC6_B 0x00F4 |
| #define LSb32Gbl_avPllCtl_avPllReserveC6_B 6 |
| #define LSb16Gbl_avPllCtl_avPllReserveC6_B 6 |
| #define bGbl_avPllCtl_avPllReserveC6_B 2 |
| #define MSK32Gbl_avPllCtl_avPllReserveC6_B 0x000000C0 |
| #define BA_Gbl_avPllCtl_avPllReserveC7_B 0x00F5 |
| #define B16Gbl_avPllCtl_avPllReserveC7_B 0x00F4 |
| #define LSb32Gbl_avPllCtl_avPllReserveC7_B 8 |
| #define LSb16Gbl_avPllCtl_avPllReserveC7_B 8 |
| #define bGbl_avPllCtl_avPllReserveC7_B 2 |
| #define MSK32Gbl_avPllCtl_avPllReserveC7_B 0x00000300 |
| #define BA_Gbl_avPllCtl_avPllReserveC8_B 0x00F5 |
| #define B16Gbl_avPllCtl_avPllReserveC8_B 0x00F4 |
| #define LSb32Gbl_avPllCtl_avPllReserveC8_B 10 |
| #define LSb16Gbl_avPllCtl_avPllReserveC8_B 10 |
| #define bGbl_avPllCtl_avPllReserveC8_B 2 |
| #define MSK32Gbl_avPllCtl_avPllReserveC8_B 0x00000C00 |
| #define BA_Gbl_avPllCtl_avPllEnLpC_B 0x00F5 |
| #define B16Gbl_avPllCtl_avPllEnLpC_B 0x00F4 |
| #define LSb32Gbl_avPllCtl_avPllEnLpC_B 12 |
| #define LSb16Gbl_avPllCtl_avPllEnLpC_B 12 |
| #define bGbl_avPllCtl_avPllEnLpC_B 8 |
| #define MSK32Gbl_avPllCtl_avPllEnLpC_B 0x000FF000 |
| #define BA_Gbl_avPllCtl_avPllPuC_B 0x00F6 |
| #define B16Gbl_avPllCtl_avPllPuC_B 0x00F6 |
| #define LSb32Gbl_avPllCtl_avPllPuC_B 20 |
| #define LSb16Gbl_avPllCtl_avPllPuC_B 4 |
| #define bGbl_avPllCtl_avPllPuC_B 7 |
| #define MSK32Gbl_avPllCtl_avPllPuC_B 0x07F00000 |
| #define RA_Gbl_avPllCtl42 0x00F8 |
| #define BA_Gbl_avPllCtl_avPllResetC_B 0x00F8 |
| #define B16Gbl_avPllCtl_avPllResetC_B 0x00F8 |
| #define LSb32Gbl_avPllCtl_avPllResetC_B 0 |
| #define LSb16Gbl_avPllCtl_avPllResetC_B 0 |
| #define bGbl_avPllCtl_avPllResetC_B 7 |
| #define MSK32Gbl_avPllCtl_avPllResetC_B 0x0000007F |
| #define BA_Gbl_avPllCtl_avPllDivHdmiC1_B 0x00F8 |
| #define B16Gbl_avPllCtl_avPllDivHdmiC1_B 0x00F8 |
| #define LSb32Gbl_avPllCtl_avPllDivHdmiC1_B 7 |
| #define LSb16Gbl_avPllCtl_avPllDivHdmiC1_B 7 |
| #define bGbl_avPllCtl_avPllDivHdmiC1_B 3 |
| #define MSK32Gbl_avPllCtl_avPllDivHdmiC1_B 0x00000380 |
| #define BA_Gbl_avPllCtl_avPllDivHdmiC2_B 0x00F9 |
| #define B16Gbl_avPllCtl_avPllDivHdmiC2_B 0x00F8 |
| #define LSb32Gbl_avPllCtl_avPllDivHdmiC2_B 10 |
| #define LSb16Gbl_avPllCtl_avPllDivHdmiC2_B 10 |
| #define bGbl_avPllCtl_avPllDivHdmiC2_B 3 |
| #define MSK32Gbl_avPllCtl_avPllDivHdmiC2_B 0x00001C00 |
| #define BA_Gbl_avPllCtl_avPllDivHdmiC3_B 0x00F9 |
| #define B16Gbl_avPllCtl_avPllDivHdmiC3_B 0x00F8 |
| #define LSb32Gbl_avPllCtl_avPllDivHdmiC3_B 13 |
| #define LSb16Gbl_avPllCtl_avPllDivHdmiC3_B 13 |
| #define bGbl_avPllCtl_avPllDivHdmiC3_B 3 |
| #define MSK32Gbl_avPllCtl_avPllDivHdmiC3_B 0x0000E000 |
| #define BA_Gbl_avPllCtl_avPllDivHdmiC4_B 0x00FA |
| #define B16Gbl_avPllCtl_avPllDivHdmiC4_B 0x00FA |
| #define LSb32Gbl_avPllCtl_avPllDivHdmiC4_B 16 |
| #define LSb16Gbl_avPllCtl_avPllDivHdmiC4_B 0 |
| #define bGbl_avPllCtl_avPllDivHdmiC4_B 3 |
| #define MSK32Gbl_avPllCtl_avPllDivHdmiC4_B 0x00070000 |
| #define BA_Gbl_avPllCtl_avPllDivHdmiC5_B 0x00FA |
| #define B16Gbl_avPllCtl_avPllDivHdmiC5_B 0x00FA |
| #define LSb32Gbl_avPllCtl_avPllDivHdmiC5_B 19 |
| #define LSb16Gbl_avPllCtl_avPllDivHdmiC5_B 3 |
| #define bGbl_avPllCtl_avPllDivHdmiC5_B 3 |
| #define MSK32Gbl_avPllCtl_avPllDivHdmiC5_B 0x00380000 |
| #define BA_Gbl_avPllCtl_avPllDivHdmiC6_B 0x00FA |
| #define B16Gbl_avPllCtl_avPllDivHdmiC6_B 0x00FA |
| #define LSb32Gbl_avPllCtl_avPllDivHdmiC6_B 22 |
| #define LSb16Gbl_avPllCtl_avPllDivHdmiC6_B 6 |
| #define bGbl_avPllCtl_avPllDivHdmiC6_B 3 |
| #define MSK32Gbl_avPllCtl_avPllDivHdmiC6_B 0x01C00000 |
| #define BA_Gbl_avPllCtl_avPllDivHdmiC7_B 0x00FB |
| #define B16Gbl_avPllCtl_avPllDivHdmiC7_B 0x00FA |
| #define LSb32Gbl_avPllCtl_avPllDivHdmiC7_B 25 |
| #define LSb16Gbl_avPllCtl_avPllDivHdmiC7_B 9 |
| #define bGbl_avPllCtl_avPllDivHdmiC7_B 3 |
| #define MSK32Gbl_avPllCtl_avPllDivHdmiC7_B 0x0E000000 |
| #define BA_Gbl_avPllCtl_avPllDivAv1C1_B 0x00FB |
| #define B16Gbl_avPllCtl_avPllDivAv1C1_B 0x00FA |
| #define LSb32Gbl_avPllCtl_avPllDivAv1C1_B 28 |
| #define LSb16Gbl_avPllCtl_avPllDivAv1C1_B 12 |
| #define bGbl_avPllCtl_avPllDivAv1C1_B 3 |
| #define MSK32Gbl_avPllCtl_avPllDivAv1C1_B 0x70000000 |
| #define RA_Gbl_avPllCtl43 0x00FC |
| #define BA_Gbl_avPllCtl_avPllDivAv1C2_B 0x00FC |
| #define B16Gbl_avPllCtl_avPllDivAv1C2_B 0x00FC |
| #define LSb32Gbl_avPllCtl_avPllDivAv1C2_B 0 |
| #define LSb16Gbl_avPllCtl_avPllDivAv1C2_B 0 |
| #define bGbl_avPllCtl_avPllDivAv1C2_B 3 |
| #define MSK32Gbl_avPllCtl_avPllDivAv1C2_B 0x00000007 |
| #define BA_Gbl_avPllCtl_avPllDivAv1C3_B 0x00FC |
| #define B16Gbl_avPllCtl_avPllDivAv1C3_B 0x00FC |
| #define LSb32Gbl_avPllCtl_avPllDivAv1C3_B 3 |
| #define LSb16Gbl_avPllCtl_avPllDivAv1C3_B 3 |
| #define bGbl_avPllCtl_avPllDivAv1C3_B 3 |
| #define MSK32Gbl_avPllCtl_avPllDivAv1C3_B 0x00000038 |
| #define BA_Gbl_avPllCtl_avPllDivAv1C4_B 0x00FC |
| #define B16Gbl_avPllCtl_avPllDivAv1C4_B 0x00FC |
| #define LSb32Gbl_avPllCtl_avPllDivAv1C4_B 6 |
| #define LSb16Gbl_avPllCtl_avPllDivAv1C4_B 6 |
| #define bGbl_avPllCtl_avPllDivAv1C4_B 3 |
| #define MSK32Gbl_avPllCtl_avPllDivAv1C4_B 0x000001C0 |
| #define BA_Gbl_avPllCtl_avPllDivAv1C5_B 0x00FD |
| #define B16Gbl_avPllCtl_avPllDivAv1C5_B 0x00FC |
| #define LSb32Gbl_avPllCtl_avPllDivAv1C5_B 9 |
| #define LSb16Gbl_avPllCtl_avPllDivAv1C5_B 9 |
| #define bGbl_avPllCtl_avPllDivAv1C5_B 3 |
| #define MSK32Gbl_avPllCtl_avPllDivAv1C5_B 0x00000E00 |
| #define BA_Gbl_avPllCtl_avPllDivAv1C6_B 0x00FD |
| #define B16Gbl_avPllCtl_avPllDivAv1C6_B 0x00FC |
| #define LSb32Gbl_avPllCtl_avPllDivAv1C6_B 12 |
| #define LSb16Gbl_avPllCtl_avPllDivAv1C6_B 12 |
| #define bGbl_avPllCtl_avPllDivAv1C6_B 3 |
| #define MSK32Gbl_avPllCtl_avPllDivAv1C6_B 0x00007000 |
| #define BA_Gbl_avPllCtl_avPllDivAv1C7_B 0x00FD |
| #define B16Gbl_avPllCtl_avPllDivAv1C7_B 0x00FC |
| #define LSb32Gbl_avPllCtl_avPllDivAv1C7_B 15 |
| #define LSb16Gbl_avPllCtl_avPllDivAv1C7_B 15 |
| #define bGbl_avPllCtl_avPllDivAv1C7_B 3 |
| #define MSK32Gbl_avPllCtl_avPllDivAv1C7_B 0x00038000 |
| #define BA_Gbl_avPllCtl_avPllDivAv2C1_B 0x00FE |
| #define B16Gbl_avPllCtl_avPllDivAv2C1_B 0x00FE |
| #define LSb32Gbl_avPllCtl_avPllDivAv2C1_B 18 |
| #define LSb16Gbl_avPllCtl_avPllDivAv2C1_B 2 |
| #define bGbl_avPllCtl_avPllDivAv2C1_B 7 |
| #define MSK32Gbl_avPllCtl_avPllDivAv2C1_B 0x01FC0000 |
| #define BA_Gbl_avPllCtl_avPllDivAv2C2_B 0x00FF |
| #define B16Gbl_avPllCtl_avPllDivAv2C2_B 0x00FE |
| #define LSb32Gbl_avPllCtl_avPllDivAv2C2_B 25 |
| #define LSb16Gbl_avPllCtl_avPllDivAv2C2_B 9 |
| #define bGbl_avPllCtl_avPllDivAv2C2_B 7 |
| #define MSK32Gbl_avPllCtl_avPllDivAv2C2_B 0xFE000000 |
| #define RA_Gbl_avPllCtl44 0x0100 |
| #define BA_Gbl_avPllCtl_avPllDivAv2C3_B 0x0100 |
| #define B16Gbl_avPllCtl_avPllDivAv2C3_B 0x0100 |
| #define LSb32Gbl_avPllCtl_avPllDivAv2C3_B 0 |
| #define LSb16Gbl_avPllCtl_avPllDivAv2C3_B 0 |
| #define bGbl_avPllCtl_avPllDivAv2C3_B 7 |
| #define MSK32Gbl_avPllCtl_avPllDivAv2C3_B 0x0000007F |
| #define BA_Gbl_avPllCtl_avPllDivAv2C4_B 0x0100 |
| #define B16Gbl_avPllCtl_avPllDivAv2C4_B 0x0100 |
| #define LSb32Gbl_avPllCtl_avPllDivAv2C4_B 7 |
| #define LSb16Gbl_avPllCtl_avPllDivAv2C4_B 7 |
| #define bGbl_avPllCtl_avPllDivAv2C4_B 7 |
| #define MSK32Gbl_avPllCtl_avPllDivAv2C4_B 0x00003F80 |
| #define BA_Gbl_avPllCtl_avPllDivAv2C5_B 0x0101 |
| #define B16Gbl_avPllCtl_avPllDivAv2C5_B 0x0100 |
| #define LSb32Gbl_avPllCtl_avPllDivAv2C5_B 14 |
| #define LSb16Gbl_avPllCtl_avPllDivAv2C5_B 14 |
| #define bGbl_avPllCtl_avPllDivAv2C5_B 7 |
| #define MSK32Gbl_avPllCtl_avPllDivAv2C5_B 0x001FC000 |
| #define BA_Gbl_avPllCtl_avPllDivAv2C6_B 0x0102 |
| #define B16Gbl_avPllCtl_avPllDivAv2C6_B 0x0102 |
| #define LSb32Gbl_avPllCtl_avPllDivAv2C6_B 21 |
| #define LSb16Gbl_avPllCtl_avPllDivAv2C6_B 5 |
| #define bGbl_avPllCtl_avPllDivAv2C6_B 7 |
| #define MSK32Gbl_avPllCtl_avPllDivAv2C6_B 0x0FE00000 |
| #define RA_Gbl_avPllCtl45 0x0104 |
| #define BA_Gbl_avPllCtl_avPllDivAv2C7_B 0x0104 |
| #define B16Gbl_avPllCtl_avPllDivAv2C7_B 0x0104 |
| #define LSb32Gbl_avPllCtl_avPllDivAv2C7_B 0 |
| #define LSb16Gbl_avPllCtl_avPllDivAv2C7_B 0 |
| #define bGbl_avPllCtl_avPllDivAv2C7_B 7 |
| #define MSK32Gbl_avPllCtl_avPllDivAv2C7_B 0x0000007F |
| #define BA_Gbl_avPllCtl_avPllDivAv3C1_B 0x0104 |
| #define B16Gbl_avPllCtl_avPllDivAv3C1_B 0x0104 |
| #define LSb32Gbl_avPllCtl_avPllDivAv3C1_B 7 |
| #define LSb16Gbl_avPllCtl_avPllDivAv3C1_B 7 |
| #define bGbl_avPllCtl_avPllDivAv3C1_B 4 |
| #define MSK32Gbl_avPllCtl_avPllDivAv3C1_B 0x00000780 |
| #define BA_Gbl_avPllCtl_avPllDivAv3C2_B 0x0105 |
| #define B16Gbl_avPllCtl_avPllDivAv3C2_B 0x0104 |
| #define LSb32Gbl_avPllCtl_avPllDivAv3C2_B 11 |
| #define LSb16Gbl_avPllCtl_avPllDivAv3C2_B 11 |
| #define bGbl_avPllCtl_avPllDivAv3C2_B 4 |
| #define MSK32Gbl_avPllCtl_avPllDivAv3C2_B 0x00007800 |
| #define BA_Gbl_avPllCtl_avPllDivAv3C3_B 0x0105 |
| #define B16Gbl_avPllCtl_avPllDivAv3C3_B 0x0104 |
| #define LSb32Gbl_avPllCtl_avPllDivAv3C3_B 15 |
| #define LSb16Gbl_avPllCtl_avPllDivAv3C3_B 15 |
| #define bGbl_avPllCtl_avPllDivAv3C3_B 4 |
| #define MSK32Gbl_avPllCtl_avPllDivAv3C3_B 0x00078000 |
| #define BA_Gbl_avPllCtl_avPllDivAv3C4_B 0x0106 |
| #define B16Gbl_avPllCtl_avPllDivAv3C4_B 0x0106 |
| #define LSb32Gbl_avPllCtl_avPllDivAv3C4_B 19 |
| #define LSb16Gbl_avPllCtl_avPllDivAv3C4_B 3 |
| #define bGbl_avPllCtl_avPllDivAv3C4_B 4 |
| #define MSK32Gbl_avPllCtl_avPllDivAv3C4_B 0x00780000 |
| #define BA_Gbl_avPllCtl_avPllDivAv3C5_B 0x0106 |
| #define B16Gbl_avPllCtl_avPllDivAv3C5_B 0x0106 |
| #define LSb32Gbl_avPllCtl_avPllDivAv3C5_B 23 |
| #define LSb16Gbl_avPllCtl_avPllDivAv3C5_B 7 |
| #define bGbl_avPllCtl_avPllDivAv3C5_B 4 |
| #define MSK32Gbl_avPllCtl_avPllDivAv3C5_B 0x07800000 |
| #define BA_Gbl_avPllCtl_avPllDivAv3C6_B 0x0107 |
| #define B16Gbl_avPllCtl_avPllDivAv3C6_B 0x0106 |
| #define LSb32Gbl_avPllCtl_avPllDivAv3C6_B 27 |
| #define LSb16Gbl_avPllCtl_avPllDivAv3C6_B 11 |
| #define bGbl_avPllCtl_avPllDivAv3C6_B 4 |
| #define MSK32Gbl_avPllCtl_avPllDivAv3C6_B 0x78000000 |
| #define RA_Gbl_avPllCtl46 0x0108 |
| #define BA_Gbl_avPllCtl_avPllDivAv3C7_B 0x0108 |
| #define B16Gbl_avPllCtl_avPllDivAv3C7_B 0x0108 |
| #define LSb32Gbl_avPllCtl_avPllDivAv3C7_B 0 |
| #define LSb16Gbl_avPllCtl_avPllDivAv3C7_B 0 |
| #define bGbl_avPllCtl_avPllDivAv3C7_B 4 |
| #define MSK32Gbl_avPllCtl_avPllDivAv3C7_B 0x0000000F |
| #define BA_Gbl_avPllCtl_avPllPSync1C1_B 0x0108 |
| #define B16Gbl_avPllCtl_avPllPSync1C1_B 0x0108 |
| #define LSb32Gbl_avPllCtl_avPllPSync1C1_B 4 |
| #define LSb16Gbl_avPllCtl_avPllPSync1C1_B 4 |
| #define bGbl_avPllCtl_avPllPSync1C1_B 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync1C1_B 0x001FFFF0 |
| #define RA_Gbl_avPllCtl47 0x010C |
| #define BA_Gbl_avPllCtl_avPllPSync1C2_B 0x010C |
| #define B16Gbl_avPllCtl_avPllPSync1C2_B 0x010C |
| #define LSb32Gbl_avPllCtl_avPllPSync1C2_B 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync1C2_B 0 |
| #define bGbl_avPllCtl_avPllPSync1C2_B 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync1C2_B 0x0001FFFF |
| #define RA_Gbl_avPllCtl48 0x0110 |
| #define BA_Gbl_avPllCtl_avPllPSync1C3_B 0x0110 |
| #define B16Gbl_avPllCtl_avPllPSync1C3_B 0x0110 |
| #define LSb32Gbl_avPllCtl_avPllPSync1C3_B 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync1C3_B 0 |
| #define bGbl_avPllCtl_avPllPSync1C3_B 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync1C3_B 0x0001FFFF |
| #define RA_Gbl_avPllCtl49 0x0114 |
| #define BA_Gbl_avPllCtl_avPllPSync1C4_B 0x0114 |
| #define B16Gbl_avPllCtl_avPllPSync1C4_B 0x0114 |
| #define LSb32Gbl_avPllCtl_avPllPSync1C4_B 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync1C4_B 0 |
| #define bGbl_avPllCtl_avPllPSync1C4_B 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync1C4_B 0x0001FFFF |
| #define RA_Gbl_avPllCtl50 0x0118 |
| #define BA_Gbl_avPllCtl_avPllPSync1C5_B 0x0118 |
| #define B16Gbl_avPllCtl_avPllPSync1C5_B 0x0118 |
| #define LSb32Gbl_avPllCtl_avPllPSync1C5_B 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync1C5_B 0 |
| #define bGbl_avPllCtl_avPllPSync1C5_B 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync1C5_B 0x0001FFFF |
| #define RA_Gbl_avPllCtl51 0x011C |
| #define BA_Gbl_avPllCtl_avPllPSync1C6_B 0x011C |
| #define B16Gbl_avPllCtl_avPllPSync1C6_B 0x011C |
| #define LSb32Gbl_avPllCtl_avPllPSync1C6_B 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync1C6_B 0 |
| #define bGbl_avPllCtl_avPllPSync1C6_B 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync1C6_B 0x0001FFFF |
| #define RA_Gbl_avPllCtl52 0x0120 |
| #define BA_Gbl_avPllCtl_avPllPSync1C7_B 0x0120 |
| #define B16Gbl_avPllCtl_avPllPSync1C7_B 0x0120 |
| #define LSb32Gbl_avPllCtl_avPllPSync1C7_B 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync1C7_B 0 |
| #define bGbl_avPllCtl_avPllPSync1C7_B 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync1C7_B 0x0001FFFF |
| #define RA_Gbl_avPllCtl53 0x0124 |
| #define BA_Gbl_avPllCtl_avPllPSync1C8_B 0x0124 |
| #define B16Gbl_avPllCtl_avPllPSync1C8_B 0x0124 |
| #define LSb32Gbl_avPllCtl_avPllPSync1C8_B 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync1C8_B 0 |
| #define bGbl_avPllCtl_avPllPSync1C8_B 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync1C8_B 0x0001FFFF |
| #define RA_Gbl_avPllCtl54 0x0128 |
| #define BA_Gbl_avPllCtl_avPllPSync2C1_B 0x0128 |
| #define B16Gbl_avPllCtl_avPllPSync2C1_B 0x0128 |
| #define LSb32Gbl_avPllCtl_avPllPSync2C1_B 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync2C1_B 0 |
| #define bGbl_avPllCtl_avPllPSync2C1_B 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync2C1_B 0x0001FFFF |
| #define RA_Gbl_avPllCtl55 0x012C |
| #define BA_Gbl_avPllCtl_avPllPSync2C2_B 0x012C |
| #define B16Gbl_avPllCtl_avPllPSync2C2_B 0x012C |
| #define LSb32Gbl_avPllCtl_avPllPSync2C2_B 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync2C2_B 0 |
| #define bGbl_avPllCtl_avPllPSync2C2_B 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync2C2_B 0x0001FFFF |
| #define RA_Gbl_avPllCtl56 0x0130 |
| #define BA_Gbl_avPllCtl_avPllPSync2C3_B 0x0130 |
| #define B16Gbl_avPllCtl_avPllPSync2C3_B 0x0130 |
| #define LSb32Gbl_avPllCtl_avPllPSync2C3_B 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync2C3_B 0 |
| #define bGbl_avPllCtl_avPllPSync2C3_B 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync2C3_B 0x0001FFFF |
| #define RA_Gbl_avPllCtl57 0x0134 |
| #define BA_Gbl_avPllCtl_avPllPSync2C4_B 0x0134 |
| #define B16Gbl_avPllCtl_avPllPSync2C4_B 0x0134 |
| #define LSb32Gbl_avPllCtl_avPllPSync2C4_B 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync2C4_B 0 |
| #define bGbl_avPllCtl_avPllPSync2C4_B 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync2C4_B 0x0001FFFF |
| #define RA_Gbl_avPllCtl58 0x0138 |
| #define BA_Gbl_avPllCtl_avPllPSync2C5_B 0x0138 |
| #define B16Gbl_avPllCtl_avPllPSync2C5_B 0x0138 |
| #define LSb32Gbl_avPllCtl_avPllPSync2C5_B 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync2C5_B 0 |
| #define bGbl_avPllCtl_avPllPSync2C5_B 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync2C5_B 0x0001FFFF |
| #define RA_Gbl_avPllCtl59 0x013C |
| #define BA_Gbl_avPllCtl_avPllPSync2C6_B 0x013C |
| #define B16Gbl_avPllCtl_avPllPSync2C6_B 0x013C |
| #define LSb32Gbl_avPllCtl_avPllPSync2C6_B 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync2C6_B 0 |
| #define bGbl_avPllCtl_avPllPSync2C6_B 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync2C6_B 0x0001FFFF |
| #define RA_Gbl_avPllCtl60 0x0140 |
| #define BA_Gbl_avPllCtl_avPllPSync2C7_B 0x0140 |
| #define B16Gbl_avPllCtl_avPllPSync2C7_B 0x0140 |
| #define LSb32Gbl_avPllCtl_avPllPSync2C7_B 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync2C7_B 0 |
| #define bGbl_avPllCtl_avPllPSync2C7_B 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync2C7_B 0x0001FFFF |
| #define RA_Gbl_avPllCtl61 0x0144 |
| #define BA_Gbl_avPllCtl_avPllPSync2C8_B 0x0144 |
| #define B16Gbl_avPllCtl_avPllPSync2C8_B 0x0144 |
| #define LSb32Gbl_avPllCtl_avPllPSync2C8_B 0 |
| #define LSb16Gbl_avPllCtl_avPllPSync2C8_B 0 |
| #define bGbl_avPllCtl_avPllPSync2C8_B 17 |
| #define MSK32Gbl_avPllCtl_avPllPSync2C8_B 0x0001FFFF |
| #define BA_Gbl_avPllCtl_avPllEnDpllC_B 0x0146 |
| #define B16Gbl_avPllCtl_avPllEnDpllC_B 0x0146 |
| #define LSb32Gbl_avPllCtl_avPllEnDpllC_B 17 |
| #define LSb16Gbl_avPllCtl_avPllEnDpllC_B 1 |
| #define bGbl_avPllCtl_avPllEnDpllC_B 8 |
| #define MSK32Gbl_avPllCtl_avPllEnDpllC_B 0x01FE0000 |
| #define BA_Gbl_avPllCtl_avPllMasterSlaveB_B 0x0147 |
| #define B16Gbl_avPllCtl_avPllMasterSlaveB_B 0x0146 |
| #define LSb32Gbl_avPllCtl_avPllMasterSlaveB_B 25 |
| #define LSb16Gbl_avPllCtl_avPllMasterSlaveB_B 9 |
| #define bGbl_avPllCtl_avPllMasterSlaveB_B 1 |
| #define MSK32Gbl_avPllCtl_avPllMasterSlaveB_B 0x02000000 |
| #define BA_Gbl_avPllCtl_avPllTestAna_B 0x0147 |
| #define B16Gbl_avPllCtl_avPllTestAna_B 0x0146 |
| #define LSb32Gbl_avPllCtl_avPllTestAna_B 26 |
| #define LSb16Gbl_avPllCtl_avPllTestAna_B 10 |
| #define bGbl_avPllCtl_avPllTestAna_B 6 |
| #define MSK32Gbl_avPllCtl_avPllTestAna_B 0xFC000000 |
| #define RA_Gbl_avPllCtl62 0x0148 |
| #define BA_Gbl_avPllCtl_avPllReservePll_B 0x0148 |
| #define B16Gbl_avPllCtl_avPllReservePll_B 0x0148 |
| #define LSb32Gbl_avPllCtl_avPllReservePll_B 0 |
| #define LSb16Gbl_avPllCtl_avPllReservePll_B 0 |
| #define bGbl_avPllCtl_avPllReservePll_B 4 |
| #define MSK32Gbl_avPllCtl_avPllReservePll_B 0x0000000F |
| #define RA_Gbl_pllStatus 0x014C |
| #define BA_Gbl_pllStatus_sysPllLock 0x014C |
| #define B16Gbl_pllStatus_sysPllLock 0x014C |
| #define LSb32Gbl_pllStatus_sysPllLock 0 |
| #define LSb16Gbl_pllStatus_sysPllLock 0 |
| #define bGbl_pllStatus_sysPllLock 1 |
| #define MSK32Gbl_pllStatus_sysPllLock 0x00000001 |
| #define BA_Gbl_pllStatus_memPllLock 0x014C |
| #define B16Gbl_pllStatus_memPllLock 0x014C |
| #define LSb32Gbl_pllStatus_memPllLock 1 |
| #define LSb16Gbl_pllStatus_memPllLock 1 |
| #define bGbl_pllStatus_memPllLock 1 |
| #define MSK32Gbl_pllStatus_memPllLock 0x00000002 |
| #define BA_Gbl_pllStatus_cpu1PllLock 0x014C |
| #define B16Gbl_pllStatus_cpu1PllLock 0x014C |
| #define LSb32Gbl_pllStatus_cpu1PllLock 2 |
| #define LSb16Gbl_pllStatus_cpu1PllLock 2 |
| #define bGbl_pllStatus_cpu1PllLock 1 |
| #define MSK32Gbl_pllStatus_cpu1PllLock 0x00000004 |
| #define BA_Gbl_pllStatus_avPllALock 0x014C |
| #define B16Gbl_pllStatus_avPllALock 0x014C |
| #define LSb32Gbl_pllStatus_avPllALock 3 |
| #define LSb16Gbl_pllStatus_avPllALock 3 |
| #define bGbl_pllStatus_avPllALock 1 |
| #define MSK32Gbl_pllStatus_avPllALock 0x00000008 |
| #define BA_Gbl_pllStatus_avPllAKvcoOut 0x014C |
| #define B16Gbl_pllStatus_avPllAKvcoOut 0x014C |
| #define LSb32Gbl_pllStatus_avPllAKvcoOut 4 |
| #define LSb16Gbl_pllStatus_avPllAKvcoOut 4 |
| #define bGbl_pllStatus_avPllAKvcoOut 3 |
| #define MSK32Gbl_pllStatus_avPllAKvcoOut 0x00000070 |
| #define BA_Gbl_pllStatus_avPllACaliDone 0x014C |
| #define B16Gbl_pllStatus_avPllACaliDone 0x014C |
| #define LSb32Gbl_pllStatus_avPllACaliDone 7 |
| #define LSb16Gbl_pllStatus_avPllACaliDone 7 |
| #define bGbl_pllStatus_avPllACaliDone 1 |
| #define MSK32Gbl_pllStatus_avPllACaliDone 0x00000080 |
| #define BA_Gbl_pllStatus_avPllBLock 0x014D |
| #define B16Gbl_pllStatus_avPllBLock 0x014C |
| #define LSb32Gbl_pllStatus_avPllBLock 8 |
| #define LSb16Gbl_pllStatus_avPllBLock 8 |
| #define bGbl_pllStatus_avPllBLock 1 |
| #define MSK32Gbl_pllStatus_avPllBLock 0x00000100 |
| #define BA_Gbl_pllStatus_avPllBKvcoOut 0x014D |
| #define B16Gbl_pllStatus_avPllBKvcoOut 0x014C |
| #define LSb32Gbl_pllStatus_avPllBKvcoOut 9 |
| #define LSb16Gbl_pllStatus_avPllBKvcoOut 9 |
| #define bGbl_pllStatus_avPllBKvcoOut 3 |
| #define MSK32Gbl_pllStatus_avPllBKvcoOut 0x00000E00 |
| #define BA_Gbl_pllStatus_avPllBCaliDone 0x014D |
| #define B16Gbl_pllStatus_avPllBCaliDone 0x014C |
| #define LSb32Gbl_pllStatus_avPllBCaliDone 12 |
| #define LSb16Gbl_pllStatus_avPllBCaliDone 12 |
| #define bGbl_pllStatus_avPllBCaliDone 1 |
| #define MSK32Gbl_pllStatus_avPllBCaliDone 0x00001000 |
| #define BA_Gbl_pllStatus_cpuPllResOut 0x014D |
| #define B16Gbl_pllStatus_cpuPllResOut 0x014C |
| #define LSb32Gbl_pllStatus_cpuPllResOut 13 |
| #define LSb16Gbl_pllStatus_cpuPllResOut 13 |
| #define bGbl_pllStatus_cpuPllResOut 4 |
| #define MSK32Gbl_pllStatus_cpuPllResOut 0x0001E000 |
| #define BA_Gbl_pllStatus_memPllResOut 0x014E |
| #define B16Gbl_pllStatus_memPllResOut 0x014E |
| #define LSb32Gbl_pllStatus_memPllResOut 17 |
| #define LSb16Gbl_pllStatus_memPllResOut 1 |
| #define bGbl_pllStatus_memPllResOut 4 |
| #define MSK32Gbl_pllStatus_memPllResOut 0x001E0000 |
| #define BA_Gbl_pllStatus_sysPllResOut 0x014E |
| #define B16Gbl_pllStatus_sysPllResOut 0x014E |
| #define LSb32Gbl_pllStatus_sysPllResOut 21 |
| #define LSb16Gbl_pllStatus_sysPllResOut 5 |
| #define bGbl_pllStatus_sysPllResOut 4 |
| #define MSK32Gbl_pllStatus_sysPllResOut 0x01E00000 |
| #define RA_Gbl_clkEnable 0x0150 |
| #define BA_Gbl_clkEnable_sysClkEn 0x0150 |
| #define B16Gbl_clkEnable_sysClkEn 0x0150 |
| #define LSb32Gbl_clkEnable_sysClkEn 0 |
| #define LSb16Gbl_clkEnable_sysClkEn 0 |
| #define bGbl_clkEnable_sysClkEn 1 |
| #define MSK32Gbl_clkEnable_sysClkEn 0x00000001 |
| #define Gbl_clkEnable_sysClkEn_enable 0x1 |
| #define Gbl_clkEnable_sysClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_cfgClkEn 0x0150 |
| #define B16Gbl_clkEnable_cfgClkEn 0x0150 |
| #define LSb32Gbl_clkEnable_cfgClkEn 1 |
| #define LSb16Gbl_clkEnable_cfgClkEn 1 |
| #define bGbl_clkEnable_cfgClkEn 1 |
| #define MSK32Gbl_clkEnable_cfgClkEn 0x00000002 |
| #define Gbl_clkEnable_cfgClkEn_enable 0x1 |
| #define Gbl_clkEnable_cfgClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_pCubeClkEn 0x0150 |
| #define B16Gbl_clkEnable_pCubeClkEn 0x0150 |
| #define LSb32Gbl_clkEnable_pCubeClkEn 2 |
| #define LSb16Gbl_clkEnable_pCubeClkEn 2 |
| #define bGbl_clkEnable_pCubeClkEn 1 |
| #define MSK32Gbl_clkEnable_pCubeClkEn 0x00000004 |
| #define Gbl_clkEnable_pCubeClkEn_enable 0x1 |
| #define Gbl_clkEnable_pCubeClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_vScopeClkEn 0x0150 |
| #define B16Gbl_clkEnable_vScopeClkEn 0x0150 |
| #define LSb32Gbl_clkEnable_vScopeClkEn 3 |
| #define LSb16Gbl_clkEnable_vScopeClkEn 3 |
| #define bGbl_clkEnable_vScopeClkEn 1 |
| #define MSK32Gbl_clkEnable_vScopeClkEn 0x00000008 |
| #define Gbl_clkEnable_vScopeClkEn_enable 0x1 |
| #define Gbl_clkEnable_vScopeClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_gfxClkEn 0x0150 |
| #define B16Gbl_clkEnable_gfxClkEn 0x0150 |
| #define LSb32Gbl_clkEnable_gfxClkEn 4 |
| #define LSb16Gbl_clkEnable_gfxClkEn 4 |
| #define bGbl_clkEnable_gfxClkEn 1 |
| #define MSK32Gbl_clkEnable_gfxClkEn 0x00000010 |
| #define Gbl_clkEnable_gfxClkEn_enable 0x1 |
| #define Gbl_clkEnable_gfxClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_zspClkEn 0x0150 |
| #define B16Gbl_clkEnable_zspClkEn 0x0150 |
| #define LSb32Gbl_clkEnable_zspClkEn 5 |
| #define LSb16Gbl_clkEnable_zspClkEn 5 |
| #define bGbl_clkEnable_zspClkEn 1 |
| #define MSK32Gbl_clkEnable_zspClkEn 0x00000020 |
| #define Gbl_clkEnable_zspClkEn_enable 0x1 |
| #define Gbl_clkEnable_zspClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_perifClkEn 0x0150 |
| #define B16Gbl_clkEnable_perifClkEn 0x0150 |
| #define LSb32Gbl_clkEnable_perifClkEn 6 |
| #define LSb16Gbl_clkEnable_perifClkEn 6 |
| #define bGbl_clkEnable_perifClkEn 1 |
| #define MSK32Gbl_clkEnable_perifClkEn 0x00000040 |
| #define Gbl_clkEnable_perifClkEn_enable 0x1 |
| #define Gbl_clkEnable_perifClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_gethCoreClkEn 0x0150 |
| #define B16Gbl_clkEnable_gethCoreClkEn 0x0150 |
| #define LSb32Gbl_clkEnable_gethCoreClkEn 7 |
| #define LSb16Gbl_clkEnable_gethCoreClkEn 7 |
| #define bGbl_clkEnable_gethCoreClkEn 1 |
| #define MSK32Gbl_clkEnable_gethCoreClkEn 0x00000080 |
| #define Gbl_clkEnable_gethCoreClkEn_enable 0x1 |
| #define Gbl_clkEnable_gethCoreClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_geth1CoreClkEn 0x0151 |
| #define B16Gbl_clkEnable_geth1CoreClkEn 0x0150 |
| #define LSb32Gbl_clkEnable_geth1CoreClkEn 8 |
| #define LSb16Gbl_clkEnable_geth1CoreClkEn 8 |
| #define bGbl_clkEnable_geth1CoreClkEn 1 |
| #define MSK32Gbl_clkEnable_geth1CoreClkEn 0x00000100 |
| #define Gbl_clkEnable_geth1CoreClkEn_enable 0x1 |
| #define Gbl_clkEnable_geth1CoreClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_sataCoreClkEn 0x0151 |
| #define B16Gbl_clkEnable_sataCoreClkEn 0x0150 |
| #define LSb32Gbl_clkEnable_sataCoreClkEn 9 |
| #define LSb16Gbl_clkEnable_sataCoreClkEn 9 |
| #define bGbl_clkEnable_sataCoreClkEn 1 |
| #define MSK32Gbl_clkEnable_sataCoreClkEn 0x00000200 |
| #define Gbl_clkEnable_sataCoreClkEn_enable 0x1 |
| #define Gbl_clkEnable_sataCoreClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_ahbApbCoreClkEn 0x0151 |
| #define B16Gbl_clkEnable_ahbApbCoreClkEn 0x0150 |
| #define LSb32Gbl_clkEnable_ahbApbCoreClkEn 10 |
| #define LSb16Gbl_clkEnable_ahbApbCoreClkEn 10 |
| #define bGbl_clkEnable_ahbApbCoreClkEn 1 |
| #define MSK32Gbl_clkEnable_ahbApbCoreClkEn 0x00000400 |
| #define Gbl_clkEnable_ahbApbCoreClkEn_enable 0x1 |
| #define Gbl_clkEnable_ahbApbCoreClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_usb0CoreClkEn 0x0151 |
| #define B16Gbl_clkEnable_usb0CoreClkEn 0x0150 |
| #define LSb32Gbl_clkEnable_usb0CoreClkEn 11 |
| #define LSb16Gbl_clkEnable_usb0CoreClkEn 11 |
| #define bGbl_clkEnable_usb0CoreClkEn 1 |
| #define MSK32Gbl_clkEnable_usb0CoreClkEn 0x00000800 |
| #define Gbl_clkEnable_usb0CoreClkEn_enable 0x1 |
| #define Gbl_clkEnable_usb0CoreClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_usb1CoreClkEn 0x0151 |
| #define B16Gbl_clkEnable_usb1CoreClkEn 0x0150 |
| #define LSb32Gbl_clkEnable_usb1CoreClkEn 12 |
| #define LSb16Gbl_clkEnable_usb1CoreClkEn 12 |
| #define bGbl_clkEnable_usb1CoreClkEn 1 |
| #define MSK32Gbl_clkEnable_usb1CoreClkEn 0x00001000 |
| #define Gbl_clkEnable_usb1CoreClkEn_enable 0x1 |
| #define Gbl_clkEnable_usb1CoreClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_pBridgeCoreClkEn 0x0151 |
| #define B16Gbl_clkEnable_pBridgeCoreClkEn 0x0150 |
| #define LSb32Gbl_clkEnable_pBridgeCoreClkEn 13 |
| #define LSb16Gbl_clkEnable_pBridgeCoreClkEn 13 |
| #define bGbl_clkEnable_pBridgeCoreClkEn 1 |
| #define MSK32Gbl_clkEnable_pBridgeCoreClkEn 0x00002000 |
| #define Gbl_clkEnable_pBridgeCoreClkEn_enable 0x1 |
| #define Gbl_clkEnable_pBridgeCoreClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_sdioCoreClkEn 0x0151 |
| #define B16Gbl_clkEnable_sdioCoreClkEn 0x0150 |
| #define LSb32Gbl_clkEnable_sdioCoreClkEn 14 |
| #define LSb16Gbl_clkEnable_sdioCoreClkEn 14 |
| #define bGbl_clkEnable_sdioCoreClkEn 1 |
| #define MSK32Gbl_clkEnable_sdioCoreClkEn 0x00004000 |
| #define Gbl_clkEnable_sdioCoreClkEn_enable 0x1 |
| #define Gbl_clkEnable_sdioCoreClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_sdio1CoreClkEn 0x0151 |
| #define B16Gbl_clkEnable_sdio1CoreClkEn 0x0150 |
| #define LSb32Gbl_clkEnable_sdio1CoreClkEn 15 |
| #define LSb16Gbl_clkEnable_sdio1CoreClkEn 15 |
| #define bGbl_clkEnable_sdio1CoreClkEn 1 |
| #define MSK32Gbl_clkEnable_sdio1CoreClkEn 0x00008000 |
| #define Gbl_clkEnable_sdio1CoreClkEn_enable 0x1 |
| #define Gbl_clkEnable_sdio1CoreClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_nfcCoreClkEn 0x0152 |
| #define B16Gbl_clkEnable_nfcCoreClkEn 0x0152 |
| #define LSb32Gbl_clkEnable_nfcCoreClkEn 17 |
| #define LSb16Gbl_clkEnable_nfcCoreClkEn 1 |
| #define bGbl_clkEnable_nfcCoreClkEn 1 |
| #define MSK32Gbl_clkEnable_nfcCoreClkEn 0x00020000 |
| #define Gbl_clkEnable_nfcCoreClkEn_enable 0x1 |
| #define Gbl_clkEnable_nfcCoreClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_nfcEccClkEn 0x0152 |
| #define B16Gbl_clkEnable_nfcEccClkEn 0x0152 |
| #define LSb32Gbl_clkEnable_nfcEccClkEn 18 |
| #define LSb16Gbl_clkEnable_nfcEccClkEn 2 |
| #define bGbl_clkEnable_nfcEccClkEn 1 |
| #define MSK32Gbl_clkEnable_nfcEccClkEn 0x00040000 |
| #define Gbl_clkEnable_nfcEccClkEn_enable 0x1 |
| #define Gbl_clkEnable_nfcEccClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_smemcCoreClkEn 0x0152 |
| #define B16Gbl_clkEnable_smemcCoreClkEn 0x0152 |
| #define LSb32Gbl_clkEnable_smemcCoreClkEn 19 |
| #define LSb16Gbl_clkEnable_smemcCoreClkEn 3 |
| #define bGbl_clkEnable_smemcCoreClkEn 1 |
| #define MSK32Gbl_clkEnable_smemcCoreClkEn 0x00080000 |
| #define Gbl_clkEnable_smemcCoreClkEn_enable 0x1 |
| #define Gbl_clkEnable_smemcCoreClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_appClkEn 0x0152 |
| #define B16Gbl_clkEnable_appClkEn 0x0152 |
| #define LSb32Gbl_clkEnable_appClkEn 20 |
| #define LSb16Gbl_clkEnable_appClkEn 4 |
| #define bGbl_clkEnable_appClkEn 1 |
| #define MSK32Gbl_clkEnable_appClkEn 0x00100000 |
| #define Gbl_clkEnable_appClkEn_enable 0x1 |
| #define Gbl_clkEnable_appClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_vppSysClkEn 0x0152 |
| #define B16Gbl_clkEnable_vppSysClkEn 0x0152 |
| #define LSb32Gbl_clkEnable_vppSysClkEn 21 |
| #define LSb16Gbl_clkEnable_vppSysClkEn 5 |
| #define bGbl_clkEnable_vppSysClkEn 1 |
| #define MSK32Gbl_clkEnable_vppSysClkEn 0x00200000 |
| #define Gbl_clkEnable_vppSysClkEn_enable 0x1 |
| #define Gbl_clkEnable_vppSysClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_audio0ClkEn 0x0152 |
| #define B16Gbl_clkEnable_audio0ClkEn 0x0152 |
| #define LSb32Gbl_clkEnable_audio0ClkEn 22 |
| #define LSb16Gbl_clkEnable_audio0ClkEn 6 |
| #define bGbl_clkEnable_audio0ClkEn 1 |
| #define MSK32Gbl_clkEnable_audio0ClkEn 0x00400000 |
| #define Gbl_clkEnable_audio0ClkEn_enable 0x1 |
| #define Gbl_clkEnable_audio0ClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_audio1ClkEn 0x0152 |
| #define B16Gbl_clkEnable_audio1ClkEn 0x0152 |
| #define LSb32Gbl_clkEnable_audio1ClkEn 23 |
| #define LSb16Gbl_clkEnable_audio1ClkEn 7 |
| #define bGbl_clkEnable_audio1ClkEn 1 |
| #define MSK32Gbl_clkEnable_audio1ClkEn 0x00800000 |
| #define Gbl_clkEnable_audio1ClkEn_enable 0x1 |
| #define Gbl_clkEnable_audio1ClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_audio2ClkEn 0x0153 |
| #define B16Gbl_clkEnable_audio2ClkEn 0x0152 |
| #define LSb32Gbl_clkEnable_audio2ClkEn 24 |
| #define LSb16Gbl_clkEnable_audio2ClkEn 8 |
| #define bGbl_clkEnable_audio2ClkEn 1 |
| #define MSK32Gbl_clkEnable_audio2ClkEn 0x01000000 |
| #define Gbl_clkEnable_audio2ClkEn_enable 0x1 |
| #define Gbl_clkEnable_audio2ClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_audio3ClkEn 0x0153 |
| #define B16Gbl_clkEnable_audio3ClkEn 0x0152 |
| #define LSb32Gbl_clkEnable_audio3ClkEn 25 |
| #define LSb16Gbl_clkEnable_audio3ClkEn 9 |
| #define bGbl_clkEnable_audio3ClkEn 1 |
| #define MSK32Gbl_clkEnable_audio3ClkEn 0x02000000 |
| #define Gbl_clkEnable_audio3ClkEn_enable 0x1 |
| #define Gbl_clkEnable_audio3ClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_audioHdClkEn 0x0153 |
| #define B16Gbl_clkEnable_audioHdClkEn 0x0152 |
| #define LSb32Gbl_clkEnable_audioHdClkEn 26 |
| #define LSb16Gbl_clkEnable_audioHdClkEn 10 |
| #define bGbl_clkEnable_audioHdClkEn 1 |
| #define MSK32Gbl_clkEnable_audioHdClkEn 0x04000000 |
| #define Gbl_clkEnable_audioHdClkEn_enable 0x1 |
| #define Gbl_clkEnable_audioHdClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_video0ClkEn 0x0153 |
| #define B16Gbl_clkEnable_video0ClkEn 0x0152 |
| #define LSb32Gbl_clkEnable_video0ClkEn 27 |
| #define LSb16Gbl_clkEnable_video0ClkEn 11 |
| #define bGbl_clkEnable_video0ClkEn 1 |
| #define MSK32Gbl_clkEnable_video0ClkEn 0x08000000 |
| #define Gbl_clkEnable_video0ClkEn_enable 0x1 |
| #define Gbl_clkEnable_video0ClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_video1ClkEn 0x0153 |
| #define B16Gbl_clkEnable_video1ClkEn 0x0152 |
| #define LSb32Gbl_clkEnable_video1ClkEn 28 |
| #define LSb16Gbl_clkEnable_video1ClkEn 12 |
| #define bGbl_clkEnable_video1ClkEn 1 |
| #define MSK32Gbl_clkEnable_video1ClkEn 0x10000000 |
| #define Gbl_clkEnable_video1ClkEn_enable 0x1 |
| #define Gbl_clkEnable_video1ClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_video2ClkEn 0x0153 |
| #define B16Gbl_clkEnable_video2ClkEn 0x0152 |
| #define LSb32Gbl_clkEnable_video2ClkEn 29 |
| #define LSb16Gbl_clkEnable_video2ClkEn 13 |
| #define bGbl_clkEnable_video2ClkEn 1 |
| #define MSK32Gbl_clkEnable_video2ClkEn 0x20000000 |
| #define Gbl_clkEnable_video2ClkEn_enable 0x1 |
| #define Gbl_clkEnable_video2ClkEn_disable 0x0 |
| #define BA_Gbl_clkEnable_PEX_mx_refclk_off 0x0153 |
| #define B16Gbl_clkEnable_PEX_mx_refclk_off 0x0152 |
| #define LSb32Gbl_clkEnable_PEX_mx_refclk_off 30 |
| #define LSb16Gbl_clkEnable_PEX_mx_refclk_off 14 |
| #define bGbl_clkEnable_PEX_mx_refclk_off 1 |
| #define MSK32Gbl_clkEnable_PEX_mx_refclk_off 0x40000000 |
| #define Gbl_clkEnable_PEX_mx_refclk_off_ON 0x0 |
| #define Gbl_clkEnable_PEX_mx_refclk_off_OFF 0x1 |
| #define RA_Gbl_clkSelect 0x0154 |
| #define BA_Gbl_clkSelect_sysClkPllSel 0x0154 |
| #define B16Gbl_clkSelect_sysClkPllSel 0x0154 |
| #define LSb32Gbl_clkSelect_sysClkPllSel 0 |
| #define LSb16Gbl_clkSelect_sysClkPllSel 0 |
| #define bGbl_clkSelect_sysClkPllSel 3 |
| #define MSK32Gbl_clkSelect_sysClkPllSel 0x00000007 |
| #define Gbl_clkSelect_sysClkPllSel_AVPllB4 0x0 |
| #define Gbl_clkSelect_sysClkPllSel_AVPllB5 0x1 |
| #define Gbl_clkSelect_sysClkPllSel_AVPllB6 0x2 |
| #define Gbl_clkSelect_sysClkPllSel_AVPllB7 0x3 |
| #define Gbl_clkSelect_sysClkPllSel_SYSPll 0x4 |
| #define BA_Gbl_clkSelect_sysClkSel 0x0154 |
| #define B16Gbl_clkSelect_sysClkSel 0x0154 |
| #define LSb32Gbl_clkSelect_sysClkSel 3 |
| #define LSb16Gbl_clkSelect_sysClkSel 3 |
| #define bGbl_clkSelect_sysClkSel 3 |
| #define MSK32Gbl_clkSelect_sysClkSel 0x00000038 |
| #define Gbl_clkSelect_sysClkSel_d2 0x1 |
| #define Gbl_clkSelect_sysClkSel_d4 0x2 |
| #define Gbl_clkSelect_sysClkSel_d6 0x3 |
| #define Gbl_clkSelect_sysClkSel_d8 0x4 |
| #define Gbl_clkSelect_sysClkSel_d12 0x5 |
| #define BA_Gbl_clkSelect_cpu0ClkPllSel 0x0154 |
| #define B16Gbl_clkSelect_cpu0ClkPllSel 0x0154 |
| #define LSb32Gbl_clkSelect_cpu0ClkPllSel 6 |
| #define LSb16Gbl_clkSelect_cpu0ClkPllSel 6 |
| #define bGbl_clkSelect_cpu0ClkPllSel 3 |
| #define MSK32Gbl_clkSelect_cpu0ClkPllSel 0x000001C0 |
| #define Gbl_clkSelect_cpu0ClkPllSel_AVPllB4 0x0 |
| #define Gbl_clkSelect_cpu0ClkPllSel_AVPllB5 0x1 |
| #define Gbl_clkSelect_cpu0ClkPllSel_AVPllB6 0x2 |
| #define Gbl_clkSelect_cpu0ClkPllSel_AVPllB7 0x3 |
| #define Gbl_clkSelect_cpu0ClkPllSel_MEMPLL 0x4 |
| #define BA_Gbl_clkSelect_cpu0ClkSel 0x0155 |
| #define B16Gbl_clkSelect_cpu0ClkSel 0x0154 |
| #define LSb32Gbl_clkSelect_cpu0ClkSel 9 |
| #define LSb16Gbl_clkSelect_cpu0ClkSel 9 |
| #define bGbl_clkSelect_cpu0ClkSel 3 |
| #define MSK32Gbl_clkSelect_cpu0ClkSel 0x00000E00 |
| #define Gbl_clkSelect_cpu0ClkSel_d2 0x1 |
| #define Gbl_clkSelect_cpu0ClkSel_d4 0x2 |
| #define Gbl_clkSelect_cpu0ClkSel_d6 0x3 |
| #define Gbl_clkSelect_cpu0ClkSel_d8 0x4 |
| #define Gbl_clkSelect_cpu0ClkSel_d12 0x5 |
| #define BA_Gbl_clkSelect_cpu1ClkPllSel 0x0155 |
| #define B16Gbl_clkSelect_cpu1ClkPllSel 0x0154 |
| #define LSb32Gbl_clkSelect_cpu1ClkPllSel 12 |
| #define LSb16Gbl_clkSelect_cpu1ClkPllSel 12 |
| #define bGbl_clkSelect_cpu1ClkPllSel 2 |
| #define MSK32Gbl_clkSelect_cpu1ClkPllSel 0x00003000 |
| #define Gbl_clkSelect_cpu1ClkPllSel_AVPllA5 0x0 |
| #define Gbl_clkSelect_cpu1ClkPllSel_AVPllA6 0x1 |
| #define Gbl_clkSelect_cpu1ClkPllSel_AVPllB6 0x2 |
| #define Gbl_clkSelect_cpu1ClkPllSel_AVPllB7 0x3 |
| #define BA_Gbl_clkSelect_cpu1ClkSel 0x0155 |
| #define B16Gbl_clkSelect_cpu1ClkSel 0x0154 |
| #define LSb32Gbl_clkSelect_cpu1ClkSel 14 |
| #define LSb16Gbl_clkSelect_cpu1ClkSel 14 |
| #define bGbl_clkSelect_cpu1ClkSel 3 |
| #define MSK32Gbl_clkSelect_cpu1ClkSel 0x0001C000 |
| #define Gbl_clkSelect_cpu1ClkSel_d2 0x1 |
| #define Gbl_clkSelect_cpu1ClkSel_d4 0x2 |
| #define Gbl_clkSelect_cpu1ClkSel_d6 0x3 |
| #define Gbl_clkSelect_cpu1ClkSel_d8 0x4 |
| #define Gbl_clkSelect_cpu1ClkSel_d12 0x5 |
| #define BA_Gbl_clkSelect_cfgClkPllSel 0x0156 |
| #define B16Gbl_clkSelect_cfgClkPllSel 0x0156 |
| #define LSb32Gbl_clkSelect_cfgClkPllSel 23 |
| #define LSb16Gbl_clkSelect_cfgClkPllSel 7 |
| #define bGbl_clkSelect_cfgClkPllSel 3 |
| #define MSK32Gbl_clkSelect_cfgClkPllSel 0x03800000 |
| #define Gbl_clkSelect_cfgClkPllSel_AVPllB4 0x0 |
| #define Gbl_clkSelect_cfgClkPllSel_AVPllB5 0x1 |
| #define Gbl_clkSelect_cfgClkPllSel_AVPllB6 0x2 |
| #define Gbl_clkSelect_cfgClkPllSel_AVPllB7 0x3 |
| #define Gbl_clkSelect_cfgClkPllSel_SYSPll 0x4 |
| #define BA_Gbl_clkSelect_cfgClkSel 0x0157 |
| #define B16Gbl_clkSelect_cfgClkSel 0x0156 |
| #define LSb32Gbl_clkSelect_cfgClkSel 26 |
| #define LSb16Gbl_clkSelect_cfgClkSel 10 |
| #define bGbl_clkSelect_cfgClkSel 3 |
| #define MSK32Gbl_clkSelect_cfgClkSel 0x1C000000 |
| #define Gbl_clkSelect_cfgClkSel_d2 0x1 |
| #define Gbl_clkSelect_cfgClkSel_d4 0x2 |
| #define Gbl_clkSelect_cfgClkSel_d6 0x3 |
| #define Gbl_clkSelect_cfgClkSel_d8 0x4 |
| #define Gbl_clkSelect_cfgClkSel_d12 0x5 |
| #define BA_Gbl_clkSelect_gfxClkPllSel 0x0157 |
| #define B16Gbl_clkSelect_gfxClkPllSel 0x0156 |
| #define LSb32Gbl_clkSelect_gfxClkPllSel 29 |
| #define LSb16Gbl_clkSelect_gfxClkPllSel 13 |
| #define bGbl_clkSelect_gfxClkPllSel 3 |
| #define MSK32Gbl_clkSelect_gfxClkPllSel 0xE0000000 |
| #define Gbl_clkSelect_gfxClkPllSel_AVPllB4 0x0 |
| #define Gbl_clkSelect_gfxClkPllSel_AVPllB5 0x1 |
| #define Gbl_clkSelect_gfxClkPllSel_AVPllB6 0x2 |
| #define Gbl_clkSelect_gfxClkPllSel_AVPllB7 0x3 |
| #define Gbl_clkSelect_gfxClkPllSel_SYSPll 0x4 |
| #define RA_Gbl_clkSelect1 0x0158 |
| #define BA_Gbl_clkSelect_gfxClkSel 0x0158 |
| #define B16Gbl_clkSelect_gfxClkSel 0x0158 |
| #define LSb32Gbl_clkSelect_gfxClkSel 0 |
| #define LSb16Gbl_clkSelect_gfxClkSel 0 |
| #define bGbl_clkSelect_gfxClkSel 3 |
| #define MSK32Gbl_clkSelect_gfxClkSel 0x00000007 |
| #define Gbl_clkSelect_gfxClkSel_d2 0x1 |
| #define Gbl_clkSelect_gfxClkSel_d4 0x2 |
| #define Gbl_clkSelect_gfxClkSel_d6 0x3 |
| #define Gbl_clkSelect_gfxClkSel_d8 0x4 |
| #define Gbl_clkSelect_gfxClkSel_d12 0x5 |
| #define BA_Gbl_clkSelect_zspClkPllSel 0x0158 |
| #define B16Gbl_clkSelect_zspClkPllSel 0x0158 |
| #define LSb32Gbl_clkSelect_zspClkPllSel 3 |
| #define LSb16Gbl_clkSelect_zspClkPllSel 3 |
| #define bGbl_clkSelect_zspClkPllSel 3 |
| #define MSK32Gbl_clkSelect_zspClkPllSel 0x00000038 |
| #define Gbl_clkSelect_zspClkPllSel_AVPllB4 0x0 |
| #define Gbl_clkSelect_zspClkPllSel_AVPllB5 0x1 |
| #define Gbl_clkSelect_zspClkPllSel_AVPllB6 0x2 |
| #define Gbl_clkSelect_zspClkPllSel_AVPllB7 0x3 |
| #define Gbl_clkSelect_zspClkPllSel_SYSPll 0x4 |
| #define BA_Gbl_clkSelect_zspClkSel 0x0158 |
| #define B16Gbl_clkSelect_zspClkSel 0x0158 |
| #define LSb32Gbl_clkSelect_zspClkSel 6 |
| #define LSb16Gbl_clkSelect_zspClkSel 6 |
| #define bGbl_clkSelect_zspClkSel 3 |
| #define MSK32Gbl_clkSelect_zspClkSel 0x000001C0 |
| #define Gbl_clkSelect_zspClkSel_d2 0x1 |
| #define Gbl_clkSelect_zspClkSel_d4 0x2 |
| #define Gbl_clkSelect_zspClkSel_d6 0x3 |
| #define Gbl_clkSelect_zspClkSel_d8 0x4 |
| #define Gbl_clkSelect_zspClkSel_d12 0x5 |
| #define BA_Gbl_clkSelect_perifClkPllSel 0x0159 |
| #define B16Gbl_clkSelect_perifClkPllSel 0x0158 |
| #define LSb32Gbl_clkSelect_perifClkPllSel 9 |
| #define LSb16Gbl_clkSelect_perifClkPllSel 9 |
| #define bGbl_clkSelect_perifClkPllSel 3 |
| #define MSK32Gbl_clkSelect_perifClkPllSel 0x00000E00 |
| #define Gbl_clkSelect_perifClkPllSel_AVPllB4 0x0 |
| #define Gbl_clkSelect_perifClkPllSel_AVPllB5 0x1 |
| #define Gbl_clkSelect_perifClkPllSel_AVPllB6 0x2 |
| #define Gbl_clkSelect_perifClkPllSel_AVPllB7 0x3 |
| #define Gbl_clkSelect_perifClkPllSel_SYSPll 0x4 |
| #define BA_Gbl_clkSelect_perifClkSel 0x0159 |
| #define B16Gbl_clkSelect_perifClkSel 0x0158 |
| #define LSb32Gbl_clkSelect_perifClkSel 12 |
| #define LSb16Gbl_clkSelect_perifClkSel 12 |
| #define bGbl_clkSelect_perifClkSel 3 |
| #define MSK32Gbl_clkSelect_perifClkSel 0x00007000 |
| #define Gbl_clkSelect_perifClkSel_d2 0x1 |
| #define Gbl_clkSelect_perifClkSel_d4 0x2 |
| #define Gbl_clkSelect_perifClkSel_d6 0x3 |
| #define Gbl_clkSelect_perifClkSel_d8 0x4 |
| #define Gbl_clkSelect_perifClkSel_d12 0x5 |
| #define BA_Gbl_clkSelect_pCubeClkPllSel 0x0159 |
| #define B16Gbl_clkSelect_pCubeClkPllSel 0x0158 |
| #define LSb32Gbl_clkSelect_pCubeClkPllSel 15 |
| #define LSb16Gbl_clkSelect_pCubeClkPllSel 15 |
| #define bGbl_clkSelect_pCubeClkPllSel 3 |
| #define MSK32Gbl_clkSelect_pCubeClkPllSel 0x00038000 |
| #define Gbl_clkSelect_pCubeClkPllSel_AVPllB4 0x0 |
| #define Gbl_clkSelect_pCubeClkPllSel_AVPllB5 0x1 |
| #define Gbl_clkSelect_pCubeClkPllSel_AVPllB6 0x2 |
| #define Gbl_clkSelect_pCubeClkPllSel_AVPllB7 0x3 |
| #define Gbl_clkSelect_pCubeClkPllSel_SYSPll 0x4 |
| #define BA_Gbl_clkSelect_pCubeClkSel 0x015A |
| #define B16Gbl_clkSelect_pCubeClkSel 0x015A |
| #define LSb32Gbl_clkSelect_pCubeClkSel 18 |
| #define LSb16Gbl_clkSelect_pCubeClkSel 2 |
| #define bGbl_clkSelect_pCubeClkSel 3 |
| #define MSK32Gbl_clkSelect_pCubeClkSel 0x001C0000 |
| #define Gbl_clkSelect_pCubeClkSel_d2 0x1 |
| #define Gbl_clkSelect_pCubeClkSel_d4 0x2 |
| #define Gbl_clkSelect_pCubeClkSel_d6 0x3 |
| #define Gbl_clkSelect_pCubeClkSel_d8 0x4 |
| #define Gbl_clkSelect_pCubeClkSel_d12 0x5 |
| #define BA_Gbl_clkSelect_vScopeClkPllSel 0x015A |
| #define B16Gbl_clkSelect_vScopeClkPllSel 0x015A |
| #define LSb32Gbl_clkSelect_vScopeClkPllSel 21 |
| #define LSb16Gbl_clkSelect_vScopeClkPllSel 5 |
| #define bGbl_clkSelect_vScopeClkPllSel 3 |
| #define MSK32Gbl_clkSelect_vScopeClkPllSel 0x00E00000 |
| #define Gbl_clkSelect_vScopeClkPllSel_AVPllB4 0x0 |
| #define Gbl_clkSelect_vScopeClkPllSel_AVPllB5 0x1 |
| #define Gbl_clkSelect_vScopeClkPllSel_AVPllB6 0x2 |
| #define Gbl_clkSelect_vScopeClkPllSel_AVPllB7 0x3 |
| #define Gbl_clkSelect_vScopeClkPllSel_SYSPll 0x4 |
| #define BA_Gbl_clkSelect_vScopeClkSel 0x015B |
| #define B16Gbl_clkSelect_vScopeClkSel 0x015A |
| #define LSb32Gbl_clkSelect_vScopeClkSel 24 |
| #define LSb16Gbl_clkSelect_vScopeClkSel 8 |
| #define bGbl_clkSelect_vScopeClkSel 3 |
| #define MSK32Gbl_clkSelect_vScopeClkSel 0x07000000 |
| #define Gbl_clkSelect_vScopeClkSel_d2 0x1 |
| #define Gbl_clkSelect_vScopeClkSel_d4 0x2 |
| #define Gbl_clkSelect_vScopeClkSel_d6 0x3 |
| #define Gbl_clkSelect_vScopeClkSel_d8 0x4 |
| #define Gbl_clkSelect_vScopeClkSel_d12 0x5 |
| #define BA_Gbl_clkSelect_nfcEccClkPllSel 0x015B |
| #define B16Gbl_clkSelect_nfcEccClkPllSel 0x015A |
| #define LSb32Gbl_clkSelect_nfcEccClkPllSel 27 |
| #define LSb16Gbl_clkSelect_nfcEccClkPllSel 11 |
| #define bGbl_clkSelect_nfcEccClkPllSel 3 |
| #define MSK32Gbl_clkSelect_nfcEccClkPllSel 0x38000000 |
| #define Gbl_clkSelect_nfcEccClkPllSel_AVPllB4 0x0 |
| #define Gbl_clkSelect_nfcEccClkPllSel_AVPllB5 0x1 |
| #define Gbl_clkSelect_nfcEccClkPllSel_AVPllB6 0x2 |
| #define Gbl_clkSelect_nfcEccClkPllSel_AVPllB7 0x3 |
| #define Gbl_clkSelect_nfcEccClkPllSel_SYSPll 0x4 |
| #define RA_Gbl_clkSelect2 0x015C |
| #define BA_Gbl_clkSelect_nfcEccClkSel 0x015C |
| #define B16Gbl_clkSelect_nfcEccClkSel 0x015C |
| #define LSb32Gbl_clkSelect_nfcEccClkSel 0 |
| #define LSb16Gbl_clkSelect_nfcEccClkSel 0 |
| #define bGbl_clkSelect_nfcEccClkSel 3 |
| #define MSK32Gbl_clkSelect_nfcEccClkSel 0x00000007 |
| #define Gbl_clkSelect_nfcEccClkSel_d2 0x1 |
| #define Gbl_clkSelect_nfcEccClkSel_d4 0x2 |
| #define Gbl_clkSelect_nfcEccClkSel_d6 0x3 |
| #define Gbl_clkSelect_nfcEccClkSel_d8 0x4 |
| #define Gbl_clkSelect_nfcEccClkSel_d12 0x5 |
| #define BA_Gbl_clkSelect_vppSysClkPllSel 0x015C |
| #define B16Gbl_clkSelect_vppSysClkPllSel 0x015C |
| #define LSb32Gbl_clkSelect_vppSysClkPllSel 3 |
| #define LSb16Gbl_clkSelect_vppSysClkPllSel 3 |
| #define bGbl_clkSelect_vppSysClkPllSel 3 |
| #define MSK32Gbl_clkSelect_vppSysClkPllSel 0x00000038 |
| #define Gbl_clkSelect_vppSysClkPllSel_AVPllB4 0x0 |
| #define Gbl_clkSelect_vppSysClkPllSel_AVPllB5 0x1 |
| #define Gbl_clkSelect_vppSysClkPllSel_AVPllB6 0x2 |
| #define Gbl_clkSelect_vppSysClkPllSel_AVPllB7 0x3 |
| #define Gbl_clkSelect_vppSysClkPllSel_SYSPll 0x4 |
| #define BA_Gbl_clkSelect_vppSysClkSel 0x015C |
| #define B16Gbl_clkSelect_vppSysClkSel 0x015C |
| #define LSb32Gbl_clkSelect_vppSysClkSel 6 |
| #define LSb16Gbl_clkSelect_vppSysClkSel 6 |
| #define bGbl_clkSelect_vppSysClkSel 3 |
| #define MSK32Gbl_clkSelect_vppSysClkSel 0x000001C0 |
| #define Gbl_clkSelect_vppSysClkSel_d2 0x1 |
| #define Gbl_clkSelect_vppSysClkSel_d4 0x2 |
| #define Gbl_clkSelect_vppSysClkSel_d6 0x3 |
| #define Gbl_clkSelect_vppSysClkSel_d8 0x4 |
| #define Gbl_clkSelect_vppSysClkSel_d12 0x5 |
| #define BA_Gbl_clkSelect_appClkPllSel 0x015D |
| #define B16Gbl_clkSelect_appClkPllSel 0x015C |
| #define LSb32Gbl_clkSelect_appClkPllSel 9 |
| #define LSb16Gbl_clkSelect_appClkPllSel 9 |
| #define bGbl_clkSelect_appClkPllSel 3 |
| #define MSK32Gbl_clkSelect_appClkPllSel 0x00000E00 |
| #define Gbl_clkSelect_appClkPllSel_AVPllB4 0x0 |
| #define Gbl_clkSelect_appClkPllSel_AVPllB5 0x1 |
| #define Gbl_clkSelect_appClkPllSel_AVPllB6 0x2 |
| #define Gbl_clkSelect_appClkPllSel_AVPllB7 0x3 |
| #define Gbl_clkSelect_appClkPllSel_SYSPll 0x4 |
| #define BA_Gbl_clkSelect_appClkSel 0x015D |
| #define B16Gbl_clkSelect_appClkSel 0x015C |
| #define LSb32Gbl_clkSelect_appClkSel 12 |
| #define LSb16Gbl_clkSelect_appClkSel 12 |
| #define bGbl_clkSelect_appClkSel 3 |
| #define MSK32Gbl_clkSelect_appClkSel 0x00007000 |
| #define Gbl_clkSelect_appClkSel_d2 0x1 |
| #define Gbl_clkSelect_appClkSel_d4 0x2 |
| #define Gbl_clkSelect_appClkSel_d6 0x3 |
| #define Gbl_clkSelect_appClkSel_d8 0x4 |
| #define Gbl_clkSelect_appClkSel_d12 0x5 |
| #define BA_Gbl_clkSelect_audioFastExtClkSel 0x015D |
| #define B16Gbl_clkSelect_audioFastExtClkSel 0x015C |
| #define LSb32Gbl_clkSelect_audioFastExtClkSel 15 |
| #define LSb16Gbl_clkSelect_audioFastExtClkSel 15 |
| #define bGbl_clkSelect_audioFastExtClkSel 1 |
| #define MSK32Gbl_clkSelect_audioFastExtClkSel 0x00008000 |
| #define BA_Gbl_clkSelect_audioFastClkSel 0x015E |
| #define B16Gbl_clkSelect_audioFastClkSel 0x015E |
| #define LSb32Gbl_clkSelect_audioFastClkSel 16 |
| #define LSb16Gbl_clkSelect_audioFastClkSel 0 |
| #define bGbl_clkSelect_audioFastClkSel 1 |
| #define MSK32Gbl_clkSelect_audioFastClkSel 0x00010000 |
| #define Gbl_clkSelect_audioFastClkSel_pllClk 0x0 |
| #define Gbl_clkSelect_audioFastClkSel_extClk 0x1 |
| #define BA_Gbl_clkSelect_audio0ClkSel 0x015E |
| #define B16Gbl_clkSelect_audio0ClkSel 0x015E |
| #define LSb32Gbl_clkSelect_audio0ClkSel 17 |
| #define LSb16Gbl_clkSelect_audio0ClkSel 1 |
| #define bGbl_clkSelect_audio0ClkSel 3 |
| #define MSK32Gbl_clkSelect_audio0ClkSel 0x000E0000 |
| #define Gbl_clkSelect_audio0ClkSel_d2 0x1 |
| #define Gbl_clkSelect_audio0ClkSel_d4 0x2 |
| #define Gbl_clkSelect_audio0ClkSel_d6 0x3 |
| #define Gbl_clkSelect_audio0ClkSel_d8 0x4 |
| #define Gbl_clkSelect_audio0ClkSel_d12 0x5 |
| #define BA_Gbl_clkSelect_audio2ClkSel 0x015E |
| #define B16Gbl_clkSelect_audio2ClkSel 0x015E |
| #define LSb32Gbl_clkSelect_audio2ClkSel 20 |
| #define LSb16Gbl_clkSelect_audio2ClkSel 4 |
| #define bGbl_clkSelect_audio2ClkSel 3 |
| #define MSK32Gbl_clkSelect_audio2ClkSel 0x00700000 |
| #define Gbl_clkSelect_audio2ClkSel_d2 0x1 |
| #define Gbl_clkSelect_audio2ClkSel_d4 0x2 |
| #define Gbl_clkSelect_audio2ClkSel_d6 0x3 |
| #define Gbl_clkSelect_audio2ClkSel_d8 0x4 |
| #define Gbl_clkSelect_audio2ClkSel_d12 0x5 |
| #define BA_Gbl_clkSelect_audio3ClkSel 0x015E |
| #define B16Gbl_clkSelect_audio3ClkSel 0x015E |
| #define LSb32Gbl_clkSelect_audio3ClkSel 23 |
| #define LSb16Gbl_clkSelect_audio3ClkSel 7 |
| #define bGbl_clkSelect_audio3ClkSel 3 |
| #define MSK32Gbl_clkSelect_audio3ClkSel 0x03800000 |
| #define Gbl_clkSelect_audio3ClkSel_d2 0x1 |
| #define Gbl_clkSelect_audio3ClkSel_d4 0x2 |
| #define Gbl_clkSelect_audio3ClkSel_d6 0x3 |
| #define Gbl_clkSelect_audio3ClkSel_d8 0x4 |
| #define Gbl_clkSelect_audio3ClkSel_d12 0x5 |
| #define BA_Gbl_clkSelect_audioHdExtClkSel 0x015F |
| #define B16Gbl_clkSelect_audioHdExtClkSel 0x015E |
| #define LSb32Gbl_clkSelect_audioHdExtClkSel 26 |
| #define LSb16Gbl_clkSelect_audioHdExtClkSel 10 |
| #define bGbl_clkSelect_audioHdExtClkSel 1 |
| #define MSK32Gbl_clkSelect_audioHdExtClkSel 0x04000000 |
| #define BA_Gbl_clkSelect_audioHdClkSel 0x015F |
| #define B16Gbl_clkSelect_audioHdClkSel 0x015E |
| #define LSb32Gbl_clkSelect_audioHdClkSel 27 |
| #define LSb16Gbl_clkSelect_audioHdClkSel 11 |
| #define bGbl_clkSelect_audioHdClkSel 1 |
| #define MSK32Gbl_clkSelect_audioHdClkSel 0x08000000 |
| #define Gbl_clkSelect_audioHdClkSel_pllClk 0x0 |
| #define Gbl_clkSelect_audioHdClkSel_extClk 0x1 |
| #define BA_Gbl_clkSelect_audio1ExtClkSel 0x015F |
| #define B16Gbl_clkSelect_audio1ExtClkSel 0x015E |
| #define LSb32Gbl_clkSelect_audio1ExtClkSel 28 |
| #define LSb16Gbl_clkSelect_audio1ExtClkSel 12 |
| #define bGbl_clkSelect_audio1ExtClkSel 1 |
| #define MSK32Gbl_clkSelect_audio1ExtClkSel 0x10000000 |
| #define BA_Gbl_clkSelect_audio1ClkPllSel 0x015F |
| #define B16Gbl_clkSelect_audio1ClkPllSel 0x015E |
| #define LSb32Gbl_clkSelect_audio1ClkPllSel 29 |
| #define LSb16Gbl_clkSelect_audio1ClkPllSel 13 |
| #define bGbl_clkSelect_audio1ClkPllSel 1 |
| #define MSK32Gbl_clkSelect_audio1ClkPllSel 0x20000000 |
| #define Gbl_clkSelect_audio1ClkPllSel_AVPllB3 0x0 |
| #define Gbl_clkSelect_audio1ClkPllSel_AVPllA3 0x1 |
| #define BA_Gbl_clkSelect_audio1SrcClkSel 0x015F |
| #define B16Gbl_clkSelect_audio1SrcClkSel 0x015E |
| #define LSb32Gbl_clkSelect_audio1SrcClkSel 30 |
| #define LSb16Gbl_clkSelect_audio1SrcClkSel 14 |
| #define bGbl_clkSelect_audio1SrcClkSel 1 |
| #define MSK32Gbl_clkSelect_audio1SrcClkSel 0x40000000 |
| #define Gbl_clkSelect_audio1SrcClkSel_pllClk 0x0 |
| #define Gbl_clkSelect_audio1SrcClkSel_extClk 0x1 |
| #define RA_Gbl_clkSelect3 0x0160 |
| #define BA_Gbl_clkSelect_audio1ClkSel 0x0160 |
| #define B16Gbl_clkSelect_audio1ClkSel 0x0160 |
| #define LSb32Gbl_clkSelect_audio1ClkSel 0 |
| #define LSb16Gbl_clkSelect_audio1ClkSel 0 |
| #define bGbl_clkSelect_audio1ClkSel 3 |
| #define MSK32Gbl_clkSelect_audio1ClkSel 0x00000007 |
| #define Gbl_clkSelect_audio1ClkSel_d2 0x1 |
| #define Gbl_clkSelect_audio1ClkSel_d4 0x2 |
| #define Gbl_clkSelect_audio1ClkSel_d6 0x3 |
| #define Gbl_clkSelect_audio1ClkSel_d8 0x4 |
| #define Gbl_clkSelect_audio1ClkSel_d12 0x5 |
| #define BA_Gbl_clkSelect_video0ExtClkSel 0x0160 |
| #define B16Gbl_clkSelect_video0ExtClkSel 0x0160 |
| #define LSb32Gbl_clkSelect_video0ExtClkSel 3 |
| #define LSb16Gbl_clkSelect_video0ExtClkSel 3 |
| #define bGbl_clkSelect_video0ExtClkSel 1 |
| #define MSK32Gbl_clkSelect_video0ExtClkSel 0x00000008 |
| #define BA_Gbl_clkSelect_video0ClkSel 0x0160 |
| #define B16Gbl_clkSelect_video0ClkSel 0x0160 |
| #define LSb32Gbl_clkSelect_video0ClkSel 4 |
| #define LSb16Gbl_clkSelect_video0ClkSel 4 |
| #define bGbl_clkSelect_video0ClkSel 1 |
| #define MSK32Gbl_clkSelect_video0ClkSel 0x00000010 |
| #define Gbl_clkSelect_video0ClkSel_pllClk 0x0 |
| #define Gbl_clkSelect_video0ClkSel_extClk 0x1 |
| #define BA_Gbl_clkSelect_video1ExtClkSel 0x0160 |
| #define B16Gbl_clkSelect_video1ExtClkSel 0x0160 |
| #define LSb32Gbl_clkSelect_video1ExtClkSel 5 |
| #define LSb16Gbl_clkSelect_video1ExtClkSel 5 |
| #define bGbl_clkSelect_video1ExtClkSel 1 |
| #define MSK32Gbl_clkSelect_video1ExtClkSel 0x00000020 |
| #define BA_Gbl_clkSelect_video1ClkSel 0x0160 |
| #define B16Gbl_clkSelect_video1ClkSel 0x0160 |
| #define LSb32Gbl_clkSelect_video1ClkSel 6 |
| #define LSb16Gbl_clkSelect_video1ClkSel 6 |
| #define bGbl_clkSelect_video1ClkSel 1 |
| #define MSK32Gbl_clkSelect_video1ClkSel 0x00000040 |
| #define Gbl_clkSelect_video1ClkSel_pllClk 0x0 |
| #define Gbl_clkSelect_video1ClkSel_extClk 0x1 |
| #define BA_Gbl_clkSelect_video1ClkPllSel 0x0160 |
| #define B16Gbl_clkSelect_video1ClkPllSel 0x0160 |
| #define LSb32Gbl_clkSelect_video1ClkPllSel 7 |
| #define LSb16Gbl_clkSelect_video1ClkPllSel 7 |
| #define bGbl_clkSelect_video1ClkPllSel 1 |
| #define MSK32Gbl_clkSelect_video1ClkPllSel 0x00000080 |
| #define Gbl_clkSelect_video1ClkPllSel_AVPllA2 0x0 |
| #define Gbl_clkSelect_video1ClkPllSel_AVPllB2 0x1 |
| #define BA_Gbl_clkSelect_video2ExtClkSel 0x0161 |
| #define B16Gbl_clkSelect_video2ExtClkSel 0x0160 |
| #define LSb32Gbl_clkSelect_video2ExtClkSel 8 |
| #define LSb16Gbl_clkSelect_video2ExtClkSel 8 |
| #define bGbl_clkSelect_video2ExtClkSel 1 |
| #define MSK32Gbl_clkSelect_video2ExtClkSel 0x00000100 |
| #define BA_Gbl_clkSelect_video2ClkSel 0x0161 |
| #define B16Gbl_clkSelect_video2ClkSel 0x0160 |
| #define LSb32Gbl_clkSelect_video2ClkSel 9 |
| #define LSb16Gbl_clkSelect_video2ClkSel 9 |
| #define bGbl_clkSelect_video2ClkSel 1 |
| #define MSK32Gbl_clkSelect_video2ClkSel 0x00000200 |
| #define Gbl_clkSelect_video2ClkSel_pllClk 0x0 |
| #define Gbl_clkSelect_video2ClkSel_extClk 0x1 |
| #define BA_Gbl_clkSelect_video2ClkPllSel 0x0161 |
| #define B16Gbl_clkSelect_video2ClkPllSel 0x0160 |
| #define LSb32Gbl_clkSelect_video2ClkPllSel 10 |
| #define LSb16Gbl_clkSelect_video2ClkPllSel 10 |
| #define bGbl_clkSelect_video2ClkPllSel 1 |
| #define MSK32Gbl_clkSelect_video2ClkPllSel 0x00000400 |
| #define Gbl_clkSelect_video2ClkPllSel_AVPllB1 0x0 |
| #define Gbl_clkSelect_video2ClkPllSel_AVPllA5 0x1 |
| #define RA_Gbl_ClkSwitch 0x0164 |
| #define BA_Gbl_ClkSwitch_sysPLLSWBypass 0x0164 |
| #define B16Gbl_ClkSwitch_sysPLLSWBypass 0x0164 |
| #define LSb32Gbl_ClkSwitch_sysPLLSWBypass 0 |
| #define LSb16Gbl_ClkSwitch_sysPLLSWBypass 0 |
| #define bGbl_ClkSwitch_sysPLLSWBypass 1 |
| #define MSK32Gbl_ClkSwitch_sysPLLSWBypass 0x00000001 |
| #define Gbl_ClkSwitch_sysPLLSWBypass_refClk 0x1 |
| #define Gbl_ClkSwitch_sysPLLSWBypass_pllClk 0x0 |
| #define BA_Gbl_ClkSwitch_memPLLSWBypass 0x0164 |
| #define B16Gbl_ClkSwitch_memPLLSWBypass 0x0164 |
| #define LSb32Gbl_ClkSwitch_memPLLSWBypass 1 |
| #define LSb16Gbl_ClkSwitch_memPLLSWBypass 1 |
| #define bGbl_ClkSwitch_memPLLSWBypass 1 |
| #define MSK32Gbl_ClkSwitch_memPLLSWBypass 0x00000002 |
| #define Gbl_ClkSwitch_memPLLSWBypass_refClk 0x1 |
| #define Gbl_ClkSwitch_memPLLSWBypass_pllClk 0x0 |
| #define BA_Gbl_ClkSwitch_cpu1PLLSWBypass 0x0164 |
| #define B16Gbl_ClkSwitch_cpu1PLLSWBypass 0x0164 |
| #define LSb32Gbl_ClkSwitch_cpu1PLLSWBypass 2 |
| #define LSb16Gbl_ClkSwitch_cpu1PLLSWBypass 2 |
| #define bGbl_ClkSwitch_cpu1PLLSWBypass 1 |
| #define MSK32Gbl_ClkSwitch_cpu1PLLSWBypass 0x00000004 |
| #define Gbl_ClkSwitch_cpu1PLLSWBypass_refClk 0x1 |
| #define Gbl_ClkSwitch_cpu1PLLSWBypass_pllClk 0x0 |
| #define BA_Gbl_ClkSwitch_sysClkPllSwitch 0x0164 |
| #define B16Gbl_ClkSwitch_sysClkPllSwitch 0x0164 |
| #define LSb32Gbl_ClkSwitch_sysClkPllSwitch 3 |
| #define LSb16Gbl_ClkSwitch_sysClkPllSwitch 3 |
| #define bGbl_ClkSwitch_sysClkPllSwitch 1 |
| #define MSK32Gbl_ClkSwitch_sysClkPllSwitch 0x00000008 |
| #define Gbl_ClkSwitch_sysClkPllSwitch_SYSPLL 0x0 |
| #define Gbl_ClkSwitch_sysClkPllSwitch_AVPLL 0x1 |
| #define BA_Gbl_ClkSwitch_sysClkSwitch 0x0164 |
| #define B16Gbl_ClkSwitch_sysClkSwitch 0x0164 |
| #define LSb32Gbl_ClkSwitch_sysClkSwitch 4 |
| #define LSb16Gbl_ClkSwitch_sysClkSwitch 4 |
| #define bGbl_ClkSwitch_sysClkSwitch 1 |
| #define MSK32Gbl_ClkSwitch_sysClkSwitch 0x00000010 |
| #define Gbl_ClkSwitch_sysClkSwitch_SrcClk 0x0 |
| #define Gbl_ClkSwitch_sysClkSwitch_DivClk 0x1 |
| #define BA_Gbl_ClkSwitch_sysClkD3Switch 0x0164 |
| #define B16Gbl_ClkSwitch_sysClkD3Switch 0x0164 |
| #define LSb32Gbl_ClkSwitch_sysClkD3Switch 5 |
| #define LSb16Gbl_ClkSwitch_sysClkD3Switch 5 |
| #define bGbl_ClkSwitch_sysClkD3Switch 1 |
| #define MSK32Gbl_ClkSwitch_sysClkD3Switch 0x00000020 |
| #define Gbl_ClkSwitch_sysClkD3Switch_NonDiv3Clk 0x0 |
| #define Gbl_ClkSwitch_sysClkD3Switch_Div3Clk 0x1 |
| #define BA_Gbl_ClkSwitch_cpu0ClkPllSwitch 0x0164 |
| #define B16Gbl_ClkSwitch_cpu0ClkPllSwitch 0x0164 |
| #define LSb32Gbl_ClkSwitch_cpu0ClkPllSwitch 6 |
| #define LSb16Gbl_ClkSwitch_cpu0ClkPllSwitch 6 |
| #define bGbl_ClkSwitch_cpu0ClkPllSwitch 1 |
| #define MSK32Gbl_ClkSwitch_cpu0ClkPllSwitch 0x00000040 |
| #define Gbl_ClkSwitch_cpu0ClkPllSwitch_CPUPLL 0x0 |
| #define Gbl_ClkSwitch_cpu0ClkPllSwitch_MEMPLL 0x1 |
| #define BA_Gbl_ClkSwitch_cpu0ClkSwitch 0x0164 |
| #define B16Gbl_ClkSwitch_cpu0ClkSwitch 0x0164 |
| #define LSb32Gbl_ClkSwitch_cpu0ClkSwitch 7 |
| #define LSb16Gbl_ClkSwitch_cpu0ClkSwitch 7 |
| #define bGbl_ClkSwitch_cpu0ClkSwitch 1 |
| #define MSK32Gbl_ClkSwitch_cpu0ClkSwitch 0x00000080 |
| #define Gbl_ClkSwitch_cpu0ClkSwitch_SrcClk 0x0 |
| #define Gbl_ClkSwitch_cpu0ClkSwitch_DivClk 0x1 |
| #define BA_Gbl_ClkSwitch_cpu0ClkD3Switch 0x0165 |
| #define B16Gbl_ClkSwitch_cpu0ClkD3Switch 0x0164 |
| #define LSb32Gbl_ClkSwitch_cpu0ClkD3Switch 8 |
| #define LSb16Gbl_ClkSwitch_cpu0ClkD3Switch 8 |
| #define bGbl_ClkSwitch_cpu0ClkD3Switch 1 |
| #define MSK32Gbl_ClkSwitch_cpu0ClkD3Switch 0x00000100 |
| #define Gbl_ClkSwitch_cpu0ClkD3Switch_NonDiv3Clk 0x0 |
| #define Gbl_ClkSwitch_cpu0ClkD3Switch_Div3Clk 0x1 |
| #define BA_Gbl_ClkSwitch_cpu1ClkPllSwitch 0x0165 |
| #define B16Gbl_ClkSwitch_cpu1ClkPllSwitch 0x0164 |
| #define LSb32Gbl_ClkSwitch_cpu1ClkPllSwitch 9 |
| #define LSb16Gbl_ClkSwitch_cpu1ClkPllSwitch 9 |
| #define bGbl_ClkSwitch_cpu1ClkPllSwitch 1 |
| #define MSK32Gbl_ClkSwitch_cpu1ClkPllSwitch 0x00000200 |
| #define Gbl_ClkSwitch_cpu1ClkPllSwitch_CPU1PLL 0x0 |
| #define Gbl_ClkSwitch_cpu1ClkPllSwitch_AVPLL 0x1 |
| #define BA_Gbl_ClkSwitch_cpu1ClkSwitch 0x0165 |
| #define B16Gbl_ClkSwitch_cpu1ClkSwitch 0x0164 |
| #define LSb32Gbl_ClkSwitch_cpu1ClkSwitch 10 |
| #define LSb16Gbl_ClkSwitch_cpu1ClkSwitch 10 |
| #define bGbl_ClkSwitch_cpu1ClkSwitch 1 |
| #define MSK32Gbl_ClkSwitch_cpu1ClkSwitch 0x00000400 |
| #define Gbl_ClkSwitch_cpu1ClkSwitch_SrcClk 0x0 |
| #define Gbl_ClkSwitch_cpu1ClkSwitch_DivClk 0x1 |
| #define BA_Gbl_ClkSwitch_cpu1ClkD3Switch 0x0165 |
| #define B16Gbl_ClkSwitch_cpu1ClkD3Switch 0x0164 |
| #define LSb32Gbl_ClkSwitch_cpu1ClkD3Switch 11 |
| #define LSb16Gbl_ClkSwitch_cpu1ClkD3Switch 11 |
| #define bGbl_ClkSwitch_cpu1ClkD3Switch 1 |
| #define MSK32Gbl_ClkSwitch_cpu1ClkD3Switch 0x00000800 |
| #define Gbl_ClkSwitch_cpu1ClkD3Switch_NonDiv3Clk 0x0 |
| #define Gbl_ClkSwitch_cpu1ClkD3Switch_Div3Clk 0x1 |
| #define BA_Gbl_ClkSwitch_cfgClkPllSwitch 0x0165 |
| #define B16Gbl_ClkSwitch_cfgClkPllSwitch 0x0164 |
| #define LSb32Gbl_ClkSwitch_cfgClkPllSwitch 15 |
| #define LSb16Gbl_ClkSwitch_cfgClkPllSwitch 15 |
| #define bGbl_ClkSwitch_cfgClkPllSwitch 1 |
| #define MSK32Gbl_ClkSwitch_cfgClkPllSwitch 0x00008000 |
| #define Gbl_ClkSwitch_cfgClkPllSwitch_SYSPLL 0x0 |
| #define Gbl_ClkSwitch_cfgClkPllSwitch_AVPLL 0x1 |
| #define BA_Gbl_ClkSwitch_cfgClkSwitch 0x0166 |
| #define B16Gbl_ClkSwitch_cfgClkSwitch 0x0166 |
| #define LSb32Gbl_ClkSwitch_cfgClkSwitch 16 |
| #define LSb16Gbl_ClkSwitch_cfgClkSwitch 0 |
| #define bGbl_ClkSwitch_cfgClkSwitch 1 |
| #define MSK32Gbl_ClkSwitch_cfgClkSwitch 0x00010000 |
| #define Gbl_ClkSwitch_cfgClkSwitch_SrcClk 0x0 |
| #define Gbl_ClkSwitch_cfgClkSwitch_DivClk 0x1 |
| #define BA_Gbl_ClkSwitch_cfgClkD3Switch 0x0166 |
| #define B16Gbl_ClkSwitch_cfgClkD3Switch 0x0166 |
| #define LSb32Gbl_ClkSwitch_cfgClkD3Switch 17 |
| #define LSb16Gbl_ClkSwitch_cfgClkD3Switch 1 |
| #define bGbl_ClkSwitch_cfgClkD3Switch 1 |
| #define MSK32Gbl_ClkSwitch_cfgClkD3Switch 0x00020000 |
| #define Gbl_ClkSwitch_cfgClkD3Switch_NonDiv3Clk 0x0 |
| #define Gbl_ClkSwitch_cfgClkD3Switch_Div3Clk 0x1 |
| #define BA_Gbl_ClkSwitch_gfxClkPllSwitch 0x0166 |
| #define B16Gbl_ClkSwitch_gfxClkPllSwitch 0x0166 |
| #define LSb32Gbl_ClkSwitch_gfxClkPllSwitch 18 |
| #define LSb16Gbl_ClkSwitch_gfxClkPllSwitch 2 |
| #define bGbl_ClkSwitch_gfxClkPllSwitch 1 |
| #define MSK32Gbl_ClkSwitch_gfxClkPllSwitch 0x00040000 |
| #define Gbl_ClkSwitch_gfxClkPllSwitch_SYSPLL 0x0 |
| #define Gbl_ClkSwitch_gfxClkPllSwitch_AVPLL 0x1 |
| #define BA_Gbl_ClkSwitch_gfxClkSwitch 0x0166 |
| #define B16Gbl_ClkSwitch_gfxClkSwitch 0x0166 |
| #define LSb32Gbl_ClkSwitch_gfxClkSwitch 19 |
| #define LSb16Gbl_ClkSwitch_gfxClkSwitch 3 |
| #define bGbl_ClkSwitch_gfxClkSwitch 1 |
| #define MSK32Gbl_ClkSwitch_gfxClkSwitch 0x00080000 |
| #define Gbl_ClkSwitch_gfxClkSwitch_SrcClk 0x0 |
| #define Gbl_ClkSwitch_gfxClkSwitch_DivClk 0x1 |
| #define BA_Gbl_ClkSwitch_gfxClkD3Switch 0x0166 |
| #define B16Gbl_ClkSwitch_gfxClkD3Switch 0x0166 |
| #define LSb32Gbl_ClkSwitch_gfxClkD3Switch 20 |
| #define LSb16Gbl_ClkSwitch_gfxClkD3Switch 4 |
| #define bGbl_ClkSwitch_gfxClkD3Switch 1 |
| #define MSK32Gbl_ClkSwitch_gfxClkD3Switch 0x00100000 |
| #define Gbl_ClkSwitch_gfxClkD3Switch_NonDiv3Clk 0x0 |
| #define Gbl_ClkSwitch_gfxClkD3Switch_Div3Clk 0x1 |
| #define BA_Gbl_ClkSwitch_zspClkPllSwitch 0x0166 |
| #define B16Gbl_ClkSwitch_zspClkPllSwitch 0x0166 |
| #define LSb32Gbl_ClkSwitch_zspClkPllSwitch 21 |
| #define LSb16Gbl_ClkSwitch_zspClkPllSwitch 5 |
| #define bGbl_ClkSwitch_zspClkPllSwitch 1 |
| #define MSK32Gbl_ClkSwitch_zspClkPllSwitch 0x00200000 |
| #define Gbl_ClkSwitch_zspClkPllSwitch_SYSPLL 0x0 |
| #define Gbl_ClkSwitch_zspClkPllSwitch_AVPLL 0x1 |
| #define BA_Gbl_ClkSwitch_zspClkSwitch 0x0166 |
| #define B16Gbl_ClkSwitch_zspClkSwitch 0x0166 |
| #define LSb32Gbl_ClkSwitch_zspClkSwitch 22 |
| #define LSb16Gbl_ClkSwitch_zspClkSwitch 6 |
| #define bGbl_ClkSwitch_zspClkSwitch 1 |
| #define MSK32Gbl_ClkSwitch_zspClkSwitch 0x00400000 |
| #define Gbl_ClkSwitch_zspClkSwitch_SrcClk 0x0 |
| #define Gbl_ClkSwitch_zspClkSwitch_DivClk 0x1 |
| #define BA_Gbl_ClkSwitch_zspClkD3Switch 0x0166 |
| #define B16Gbl_ClkSwitch_zspClkD3Switch 0x0166 |
| #define LSb32Gbl_ClkSwitch_zspClkD3Switch 23 |
| #define LSb16Gbl_ClkSwitch_zspClkD3Switch 7 |
| #define bGbl_ClkSwitch_zspClkD3Switch 1 |
| #define MSK32Gbl_ClkSwitch_zspClkD3Switch 0x00800000 |
| #define Gbl_ClkSwitch_zspClkD3Switch_NonDiv3Clk 0x0 |
| #define Gbl_ClkSwitch_zspClkD3Switch_Div3Clk 0x1 |
| #define BA_Gbl_ClkSwitch_perifClkPllSwitch 0x0167 |
| #define B16Gbl_ClkSwitch_perifClkPllSwitch 0x0166 |
| #define LSb32Gbl_ClkSwitch_perifClkPllSwitch 24 |
| #define LSb16Gbl_ClkSwitch_perifClkPllSwitch 8 |
| #define bGbl_ClkSwitch_perifClkPllSwitch 1 |
| #define MSK32Gbl_ClkSwitch_perifClkPllSwitch 0x01000000 |
| #define Gbl_ClkSwitch_perifClkPllSwitch_SYSPLL 0x0 |
| #define Gbl_ClkSwitch_perifClkPllSwitch_AVPLL 0x1 |
| #define BA_Gbl_ClkSwitch_perifClkSwitch 0x0167 |
| #define B16Gbl_ClkSwitch_perifClkSwitch 0x0166 |
| #define LSb32Gbl_ClkSwitch_perifClkSwitch 25 |
| #define LSb16Gbl_ClkSwitch_perifClkSwitch 9 |
| #define bGbl_ClkSwitch_perifClkSwitch 1 |
| #define MSK32Gbl_ClkSwitch_perifClkSwitch 0x02000000 |
| #define Gbl_ClkSwitch_perifClkSwitch_SrcClk 0x0 |
| #define Gbl_ClkSwitch_perifClkSwitch_DivClk 0x1 |
| #define BA_Gbl_ClkSwitch_perifClkD3Switch 0x0167 |
| #define B16Gbl_ClkSwitch_perifClkD3Switch 0x0166 |
| #define LSb32Gbl_ClkSwitch_perifClkD3Switch 26 |
| #define LSb16Gbl_ClkSwitch_perifClkD3Switch 10 |
| #define bGbl_ClkSwitch_perifClkD3Switch 1 |
| #define MSK32Gbl_ClkSwitch_perifClkD3Switch 0x04000000 |
| #define Gbl_ClkSwitch_perifClkD3Switch_NonDiv3Clk 0x0 |
| #define Gbl_ClkSwitch_perifClkD3Switch_Div3Clk 0x1 |
| #define BA_Gbl_ClkSwitch_pCubeClkPllSwitch 0x0167 |
| #define B16Gbl_ClkSwitch_pCubeClkPllSwitch 0x0166 |
| #define LSb32Gbl_ClkSwitch_pCubeClkPllSwitch 27 |
| #define LSb16Gbl_ClkSwitch_pCubeClkPllSwitch 11 |
| #define bGbl_ClkSwitch_pCubeClkPllSwitch 1 |
| #define MSK32Gbl_ClkSwitch_pCubeClkPllSwitch 0x08000000 |
| #define Gbl_ClkSwitch_pCubeClkPllSwitch_SYSPLL 0x0 |
| #define Gbl_ClkSwitch_pCubeClkPllSwitch_AVPLL 0x1 |
| #define BA_Gbl_ClkSwitch_pCubeClkSwitch 0x0167 |
| #define B16Gbl_ClkSwitch_pCubeClkSwitch 0x0166 |
| #define LSb32Gbl_ClkSwitch_pCubeClkSwitch 28 |
| #define LSb16Gbl_ClkSwitch_pCubeClkSwitch 12 |
| #define bGbl_ClkSwitch_pCubeClkSwitch 1 |
| #define MSK32Gbl_ClkSwitch_pCubeClkSwitch 0x10000000 |
| #define Gbl_ClkSwitch_pCubeClkSwitch_SrcClk 0x0 |
| #define Gbl_ClkSwitch_pCubeClkSwitch_DivClk 0x1 |
| #define BA_Gbl_ClkSwitch_pCubeClkD3Switch 0x0167 |
| #define B16Gbl_ClkSwitch_pCubeClkD3Switch 0x0166 |
| #define LSb32Gbl_ClkSwitch_pCubeClkD3Switch 29 |
| #define LSb16Gbl_ClkSwitch_pCubeClkD3Switch 13 |
| #define bGbl_ClkSwitch_pCubeClkD3Switch 1 |
| #define MSK32Gbl_ClkSwitch_pCubeClkD3Switch 0x20000000 |
| #define Gbl_ClkSwitch_pCubeClkD3Switch_NonDiv3Clk 0x0 |
| #define Gbl_ClkSwitch_pCubeClkD3Switch_Div3Clk 0x1 |
| #define BA_Gbl_ClkSwitch_vScopeClkPllSwitch 0x0167 |
| #define B16Gbl_ClkSwitch_vScopeClkPllSwitch 0x0166 |
| #define LSb32Gbl_ClkSwitch_vScopeClkPllSwitch 30 |
| #define LSb16Gbl_ClkSwitch_vScopeClkPllSwitch 14 |
| #define bGbl_ClkSwitch_vScopeClkPllSwitch 1 |
| #define MSK32Gbl_ClkSwitch_vScopeClkPllSwitch 0x40000000 |
| #define Gbl_ClkSwitch_vScopeClkPllSwitch_SYSPLL 0x0 |
| #define Gbl_ClkSwitch_vScopeClkPllSwitch_AVPLL 0x1 |
| #define BA_Gbl_ClkSwitch_vScopeClkSwitch 0x0167 |
| #define B16Gbl_ClkSwitch_vScopeClkSwitch 0x0166 |
| #define LSb32Gbl_ClkSwitch_vScopeClkSwitch 31 |
| #define LSb16Gbl_ClkSwitch_vScopeClkSwitch 15 |
| #define bGbl_ClkSwitch_vScopeClkSwitch 1 |
| #define MSK32Gbl_ClkSwitch_vScopeClkSwitch 0x80000000 |
| #define Gbl_ClkSwitch_vScopeClkSwitch_SrcClk 0x0 |
| #define Gbl_ClkSwitch_vScopeClkSwitch_DivClk 0x1 |
| #define RA_Gbl_ClkSwitch1 0x0168 |
| #define BA_Gbl_ClkSwitch_vScopeClkD3Switch 0x0168 |
| #define B16Gbl_ClkSwitch_vScopeClkD3Switch 0x0168 |
| #define LSb32Gbl_ClkSwitch_vScopeClkD3Switch 0 |
| #define LSb16Gbl_ClkSwitch_vScopeClkD3Switch 0 |
| #define bGbl_ClkSwitch_vScopeClkD3Switch 1 |
| #define MSK32Gbl_ClkSwitch_vScopeClkD3Switch 0x00000001 |
| #define Gbl_ClkSwitch_vScopeClkD3Switch_NonDiv3Clk 0x0 |
| #define Gbl_ClkSwitch_vScopeClkD3Switch_Div3Clk 0x1 |
| #define BA_Gbl_ClkSwitch_nfcEccClkPllSwitch 0x0168 |
| #define B16Gbl_ClkSwitch_nfcEccClkPllSwitch 0x0168 |
| #define LSb32Gbl_ClkSwitch_nfcEccClkPllSwitch 1 |
| #define LSb16Gbl_ClkSwitch_nfcEccClkPllSwitch 1 |
| #define bGbl_ClkSwitch_nfcEccClkPllSwitch 1 |
| #define MSK32Gbl_ClkSwitch_nfcEccClkPllSwitch 0x00000002 |
| #define Gbl_ClkSwitch_nfcEccClkPllSwitch_SYSPLL 0x0 |
| #define Gbl_ClkSwitch_nfcEccClkPllSwitch_AVPLL 0x1 |
| #define BA_Gbl_ClkSwitch_nfcEccClkSwitch 0x0168 |
| #define B16Gbl_ClkSwitch_nfcEccClkSwitch 0x0168 |
| #define LSb32Gbl_ClkSwitch_nfcEccClkSwitch 2 |
| #define LSb16Gbl_ClkSwitch_nfcEccClkSwitch 2 |
| #define bGbl_ClkSwitch_nfcEccClkSwitch 1 |
| #define MSK32Gbl_ClkSwitch_nfcEccClkSwitch 0x00000004 |
| #define Gbl_ClkSwitch_nfcEccClkSwitch_SrcClk 0x0 |
| #define Gbl_ClkSwitch_nfcEccClkSwitch_DivClk 0x1 |
| #define BA_Gbl_ClkSwitch_nfcEccClkD3Switch 0x0168 |
| #define B16Gbl_ClkSwitch_nfcEccClkD3Switch 0x0168 |
| #define LSb32Gbl_ClkSwitch_nfcEccClkD3Switch 3 |
| #define LSb16Gbl_ClkSwitch_nfcEccClkD3Switch 3 |
| #define bGbl_ClkSwitch_nfcEccClkD3Switch 1 |
| #define MSK32Gbl_ClkSwitch_nfcEccClkD3Switch 0x00000008 |
| #define Gbl_ClkSwitch_nfcEccClkD3Switch_NonDiv3Clk 0x0 |
| #define Gbl_ClkSwitch_nfcEccClkD3Switch_Div3Clk 0x1 |
| #define BA_Gbl_ClkSwitch_vppSysClkPllSwitch 0x0168 |
| #define B16Gbl_ClkSwitch_vppSysClkPllSwitch 0x0168 |
| #define LSb32Gbl_ClkSwitch_vppSysClkPllSwitch 4 |
| #define LSb16Gbl_ClkSwitch_vppSysClkPllSwitch 4 |
| #define bGbl_ClkSwitch_vppSysClkPllSwitch 1 |
| #define MSK32Gbl_ClkSwitch_vppSysClkPllSwitch 0x00000010 |
| #define Gbl_ClkSwitch_vppSysClkPllSwitch_SYSPLL 0x0 |
| #define Gbl_ClkSwitch_vppSysClkPllSwitch_AVPLL 0x1 |
| #define BA_Gbl_ClkSwitch_vppSysClkSwitch 0x0168 |
| #define B16Gbl_ClkSwitch_vppSysClkSwitch 0x0168 |
| #define LSb32Gbl_ClkSwitch_vppSysClkSwitch 5 |
| #define LSb16Gbl_ClkSwitch_vppSysClkSwitch 5 |
| #define bGbl_ClkSwitch_vppSysClkSwitch 1 |
| #define MSK32Gbl_ClkSwitch_vppSysClkSwitch 0x00000020 |
| #define Gbl_ClkSwitch_vppSysClkSwitch_SrcClk 0x0 |
| #define Gbl_ClkSwitch_vppSysClkSwitch_DivClk 0x1 |
| #define BA_Gbl_ClkSwitch_vppSysClkD3Switch 0x0168 |
| #define B16Gbl_ClkSwitch_vppSysClkD3Switch 0x0168 |
| #define LSb32Gbl_ClkSwitch_vppSysClkD3Switch 6 |
| #define LSb16Gbl_ClkSwitch_vppSysClkD3Switch 6 |
| #define bGbl_ClkSwitch_vppSysClkD3Switch 1 |
| #define MSK32Gbl_ClkSwitch_vppSysClkD3Switch 0x00000040 |
| #define Gbl_ClkSwitch_vppSysClkD3Switch_NonDiv3Clk 0x0 |
| #define Gbl_ClkSwitch_vppSysClkD3Switch_Div3Clk 0x1 |
| #define BA_Gbl_ClkSwitch_appClkPllSwitch 0x0168 |
| #define B16Gbl_ClkSwitch_appClkPllSwitch 0x0168 |
| #define LSb32Gbl_ClkSwitch_appClkPllSwitch 7 |
| #define LSb16Gbl_ClkSwitch_appClkPllSwitch 7 |
| #define bGbl_ClkSwitch_appClkPllSwitch 1 |
| #define MSK32Gbl_ClkSwitch_appClkPllSwitch 0x00000080 |
| #define Gbl_ClkSwitch_appClkPllSwitch_SYSPLL 0x0 |
| #define Gbl_ClkSwitch_appClkPllSwitch_AVPLL 0x1 |
| #define BA_Gbl_ClkSwitch_appClkSwitch 0x0169 |
| #define B16Gbl_ClkSwitch_appClkSwitch 0x0168 |
| #define LSb32Gbl_ClkSwitch_appClkSwitch 8 |
| #define LSb16Gbl_ClkSwitch_appClkSwitch 8 |
| #define bGbl_ClkSwitch_appClkSwitch 1 |
| #define MSK32Gbl_ClkSwitch_appClkSwitch 0x00000100 |
| #define Gbl_ClkSwitch_appClkSwitch_SrcClk 0x0 |
| #define Gbl_ClkSwitch_appClkSwitch_DivClk 0x1 |
| #define BA_Gbl_ClkSwitch_appClkD3Switch 0x0169 |
| #define B16Gbl_ClkSwitch_appClkD3Switch 0x0168 |
| #define LSb32Gbl_ClkSwitch_appClkD3Switch 9 |
| #define LSb16Gbl_ClkSwitch_appClkD3Switch 9 |
| #define bGbl_ClkSwitch_appClkD3Switch 1 |
| #define MSK32Gbl_ClkSwitch_appClkD3Switch 0x00000200 |
| #define Gbl_ClkSwitch_appClkD3Switch_NonDiv3Clk 0x0 |
| #define Gbl_ClkSwitch_appClkD3Switch_Div3Clk 0x1 |
| #define BA_Gbl_ClkSwitch_audio0ClkSwitch 0x0169 |
| #define B16Gbl_ClkSwitch_audio0ClkSwitch 0x0168 |
| #define LSb32Gbl_ClkSwitch_audio0ClkSwitch 10 |
| #define LSb16Gbl_ClkSwitch_audio0ClkSwitch 10 |
| #define bGbl_ClkSwitch_audio0ClkSwitch 1 |
| #define MSK32Gbl_ClkSwitch_audio0ClkSwitch 0x00000400 |
| #define Gbl_ClkSwitch_audio0ClkSwitch_SrcClk 0x0 |
| #define Gbl_ClkSwitch_audio0ClkSwitch_DivClk 0x1 |
| #define BA_Gbl_ClkSwitch_audio0ClkD3Switch 0x0169 |
| #define B16Gbl_ClkSwitch_audio0ClkD3Switch 0x0168 |
| #define LSb32Gbl_ClkSwitch_audio0ClkD3Switch 11 |
| #define LSb16Gbl_ClkSwitch_audio0ClkD3Switch 11 |
| #define bGbl_ClkSwitch_audio0ClkD3Switch 1 |
| #define MSK32Gbl_ClkSwitch_audio0ClkD3Switch 0x00000800 |
| #define Gbl_ClkSwitch_audio0ClkD3Switch_NonDiv3Clk 0x0 |
| #define Gbl_ClkSwitch_audio0ClkD3Switch_Div3Clk 0x1 |
| #define BA_Gbl_ClkSwitch_audio1ClkSwitch 0x0169 |
| #define B16Gbl_ClkSwitch_audio1ClkSwitch 0x0168 |
| #define LSb32Gbl_ClkSwitch_audio1ClkSwitch 12 |
| #define LSb16Gbl_ClkSwitch_audio1ClkSwitch 12 |
| #define bGbl_ClkSwitch_audio1ClkSwitch 1 |
| #define MSK32Gbl_ClkSwitch_audio1ClkSwitch 0x00001000 |
| #define Gbl_ClkSwitch_audio1ClkSwitch_SrcClk 0x0 |
| #define Gbl_ClkSwitch_audio1ClkSwitch_DivClk 0x1 |
| #define BA_Gbl_ClkSwitch_audio1ClkD3Switch 0x0169 |
| #define B16Gbl_ClkSwitch_audio1ClkD3Switch 0x0168 |
| #define LSb32Gbl_ClkSwitch_audio1ClkD3Switch 13 |
| #define LSb16Gbl_ClkSwitch_audio1ClkD3Switch 13 |
| #define bGbl_ClkSwitch_audio1ClkD3Switch 1 |
| #define MSK32Gbl_ClkSwitch_audio1ClkD3Switch 0x00002000 |
| #define Gbl_ClkSwitch_audio1ClkD3Switch_NonDiv3Clk 0x0 |
| #define Gbl_ClkSwitch_audio1ClkD3Switch_Div3Clk 0x1 |
| #define BA_Gbl_ClkSwitch_audio2ClkSwitch 0x0169 |
| #define B16Gbl_ClkSwitch_audio2ClkSwitch 0x0168 |
| #define LSb32Gbl_ClkSwitch_audio2ClkSwitch 14 |
| #define LSb16Gbl_ClkSwitch_audio2ClkSwitch 14 |
| #define bGbl_ClkSwitch_audio2ClkSwitch 1 |
| #define MSK32Gbl_ClkSwitch_audio2ClkSwitch 0x00004000 |
| #define Gbl_ClkSwitch_audio2ClkSwitch_SrcClk 0x0 |
| #define Gbl_ClkSwitch_audio2ClkSwitch_DivClk 0x1 |
| #define BA_Gbl_ClkSwitch_audio2ClkD3Switch 0x0169 |
| #define B16Gbl_ClkSwitch_audio2ClkD3Switch 0x0168 |
| #define LSb32Gbl_ClkSwitch_audio2ClkD3Switch 15 |
| #define LSb16Gbl_ClkSwitch_audio2ClkD3Switch 15 |
| #define bGbl_ClkSwitch_audio2ClkD3Switch 1 |
| #define MSK32Gbl_ClkSwitch_audio2ClkD3Switch 0x00008000 |
| #define Gbl_ClkSwitch_audio2ClkD3Switch_NonDiv3Clk 0x0 |
| #define Gbl_ClkSwitch_audio2ClkD3Switch_Div3Clk 0x1 |
| #define BA_Gbl_ClkSwitch_audio3ClkSwitch 0x016A |
| #define B16Gbl_ClkSwitch_audio3ClkSwitch 0x016A |
| #define LSb32Gbl_ClkSwitch_audio3ClkSwitch 16 |
| #define LSb16Gbl_ClkSwitch_audio3ClkSwitch 0 |
| #define bGbl_ClkSwitch_audio3ClkSwitch 1 |
| #define MSK32Gbl_ClkSwitch_audio3ClkSwitch 0x00010000 |
| #define Gbl_ClkSwitch_audio3ClkSwitch_SrcClk 0x0 |
| #define Gbl_ClkSwitch_audio3ClkSwitch_DivClk 0x1 |
| #define BA_Gbl_ClkSwitch_audio3ClkD3Switch 0x016A |
| #define B16Gbl_ClkSwitch_audio3ClkD3Switch 0x016A |
| #define LSb32Gbl_ClkSwitch_audio3ClkD3Switch 17 |
| #define LSb16Gbl_ClkSwitch_audio3ClkD3Switch 1 |
| #define bGbl_ClkSwitch_audio3ClkD3Switch 1 |
| #define MSK32Gbl_ClkSwitch_audio3ClkD3Switch 0x00020000 |
| #define Gbl_ClkSwitch_audio3ClkD3Switch_NonDiv3Clk 0x0 |
| #define Gbl_ClkSwitch_audio3ClkD3Switch_Div3Clk 0x1 |
| #define RA_Gbl_PadSelect 0x016C |
| #define BA_Gbl_PadSelect_GBL_PDB 0x016C |
| #define B16Gbl_PadSelect_GBL_PDB 0x016C |
| #define LSb32Gbl_PadSelect_GBL_PDB 0 |
| #define LSb16Gbl_PadSelect_GBL_PDB 0 |
| #define bGbl_PadSelect_GBL_PDB 1 |
| #define MSK32Gbl_PadSelect_GBL_PDB 0x00000001 |
| #define Gbl_PadSelect_GBL_PDB_NORMAL 0x1 |
| #define Gbl_PadSelect_GBL_PDB_PWRDN 0x0 |
| #define BA_Gbl_PadSelect_NAND_PDB 0x016C |
| #define B16Gbl_PadSelect_NAND_PDB 0x016C |
| #define LSb32Gbl_PadSelect_NAND_PDB 1 |
| #define LSb16Gbl_PadSelect_NAND_PDB 1 |
| #define bGbl_PadSelect_NAND_PDB 1 |
| #define MSK32Gbl_PadSelect_NAND_PDB 0x00000002 |
| #define Gbl_PadSelect_NAND_PDB_NORMAL 0x1 |
| #define Gbl_PadSelect_NAND_PDB_PWRDN 0x0 |
| #define BA_Gbl_PadSelect_SD0_PDB 0x016C |
| #define B16Gbl_PadSelect_SD0_PDB 0x016C |
| #define LSb32Gbl_PadSelect_SD0_PDB 2 |
| #define LSb16Gbl_PadSelect_SD0_PDB 2 |
| #define bGbl_PadSelect_SD0_PDB 1 |
| #define MSK32Gbl_PadSelect_SD0_PDB 0x00000004 |
| #define Gbl_PadSelect_SD0_PDB_NORMAL 0x1 |
| #define Gbl_PadSelect_SD0_PDB_PWRDN 0x0 |
| #define BA_Gbl_PadSelect_SD1_PDB 0x016C |
| #define B16Gbl_PadSelect_SD1_PDB 0x016C |
| #define LSb32Gbl_PadSelect_SD1_PDB 3 |
| #define LSb16Gbl_PadSelect_SD1_PDB 3 |
| #define bGbl_PadSelect_SD1_PDB 1 |
| #define MSK32Gbl_PadSelect_SD1_PDB 0x00000008 |
| #define Gbl_PadSelect_SD1_PDB_NORMAL 0x1 |
| #define Gbl_PadSelect_SD1_PDB_PWRDN 0x0 |
| #define BA_Gbl_PadSelect_SPI_PDB 0x016C |
| #define B16Gbl_PadSelect_SPI_PDB 0x016C |
| #define LSb32Gbl_PadSelect_SPI_PDB 4 |
| #define LSb16Gbl_PadSelect_SPI_PDB 4 |
| #define bGbl_PadSelect_SPI_PDB 1 |
| #define MSK32Gbl_PadSelect_SPI_PDB 0x00000010 |
| #define Gbl_PadSelect_SPI_PDB_NORMAL 0x1 |
| #define Gbl_PadSelect_SPI_PDB_PWRDN 0x0 |
| #define BA_Gbl_PadSelect_CLK0_V18EN 0x016C |
| #define B16Gbl_PadSelect_CLK0_V18EN 0x016C |
| #define LSb32Gbl_PadSelect_CLK0_V18EN 5 |
| #define LSb16Gbl_PadSelect_CLK0_V18EN 5 |
| #define bGbl_PadSelect_CLK0_V18EN 1 |
| #define MSK32Gbl_PadSelect_CLK0_V18EN 0x00000020 |
| #define Gbl_PadSelect_CLK0_V18EN_V1P8 0x1 |
| #define Gbl_PadSelect_CLK0_V18EN_V3R3 0x0 |
| #define BA_Gbl_PadSelect_DVIO0_V18EN 0x016C |
| #define B16Gbl_PadSelect_DVIO0_V18EN 0x016C |
| #define LSb32Gbl_PadSelect_DVIO0_V18EN 6 |
| #define LSb16Gbl_PadSelect_DVIO0_V18EN 6 |
| #define bGbl_PadSelect_DVIO0_V18EN 1 |
| #define MSK32Gbl_PadSelect_DVIO0_V18EN 0x00000040 |
| #define Gbl_PadSelect_DVIO0_V18EN_V1P8 0x1 |
| #define Gbl_PadSelect_DVIO0_V18EN_V3R3 0x0 |
| #define BA_Gbl_PadSelect_GBL_V18EN 0x016C |
| #define B16Gbl_PadSelect_GBL_V18EN 0x016C |
| #define LSb32Gbl_PadSelect_GBL_V18EN 7 |
| #define LSb16Gbl_PadSelect_GBL_V18EN 7 |
| #define bGbl_PadSelect_GBL_V18EN 1 |
| #define MSK32Gbl_PadSelect_GBL_V18EN 0x00000080 |
| #define Gbl_PadSelect_GBL_V18EN_V1P8 0x1 |
| #define Gbl_PadSelect_GBL_V18EN_V3R3 0x0 |
| #define BA_Gbl_PadSelect_SPI0_V18EN 0x016D |
| #define B16Gbl_PadSelect_SPI0_V18EN 0x016C |
| #define LSb32Gbl_PadSelect_SPI0_V18EN 8 |
| #define LSb16Gbl_PadSelect_SPI0_V18EN 8 |
| #define bGbl_PadSelect_SPI0_V18EN 1 |
| #define MSK32Gbl_PadSelect_SPI0_V18EN 0x00000100 |
| #define Gbl_PadSelect_SPI0_V18EN_V1P8 0x1 |
| #define Gbl_PadSelect_SPI0_V18EN_V3R3 0x0 |
| #define BA_Gbl_PadSelect_SD0_V18EN 0x016D |
| #define B16Gbl_PadSelect_SD0_V18EN 0x016C |
| #define LSb32Gbl_PadSelect_SD0_V18EN 9 |
| #define LSb16Gbl_PadSelect_SD0_V18EN 9 |
| #define bGbl_PadSelect_SD0_V18EN 1 |
| #define MSK32Gbl_PadSelect_SD0_V18EN 0x00000200 |
| #define Gbl_PadSelect_SD0_V18EN_V1P8 0x1 |
| #define Gbl_PadSelect_SD0_V18EN_V3R3 0x0 |
| #define BA_Gbl_PadSelect_SD10_V18EN 0x016D |
| #define B16Gbl_PadSelect_SD10_V18EN 0x016C |
| #define LSb32Gbl_PadSelect_SD10_V18EN 10 |
| #define LSb16Gbl_PadSelect_SD10_V18EN 10 |
| #define bGbl_PadSelect_SD10_V18EN 1 |
| #define MSK32Gbl_PadSelect_SD10_V18EN 0x00000400 |
| #define Gbl_PadSelect_SD10_V18EN_V1P8 0x1 |
| #define Gbl_PadSelect_SD10_V18EN_V3R3 0x0 |
| #define BA_Gbl_PadSelect_CLK0_V25EN 0x016D |
| #define B16Gbl_PadSelect_CLK0_V25EN 0x016C |
| #define LSb32Gbl_PadSelect_CLK0_V25EN 11 |
| #define LSb16Gbl_PadSelect_CLK0_V25EN 11 |
| #define bGbl_PadSelect_CLK0_V25EN 1 |
| #define MSK32Gbl_PadSelect_CLK0_V25EN 0x00000800 |
| #define Gbl_PadSelect_CLK0_V25EN_Enable 0x1 |
| #define Gbl_PadSelect_CLK0_V25EN_Disable 0x0 |
| #define BA_Gbl_PadSelect_DVIO0_V25EN 0x016D |
| #define B16Gbl_PadSelect_DVIO0_V25EN 0x016C |
| #define LSb32Gbl_PadSelect_DVIO0_V25EN 12 |
| #define LSb16Gbl_PadSelect_DVIO0_V25EN 12 |
| #define bGbl_PadSelect_DVIO0_V25EN 1 |
| #define MSK32Gbl_PadSelect_DVIO0_V25EN 0x00001000 |
| #define Gbl_PadSelect_DVIO0_V25EN_Enable 0x1 |
| #define Gbl_PadSelect_DVIO0_V25EN_Disable 0x0 |
| #define BA_Gbl_PadSelect_TS0_V25EN 0x016D |
| #define B16Gbl_PadSelect_TS0_V25EN 0x016C |
| #define LSb32Gbl_PadSelect_TS0_V25EN 13 |
| #define LSb16Gbl_PadSelect_TS0_V25EN 13 |
| #define bGbl_PadSelect_TS0_V25EN 1 |
| #define MSK32Gbl_PadSelect_TS0_V25EN 0x00002000 |
| #define Gbl_PadSelect_TS0_V25EN_Enable 0x1 |
| #define Gbl_PadSelect_TS0_V25EN_Disable 0x0 |
| #define BA_Gbl_PadSelect_SPI0_V25EN 0x016D |
| #define B16Gbl_PadSelect_SPI0_V25EN 0x016C |
| #define LSb32Gbl_PadSelect_SPI0_V25EN 14 |
| #define LSb16Gbl_PadSelect_SPI0_V25EN 14 |
| #define bGbl_PadSelect_SPI0_V25EN 1 |
| #define MSK32Gbl_PadSelect_SPI0_V25EN 0x00004000 |
| #define Gbl_PadSelect_SPI0_V25EN_Enable 0x1 |
| #define Gbl_PadSelect_SPI0_V25EN_Disable 0x0 |
| #define BA_Gbl_PadSelect_U6_V25EN 0x016D |
| #define B16Gbl_PadSelect_U6_V25EN 0x016C |
| #define LSb32Gbl_PadSelect_U6_V25EN 15 |
| #define LSb16Gbl_PadSelect_U6_V25EN 15 |
| #define bGbl_PadSelect_U6_V25EN 1 |
| #define MSK32Gbl_PadSelect_U6_V25EN 0x00008000 |
| #define Gbl_PadSelect_U6_V25EN_Enable 0x1 |
| #define Gbl_PadSelect_U6_V25EN_Disable 0x0 |
| #define BA_Gbl_PadSelect_U7_V25EN 0x016E |
| #define B16Gbl_PadSelect_U7_V25EN 0x016E |
| #define LSb32Gbl_PadSelect_U7_V25EN 16 |
| #define LSb16Gbl_PadSelect_U7_V25EN 0 |
| #define bGbl_PadSelect_U7_V25EN 1 |
| #define MSK32Gbl_PadSelect_U7_V25EN 0x00010000 |
| #define Gbl_PadSelect_U7_V25EN_Enable 0x1 |
| #define Gbl_PadSelect_U7_V25EN_Disable 0x0 |
| #define BA_Gbl_PadSelect_U8_V25EN 0x016E |
| #define B16Gbl_PadSelect_U8_V25EN 0x016E |
| #define LSb32Gbl_PadSelect_U8_V25EN 17 |
| #define LSb16Gbl_PadSelect_U8_V25EN 1 |
| #define bGbl_PadSelect_U8_V25EN 1 |
| #define MSK32Gbl_PadSelect_U8_V25EN 0x00020000 |
| #define Gbl_PadSelect_U8_V25EN_Enable 0x1 |
| #define Gbl_PadSelect_U8_V25EN_Disable 0x0 |
| #define BA_Gbl_PadSelect_W14_V25EN 0x016E |
| #define B16Gbl_PadSelect_W14_V25EN 0x016E |
| #define LSb32Gbl_PadSelect_W14_V25EN 18 |
| #define LSb16Gbl_PadSelect_W14_V25EN 2 |
| #define bGbl_PadSelect_W14_V25EN 1 |
| #define MSK32Gbl_PadSelect_W14_V25EN 0x00040000 |
| #define Gbl_PadSelect_W14_V25EN_Enable 0x1 |
| #define Gbl_PadSelect_W14_V25EN_Disable 0x0 |
| #define BA_Gbl_PadSelect_DVU0_V25EN 0x016E |
| #define B16Gbl_PadSelect_DVU0_V25EN 0x016E |
| #define LSb32Gbl_PadSelect_DVU0_V25EN 19 |
| #define LSb16Gbl_PadSelect_DVU0_V25EN 3 |
| #define bGbl_PadSelect_DVU0_V25EN 1 |
| #define MSK32Gbl_PadSelect_DVU0_V25EN 0x00080000 |
| #define Gbl_PadSelect_DVU0_V25EN_Enable 0x1 |
| #define Gbl_PadSelect_DVU0_V25EN_Disable 0x0 |
| #define BA_Gbl_PadSelect_GBL_V25EN 0x016E |
| #define B16Gbl_PadSelect_GBL_V25EN 0x016E |
| #define LSb32Gbl_PadSelect_GBL_V25EN 20 |
| #define LSb16Gbl_PadSelect_GBL_V25EN 4 |
| #define bGbl_PadSelect_GBL_V25EN 1 |
| #define MSK32Gbl_PadSelect_GBL_V25EN 0x00100000 |
| #define Gbl_PadSelect_GBL_V25EN_Enable 0x1 |
| #define Gbl_PadSelect_GBL_V25EN_Disable 0x0 |
| #define BA_Gbl_PadSelect_SD0_V25EN 0x016E |
| #define B16Gbl_PadSelect_SD0_V25EN 0x016E |
| #define LSb32Gbl_PadSelect_SD0_V25EN 21 |
| #define LSb16Gbl_PadSelect_SD0_V25EN 5 |
| #define bGbl_PadSelect_SD0_V25EN 1 |
| #define MSK32Gbl_PadSelect_SD0_V25EN 0x00200000 |
| #define Gbl_PadSelect_SD0_V25EN_Enable 0x1 |
| #define Gbl_PadSelect_SD0_V25EN_Disable 0x0 |
| #define BA_Gbl_PadSelect_DVIO_OEN 0x016E |
| #define B16Gbl_PadSelect_DVIO_OEN 0x016E |
| #define LSb32Gbl_PadSelect_DVIO_OEN 22 |
| #define LSb16Gbl_PadSelect_DVIO_OEN 6 |
| #define bGbl_PadSelect_DVIO_OEN 1 |
| #define MSK32Gbl_PadSelect_DVIO_OEN 0x00400000 |
| #define Gbl_PadSelect_DVIO_OEN_Enable 0x1 |
| #define Gbl_PadSelect_DVIO_OEN_Disable 0x0 |
| #define BA_Gbl_PadSelect_CLK0_ZN 0x016E |
| #define B16Gbl_PadSelect_CLK0_ZN 0x016E |
| #define LSb32Gbl_PadSelect_CLK0_ZN 23 |
| #define LSb16Gbl_PadSelect_CLK0_ZN 7 |
| #define bGbl_PadSelect_CLK0_ZN 3 |
| #define MSK32Gbl_PadSelect_CLK0_ZN 0x03800000 |
| #define BA_Gbl_PadSelect_CLK0_ZP 0x016F |
| #define B16Gbl_PadSelect_CLK0_ZP 0x016E |
| #define LSb32Gbl_PadSelect_CLK0_ZP 26 |
| #define LSb16Gbl_PadSelect_CLK0_ZP 10 |
| #define bGbl_PadSelect_CLK0_ZP 3 |
| #define MSK32Gbl_PadSelect_CLK0_ZP 0x1C000000 |
| #define BA_Gbl_PadSelect_DVIO0_ZN 0x016F |
| #define B16Gbl_PadSelect_DVIO0_ZN 0x016E |
| #define LSb32Gbl_PadSelect_DVIO0_ZN 29 |
| #define LSb16Gbl_PadSelect_DVIO0_ZN 13 |
| #define bGbl_PadSelect_DVIO0_ZN 3 |
| #define MSK32Gbl_PadSelect_DVIO0_ZN 0xE0000000 |
| #define RA_Gbl_PadSelect1 0x0170 |
| #define BA_Gbl_PadSelect_DVIO0_ZP 0x0170 |
| #define B16Gbl_PadSelect_DVIO0_ZP 0x0170 |
| #define LSb32Gbl_PadSelect_DVIO0_ZP 0 |
| #define LSb16Gbl_PadSelect_DVIO0_ZP 0 |
| #define bGbl_PadSelect_DVIO0_ZP 3 |
| #define MSK32Gbl_PadSelect_DVIO0_ZP 0x00000007 |
| #define BA_Gbl_PadSelect_ND0_ZN 0x0170 |
| #define B16Gbl_PadSelect_ND0_ZN 0x0170 |
| #define LSb32Gbl_PadSelect_ND0_ZN 3 |
| #define LSb16Gbl_PadSelect_ND0_ZN 3 |
| #define bGbl_PadSelect_ND0_ZN 4 |
| #define MSK32Gbl_PadSelect_ND0_ZN 0x00000078 |
| #define BA_Gbl_PadSelect_ND0_ZP 0x0170 |
| #define B16Gbl_PadSelect_ND0_ZP 0x0170 |
| #define LSb32Gbl_PadSelect_ND0_ZP 7 |
| #define LSb16Gbl_PadSelect_ND0_ZP 7 |
| #define bGbl_PadSelect_ND0_ZP 4 |
| #define MSK32Gbl_PadSelect_ND0_ZP 0x00000780 |
| #define BA_Gbl_PadSelect_GBL_ZN 0x0171 |
| #define B16Gbl_PadSelect_GBL_ZN 0x0170 |
| #define LSb32Gbl_PadSelect_GBL_ZN 11 |
| #define LSb16Gbl_PadSelect_GBL_ZN 11 |
| #define bGbl_PadSelect_GBL_ZN 4 |
| #define MSK32Gbl_PadSelect_GBL_ZN 0x00007800 |
| #define BA_Gbl_PadSelect_GBL_ZP 0x0171 |
| #define B16Gbl_PadSelect_GBL_ZP 0x0170 |
| #define LSb32Gbl_PadSelect_GBL_ZP 15 |
| #define LSb16Gbl_PadSelect_GBL_ZP 15 |
| #define bGbl_PadSelect_GBL_ZP 4 |
| #define MSK32Gbl_PadSelect_GBL_ZP 0x00078000 |
| #define BA_Gbl_PadSelect_SPI0_ZN 0x0172 |
| #define B16Gbl_PadSelect_SPI0_ZN 0x0172 |
| #define LSb32Gbl_PadSelect_SPI0_ZN 19 |
| #define LSb16Gbl_PadSelect_SPI0_ZN 3 |
| #define bGbl_PadSelect_SPI0_ZN 4 |
| #define MSK32Gbl_PadSelect_SPI0_ZN 0x00780000 |
| #define BA_Gbl_PadSelect_SPI0_ZP 0x0172 |
| #define B16Gbl_PadSelect_SPI0_ZP 0x0172 |
| #define LSb32Gbl_PadSelect_SPI0_ZP 23 |
| #define LSb16Gbl_PadSelect_SPI0_ZP 7 |
| #define bGbl_PadSelect_SPI0_ZP 4 |
| #define MSK32Gbl_PadSelect_SPI0_ZP 0x07800000 |
| #define BA_Gbl_PadSelect_SD0_ZN 0x0173 |
| #define B16Gbl_PadSelect_SD0_ZN 0x0172 |
| #define LSb32Gbl_PadSelect_SD0_ZN 27 |
| #define LSb16Gbl_PadSelect_SD0_ZN 11 |
| #define bGbl_PadSelect_SD0_ZN 4 |
| #define MSK32Gbl_PadSelect_SD0_ZN 0x78000000 |
| #define RA_Gbl_PadSelect2 0x0174 |
| #define BA_Gbl_PadSelect_SD0_ZP 0x0174 |
| #define B16Gbl_PadSelect_SD0_ZP 0x0174 |
| #define LSb32Gbl_PadSelect_SD0_ZP 0 |
| #define LSb16Gbl_PadSelect_SD0_ZP 0 |
| #define bGbl_PadSelect_SD0_ZP 4 |
| #define MSK32Gbl_PadSelect_SD0_ZP 0x0000000F |
| #define BA_Gbl_PadSelect_SD10_ZN 0x0174 |
| #define B16Gbl_PadSelect_SD10_ZN 0x0174 |
| #define LSb32Gbl_PadSelect_SD10_ZN 4 |
| #define LSb16Gbl_PadSelect_SD10_ZN 4 |
| #define bGbl_PadSelect_SD10_ZN 4 |
| #define MSK32Gbl_PadSelect_SD10_ZN 0x000000F0 |
| #define BA_Gbl_PadSelect_SD10_ZP 0x0175 |
| #define B16Gbl_PadSelect_SD10_ZP 0x0174 |
| #define LSb32Gbl_PadSelect_SD10_ZP 8 |
| #define LSb16Gbl_PadSelect_SD10_ZP 8 |
| #define bGbl_PadSelect_SD10_ZP 4 |
| #define MSK32Gbl_PadSelect_SD10_ZP 0x00000F00 |
| #define BA_Gbl_PadSelect_DVIO_1_V18EN 0x0175 |
| #define B16Gbl_PadSelect_DVIO_1_V18EN 0x0174 |
| #define LSb32Gbl_PadSelect_DVIO_1_V18EN 12 |
| #define LSb16Gbl_PadSelect_DVIO_1_V18EN 12 |
| #define bGbl_PadSelect_DVIO_1_V18EN 1 |
| #define MSK32Gbl_PadSelect_DVIO_1_V18EN 0x00001000 |
| #define Gbl_PadSelect_DVIO_1_V18EN_V1P8 0x1 |
| #define Gbl_PadSelect_DVIO_1_V18EN_V3R3 0x0 |
| #define BA_Gbl_PadSelect_I2S_V18EN 0x0175 |
| #define B16Gbl_PadSelect_I2S_V18EN 0x0174 |
| #define LSb32Gbl_PadSelect_I2S_V18EN 13 |
| #define LSb16Gbl_PadSelect_I2S_V18EN 13 |
| #define bGbl_PadSelect_I2S_V18EN 1 |
| #define MSK32Gbl_PadSelect_I2S_V18EN 0x00002000 |
| #define Gbl_PadSelect_I2S_V18EN_V1P8 0x1 |
| #define Gbl_PadSelect_I2S_V18EN_V3R3 0x0 |
| #define BA_Gbl_PadSelect_DVIO_1_V25EN 0x0175 |
| #define B16Gbl_PadSelect_DVIO_1_V25EN 0x0174 |
| #define LSb32Gbl_PadSelect_DVIO_1_V25EN 14 |
| #define LSb16Gbl_PadSelect_DVIO_1_V25EN 14 |
| #define bGbl_PadSelect_DVIO_1_V25EN 1 |
| #define MSK32Gbl_PadSelect_DVIO_1_V25EN 0x00004000 |
| #define Gbl_PadSelect_DVIO_1_V25EN_Enable 0x1 |
| #define Gbl_PadSelect_DVIO_1_V25EN_Disable 0x0 |
| #define BA_Gbl_PadSelect_I2S_V25EN 0x0175 |
| #define B16Gbl_PadSelect_I2S_V25EN 0x0174 |
| #define LSb32Gbl_PadSelect_I2S_V25EN 15 |
| #define LSb16Gbl_PadSelect_I2S_V25EN 15 |
| #define bGbl_PadSelect_I2S_V25EN 1 |
| #define MSK32Gbl_PadSelect_I2S_V25EN 0x00008000 |
| #define Gbl_PadSelect_I2S_V25EN_Enable 0x1 |
| #define Gbl_PadSelect_I2S_V25EN_Disable 0x0 |
| #define BA_Gbl_PadSelect_DVIO_1_ZN 0x0176 |
| #define B16Gbl_PadSelect_DVIO_1_ZN 0x0176 |
| #define LSb32Gbl_PadSelect_DVIO_1_ZN 16 |
| #define LSb16Gbl_PadSelect_DVIO_1_ZN 0 |
| #define bGbl_PadSelect_DVIO_1_ZN 3 |
| #define MSK32Gbl_PadSelect_DVIO_1_ZN 0x00070000 |
| #define BA_Gbl_PadSelect_DVIO_1_ZP 0x0176 |
| #define B16Gbl_PadSelect_DVIO_1_ZP 0x0176 |
| #define LSb32Gbl_PadSelect_DVIO_1_ZP 19 |
| #define LSb16Gbl_PadSelect_DVIO_1_ZP 3 |
| #define bGbl_PadSelect_DVIO_1_ZP 3 |
| #define MSK32Gbl_PadSelect_DVIO_1_ZP 0x00380000 |
| #define BA_Gbl_PadSelect_I2S_ZN 0x0176 |
| #define B16Gbl_PadSelect_I2S_ZN 0x0176 |
| #define LSb32Gbl_PadSelect_I2S_ZN 22 |
| #define LSb16Gbl_PadSelect_I2S_ZN 6 |
| #define bGbl_PadSelect_I2S_ZN 3 |
| #define MSK32Gbl_PadSelect_I2S_ZN 0x01C00000 |
| #define BA_Gbl_PadSelect_I2S_ZP 0x0177 |
| #define B16Gbl_PadSelect_I2S_ZP 0x0176 |
| #define LSb32Gbl_PadSelect_I2S_ZP 25 |
| #define LSb16Gbl_PadSelect_I2S_ZP 9 |
| #define bGbl_PadSelect_I2S_ZP 3 |
| #define MSK32Gbl_PadSelect_I2S_ZP 0x0E000000 |
| #define RA_Gbl_ResetTrigger 0x0178 |
| #define BA_Gbl_ResetTrigger_chipReset 0x0178 |
| #define B16Gbl_ResetTrigger_chipReset 0x0178 |
| #define LSb32Gbl_ResetTrigger_chipReset 0 |
| #define LSb16Gbl_ResetTrigger_chipReset 0 |
| #define bGbl_ResetTrigger_chipReset 1 |
| #define MSK32Gbl_ResetTrigger_chipReset 0x00000001 |
| #define Gbl_ResetTrigger_chipReset_assert 0x1 |
| #define Gbl_ResetTrigger_chipReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_audio0ClkReset 0x0178 |
| #define B16Gbl_ResetTrigger_audio0ClkReset 0x0178 |
| #define LSb32Gbl_ResetTrigger_audio0ClkReset 1 |
| #define LSb16Gbl_ResetTrigger_audio0ClkReset 1 |
| #define bGbl_ResetTrigger_audio0ClkReset 1 |
| #define MSK32Gbl_ResetTrigger_audio0ClkReset 0x00000002 |
| #define Gbl_ResetTrigger_audio0ClkReset_assert 0x1 |
| #define Gbl_ResetTrigger_audio0ClkReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_audio1ClkReset 0x0178 |
| #define B16Gbl_ResetTrigger_audio1ClkReset 0x0178 |
| #define LSb32Gbl_ResetTrigger_audio1ClkReset 2 |
| #define LSb16Gbl_ResetTrigger_audio1ClkReset 2 |
| #define bGbl_ResetTrigger_audio1ClkReset 1 |
| #define MSK32Gbl_ResetTrigger_audio1ClkReset 0x00000004 |
| #define Gbl_ResetTrigger_audio1ClkReset_assert 0x1 |
| #define Gbl_ResetTrigger_audio1ClkReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_audio2ClkReset 0x0178 |
| #define B16Gbl_ResetTrigger_audio2ClkReset 0x0178 |
| #define LSb32Gbl_ResetTrigger_audio2ClkReset 3 |
| #define LSb16Gbl_ResetTrigger_audio2ClkReset 3 |
| #define bGbl_ResetTrigger_audio2ClkReset 1 |
| #define MSK32Gbl_ResetTrigger_audio2ClkReset 0x00000008 |
| #define Gbl_ResetTrigger_audio2ClkReset_assert 0x1 |
| #define Gbl_ResetTrigger_audio2ClkReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_audio3ClkReset 0x0178 |
| #define B16Gbl_ResetTrigger_audio3ClkReset 0x0178 |
| #define LSb32Gbl_ResetTrigger_audio3ClkReset 4 |
| #define LSb16Gbl_ResetTrigger_audio3ClkReset 4 |
| #define bGbl_ResetTrigger_audio3ClkReset 1 |
| #define MSK32Gbl_ResetTrigger_audio3ClkReset 0x00000010 |
| #define Gbl_ResetTrigger_audio3ClkReset_assert 0x1 |
| #define Gbl_ResetTrigger_audio3ClkReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_audioHdClkReset 0x0178 |
| #define B16Gbl_ResetTrigger_audioHdClkReset 0x0178 |
| #define LSb32Gbl_ResetTrigger_audioHdClkReset 5 |
| #define LSb16Gbl_ResetTrigger_audioHdClkReset 5 |
| #define bGbl_ResetTrigger_audioHdClkReset 1 |
| #define MSK32Gbl_ResetTrigger_audioHdClkReset 0x00000020 |
| #define Gbl_ResetTrigger_audioHdClkReset_assert 0x1 |
| #define Gbl_ResetTrigger_audioHdClkReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_sysPllSyncReset 0x0178 |
| #define B16Gbl_ResetTrigger_sysPllSyncReset 0x0178 |
| #define LSb32Gbl_ResetTrigger_sysPllSyncReset 6 |
| #define LSb16Gbl_ResetTrigger_sysPllSyncReset 6 |
| #define bGbl_ResetTrigger_sysPllSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_sysPllSyncReset 0x00000040 |
| #define Gbl_ResetTrigger_sysPllSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_sysPllSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_memPllSyncReset 0x0178 |
| #define B16Gbl_ResetTrigger_memPllSyncReset 0x0178 |
| #define LSb32Gbl_ResetTrigger_memPllSyncReset 7 |
| #define LSb16Gbl_ResetTrigger_memPllSyncReset 7 |
| #define bGbl_ResetTrigger_memPllSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_memPllSyncReset 0x00000080 |
| #define Gbl_ResetTrigger_memPllSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_memPllSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_cpu1PllSyncReset 0x0179 |
| #define B16Gbl_ResetTrigger_cpu1PllSyncReset 0x0178 |
| #define LSb32Gbl_ResetTrigger_cpu1PllSyncReset 8 |
| #define LSb16Gbl_ResetTrigger_cpu1PllSyncReset 8 |
| #define bGbl_ResetTrigger_cpu1PllSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_cpu1PllSyncReset 0x00000100 |
| #define Gbl_ResetTrigger_cpu1PllSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_cpu1PllSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_cpu0SyncReset 0x0179 |
| #define B16Gbl_ResetTrigger_cpu0SyncReset 0x0178 |
| #define LSb32Gbl_ResetTrigger_cpu0SyncReset 9 |
| #define LSb16Gbl_ResetTrigger_cpu0SyncReset 9 |
| #define bGbl_ResetTrigger_cpu0SyncReset 1 |
| #define MSK32Gbl_ResetTrigger_cpu0SyncReset 0x00000200 |
| #define Gbl_ResetTrigger_cpu0SyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_cpu0SyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_cpu1SyncReset 0x0179 |
| #define B16Gbl_ResetTrigger_cpu1SyncReset 0x0178 |
| #define LSb32Gbl_ResetTrigger_cpu1SyncReset 10 |
| #define LSb16Gbl_ResetTrigger_cpu1SyncReset 10 |
| #define bGbl_ResetTrigger_cpu1SyncReset 1 |
| #define MSK32Gbl_ResetTrigger_cpu1SyncReset 0x00000400 |
| #define Gbl_ResetTrigger_cpu1SyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_cpu1SyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_socDdrSyncReset 0x0179 |
| #define B16Gbl_ResetTrigger_socDdrSyncReset 0x0178 |
| #define LSb32Gbl_ResetTrigger_socDdrSyncReset 11 |
| #define LSb16Gbl_ResetTrigger_socDdrSyncReset 11 |
| #define bGbl_ResetTrigger_socDdrSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_socDdrSyncReset 0x00000800 |
| #define Gbl_ResetTrigger_socDdrSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_socDdrSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_gfxSyncReset 0x0179 |
| #define B16Gbl_ResetTrigger_gfxSyncReset 0x0178 |
| #define LSb32Gbl_ResetTrigger_gfxSyncReset 12 |
| #define LSb16Gbl_ResetTrigger_gfxSyncReset 12 |
| #define bGbl_ResetTrigger_gfxSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_gfxSyncReset 0x00001000 |
| #define Gbl_ResetTrigger_gfxSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_gfxSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_zspSyncReset 0x0179 |
| #define B16Gbl_ResetTrigger_zspSyncReset 0x0178 |
| #define LSb32Gbl_ResetTrigger_zspSyncReset 13 |
| #define LSb16Gbl_ResetTrigger_zspSyncReset 13 |
| #define bGbl_ResetTrigger_zspSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_zspSyncReset 0x00002000 |
| #define Gbl_ResetTrigger_zspSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_zspSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_avioSyncReset 0x0179 |
| #define B16Gbl_ResetTrigger_avioSyncReset 0x0178 |
| #define LSb32Gbl_ResetTrigger_avioSyncReset 14 |
| #define LSb16Gbl_ResetTrigger_avioSyncReset 14 |
| #define bGbl_ResetTrigger_avioSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_avioSyncReset 0x00004000 |
| #define Gbl_ResetTrigger_avioSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_avioSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_perifSyncReset 0x0179 |
| #define B16Gbl_ResetTrigger_perifSyncReset 0x0178 |
| #define LSb32Gbl_ResetTrigger_perifSyncReset 15 |
| #define LSb16Gbl_ResetTrigger_perifSyncReset 15 |
| #define bGbl_ResetTrigger_perifSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_perifSyncReset 0x00008000 |
| #define Gbl_ResetTrigger_perifSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_perifSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_gethSyncReset 0x017A |
| #define B16Gbl_ResetTrigger_gethSyncReset 0x017A |
| #define LSb32Gbl_ResetTrigger_gethSyncReset 16 |
| #define LSb16Gbl_ResetTrigger_gethSyncReset 0 |
| #define bGbl_ResetTrigger_gethSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_gethSyncReset 0x00010000 |
| #define Gbl_ResetTrigger_gethSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_gethSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_sataSyncReset 0x017A |
| #define B16Gbl_ResetTrigger_sataSyncReset 0x017A |
| #define LSb32Gbl_ResetTrigger_sataSyncReset 17 |
| #define LSb16Gbl_ResetTrigger_sataSyncReset 1 |
| #define bGbl_ResetTrigger_sataSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_sataSyncReset 0x00020000 |
| #define Gbl_ResetTrigger_sataSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_sataSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_geth1SyncReset 0x017A |
| #define B16Gbl_ResetTrigger_geth1SyncReset 0x017A |
| #define LSb32Gbl_ResetTrigger_geth1SyncReset 18 |
| #define LSb16Gbl_ResetTrigger_geth1SyncReset 2 |
| #define bGbl_ResetTrigger_geth1SyncReset 1 |
| #define MSK32Gbl_ResetTrigger_geth1SyncReset 0x00040000 |
| #define Gbl_ResetTrigger_geth1SyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_geth1SyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_ahbApbSyncReset 0x017A |
| #define B16Gbl_ResetTrigger_ahbApbSyncReset 0x017A |
| #define LSb32Gbl_ResetTrigger_ahbApbSyncReset 19 |
| #define LSb16Gbl_ResetTrigger_ahbApbSyncReset 3 |
| #define bGbl_ResetTrigger_ahbApbSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_ahbApbSyncReset 0x00080000 |
| #define Gbl_ResetTrigger_ahbApbSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_ahbApbSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_nanfSyncReset 0x017A |
| #define B16Gbl_ResetTrigger_nanfSyncReset 0x017A |
| #define LSb32Gbl_ResetTrigger_nanfSyncReset 20 |
| #define LSb16Gbl_ResetTrigger_nanfSyncReset 4 |
| #define bGbl_ResetTrigger_nanfSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_nanfSyncReset 0x00100000 |
| #define Gbl_ResetTrigger_nanfSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_nanfSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_smemcSyncReset 0x017A |
| #define B16Gbl_ResetTrigger_smemcSyncReset 0x017A |
| #define LSb32Gbl_ResetTrigger_smemcSyncReset 21 |
| #define LSb16Gbl_ResetTrigger_smemcSyncReset 5 |
| #define bGbl_ResetTrigger_smemcSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_smemcSyncReset 0x00200000 |
| #define Gbl_ResetTrigger_smemcSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_smemcSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_drmSyncReset 0x017A |
| #define B16Gbl_ResetTrigger_drmSyncReset 0x017A |
| #define LSb32Gbl_ResetTrigger_drmSyncReset 22 |
| #define LSb16Gbl_ResetTrigger_drmSyncReset 6 |
| #define bGbl_ResetTrigger_drmSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_drmSyncReset 0x00400000 |
| #define Gbl_ResetTrigger_drmSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_drmSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_usb0SyncReset 0x017A |
| #define B16Gbl_ResetTrigger_usb0SyncReset 0x017A |
| #define LSb32Gbl_ResetTrigger_usb0SyncReset 23 |
| #define LSb16Gbl_ResetTrigger_usb0SyncReset 7 |
| #define bGbl_ResetTrigger_usb0SyncReset 1 |
| #define MSK32Gbl_ResetTrigger_usb0SyncReset 0x00800000 |
| #define Gbl_ResetTrigger_usb0SyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_usb0SyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_usb1SyncReset 0x017B |
| #define B16Gbl_ResetTrigger_usb1SyncReset 0x017A |
| #define LSb32Gbl_ResetTrigger_usb1SyncReset 24 |
| #define LSb16Gbl_ResetTrigger_usb1SyncReset 8 |
| #define bGbl_ResetTrigger_usb1SyncReset 1 |
| #define MSK32Gbl_ResetTrigger_usb1SyncReset 0x01000000 |
| #define Gbl_ResetTrigger_usb1SyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_usb1SyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_pBridgeSyncReset 0x017B |
| #define B16Gbl_ResetTrigger_pBridgeSyncReset 0x017A |
| #define LSb32Gbl_ResetTrigger_pBridgeSyncReset 25 |
| #define LSb16Gbl_ResetTrigger_pBridgeSyncReset 9 |
| #define bGbl_ResetTrigger_pBridgeSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_pBridgeSyncReset 0x02000000 |
| #define Gbl_ResetTrigger_pBridgeSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_pBridgeSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_vppSyncReset 0x017B |
| #define B16Gbl_ResetTrigger_vppSyncReset 0x017A |
| #define LSb32Gbl_ResetTrigger_vppSyncReset 26 |
| #define LSb16Gbl_ResetTrigger_vppSyncReset 10 |
| #define bGbl_ResetTrigger_vppSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_vppSyncReset 0x04000000 |
| #define Gbl_ResetTrigger_vppSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_vppSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_vipSyncReset 0x017B |
| #define B16Gbl_ResetTrigger_vipSyncReset 0x017A |
| #define LSb32Gbl_ResetTrigger_vipSyncReset 27 |
| #define LSb16Gbl_ResetTrigger_vipSyncReset 11 |
| #define bGbl_ResetTrigger_vipSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_vipSyncReset 0x08000000 |
| #define Gbl_ResetTrigger_vipSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_vipSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_appSyncReset 0x017B |
| #define B16Gbl_ResetTrigger_appSyncReset 0x017A |
| #define LSb32Gbl_ResetTrigger_appSyncReset 28 |
| #define LSb16Gbl_ResetTrigger_appSyncReset 12 |
| #define bGbl_ResetTrigger_appSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_appSyncReset 0x10000000 |
| #define Gbl_ResetTrigger_appSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_appSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_sdioSyncReset 0x017B |
| #define B16Gbl_ResetTrigger_sdioSyncReset 0x017A |
| #define LSb32Gbl_ResetTrigger_sdioSyncReset 29 |
| #define LSb16Gbl_ResetTrigger_sdioSyncReset 13 |
| #define bGbl_ResetTrigger_sdioSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_sdioSyncReset 0x20000000 |
| #define Gbl_ResetTrigger_sdioSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_sdioSyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_sdio1SyncReset 0x017B |
| #define B16Gbl_ResetTrigger_sdio1SyncReset 0x017A |
| #define LSb32Gbl_ResetTrigger_sdio1SyncReset 30 |
| #define LSb16Gbl_ResetTrigger_sdio1SyncReset 14 |
| #define bGbl_ResetTrigger_sdio1SyncReset 1 |
| #define MSK32Gbl_ResetTrigger_sdio1SyncReset 0x40000000 |
| #define Gbl_ResetTrigger_sdio1SyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_sdio1SyncReset_deassert 0x0 |
| #define BA_Gbl_ResetTrigger_hdmirxSyncReset 0x017B |
| #define B16Gbl_ResetTrigger_hdmirxSyncReset 0x017A |
| #define LSb32Gbl_ResetTrigger_hdmirxSyncReset 31 |
| #define LSb16Gbl_ResetTrigger_hdmirxSyncReset 15 |
| #define bGbl_ResetTrigger_hdmirxSyncReset 1 |
| #define MSK32Gbl_ResetTrigger_hdmirxSyncReset 0x80000000 |
| #define Gbl_ResetTrigger_hdmirxSyncReset_assert 0x1 |
| #define Gbl_ResetTrigger_hdmirxSyncReset_deassert 0x0 |
| #define RA_Gbl_ResetStatus 0x017C |
| #define BA_Gbl_ResetStatus_ChipResetStatus 0x017C |
| #define B16Gbl_ResetStatus_ChipResetStatus 0x017C |
| #define LSb32Gbl_ResetStatus_ChipResetStatus 0 |
| #define LSb16Gbl_ResetStatus_ChipResetStatus 0 |
| #define bGbl_ResetStatus_ChipResetStatus 1 |
| #define MSK32Gbl_ResetStatus_ChipResetStatus 0x00000001 |
| #define Gbl_ResetStatus_ChipResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_ChipResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_wd0Status 0x017C |
| #define B16Gbl_ResetStatus_wd0Status 0x017C |
| #define LSb32Gbl_ResetStatus_wd0Status 1 |
| #define LSb16Gbl_ResetStatus_wd0Status 1 |
| #define bGbl_ResetStatus_wd0Status 1 |
| #define MSK32Gbl_ResetStatus_wd0Status 0x00000002 |
| #define Gbl_ResetStatus_wd0Status_asserted 0x1 |
| #define Gbl_ResetStatus_wd0Status_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_wd1Status 0x017C |
| #define B16Gbl_ResetStatus_wd1Status 0x017C |
| #define LSb32Gbl_ResetStatus_wd1Status 2 |
| #define LSb16Gbl_ResetStatus_wd1Status 2 |
| #define bGbl_ResetStatus_wd1Status 1 |
| #define MSK32Gbl_ResetStatus_wd1Status 0x00000004 |
| #define Gbl_ResetStatus_wd1Status_asserted 0x1 |
| #define Gbl_ResetStatus_wd1Status_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_wd2Status 0x017C |
| #define B16Gbl_ResetStatus_wd2Status 0x017C |
| #define LSb32Gbl_ResetStatus_wd2Status 3 |
| #define LSb16Gbl_ResetStatus_wd2Status 3 |
| #define bGbl_ResetStatus_wd2Status 1 |
| #define MSK32Gbl_ResetStatus_wd2Status 0x00000008 |
| #define Gbl_ResetStatus_wd2Status_asserted 0x1 |
| #define Gbl_ResetStatus_wd2Status_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_audio0ClkResetStatus 0x017C |
| #define B16Gbl_ResetStatus_audio0ClkResetStatus 0x017C |
| #define LSb32Gbl_ResetStatus_audio0ClkResetStatus 4 |
| #define LSb16Gbl_ResetStatus_audio0ClkResetStatus 4 |
| #define bGbl_ResetStatus_audio0ClkResetStatus 1 |
| #define MSK32Gbl_ResetStatus_audio0ClkResetStatus 0x00000010 |
| #define Gbl_ResetStatus_audio0ClkResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_audio0ClkResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_audio1ClkResetStatus 0x017C |
| #define B16Gbl_ResetStatus_audio1ClkResetStatus 0x017C |
| #define LSb32Gbl_ResetStatus_audio1ClkResetStatus 5 |
| #define LSb16Gbl_ResetStatus_audio1ClkResetStatus 5 |
| #define bGbl_ResetStatus_audio1ClkResetStatus 1 |
| #define MSK32Gbl_ResetStatus_audio1ClkResetStatus 0x00000020 |
| #define Gbl_ResetStatus_audio1ClkResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_audio1ClkResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_audio2ClkResetStatus 0x017C |
| #define B16Gbl_ResetStatus_audio2ClkResetStatus 0x017C |
| #define LSb32Gbl_ResetStatus_audio2ClkResetStatus 6 |
| #define LSb16Gbl_ResetStatus_audio2ClkResetStatus 6 |
| #define bGbl_ResetStatus_audio2ClkResetStatus 1 |
| #define MSK32Gbl_ResetStatus_audio2ClkResetStatus 0x00000040 |
| #define Gbl_ResetStatus_audio2ClkResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_audio2ClkResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_audio3ClkResetStatus 0x017C |
| #define B16Gbl_ResetStatus_audio3ClkResetStatus 0x017C |
| #define LSb32Gbl_ResetStatus_audio3ClkResetStatus 7 |
| #define LSb16Gbl_ResetStatus_audio3ClkResetStatus 7 |
| #define bGbl_ResetStatus_audio3ClkResetStatus 1 |
| #define MSK32Gbl_ResetStatus_audio3ClkResetStatus 0x00000080 |
| #define Gbl_ResetStatus_audio3ClkResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_audio3ClkResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_audioHdClkResetStatus 0x017D |
| #define B16Gbl_ResetStatus_audioHdClkResetStatus 0x017C |
| #define LSb32Gbl_ResetStatus_audioHdClkResetStatus 8 |
| #define LSb16Gbl_ResetStatus_audioHdClkResetStatus 8 |
| #define bGbl_ResetStatus_audioHdClkResetStatus 1 |
| #define MSK32Gbl_ResetStatus_audioHdClkResetStatus 0x00000100 |
| #define Gbl_ResetStatus_audioHdClkResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_audioHdClkResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_sysPllSyncResetStatus 0x017D |
| #define B16Gbl_ResetStatus_sysPllSyncResetStatus 0x017C |
| #define LSb32Gbl_ResetStatus_sysPllSyncResetStatus 9 |
| #define LSb16Gbl_ResetStatus_sysPllSyncResetStatus 9 |
| #define bGbl_ResetStatus_sysPllSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_sysPllSyncResetStatus 0x00000200 |
| #define Gbl_ResetStatus_sysPllSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_sysPllSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_memPllSyncResetStatus 0x017D |
| #define B16Gbl_ResetStatus_memPllSyncResetStatus 0x017C |
| #define LSb32Gbl_ResetStatus_memPllSyncResetStatus 10 |
| #define LSb16Gbl_ResetStatus_memPllSyncResetStatus 10 |
| #define bGbl_ResetStatus_memPllSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_memPllSyncResetStatus 0x00000400 |
| #define Gbl_ResetStatus_memPllSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_memPllSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_cpu1PllSyncResetStatus 0x017D |
| #define B16Gbl_ResetStatus_cpu1PllSyncResetStatus 0x017C |
| #define LSb32Gbl_ResetStatus_cpu1PllSyncResetStatus 11 |
| #define LSb16Gbl_ResetStatus_cpu1PllSyncResetStatus 11 |
| #define bGbl_ResetStatus_cpu1PllSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_cpu1PllSyncResetStatus 0x00000800 |
| #define Gbl_ResetStatus_cpu1PllSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_cpu1PllSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_avPllASyncResetStatus 0x017D |
| #define B16Gbl_ResetStatus_avPllASyncResetStatus 0x017C |
| #define LSb32Gbl_ResetStatus_avPllASyncResetStatus 12 |
| #define LSb16Gbl_ResetStatus_avPllASyncResetStatus 12 |
| #define bGbl_ResetStatus_avPllASyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_avPllASyncResetStatus 0x00001000 |
| #define Gbl_ResetStatus_avPllASyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_avPllASyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_avPllBSyncResetStatus 0x017D |
| #define B16Gbl_ResetStatus_avPllBSyncResetStatus 0x017C |
| #define LSb32Gbl_ResetStatus_avPllBSyncResetStatus 13 |
| #define LSb16Gbl_ResetStatus_avPllBSyncResetStatus 13 |
| #define bGbl_ResetStatus_avPllBSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_avPllBSyncResetStatus 0x00002000 |
| #define Gbl_ResetStatus_avPllBSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_avPllBSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_cpu0SyncResetStatus 0x017D |
| #define B16Gbl_ResetStatus_cpu0SyncResetStatus 0x017C |
| #define LSb32Gbl_ResetStatus_cpu0SyncResetStatus 14 |
| #define LSb16Gbl_ResetStatus_cpu0SyncResetStatus 14 |
| #define bGbl_ResetStatus_cpu0SyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_cpu0SyncResetStatus 0x00004000 |
| #define Gbl_ResetStatus_cpu0SyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_cpu0SyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_cpu1SyncResetStatus 0x017D |
| #define B16Gbl_ResetStatus_cpu1SyncResetStatus 0x017C |
| #define LSb32Gbl_ResetStatus_cpu1SyncResetStatus 15 |
| #define LSb16Gbl_ResetStatus_cpu1SyncResetStatus 15 |
| #define bGbl_ResetStatus_cpu1SyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_cpu1SyncResetStatus 0x00008000 |
| #define Gbl_ResetStatus_cpu1SyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_cpu1SyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_socDdrSyncResetStatus 0x017E |
| #define B16Gbl_ResetStatus_socDdrSyncResetStatus 0x017E |
| #define LSb32Gbl_ResetStatus_socDdrSyncResetStatus 16 |
| #define LSb16Gbl_ResetStatus_socDdrSyncResetStatus 0 |
| #define bGbl_ResetStatus_socDdrSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_socDdrSyncResetStatus 0x00010000 |
| #define Gbl_ResetStatus_socDdrSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_socDdrSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_gfxSyncResetStatus 0x017E |
| #define B16Gbl_ResetStatus_gfxSyncResetStatus 0x017E |
| #define LSb32Gbl_ResetStatus_gfxSyncResetStatus 17 |
| #define LSb16Gbl_ResetStatus_gfxSyncResetStatus 1 |
| #define bGbl_ResetStatus_gfxSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_gfxSyncResetStatus 0x00020000 |
| #define Gbl_ResetStatus_gfxSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_gfxSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_zspSyncResetStatus 0x017E |
| #define B16Gbl_ResetStatus_zspSyncResetStatus 0x017E |
| #define LSb32Gbl_ResetStatus_zspSyncResetStatus 18 |
| #define LSb16Gbl_ResetStatus_zspSyncResetStatus 2 |
| #define bGbl_ResetStatus_zspSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_zspSyncResetStatus 0x00040000 |
| #define Gbl_ResetStatus_zspSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_zspSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_avioSyncResetStatus 0x017E |
| #define B16Gbl_ResetStatus_avioSyncResetStatus 0x017E |
| #define LSb32Gbl_ResetStatus_avioSyncResetStatus 19 |
| #define LSb16Gbl_ResetStatus_avioSyncResetStatus 3 |
| #define bGbl_ResetStatus_avioSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_avioSyncResetStatus 0x00080000 |
| #define Gbl_ResetStatus_avioSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_avioSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_perifSyncResetStatus 0x017E |
| #define B16Gbl_ResetStatus_perifSyncResetStatus 0x017E |
| #define LSb32Gbl_ResetStatus_perifSyncResetStatus 20 |
| #define LSb16Gbl_ResetStatus_perifSyncResetStatus 4 |
| #define bGbl_ResetStatus_perifSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_perifSyncResetStatus 0x00100000 |
| #define Gbl_ResetStatus_perifSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_perifSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_gethSyncResetStatus 0x017E |
| #define B16Gbl_ResetStatus_gethSyncResetStatus 0x017E |
| #define LSb32Gbl_ResetStatus_gethSyncResetStatus 21 |
| #define LSb16Gbl_ResetStatus_gethSyncResetStatus 5 |
| #define bGbl_ResetStatus_gethSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_gethSyncResetStatus 0x00200000 |
| #define Gbl_ResetStatus_gethSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_gethSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_geth1SyncResetStatus 0x017E |
| #define B16Gbl_ResetStatus_geth1SyncResetStatus 0x017E |
| #define LSb32Gbl_ResetStatus_geth1SyncResetStatus 22 |
| #define LSb16Gbl_ResetStatus_geth1SyncResetStatus 6 |
| #define bGbl_ResetStatus_geth1SyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_geth1SyncResetStatus 0x00400000 |
| #define Gbl_ResetStatus_geth1SyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_geth1SyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_sataSyncResetStatus 0x017E |
| #define B16Gbl_ResetStatus_sataSyncResetStatus 0x017E |
| #define LSb32Gbl_ResetStatus_sataSyncResetStatus 23 |
| #define LSb16Gbl_ResetStatus_sataSyncResetStatus 7 |
| #define bGbl_ResetStatus_sataSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_sataSyncResetStatus 0x00800000 |
| #define Gbl_ResetStatus_sataSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_sataSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_ahbApbSyncResetStatus 0x017F |
| #define B16Gbl_ResetStatus_ahbApbSyncResetStatus 0x017E |
| #define LSb32Gbl_ResetStatus_ahbApbSyncResetStatus 24 |
| #define LSb16Gbl_ResetStatus_ahbApbSyncResetStatus 8 |
| #define bGbl_ResetStatus_ahbApbSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_ahbApbSyncResetStatus 0x01000000 |
| #define Gbl_ResetStatus_ahbApbSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_ahbApbSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_nanfSyncResetStatus 0x017F |
| #define B16Gbl_ResetStatus_nanfSyncResetStatus 0x017E |
| #define LSb32Gbl_ResetStatus_nanfSyncResetStatus 25 |
| #define LSb16Gbl_ResetStatus_nanfSyncResetStatus 9 |
| #define bGbl_ResetStatus_nanfSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_nanfSyncResetStatus 0x02000000 |
| #define Gbl_ResetStatus_nanfSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_nanfSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_smemcSyncResetStatus 0x017F |
| #define B16Gbl_ResetStatus_smemcSyncResetStatus 0x017E |
| #define LSb32Gbl_ResetStatus_smemcSyncResetStatus 26 |
| #define LSb16Gbl_ResetStatus_smemcSyncResetStatus 10 |
| #define bGbl_ResetStatus_smemcSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_smemcSyncResetStatus 0x04000000 |
| #define Gbl_ResetStatus_smemcSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_smemcSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_drmSyncResetStatus 0x017F |
| #define B16Gbl_ResetStatus_drmSyncResetStatus 0x017E |
| #define LSb32Gbl_ResetStatus_drmSyncResetStatus 27 |
| #define LSb16Gbl_ResetStatus_drmSyncResetStatus 11 |
| #define bGbl_ResetStatus_drmSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_drmSyncResetStatus 0x08000000 |
| #define Gbl_ResetStatus_drmSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_drmSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_usb0SyncResetStatus 0x017F |
| #define B16Gbl_ResetStatus_usb0SyncResetStatus 0x017E |
| #define LSb32Gbl_ResetStatus_usb0SyncResetStatus 28 |
| #define LSb16Gbl_ResetStatus_usb0SyncResetStatus 12 |
| #define bGbl_ResetStatus_usb0SyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_usb0SyncResetStatus 0x10000000 |
| #define Gbl_ResetStatus_usb0SyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_usb0SyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_usb1SyncResetStatus 0x017F |
| #define B16Gbl_ResetStatus_usb1SyncResetStatus 0x017E |
| #define LSb32Gbl_ResetStatus_usb1SyncResetStatus 29 |
| #define LSb16Gbl_ResetStatus_usb1SyncResetStatus 13 |
| #define bGbl_ResetStatus_usb1SyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_usb1SyncResetStatus 0x20000000 |
| #define Gbl_ResetStatus_usb1SyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_usb1SyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_pBridgeSyncResetStatus 0x017F |
| #define B16Gbl_ResetStatus_pBridgeSyncResetStatus 0x017E |
| #define LSb32Gbl_ResetStatus_pBridgeSyncResetStatus 30 |
| #define LSb16Gbl_ResetStatus_pBridgeSyncResetStatus 14 |
| #define bGbl_ResetStatus_pBridgeSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_pBridgeSyncResetStatus 0x40000000 |
| #define Gbl_ResetStatus_pBridgeSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_pBridgeSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_vppSyncResetStatus 0x017F |
| #define B16Gbl_ResetStatus_vppSyncResetStatus 0x017E |
| #define LSb32Gbl_ResetStatus_vppSyncResetStatus 31 |
| #define LSb16Gbl_ResetStatus_vppSyncResetStatus 15 |
| #define bGbl_ResetStatus_vppSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_vppSyncResetStatus 0x80000000 |
| #define Gbl_ResetStatus_vppSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_vppSyncResetStatus_deasserted 0x0 |
| #define RA_Gbl_ResetStatus1 0x0180 |
| #define BA_Gbl_ResetStatus_vipSyncResetStatus 0x0180 |
| #define B16Gbl_ResetStatus_vipSyncResetStatus 0x0180 |
| #define LSb32Gbl_ResetStatus_vipSyncResetStatus 0 |
| #define LSb16Gbl_ResetStatus_vipSyncResetStatus 0 |
| #define bGbl_ResetStatus_vipSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_vipSyncResetStatus 0x00000001 |
| #define Gbl_ResetStatus_vipSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_vipSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_appSyncResetStatus 0x0180 |
| #define B16Gbl_ResetStatus_appSyncResetStatus 0x0180 |
| #define LSb32Gbl_ResetStatus_appSyncResetStatus 1 |
| #define LSb16Gbl_ResetStatus_appSyncResetStatus 1 |
| #define bGbl_ResetStatus_appSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_appSyncResetStatus 0x00000002 |
| #define Gbl_ResetStatus_appSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_appSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_sdioSyncResetStatus 0x0180 |
| #define B16Gbl_ResetStatus_sdioSyncResetStatus 0x0180 |
| #define LSb32Gbl_ResetStatus_sdioSyncResetStatus 2 |
| #define LSb16Gbl_ResetStatus_sdioSyncResetStatus 2 |
| #define bGbl_ResetStatus_sdioSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_sdioSyncResetStatus 0x00000004 |
| #define Gbl_ResetStatus_sdioSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_sdioSyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_sdio1SyncResetStatus 0x0180 |
| #define B16Gbl_ResetStatus_sdio1SyncResetStatus 0x0180 |
| #define LSb32Gbl_ResetStatus_sdio1SyncResetStatus 3 |
| #define LSb16Gbl_ResetStatus_sdio1SyncResetStatus 3 |
| #define bGbl_ResetStatus_sdio1SyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_sdio1SyncResetStatus 0x00000008 |
| #define Gbl_ResetStatus_sdio1SyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_sdio1SyncResetStatus_deasserted 0x0 |
| #define BA_Gbl_ResetStatus_hdmirxSyncResetStatus 0x0180 |
| #define B16Gbl_ResetStatus_hdmirxSyncResetStatus 0x0180 |
| #define LSb32Gbl_ResetStatus_hdmirxSyncResetStatus 4 |
| #define LSb16Gbl_ResetStatus_hdmirxSyncResetStatus 4 |
| #define bGbl_ResetStatus_hdmirxSyncResetStatus 1 |
| #define MSK32Gbl_ResetStatus_hdmirxSyncResetStatus 0x00000010 |
| #define Gbl_ResetStatus_hdmirxSyncResetStatus_asserted 0x1 |
| #define Gbl_ResetStatus_hdmirxSyncResetStatus_deasserted 0x0 |
| #define RA_Gbl_sw_generic0 0x0184 |
| #define BA_Gbl_sw_generic0_swReg0 0x0184 |
| #define B16Gbl_sw_generic0_swReg0 0x0184 |
| #define LSb32Gbl_sw_generic0_swReg0 0 |
| #define LSb16Gbl_sw_generic0_swReg0 0 |
| #define bGbl_sw_generic0_swReg0 32 |
| #define MSK32Gbl_sw_generic0_swReg0 0xFFFFFFFF |
| #define RA_Gbl_sw_generic1 0x0188 |
| #define BA_Gbl_sw_generic1_swReg1 0x0188 |
| #define B16Gbl_sw_generic1_swReg1 0x0188 |
| #define LSb32Gbl_sw_generic1_swReg1 0 |
| #define LSb16Gbl_sw_generic1_swReg1 0 |
| #define bGbl_sw_generic1_swReg1 32 |
| #define MSK32Gbl_sw_generic1_swReg1 0xFFFFFFFF |
| #define RA_Gbl_sw_generic2 0x018C |
| #define BA_Gbl_sw_generic2_swReg2 0x018C |
| #define B16Gbl_sw_generic2_swReg2 0x018C |
| #define LSb32Gbl_sw_generic2_swReg2 0 |
| #define LSb16Gbl_sw_generic2_swReg2 0 |
| #define bGbl_sw_generic2_swReg2 32 |
| #define MSK32Gbl_sw_generic2_swReg2 0xFFFFFFFF |
| #define RA_Gbl_sw_generic3 0x0190 |
| #define BA_Gbl_sw_generic3_swReg3 0x0190 |
| #define B16Gbl_sw_generic3_swReg3 0x0190 |
| #define LSb32Gbl_sw_generic3_swReg3 0 |
| #define LSb16Gbl_sw_generic3_swReg3 0 |
| #define bGbl_sw_generic3_swReg3 32 |
| #define MSK32Gbl_sw_generic3_swReg3 0xFFFFFFFF |
| #define RA_Gbl_ChipCntl0 0x0194 |
| #define BA_Gbl_ChipCntl0_dCacheCfgCPU0 0x0194 |
| #define B16Gbl_ChipCntl0_dCacheCfgCPU0 0x0194 |
| #define LSb32Gbl_ChipCntl0_dCacheCfgCPU0 0 |
| #define LSb16Gbl_ChipCntl0_dCacheCfgCPU0 0 |
| #define bGbl_ChipCntl0_dCacheCfgCPU0 2 |
| #define MSK32Gbl_ChipCntl0_dCacheCfgCPU0 0x00000003 |
| #define BA_Gbl_ChipCntl0_iCacheCfgCPU0 0x0194 |
| #define B16Gbl_ChipCntl0_iCacheCfgCPU0 0x0194 |
| #define LSb32Gbl_ChipCntl0_iCacheCfgCPU0 2 |
| #define LSb16Gbl_ChipCntl0_iCacheCfgCPU0 2 |
| #define bGbl_ChipCntl0_iCacheCfgCPU0 2 |
| #define MSK32Gbl_ChipCntl0_iCacheCfgCPU0 0x0000000C |
| #define BA_Gbl_ChipCntl0_dCacheCfgCPU1 0x0194 |
| #define B16Gbl_ChipCntl0_dCacheCfgCPU1 0x0194 |
| #define LSb32Gbl_ChipCntl0_dCacheCfgCPU1 4 |
| #define LSb16Gbl_ChipCntl0_dCacheCfgCPU1 4 |
| #define bGbl_ChipCntl0_dCacheCfgCPU1 2 |
| #define MSK32Gbl_ChipCntl0_dCacheCfgCPU1 0x00000030 |
| #define BA_Gbl_ChipCntl0_iCacheCfgCPU1 0x0194 |
| #define B16Gbl_ChipCntl0_iCacheCfgCPU1 0x0194 |
| #define LSb32Gbl_ChipCntl0_iCacheCfgCPU1 6 |
| #define LSb16Gbl_ChipCntl0_iCacheCfgCPU1 6 |
| #define bGbl_ChipCntl0_iCacheCfgCPU1 2 |
| #define MSK32Gbl_ChipCntl0_iCacheCfgCPU1 0x000000C0 |
| #define BA_Gbl_ChipCntl0_cg_bpass0Cpu0 0x0195 |
| #define B16Gbl_ChipCntl0_cg_bpass0Cpu0 0x0194 |
| #define LSb32Gbl_ChipCntl0_cg_bpass0Cpu0 8 |
| #define LSb16Gbl_ChipCntl0_cg_bpass0Cpu0 8 |
| #define bGbl_ChipCntl0_cg_bpass0Cpu0 1 |
| #define MSK32Gbl_ChipCntl0_cg_bpass0Cpu0 0x00000100 |
| #define BA_Gbl_ChipCntl0_cg_bpass0Cpu1 0x0195 |
| #define B16Gbl_ChipCntl0_cg_bpass0Cpu1 0x0194 |
| #define LSb32Gbl_ChipCntl0_cg_bpass0Cpu1 9 |
| #define LSb16Gbl_ChipCntl0_cg_bpass0Cpu1 9 |
| #define bGbl_ChipCntl0_cg_bpass0Cpu1 1 |
| #define MSK32Gbl_ChipCntl0_cg_bpass0Cpu1 0x00000200 |
| #define BA_Gbl_ChipCntl0_wfiJtagClkEn 0x0195 |
| #define B16Gbl_ChipCntl0_wfiJtagClkEn 0x0194 |
| #define LSb32Gbl_ChipCntl0_wfiJtagClkEn 10 |
| #define LSb16Gbl_ChipCntl0_wfiJtagClkEn 10 |
| #define bGbl_ChipCntl0_wfiJtagClkEn 1 |
| #define MSK32Gbl_ChipCntl0_wfiJtagClkEn 0x00000400 |
| #define Gbl_ChipCntl0_wfiJtagClkEn_RUNNING 0x1 |
| #define Gbl_ChipCntl0_wfiJtagClkEn_FREEZE 0x0 |
| #define RA_Gbl_ChipCntl1 0x0198 |
| #define BA_Gbl_ChipCntl1_bpm_wtc 0x0198 |
| #define B16Gbl_ChipCntl1_bpm_wtc 0x0198 |
| #define LSb32Gbl_ChipCntl1_bpm_wtc 0 |
| #define LSb16Gbl_ChipCntl1_bpm_wtc 0 |
| #define bGbl_ChipCntl1_bpm_wtc 2 |
| #define MSK32Gbl_ChipCntl1_bpm_wtc 0x00000003 |
| #define BA_Gbl_ChipCntl1_bpm_rtc 0x0198 |
| #define B16Gbl_ChipCntl1_bpm_rtc 0x0198 |
| #define LSb32Gbl_ChipCntl1_bpm_rtc 2 |
| #define LSb16Gbl_ChipCntl1_bpm_rtc 2 |
| #define bGbl_ChipCntl1_bpm_rtc 2 |
| #define MSK32Gbl_ChipCntl1_bpm_rtc 0x0000000C |
| #define BA_Gbl_ChipCntl1_icl0data_wtc 0x0198 |
| #define B16Gbl_ChipCntl1_icl0data_wtc 0x0198 |
| #define LSb32Gbl_ChipCntl1_icl0data_wtc 4 |
| #define LSb16Gbl_ChipCntl1_icl0data_wtc 4 |
| #define bGbl_ChipCntl1_icl0data_wtc 2 |
| #define MSK32Gbl_ChipCntl1_icl0data_wtc 0x00000030 |
| #define BA_Gbl_ChipCntl1_icl0data_rtc 0x0198 |
| #define B16Gbl_ChipCntl1_icl0data_rtc 0x0198 |
| #define LSb32Gbl_ChipCntl1_icl0data_rtc 6 |
| #define LSb16Gbl_ChipCntl1_icl0data_rtc 6 |
| #define bGbl_ChipCntl1_icl0data_rtc 2 |
| #define MSK32Gbl_ChipCntl1_icl0data_rtc 0x000000C0 |
| #define BA_Gbl_ChipCntl1_icl0tag_wtc 0x0199 |
| #define B16Gbl_ChipCntl1_icl0tag_wtc 0x0198 |
| #define LSb32Gbl_ChipCntl1_icl0tag_wtc 8 |
| #define LSb16Gbl_ChipCntl1_icl0tag_wtc 8 |
| #define bGbl_ChipCntl1_icl0tag_wtc 2 |
| #define MSK32Gbl_ChipCntl1_icl0tag_wtc 0x00000300 |
| #define BA_Gbl_ChipCntl1_icl0tag_rtc 0x0199 |
| #define B16Gbl_ChipCntl1_icl0tag_rtc 0x0198 |
| #define LSb32Gbl_ChipCntl1_icl0tag_rtc 10 |
| #define LSb16Gbl_ChipCntl1_icl0tag_rtc 10 |
| #define bGbl_ChipCntl1_icl0tag_rtc 2 |
| #define MSK32Gbl_ChipCntl1_icl0tag_rtc 0x00000C00 |
| #define BA_Gbl_ChipCntl1_icl1data_wtc 0x0199 |
| #define B16Gbl_ChipCntl1_icl1data_wtc 0x0198 |
| #define LSb32Gbl_ChipCntl1_icl1data_wtc 12 |
| #define LSb16Gbl_ChipCntl1_icl1data_wtc 12 |
| #define bGbl_ChipCntl1_icl1data_wtc 2 |
| #define MSK32Gbl_ChipCntl1_icl1data_wtc 0x00003000 |
| #define BA_Gbl_ChipCntl1_icl1data_rtc 0x0199 |
| #define B16Gbl_ChipCntl1_icl1data_rtc 0x0198 |
| #define LSb32Gbl_ChipCntl1_icl1data_rtc 14 |
| #define LSb16Gbl_ChipCntl1_icl1data_rtc 14 |
| #define bGbl_ChipCntl1_icl1data_rtc 2 |
| #define MSK32Gbl_ChipCntl1_icl1data_rtc 0x0000C000 |
| #define BA_Gbl_ChipCntl1_icl1tag_wtc 0x019A |
| #define B16Gbl_ChipCntl1_icl1tag_wtc 0x019A |
| #define LSb32Gbl_ChipCntl1_icl1tag_wtc 16 |
| #define LSb16Gbl_ChipCntl1_icl1tag_wtc 0 |
| #define bGbl_ChipCntl1_icl1tag_wtc 2 |
| #define MSK32Gbl_ChipCntl1_icl1tag_wtc 0x00030000 |
| #define BA_Gbl_ChipCntl1_icl1tag_rtc 0x019A |
| #define B16Gbl_ChipCntl1_icl1tag_rtc 0x019A |
| #define LSb32Gbl_ChipCntl1_icl1tag_rtc 18 |
| #define LSb16Gbl_ChipCntl1_icl1tag_rtc 2 |
| #define bGbl_ChipCntl1_icl1tag_rtc 2 |
| #define MSK32Gbl_ChipCntl1_icl1tag_rtc 0x000C0000 |
| #define BA_Gbl_ChipCntl1_dcl1data_wtc 0x019A |
| #define B16Gbl_ChipCntl1_dcl1data_wtc 0x019A |
| #define LSb32Gbl_ChipCntl1_dcl1data_wtc 20 |
| #define LSb16Gbl_ChipCntl1_dcl1data_wtc 4 |
| #define bGbl_ChipCntl1_dcl1data_wtc 2 |
| #define MSK32Gbl_ChipCntl1_dcl1data_wtc 0x00300000 |
| #define BA_Gbl_ChipCntl1_dcl1data_rtc 0x019A |
| #define B16Gbl_ChipCntl1_dcl1data_rtc 0x019A |
| #define LSb32Gbl_ChipCntl1_dcl1data_rtc 22 |
| #define LSb16Gbl_ChipCntl1_dcl1data_rtc 6 |
| #define bGbl_ChipCntl1_dcl1data_rtc 2 |
| #define MSK32Gbl_ChipCntl1_dcl1data_rtc 0x00C00000 |
| #define BA_Gbl_ChipCntl1_dcl1tag_wtc 0x019B |
| #define B16Gbl_ChipCntl1_dcl1tag_wtc 0x019A |
| #define LSb32Gbl_ChipCntl1_dcl1tag_wtc 24 |
| #define LSb16Gbl_ChipCntl1_dcl1tag_wtc 8 |
| #define bGbl_ChipCntl1_dcl1tag_wtc 2 |
| #define MSK32Gbl_ChipCntl1_dcl1tag_wtc 0x03000000 |
| #define BA_Gbl_ChipCntl1_dcl1tag_rtc 0x019B |
| #define B16Gbl_ChipCntl1_dcl1tag_rtc 0x019A |
| #define LSb32Gbl_ChipCntl1_dcl1tag_rtc 26 |
| #define LSb16Gbl_ChipCntl1_dcl1tag_rtc 10 |
| #define bGbl_ChipCntl1_dcl1tag_rtc 2 |
| #define MSK32Gbl_ChipCntl1_dcl1tag_rtc 0x0C000000 |
| #define BA_Gbl_ChipCntl1_dcl1state_wtc 0x019B |
| #define B16Gbl_ChipCntl1_dcl1state_wtc 0x019A |
| #define LSb32Gbl_ChipCntl1_dcl1state_wtc 28 |
| #define LSb16Gbl_ChipCntl1_dcl1state_wtc 12 |
| #define bGbl_ChipCntl1_dcl1state_wtc 2 |
| #define MSK32Gbl_ChipCntl1_dcl1state_wtc 0x30000000 |
| #define BA_Gbl_ChipCntl1_dcl1state_rtc 0x019B |
| #define B16Gbl_ChipCntl1_dcl1state_rtc 0x019A |
| #define LSb32Gbl_ChipCntl1_dcl1state_rtc 30 |
| #define LSb16Gbl_ChipCntl1_dcl1state_rtc 14 |
| #define bGbl_ChipCntl1_dcl1state_rtc 2 |
| #define MSK32Gbl_ChipCntl1_dcl1state_rtc 0xC0000000 |
| #define RA_Gbl_ChipCntl11 0x019C |
| #define BA_Gbl_ChipCntl1_dcl1attr_wtc 0x019C |
| #define B16Gbl_ChipCntl1_dcl1attr_wtc 0x019C |
| #define LSb32Gbl_ChipCntl1_dcl1attr_wtc 0 |
| #define LSb16Gbl_ChipCntl1_dcl1attr_wtc 0 |
| #define bGbl_ChipCntl1_dcl1attr_wtc 2 |
| #define MSK32Gbl_ChipCntl1_dcl1attr_wtc 0x00000003 |
| #define BA_Gbl_ChipCntl1_dcl1attr_rtc 0x019C |
| #define B16Gbl_ChipCntl1_dcl1attr_rtc 0x019C |
| #define LSb32Gbl_ChipCntl1_dcl1attr_rtc 2 |
| #define LSb16Gbl_ChipCntl1_dcl1attr_rtc 2 |
| #define bGbl_ChipCntl1_dcl1attr_rtc 2 |
| #define MSK32Gbl_ChipCntl1_dcl1attr_rtc 0x0000000C |
| #define BA_Gbl_ChipCntl1_dcl1fifo_wtc 0x019C |
| #define B16Gbl_ChipCntl1_dcl1fifo_wtc 0x019C |
| #define LSb32Gbl_ChipCntl1_dcl1fifo_wtc 4 |
| #define LSb16Gbl_ChipCntl1_dcl1fifo_wtc 4 |
| #define bGbl_ChipCntl1_dcl1fifo_wtc 2 |
| #define MSK32Gbl_ChipCntl1_dcl1fifo_wtc 0x00000030 |
| #define BA_Gbl_ChipCntl1_dcl1fifo_rtc 0x019C |
| #define B16Gbl_ChipCntl1_dcl1fifo_rtc 0x019C |
| #define LSb32Gbl_ChipCntl1_dcl1fifo_rtc 6 |
| #define LSb16Gbl_ChipCntl1_dcl1fifo_rtc 6 |
| #define bGbl_ChipCntl1_dcl1fifo_rtc 2 |
| #define MSK32Gbl_ChipCntl1_dcl1fifo_rtc 0x000000C0 |
| #define BA_Gbl_ChipCntl1_dcl0data_wtc 0x019D |
| #define B16Gbl_ChipCntl1_dcl0data_wtc 0x019C |
| #define LSb32Gbl_ChipCntl1_dcl0data_wtc 8 |
| #define LSb16Gbl_ChipCntl1_dcl0data_wtc 8 |
| #define bGbl_ChipCntl1_dcl0data_wtc 2 |
| #define MSK32Gbl_ChipCntl1_dcl0data_wtc 0x00000300 |
| #define BA_Gbl_ChipCntl1_dcl0data_rtc 0x019D |
| #define B16Gbl_ChipCntl1_dcl0data_rtc 0x019C |
| #define LSb32Gbl_ChipCntl1_dcl0data_rtc 10 |
| #define LSb16Gbl_ChipCntl1_dcl0data_rtc 10 |
| #define bGbl_ChipCntl1_dcl0data_rtc 2 |
| #define MSK32Gbl_ChipCntl1_dcl0data_rtc 0x00000C00 |
| #define BA_Gbl_ChipCntl1_dcl0tag_wtc 0x019D |
| #define B16Gbl_ChipCntl1_dcl0tag_wtc 0x019C |
| #define LSb32Gbl_ChipCntl1_dcl0tag_wtc 12 |
| #define LSb16Gbl_ChipCntl1_dcl0tag_wtc 12 |
| #define bGbl_ChipCntl1_dcl0tag_wtc 2 |
| #define MSK32Gbl_ChipCntl1_dcl0tag_wtc 0x00003000 |
| #define BA_Gbl_ChipCntl1_dcl0tag_rtc 0x019D |
| #define B16Gbl_ChipCntl1_dcl0tag_rtc 0x019C |
| #define LSb32Gbl_ChipCntl1_dcl0tag_rtc 14 |
| #define LSb16Gbl_ChipCntl1_dcl0tag_rtc 14 |
| #define bGbl_ChipCntl1_dcl0tag_rtc 2 |
| #define MSK32Gbl_ChipCntl1_dcl0tag_rtc 0x0000C000 |
| #define BA_Gbl_ChipCntl1_l2c_dataram_wtc 0x019E |
| #define B16Gbl_ChipCntl1_l2c_dataram_wtc 0x019E |
| #define LSb32Gbl_ChipCntl1_l2c_dataram_wtc 16 |
| #define LSb16Gbl_ChipCntl1_l2c_dataram_wtc 0 |
| #define bGbl_ChipCntl1_l2c_dataram_wtc 2 |
| #define MSK32Gbl_ChipCntl1_l2c_dataram_wtc 0x00030000 |
| #define BA_Gbl_ChipCntl1_l2c_dataram_rtc 0x019E |
| #define B16Gbl_ChipCntl1_l2c_dataram_rtc 0x019E |
| #define LSb32Gbl_ChipCntl1_l2c_dataram_rtc 18 |
| #define LSb16Gbl_ChipCntl1_l2c_dataram_rtc 2 |
| #define bGbl_ChipCntl1_l2c_dataram_rtc 3 |
| #define MSK32Gbl_ChipCntl1_l2c_dataram_rtc 0x001C0000 |
| #define BA_Gbl_ChipCntl1_l2c_dirtyram_wtc 0x019E |
| #define B16Gbl_ChipCntl1_l2c_dirtyram_wtc 0x019E |
| #define LSb32Gbl_ChipCntl1_l2c_dirtyram_wtc 21 |
| #define LSb16Gbl_ChipCntl1_l2c_dirtyram_wtc 5 |
| #define bGbl_ChipCntl1_l2c_dirtyram_wtc 3 |
| #define MSK32Gbl_ChipCntl1_l2c_dirtyram_wtc 0x00E00000 |
| #define BA_Gbl_ChipCntl1_l2c_dirtyram_rtc 0x019F |
| #define B16Gbl_ChipCntl1_l2c_dirtyram_rtc 0x019E |
| #define LSb32Gbl_ChipCntl1_l2c_dirtyram_rtc 24 |
| #define LSb16Gbl_ChipCntl1_l2c_dirtyram_rtc 8 |
| #define bGbl_ChipCntl1_l2c_dirtyram_rtc 2 |
| #define MSK32Gbl_ChipCntl1_l2c_dirtyram_rtc 0x03000000 |
| #define BA_Gbl_ChipCntl1_l2c_lockram_wtc 0x019F |
| #define B16Gbl_ChipCntl1_l2c_lockram_wtc 0x019E |
| #define LSb32Gbl_ChipCntl1_l2c_lockram_wtc 26 |
| #define LSb16Gbl_ChipCntl1_l2c_lockram_wtc 10 |
| #define bGbl_ChipCntl1_l2c_lockram_wtc 3 |
| #define MSK32Gbl_ChipCntl1_l2c_lockram_wtc 0x1C000000 |
| #define BA_Gbl_ChipCntl1_l2c_lockram_rtc 0x019F |
| #define B16Gbl_ChipCntl1_l2c_lockram_rtc 0x019E |
| #define LSb32Gbl_ChipCntl1_l2c_lockram_rtc 29 |
| #define LSb16Gbl_ChipCntl1_l2c_lockram_rtc 13 |
| #define bGbl_ChipCntl1_l2c_lockram_rtc 2 |
| #define MSK32Gbl_ChipCntl1_l2c_lockram_rtc 0x60000000 |
| #define RA_Gbl_ChipCntl12 0x01A0 |
| #define BA_Gbl_ChipCntl1_l2c_eccram_wtc 0x01A0 |
| #define B16Gbl_ChipCntl1_l2c_eccram_wtc 0x01A0 |
| #define LSb32Gbl_ChipCntl1_l2c_eccram_wtc 0 |
| #define LSb16Gbl_ChipCntl1_l2c_eccram_wtc 0 |
| #define bGbl_ChipCntl1_l2c_eccram_wtc 2 |
| #define MSK32Gbl_ChipCntl1_l2c_eccram_wtc 0x00000003 |
| #define BA_Gbl_ChipCntl1_l2c_eccram_rtc 0x01A0 |
| #define B16Gbl_ChipCntl1_l2c_eccram_rtc 0x01A0 |
| #define LSb32Gbl_ChipCntl1_l2c_eccram_rtc 2 |
| #define LSb16Gbl_ChipCntl1_l2c_eccram_rtc 2 |
| #define bGbl_ChipCntl1_l2c_eccram_rtc 3 |
| #define MSK32Gbl_ChipCntl1_l2c_eccram_rtc 0x0000001C |
| #define BA_Gbl_ChipCntl1_l2c_tagram_wtc 0x01A0 |
| #define B16Gbl_ChipCntl1_l2c_tagram_wtc 0x01A0 |
| #define LSb32Gbl_ChipCntl1_l2c_tagram_wtc 5 |
| #define LSb16Gbl_ChipCntl1_l2c_tagram_wtc 5 |
| #define bGbl_ChipCntl1_l2c_tagram_wtc 3 |
| #define MSK32Gbl_ChipCntl1_l2c_tagram_wtc 0x000000E0 |
| #define BA_Gbl_ChipCntl1_l2c_tagram_rtc 0x01A1 |
| #define B16Gbl_ChipCntl1_l2c_tagram_rtc 0x01A0 |
| #define LSb32Gbl_ChipCntl1_l2c_tagram_rtc 8 |
| #define LSb16Gbl_ChipCntl1_l2c_tagram_rtc 8 |
| #define bGbl_ChipCntl1_l2c_tagram_rtc 3 |
| #define MSK32Gbl_ChipCntl1_l2c_tagram_rtc 0x00000700 |
| #define BA_Gbl_ChipCntl1_l2c_tzram_wtc 0x01A1 |
| #define B16Gbl_ChipCntl1_l2c_tzram_wtc 0x01A0 |
| #define LSb32Gbl_ChipCntl1_l2c_tzram_wtc 11 |
| #define LSb16Gbl_ChipCntl1_l2c_tzram_wtc 11 |
| #define bGbl_ChipCntl1_l2c_tzram_wtc 3 |
| #define MSK32Gbl_ChipCntl1_l2c_tzram_wtc 0x00003800 |
| #define BA_Gbl_ChipCntl1_l2c_tzram_rtc 0x01A1 |
| #define B16Gbl_ChipCntl1_l2c_tzram_rtc 0x01A0 |
| #define LSb32Gbl_ChipCntl1_l2c_tzram_rtc 14 |
| #define LSb16Gbl_ChipCntl1_l2c_tzram_rtc 14 |
| #define bGbl_ChipCntl1_l2c_tzram_rtc 2 |
| #define MSK32Gbl_ChipCntl1_l2c_tzram_rtc 0x0000C000 |
| #define BA_Gbl_ChipCntl1_l2c_validram_wtc 0x01A2 |
| #define B16Gbl_ChipCntl1_l2c_validram_wtc 0x01A2 |
| #define LSb32Gbl_ChipCntl1_l2c_validram_wtc 16 |
| #define LSb16Gbl_ChipCntl1_l2c_validram_wtc 0 |
| #define bGbl_ChipCntl1_l2c_validram_wtc 3 |
| #define MSK32Gbl_ChipCntl1_l2c_validram_wtc 0x00070000 |
| #define BA_Gbl_ChipCntl1_l2c_validram_rtc 0x01A2 |
| #define B16Gbl_ChipCntl1_l2c_validram_rtc 0x01A2 |
| #define LSb32Gbl_ChipCntl1_l2c_validram_rtc 19 |
| #define LSb16Gbl_ChipCntl1_l2c_validram_rtc 3 |
| #define bGbl_ChipCntl1_l2c_validram_rtc 2 |
| #define MSK32Gbl_ChipCntl1_l2c_validram_rtc 0x00180000 |
| #define BA_Gbl_ChipCntl1_mmu_wtc 0x01A2 |
| #define B16Gbl_ChipCntl1_mmu_wtc 0x01A2 |
| #define LSb32Gbl_ChipCntl1_mmu_wtc 21 |
| #define LSb16Gbl_ChipCntl1_mmu_wtc 5 |
| #define bGbl_ChipCntl1_mmu_wtc 2 |
| #define MSK32Gbl_ChipCntl1_mmu_wtc 0x00600000 |
| #define BA_Gbl_ChipCntl1_mmu_rtc 0x01A2 |
| #define B16Gbl_ChipCntl1_mmu_rtc 0x01A2 |
| #define LSb32Gbl_ChipCntl1_mmu_rtc 23 |
| #define LSb16Gbl_ChipCntl1_mmu_rtc 7 |
| #define bGbl_ChipCntl1_mmu_rtc 2 |
| #define MSK32Gbl_ChipCntl1_mmu_rtc 0x01800000 |
| #define BA_Gbl_ChipCntl1_sf_wtc 0x01A3 |
| #define B16Gbl_ChipCntl1_sf_wtc 0x01A2 |
| #define LSb32Gbl_ChipCntl1_sf_wtc 25 |
| #define LSb16Gbl_ChipCntl1_sf_wtc 9 |
| #define bGbl_ChipCntl1_sf_wtc 2 |
| #define MSK32Gbl_ChipCntl1_sf_wtc 0x06000000 |
| #define BA_Gbl_ChipCntl1_sf_rtc 0x01A3 |
| #define B16Gbl_ChipCntl1_sf_rtc 0x01A2 |
| #define LSb32Gbl_ChipCntl1_sf_rtc 27 |
| #define LSb16Gbl_ChipCntl1_sf_rtc 11 |
| #define bGbl_ChipCntl1_sf_rtc 2 |
| #define MSK32Gbl_ChipCntl1_sf_rtc 0x18000000 |
| #define RA_Gbl_RWTC_avio31to0 0x01A4 |
| #define BA_Gbl_RWTC_avio31to0_value 0x01A4 |
| #define B16Gbl_RWTC_avio31to0_value 0x01A4 |
| #define LSb32Gbl_RWTC_avio31to0_value 0 |
| #define LSb16Gbl_RWTC_avio31to0_value 0 |
| #define bGbl_RWTC_avio31to0_value 32 |
| #define MSK32Gbl_RWTC_avio31to0_value 0xFFFFFFFF |
| #define RA_Gbl_RWTC_avio41to32 0x01A8 |
| #define BA_Gbl_RWTC_avio41to32_value 0x01A8 |
| #define B16Gbl_RWTC_avio41to32_value 0x01A8 |
| #define LSb32Gbl_RWTC_avio41to32_value 0 |
| #define LSb16Gbl_RWTC_avio41to32_value 0 |
| #define bGbl_RWTC_avio41to32_value 10 |
| #define MSK32Gbl_RWTC_avio41to32_value 0x000003FF |
| #define RA_Gbl_RWTC_gfx2D31to0 0x01AC |
| #define BA_Gbl_RWTC_gfx2D31to0_value 0x01AC |
| #define B16Gbl_RWTC_gfx2D31to0_value 0x01AC |
| #define LSb32Gbl_RWTC_gfx2D31to0_value 0 |
| #define LSb16Gbl_RWTC_gfx2D31to0_value 0 |
| #define bGbl_RWTC_gfx2D31to0_value 32 |
| #define MSK32Gbl_RWTC_gfx2D31to0_value 0xFFFFFFFF |
| #define RA_Gbl_RWTC_gfx2D41to32 0x01B0 |
| #define BA_Gbl_RWTC_gfx2D41to32_value 0x01B0 |
| #define B16Gbl_RWTC_gfx2D41to32_value 0x01B0 |
| #define LSb32Gbl_RWTC_gfx2D41to32_value 0 |
| #define LSb16Gbl_RWTC_gfx2D41to32_value 0 |
| #define bGbl_RWTC_gfx2D41to32_value 10 |
| #define MSK32Gbl_RWTC_gfx2D41to32_value 0x000003FF |
| #define RA_Gbl_RWTC_gfx3D31to0 0x01B4 |
| #define BA_Gbl_RWTC_gfx3D31to0_value 0x01B4 |
| #define B16Gbl_RWTC_gfx3D31to0_value 0x01B4 |
| #define LSb32Gbl_RWTC_gfx3D31to0_value 0 |
| #define LSb16Gbl_RWTC_gfx3D31to0_value 0 |
| #define bGbl_RWTC_gfx3D31to0_value 32 |
| #define MSK32Gbl_RWTC_gfx3D31to0_value 0xFFFFFFFF |
| #define RA_Gbl_RWTC_gfx3D41to32 0x01B8 |
| #define BA_Gbl_RWTC_gfx3D41to32_value 0x01B8 |
| #define B16Gbl_RWTC_gfx3D41to32_value 0x01B8 |
| #define LSb32Gbl_RWTC_gfx3D41to32_value 0 |
| #define LSb16Gbl_RWTC_gfx3D41to32_value 0 |
| #define bGbl_RWTC_gfx3D41to32_value 10 |
| #define MSK32Gbl_RWTC_gfx3D41to32_value 0x000003FF |
| #define RA_Gbl_RWTC_soc31to0 0x01BC |
| #define BA_Gbl_RWTC_soc31to0_value 0x01BC |
| #define B16Gbl_RWTC_soc31to0_value 0x01BC |
| #define LSb32Gbl_RWTC_soc31to0_value 0 |
| #define LSb16Gbl_RWTC_soc31to0_value 0 |
| #define bGbl_RWTC_soc31to0_value 32 |
| #define MSK32Gbl_RWTC_soc31to0_value 0xFFFFFFFF |
| #define RA_Gbl_RWTC_soc41to32 0x01C0 |
| #define BA_Gbl_RWTC_soc41to32_value 0x01C0 |
| #define B16Gbl_RWTC_soc41to32_value 0x01C0 |
| #define LSb32Gbl_RWTC_soc41to32_value 0 |
| #define LSb16Gbl_RWTC_soc41to32_value 0 |
| #define bGbl_RWTC_soc41to32_value 10 |
| #define MSK32Gbl_RWTC_soc41to32_value 0x000003FF |
| #define RA_Gbl_RWTC_vPro31to0 0x01C4 |
| #define BA_Gbl_RWTC_vPro31to0_value 0x01C4 |
| #define B16Gbl_RWTC_vPro31to0_value 0x01C4 |
| #define LSb32Gbl_RWTC_vPro31to0_value 0 |
| #define LSb16Gbl_RWTC_vPro31to0_value 0 |
| #define bGbl_RWTC_vPro31to0_value 32 |
| #define MSK32Gbl_RWTC_vPro31to0_value 0xFFFFFFFF |
| #define RA_Gbl_RWTC_vPro41to32 0x01C8 |
| #define BA_Gbl_RWTC_vPro41to32_value 0x01C8 |
| #define B16Gbl_RWTC_vPro41to32_value 0x01C8 |
| #define LSb32Gbl_RWTC_vPro41to32_value 0 |
| #define LSb16Gbl_RWTC_vPro41to32_value 0 |
| #define bGbl_RWTC_vPro41to32_value 10 |
| #define MSK32Gbl_RWTC_vPro41to32_value 0x000003FF |
| #define RA_Gbl_ProductId 0x01CC |
| #define BA_Gbl_ProductId_Id 0x01CC |
| #define B16Gbl_ProductId_Id 0x01CC |
| #define LSb32Gbl_ProductId_Id 0 |
| #define LSb16Gbl_ProductId_Id 0 |
| #define bGbl_ProductId_Id 32 |
| #define MSK32Gbl_ProductId_Id 0xFFFFFFFF |
| #define RA_Gbl_ProductId_ext 0x01D0 |
| #define BA_Gbl_ProductId_ext_ID_EXT 0x01D0 |
| #define B16Gbl_ProductId_ext_ID_EXT 0x01D0 |
| #define LSb32Gbl_ProductId_ext_ID_EXT 0 |
| #define LSb16Gbl_ProductId_ext_ID_EXT 0 |
| #define bGbl_ProductId_ext_ID_EXT 8 |
| #define MSK32Gbl_ProductId_ext_ID_EXT 0x000000FF |
| #define RA_Gbl_FPGAR 0x01D4 |
| #define BA_Gbl_FPGAR_FPGAR 0x01D4 |
| #define B16Gbl_FPGAR_FPGAR 0x01D4 |
| #define LSb32Gbl_FPGAR_FPGAR 0 |
| #define LSb16Gbl_FPGAR_FPGAR 0 |
| #define bGbl_FPGAR_FPGAR 32 |
| #define MSK32Gbl_FPGAR_FPGAR 0xFFFFFFFF |
| #define RA_Gbl_FPGARW 0x01D8 |
| #define BA_Gbl_FPGARW_FPGARW 0x01D8 |
| #define B16Gbl_FPGARW_FPGARW 0x01D8 |
| #define LSb32Gbl_FPGARW_FPGARW 0 |
| #define LSb16Gbl_FPGARW_FPGARW 0 |
| #define bGbl_FPGARW_FPGARW 32 |
| #define MSK32Gbl_FPGARW_FPGARW 0xFFFFFFFF |
| #define RA_Gbl_RingOscCtl 0x01DC |
| #define BA_Gbl_RingOscCtl_centerInit 0x01DC |
| #define B16Gbl_RingOscCtl_centerInit 0x01DC |
| #define LSb32Gbl_RingOscCtl_centerInit 0 |
| #define LSb16Gbl_RingOscCtl_centerInit 0 |
| #define bGbl_RingOscCtl_centerInit 1 |
| #define MSK32Gbl_RingOscCtl_centerInit 0x00000001 |
| #define Gbl_RingOscCtl_centerInit_OFF 0x0 |
| #define Gbl_RingOscCtl_centerInit_ON 0x1 |
| #define BA_Gbl_RingOscCtl_avioTopInit 0x01DC |
| #define B16Gbl_RingOscCtl_avioTopInit 0x01DC |
| #define LSb32Gbl_RingOscCtl_avioTopInit 1 |
| #define LSb16Gbl_RingOscCtl_avioTopInit 1 |
| #define bGbl_RingOscCtl_avioTopInit 1 |
| #define MSK32Gbl_RingOscCtl_avioTopInit 0x00000002 |
| #define Gbl_RingOscCtl_avioTopInit_OFF 0x0 |
| #define Gbl_RingOscCtl_avioTopInit_ON 0x1 |
| #define BA_Gbl_RingOscCtl_avioBotInit 0x01DC |
| #define B16Gbl_RingOscCtl_avioBotInit 0x01DC |
| #define LSb32Gbl_RingOscCtl_avioBotInit 2 |
| #define LSb16Gbl_RingOscCtl_avioBotInit 2 |
| #define bGbl_RingOscCtl_avioBotInit 1 |
| #define MSK32Gbl_RingOscCtl_avioBotInit 0x00000004 |
| #define Gbl_RingOscCtl_avioBotInit_OFF 0x0 |
| #define Gbl_RingOscCtl_avioBotInit_ON 0x1 |
| #define BA_Gbl_RingOscCtl_usbTopInit 0x01DC |
| #define B16Gbl_RingOscCtl_usbTopInit 0x01DC |
| #define LSb32Gbl_RingOscCtl_usbTopInit 3 |
| #define LSb16Gbl_RingOscCtl_usbTopInit 3 |
| #define bGbl_RingOscCtl_usbTopInit 1 |
| #define MSK32Gbl_RingOscCtl_usbTopInit 0x00000008 |
| #define Gbl_RingOscCtl_usbTopInit_OFF 0x0 |
| #define Gbl_RingOscCtl_usbTopInit_ON 0x1 |
| #define BA_Gbl_RingOscCtl_cpu1TopInit 0x01DC |
| #define B16Gbl_RingOscCtl_cpu1TopInit 0x01DC |
| #define LSb32Gbl_RingOscCtl_cpu1TopInit 4 |
| #define LSb16Gbl_RingOscCtl_cpu1TopInit 4 |
| #define bGbl_RingOscCtl_cpu1TopInit 1 |
| #define MSK32Gbl_RingOscCtl_cpu1TopInit 0x00000010 |
| #define Gbl_RingOscCtl_cpu1TopInit_OFF 0x0 |
| #define Gbl_RingOscCtl_cpu1TopInit_ON 0x1 |
| #define BA_Gbl_RingOscCtl_cpu0TopInit 0x01DC |
| #define B16Gbl_RingOscCtl_cpu0TopInit 0x01DC |
| #define LSb32Gbl_RingOscCtl_cpu0TopInit 5 |
| #define LSb16Gbl_RingOscCtl_cpu0TopInit 5 |
| #define bGbl_RingOscCtl_cpu0TopInit 1 |
| #define MSK32Gbl_RingOscCtl_cpu0TopInit 0x00000020 |
| #define Gbl_RingOscCtl_cpu0TopInit_OFF 0x0 |
| #define Gbl_RingOscCtl_cpu0TopInit_ON 0x1 |
| #define BA_Gbl_RingOscCtl_cpuBotInit 0x01DC |
| #define B16Gbl_RingOscCtl_cpuBotInit 0x01DC |
| #define LSb32Gbl_RingOscCtl_cpuBotInit 6 |
| #define LSb16Gbl_RingOscCtl_cpuBotInit 6 |
| #define bGbl_RingOscCtl_cpuBotInit 1 |
| #define MSK32Gbl_RingOscCtl_cpuBotInit 0x00000040 |
| #define Gbl_RingOscCtl_cpuBotInit_OFF 0x0 |
| #define Gbl_RingOscCtl_cpuBotInit_ON 0x1 |
| #define BA_Gbl_RingOscCtl_topRiteInit 0x01DC |
| #define B16Gbl_RingOscCtl_topRiteInit 0x01DC |
| #define LSb32Gbl_RingOscCtl_topRiteInit 7 |
| #define LSb16Gbl_RingOscCtl_topRiteInit 7 |
| #define bGbl_RingOscCtl_topRiteInit 1 |
| #define MSK32Gbl_RingOscCtl_topRiteInit 0x00000080 |
| #define Gbl_RingOscCtl_topRiteInit_OFF 0x0 |
| #define Gbl_RingOscCtl_topRiteInit_ON 0x1 |
| #define BA_Gbl_RingOscCtl_midRiteInit 0x01DD |
| #define B16Gbl_RingOscCtl_midRiteInit 0x01DC |
| #define LSb32Gbl_RingOscCtl_midRiteInit 8 |
| #define LSb16Gbl_RingOscCtl_midRiteInit 8 |
| #define bGbl_RingOscCtl_midRiteInit 1 |
| #define MSK32Gbl_RingOscCtl_midRiteInit 0x00000100 |
| #define Gbl_RingOscCtl_midRiteInit_OFF 0x0 |
| #define Gbl_RingOscCtl_midRiteInit_ON 0x1 |
| #define BA_Gbl_RingOscCtl_botRiteInit 0x01DD |
| #define B16Gbl_RingOscCtl_botRiteInit 0x01DC |
| #define LSb32Gbl_RingOscCtl_botRiteInit 9 |
| #define LSb16Gbl_RingOscCtl_botRiteInit 9 |
| #define bGbl_RingOscCtl_botRiteInit 1 |
| #define MSK32Gbl_RingOscCtl_botRiteInit 0x00000200 |
| #define Gbl_RingOscCtl_botRiteInit_OFF 0x0 |
| #define Gbl_RingOscCtl_botRiteInit_ON 0x1 |
| #define RA_Gbl_PLLBypsBootStrapEn 0x01E0 |
| #define BA_Gbl_PLLBypsBootStrapEn_sysPLLBypsEn 0x01E0 |
| #define B16Gbl_PLLBypsBootStrapEn_sysPLLBypsEn 0x01E0 |
| #define LSb32Gbl_PLLBypsBootStrapEn_sysPLLBypsEn 0 |
| #define LSb16Gbl_PLLBypsBootStrapEn_sysPLLBypsEn 0 |
| #define bGbl_PLLBypsBootStrapEn_sysPLLBypsEn 1 |
| #define MSK32Gbl_PLLBypsBootStrapEn_sysPLLBypsEn 0x00000001 |
| #define Gbl_PLLBypsBootStrapEn_sysPLLBypsEn_Disable 0x0 |
| #define Gbl_PLLBypsBootStrapEn_sysPLLBypsEn_Enable 0x1 |
| #define BA_Gbl_PLLBypsBootStrapEn_memPLLBypsEn 0x01E0 |
| #define B16Gbl_PLLBypsBootStrapEn_memPLLBypsEn 0x01E0 |
| #define LSb32Gbl_PLLBypsBootStrapEn_memPLLBypsEn 1 |
| #define LSb16Gbl_PLLBypsBootStrapEn_memPLLBypsEn 1 |
| #define bGbl_PLLBypsBootStrapEn_memPLLBypsEn 1 |
| #define MSK32Gbl_PLLBypsBootStrapEn_memPLLBypsEn 0x00000002 |
| #define Gbl_PLLBypsBootStrapEn_memPLLBypsEn_Disable 0x0 |
| #define Gbl_PLLBypsBootStrapEn_memPLLBypsEn_Enable 0x1 |
| #define BA_Gbl_PLLBypsBootStrapEn_cpu1PLLBypsEn 0x01E0 |
| #define B16Gbl_PLLBypsBootStrapEn_cpu1PLLBypsEn 0x01E0 |
| #define LSb32Gbl_PLLBypsBootStrapEn_cpu1PLLBypsEn 2 |
| #define LSb16Gbl_PLLBypsBootStrapEn_cpu1PLLBypsEn 2 |
| #define bGbl_PLLBypsBootStrapEn_cpu1PLLBypsEn 1 |
| #define MSK32Gbl_PLLBypsBootStrapEn_cpu1PLLBypsEn 0x00000004 |
| #define Gbl_PLLBypsBootStrapEn_cpu1PLLBypsEn_Disable 0x0 |
| #define Gbl_PLLBypsBootStrapEn_cpu1PLLBypsEn_Enable 0x1 |
| #define RA_Gbl_IO_CALIBRATE_IN 0x01E4 |
| #define BA_Gbl_IO_CALIBRATE_IN_DO 0x01E4 |
| #define B16Gbl_IO_CALIBRATE_IN_DO 0x01E4 |
| #define LSb32Gbl_IO_CALIBRATE_IN_DO 0 |
| #define LSb16Gbl_IO_CALIBRATE_IN_DO 0 |
| #define bGbl_IO_CALIBRATE_IN_DO 1 |
| #define MSK32Gbl_IO_CALIBRATE_IN_DO 0x00000001 |
| #define Gbl_IO_CALIBRATE_IN_DO_NMOS 0x0 |
| #define Gbl_IO_CALIBRATE_IN_DO_PMOS 0x1 |
| #define BA_Gbl_IO_CALIBRATE_IN_CAL_EN 0x01E4 |
| #define B16Gbl_IO_CALIBRATE_IN_CAL_EN 0x01E4 |
| #define LSb32Gbl_IO_CALIBRATE_IN_CAL_EN 1 |
| #define LSb16Gbl_IO_CALIBRATE_IN_CAL_EN 1 |
| #define bGbl_IO_CALIBRATE_IN_CAL_EN 1 |
| #define MSK32Gbl_IO_CALIBRATE_IN_CAL_EN 0x00000002 |
| #define Gbl_IO_CALIBRATE_IN_CAL_EN_DISABLE 0x0 |
| #define Gbl_IO_CALIBRATE_IN_CAL_EN_ENABLE 0x1 |
| #define BA_Gbl_IO_CALIBRATE_IN_ZP_CAL 0x01E4 |
| #define B16Gbl_IO_CALIBRATE_IN_ZP_CAL 0x01E4 |
| #define LSb32Gbl_IO_CALIBRATE_IN_ZP_CAL 2 |
| #define LSb16Gbl_IO_CALIBRATE_IN_ZP_CAL 2 |
| #define bGbl_IO_CALIBRATE_IN_ZP_CAL 3 |
| #define MSK32Gbl_IO_CALIBRATE_IN_ZP_CAL 0x0000001C |
| #define BA_Gbl_IO_CALIBRATE_IN_ZN_CAL 0x01E4 |
| #define B16Gbl_IO_CALIBRATE_IN_ZN_CAL 0x01E4 |
| #define LSb32Gbl_IO_CALIBRATE_IN_ZN_CAL 5 |
| #define LSb16Gbl_IO_CALIBRATE_IN_ZN_CAL 5 |
| #define bGbl_IO_CALIBRATE_IN_ZN_CAL 3 |
| #define MSK32Gbl_IO_CALIBRATE_IN_ZN_CAL 0x000000E0 |
| #define BA_Gbl_IO_CALIBRATE_IN_RON_ADJ 0x01E5 |
| #define B16Gbl_IO_CALIBRATE_IN_RON_ADJ 0x01E4 |
| #define LSb32Gbl_IO_CALIBRATE_IN_RON_ADJ 8 |
| #define LSb16Gbl_IO_CALIBRATE_IN_RON_ADJ 8 |
| #define bGbl_IO_CALIBRATE_IN_RON_ADJ 3 |
| #define MSK32Gbl_IO_CALIBRATE_IN_RON_ADJ 0x00000700 |
| #define BA_Gbl_IO_CALIBRATE_IN_TSI_CAL_N_EN 0x01E5 |
| #define B16Gbl_IO_CALIBRATE_IN_TSI_CAL_N_EN 0x01E4 |
| #define LSb32Gbl_IO_CALIBRATE_IN_TSI_CAL_N_EN 11 |
| #define LSb16Gbl_IO_CALIBRATE_IN_TSI_CAL_N_EN 11 |
| #define bGbl_IO_CALIBRATE_IN_TSI_CAL_N_EN 1 |
| #define MSK32Gbl_IO_CALIBRATE_IN_TSI_CAL_N_EN 0x00000800 |
| #define BA_Gbl_IO_CALIBRATE_IN_TSI_CAL_P_EN 0x01E5 |
| #define B16Gbl_IO_CALIBRATE_IN_TSI_CAL_P_EN 0x01E4 |
| #define LSb32Gbl_IO_CALIBRATE_IN_TSI_CAL_P_EN 12 |
| #define LSb16Gbl_IO_CALIBRATE_IN_TSI_CAL_P_EN 12 |
| #define bGbl_IO_CALIBRATE_IN_TSI_CAL_P_EN 1 |
| #define MSK32Gbl_IO_CALIBRATE_IN_TSI_CAL_P_EN 0x00001000 |
| #define BA_Gbl_IO_CALIBRATE_IN_TSI_ODR 0x01E5 |
| #define B16Gbl_IO_CALIBRATE_IN_TSI_ODR 0x01E4 |
| #define LSb32Gbl_IO_CALIBRATE_IN_TSI_ODR 13 |
| #define LSb16Gbl_IO_CALIBRATE_IN_TSI_ODR 13 |
| #define bGbl_IO_CALIBRATE_IN_TSI_ODR 3 |
| #define MSK32Gbl_IO_CALIBRATE_IN_TSI_ODR 0x0000E000 |
| #define BA_Gbl_IO_CALIBRATE_IN_TSI_ODR_EN 0x01E6 |
| #define B16Gbl_IO_CALIBRATE_IN_TSI_ODR_EN 0x01E6 |
| #define LSb32Gbl_IO_CALIBRATE_IN_TSI_ODR_EN 16 |
| #define LSb16Gbl_IO_CALIBRATE_IN_TSI_ODR_EN 0 |
| #define bGbl_IO_CALIBRATE_IN_TSI_ODR_EN 1 |
| #define MSK32Gbl_IO_CALIBRATE_IN_TSI_ODR_EN 0x00010000 |
| #define BA_Gbl_IO_CALIBRATE_IN_TSI_ZN 0x01E6 |
| #define B16Gbl_IO_CALIBRATE_IN_TSI_ZN 0x01E6 |
| #define LSb32Gbl_IO_CALIBRATE_IN_TSI_ZN 17 |
| #define LSb16Gbl_IO_CALIBRATE_IN_TSI_ZN 1 |
| #define bGbl_IO_CALIBRATE_IN_TSI_ZN 4 |
| #define MSK32Gbl_IO_CALIBRATE_IN_TSI_ZN 0x001E0000 |
| #define BA_Gbl_IO_CALIBRATE_IN_TSI_ZP 0x01E6 |
| #define B16Gbl_IO_CALIBRATE_IN_TSI_ZP 0x01E6 |
| #define LSb32Gbl_IO_CALIBRATE_IN_TSI_ZP 21 |
| #define LSb16Gbl_IO_CALIBRATE_IN_TSI_ZP 5 |
| #define bGbl_IO_CALIBRATE_IN_TSI_ZP 4 |
| #define MSK32Gbl_IO_CALIBRATE_IN_TSI_ZP 0x01E00000 |
| #define BA_Gbl_IO_CALIBRATE_IN_TSI_ZP_AFT_CAL 0x01E7 |
| #define B16Gbl_IO_CALIBRATE_IN_TSI_ZP_AFT_CAL 0x01E6 |
| #define LSb32Gbl_IO_CALIBRATE_IN_TSI_ZP_AFT_CAL 25 |
| #define LSb16Gbl_IO_CALIBRATE_IN_TSI_ZP_AFT_CAL 9 |
| #define bGbl_IO_CALIBRATE_IN_TSI_ZP_AFT_CAL 4 |
| #define MSK32Gbl_IO_CALIBRATE_IN_TSI_ZP_AFT_CAL 0x1E000000 |
| #define BA_Gbl_IO_CALIBRATE_IN_NAND_CAL_N_EN 0x01E7 |
| #define B16Gbl_IO_CALIBRATE_IN_NAND_CAL_N_EN 0x01E6 |
| #define LSb32Gbl_IO_CALIBRATE_IN_NAND_CAL_N_EN 29 |
| #define LSb16Gbl_IO_CALIBRATE_IN_NAND_CAL_N_EN 13 |
| #define bGbl_IO_CALIBRATE_IN_NAND_CAL_N_EN 1 |
| #define MSK32Gbl_IO_CALIBRATE_IN_NAND_CAL_N_EN 0x20000000 |
| #define BA_Gbl_IO_CALIBRATE_IN_NAND_CAL_P_EN 0x01E7 |
| #define B16Gbl_IO_CALIBRATE_IN_NAND_CAL_P_EN 0x01E6 |
| #define LSb32Gbl_IO_CALIBRATE_IN_NAND_CAL_P_EN 30 |
| #define LSb16Gbl_IO_CALIBRATE_IN_NAND_CAL_P_EN 14 |
| #define bGbl_IO_CALIBRATE_IN_NAND_CAL_P_EN 1 |
| #define MSK32Gbl_IO_CALIBRATE_IN_NAND_CAL_P_EN 0x40000000 |
| #define RA_Gbl_IO_CALIBRATE_IN1 0x01E8 |
| #define BA_Gbl_IO_CALIBRATE_IN_NAND_ODR 0x01E8 |
| #define B16Gbl_IO_CALIBRATE_IN_NAND_ODR 0x01E8 |
| #define LSb32Gbl_IO_CALIBRATE_IN_NAND_ODR 0 |
| #define LSb16Gbl_IO_CALIBRATE_IN_NAND_ODR 0 |
| #define bGbl_IO_CALIBRATE_IN_NAND_ODR 3 |
| #define MSK32Gbl_IO_CALIBRATE_IN_NAND_ODR 0x00000007 |
| #define BA_Gbl_IO_CALIBRATE_IN_NAND_ODR_EN 0x01E8 |
| #define B16Gbl_IO_CALIBRATE_IN_NAND_ODR_EN 0x01E8 |
| #define LSb32Gbl_IO_CALIBRATE_IN_NAND_ODR_EN 3 |
| #define LSb16Gbl_IO_CALIBRATE_IN_NAND_ODR_EN 3 |
| #define bGbl_IO_CALIBRATE_IN_NAND_ODR_EN 1 |
| #define MSK32Gbl_IO_CALIBRATE_IN_NAND_ODR_EN 0x00000008 |
| #define BA_Gbl_IO_CALIBRATE_IN_NAND_ZN 0x01E8 |
| #define B16Gbl_IO_CALIBRATE_IN_NAND_ZN 0x01E8 |
| #define LSb32Gbl_IO_CALIBRATE_IN_NAND_ZN 4 |
| #define LSb16Gbl_IO_CALIBRATE_IN_NAND_ZN 4 |
| #define bGbl_IO_CALIBRATE_IN_NAND_ZN 4 |
| #define MSK32Gbl_IO_CALIBRATE_IN_NAND_ZN 0x000000F0 |
| #define BA_Gbl_IO_CALIBRATE_IN_NAND_ZP 0x01E9 |
| #define B16Gbl_IO_CALIBRATE_IN_NAND_ZP 0x01E8 |
| #define LSb32Gbl_IO_CALIBRATE_IN_NAND_ZP 8 |
| #define LSb16Gbl_IO_CALIBRATE_IN_NAND_ZP 8 |
| #define bGbl_IO_CALIBRATE_IN_NAND_ZP 4 |
| #define MSK32Gbl_IO_CALIBRATE_IN_NAND_ZP 0x00000F00 |
| #define BA_Gbl_IO_CALIBRATE_IN_NAND_ZP_AFT_CAL 0x01E9 |
| #define B16Gbl_IO_CALIBRATE_IN_NAND_ZP_AFT_CAL 0x01E8 |
| #define LSb32Gbl_IO_CALIBRATE_IN_NAND_ZP_AFT_CAL 12 |
| #define LSb16Gbl_IO_CALIBRATE_IN_NAND_ZP_AFT_CAL 12 |
| #define bGbl_IO_CALIBRATE_IN_NAND_ZP_AFT_CAL 4 |
| #define MSK32Gbl_IO_CALIBRATE_IN_NAND_ZP_AFT_CAL 0x0000F000 |
| #define BA_Gbl_IO_CALIBRATE_IN_SPI_CAL_N_EN 0x01EA |
| #define B16Gbl_IO_CALIBRATE_IN_SPI_CAL_N_EN 0x01EA |
| #define LSb32Gbl_IO_CALIBRATE_IN_SPI_CAL_N_EN 16 |
| #define LSb16Gbl_IO_CALIBRATE_IN_SPI_CAL_N_EN 0 |
| #define bGbl_IO_CALIBRATE_IN_SPI_CAL_N_EN 1 |
| #define MSK32Gbl_IO_CALIBRATE_IN_SPI_CAL_N_EN 0x00010000 |
| #define BA_Gbl_IO_CALIBRATE_IN_SPI_CAL_P_EN 0x01EA |
| #define B16Gbl_IO_CALIBRATE_IN_SPI_CAL_P_EN 0x01EA |
| #define LSb32Gbl_IO_CALIBRATE_IN_SPI_CAL_P_EN 17 |
| #define LSb16Gbl_IO_CALIBRATE_IN_SPI_CAL_P_EN 1 |
| #define bGbl_IO_CALIBRATE_IN_SPI_CAL_P_EN 1 |
| #define MSK32Gbl_IO_CALIBRATE_IN_SPI_CAL_P_EN 0x00020000 |
| #define BA_Gbl_IO_CALIBRATE_IN_SPI_ODR 0x01EA |
| #define B16Gbl_IO_CALIBRATE_IN_SPI_ODR 0x01EA |
| #define LSb32Gbl_IO_CALIBRATE_IN_SPI_ODR 18 |
| #define LSb16Gbl_IO_CALIBRATE_IN_SPI_ODR 2 |
| #define bGbl_IO_CALIBRATE_IN_SPI_ODR 3 |
| #define MSK32Gbl_IO_CALIBRATE_IN_SPI_ODR 0x001C0000 |
| #define BA_Gbl_IO_CALIBRATE_IN_SPI_ODR_EN 0x01EA |
| #define B16Gbl_IO_CALIBRATE_IN_SPI_ODR_EN 0x01EA |
| #define LSb32Gbl_IO_CALIBRATE_IN_SPI_ODR_EN 21 |
| #define LSb16Gbl_IO_CALIBRATE_IN_SPI_ODR_EN 5 |
| #define bGbl_IO_CALIBRATE_IN_SPI_ODR_EN 1 |
| #define MSK32Gbl_IO_CALIBRATE_IN_SPI_ODR_EN 0x00200000 |
| #define BA_Gbl_IO_CALIBRATE_IN_SPI_ZN 0x01EA |
| #define B16Gbl_IO_CALIBRATE_IN_SPI_ZN 0x01EA |
| #define LSb32Gbl_IO_CALIBRATE_IN_SPI_ZN 22 |
| #define LSb16Gbl_IO_CALIBRATE_IN_SPI_ZN 6 |
| #define bGbl_IO_CALIBRATE_IN_SPI_ZN 4 |
| #define MSK32Gbl_IO_CALIBRATE_IN_SPI_ZN 0x03C00000 |
| #define BA_Gbl_IO_CALIBRATE_IN_SPI_ZP 0x01EB |
| #define B16Gbl_IO_CALIBRATE_IN_SPI_ZP 0x01EA |
| #define LSb32Gbl_IO_CALIBRATE_IN_SPI_ZP 26 |
| #define LSb16Gbl_IO_CALIBRATE_IN_SPI_ZP 10 |
| #define bGbl_IO_CALIBRATE_IN_SPI_ZP 4 |
| #define MSK32Gbl_IO_CALIBRATE_IN_SPI_ZP 0x3C000000 |
| #define RA_Gbl_IO_CALIBRATE_IN2 0x01EC |
| #define BA_Gbl_IO_CALIBRATE_IN_SPI_ZP_AFT_CAL 0x01EC |
| #define B16Gbl_IO_CALIBRATE_IN_SPI_ZP_AFT_CAL 0x01EC |
| #define LSb32Gbl_IO_CALIBRATE_IN_SPI_ZP_AFT_CAL 0 |
| #define LSb16Gbl_IO_CALIBRATE_IN_SPI_ZP_AFT_CAL 0 |
| #define bGbl_IO_CALIBRATE_IN_SPI_ZP_AFT_CAL 4 |
| #define MSK32Gbl_IO_CALIBRATE_IN_SPI_ZP_AFT_CAL 0x0000000F |
| #define BA_Gbl_IO_CALIBRATE_IN_SD0_CAL_N_EN 0x01EC |
| #define B16Gbl_IO_CALIBRATE_IN_SD0_CAL_N_EN 0x01EC |
| #define LSb32Gbl_IO_CALIBRATE_IN_SD0_CAL_N_EN 4 |
| #define LSb16Gbl_IO_CALIBRATE_IN_SD0_CAL_N_EN 4 |
| #define bGbl_IO_CALIBRATE_IN_SD0_CAL_N_EN 1 |
| #define MSK32Gbl_IO_CALIBRATE_IN_SD0_CAL_N_EN 0x00000010 |
| #define BA_Gbl_IO_CALIBRATE_IN_SD0_CAL_P_EN 0x01EC |
| #define B16Gbl_IO_CALIBRATE_IN_SD0_CAL_P_EN 0x01EC |
| #define LSb32Gbl_IO_CALIBRATE_IN_SD0_CAL_P_EN 5 |
| #define LSb16Gbl_IO_CALIBRATE_IN_SD0_CAL_P_EN 5 |
| #define bGbl_IO_CALIBRATE_IN_SD0_CAL_P_EN 1 |
| #define MSK32Gbl_IO_CALIBRATE_IN_SD0_CAL_P_EN 0x00000020 |
| #define BA_Gbl_IO_CALIBRATE_IN_SD0_ODR 0x01EC |
| #define B16Gbl_IO_CALIBRATE_IN_SD0_ODR 0x01EC |
| #define LSb32Gbl_IO_CALIBRATE_IN_SD0_ODR 6 |
| #define LSb16Gbl_IO_CALIBRATE_IN_SD0_ODR 6 |
| #define bGbl_IO_CALIBRATE_IN_SD0_ODR 3 |
| #define MSK32Gbl_IO_CALIBRATE_IN_SD0_ODR 0x000001C0 |
| #define BA_Gbl_IO_CALIBRATE_IN_SD0_ODR_EN 0x01ED |
| #define B16Gbl_IO_CALIBRATE_IN_SD0_ODR_EN 0x01EC |
| #define LSb32Gbl_IO_CALIBRATE_IN_SD0_ODR_EN 9 |
| #define LSb16Gbl_IO_CALIBRATE_IN_SD0_ODR_EN 9 |
| #define bGbl_IO_CALIBRATE_IN_SD0_ODR_EN 1 |
| #define MSK32Gbl_IO_CALIBRATE_IN_SD0_ODR_EN 0x00000200 |
| #define BA_Gbl_IO_CALIBRATE_IN_SD0_ZN 0x01ED |
| #define B16Gbl_IO_CALIBRATE_IN_SD0_ZN 0x01EC |
| #define LSb32Gbl_IO_CALIBRATE_IN_SD0_ZN 10 |
| #define LSb16Gbl_IO_CALIBRATE_IN_SD0_ZN 10 |
| #define bGbl_IO_CALIBRATE_IN_SD0_ZN 4 |
| #define MSK32Gbl_IO_CALIBRATE_IN_SD0_ZN 0x00003C00 |
| #define BA_Gbl_IO_CALIBRATE_IN_SD0_ZP 0x01ED |
| #define B16Gbl_IO_CALIBRATE_IN_SD0_ZP 0x01EC |
| #define LSb32Gbl_IO_CALIBRATE_IN_SD0_ZP 14 |
| #define LSb16Gbl_IO_CALIBRATE_IN_SD0_ZP 14 |
| #define bGbl_IO_CALIBRATE_IN_SD0_ZP 4 |
| #define MSK32Gbl_IO_CALIBRATE_IN_SD0_ZP 0x0003C000 |
| #define BA_Gbl_IO_CALIBRATE_IN_SD0_ZP_AFT_CAL 0x01EE |
| #define B16Gbl_IO_CALIBRATE_IN_SD0_ZP_AFT_CAL 0x01EE |
| #define LSb32Gbl_IO_CALIBRATE_IN_SD0_ZP_AFT_CAL 18 |
| #define LSb16Gbl_IO_CALIBRATE_IN_SD0_ZP_AFT_CAL 2 |
| #define bGbl_IO_CALIBRATE_IN_SD0_ZP_AFT_CAL 4 |
| #define MSK32Gbl_IO_CALIBRATE_IN_SD0_ZP_AFT_CAL 0x003C0000 |
| #define BA_Gbl_IO_CALIBRATE_IN_SD1_CAL_N_EN 0x01EE |
| #define B16Gbl_IO_CALIBRATE_IN_SD1_CAL_N_EN 0x01EE |
| #define LSb32Gbl_IO_CALIBRATE_IN_SD1_CAL_N_EN 22 |
| #define LSb16Gbl_IO_CALIBRATE_IN_SD1_CAL_N_EN 6 |
| #define bGbl_IO_CALIBRATE_IN_SD1_CAL_N_EN 1 |
| #define MSK32Gbl_IO_CALIBRATE_IN_SD1_CAL_N_EN 0x00400000 |
| #define BA_Gbl_IO_CALIBRATE_IN_SD1_CAL_P_EN 0x01EE |
| #define B16Gbl_IO_CALIBRATE_IN_SD1_CAL_P_EN 0x01EE |
| #define LSb32Gbl_IO_CALIBRATE_IN_SD1_CAL_P_EN 23 |
| #define LSb16Gbl_IO_CALIBRATE_IN_SD1_CAL_P_EN 7 |
| #define bGbl_IO_CALIBRATE_IN_SD1_CAL_P_EN 1 |
| #define MSK32Gbl_IO_CALIBRATE_IN_SD1_CAL_P_EN 0x00800000 |
| #define BA_Gbl_IO_CALIBRATE_IN_SD1_ODR 0x01EF |
| #define B16Gbl_IO_CALIBRATE_IN_SD1_ODR 0x01EE |
| #define LSb32Gbl_IO_CALIBRATE_IN_SD1_ODR 24 |
| #define LSb16Gbl_IO_CALIBRATE_IN_SD1_ODR 8 |
| #define bGbl_IO_CALIBRATE_IN_SD1_ODR 3 |
| #define MSK32Gbl_IO_CALIBRATE_IN_SD1_ODR 0x07000000 |
| #define BA_Gbl_IO_CALIBRATE_IN_SD1_ODR_EN 0x01EF |
| #define B16Gbl_IO_CALIBRATE_IN_SD1_ODR_EN 0x01EE |
| #define LSb32Gbl_IO_CALIBRATE_IN_SD1_ODR_EN 27 |
| #define LSb16Gbl_IO_CALIBRATE_IN_SD1_ODR_EN 11 |
| #define bGbl_IO_CALIBRATE_IN_SD1_ODR_EN 1 |
| #define MSK32Gbl_IO_CALIBRATE_IN_SD1_ODR_EN 0x08000000 |
| #define BA_Gbl_IO_CALIBRATE_IN_SD1_ZN 0x01EF |
| #define B16Gbl_IO_CALIBRATE_IN_SD1_ZN 0x01EE |
| #define LSb32Gbl_IO_CALIBRATE_IN_SD1_ZN 28 |
| #define LSb16Gbl_IO_CALIBRATE_IN_SD1_ZN 12 |
| #define bGbl_IO_CALIBRATE_IN_SD1_ZN 4 |
| #define MSK32Gbl_IO_CALIBRATE_IN_SD1_ZN 0xF0000000 |
| #define RA_Gbl_IO_CALIBRATE_IN3 0x01F0 |
| #define BA_Gbl_IO_CALIBRATE_IN_SD1_ZP 0x01F0 |
| #define B16Gbl_IO_CALIBRATE_IN_SD1_ZP 0x01F0 |
| #define LSb32Gbl_IO_CALIBRATE_IN_SD1_ZP 0 |
| #define LSb16Gbl_IO_CALIBRATE_IN_SD1_ZP 0 |
| #define bGbl_IO_CALIBRATE_IN_SD1_ZP 4 |
| #define MSK32Gbl_IO_CALIBRATE_IN_SD1_ZP 0x0000000F |
| #define BA_Gbl_IO_CALIBRATE_IN_SD1_ZP_AFT_CAL 0x01F0 |
| #define B16Gbl_IO_CALIBRATE_IN_SD1_ZP_AFT_CAL 0x01F0 |
| #define LSb32Gbl_IO_CALIBRATE_IN_SD1_ZP_AFT_CAL 4 |
| #define LSb16Gbl_IO_CALIBRATE_IN_SD1_ZP_AFT_CAL 4 |
| #define bGbl_IO_CALIBRATE_IN_SD1_ZP_AFT_CAL 4 |
| #define MSK32Gbl_IO_CALIBRATE_IN_SD1_ZP_AFT_CAL 0x000000F0 |
| #define BA_Gbl_IO_CALIBRATE_IN_DVIO_1_DO 0x01F1 |
| #define B16Gbl_IO_CALIBRATE_IN_DVIO_1_DO 0x01F0 |
| #define LSb32Gbl_IO_CALIBRATE_IN_DVIO_1_DO 8 |
| #define LSb16Gbl_IO_CALIBRATE_IN_DVIO_1_DO 8 |
| #define bGbl_IO_CALIBRATE_IN_DVIO_1_DO 1 |
| #define MSK32Gbl_IO_CALIBRATE_IN_DVIO_1_DO 0x00000100 |
| #define Gbl_IO_CALIBRATE_IN_DVIO_1_DO_NMOS 0x0 |
| #define Gbl_IO_CALIBRATE_IN_DVIO_1_DO_PMOS 0x1 |
| #define BA_Gbl_IO_CALIBRATE_IN_DVIO_1_CAL_EN 0x01F1 |
| #define B16Gbl_IO_CALIBRATE_IN_DVIO_1_CAL_EN 0x01F0 |
| #define LSb32Gbl_IO_CALIBRATE_IN_DVIO_1_CAL_EN 9 |
| #define LSb16Gbl_IO_CALIBRATE_IN_DVIO_1_CAL_EN 9 |
| #define bGbl_IO_CALIBRATE_IN_DVIO_1_CAL_EN 1 |
| #define MSK32Gbl_IO_CALIBRATE_IN_DVIO_1_CAL_EN 0x00000200 |
| #define Gbl_IO_CALIBRATE_IN_DVIO_1_CAL_EN_DISABLE 0x0 |
| #define Gbl_IO_CALIBRATE_IN_DVIO_1_CAL_EN_ENABLE 0x1 |
| #define BA_Gbl_IO_CALIBRATE_IN_DVIO_1_ZP_CAL 0x01F1 |
| #define B16Gbl_IO_CALIBRATE_IN_DVIO_1_ZP_CAL 0x01F0 |
| #define LSb32Gbl_IO_CALIBRATE_IN_DVIO_1_ZP_CAL 10 |
| #define LSb16Gbl_IO_CALIBRATE_IN_DVIO_1_ZP_CAL 10 |
| #define bGbl_IO_CALIBRATE_IN_DVIO_1_ZP_CAL 3 |
| #define MSK32Gbl_IO_CALIBRATE_IN_DVIO_1_ZP_CAL 0x00001C00 |
| #define BA_Gbl_IO_CALIBRATE_IN_DVIO_1_ZN_CAL 0x01F1 |
| #define B16Gbl_IO_CALIBRATE_IN_DVIO_1_ZN_CAL 0x01F0 |
| #define LSb32Gbl_IO_CALIBRATE_IN_DVIO_1_ZN_CAL 13 |
| #define LSb16Gbl_IO_CALIBRATE_IN_DVIO_1_ZN_CAL 13 |
| #define bGbl_IO_CALIBRATE_IN_DVIO_1_ZN_CAL 3 |
| #define MSK32Gbl_IO_CALIBRATE_IN_DVIO_1_ZN_CAL 0x0000E000 |
| #define BA_Gbl_IO_CALIBRATE_IN_DVIO_1_RON_ADJ 0x01F2 |
| #define B16Gbl_IO_CALIBRATE_IN_DVIO_1_RON_ADJ 0x01F2 |
| #define LSb32Gbl_IO_CALIBRATE_IN_DVIO_1_RON_ADJ 16 |
| #define LSb16Gbl_IO_CALIBRATE_IN_DVIO_1_RON_ADJ 0 |
| #define bGbl_IO_CALIBRATE_IN_DVIO_1_RON_ADJ 3 |
| #define MSK32Gbl_IO_CALIBRATE_IN_DVIO_1_RON_ADJ 0x00070000 |
| #define BA_Gbl_IO_CALIBRATE_IN_I2S_DO 0x01F2 |
| #define B16Gbl_IO_CALIBRATE_IN_I2S_DO 0x01F2 |
| #define LSb32Gbl_IO_CALIBRATE_IN_I2S_DO 19 |
| #define LSb16Gbl_IO_CALIBRATE_IN_I2S_DO 3 |
| #define bGbl_IO_CALIBRATE_IN_I2S_DO 1 |
| #define MSK32Gbl_IO_CALIBRATE_IN_I2S_DO 0x00080000 |
| #define Gbl_IO_CALIBRATE_IN_I2S_DO_NMOS 0x0 |
| #define Gbl_IO_CALIBRATE_IN_I2S_DO_PMOS 0x1 |
| #define BA_Gbl_IO_CALIBRATE_IN_I2S_CAL_EN 0x01F2 |
| #define B16Gbl_IO_CALIBRATE_IN_I2S_CAL_EN 0x01F2 |
| #define LSb32Gbl_IO_CALIBRATE_IN_I2S_CAL_EN 20 |
| #define LSb16Gbl_IO_CALIBRATE_IN_I2S_CAL_EN 4 |
| #define bGbl_IO_CALIBRATE_IN_I2S_CAL_EN 1 |
| #define MSK32Gbl_IO_CALIBRATE_IN_I2S_CAL_EN 0x00100000 |
| #define Gbl_IO_CALIBRATE_IN_I2S_CAL_EN_DISABLE 0x0 |
| #define Gbl_IO_CALIBRATE_IN_I2S_CAL_EN_ENABLE 0x1 |
| #define BA_Gbl_IO_CALIBRATE_IN_I2S_ZP_CAL 0x01F2 |
| #define B16Gbl_IO_CALIBRATE_IN_I2S_ZP_CAL 0x01F2 |
| #define LSb32Gbl_IO_CALIBRATE_IN_I2S_ZP_CAL 21 |
| #define LSb16Gbl_IO_CALIBRATE_IN_I2S_ZP_CAL 5 |
| #define bGbl_IO_CALIBRATE_IN_I2S_ZP_CAL 3 |
| #define MSK32Gbl_IO_CALIBRATE_IN_I2S_ZP_CAL 0x00E00000 |
| #define BA_Gbl_IO_CALIBRATE_IN_I2S_ZN_CAL 0x01F3 |
| #define B16Gbl_IO_CALIBRATE_IN_I2S_ZN_CAL 0x01F2 |
| #define LSb32Gbl_IO_CALIBRATE_IN_I2S_ZN_CAL 24 |
| #define LSb16Gbl_IO_CALIBRATE_IN_I2S_ZN_CAL 8 |
| #define bGbl_IO_CALIBRATE_IN_I2S_ZN_CAL 3 |
| #define MSK32Gbl_IO_CALIBRATE_IN_I2S_ZN_CAL 0x07000000 |
| #define BA_Gbl_IO_CALIBRATE_IN_I2S_RON_ADJ 0x01F3 |
| #define B16Gbl_IO_CALIBRATE_IN_I2S_RON_ADJ 0x01F2 |
| #define LSb32Gbl_IO_CALIBRATE_IN_I2S_RON_ADJ 27 |
| #define LSb16Gbl_IO_CALIBRATE_IN_I2S_RON_ADJ 11 |
| #define bGbl_IO_CALIBRATE_IN_I2S_RON_ADJ 3 |
| #define MSK32Gbl_IO_CALIBRATE_IN_I2S_RON_ADJ 0x38000000 |
| #define RA_Gbl_IO_CALBRATE_OUT 0x01F4 |
| #define BA_Gbl_IO_CALBRATE_OUT_INC 0x01F4 |
| #define B16Gbl_IO_CALBRATE_OUT_INC 0x01F4 |
| #define LSb32Gbl_IO_CALBRATE_OUT_INC 0 |
| #define LSb16Gbl_IO_CALBRATE_OUT_INC 0 |
| #define bGbl_IO_CALBRATE_OUT_INC 1 |
| #define MSK32Gbl_IO_CALBRATE_OUT_INC 0x00000001 |
| #define BA_Gbl_IO_CALBRATE_OUT_TSI_CAL_N_INC 0x01F4 |
| #define B16Gbl_IO_CALBRATE_OUT_TSI_CAL_N_INC 0x01F4 |
| #define LSb32Gbl_IO_CALBRATE_OUT_TSI_CAL_N_INC 1 |
| #define LSb16Gbl_IO_CALBRATE_OUT_TSI_CAL_N_INC 1 |
| #define bGbl_IO_CALBRATE_OUT_TSI_CAL_N_INC 1 |
| #define MSK32Gbl_IO_CALBRATE_OUT_TSI_CAL_N_INC 0x00000002 |
| #define BA_Gbl_IO_CALBRATE_OUT_TSI_CAL_P_INC 0x01F4 |
| #define B16Gbl_IO_CALBRATE_OUT_TSI_CAL_P_INC 0x01F4 |
| #define LSb32Gbl_IO_CALBRATE_OUT_TSI_CAL_P_INC 2 |
| #define LSb16Gbl_IO_CALBRATE_OUT_TSI_CAL_P_INC 2 |
| #define bGbl_IO_CALBRATE_OUT_TSI_CAL_P_INC 1 |
| #define MSK32Gbl_IO_CALBRATE_OUT_TSI_CAL_P_INC 0x00000004 |
| #define BA_Gbl_IO_CALBRATE_OUT_SD0_CAL_N_INC 0x01F4 |
| #define B16Gbl_IO_CALBRATE_OUT_SD0_CAL_N_INC 0x01F4 |
| #define LSb32Gbl_IO_CALBRATE_OUT_SD0_CAL_N_INC 3 |
| #define LSb16Gbl_IO_CALBRATE_OUT_SD0_CAL_N_INC 3 |
| #define bGbl_IO_CALBRATE_OUT_SD0_CAL_N_INC 1 |
| #define MSK32Gbl_IO_CALBRATE_OUT_SD0_CAL_N_INC 0x00000008 |
| #define BA_Gbl_IO_CALBRATE_OUT_SD0_CAL_P_INC 0x01F4 |
| #define B16Gbl_IO_CALBRATE_OUT_SD0_CAL_P_INC 0x01F4 |
| #define LSb32Gbl_IO_CALBRATE_OUT_SD0_CAL_P_INC 4 |
| #define LSb16Gbl_IO_CALBRATE_OUT_SD0_CAL_P_INC 4 |
| #define bGbl_IO_CALBRATE_OUT_SD0_CAL_P_INC 1 |
| #define MSK32Gbl_IO_CALBRATE_OUT_SD0_CAL_P_INC 0x00000010 |
| #define BA_Gbl_IO_CALBRATE_OUT_SD1_CAL_N_INC 0x01F4 |
| #define B16Gbl_IO_CALBRATE_OUT_SD1_CAL_N_INC 0x01F4 |
| #define LSb32Gbl_IO_CALBRATE_OUT_SD1_CAL_N_INC 5 |
| #define LSb16Gbl_IO_CALBRATE_OUT_SD1_CAL_N_INC 5 |
| #define bGbl_IO_CALBRATE_OUT_SD1_CAL_N_INC 1 |
| #define MSK32Gbl_IO_CALBRATE_OUT_SD1_CAL_N_INC 0x00000020 |
| #define BA_Gbl_IO_CALBRATE_OUT_SD1_CAL_P_INC 0x01F4 |
| #define B16Gbl_IO_CALBRATE_OUT_SD1_CAL_P_INC 0x01F4 |
| #define LSb32Gbl_IO_CALBRATE_OUT_SD1_CAL_P_INC 6 |
| #define LSb16Gbl_IO_CALBRATE_OUT_SD1_CAL_P_INC 6 |
| #define bGbl_IO_CALBRATE_OUT_SD1_CAL_P_INC 1 |
| #define MSK32Gbl_IO_CALBRATE_OUT_SD1_CAL_P_INC 0x00000040 |
| #define BA_Gbl_IO_CALBRATE_OUT_NAND_CAL_N_INC 0x01F4 |
| #define B16Gbl_IO_CALBRATE_OUT_NAND_CAL_N_INC 0x01F4 |
| #define LSb32Gbl_IO_CALBRATE_OUT_NAND_CAL_N_INC 7 |
| #define LSb16Gbl_IO_CALBRATE_OUT_NAND_CAL_N_INC 7 |
| #define bGbl_IO_CALBRATE_OUT_NAND_CAL_N_INC 1 |
| #define MSK32Gbl_IO_CALBRATE_OUT_NAND_CAL_N_INC 0x00000080 |
| #define BA_Gbl_IO_CALBRATE_OUT_NAND_CAL_P_INC 0x01F5 |
| #define B16Gbl_IO_CALBRATE_OUT_NAND_CAL_P_INC 0x01F4 |
| #define LSb32Gbl_IO_CALBRATE_OUT_NAND_CAL_P_INC 8 |
| #define LSb16Gbl_IO_CALBRATE_OUT_NAND_CAL_P_INC 8 |
| #define bGbl_IO_CALBRATE_OUT_NAND_CAL_P_INC 1 |
| #define MSK32Gbl_IO_CALBRATE_OUT_NAND_CAL_P_INC 0x00000100 |
| #define BA_Gbl_IO_CALBRATE_OUT_DVIO_1_INC 0x01F5 |
| #define B16Gbl_IO_CALBRATE_OUT_DVIO_1_INC 0x01F4 |
| #define LSb32Gbl_IO_CALBRATE_OUT_DVIO_1_INC 9 |
| #define LSb16Gbl_IO_CALBRATE_OUT_DVIO_1_INC 9 |
| #define bGbl_IO_CALBRATE_OUT_DVIO_1_INC 1 |
| #define MSK32Gbl_IO_CALBRATE_OUT_DVIO_1_INC 0x00000200 |
| #define BA_Gbl_IO_CALBRATE_OUT_I2S_INC 0x01F5 |
| #define B16Gbl_IO_CALBRATE_OUT_I2S_INC 0x01F4 |
| #define LSb32Gbl_IO_CALBRATE_OUT_I2S_INC 10 |
| #define LSb16Gbl_IO_CALBRATE_OUT_I2S_INC 10 |
| #define bGbl_IO_CALBRATE_OUT_I2S_INC 1 |
| #define MSK32Gbl_IO_CALBRATE_OUT_I2S_INC 0x00000400 |
| #define RA_Gbl_SECURE_SCAN_EN 0x01F8 |
| #define BA_Gbl_SECURE_SCAN_EN_SET 0x01F8 |
| #define B16Gbl_SECURE_SCAN_EN_SET 0x01F8 |
| #define LSb32Gbl_SECURE_SCAN_EN_SET 0 |
| #define LSb16Gbl_SECURE_SCAN_EN_SET 0 |
| #define bGbl_SECURE_SCAN_EN_SET 1 |
| #define MSK32Gbl_SECURE_SCAN_EN_SET 0x00000001 |
| #define RA_Gbl_NandWPn 0x01FC |
| #define BA_Gbl_NandWPn_Sel 0x01FC |
| #define B16Gbl_NandWPn_Sel 0x01FC |
| #define LSb32Gbl_NandWPn_Sel 0 |
| #define LSb16Gbl_NandWPn_Sel 0 |
| #define bGbl_NandWPn_Sel 1 |
| #define MSK32Gbl_NandWPn_Sel 0x00000001 |
| #define RA_Gbl_RingCntCntl 0x0200 |
| #define BA_Gbl_RingCntCntl_centerStart 0x0200 |
| #define B16Gbl_RingCntCntl_centerStart 0x0200 |
| #define LSb32Gbl_RingCntCntl_centerStart 0 |
| #define LSb16Gbl_RingCntCntl_centerStart 0 |
| #define bGbl_RingCntCntl_centerStart 1 |
| #define MSK32Gbl_RingCntCntl_centerStart 0x00000001 |
| #define BA_Gbl_RingCntCntl_centerStop 0x0200 |
| #define B16Gbl_RingCntCntl_centerStop 0x0200 |
| #define LSb32Gbl_RingCntCntl_centerStop 1 |
| #define LSb16Gbl_RingCntCntl_centerStop 1 |
| #define bGbl_RingCntCntl_centerStop 1 |
| #define MSK32Gbl_RingCntCntl_centerStop 0x00000002 |
| #define BA_Gbl_RingCntCntl_avioTopStart 0x0200 |
| #define B16Gbl_RingCntCntl_avioTopStart 0x0200 |
| #define LSb32Gbl_RingCntCntl_avioTopStart 2 |
| #define LSb16Gbl_RingCntCntl_avioTopStart 2 |
| #define bGbl_RingCntCntl_avioTopStart 1 |
| #define MSK32Gbl_RingCntCntl_avioTopStart 0x00000004 |
| #define BA_Gbl_RingCntCntl_avioTopStop 0x0200 |
| #define B16Gbl_RingCntCntl_avioTopStop 0x0200 |
| #define LSb32Gbl_RingCntCntl_avioTopStop 3 |
| #define LSb16Gbl_RingCntCntl_avioTopStop 3 |
| #define bGbl_RingCntCntl_avioTopStop 1 |
| #define MSK32Gbl_RingCntCntl_avioTopStop 0x00000008 |
| #define BA_Gbl_RingCntCntl_avioBotStart 0x0200 |
| #define B16Gbl_RingCntCntl_avioBotStart 0x0200 |
| #define LSb32Gbl_RingCntCntl_avioBotStart 4 |
| #define LSb16Gbl_RingCntCntl_avioBotStart 4 |
| #define bGbl_RingCntCntl_avioBotStart 1 |
| #define MSK32Gbl_RingCntCntl_avioBotStart 0x00000010 |
| #define BA_Gbl_RingCntCntl_avioBotStop 0x0200 |
| #define B16Gbl_RingCntCntl_avioBotStop 0x0200 |
| #define LSb32Gbl_RingCntCntl_avioBotStop 5 |
| #define LSb16Gbl_RingCntCntl_avioBotStop 5 |
| #define bGbl_RingCntCntl_avioBotStop 1 |
| #define MSK32Gbl_RingCntCntl_avioBotStop 0x00000020 |
| #define BA_Gbl_RingCntCntl_usbTopStart 0x0200 |
| #define B16Gbl_RingCntCntl_usbTopStart 0x0200 |
| #define LSb32Gbl_RingCntCntl_usbTopStart 6 |
| #define LSb16Gbl_RingCntCntl_usbTopStart 6 |
| #define bGbl_RingCntCntl_usbTopStart 1 |
| #define MSK32Gbl_RingCntCntl_usbTopStart 0x00000040 |
| #define BA_Gbl_RingCntCntl_usbTopStop 0x0200 |
| #define B16Gbl_RingCntCntl_usbTopStop 0x0200 |
| #define LSb32Gbl_RingCntCntl_usbTopStop 7 |
| #define LSb16Gbl_RingCntCntl_usbTopStop 7 |
| #define bGbl_RingCntCntl_usbTopStop 1 |
| #define MSK32Gbl_RingCntCntl_usbTopStop 0x00000080 |
| #define BA_Gbl_RingCntCntl_cpu1TopStart 0x0201 |
| #define B16Gbl_RingCntCntl_cpu1TopStart 0x0200 |
| #define LSb32Gbl_RingCntCntl_cpu1TopStart 8 |
| #define LSb16Gbl_RingCntCntl_cpu1TopStart 8 |
| #define bGbl_RingCntCntl_cpu1TopStart 1 |
| #define MSK32Gbl_RingCntCntl_cpu1TopStart 0x00000100 |
| #define BA_Gbl_RingCntCntl_cpu1TopStop 0x0201 |
| #define B16Gbl_RingCntCntl_cpu1TopStop 0x0200 |
| #define LSb32Gbl_RingCntCntl_cpu1TopStop 9 |
| #define LSb16Gbl_RingCntCntl_cpu1TopStop 9 |
| #define bGbl_RingCntCntl_cpu1TopStop 1 |
| #define MSK32Gbl_RingCntCntl_cpu1TopStop 0x00000200 |
| #define BA_Gbl_RingCntCntl_cpu0TopStart 0x0201 |
| #define B16Gbl_RingCntCntl_cpu0TopStart 0x0200 |
| #define LSb32Gbl_RingCntCntl_cpu0TopStart 10 |
| #define LSb16Gbl_RingCntCntl_cpu0TopStart 10 |
| #define bGbl_RingCntCntl_cpu0TopStart 1 |
| #define MSK32Gbl_RingCntCntl_cpu0TopStart 0x00000400 |
| #define BA_Gbl_RingCntCntl_cpu0TopStop 0x0201 |
| #define B16Gbl_RingCntCntl_cpu0TopStop 0x0200 |
| #define LSb32Gbl_RingCntCntl_cpu0TopStop 11 |
| #define LSb16Gbl_RingCntCntl_cpu0TopStop 11 |
| #define bGbl_RingCntCntl_cpu0TopStop 1 |
| #define MSK32Gbl_RingCntCntl_cpu0TopStop 0x00000800 |
| #define BA_Gbl_RingCntCntl_cpuBotStart 0x0201 |
| #define B16Gbl_RingCntCntl_cpuBotStart 0x0200 |
| #define LSb32Gbl_RingCntCntl_cpuBotStart 12 |
| #define LSb16Gbl_RingCntCntl_cpuBotStart 12 |
| #define bGbl_RingCntCntl_cpuBotStart 1 |
| #define MSK32Gbl_RingCntCntl_cpuBotStart 0x00001000 |
| #define BA_Gbl_RingCntCntl_cpuBotStop 0x0201 |
| #define B16Gbl_RingCntCntl_cpuBotStop 0x0200 |
| #define LSb32Gbl_RingCntCntl_cpuBotStop 13 |
| #define LSb16Gbl_RingCntCntl_cpuBotStop 13 |
| #define bGbl_RingCntCntl_cpuBotStop 1 |
| #define MSK32Gbl_RingCntCntl_cpuBotStop 0x00002000 |
| #define BA_Gbl_RingCntCntl_topRiteStart 0x0201 |
| #define B16Gbl_RingCntCntl_topRiteStart 0x0200 |
| #define LSb32Gbl_RingCntCntl_topRiteStart 14 |
| #define LSb16Gbl_RingCntCntl_topRiteStart 14 |
| #define bGbl_RingCntCntl_topRiteStart 1 |
| #define MSK32Gbl_RingCntCntl_topRiteStart 0x00004000 |
| #define BA_Gbl_RingCntCntl_topRiteStop 0x0201 |
| #define B16Gbl_RingCntCntl_topRiteStop 0x0200 |
| #define LSb32Gbl_RingCntCntl_topRiteStop 15 |
| #define LSb16Gbl_RingCntCntl_topRiteStop 15 |
| #define bGbl_RingCntCntl_topRiteStop 1 |
| #define MSK32Gbl_RingCntCntl_topRiteStop 0x00008000 |
| #define BA_Gbl_RingCntCntl_midRiteStart 0x0202 |
| #define B16Gbl_RingCntCntl_midRiteStart 0x0202 |
| #define LSb32Gbl_RingCntCntl_midRiteStart 16 |
| #define LSb16Gbl_RingCntCntl_midRiteStart 0 |
| #define bGbl_RingCntCntl_midRiteStart 1 |
| #define MSK32Gbl_RingCntCntl_midRiteStart 0x00010000 |
| #define BA_Gbl_RingCntCntl_midRiteStop 0x0202 |
| #define B16Gbl_RingCntCntl_midRiteStop 0x0202 |
| #define LSb32Gbl_RingCntCntl_midRiteStop 17 |
| #define LSb16Gbl_RingCntCntl_midRiteStop 1 |
| #define bGbl_RingCntCntl_midRiteStop 1 |
| #define MSK32Gbl_RingCntCntl_midRiteStop 0x00020000 |
| #define BA_Gbl_RingCntCntl_botRiteStart 0x0202 |
| #define B16Gbl_RingCntCntl_botRiteStart 0x0202 |
| #define LSb32Gbl_RingCntCntl_botRiteStart 18 |
| #define LSb16Gbl_RingCntCntl_botRiteStart 2 |
| #define bGbl_RingCntCntl_botRiteStart 1 |
| #define MSK32Gbl_RingCntCntl_botRiteStart 0x00040000 |
| #define BA_Gbl_RingCntCntl_botRiteStop 0x0202 |
| #define B16Gbl_RingCntCntl_botRiteStop 0x0202 |
| #define LSb32Gbl_RingCntCntl_botRiteStop 19 |
| #define LSb16Gbl_RingCntCntl_botRiteStop 3 |
| #define bGbl_RingCntCntl_botRiteStop 1 |
| #define MSK32Gbl_RingCntCntl_botRiteStop 0x00080000 |
| #define RA_Gbl_topSvtDro0Cnt 0x0204 |
| #define RA_Gbl_topLvtDro1Cnt 0x0208 |
| #define RA_Gbl_topSvtDro2Cnt 0x020C |
| #define RA_Gbl_topLvtDro3Cnt 0x0210 |
| #define RA_Gbl_topSvtDro4Cnt 0x0214 |
| #define RA_Gbl_topLvtDro5Cnt 0x0218 |
| #define RA_Gbl_avioSvtDro0Cnt 0x021C |
| #define RA_Gbl_avioLvtDro1Cnt 0x0220 |
| #define RA_Gbl_avioSvtDro2Cnt 0x0224 |
| #define RA_Gbl_avioLvtDro3Cnt 0x0228 |
| #define RA_Gbl_gfx3DCoreClkCtrl 0x022C |
| #define BA_Gbl_gfx3DCoreClkCtrl_clkEN 0x022C |
| #define B16Gbl_gfx3DCoreClkCtrl_clkEN 0x022C |
| #define LSb32Gbl_gfx3DCoreClkCtrl_clkEN 0 |
| #define LSb16Gbl_gfx3DCoreClkCtrl_clkEN 0 |
| #define bGbl_gfx3DCoreClkCtrl_clkEN 1 |
| #define MSK32Gbl_gfx3DCoreClkCtrl_clkEN 0x00000001 |
| #define Gbl_gfx3DCoreClkCtrl_clkEN_enable 0x1 |
| #define Gbl_gfx3DCoreClkCtrl_clkEN_disable 0x0 |
| #define BA_Gbl_gfx3DCoreClkCtrl_ClkPllSel 0x022C |
| #define B16Gbl_gfx3DCoreClkCtrl_ClkPllSel 0x022C |
| #define LSb32Gbl_gfx3DCoreClkCtrl_ClkPllSel 1 |
| #define LSb16Gbl_gfx3DCoreClkCtrl_ClkPllSel 1 |
| #define bGbl_gfx3DCoreClkCtrl_ClkPllSel 3 |
| #define MSK32Gbl_gfx3DCoreClkCtrl_ClkPllSel 0x0000000E |
| #define Gbl_gfx3DCoreClkCtrl_ClkPllSel_AVPllB4 0x0 |
| #define Gbl_gfx3DCoreClkCtrl_ClkPllSel_AVPllB5 0x1 |
| #define Gbl_gfx3DCoreClkCtrl_ClkPllSel_AVPllB6 0x2 |
| #define Gbl_gfx3DCoreClkCtrl_ClkPllSel_AVPllB7 0x3 |
| #define Gbl_gfx3DCoreClkCtrl_ClkPllSel_SYSPll 0x4 |
| #define BA_Gbl_gfx3DCoreClkCtrl_ClkPllSwitch 0x022C |
| #define B16Gbl_gfx3DCoreClkCtrl_ClkPllSwitch 0x022C |
| #define LSb32Gbl_gfx3DCoreClkCtrl_ClkPllSwitch 4 |
| #define LSb16Gbl_gfx3DCoreClkCtrl_ClkPllSwitch 4 |
| #define bGbl_gfx3DCoreClkCtrl_ClkPllSwitch 1 |
| #define MSK32Gbl_gfx3DCoreClkCtrl_ClkPllSwitch 0x00000010 |
| #define Gbl_gfx3DCoreClkCtrl_ClkPllSwitch_SYSPLL 0x0 |
| #define Gbl_gfx3DCoreClkCtrl_ClkPllSwitch_AVPLL 0x1 |
| #define BA_Gbl_gfx3DCoreClkCtrl_ClkSwitch 0x022C |
| #define B16Gbl_gfx3DCoreClkCtrl_ClkSwitch 0x022C |
| #define LSb32Gbl_gfx3DCoreClkCtrl_ClkSwitch 5 |
| #define LSb16Gbl_gfx3DCoreClkCtrl_ClkSwitch 5 |
| #define bGbl_gfx3DCoreClkCtrl_ClkSwitch 1 |
| #define MSK32Gbl_gfx3DCoreClkCtrl_ClkSwitch 0x00000020 |
| #define Gbl_gfx3DCoreClkCtrl_ClkSwitch_SrcClk 0x0 |
| #define Gbl_gfx3DCoreClkCtrl_ClkSwitch_DivClk 0x1 |
| #define BA_Gbl_gfx3DCoreClkCtrl_ClkD3Switch 0x022C |
| #define B16Gbl_gfx3DCoreClkCtrl_ClkD3Switch 0x022C |
| #define LSb32Gbl_gfx3DCoreClkCtrl_ClkD3Switch 6 |
| #define LSb16Gbl_gfx3DCoreClkCtrl_ClkD3Switch 6 |
| #define bGbl_gfx3DCoreClkCtrl_ClkD3Switch 1 |
| #define MSK32Gbl_gfx3DCoreClkCtrl_ClkD3Switch 0x00000040 |
| #define Gbl_gfx3DCoreClkCtrl_ClkD3Switch_NonDiv3Clk 0x0 |
| #define Gbl_gfx3DCoreClkCtrl_ClkD3Switch_Div3Clk 0x1 |
| #define BA_Gbl_gfx3DCoreClkCtrl_ClkSel 0x022C |
| #define B16Gbl_gfx3DCoreClkCtrl_ClkSel 0x022C |
| #define LSb32Gbl_gfx3DCoreClkCtrl_ClkSel 7 |
| #define LSb16Gbl_gfx3DCoreClkCtrl_ClkSel 7 |
| #define bGbl_gfx3DCoreClkCtrl_ClkSel 3 |
| #define MSK32Gbl_gfx3DCoreClkCtrl_ClkSel 0x00000380 |
| #define Gbl_gfx3DCoreClkCtrl_ClkSel_d2 0x1 |
| #define Gbl_gfx3DCoreClkCtrl_ClkSel_d4 0x2 |
| #define Gbl_gfx3DCoreClkCtrl_ClkSel_d6 0x3 |
| #define Gbl_gfx3DCoreClkCtrl_ClkSel_d8 0x4 |
| #define Gbl_gfx3DCoreClkCtrl_ClkSel_d12 0x5 |
| #define RA_Gbl_gfx3DSysClkCtrl 0x0230 |
| #define BA_Gbl_gfx3DSysClkCtrl_clkEN 0x0230 |
| #define B16Gbl_gfx3DSysClkCtrl_clkEN 0x0230 |
| #define LSb32Gbl_gfx3DSysClkCtrl_clkEN 0 |
| #define LSb16Gbl_gfx3DSysClkCtrl_clkEN 0 |
| #define bGbl_gfx3DSysClkCtrl_clkEN 1 |
| #define MSK32Gbl_gfx3DSysClkCtrl_clkEN 0x00000001 |
| #define Gbl_gfx3DSysClkCtrl_clkEN_enable 0x1 |
| #define Gbl_gfx3DSysClkCtrl_clkEN_disable 0x0 |
| #define BA_Gbl_gfx3DSysClkCtrl_ClkPllSel 0x0230 |
| #define B16Gbl_gfx3DSysClkCtrl_ClkPllSel 0x0230 |
| #define LSb32Gbl_gfx3DSysClkCtrl_ClkPllSel 1 |
| #define LSb16Gbl_gfx3DSysClkCtrl_ClkPllSel 1 |
| #define bGbl_gfx3DSysClkCtrl_ClkPllSel 3 |
| #define MSK32Gbl_gfx3DSysClkCtrl_ClkPllSel 0x0000000E |
| #define Gbl_gfx3DSysClkCtrl_ClkPllSel_AVPllB4 0x0 |
| #define Gbl_gfx3DSysClkCtrl_ClkPllSel_AVPllB5 0x1 |
| #define Gbl_gfx3DSysClkCtrl_ClkPllSel_AVPllB6 0x2 |
| #define Gbl_gfx3DSysClkCtrl_ClkPllSel_AVPllB7 0x3 |
| #define Gbl_gfx3DSysClkCtrl_ClkPllSel_SYSPll 0x4 |
| #define BA_Gbl_gfx3DSysClkCtrl_ClkPllSwitch 0x0230 |
| #define B16Gbl_gfx3DSysClkCtrl_ClkPllSwitch 0x0230 |
| #define LSb32Gbl_gfx3DSysClkCtrl_ClkPllSwitch 4 |
| #define LSb16Gbl_gfx3DSysClkCtrl_ClkPllSwitch 4 |
| #define bGbl_gfx3DSysClkCtrl_ClkPllSwitch 1 |
| #define MSK32Gbl_gfx3DSysClkCtrl_ClkPllSwitch 0x00000010 |
| #define Gbl_gfx3DSysClkCtrl_ClkPllSwitch_SYSPLL 0x0 |
| #define Gbl_gfx3DSysClkCtrl_ClkPllSwitch_AVPLL 0x1 |
| #define BA_Gbl_gfx3DSysClkCtrl_ClkSwitch 0x0230 |
| #define B16Gbl_gfx3DSysClkCtrl_ClkSwitch 0x0230 |
| #define LSb32Gbl_gfx3DSysClkCtrl_ClkSwitch 5 |
| #define LSb16Gbl_gfx3DSysClkCtrl_ClkSwitch 5 |
| #define bGbl_gfx3DSysClkCtrl_ClkSwitch 1 |
| #define MSK32Gbl_gfx3DSysClkCtrl_ClkSwitch 0x00000020 |
| #define Gbl_gfx3DSysClkCtrl_ClkSwitch_SrcClk 0x0 |
| #define Gbl_gfx3DSysClkCtrl_ClkSwitch_DivClk 0x1 |
| #define BA_Gbl_gfx3DSysClkCtrl_ClkD3Switch 0x0230 |
| #define B16Gbl_gfx3DSysClkCtrl_ClkD3Switch 0x0230 |
| #define LSb32Gbl_gfx3DSysClkCtrl_ClkD3Switch 6 |
| #define LSb16Gbl_gfx3DSysClkCtrl_ClkD3Switch 6 |
| #define bGbl_gfx3DSysClkCtrl_ClkD3Switch 1 |
| #define MSK32Gbl_gfx3DSysClkCtrl_ClkD3Switch 0x00000040 |
| #define Gbl_gfx3DSysClkCtrl_ClkD3Switch_NonDiv3Clk 0x0 |
| #define Gbl_gfx3DSysClkCtrl_ClkD3Switch_Div3Clk 0x1 |
| #define BA_Gbl_gfx3DSysClkCtrl_ClkSel 0x0230 |
| #define B16Gbl_gfx3DSysClkCtrl_ClkSel 0x0230 |
| #define LSb32Gbl_gfx3DSysClkCtrl_ClkSel 7 |
| #define LSb16Gbl_gfx3DSysClkCtrl_ClkSel 7 |
| #define bGbl_gfx3DSysClkCtrl_ClkSel 3 |
| #define MSK32Gbl_gfx3DSysClkCtrl_ClkSel 0x00000380 |
| #define Gbl_gfx3DSysClkCtrl_ClkSel_d2 0x1 |
| #define Gbl_gfx3DSysClkCtrl_ClkSel_d4 0x2 |
| #define Gbl_gfx3DSysClkCtrl_ClkSel_d6 0x3 |
| #define Gbl_gfx3DSysClkCtrl_ClkSel_d8 0x4 |
| #define Gbl_gfx3DSysClkCtrl_ClkSel_d12 0x5 |
| #define RA_Gbl_arcRefClkCtrl 0x0234 |
| #define BA_Gbl_arcRefClkCtrl_clkEN 0x0234 |
| #define B16Gbl_arcRefClkCtrl_clkEN 0x0234 |
| #define LSb32Gbl_arcRefClkCtrl_clkEN 0 |
| #define LSb16Gbl_arcRefClkCtrl_clkEN 0 |
| #define bGbl_arcRefClkCtrl_clkEN 1 |
| #define MSK32Gbl_arcRefClkCtrl_clkEN 0x00000001 |
| #define Gbl_arcRefClkCtrl_clkEN_enable 0x1 |
| #define Gbl_arcRefClkCtrl_clkEN_disable 0x0 |
| #define BA_Gbl_arcRefClkCtrl_ClkPllSel 0x0234 |
| #define B16Gbl_arcRefClkCtrl_ClkPllSel 0x0234 |
| #define LSb32Gbl_arcRefClkCtrl_ClkPllSel 1 |
| #define LSb16Gbl_arcRefClkCtrl_ClkPllSel 1 |
| #define bGbl_arcRefClkCtrl_ClkPllSel 3 |
| #define MSK32Gbl_arcRefClkCtrl_ClkPllSel 0x0000000E |
| #define Gbl_arcRefClkCtrl_ClkPllSel_AVPllB4 0x0 |
| #define Gbl_arcRefClkCtrl_ClkPllSel_AVPllB5 0x1 |
| #define Gbl_arcRefClkCtrl_ClkPllSel_AVPllB6 0x2 |
| #define Gbl_arcRefClkCtrl_ClkPllSel_AVPllB7 0x3 |
| #define Gbl_arcRefClkCtrl_ClkPllSel_SYSPll 0x4 |
| #define BA_Gbl_arcRefClkCtrl_ClkPllSwitch 0x0234 |
| #define B16Gbl_arcRefClkCtrl_ClkPllSwitch 0x0234 |
| #define LSb32Gbl_arcRefClkCtrl_ClkPllSwitch 4 |
| #define LSb16Gbl_arcRefClkCtrl_ClkPllSwitch 4 |
| #define bGbl_arcRefClkCtrl_ClkPllSwitch 1 |
| #define MSK32Gbl_arcRefClkCtrl_ClkPllSwitch 0x00000010 |
| #define Gbl_arcRefClkCtrl_ClkPllSwitch_SYSPLL 0x0 |
| #define Gbl_arcRefClkCtrl_ClkPllSwitch_AVPLL 0x1 |
| #define BA_Gbl_arcRefClkCtrl_ClkSwitch 0x0234 |
| #define B16Gbl_arcRefClkCtrl_ClkSwitch 0x0234 |
| #define LSb32Gbl_arcRefClkCtrl_ClkSwitch 5 |
| #define LSb16Gbl_arcRefClkCtrl_ClkSwitch 5 |
| #define bGbl_arcRefClkCtrl_ClkSwitch 1 |
| #define MSK32Gbl_arcRefClkCtrl_ClkSwitch 0x00000020 |
| #define Gbl_arcRefClkCtrl_ClkSwitch_SrcClk 0x0 |
| #define Gbl_arcRefClkCtrl_ClkSwitch_DivClk 0x1 |
| #define BA_Gbl_arcRefClkCtrl_ClkD3Switch 0x0234 |
| #define B16Gbl_arcRefClkCtrl_ClkD3Switch 0x0234 |
| #define LSb32Gbl_arcRefClkCtrl_ClkD3Switch 6 |
| #define LSb16Gbl_arcRefClkCtrl_ClkD3Switch 6 |
| #define bGbl_arcRefClkCtrl_ClkD3Switch 1 |
| #define MSK32Gbl_arcRefClkCtrl_ClkD3Switch 0x00000040 |
| #define Gbl_arcRefClkCtrl_ClkD3Switch_NonDiv3Clk 0x0 |
| #define Gbl_arcRefClkCtrl_ClkD3Switch_Div3Clk 0x1 |
| #define BA_Gbl_arcRefClkCtrl_ClkSel 0x0234 |
| #define B16Gbl_arcRefClkCtrl_ClkSel 0x0234 |
| #define LSb32Gbl_arcRefClkCtrl_ClkSel 7 |
| #define LSb16Gbl_arcRefClkCtrl_ClkSel 7 |
| #define bGbl_arcRefClkCtrl_ClkSel 3 |
| #define MSK32Gbl_arcRefClkCtrl_ClkSel 0x00000380 |
| #define Gbl_arcRefClkCtrl_ClkSel_d2 0x1 |
| #define Gbl_arcRefClkCtrl_ClkSel_d4 0x2 |
| #define Gbl_arcRefClkCtrl_ClkSel_d6 0x3 |
| #define Gbl_arcRefClkCtrl_ClkSel_d8 0x4 |
| #define Gbl_arcRefClkCtrl_ClkSel_d12 0x5 |
| #define RA_Gbl_vipClkCtrl 0x0238 |
| #define BA_Gbl_vipClkCtrl_clkEN 0x0238 |
| #define B16Gbl_vipClkCtrl_clkEN 0x0238 |
| #define LSb32Gbl_vipClkCtrl_clkEN 0 |
| #define LSb16Gbl_vipClkCtrl_clkEN 0 |
| #define bGbl_vipClkCtrl_clkEN 1 |
| #define MSK32Gbl_vipClkCtrl_clkEN 0x00000001 |
| #define Gbl_vipClkCtrl_clkEN_enable 0x1 |
| #define Gbl_vipClkCtrl_clkEN_disable 0x0 |
| #define BA_Gbl_vipClkCtrl_ClkPllSel 0x0238 |
| #define B16Gbl_vipClkCtrl_ClkPllSel 0x0238 |
| #define LSb32Gbl_vipClkCtrl_ClkPllSel 1 |
| #define LSb16Gbl_vipClkCtrl_ClkPllSel 1 |
| #define bGbl_vipClkCtrl_ClkPllSel 3 |
| #define MSK32Gbl_vipClkCtrl_ClkPllSel 0x0000000E |
| #define Gbl_vipClkCtrl_ClkPllSel_AVPllB4 0x0 |
| #define Gbl_vipClkCtrl_ClkPllSel_AVPllB5 0x1 |
| #define Gbl_vipClkCtrl_ClkPllSel_AVPllB6 0x2 |
| #define Gbl_vipClkCtrl_ClkPllSel_AVPllB7 0x3 |
| #define Gbl_vipClkCtrl_ClkPllSel_SYSPll 0x4 |
| #define BA_Gbl_vipClkCtrl_ClkPllSwitch 0x0238 |
| #define B16Gbl_vipClkCtrl_ClkPllSwitch 0x0238 |
| #define LSb32Gbl_vipClkCtrl_ClkPllSwitch 4 |
| #define LSb16Gbl_vipClkCtrl_ClkPllSwitch 4 |
| #define bGbl_vipClkCtrl_ClkPllSwitch 1 |
| #define MSK32Gbl_vipClkCtrl_ClkPllSwitch 0x00000010 |
| #define Gbl_vipClkCtrl_ClkPllSwitch_SYSPLL 0x0 |
| #define Gbl_vipClkCtrl_ClkPllSwitch_AVPLL 0x1 |
| #define BA_Gbl_vipClkCtrl_ClkSwitch 0x0238 |
| #define B16Gbl_vipClkCtrl_ClkSwitch 0x0238 |
| #define LSb32Gbl_vipClkCtrl_ClkSwitch 5 |
| #define LSb16Gbl_vipClkCtrl_ClkSwitch 5 |
| #define bGbl_vipClkCtrl_ClkSwitch 1 |
| #define MSK32Gbl_vipClkCtrl_ClkSwitch 0x00000020 |
| #define Gbl_vipClkCtrl_ClkSwitch_SrcClk 0x0 |
| #define Gbl_vipClkCtrl_ClkSwitch_DivClk 0x1 |
| #define BA_Gbl_vipClkCtrl_ClkD3Switch 0x0238 |
| #define B16Gbl_vipClkCtrl_ClkD3Switch 0x0238 |
| #define LSb32Gbl_vipClkCtrl_ClkD3Switch 6 |
| #define LSb16Gbl_vipClkCtrl_ClkD3Switch 6 |
| #define bGbl_vipClkCtrl_ClkD3Switch 1 |
| #define MSK32Gbl_vipClkCtrl_ClkD3Switch 0x00000040 |
| #define Gbl_vipClkCtrl_ClkD3Switch_NonDiv3Clk 0x0 |
| #define Gbl_vipClkCtrl_ClkD3Switch_Div3Clk 0x1 |
| #define BA_Gbl_vipClkCtrl_ClkSel 0x0238 |
| #define B16Gbl_vipClkCtrl_ClkSel 0x0238 |
| #define LSb32Gbl_vipClkCtrl_ClkSel 7 |
| #define LSb16Gbl_vipClkCtrl_ClkSel 7 |
| #define bGbl_vipClkCtrl_ClkSel 3 |
| #define MSK32Gbl_vipClkCtrl_ClkSel 0x00000380 |
| #define Gbl_vipClkCtrl_ClkSel_d2 0x1 |
| #define Gbl_vipClkCtrl_ClkSel_d4 0x2 |
| #define Gbl_vipClkCtrl_ClkSel_d6 0x3 |
| #define Gbl_vipClkCtrl_ClkSel_d8 0x4 |
| #define Gbl_vipClkCtrl_ClkSel_d12 0x5 |
| #define RA_Gbl_sdioXinClkCtrl 0x023C |
| #define BA_Gbl_sdioXinClkCtrl_ClkEN 0x023C |
| #define B16Gbl_sdioXinClkCtrl_ClkEN 0x023C |
| #define LSb32Gbl_sdioXinClkCtrl_ClkEN 0 |
| #define LSb16Gbl_sdioXinClkCtrl_ClkEN 0 |
| #define bGbl_sdioXinClkCtrl_ClkEN 1 |
| #define MSK32Gbl_sdioXinClkCtrl_ClkEN 0x00000001 |
| #define Gbl_sdioXinClkCtrl_ClkEN_enable 0x1 |
| #define Gbl_sdioXinClkCtrl_ClkEN_disable 0x0 |
| #define BA_Gbl_sdioXinClkCtrl_ClkPllSel 0x023C |
| #define B16Gbl_sdioXinClkCtrl_ClkPllSel 0x023C |
| #define LSb32Gbl_sdioXinClkCtrl_ClkPllSel 1 |
| #define LSb16Gbl_sdioXinClkCtrl_ClkPllSel 1 |
| #define bGbl_sdioXinClkCtrl_ClkPllSel 3 |
| #define MSK32Gbl_sdioXinClkCtrl_ClkPllSel 0x0000000E |
| #define Gbl_sdioXinClkCtrl_ClkPllSel_AVPllB4 0x0 |
| #define Gbl_sdioXinClkCtrl_ClkPllSel_AVPllB5 0x1 |
| #define Gbl_sdioXinClkCtrl_ClkPllSel_AVPllB6 0x2 |
| #define Gbl_sdioXinClkCtrl_ClkPllSel_AVPllB7 0x3 |
| #define Gbl_sdioXinClkCtrl_ClkPllSel_SYSPll 0x4 |
| #define BA_Gbl_sdioXinClkCtrl_ClkPllSwitch 0x023C |
| #define B16Gbl_sdioXinClkCtrl_ClkPllSwitch 0x023C |
| #define LSb32Gbl_sdioXinClkCtrl_ClkPllSwitch 4 |
| #define LSb16Gbl_sdioXinClkCtrl_ClkPllSwitch 4 |
| #define bGbl_sdioXinClkCtrl_ClkPllSwitch 1 |
| #define MSK32Gbl_sdioXinClkCtrl_ClkPllSwitch 0x00000010 |
| #define Gbl_sdioXinClkCtrl_ClkPllSwitch_SYSPLL 0x0 |
| #define Gbl_sdioXinClkCtrl_ClkPllSwitch_AVPLL 0x1 |
| #define BA_Gbl_sdioXinClkCtrl_ClkSwitch 0x023C |
| #define B16Gbl_sdioXinClkCtrl_ClkSwitch 0x023C |
| #define LSb32Gbl_sdioXinClkCtrl_ClkSwitch 5 |
| #define LSb16Gbl_sdioXinClkCtrl_ClkSwitch 5 |
| #define bGbl_sdioXinClkCtrl_ClkSwitch 1 |
| #define MSK32Gbl_sdioXinClkCtrl_ClkSwitch 0x00000020 |
| #define Gbl_sdioXinClkCtrl_ClkSwitch_SrcClk 0x0 |
| #define Gbl_sdioXinClkCtrl_ClkSwitch_DivClk 0x1 |
| #define BA_Gbl_sdioXinClkCtrl_ClkD3Switch 0x023C |
| #define B16Gbl_sdioXinClkCtrl_ClkD3Switch 0x023C |
| #define LSb32Gbl_sdioXinClkCtrl_ClkD3Switch 6 |
| #define LSb16Gbl_sdioXinClkCtrl_ClkD3Switch 6 |
| #define bGbl_sdioXinClkCtrl_ClkD3Switch 1 |
| #define MSK32Gbl_sdioXinClkCtrl_ClkD3Switch 0x00000040 |
| #define Gbl_sdioXinClkCtrl_ClkD3Switch_NonDiv3Clk 0x0 |
| #define Gbl_sdioXinClkCtrl_ClkD3Switch_Div3Clk 0x1 |
| #define BA_Gbl_sdioXinClkCtrl_ClkSel 0x023C |
| #define B16Gbl_sdioXinClkCtrl_ClkSel 0x023C |
| #define LSb32Gbl_sdioXinClkCtrl_ClkSel 7 |
| #define LSb16Gbl_sdioXinClkCtrl_ClkSel 7 |
| #define bGbl_sdioXinClkCtrl_ClkSel 3 |
| #define MSK32Gbl_sdioXinClkCtrl_ClkSel 0x00000380 |
| #define Gbl_sdioXinClkCtrl_ClkSel_d2 0x1 |
| #define Gbl_sdioXinClkCtrl_ClkSel_d4 0x2 |
| #define Gbl_sdioXinClkCtrl_ClkSel_d6 0x3 |
| #define Gbl_sdioXinClkCtrl_ClkSel_d8 0x4 |
| #define Gbl_sdioXinClkCtrl_ClkSel_d12 0x5 |
| #define RA_Gbl_sdio1XinClkCtrl 0x0240 |
| #define BA_Gbl_sdio1XinClkCtrl_ClkEN 0x0240 |
| #define B16Gbl_sdio1XinClkCtrl_ClkEN 0x0240 |
| #define LSb32Gbl_sdio1XinClkCtrl_ClkEN 0 |
| #define LSb16Gbl_sdio1XinClkCtrl_ClkEN 0 |
| #define bGbl_sdio1XinClkCtrl_ClkEN 1 |
| #define MSK32Gbl_sdio1XinClkCtrl_ClkEN 0x00000001 |
| #define Gbl_sdio1XinClkCtrl_ClkEN_enable 0x1 |
| #define Gbl_sdio1XinClkCtrl_ClkEN_disable 0x0 |
| #define BA_Gbl_sdio1XinClkCtrl_ClkPllSel 0x0240 |
| #define B16Gbl_sdio1XinClkCtrl_ClkPllSel 0x0240 |
| #define LSb32Gbl_sdio1XinClkCtrl_ClkPllSel 1 |
| #define LSb16Gbl_sdio1XinClkCtrl_ClkPllSel 1 |
| #define bGbl_sdio1XinClkCtrl_ClkPllSel 3 |
| #define MSK32Gbl_sdio1XinClkCtrl_ClkPllSel 0x0000000E |
| #define Gbl_sdio1XinClkCtrl_ClkPllSel_AVPllB4 0x0 |
| #define Gbl_sdio1XinClkCtrl_ClkPllSel_AVPllB5 0x1 |
| #define Gbl_sdio1XinClkCtrl_ClkPllSel_AVPllB6 0x2 |
| #define Gbl_sdio1XinClkCtrl_ClkPllSel_AVPllB7 0x3 |
| #define Gbl_sdio1XinClkCtrl_ClkPllSel_SYSPll 0x4 |
| #define BA_Gbl_sdio1XinClkCtrl_ClkPllSwitch 0x0240 |
| #define B16Gbl_sdio1XinClkCtrl_ClkPllSwitch 0x0240 |
| #define LSb32Gbl_sdio1XinClkCtrl_ClkPllSwitch 4 |
| #define LSb16Gbl_sdio1XinClkCtrl_ClkPllSwitch 4 |
| #define bGbl_sdio1XinClkCtrl_ClkPllSwitch 1 |
| #define MSK32Gbl_sdio1XinClkCtrl_ClkPllSwitch 0x00000010 |
| #define Gbl_sdio1XinClkCtrl_ClkPllSwitch_SYSPLL 0x0 |
| #define Gbl_sdio1XinClkCtrl_ClkPllSwitch_AVPLL 0x1 |
| #define BA_Gbl_sdio1XinClkCtrl_ClkSwitch 0x0240 |
| #define B16Gbl_sdio1XinClkCtrl_ClkSwitch 0x0240 |
| #define LSb32Gbl_sdio1XinClkCtrl_ClkSwitch 5 |
| #define LSb16Gbl_sdio1XinClkCtrl_ClkSwitch 5 |
| #define bGbl_sdio1XinClkCtrl_ClkSwitch 1 |
| #define MSK32Gbl_sdio1XinClkCtrl_ClkSwitch 0x00000020 |
| #define Gbl_sdio1XinClkCtrl_ClkSwitch_SrcClk 0x0 |
| #define Gbl_sdio1XinClkCtrl_ClkSwitch_DivClk 0x1 |
| #define BA_Gbl_sdio1XinClkCtrl_ClkD3Switch 0x0240 |
| #define B16Gbl_sdio1XinClkCtrl_ClkD3Switch 0x0240 |
| #define LSb32Gbl_sdio1XinClkCtrl_ClkD3Switch 6 |
| #define LSb16Gbl_sdio1XinClkCtrl_ClkD3Switch 6 |
| #define bGbl_sdio1XinClkCtrl_ClkD3Switch 1 |
| #define MSK32Gbl_sdio1XinClkCtrl_ClkD3Switch 0x00000040 |
| #define Gbl_sdio1XinClkCtrl_ClkD3Switch_NonDiv3Clk 0x0 |
| #define Gbl_sdio1XinClkCtrl_ClkD3Switch_Div3Clk 0x1 |
| #define BA_Gbl_sdio1XinClkCtrl_ClkSel 0x0240 |
| #define B16Gbl_sdio1XinClkCtrl_ClkSel 0x0240 |
| #define LSb32Gbl_sdio1XinClkCtrl_ClkSel 7 |
| #define LSb16Gbl_sdio1XinClkCtrl_ClkSel 7 |
| #define bGbl_sdio1XinClkCtrl_ClkSel 3 |
| #define MSK32Gbl_sdio1XinClkCtrl_ClkSel 0x00000380 |
| #define Gbl_sdio1XinClkCtrl_ClkSel_d2 0x1 |
| #define Gbl_sdio1XinClkCtrl_ClkSel_d4 0x2 |
| #define Gbl_sdio1XinClkCtrl_ClkSel_d6 0x3 |
| #define Gbl_sdio1XinClkCtrl_ClkSel_d8 0x4 |
| #define Gbl_sdio1XinClkCtrl_ClkSel_d12 0x5 |
| #define RA_Gbl_gfx3DExtraClkCtrl 0x0244 |
| #define BA_Gbl_gfx3DExtraClkCtrl_ClkEN 0x0244 |
| #define B16Gbl_gfx3DExtraClkCtrl_ClkEN 0x0244 |
| #define LSb32Gbl_gfx3DExtraClkCtrl_ClkEN 0 |
| #define LSb16Gbl_gfx3DExtraClkCtrl_ClkEN 0 |
| #define bGbl_gfx3DExtraClkCtrl_ClkEN 1 |
| #define MSK32Gbl_gfx3DExtraClkCtrl_ClkEN 0x00000001 |
| #define Gbl_gfx3DExtraClkCtrl_ClkEN_enable 0x1 |
| #define Gbl_gfx3DExtraClkCtrl_ClkEN_disable 0x0 |
| #define BA_Gbl_gfx3DExtraClkCtrl_ClkPllSel 0x0244 |
| #define B16Gbl_gfx3DExtraClkCtrl_ClkPllSel 0x0244 |
| #define LSb32Gbl_gfx3DExtraClkCtrl_ClkPllSel 1 |
| #define LSb16Gbl_gfx3DExtraClkCtrl_ClkPllSel 1 |
| #define bGbl_gfx3DExtraClkCtrl_ClkPllSel 3 |
| #define MSK32Gbl_gfx3DExtraClkCtrl_ClkPllSel 0x0000000E |
| #define Gbl_gfx3DExtraClkCtrl_ClkPllSel_AVPllB4 0x0 |
| #define Gbl_gfx3DExtraClkCtrl_ClkPllSel_AVPllB5 0x1 |
| #define Gbl_gfx3DExtraClkCtrl_ClkPllSel_AVPllB6 0x2 |
| #define Gbl_gfx3DExtraClkCtrl_ClkPllSel_AVPllB7 0x3 |
| #define Gbl_gfx3DExtraClkCtrl_ClkPllSel_SYSPll 0x4 |
| #define BA_Gbl_gfx3DExtraClkCtrl_ClkPllSwitch 0x0244 |
| #define B16Gbl_gfx3DExtraClkCtrl_ClkPllSwitch 0x0244 |
| #define LSb32Gbl_gfx3DExtraClkCtrl_ClkPllSwitch 4 |
| #define LSb16Gbl_gfx3DExtraClkCtrl_ClkPllSwitch 4 |
| #define bGbl_gfx3DExtraClkCtrl_ClkPllSwitch 1 |
| #define MSK32Gbl_gfx3DExtraClkCtrl_ClkPllSwitch 0x00000010 |
| #define Gbl_gfx3DExtraClkCtrl_ClkPllSwitch_SYSPLL 0x0 |
| #define Gbl_gfx3DExtraClkCtrl_ClkPllSwitch_AVPLL 0x1 |
| #define BA_Gbl_gfx3DExtraClkCtrl_ClkSwitch 0x0244 |
| #define B16Gbl_gfx3DExtraClkCtrl_ClkSwitch 0x0244 |
| #define LSb32Gbl_gfx3DExtraClkCtrl_ClkSwitch 5 |
| #define LSb16Gbl_gfx3DExtraClkCtrl_ClkSwitch 5 |
| #define bGbl_gfx3DExtraClkCtrl_ClkSwitch 1 |
| #define MSK32Gbl_gfx3DExtraClkCtrl_ClkSwitch 0x00000020 |
| #define Gbl_gfx3DExtraClkCtrl_ClkSwitch_SrcClk 0x0 |
| #define Gbl_gfx3DExtraClkCtrl_ClkSwitch_DivClk 0x1 |
| #define BA_Gbl_gfx3DExtraClkCtrl_ClkD3Switch 0x0244 |
| #define B16Gbl_gfx3DExtraClkCtrl_ClkD3Switch 0x0244 |
| #define LSb32Gbl_gfx3DExtraClkCtrl_ClkD3Switch 6 |
| #define LSb16Gbl_gfx3DExtraClkCtrl_ClkD3Switch 6 |
| #define bGbl_gfx3DExtraClkCtrl_ClkD3Switch 1 |
| #define MSK32Gbl_gfx3DExtraClkCtrl_ClkD3Switch 0x00000040 |
| #define Gbl_gfx3DExtraClkCtrl_ClkD3Switch_NonDiv3Clk 0x0 |
| #define Gbl_gfx3DExtraClkCtrl_ClkD3Switch_Div3Clk 0x1 |
| #define BA_Gbl_gfx3DExtraClkCtrl_ClkSel 0x0244 |
| #define B16Gbl_gfx3DExtraClkCtrl_ClkSel 0x0244 |
| #define LSb32Gbl_gfx3DExtraClkCtrl_ClkSel 7 |
| #define LSb16Gbl_gfx3DExtraClkCtrl_ClkSel 7 |
| #define bGbl_gfx3DExtraClkCtrl_ClkSel 3 |
| #define MSK32Gbl_gfx3DExtraClkCtrl_ClkSel 0x00000380 |
| #define Gbl_gfx3DExtraClkCtrl_ClkSel_d2 0x1 |
| #define Gbl_gfx3DExtraClkCtrl_ClkSel_d4 0x2 |
| #define Gbl_gfx3DExtraClkCtrl_ClkSel_d6 0x3 |
| #define Gbl_gfx3DExtraClkCtrl_ClkSel_d8 0x4 |
| #define Gbl_gfx3DExtraClkCtrl_ClkSel_d12 0x5 |
| #define RA_Gbl_gfx3DReset 0x0248 |
| #define BA_Gbl_gfx3DReset_SyncReset 0x0248 |
| #define B16Gbl_gfx3DReset_SyncReset 0x0248 |
| #define LSb32Gbl_gfx3DReset_SyncReset 0 |
| #define LSb16Gbl_gfx3DReset_SyncReset 0 |
| #define bGbl_gfx3DReset_SyncReset 1 |
| #define MSK32Gbl_gfx3DReset_SyncReset 0x00000001 |
| #define Gbl_gfx3DReset_SyncReset_assert 0x1 |
| #define Gbl_gfx3DReset_SyncReset_deassert 0x0 |
| #define RA_Gbl_gc360ClkCtrl 0x024C |
| #define BA_Gbl_gc360ClkCtrl_ClkEN 0x024C |
| #define B16Gbl_gc360ClkCtrl_ClkEN 0x024C |
| #define LSb32Gbl_gc360ClkCtrl_ClkEN 0 |
| #define LSb16Gbl_gc360ClkCtrl_ClkEN 0 |
| #define bGbl_gc360ClkCtrl_ClkEN 1 |
| #define MSK32Gbl_gc360ClkCtrl_ClkEN 0x00000001 |
| #define Gbl_gc360ClkCtrl_ClkEN_enable 0x1 |
| #define Gbl_gc360ClkCtrl_ClkEN_disable 0x0 |
| #define BA_Gbl_gc360ClkCtrl_ClkPllSel 0x024C |
| #define B16Gbl_gc360ClkCtrl_ClkPllSel 0x024C |
| #define LSb32Gbl_gc360ClkCtrl_ClkPllSel 1 |
| #define LSb16Gbl_gc360ClkCtrl_ClkPllSel 1 |
| #define bGbl_gc360ClkCtrl_ClkPllSel 3 |
| #define MSK32Gbl_gc360ClkCtrl_ClkPllSel 0x0000000E |
| #define Gbl_gc360ClkCtrl_ClkPllSel_AVPllB4 0x0 |
| #define Gbl_gc360ClkCtrl_ClkPllSel_AVPllB5 0x1 |
| #define Gbl_gc360ClkCtrl_ClkPllSel_AVPllB6 0x2 |
| #define Gbl_gc360ClkCtrl_ClkPllSel_AVPllB7 0x3 |
| #define Gbl_gc360ClkCtrl_ClkPllSel_SYSPll 0x4 |
| #define BA_Gbl_gc360ClkCtrl_ClkPllSwitch 0x024C |
| #define B16Gbl_gc360ClkCtrl_ClkPllSwitch 0x024C |
| #define LSb32Gbl_gc360ClkCtrl_ClkPllSwitch 4 |
| #define LSb16Gbl_gc360ClkCtrl_ClkPllSwitch 4 |
| #define bGbl_gc360ClkCtrl_ClkPllSwitch 1 |
| #define MSK32Gbl_gc360ClkCtrl_ClkPllSwitch 0x00000010 |
| #define Gbl_gc360ClkCtrl_ClkPllSwitch_SYSPLL 0x0 |
| #define Gbl_gc360ClkCtrl_ClkPllSwitch_AVPLL 0x1 |
| #define BA_Gbl_gc360ClkCtrl_ClkSwitch 0x024C |
| #define B16Gbl_gc360ClkCtrl_ClkSwitch 0x024C |
| #define LSb32Gbl_gc360ClkCtrl_ClkSwitch 5 |
| #define LSb16Gbl_gc360ClkCtrl_ClkSwitch 5 |
| #define bGbl_gc360ClkCtrl_ClkSwitch 1 |
| #define MSK32Gbl_gc360ClkCtrl_ClkSwitch 0x00000020 |
| #define Gbl_gc360ClkCtrl_ClkSwitch_SrcClk 0x0 |
| #define Gbl_gc360ClkCtrl_ClkSwitch_DivClk 0x1 |
| #define BA_Gbl_gc360ClkCtrl_ClkD3Switch 0x024C |
| #define B16Gbl_gc360ClkCtrl_ClkD3Switch 0x024C |
| #define LSb32Gbl_gc360ClkCtrl_ClkD3Switch 6 |
| #define LSb16Gbl_gc360ClkCtrl_ClkD3Switch 6 |
| #define bGbl_gc360ClkCtrl_ClkD3Switch 1 |
| #define MSK32Gbl_gc360ClkCtrl_ClkD3Switch 0x00000040 |
| #define Gbl_gc360ClkCtrl_ClkD3Switch_NonDiv3Clk 0x0 |
| #define Gbl_gc360ClkCtrl_ClkD3Switch_Div3Clk 0x1 |
| #define BA_Gbl_gc360ClkCtrl_ClkSel 0x024C |
| #define B16Gbl_gc360ClkCtrl_ClkSel 0x024C |
| #define LSb32Gbl_gc360ClkCtrl_ClkSel 7 |
| #define LSb16Gbl_gc360ClkCtrl_ClkSel 7 |
| #define bGbl_gc360ClkCtrl_ClkSel 3 |
| #define MSK32Gbl_gc360ClkCtrl_ClkSel 0x00000380 |
| #define Gbl_gc360ClkCtrl_ClkSel_d2 0x1 |
| #define Gbl_gc360ClkCtrl_ClkSel_d4 0x2 |
| #define Gbl_gc360ClkCtrl_ClkSel_d6 0x3 |
| #define Gbl_gc360ClkCtrl_ClkSel_d8 0x4 |
| #define Gbl_gc360ClkCtrl_ClkSel_d12 0x5 |
| #define RA_Gbl_sdioDllMstRef 0x0250 |
| #define BA_Gbl_sdioDllMstRef_ClkEN 0x0250 |
| #define B16Gbl_sdioDllMstRef_ClkEN 0x0250 |
| #define LSb32Gbl_sdioDllMstRef_ClkEN 0 |
| #define LSb16Gbl_sdioDllMstRef_ClkEN 0 |
| #define bGbl_sdioDllMstRef_ClkEN 1 |
| #define MSK32Gbl_sdioDllMstRef_ClkEN 0x00000001 |
| #define Gbl_sdioDllMstRef_ClkEN_enable 0x1 |
| #define Gbl_sdioDllMstRef_ClkEN_disable 0x0 |
| #define BA_Gbl_sdioDllMstRef_ClkPllSel 0x0250 |
| #define B16Gbl_sdioDllMstRef_ClkPllSel 0x0250 |
| #define LSb32Gbl_sdioDllMstRef_ClkPllSel 1 |
| #define LSb16Gbl_sdioDllMstRef_ClkPllSel 1 |
| #define bGbl_sdioDllMstRef_ClkPllSel 3 |
| #define MSK32Gbl_sdioDllMstRef_ClkPllSel 0x0000000E |
| #define Gbl_sdioDllMstRef_ClkPllSel_AVPllB4 0x0 |
| #define Gbl_sdioDllMstRef_ClkPllSel_AVPllB5 0x1 |
| #define Gbl_sdioDllMstRef_ClkPllSel_AVPllB6 0x2 |
| #define Gbl_sdioDllMstRef_ClkPllSel_AVPllB7 0x3 |
| #define Gbl_sdioDllMstRef_ClkPllSel_SYSPll 0x4 |
| #define BA_Gbl_sdioDllMstRef_ClkPllSwitch 0x0250 |
| #define B16Gbl_sdioDllMstRef_ClkPllSwitch 0x0250 |
| #define LSb32Gbl_sdioDllMstRef_ClkPllSwitch 4 |
| #define LSb16Gbl_sdioDllMstRef_ClkPllSwitch 4 |
| #define bGbl_sdioDllMstRef_ClkPllSwitch 1 |
| #define MSK32Gbl_sdioDllMstRef_ClkPllSwitch 0x00000010 |
| #define Gbl_sdioDllMstRef_ClkPllSwitch_SYSPLL 0x0 |
| #define Gbl_sdioDllMstRef_ClkPllSwitch_AVPLL 0x1 |
| #define BA_Gbl_sdioDllMstRef_ClkSwitch 0x0250 |
| #define B16Gbl_sdioDllMstRef_ClkSwitch 0x0250 |
| #define LSb32Gbl_sdioDllMstRef_ClkSwitch 5 |
| #define LSb16Gbl_sdioDllMstRef_ClkSwitch 5 |
| #define bGbl_sdioDllMstRef_ClkSwitch 1 |
| #define MSK32Gbl_sdioDllMstRef_ClkSwitch 0x00000020 |
| #define Gbl_sdioDllMstRef_ClkSwitch_SrcClk 0x0 |
| #define Gbl_sdioDllMstRef_ClkSwitch_DivClk 0x1 |
| #define BA_Gbl_sdioDllMstRef_ClkD3Switch 0x0250 |
| #define B16Gbl_sdioDllMstRef_ClkD3Switch 0x0250 |
| #define LSb32Gbl_sdioDllMstRef_ClkD3Switch 6 |
| #define LSb16Gbl_sdioDllMstRef_ClkD3Switch 6 |
| #define bGbl_sdioDllMstRef_ClkD3Switch 1 |
| #define MSK32Gbl_sdioDllMstRef_ClkD3Switch 0x00000040 |
| #define Gbl_sdioDllMstRef_ClkD3Switch_NonDiv3Clk 0x0 |
| #define Gbl_sdioDllMstRef_ClkD3Switch_Div3Clk 0x1 |
| #define BA_Gbl_sdioDllMstRef_ClkSel 0x0250 |
| #define B16Gbl_sdioDllMstRef_ClkSel 0x0250 |
| #define LSb32Gbl_sdioDllMstRef_ClkSel 7 |
| #define LSb16Gbl_sdioDllMstRef_ClkSel 7 |
| #define bGbl_sdioDllMstRef_ClkSel 3 |
| #define MSK32Gbl_sdioDllMstRef_ClkSel 0x00000380 |
| #define Gbl_sdioDllMstRef_ClkSel_d2 0x1 |
| #define Gbl_sdioDllMstRef_ClkSel_d4 0x2 |
| #define Gbl_sdioDllMstRef_ClkSel_d6 0x3 |
| #define Gbl_sdioDllMstRef_ClkSel_d8 0x4 |
| #define Gbl_sdioDllMstRef_ClkSel_d12 0x5 |
| #define RA_Gbl_sdioDllMstCtrl 0x0254 |
| #define BA_Gbl_sdioDllMstCtrl_PH_SEL1 0x0254 |
| #define B16Gbl_sdioDllMstCtrl_PH_SEL1 0x0254 |
| #define LSb32Gbl_sdioDllMstCtrl_PH_SEL1 0 |
| #define LSb16Gbl_sdioDllMstCtrl_PH_SEL1 0 |
| #define bGbl_sdioDllMstCtrl_PH_SEL1 5 |
| #define MSK32Gbl_sdioDllMstCtrl_PH_SEL1 0x0000001F |
| #define BA_Gbl_sdioDllMstCtrl_PH_SEL2 0x0254 |
| #define B16Gbl_sdioDllMstCtrl_PH_SEL2 0x0254 |
| #define LSb32Gbl_sdioDllMstCtrl_PH_SEL2 5 |
| #define LSb16Gbl_sdioDllMstCtrl_PH_SEL2 5 |
| #define bGbl_sdioDllMstCtrl_PH_SEL2 5 |
| #define MSK32Gbl_sdioDllMstCtrl_PH_SEL2 0x000003E0 |
| #define BA_Gbl_sdioDllMstCtrl_PH_SEL3 0x0255 |
| #define B16Gbl_sdioDllMstCtrl_PH_SEL3 0x0254 |
| #define LSb32Gbl_sdioDllMstCtrl_PH_SEL3 10 |
| #define LSb16Gbl_sdioDllMstCtrl_PH_SEL3 10 |
| #define bGbl_sdioDllMstCtrl_PH_SEL3 5 |
| #define MSK32Gbl_sdioDllMstCtrl_PH_SEL3 0x00007C00 |
| #define BA_Gbl_sdioDllMstCtrl_PH_SEL4 0x0255 |
| #define B16Gbl_sdioDllMstCtrl_PH_SEL4 0x0254 |
| #define LSb32Gbl_sdioDllMstCtrl_PH_SEL4 15 |
| #define LSb16Gbl_sdioDllMstCtrl_PH_SEL4 15 |
| #define bGbl_sdioDllMstCtrl_PH_SEL4 5 |
| #define MSK32Gbl_sdioDllMstCtrl_PH_SEL4 0x000F8000 |
| #define BA_Gbl_sdioDllMstCtrl_AUTO_UPDATE_EN 0x0256 |
| #define B16Gbl_sdioDllMstCtrl_AUTO_UPDATE_EN 0x0256 |
| #define LSb32Gbl_sdioDllMstCtrl_AUTO_UPDATE_EN 20 |
| #define LSb16Gbl_sdioDllMstCtrl_AUTO_UPDATE_EN 4 |
| #define bGbl_sdioDllMstCtrl_AUTO_UPDATE_EN 1 |
| #define MSK32Gbl_sdioDllMstCtrl_AUTO_UPDATE_EN 0x00100000 |
| #define BA_Gbl_sdioDllMstCtrl_UPDATE_EN 0x0256 |
| #define B16Gbl_sdioDllMstCtrl_UPDATE_EN 0x0256 |
| #define LSb32Gbl_sdioDllMstCtrl_UPDATE_EN 21 |
| #define LSb16Gbl_sdioDllMstCtrl_UPDATE_EN 5 |
| #define bGbl_sdioDllMstCtrl_UPDATE_EN 1 |
| #define MSK32Gbl_sdioDllMstCtrl_UPDATE_EN 0x00200000 |
| #define BA_Gbl_sdioDllMstCtrl_RESET 0x0256 |
| #define B16Gbl_sdioDllMstCtrl_RESET 0x0256 |
| #define LSb32Gbl_sdioDllMstCtrl_RESET 22 |
| #define LSb16Gbl_sdioDllMstCtrl_RESET 6 |
| #define bGbl_sdioDllMstCtrl_RESET 1 |
| #define MSK32Gbl_sdioDllMstCtrl_RESET 0x00400000 |
| #define BA_Gbl_sdioDllMstCtrl_GAIN2X 0x0256 |
| #define B16Gbl_sdioDllMstCtrl_GAIN2X 0x0256 |
| #define LSb32Gbl_sdioDllMstCtrl_GAIN2X 23 |
| #define LSb16Gbl_sdioDllMstCtrl_GAIN2X 7 |
| #define bGbl_sdioDllMstCtrl_GAIN2X 1 |
| #define MSK32Gbl_sdioDllMstCtrl_GAIN2X 0x00800000 |
| #define BA_Gbl_sdioDllMstCtrl_TEST_EN 0x0257 |
| #define B16Gbl_sdioDllMstCtrl_TEST_EN 0x0256 |
| #define LSb32Gbl_sdioDllMstCtrl_TEST_EN 24 |
| #define LSb16Gbl_sdioDllMstCtrl_TEST_EN 8 |
| #define bGbl_sdioDllMstCtrl_TEST_EN 1 |
| #define MSK32Gbl_sdioDllMstCtrl_TEST_EN 0x01000000 |
| #define BA_Gbl_sdioDllMstCtrl_BYPASS_EN 0x0257 |
| #define B16Gbl_sdioDllMstCtrl_BYPASS_EN 0x0256 |
| #define LSb32Gbl_sdioDllMstCtrl_BYPASS_EN 25 |
| #define LSb16Gbl_sdioDllMstCtrl_BYPASS_EN 9 |
| #define bGbl_sdioDllMstCtrl_BYPASS_EN 1 |
| #define MSK32Gbl_sdioDllMstCtrl_BYPASS_EN 0x02000000 |
| #define RA_Gbl_sdioDllMstCtrl1 0x0258 |
| #define BA_Gbl_sdioDllMstCtrl_DELAY_TEST 0x0258 |
| #define B16Gbl_sdioDllMstCtrl_DELAY_TEST 0x0258 |
| #define LSb32Gbl_sdioDllMstCtrl_DELAY_TEST 0 |
| #define LSb16Gbl_sdioDllMstCtrl_DELAY_TEST 0 |
| #define bGbl_sdioDllMstCtrl_DELAY_TEST 9 |
| #define MSK32Gbl_sdioDllMstCtrl_DELAY_TEST 0x000001FF |
| #define BA_Gbl_sdioDllMstCtrl_RESERVE 0x0259 |
| #define B16Gbl_sdioDllMstCtrl_RESERVE 0x0258 |
| #define LSb32Gbl_sdioDllMstCtrl_RESERVE 9 |
| #define LSb16Gbl_sdioDllMstCtrl_RESERVE 9 |
| #define bGbl_sdioDllMstCtrl_RESERVE 5 |
| #define MSK32Gbl_sdioDllMstCtrl_RESERVE 0x00003E00 |
| #define RA_Gbl_sdioDllMstStatus 0x025C |
| #define BA_Gbl_sdioDllMstStatus_DELAY_CTRL2 0x025C |
| #define B16Gbl_sdioDllMstStatus_DELAY_CTRL2 0x025C |
| #define LSb32Gbl_sdioDllMstStatus_DELAY_CTRL2 0 |
| #define LSb16Gbl_sdioDllMstStatus_DELAY_CTRL2 0 |
| #define bGbl_sdioDllMstStatus_DELAY_CTRL2 9 |
| #define MSK32Gbl_sdioDllMstStatus_DELAY_CTRL2 0x000001FF |
| #define BA_Gbl_sdioDllMstStatus_DELAY_CTRL3 0x025D |
| #define B16Gbl_sdioDllMstStatus_DELAY_CTRL3 0x025C |
| #define LSb32Gbl_sdioDllMstStatus_DELAY_CTRL3 9 |
| #define LSb16Gbl_sdioDllMstStatus_DELAY_CTRL3 9 |
| #define bGbl_sdioDllMstStatus_DELAY_CTRL3 9 |
| #define MSK32Gbl_sdioDllMstStatus_DELAY_CTRL3 0x0003FE00 |
| #define BA_Gbl_sdioDllMstStatus_DELAY_CTRL4 0x025E |
| #define B16Gbl_sdioDllMstStatus_DELAY_CTRL4 0x025E |
| #define LSb32Gbl_sdioDllMstStatus_DELAY_CTRL4 18 |
| #define LSb16Gbl_sdioDllMstStatus_DELAY_CTRL4 2 |
| #define bGbl_sdioDllMstStatus_DELAY_CTRL4 9 |
| #define MSK32Gbl_sdioDllMstStatus_DELAY_CTRL4 0x07FC0000 |
| #define BA_Gbl_sdioDllMstStatus_PRE_LOCK 0x025F |
| #define B16Gbl_sdioDllMstStatus_PRE_LOCK 0x025E |
| #define LSb32Gbl_sdioDllMstStatus_PRE_LOCK 27 |
| #define LSb16Gbl_sdioDllMstStatus_PRE_LOCK 11 |
| #define bGbl_sdioDllMstStatus_PRE_LOCK 1 |
| #define MSK32Gbl_sdioDllMstStatus_PRE_LOCK 0x08000000 |
| #define BA_Gbl_sdioDllMstStatus_DLL_LOCK 0x025F |
| #define B16Gbl_sdioDllMstStatus_DLL_LOCK 0x025E |
| #define LSb32Gbl_sdioDllMstStatus_DLL_LOCK 28 |
| #define LSb16Gbl_sdioDllMstStatus_DLL_LOCK 12 |
| #define bGbl_sdioDllMstStatus_DLL_LOCK 1 |
| #define MSK32Gbl_sdioDllMstStatus_DLL_LOCK 0x10000000 |
| #define RA_Gbl_sdioDllMstStatus1 0x0260 |
| #define BA_Gbl_sdioDllMstStatus_DELAY_OUT 0x0260 |
| #define B16Gbl_sdioDllMstStatus_DELAY_OUT 0x0260 |
| #define LSb32Gbl_sdioDllMstStatus_DELAY_OUT 0 |
| #define LSb16Gbl_sdioDllMstStatus_DELAY_OUT 0 |
| #define bGbl_sdioDllMstStatus_DELAY_OUT 8 |
| #define MSK32Gbl_sdioDllMstStatus_DELAY_OUT 0x000000FF |
| #define RA_Gbl_sdioPortSel 0x0264 |
| #define BA_Gbl_sdioPortSel_port0 0x0264 |
| #define B16Gbl_sdioPortSel_port0 0x0264 |
| #define LSb32Gbl_sdioPortSel_port0 0 |
| #define LSb16Gbl_sdioPortSel_port0 0 |
| #define bGbl_sdioPortSel_port0 1 |
| #define MSK32Gbl_sdioPortSel_port0 0x00000001 |
| #define BA_Gbl_sdioPortSel_port1 0x0264 |
| #define B16Gbl_sdioPortSel_port1 0x0264 |
| #define LSb32Gbl_sdioPortSel_port1 1 |
| #define LSb16Gbl_sdioPortSel_port1 1 |
| #define bGbl_sdioPortSel_port1 1 |
| #define MSK32Gbl_sdioPortSel_port1 0x00000002 |
| #define RA_Gbl_gc360Reset 0x0268 |
| #define BA_Gbl_gc360Reset_SyncReset 0x0268 |
| #define B16Gbl_gc360Reset_SyncReset 0x0268 |
| #define LSb32Gbl_gc360Reset_SyncReset 0 |
| #define LSb16Gbl_gc360Reset_SyncReset 0 |
| #define bGbl_gc360Reset_SyncReset 1 |
| #define MSK32Gbl_gc360Reset_SyncReset 0x00000001 |
| #define Gbl_gc360Reset_SyncReset_assert 0x1 |
| #define Gbl_gc360Reset_SyncReset_deassert 0x0 |
| #define RA_Gbl_SpdifRxReset 0x026C |
| #define BA_Gbl_SpdifRxReset_SyncReset 0x026C |
| #define B16Gbl_SpdifRxReset_SyncReset 0x026C |
| #define LSb32Gbl_SpdifRxReset_SyncReset 0 |
| #define LSb16Gbl_SpdifRxReset_SyncReset 0 |
| #define bGbl_SpdifRxReset_SyncReset 1 |
| #define MSK32Gbl_SpdifRxReset_SyncReset 0x00000001 |
| #define Gbl_SpdifRxReset_SyncReset_assert 0x1 |
| #define Gbl_SpdifRxReset_SyncReset_deassert 0x0 |
| #define RA_Gbl_gfx3DDisRamClkGate 0x0270 |
| #define BA_Gbl_gfx3DDisRamClkGate_drcg 0x0270 |
| #define B16Gbl_gfx3DDisRamClkGate_drcg 0x0270 |
| #define LSb32Gbl_gfx3DDisRamClkGate_drcg 0 |
| #define LSb16Gbl_gfx3DDisRamClkGate_drcg 0 |
| #define bGbl_gfx3DDisRamClkGate_drcg 1 |
| #define MSK32Gbl_gfx3DDisRamClkGate_drcg 0x00000001 |
| #define Gbl_gfx3DDisRamClkGate_drcg_drcgActive 0x1 |
| #define Gbl_gfx3DDisRamClkGate_drcg_drcgInactive 0x0 |
| #define RA_Gbl_gfx3DResetStatus 0x0274 |
| #define BA_Gbl_gfx3DResetStatus_SyncReset 0x0274 |
| #define B16Gbl_gfx3DResetStatus_SyncReset 0x0274 |
| #define LSb32Gbl_gfx3DResetStatus_SyncReset 0 |
| #define LSb16Gbl_gfx3DResetStatus_SyncReset 0 |
| #define bGbl_gfx3DResetStatus_SyncReset 1 |
| #define MSK32Gbl_gfx3DResetStatus_SyncReset 0x00000001 |
| #define Gbl_gfx3DResetStatus_SyncReset_assert 0x1 |
| #define Gbl_gfx3DResetStatus_SyncReset_deassert 0x0 |
| #define RA_Gbl_gc360DisRCG 0x0278 |
| #define BA_Gbl_gc360DisRCG_drcg 0x0278 |
| #define B16Gbl_gc360DisRCG_drcg 0x0278 |
| #define LSb32Gbl_gc360DisRCG_drcg 0 |
| #define LSb16Gbl_gc360DisRCG_drcg 0 |
| #define bGbl_gc360DisRCG_drcg 1 |
| #define MSK32Gbl_gc360DisRCG_drcg 0x00000001 |
| #define Gbl_gc360DisRCG_drcg_drcgActive 0x1 |
| #define Gbl_gc360DisRCG_drcg_drcgInactive 0x0 |
| #define RA_Gbl_gc360ResetStatus 0x027C |
| #define BA_Gbl_gc360ResetStatus_SyncReset 0x027C |
| #define B16Gbl_gc360ResetStatus_SyncReset 0x027C |
| #define LSb32Gbl_gc360ResetStatus_SyncReset 0 |
| #define LSb16Gbl_gc360ResetStatus_SyncReset 0 |
| #define bGbl_gc360ResetStatus_SyncReset 1 |
| #define MSK32Gbl_gc360ResetStatus_SyncReset 0x00000001 |
| #define Gbl_gc360ResetStatus_SyncReset_assert 0x1 |
| #define Gbl_gc360ResetStatus_SyncReset_deassert 0x0 |
| #define RA_Gbl_SpdifRxResetStatus 0x0280 |
| #define BA_Gbl_SpdifRxResetStatus_SyncReset 0x0280 |
| #define B16Gbl_SpdifRxResetStatus_SyncReset 0x0280 |
| #define LSb32Gbl_SpdifRxResetStatus_SyncReset 0 |
| #define LSb16Gbl_SpdifRxResetStatus_SyncReset 0 |
| #define bGbl_SpdifRxResetStatus_SyncReset 1 |
| #define MSK32Gbl_SpdifRxResetStatus_SyncReset 0x00000001 |
| #define Gbl_SpdifRxResetStatus_SyncReset_assert 0x1 |
| #define Gbl_SpdifRxResetStatus_SyncReset_deassert 0x0 |
| #define RA_Gbl_DroEnable 0x0284 |
| #define BA_Gbl_DroEnable_EnDroCounter 0x0284 |
| #define B16Gbl_DroEnable_EnDroCounter 0x0284 |
| #define LSb32Gbl_DroEnable_EnDroCounter 0 |
| #define LSb16Gbl_DroEnable_EnDroCounter 0 |
| #define bGbl_DroEnable_EnDroCounter 1 |
| #define MSK32Gbl_DroEnable_EnDroCounter 0x00000001 |
| #define Gbl_DroEnable_EnDroCounter_assert 0x1 |
| #define Gbl_DroEnable_EnDroCounter_deassert 0x0 |
| #define RA_Gbl_DroCounter 0x0288 |
| #define BA_Gbl_DroCounter_CountVal 0x0288 |
| #define B16Gbl_DroCounter_CountVal 0x0288 |
| #define LSb32Gbl_DroCounter_CountVal 0 |
| #define LSb16Gbl_DroCounter_CountVal 0 |
| #define bGbl_DroCounter_CountVal 32 |
| #define MSK32Gbl_DroCounter_CountVal 0xFFFFFFFF |
| #define RA_Gbl_DroDone 0x028C |
| #define BA_Gbl_DroDone_status 0x028C |
| #define B16Gbl_DroDone_status 0x028C |
| #define LSb32Gbl_DroDone_status 0 |
| #define LSb16Gbl_DroDone_status 0 |
| #define bGbl_DroDone_status 1 |
| #define MSK32Gbl_DroDone_status 0x00000001 |
| #define RA_Gbl_cpussSvtDro0Cnt 0x0290 |
| #define RA_Gbl_cpussLvtDro1Cnt 0x0294 |
| #define RA_Gbl_cpussSvtDro2Cnt 0x0298 |
| #define RA_Gbl_cpussLvtDro3Cnt 0x029C |
| #define RA_Gbl_vMetaSvtDro0Cnt 0x02A0 |
| #define RA_Gbl_vMetaLvtDro1Cnt 0x02A4 |
| #define RA_Gbl_gfx3DSvtDro0Cnt 0x02A8 |
| #define RA_Gbl_gfx3DLvtDro1Cnt 0x02AC |
| #define RA_Gbl_INT_ID 0x02B0 |
| #define BA_Gbl_INT_ID_VALUE 0x02B0 |
| #define B16Gbl_INT_ID_VALUE 0x02B0 |
| #define LSb32Gbl_INT_ID_VALUE 0 |
| #define LSb16Gbl_INT_ID_VALUE 0 |
| #define bGbl_INT_ID_VALUE 8 |
| #define MSK32Gbl_INT_ID_VALUE 0x000000FF |
| #define RA_Gbl_hdmirxFpllRefClk 0x02B4 |
| #define RA_Gbl_hdmirxTClk 0x02B8 |
| #define RA_Gbl_hdmirxMClk 0x02BC |
| #define RA_Gbl_gethRgmiiClk 0x02C0 |
| #define RA_Gbl_pcieTestClk 0x02C4 |
| #define RA_Gbl_stickyResetN 0x02C8 |
| #define BA_Gbl_stickyResetN_gethRgmiiMemRstn 0x02C8 |
| #define B16Gbl_stickyResetN_gethRgmiiMemRstn 0x02C8 |
| #define LSb32Gbl_stickyResetN_gethRgmiiMemRstn 0 |
| #define LSb16Gbl_stickyResetN_gethRgmiiMemRstn 0 |
| #define bGbl_stickyResetN_gethRgmiiMemRstn 1 |
| #define MSK32Gbl_stickyResetN_gethRgmiiMemRstn 0x00000001 |
| #define Gbl_stickyResetN_gethRgmiiMemRstn_asserted 0x0 |
| #define Gbl_stickyResetN_gethRgmiiMemRstn_deasserted 0x1 |
| #define BA_Gbl_stickyResetN_gethRgmiiRstn 0x02C8 |
| #define B16Gbl_stickyResetN_gethRgmiiRstn 0x02C8 |
| #define LSb32Gbl_stickyResetN_gethRgmiiRstn 1 |
| #define LSb16Gbl_stickyResetN_gethRgmiiRstn 1 |
| #define bGbl_stickyResetN_gethRgmiiRstn 1 |
| #define MSK32Gbl_stickyResetN_gethRgmiiRstn 0x00000002 |
| #define Gbl_stickyResetN_gethRgmiiRstn_asserted 0x0 |
| #define Gbl_stickyResetN_gethRgmiiRstn_deasserted 0x1 |
| #define BA_Gbl_stickyResetN_cpuPllRstn 0x02C8 |
| #define B16Gbl_stickyResetN_cpuPllRstn 0x02C8 |
| #define LSb32Gbl_stickyResetN_cpuPllRstn 2 |
| #define LSb16Gbl_stickyResetN_cpuPllRstn 2 |
| #define bGbl_stickyResetN_cpuPllRstn 1 |
| #define MSK32Gbl_stickyResetN_cpuPllRstn 0x00000004 |
| #define Gbl_stickyResetN_cpuPllRstn_asserted 0x0 |
| #define Gbl_stickyResetN_cpuPllRstn_deasserted 0x1 |
| #define BA_Gbl_stickyResetN_memPllRstn 0x02C8 |
| #define B16Gbl_stickyResetN_memPllRstn 0x02C8 |
| #define LSb32Gbl_stickyResetN_memPllRstn 3 |
| #define LSb16Gbl_stickyResetN_memPllRstn 3 |
| #define bGbl_stickyResetN_memPllRstn 1 |
| #define MSK32Gbl_stickyResetN_memPllRstn 0x00000008 |
| #define Gbl_stickyResetN_memPllRstn_asserted 0x0 |
| #define Gbl_stickyResetN_memPllRstn_deasserted 0x1 |
| #define BA_Gbl_stickyResetN_sysPllRstn 0x02C8 |
| #define B16Gbl_stickyResetN_sysPllRstn 0x02C8 |
| #define LSb32Gbl_stickyResetN_sysPllRstn 4 |
| #define LSb16Gbl_stickyResetN_sysPllRstn 4 |
| #define bGbl_stickyResetN_sysPllRstn 1 |
| #define MSK32Gbl_stickyResetN_sysPllRstn 0x00000010 |
| #define Gbl_stickyResetN_sysPllRstn_asserted 0x0 |
| #define Gbl_stickyResetN_sysPllRstn_deasserted 0x1 |
| #define RA_Gbl_gethRgmii_dll 0x02CC |
| #define BA_Gbl_gethRgmii_dll_tx_delay 0x02CC |
| #define B16Gbl_gethRgmii_dll_tx_delay 0x02CC |
| #define LSb32Gbl_gethRgmii_dll_tx_delay 0 |
| #define LSb16Gbl_gethRgmii_dll_tx_delay 0 |
| #define bGbl_gethRgmii_dll_tx_delay 9 |
| #define MSK32Gbl_gethRgmii_dll_tx_delay 0x000001FF |
| #define BA_Gbl_gethRgmii_dll_rx_delay 0x02CD |
| #define B16Gbl_gethRgmii_dll_rx_delay 0x02CC |
| #define LSb32Gbl_gethRgmii_dll_rx_delay 9 |
| #define LSb16Gbl_gethRgmii_dll_rx_delay 9 |
| #define bGbl_gethRgmii_dll_rx_delay 9 |
| #define MSK32Gbl_gethRgmii_dll_rx_delay 0x0003FE00 |
| #define RA_Gbl_funcSel 0x02D0 |
| #define BA_Gbl_funcSel_pcie_sata_sel 0x02D0 |
| #define B16Gbl_funcSel_pcie_sata_sel 0x02D0 |
| #define LSb32Gbl_funcSel_pcie_sata_sel 0 |
| #define LSb16Gbl_funcSel_pcie_sata_sel 0 |
| #define bGbl_funcSel_pcie_sata_sel 1 |
| #define MSK32Gbl_funcSel_pcie_sata_sel 0x00000001 |
| #define BA_Gbl_funcSel_gmac_eth_sel 0x02D0 |
| #define B16Gbl_funcSel_gmac_eth_sel 0x02D0 |
| #define LSb32Gbl_funcSel_gmac_eth_sel 1 |
| #define LSb16Gbl_funcSel_gmac_eth_sel 1 |
| #define bGbl_funcSel_gmac_eth_sel 1 |
| #define MSK32Gbl_funcSel_gmac_eth_sel 0x00000002 |
| #define RA_Gbl_efuse 0x02D4 |
| #define RA_Gbl_chipCntl 0x0300 |
| #define BA_Gbl_chipCntl_pcieDownMap 0x0300 |
| #define B16Gbl_chipCntl_pcieDownMap 0x0300 |
| #define LSb32Gbl_chipCntl_pcieDownMap 0 |
| #define LSb16Gbl_chipCntl_pcieDownMap 0 |
| #define bGbl_chipCntl_pcieDownMap 1 |
| #define MSK32Gbl_chipCntl_pcieDownMap 0x00000001 |
| #define Gbl_chipCntl_pcieDownMap_M512 0x0 |
| #define Gbl_chipCntl_pcieDownMap_M256 0x1 |
| #define BA_Gbl_chipCntl_pcie_rc 0x0300 |
| #define B16Gbl_chipCntl_pcie_rc 0x0300 |
| #define LSb32Gbl_chipCntl_pcie_rc 1 |
| #define LSb16Gbl_chipCntl_pcie_rc 1 |
| #define bGbl_chipCntl_pcie_rc 1 |
| #define MSK32Gbl_chipCntl_pcie_rc 0x00000002 |
| #define Gbl_chipCntl_pcie_rc_END_POINT 0x0 |
| #define Gbl_chipCntl_pcie_rc_ROOT_COMPLEX 0x1 |
| #define RA_Gbl_bootStrapEn 0x0304 |
| #define BA_Gbl_bootStrapEn_pllPwrDownEn 0x0304 |
| #define B16Gbl_bootStrapEn_pllPwrDownEn 0x0304 |
| #define LSb32Gbl_bootStrapEn_pllPwrDownEn 0 |
| #define LSb16Gbl_bootStrapEn_pllPwrDownEn 0 |
| #define bGbl_bootStrapEn_pllPwrDownEn 1 |
| #define MSK32Gbl_bootStrapEn_pllPwrDownEn 0x00000001 |
| #define Gbl_bootStrapEn_pllPwrDownEn_Disable 0x0 |
| #define Gbl_bootStrapEn_pllPwrDownEn_Enable 0x1 |
| #define BA_Gbl_bootStrapEn_refClk12P5MEn 0x0304 |
| #define B16Gbl_bootStrapEn_refClk12P5MEn 0x0304 |
| #define LSb32Gbl_bootStrapEn_refClk12P5MEn 1 |
| #define LSb16Gbl_bootStrapEn_refClk12P5MEn 1 |
| #define bGbl_bootStrapEn_refClk12P5MEn 1 |
| #define MSK32Gbl_bootStrapEn_refClk12P5MEn 0x00000002 |
| #define Gbl_bootStrapEn_refClk12P5MEn_Disable 0x0 |
| #define Gbl_bootStrapEn_refClk12P5MEn_Enable 0x1 |
| #define RA_Gbl_axiClkEn 0x0308 |
| #define BA_Gbl_axiClkEn_avioAxiClkEn 0x0308 |
| #define B16Gbl_axiClkEn_avioAxiClkEn 0x0308 |
| #define LSb32Gbl_axiClkEn_avioAxiClkEn 0 |
| #define LSb16Gbl_axiClkEn_avioAxiClkEn 0 |
| #define bGbl_axiClkEn_avioAxiClkEn 1 |
| #define MSK32Gbl_axiClkEn_avioAxiClkEn 0x00000001 |
| #define Gbl_axiClkEn_avioAxiClkEn_enable 0x1 |
| #define Gbl_axiClkEn_avioAxiClkEn_disable 0x0 |
| #define RA_Gbl_ahbClkEn 0x030C |
| #define BA_Gbl_ahbClkEn_avioAhbClkEn 0x030C |
| #define B16Gbl_ahbClkEn_avioAhbClkEn 0x030C |
| #define LSb32Gbl_ahbClkEn_avioAhbClkEn 0 |
| #define LSb16Gbl_ahbClkEn_avioAhbClkEn 0 |
| #define bGbl_ahbClkEn_avioAhbClkEn 1 |
| #define MSK32Gbl_ahbClkEn_avioAhbClkEn 0x00000001 |
| #define Gbl_ahbClkEn_avioAhbClkEn_enable 0x1 |
| #define Gbl_ahbClkEn_avioAhbClkEn_disable 0x0 |
| #define RA_Gbl_SPI1_SS0nCntl 0x8000 |
| #define BA_Gbl_SPI1_SS0nCntl_PU_EN 0x8000 |
| #define B16Gbl_SPI1_SS0nCntl_PU_EN 0x8000 |
| #define LSb32Gbl_SPI1_SS0nCntl_PU_EN 0 |
| #define LSb16Gbl_SPI1_SS0nCntl_PU_EN 0 |
| #define bGbl_SPI1_SS0nCntl_PU_EN 1 |
| #define MSK32Gbl_SPI1_SS0nCntl_PU_EN 0x00000001 |
| #define BA_Gbl_SPI1_SS0nCntl_PD_EN 0x8000 |
| #define B16Gbl_SPI1_SS0nCntl_PD_EN 0x8000 |
| #define LSb32Gbl_SPI1_SS0nCntl_PD_EN 1 |
| #define LSb16Gbl_SPI1_SS0nCntl_PD_EN 1 |
| #define bGbl_SPI1_SS0nCntl_PD_EN 1 |
| #define MSK32Gbl_SPI1_SS0nCntl_PD_EN 0x00000002 |
| #define RA_Gbl_SPI1_SS1nCntl 0x8004 |
| #define BA_Gbl_SPI1_SS1nCntl_PU_EN 0x8004 |
| #define B16Gbl_SPI1_SS1nCntl_PU_EN 0x8004 |
| #define LSb32Gbl_SPI1_SS1nCntl_PU_EN 0 |
| #define LSb16Gbl_SPI1_SS1nCntl_PU_EN 0 |
| #define bGbl_SPI1_SS1nCntl_PU_EN 1 |
| #define MSK32Gbl_SPI1_SS1nCntl_PU_EN 0x00000001 |
| #define BA_Gbl_SPI1_SS1nCntl_PD_EN 0x8004 |
| #define B16Gbl_SPI1_SS1nCntl_PD_EN 0x8004 |
| #define LSb32Gbl_SPI1_SS1nCntl_PD_EN 1 |
| #define LSb16Gbl_SPI1_SS1nCntl_PD_EN 1 |
| #define bGbl_SPI1_SS1nCntl_PD_EN 1 |
| #define MSK32Gbl_SPI1_SS1nCntl_PD_EN 0x00000002 |
| #define RA_Gbl_SPI1_SS2nCntl 0x8008 |
| #define BA_Gbl_SPI1_SS2nCntl_PU_EN 0x8008 |
| #define B16Gbl_SPI1_SS2nCntl_PU_EN 0x8008 |
| #define LSb32Gbl_SPI1_SS2nCntl_PU_EN 0 |
| #define LSb16Gbl_SPI1_SS2nCntl_PU_EN 0 |
| #define bGbl_SPI1_SS2nCntl_PU_EN 1 |
| #define MSK32Gbl_SPI1_SS2nCntl_PU_EN 0x00000001 |
| #define BA_Gbl_SPI1_SS2nCntl_PD_EN 0x8008 |
| #define B16Gbl_SPI1_SS2nCntl_PD_EN 0x8008 |
| #define LSb32Gbl_SPI1_SS2nCntl_PD_EN 1 |
| #define LSb16Gbl_SPI1_SS2nCntl_PD_EN 1 |
| #define bGbl_SPI1_SS2nCntl_PD_EN 1 |
| #define MSK32Gbl_SPI1_SS2nCntl_PD_EN 0x00000002 |
| #define RA_Gbl_SPI1_SCLKCntl 0x800C |
| #define BA_Gbl_SPI1_SCLKCntl_PU_EN 0x800C |
| #define B16Gbl_SPI1_SCLKCntl_PU_EN 0x800C |
| #define LSb32Gbl_SPI1_SCLKCntl_PU_EN 0 |
| #define LSb16Gbl_SPI1_SCLKCntl_PU_EN 0 |
| #define bGbl_SPI1_SCLKCntl_PU_EN 1 |
| #define MSK32Gbl_SPI1_SCLKCntl_PU_EN 0x00000001 |
| #define BA_Gbl_SPI1_SCLKCntl_PD_EN 0x800C |
| #define B16Gbl_SPI1_SCLKCntl_PD_EN 0x800C |
| #define LSb32Gbl_SPI1_SCLKCntl_PD_EN 1 |
| #define LSb16Gbl_SPI1_SCLKCntl_PD_EN 1 |
| #define bGbl_SPI1_SCLKCntl_PD_EN 1 |
| #define MSK32Gbl_SPI1_SCLKCntl_PD_EN 0x00000002 |
| #define RA_Gbl_SPI1_SDOCntl 0x8010 |
| #define BA_Gbl_SPI1_SDOCntl_PU_EN 0x8010 |
| #define B16Gbl_SPI1_SDOCntl_PU_EN 0x8010 |
| #define LSb32Gbl_SPI1_SDOCntl_PU_EN 0 |
| #define LSb16Gbl_SPI1_SDOCntl_PU_EN 0 |
| #define bGbl_SPI1_SDOCntl_PU_EN 1 |
| #define MSK32Gbl_SPI1_SDOCntl_PU_EN 0x00000001 |
| #define BA_Gbl_SPI1_SDOCntl_PD_EN 0x8010 |
| #define B16Gbl_SPI1_SDOCntl_PD_EN 0x8010 |
| #define LSb32Gbl_SPI1_SDOCntl_PD_EN 1 |
| #define LSb16Gbl_SPI1_SDOCntl_PD_EN 1 |
| #define bGbl_SPI1_SDOCntl_PD_EN 1 |
| #define MSK32Gbl_SPI1_SDOCntl_PD_EN 0x00000002 |
| #define RA_Gbl_SPI1_SDICntl 0x8014 |
| #define BA_Gbl_SPI1_SDICntl_PU_EN 0x8014 |
| #define B16Gbl_SPI1_SDICntl_PU_EN 0x8014 |
| #define LSb32Gbl_SPI1_SDICntl_PU_EN 0 |
| #define LSb16Gbl_SPI1_SDICntl_PU_EN 0 |
| #define bGbl_SPI1_SDICntl_PU_EN 1 |
| #define MSK32Gbl_SPI1_SDICntl_PU_EN 0x00000001 |
| #define BA_Gbl_SPI1_SDICntl_PD_EN 0x8014 |
| #define B16Gbl_SPI1_SDICntl_PD_EN 0x8014 |
| #define LSb32Gbl_SPI1_SDICntl_PD_EN 1 |
| #define LSb16Gbl_SPI1_SDICntl_PD_EN 1 |
| #define bGbl_SPI1_SDICntl_PD_EN 1 |
| #define MSK32Gbl_SPI1_SDICntl_PD_EN 0x00000002 |
| #define RA_Gbl_URT0_RXDCntl 0x8018 |
| #define BA_Gbl_URT0_RXDCntl_PU_EN 0x8018 |
| #define B16Gbl_URT0_RXDCntl_PU_EN 0x8018 |
| #define LSb32Gbl_URT0_RXDCntl_PU_EN 0 |
| #define LSb16Gbl_URT0_RXDCntl_PU_EN 0 |
| #define bGbl_URT0_RXDCntl_PU_EN 1 |
| #define MSK32Gbl_URT0_RXDCntl_PU_EN 0x00000001 |
| #define BA_Gbl_URT0_RXDCntl_PD_EN 0x8018 |
| #define B16Gbl_URT0_RXDCntl_PD_EN 0x8018 |
| #define LSb32Gbl_URT0_RXDCntl_PD_EN 1 |
| #define LSb16Gbl_URT0_RXDCntl_PD_EN 1 |
| #define bGbl_URT0_RXDCntl_PD_EN 1 |
| #define MSK32Gbl_URT0_RXDCntl_PD_EN 0x00000002 |
| #define RA_Gbl_URT0_TXDCntl 0x801C |
| #define BA_Gbl_URT0_TXDCntl_PU_EN 0x801C |
| #define B16Gbl_URT0_TXDCntl_PU_EN 0x801C |
| #define LSb32Gbl_URT0_TXDCntl_PU_EN 0 |
| #define LSb16Gbl_URT0_TXDCntl_PU_EN 0 |
| #define bGbl_URT0_TXDCntl_PU_EN 1 |
| #define MSK32Gbl_URT0_TXDCntl_PU_EN 0x00000001 |
| #define BA_Gbl_URT0_TXDCntl_PD_EN 0x801C |
| #define B16Gbl_URT0_TXDCntl_PD_EN 0x801C |
| #define LSb32Gbl_URT0_TXDCntl_PD_EN 1 |
| #define LSb16Gbl_URT0_TXDCntl_PD_EN 1 |
| #define bGbl_URT0_TXDCntl_PD_EN 1 |
| #define MSK32Gbl_URT0_TXDCntl_PD_EN 0x00000002 |
| #define RA_Gbl_DVIO0Cntl 0x8020 |
| #define BA_Gbl_DVIO0Cntl_PU_EN 0x8020 |
| #define B16Gbl_DVIO0Cntl_PU_EN 0x8020 |
| #define LSb32Gbl_DVIO0Cntl_PU_EN 0 |
| #define LSb16Gbl_DVIO0Cntl_PU_EN 0 |
| #define bGbl_DVIO0Cntl_PU_EN 1 |
| #define MSK32Gbl_DVIO0Cntl_PU_EN 0x00000001 |
| #define BA_Gbl_DVIO0Cntl_PD_EN 0x8020 |
| #define B16Gbl_DVIO0Cntl_PD_EN 0x8020 |
| #define LSb32Gbl_DVIO0Cntl_PD_EN 1 |
| #define LSb16Gbl_DVIO0Cntl_PD_EN 1 |
| #define bGbl_DVIO0Cntl_PD_EN 1 |
| #define MSK32Gbl_DVIO0Cntl_PD_EN 0x00000002 |
| #define BA_Gbl_DVIO0Cntl_SLP_DI 0x8020 |
| #define B16Gbl_DVIO0Cntl_SLP_DI 0x8020 |
| #define LSb32Gbl_DVIO0Cntl_SLP_DI 2 |
| #define LSb16Gbl_DVIO0Cntl_SLP_DI 2 |
| #define bGbl_DVIO0Cntl_SLP_DI 1 |
| #define MSK32Gbl_DVIO0Cntl_SLP_DI 0x00000004 |
| #define RA_Gbl_DVIO1Cntl 0x8024 |
| #define BA_Gbl_DVIO1Cntl_PU_EN 0x8024 |
| #define B16Gbl_DVIO1Cntl_PU_EN 0x8024 |
| #define LSb32Gbl_DVIO1Cntl_PU_EN 0 |
| #define LSb16Gbl_DVIO1Cntl_PU_EN 0 |
| #define bGbl_DVIO1Cntl_PU_EN 1 |
| #define MSK32Gbl_DVIO1Cntl_PU_EN 0x00000001 |
| #define BA_Gbl_DVIO1Cntl_PD_EN 0x8024 |
| #define B16Gbl_DVIO1Cntl_PD_EN 0x8024 |
| #define LSb32Gbl_DVIO1Cntl_PD_EN 1 |
| #define LSb16Gbl_DVIO1Cntl_PD_EN 1 |
| #define bGbl_DVIO1Cntl_PD_EN 1 |
| #define MSK32Gbl_DVIO1Cntl_PD_EN 0x00000002 |
| #define BA_Gbl_DVIO1Cntl_SLP_DI 0x8024 |
| #define B16Gbl_DVIO1Cntl_SLP_DI 0x8024 |
| #define LSb32Gbl_DVIO1Cntl_SLP_DI 2 |
| #define LSb16Gbl_DVIO1Cntl_SLP_DI 2 |
| #define bGbl_DVIO1Cntl_SLP_DI 1 |
| #define MSK32Gbl_DVIO1Cntl_SLP_DI 0x00000004 |
| #define RA_Gbl_DVIO2Cntl 0x8028 |
| #define BA_Gbl_DVIO2Cntl_PU_EN 0x8028 |
| #define B16Gbl_DVIO2Cntl_PU_EN 0x8028 |
| #define LSb32Gbl_DVIO2Cntl_PU_EN 0 |
| #define LSb16Gbl_DVIO2Cntl_PU_EN 0 |
| #define bGbl_DVIO2Cntl_PU_EN 1 |
| #define MSK32Gbl_DVIO2Cntl_PU_EN 0x00000001 |
| #define BA_Gbl_DVIO2Cntl_PD_EN 0x8028 |
| #define B16Gbl_DVIO2Cntl_PD_EN 0x8028 |
| #define LSb32Gbl_DVIO2Cntl_PD_EN 1 |
| #define LSb16Gbl_DVIO2Cntl_PD_EN 1 |
| #define bGbl_DVIO2Cntl_PD_EN 1 |
| #define MSK32Gbl_DVIO2Cntl_PD_EN 0x00000002 |
| #define BA_Gbl_DVIO2Cntl_SLP_DI 0x8028 |
| #define B16Gbl_DVIO2Cntl_SLP_DI 0x8028 |
| #define LSb32Gbl_DVIO2Cntl_SLP_DI 2 |
| #define LSb16Gbl_DVIO2Cntl_SLP_DI 2 |
| #define bGbl_DVIO2Cntl_SLP_DI 1 |
| #define MSK32Gbl_DVIO2Cntl_SLP_DI 0x00000004 |
| #define RA_Gbl_DVIO3Cntl 0x802C |
| #define BA_Gbl_DVIO3Cntl_PU_EN 0x802C |
| #define B16Gbl_DVIO3Cntl_PU_EN 0x802C |
| #define LSb32Gbl_DVIO3Cntl_PU_EN 0 |
| #define LSb16Gbl_DVIO3Cntl_PU_EN 0 |
| #define bGbl_DVIO3Cntl_PU_EN 1 |
| #define MSK32Gbl_DVIO3Cntl_PU_EN 0x00000001 |
| #define BA_Gbl_DVIO3Cntl_PD_EN 0x802C |
| #define B16Gbl_DVIO3Cntl_PD_EN 0x802C |
| #define LSb32Gbl_DVIO3Cntl_PD_EN 1 |
| #define LSb16Gbl_DVIO3Cntl_PD_EN 1 |
| #define bGbl_DVIO3Cntl_PD_EN 1 |
| #define MSK32Gbl_DVIO3Cntl_PD_EN 0x00000002 |
| #define BA_Gbl_DVIO3Cntl_SLP_DI 0x802C |
| #define B16Gbl_DVIO3Cntl_SLP_DI 0x802C |
| #define LSb32Gbl_DVIO3Cntl_SLP_DI 2 |
| #define LSb16Gbl_DVIO3Cntl_SLP_DI 2 |
| #define bGbl_DVIO3Cntl_SLP_DI 1 |
| #define MSK32Gbl_DVIO3Cntl_SLP_DI 0x00000004 |
| #define RA_Gbl_DVIO4Cntl 0x8030 |
| #define BA_Gbl_DVIO4Cntl_PU_EN 0x8030 |
| #define B16Gbl_DVIO4Cntl_PU_EN 0x8030 |
| #define LSb32Gbl_DVIO4Cntl_PU_EN 0 |
| #define LSb16Gbl_DVIO4Cntl_PU_EN 0 |
| #define bGbl_DVIO4Cntl_PU_EN 1 |
| #define MSK32Gbl_DVIO4Cntl_PU_EN 0x00000001 |
| #define BA_Gbl_DVIO4Cntl_PD_EN 0x8030 |
| #define B16Gbl_DVIO4Cntl_PD_EN 0x8030 |
| #define LSb32Gbl_DVIO4Cntl_PD_EN 1 |
| #define LSb16Gbl_DVIO4Cntl_PD_EN 1 |
| #define bGbl_DVIO4Cntl_PD_EN 1 |
| #define MSK32Gbl_DVIO4Cntl_PD_EN 0x00000002 |
| #define BA_Gbl_DVIO4Cntl_SLP_DI 0x8030 |
| #define B16Gbl_DVIO4Cntl_SLP_DI 0x8030 |
| #define LSb32Gbl_DVIO4Cntl_SLP_DI 2 |
| #define LSb16Gbl_DVIO4Cntl_SLP_DI 2 |
| #define bGbl_DVIO4Cntl_SLP_DI 1 |
| #define MSK32Gbl_DVIO4Cntl_SLP_DI 0x00000004 |
| #define RA_Gbl_DVIO5Cntl 0x8034 |
| #define BA_Gbl_DVIO5Cntl_PU_EN 0x8034 |
| #define B16Gbl_DVIO5Cntl_PU_EN 0x8034 |
| #define LSb32Gbl_DVIO5Cntl_PU_EN 0 |
| #define LSb16Gbl_DVIO5Cntl_PU_EN 0 |
| #define bGbl_DVIO5Cntl_PU_EN 1 |
| #define MSK32Gbl_DVIO5Cntl_PU_EN 0x00000001 |
| #define BA_Gbl_DVIO5Cntl_PD_EN 0x8034 |
| #define B16Gbl_DVIO5Cntl_PD_EN 0x8034 |
| #define LSb32Gbl_DVIO5Cntl_PD_EN 1 |
| #define LSb16Gbl_DVIO5Cntl_PD_EN 1 |
| #define bGbl_DVIO5Cntl_PD_EN 1 |
| #define MSK32Gbl_DVIO5Cntl_PD_EN 0x00000002 |
| #define BA_Gbl_DVIO5Cntl_SLP_DI 0x8034 |
| #define B16Gbl_DVIO5Cntl_SLP_DI 0x8034 |
| #define LSb32Gbl_DVIO5Cntl_SLP_DI 2 |
| #define LSb16Gbl_DVIO5Cntl_SLP_DI 2 |
| #define bGbl_DVIO5Cntl_SLP_DI 1 |
| #define MSK32Gbl_DVIO5Cntl_SLP_DI 0x00000004 |
| #define RA_Gbl_DVIO6Cntl 0x8038 |
| #define BA_Gbl_DVIO6Cntl_PU_EN 0x8038 |
| #define B16Gbl_DVIO6Cntl_PU_EN 0x8038 |
| #define LSb32Gbl_DVIO6Cntl_PU_EN 0 |
| #define LSb16Gbl_DVIO6Cntl_PU_EN 0 |
| #define bGbl_DVIO6Cntl_PU_EN 1 |
| #define MSK32Gbl_DVIO6Cntl_PU_EN 0x00000001 |
| #define BA_Gbl_DVIO6Cntl_PD_EN 0x8038 |
| #define B16Gbl_DVIO6Cntl_PD_EN 0x8038 |
| #define LSb32Gbl_DVIO6Cntl_PD_EN 1 |
| #define LSb16Gbl_DVIO6Cntl_PD_EN 1 |
| #define bGbl_DVIO6Cntl_PD_EN 1 |
| #define MSK32Gbl_DVIO6Cntl_PD_EN 0x00000002 |
| #define BA_Gbl_DVIO6Cntl_SLP_DI 0x8038 |
| #define B16Gbl_DVIO6Cntl_SLP_DI 0x8038 |
| #define LSb32Gbl_DVIO6Cntl_SLP_DI 2 |
| #define LSb16Gbl_DVIO6Cntl_SLP_DI 2 |
| #define bGbl_DVIO6Cntl_SLP_DI 1 |
| #define MSK32Gbl_DVIO6Cntl_SLP_DI 0x00000004 |
| #define RA_Gbl_DVIO7Cntl 0x803C |
| #define BA_Gbl_DVIO7Cntl_PU_EN 0x803C |
| #define B16Gbl_DVIO7Cntl_PU_EN 0x803C |
| #define LSb32Gbl_DVIO7Cntl_PU_EN 0 |
| #define LSb16Gbl_DVIO7Cntl_PU_EN 0 |
| #define bGbl_DVIO7Cntl_PU_EN 1 |
| #define MSK32Gbl_DVIO7Cntl_PU_EN 0x00000001 |
| #define BA_Gbl_DVIO7Cntl_PD_EN 0x803C |
| #define B16Gbl_DVIO7Cntl_PD_EN 0x803C |
| #define LSb32Gbl_DVIO7Cntl_PD_EN 1 |
| #define LSb16Gbl_DVIO7Cntl_PD_EN 1 |
| #define bGbl_DVIO7Cntl_PD_EN 1 |
| #define MSK32Gbl_DVIO7Cntl_PD_EN 0x00000002 |
| #define BA_Gbl_DVIO7Cntl_SLP_DI 0x803C |
| #define B16Gbl_DVIO7Cntl_SLP_DI 0x803C |
| #define LSb32Gbl_DVIO7Cntl_SLP_DI 2 |
| #define LSb16Gbl_DVIO7Cntl_SLP_DI 2 |
| #define bGbl_DVIO7Cntl_SLP_DI 1 |
| #define MSK32Gbl_DVIO7Cntl_SLP_DI 0x00000004 |
| #define RA_Gbl_DVIO8Cntl 0x8040 |
| #define BA_Gbl_DVIO8Cntl_PU_EN 0x8040 |
| #define B16Gbl_DVIO8Cntl_PU_EN 0x8040 |
| #define LSb32Gbl_DVIO8Cntl_PU_EN 0 |
| #define LSb16Gbl_DVIO8Cntl_PU_EN 0 |
| #define bGbl_DVIO8Cntl_PU_EN 1 |
| #define MSK32Gbl_DVIO8Cntl_PU_EN 0x00000001 |
| #define BA_Gbl_DVIO8Cntl_PD_EN 0x8040 |
| #define B16Gbl_DVIO8Cntl_PD_EN 0x8040 |
| #define LSb32Gbl_DVIO8Cntl_PD_EN 1 |
| #define LSb16Gbl_DVIO8Cntl_PD_EN 1 |
| #define bGbl_DVIO8Cntl_PD_EN 1 |
| #define MSK32Gbl_DVIO8Cntl_PD_EN 0x00000002 |
| #define BA_Gbl_DVIO8Cntl_SLP_DI 0x8040 |
| #define B16Gbl_DVIO8Cntl_SLP_DI 0x8040 |
| #define LSb32Gbl_DVIO8Cntl_SLP_DI 2 |
| #define LSb16Gbl_DVIO8Cntl_SLP_DI 2 |
| #define bGbl_DVIO8Cntl_SLP_DI 1 |
| #define MSK32Gbl_DVIO8Cntl_SLP_DI 0x00000004 |
| #define RA_Gbl_DVIO9Cntl 0x8044 |
| #define BA_Gbl_DVIO9Cntl_PU_EN 0x8044 |
| #define B16Gbl_DVIO9Cntl_PU_EN 0x8044 |
| #define LSb32Gbl_DVIO9Cntl_PU_EN 0 |
| #define LSb16Gbl_DVIO9Cntl_PU_EN 0 |
| #define bGbl_DVIO9Cntl_PU_EN 1 |
| #define MSK32Gbl_DVIO9Cntl_PU_EN 0x00000001 |
| #define BA_Gbl_DVIO9Cntl_PD_EN 0x8044 |
| #define B16Gbl_DVIO9Cntl_PD_EN 0x8044 |
| #define LSb32Gbl_DVIO9Cntl_PD_EN 1 |
| #define LSb16Gbl_DVIO9Cntl_PD_EN 1 |
| #define bGbl_DVIO9Cntl_PD_EN 1 |
| #define MSK32Gbl_DVIO9Cntl_PD_EN 0x00000002 |
| #define BA_Gbl_DVIO9Cntl_SLP_DI 0x8044 |
| #define B16Gbl_DVIO9Cntl_SLP_DI 0x8044 |
| #define LSb32Gbl_DVIO9Cntl_SLP_DI 2 |
| #define LSb16Gbl_DVIO9Cntl_SLP_DI 2 |
| #define bGbl_DVIO9Cntl_SLP_DI 1 |
| #define MSK32Gbl_DVIO9Cntl_SLP_DI 0x00000004 |
| #define RA_Gbl_DVIO10Cntl 0x8048 |
| #define BA_Gbl_DVIO10Cntl_PU_EN 0x8048 |
| #define B16Gbl_DVIO10Cntl_PU_EN 0x8048 |
| #define LSb32Gbl_DVIO10Cntl_PU_EN 0 |
| #define LSb16Gbl_DVIO10Cntl_PU_EN 0 |
| #define bGbl_DVIO10Cntl_PU_EN 1 |
| #define MSK32Gbl_DVIO10Cntl_PU_EN 0x00000001 |
| #define BA_Gbl_DVIO10Cntl_PD_EN 0x8048 |
| #define B16Gbl_DVIO10Cntl_PD_EN 0x8048 |
| #define LSb32Gbl_DVIO10Cntl_PD_EN 1 |
| #define LSb16Gbl_DVIO10Cntl_PD_EN 1 |
| #define bGbl_DVIO10Cntl_PD_EN 1 |
| #define MSK32Gbl_DVIO10Cntl_PD_EN 0x00000002 |
| #define BA_Gbl_DVIO10Cntl_SLP_DI 0x8048 |
| #define B16Gbl_DVIO10Cntl_SLP_DI 0x8048 |
| #define LSb32Gbl_DVIO10Cntl_SLP_DI 2 |
| #define LSb16Gbl_DVIO10Cntl_SLP_DI 2 |
| #define bGbl_DVIO10Cntl_SLP_DI 1 |
| #define MSK32Gbl_DVIO10Cntl_SLP_DI 0x00000004 |
| #define RA_Gbl_DVIO11Cntl 0x804C |
| #define BA_Gbl_DVIO11Cntl_PU_EN 0x804C |
| #define B16Gbl_DVIO11Cntl_PU_EN 0x804C |
| #define LSb32Gbl_DVIO11Cntl_PU_EN 0 |
| #define LSb16Gbl_DVIO11Cntl_PU_EN 0 |
| #define bGbl_DVIO11Cntl_PU_EN 1 |
| #define MSK32Gbl_DVIO11Cntl_PU_EN 0x00000001 |
| #define BA_Gbl_DVIO11Cntl_PD_EN 0x804C |
| #define B16Gbl_DVIO11Cntl_PD_EN 0x804C |
| #define LSb32Gbl_DVIO11Cntl_PD_EN 1 |
| #define LSb16Gbl_DVIO11Cntl_PD_EN 1 |
| #define bGbl_DVIO11Cntl_PD_EN 1 |
| #define MSK32Gbl_DVIO11Cntl_PD_EN 0x00000002 |
| #define BA_Gbl_DVIO11Cntl_SLP_DI 0x804C |
| #define B16Gbl_DVIO11Cntl_SLP_DI 0x804C |
| #define LSb32Gbl_DVIO11Cntl_SLP_DI 2 |
| #define LSb16Gbl_DVIO11Cntl_SLP_DI 2 |
| #define bGbl_DVIO11Cntl_SLP_DI 1 |
| #define MSK32Gbl_DVIO11Cntl_SLP_DI 0x00000004 |
| #define RA_Gbl_DV0_CLKCntl 0x8050 |
| #define BA_Gbl_DV0_CLKCntl_PU_EN 0x8050 |
| #define B16Gbl_DV0_CLKCntl_PU_EN 0x8050 |
| #define LSb32Gbl_DV0_CLKCntl_PU_EN 0 |
| #define LSb16Gbl_DV0_CLKCntl_PU_EN 0 |
| #define bGbl_DV0_CLKCntl_PU_EN 1 |
| #define MSK32Gbl_DV0_CLKCntl_PU_EN 0x00000001 |
| #define BA_Gbl_DV0_CLKCntl_PD_EN 0x8050 |
| #define B16Gbl_DV0_CLKCntl_PD_EN 0x8050 |
| #define LSb32Gbl_DV0_CLKCntl_PD_EN 1 |
| #define LSb16Gbl_DV0_CLKCntl_PD_EN 1 |
| #define bGbl_DV0_CLKCntl_PD_EN 1 |
| #define MSK32Gbl_DV0_CLKCntl_PD_EN 0x00000002 |
| #define BA_Gbl_DV0_CLKCntl_SLP_DI 0x8050 |
| #define B16Gbl_DV0_CLKCntl_SLP_DI 0x8050 |
| #define LSb32Gbl_DV0_CLKCntl_SLP_DI 2 |
| #define LSb16Gbl_DV0_CLKCntl_SLP_DI 2 |
| #define bGbl_DV0_CLKCntl_SLP_DI 1 |
| #define MSK32Gbl_DV0_CLKCntl_SLP_DI 0x00000004 |
| #define RA_Gbl_DV0_HSCntl 0x8054 |
| #define BA_Gbl_DV0_HSCntl_PU_EN 0x8054 |
| #define B16Gbl_DV0_HSCntl_PU_EN 0x8054 |
| #define LSb32Gbl_DV0_HSCntl_PU_EN 0 |
| #define LSb16Gbl_DV0_HSCntl_PU_EN 0 |
| #define bGbl_DV0_HSCntl_PU_EN 1 |
| #define MSK32Gbl_DV0_HSCntl_PU_EN 0x00000001 |
| #define BA_Gbl_DV0_HSCntl_PD_EN 0x8054 |
| #define B16Gbl_DV0_HSCntl_PD_EN 0x8054 |
| #define LSb32Gbl_DV0_HSCntl_PD_EN 1 |
| #define LSb16Gbl_DV0_HSCntl_PD_EN 1 |
| #define bGbl_DV0_HSCntl_PD_EN 1 |
| #define MSK32Gbl_DV0_HSCntl_PD_EN 0x00000002 |
| #define BA_Gbl_DV0_HSCntl_SLP_DI 0x8054 |
| #define B16Gbl_DV0_HSCntl_SLP_DI 0x8054 |
| #define LSb32Gbl_DV0_HSCntl_SLP_DI 2 |
| #define LSb16Gbl_DV0_HSCntl_SLP_DI 2 |
| #define bGbl_DV0_HSCntl_SLP_DI 1 |
| #define MSK32Gbl_DV0_HSCntl_SLP_DI 0x00000004 |
| #define RA_Gbl_DV0_VSCntl 0x8058 |
| #define BA_Gbl_DV0_VSCntl_PU_EN 0x8058 |
| #define B16Gbl_DV0_VSCntl_PU_EN 0x8058 |
| #define LSb32Gbl_DV0_VSCntl_PU_EN 0 |
| #define LSb16Gbl_DV0_VSCntl_PU_EN 0 |
| #define bGbl_DV0_VSCntl_PU_EN 1 |
| #define MSK32Gbl_DV0_VSCntl_PU_EN 0x00000001 |
| #define BA_Gbl_DV0_VSCntl_PD_EN 0x8058 |
| #define B16Gbl_DV0_VSCntl_PD_EN 0x8058 |
| #define LSb32Gbl_DV0_VSCntl_PD_EN 1 |
| #define LSb16Gbl_DV0_VSCntl_PD_EN 1 |
| #define bGbl_DV0_VSCntl_PD_EN 1 |
| #define MSK32Gbl_DV0_VSCntl_PD_EN 0x00000002 |
| #define BA_Gbl_DV0_VSCntl_SLP_DI 0x8058 |
| #define B16Gbl_DV0_VSCntl_SLP_DI 0x8058 |
| #define LSb32Gbl_DV0_VSCntl_SLP_DI 2 |
| #define LSb16Gbl_DV0_VSCntl_SLP_DI 2 |
| #define bGbl_DV0_VSCntl_SLP_DI 1 |
| #define MSK32Gbl_DV0_VSCntl_SLP_DI 0x00000004 |
| #define RA_Gbl_DV0_FIDCntl 0x805C |
| #define BA_Gbl_DV0_FIDCntl_PU_EN 0x805C |
| #define B16Gbl_DV0_FIDCntl_PU_EN 0x805C |
| #define LSb32Gbl_DV0_FIDCntl_PU_EN 0 |
| #define LSb16Gbl_DV0_FIDCntl_PU_EN 0 |
| #define bGbl_DV0_FIDCntl_PU_EN 1 |
| #define MSK32Gbl_DV0_FIDCntl_PU_EN 0x00000001 |
| #define BA_Gbl_DV0_FIDCntl_PD_EN 0x805C |
| #define B16Gbl_DV0_FIDCntl_PD_EN 0x805C |
| #define LSb32Gbl_DV0_FIDCntl_PD_EN 1 |
| #define LSb16Gbl_DV0_FIDCntl_PD_EN 1 |
| #define bGbl_DV0_FIDCntl_PD_EN 1 |
| #define MSK32Gbl_DV0_FIDCntl_PD_EN 0x00000002 |
| #define BA_Gbl_DV0_FIDCntl_SLP_DI 0x805C |
| #define B16Gbl_DV0_FIDCntl_SLP_DI 0x805C |
| #define LSb32Gbl_DV0_FIDCntl_SLP_DI 2 |
| #define LSb16Gbl_DV0_FIDCntl_SLP_DI 2 |
| #define bGbl_DV0_FIDCntl_SLP_DI 1 |
| #define MSK32Gbl_DV0_FIDCntl_SLP_DI 0x00000004 |
| #define RA_Gbl_I2S0_BCLKCntl 0x8060 |
| #define BA_Gbl_I2S0_BCLKCntl_PU_EN 0x8060 |
| #define B16Gbl_I2S0_BCLKCntl_PU_EN 0x8060 |
| #define LSb32Gbl_I2S0_BCLKCntl_PU_EN 0 |
| #define LSb16Gbl_I2S0_BCLKCntl_PU_EN 0 |
| #define bGbl_I2S0_BCLKCntl_PU_EN 1 |
| #define MSK32Gbl_I2S0_BCLKCntl_PU_EN 0x00000001 |
| #define BA_Gbl_I2S0_BCLKCntl_PD_EN 0x8060 |
| #define B16Gbl_I2S0_BCLKCntl_PD_EN 0x8060 |
| #define LSb32Gbl_I2S0_BCLKCntl_PD_EN 1 |
| #define LSb16Gbl_I2S0_BCLKCntl_PD_EN 1 |
| #define bGbl_I2S0_BCLKCntl_PD_EN 1 |
| #define MSK32Gbl_I2S0_BCLKCntl_PD_EN 0x00000002 |
| #define BA_Gbl_I2S0_BCLKCntl_SLP_DI 0x8060 |
| #define B16Gbl_I2S0_BCLKCntl_SLP_DI 0x8060 |
| #define LSb32Gbl_I2S0_BCLKCntl_SLP_DI 2 |
| #define LSb16Gbl_I2S0_BCLKCntl_SLP_DI 2 |
| #define bGbl_I2S0_BCLKCntl_SLP_DI 1 |
| #define MSK32Gbl_I2S0_BCLKCntl_SLP_DI 0x00000004 |
| #define RA_Gbl_I2S0_LRCKCntl 0x8064 |
| #define BA_Gbl_I2S0_LRCKCntl_PU_EN 0x8064 |
| #define B16Gbl_I2S0_LRCKCntl_PU_EN 0x8064 |
| #define LSb32Gbl_I2S0_LRCKCntl_PU_EN 0 |
| #define LSb16Gbl_I2S0_LRCKCntl_PU_EN 0 |
| #define bGbl_I2S0_LRCKCntl_PU_EN 1 |
| #define MSK32Gbl_I2S0_LRCKCntl_PU_EN 0x00000001 |
| #define BA_Gbl_I2S0_LRCKCntl_PD_EN 0x8064 |
| #define B16Gbl_I2S0_LRCKCntl_PD_EN 0x8064 |
| #define LSb32Gbl_I2S0_LRCKCntl_PD_EN 1 |
| #define LSb16Gbl_I2S0_LRCKCntl_PD_EN 1 |
| #define bGbl_I2S0_LRCKCntl_PD_EN 1 |
| #define MSK32Gbl_I2S0_LRCKCntl_PD_EN 0x00000002 |
| #define BA_Gbl_I2S0_LRCKCntl_SLP_DI 0x8064 |
| #define B16Gbl_I2S0_LRCKCntl_SLP_DI 0x8064 |
| #define LSb32Gbl_I2S0_LRCKCntl_SLP_DI 2 |
| #define LSb16Gbl_I2S0_LRCKCntl_SLP_DI 2 |
| #define bGbl_I2S0_LRCKCntl_SLP_DI 1 |
| #define MSK32Gbl_I2S0_LRCKCntl_SLP_DI 0x00000004 |
| #define RA_Gbl_I2S0_DO0Cntl 0x8068 |
| #define BA_Gbl_I2S0_DO0Cntl_PU_EN 0x8068 |
| #define B16Gbl_I2S0_DO0Cntl_PU_EN 0x8068 |
| #define LSb32Gbl_I2S0_DO0Cntl_PU_EN 0 |
| #define LSb16Gbl_I2S0_DO0Cntl_PU_EN 0 |
| #define bGbl_I2S0_DO0Cntl_PU_EN 1 |
| #define MSK32Gbl_I2S0_DO0Cntl_PU_EN 0x00000001 |
| #define BA_Gbl_I2S0_DO0Cntl_PD_EN 0x8068 |
| #define B16Gbl_I2S0_DO0Cntl_PD_EN 0x8068 |
| #define LSb32Gbl_I2S0_DO0Cntl_PD_EN 1 |
| #define LSb16Gbl_I2S0_DO0Cntl_PD_EN 1 |
| #define bGbl_I2S0_DO0Cntl_PD_EN 1 |
| #define MSK32Gbl_I2S0_DO0Cntl_PD_EN 0x00000002 |
| #define BA_Gbl_I2S0_DO0Cntl_SLP_DI 0x8068 |
| #define B16Gbl_I2S0_DO0Cntl_SLP_DI 0x8068 |
| #define LSb32Gbl_I2S0_DO0Cntl_SLP_DI 2 |
| #define LSb16Gbl_I2S0_DO0Cntl_SLP_DI 2 |
| #define bGbl_I2S0_DO0Cntl_SLP_DI 1 |
| #define MSK32Gbl_I2S0_DO0Cntl_SLP_DI 0x00000004 |
| #define RA_Gbl_I2S0_DO1Cntl 0x806C |
| #define BA_Gbl_I2S0_DO1Cntl_PU_EN 0x806C |
| #define B16Gbl_I2S0_DO1Cntl_PU_EN 0x806C |
| #define LSb32Gbl_I2S0_DO1Cntl_PU_EN 0 |
| #define LSb16Gbl_I2S0_DO1Cntl_PU_EN 0 |
| #define bGbl_I2S0_DO1Cntl_PU_EN 1 |
| #define MSK32Gbl_I2S0_DO1Cntl_PU_EN 0x00000001 |
| #define BA_Gbl_I2S0_DO1Cntl_PD_EN 0x806C |
| #define B16Gbl_I2S0_DO1Cntl_PD_EN 0x806C |
| #define LSb32Gbl_I2S0_DO1Cntl_PD_EN 1 |
| #define LSb16Gbl_I2S0_DO1Cntl_PD_EN 1 |
| #define bGbl_I2S0_DO1Cntl_PD_EN 1 |
| #define MSK32Gbl_I2S0_DO1Cntl_PD_EN 0x00000002 |
| #define BA_Gbl_I2S0_DO1Cntl_SLP_DI 0x806C |
| #define B16Gbl_I2S0_DO1Cntl_SLP_DI 0x806C |
| #define LSb32Gbl_I2S0_DO1Cntl_SLP_DI 2 |
| #define LSb16Gbl_I2S0_DO1Cntl_SLP_DI 2 |
| #define bGbl_I2S0_DO1Cntl_SLP_DI 1 |
| #define MSK32Gbl_I2S0_DO1Cntl_SLP_DI 0x00000004 |
| #define RA_Gbl_I2S0_DO2Cntl 0x8070 |
| #define BA_Gbl_I2S0_DO2Cntl_PU_EN 0x8070 |
| #define B16Gbl_I2S0_DO2Cntl_PU_EN 0x8070 |
| #define LSb32Gbl_I2S0_DO2Cntl_PU_EN 0 |
| #define LSb16Gbl_I2S0_DO2Cntl_PU_EN 0 |
| #define bGbl_I2S0_DO2Cntl_PU_EN 1 |
| #define MSK32Gbl_I2S0_DO2Cntl_PU_EN 0x00000001 |
| #define BA_Gbl_I2S0_DO2Cntl_PD_EN 0x8070 |
| #define B16Gbl_I2S0_DO2Cntl_PD_EN 0x8070 |
| #define LSb32Gbl_I2S0_DO2Cntl_PD_EN 1 |
| #define LSb16Gbl_I2S0_DO2Cntl_PD_EN 1 |
| #define bGbl_I2S0_DO2Cntl_PD_EN 1 |
| #define MSK32Gbl_I2S0_DO2Cntl_PD_EN 0x00000002 |
| #define BA_Gbl_I2S0_DO2Cntl_SLP_DI 0x8070 |
| #define B16Gbl_I2S0_DO2Cntl_SLP_DI 0x8070 |
| #define LSb32Gbl_I2S0_DO2Cntl_SLP_DI 2 |
| #define LSb16Gbl_I2S0_DO2Cntl_SLP_DI 2 |
| #define bGbl_I2S0_DO2Cntl_SLP_DI 1 |
| #define MSK32Gbl_I2S0_DO2Cntl_SLP_DI 0x00000004 |
| #define RA_Gbl_I2S0_DO3Cntl 0x8074 |
| #define BA_Gbl_I2S0_DO3Cntl_PU_EN 0x8074 |
| #define B16Gbl_I2S0_DO3Cntl_PU_EN 0x8074 |
| #define LSb32Gbl_I2S0_DO3Cntl_PU_EN 0 |
| #define LSb16Gbl_I2S0_DO3Cntl_PU_EN 0 |
| #define bGbl_I2S0_DO3Cntl_PU_EN 1 |
| #define MSK32Gbl_I2S0_DO3Cntl_PU_EN 0x00000001 |
| #define BA_Gbl_I2S0_DO3Cntl_PD_EN 0x8074 |
| #define B16Gbl_I2S0_DO3Cntl_PD_EN 0x8074 |
| #define LSb32Gbl_I2S0_DO3Cntl_PD_EN 1 |
| #define LSb16Gbl_I2S0_DO3Cntl_PD_EN 1 |
| #define bGbl_I2S0_DO3Cntl_PD_EN 1 |
| #define MSK32Gbl_I2S0_DO3Cntl_PD_EN 0x00000002 |
| #define BA_Gbl_I2S0_DO3Cntl_SLP_DI 0x8074 |
| #define B16Gbl_I2S0_DO3Cntl_SLP_DI 0x8074 |
| #define LSb32Gbl_I2S0_DO3Cntl_SLP_DI 2 |
| #define LSb16Gbl_I2S0_DO3Cntl_SLP_DI 2 |
| #define bGbl_I2S0_DO3Cntl_SLP_DI 1 |
| #define MSK32Gbl_I2S0_DO3Cntl_SLP_DI 0x00000004 |
| #define RA_Gbl_SPDIFICntl 0x8078 |
| #define BA_Gbl_SPDIFICntl_PU_EN 0x8078 |
| #define B16Gbl_SPDIFICntl_PU_EN 0x8078 |
| #define LSb32Gbl_SPDIFICntl_PU_EN 0 |
| #define LSb16Gbl_SPDIFICntl_PU_EN 0 |
| #define bGbl_SPDIFICntl_PU_EN 1 |
| #define MSK32Gbl_SPDIFICntl_PU_EN 0x00000001 |
| #define BA_Gbl_SPDIFICntl_PD_EN 0x8078 |
| #define B16Gbl_SPDIFICntl_PD_EN 0x8078 |
| #define LSb32Gbl_SPDIFICntl_PD_EN 1 |
| #define LSb16Gbl_SPDIFICntl_PD_EN 1 |
| #define bGbl_SPDIFICntl_PD_EN 1 |
| #define MSK32Gbl_SPDIFICntl_PD_EN 0x00000002 |
| #define BA_Gbl_SPDIFICntl_SLP_DI 0x8078 |
| #define B16Gbl_SPDIFICntl_SLP_DI 0x8078 |
| #define LSb32Gbl_SPDIFICntl_SLP_DI 2 |
| #define LSb16Gbl_SPDIFICntl_SLP_DI 2 |
| #define bGbl_SPDIFICntl_SLP_DI 1 |
| #define MSK32Gbl_SPDIFICntl_SLP_DI 0x00000004 |
| #define RA_Gbl_I2S1_LRCKCntl 0x807C |
| #define BA_Gbl_I2S1_LRCKCntl_PU_EN 0x807C |
| #define B16Gbl_I2S1_LRCKCntl_PU_EN 0x807C |
| #define LSb32Gbl_I2S1_LRCKCntl_PU_EN 0 |
| #define LSb16Gbl_I2S1_LRCKCntl_PU_EN 0 |
| #define bGbl_I2S1_LRCKCntl_PU_EN 1 |
| #define MSK32Gbl_I2S1_LRCKCntl_PU_EN 0x00000001 |
| #define BA_Gbl_I2S1_LRCKCntl_PD_EN 0x807C |
| #define B16Gbl_I2S1_LRCKCntl_PD_EN 0x807C |
| #define LSb32Gbl_I2S1_LRCKCntl_PD_EN 1 |
| #define LSb16Gbl_I2S1_LRCKCntl_PD_EN 1 |
| #define bGbl_I2S1_LRCKCntl_PD_EN 1 |
| #define MSK32Gbl_I2S1_LRCKCntl_PD_EN 0x00000002 |
| #define BA_Gbl_I2S1_LRCKCntl_SLP_DI 0x807C |
| #define B16Gbl_I2S1_LRCKCntl_SLP_DI 0x807C |
| #define LSb32Gbl_I2S1_LRCKCntl_SLP_DI 2 |
| #define LSb16Gbl_I2S1_LRCKCntl_SLP_DI 2 |
| #define bGbl_I2S1_LRCKCntl_SLP_DI 1 |
| #define MSK32Gbl_I2S1_LRCKCntl_SLP_DI 0x00000004 |
| #define RA_Gbl_I2S1_BCLKCntl 0x8080 |
| #define BA_Gbl_I2S1_BCLKCntl_PU_EN 0x8080 |
| #define B16Gbl_I2S1_BCLKCntl_PU_EN 0x8080 |
| #define LSb32Gbl_I2S1_BCLKCntl_PU_EN 0 |
| #define LSb16Gbl_I2S1_BCLKCntl_PU_EN 0 |
| #define bGbl_I2S1_BCLKCntl_PU_EN 1 |
| #define MSK32Gbl_I2S1_BCLKCntl_PU_EN 0x00000001 |
| #define BA_Gbl_I2S1_BCLKCntl_PD_EN 0x8080 |
| #define B16Gbl_I2S1_BCLKCntl_PD_EN 0x8080 |
| #define LSb32Gbl_I2S1_BCLKCntl_PD_EN 1 |
| #define LSb16Gbl_I2S1_BCLKCntl_PD_EN 1 |
| #define bGbl_I2S1_BCLKCntl_PD_EN 1 |
| #define MSK32Gbl_I2S1_BCLKCntl_PD_EN 0x00000002 |
| #define BA_Gbl_I2S1_BCLKCntl_SLP_DI 0x8080 |
| #define B16Gbl_I2S1_BCLKCntl_SLP_DI 0x8080 |
| #define LSb32Gbl_I2S1_BCLKCntl_SLP_DI 2 |
| #define LSb16Gbl_I2S1_BCLKCntl_SLP_DI 2 |
| #define bGbl_I2S1_BCLKCntl_SLP_DI 1 |
| #define MSK32Gbl_I2S1_BCLKCntl_SLP_DI 0x00000004 |
| #define RA_Gbl_I2S1_DOCntl 0x8084 |
| #define BA_Gbl_I2S1_DOCntl_PU_EN 0x8084 |
| #define B16Gbl_I2S1_DOCntl_PU_EN 0x8084 |
| #define LSb32Gbl_I2S1_DOCntl_PU_EN 0 |
| #define LSb16Gbl_I2S1_DOCntl_PU_EN 0 |
| #define bGbl_I2S1_DOCntl_PU_EN 1 |
| #define MSK32Gbl_I2S1_DOCntl_PU_EN 0x00000001 |
| #define BA_Gbl_I2S1_DOCntl_PD_EN 0x8084 |
| #define B16Gbl_I2S1_DOCntl_PD_EN 0x8084 |
| #define LSb32Gbl_I2S1_DOCntl_PD_EN 1 |
| #define LSb16Gbl_I2S1_DOCntl_PD_EN 1 |
| #define bGbl_I2S1_DOCntl_PD_EN 1 |
| #define MSK32Gbl_I2S1_DOCntl_PD_EN 0x00000002 |
| #define BA_Gbl_I2S1_DOCntl_SLP_DI 0x8084 |
| #define B16Gbl_I2S1_DOCntl_SLP_DI 0x8084 |
| #define LSb32Gbl_I2S1_DOCntl_SLP_DI 2 |
| #define LSb16Gbl_I2S1_DOCntl_SLP_DI 2 |
| #define bGbl_I2S1_DOCntl_SLP_DI 1 |
| #define MSK32Gbl_I2S1_DOCntl_SLP_DI 0x00000004 |
| #define RA_Gbl_I2S2_LRCKCntl 0x8088 |
| #define BA_Gbl_I2S2_LRCKCntl_PU_EN 0x8088 |
| #define B16Gbl_I2S2_LRCKCntl_PU_EN 0x8088 |
| #define LSb32Gbl_I2S2_LRCKCntl_PU_EN 0 |
| #define LSb16Gbl_I2S2_LRCKCntl_PU_EN 0 |
| #define bGbl_I2S2_LRCKCntl_PU_EN 1 |
| #define MSK32Gbl_I2S2_LRCKCntl_PU_EN 0x00000001 |
| #define BA_Gbl_I2S2_LRCKCntl_PD_EN 0x8088 |
| #define B16Gbl_I2S2_LRCKCntl_PD_EN 0x8088 |
| #define LSb32Gbl_I2S2_LRCKCntl_PD_EN 1 |
| #define LSb16Gbl_I2S2_LRCKCntl_PD_EN 1 |
| #define bGbl_I2S2_LRCKCntl_PD_EN 1 |
| #define MSK32Gbl_I2S2_LRCKCntl_PD_EN 0x00000002 |
| #define BA_Gbl_I2S2_LRCKCntl_SLP_DI 0x8088 |
| #define B16Gbl_I2S2_LRCKCntl_SLP_DI 0x8088 |
| #define LSb32Gbl_I2S2_LRCKCntl_SLP_DI 2 |
| #define LSb16Gbl_I2S2_LRCKCntl_SLP_DI 2 |
| #define bGbl_I2S2_LRCKCntl_SLP_DI 1 |
| #define MSK32Gbl_I2S2_LRCKCntl_SLP_DI 0x00000004 |
| #define RA_Gbl_I2S2_BCLKCntl 0x808C |
| #define BA_Gbl_I2S2_BCLKCntl_PU_EN 0x808C |
| #define B16Gbl_I2S2_BCLKCntl_PU_EN 0x808C |
| #define LSb32Gbl_I2S2_BCLKCntl_PU_EN 0 |
| #define LSb16Gbl_I2S2_BCLKCntl_PU_EN 0 |
| #define bGbl_I2S2_BCLKCntl_PU_EN 1 |
| #define MSK32Gbl_I2S2_BCLKCntl_PU_EN 0x00000001 |
| #define BA_Gbl_I2S2_BCLKCntl_PD_EN 0x808C |
| #define B16Gbl_I2S2_BCLKCntl_PD_EN 0x808C |
| #define LSb32Gbl_I2S2_BCLKCntl_PD_EN 1 |
| #define LSb16Gbl_I2S2_BCLKCntl_PD_EN 1 |
| #define bGbl_I2S2_BCLKCntl_PD_EN 1 |
| #define MSK32Gbl_I2S2_BCLKCntl_PD_EN 0x00000002 |
| #define BA_Gbl_I2S2_BCLKCntl_SLP_DI 0x808C |
| #define B16Gbl_I2S2_BCLKCntl_SLP_DI 0x808C |
| #define LSb32Gbl_I2S2_BCLKCntl_SLP_DI 2 |
| #define LSb16Gbl_I2S2_BCLKCntl_SLP_DI 2 |
| #define bGbl_I2S2_BCLKCntl_SLP_DI 1 |
| #define MSK32Gbl_I2S2_BCLKCntl_SLP_DI 0x00000004 |
| #define RA_Gbl_I2S2_DI_0Cntl 0x8090 |
| #define BA_Gbl_I2S2_DI_0Cntl_PU_EN 0x8090 |
| #define B16Gbl_I2S2_DI_0Cntl_PU_EN 0x8090 |
| #define LSb32Gbl_I2S2_DI_0Cntl_PU_EN 0 |
| #define LSb16Gbl_I2S2_DI_0Cntl_PU_EN 0 |
| #define bGbl_I2S2_DI_0Cntl_PU_EN 1 |
| #define MSK32Gbl_I2S2_DI_0Cntl_PU_EN 0x00000001 |
| #define BA_Gbl_I2S2_DI_0Cntl_PD_EN 0x8090 |
| #define B16Gbl_I2S2_DI_0Cntl_PD_EN 0x8090 |
| #define LSb32Gbl_I2S2_DI_0Cntl_PD_EN 1 |
| #define LSb16Gbl_I2S2_DI_0Cntl_PD_EN 1 |
| #define bGbl_I2S2_DI_0Cntl_PD_EN 1 |
| #define MSK32Gbl_I2S2_DI_0Cntl_PD_EN 0x00000002 |
| #define BA_Gbl_I2S2_DI_0Cntl_SLP_DI 0x8090 |
| #define B16Gbl_I2S2_DI_0Cntl_SLP_DI 0x8090 |
| #define LSb32Gbl_I2S2_DI_0Cntl_SLP_DI 2 |
| #define LSb16Gbl_I2S2_DI_0Cntl_SLP_DI 2 |
| #define bGbl_I2S2_DI_0Cntl_SLP_DI 1 |
| #define MSK32Gbl_I2S2_DI_0Cntl_SLP_DI 0x00000004 |
| #define RA_Gbl_SPDIFOCntl 0x8094 |
| #define BA_Gbl_SPDIFOCntl_PU_EN 0x8094 |
| #define B16Gbl_SPDIFOCntl_PU_EN 0x8094 |
| #define LSb32Gbl_SPDIFOCntl_PU_EN 0 |
| #define LSb16Gbl_SPDIFOCntl_PU_EN 0 |
| #define bGbl_SPDIFOCntl_PU_EN 1 |
| #define MSK32Gbl_SPDIFOCntl_PU_EN 0x00000001 |
| #define BA_Gbl_SPDIFOCntl_PD_EN 0x8094 |
| #define B16Gbl_SPDIFOCntl_PD_EN 0x8094 |
| #define LSb32Gbl_SPDIFOCntl_PD_EN 1 |
| #define LSb16Gbl_SPDIFOCntl_PD_EN 1 |
| #define bGbl_SPDIFOCntl_PD_EN 1 |
| #define MSK32Gbl_SPDIFOCntl_PD_EN 0x00000002 |
| #define BA_Gbl_SPDIFOCntl_SLP_DI 0x8094 |
| #define B16Gbl_SPDIFOCntl_SLP_DI 0x8094 |
| #define LSb32Gbl_SPDIFOCntl_SLP_DI 2 |
| #define LSb16Gbl_SPDIFOCntl_SLP_DI 2 |
| #define bGbl_SPDIFOCntl_SLP_DI 1 |
| #define MSK32Gbl_SPDIFOCntl_SLP_DI 0x00000004 |
| |
| #endif |
| |
