| /******************************************************************************** |
| * Marvell GPL License Option |
| * |
| * If you received this File from Marvell, you may opt to use, redistribute and/or |
| * modify this File in accordance with the terms and conditions of the General |
| * Public License Version 2, June 1991 (the "GPL License"), a copy of which is |
| * available along with the File in the license.txt file or by writing to the Free |
| * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or |
| * on the worldwide web at http://www.gnu.org/licenses/gpl.txt. |
| * |
| * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED |
| * WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY |
| * DISCLAIMED. The GPL License provides additional details about this warranty |
| * disclaimer. |
| ******************************************************************************/ |
| |
| #ifndef __APB_REG_BASE__ |
| #define __APB_REG_BASE__ |
| |
| //#include "Diag.h" |
| |
| //APB Peripherals |
| #define APB_GPIO0_BASE (MEMMAP_APBPERIF_REG_BASE + 0x0400) |
| #define APB_GPIO1_BASE (MEMMAP_APBPERIF_REG_BASE + 0x0800) |
| #define APB_GPIO2_BASE (MEMMAP_APBPERIF_REG_BASE + 0x0C00) |
| #define APB_GPIO3_BASE (MEMMAP_APBPERIF_REG_BASE + 0x1000) |
| #define APB_I2C0_BASE (MEMMAP_APBPERIF_REG_BASE + 0x1400) |
| #define APB_I2C1_BASE (MEMMAP_APBPERIF_REG_BASE + 0x1800) |
| #define APB_SSI1_BASE (MEMMAP_APBPERIF_REG_BASE + 0x1C00) |
| #define APB_WDT0_BASE (MEMMAP_APBPERIF_REG_BASE + 0x2000) |
| #define APB_WDT1_BASE (MEMMAP_APBPERIF_REG_BASE + 0x2400) |
| #define APB_WDT2_BASE (MEMMAP_APBPERIF_REG_BASE + 0x2800) |
| #define APB_TIMER_BASE (MEMMAP_APBPERIF_REG_BASE + 0x2C00) |
| #define APB_ICTL0_BASE (MEMMAP_APBPERIF_REG_BASE + 0x3000) |
| #define APB_ICTL1_BASE (MEMMAP_APBPERIF_REG_BASE + 0x3400) |
| #define APB_ICTL2_BASE (MEMMAP_APBPERIF_REG_BASE + 0x3800) |
| |
| #define SOC_SM_ITCM_BASE (MEMMAP_SM_REG_BASE) |
| #define SOC_SM_DTCM_BASE (MEMMAP_SM_REG_BASE + 0x20000) |
| #define SOC_SM_APB_REG_BASE (MEMMAP_SM_REG_BASE + 0x40000) |
| |
| #define SM_APB_ICTL_BASE (SOC_SM_APB_REG_BASE) |
| #define SM_APB_WDT0_BASE (SOC_SM_APB_REG_BASE + 0x1000) |
| #define SM_APB_WDT1_BASE (SOC_SM_APB_REG_BASE + 0x2000) |
| #define SM_APB_WDT2_BASE (SOC_SM_APB_REG_BASE + 0x3000) |
| #define SM_APB_TIMERS_BASE (SOC_SM_APB_REG_BASE + 0x4000) |
| #define SM_APB_GPIO1_BASE (SOC_SM_APB_REG_BASE + 0x5000) |
| #define SM_APB_SPI_BASE (SOC_SM_APB_REG_BASE + 0x6000) |
| #define SM_APB_I2C0_BASE (SOC_SM_APB_REG_BASE + 0x7000) |
| #define SM_APB_I2C1_BASE (SOC_SM_APB_REG_BASE + 0x8000) |
| #define SM_APB_UART0_BASE (SOC_SM_APB_REG_BASE + 0x9000) |
| #define SM_APB_UART1_BASE (SOC_SM_APB_REG_BASE + 0xA000) |
| #define SM_APB_UART2_BASE (SOC_SM_APB_REG_BASE + 0xB000) |
| #define SM_APB_GPIO0_BASE (SOC_SM_APB_REG_BASE + 0xC000) |
| #define SM_SYS_CTRL_REG_BASE (SOC_SM_APB_REG_BASE + 0xD000) |
| |
| #define SM_PIN_MUX_REG (SM_SYS_CTRL_REG_BASE + RA_smSysCtl_SM_GSM_SEL) |
| |
| #endif |
