| /* |
| * Copyright ARM Ltd 2002. All rights reserved. |
| * |
| * This implementation of __user_initial_stackheap places the stack and heap |
| * using absolute value parameters. |
| * The memory locations were chosen to be suitable to the Integrator platform. |
| * |
| * The default build implements a one region stack and heap model |
| * To implement a two region model, predefine TWO_REGION_MODEL on the command line. |
| * ie: armasm -g -PD "TWO_REGION_MODEL SETL {TRUE}" uish.s |
| */ |
| |
| #include "memmap.h" |
| #include "ra_gbl.h" |
| |
| #define RA_vProRst_vPro (0x0004) |
| #define RA_vProRst_vproBiu (0x0008) |
| |
| #define PROCESSOR_ID_REG_BASE (0x00 + MEMMAP_PROCESSOR_ID_REG_BASE) |
| |
| #define CHIP_CTRL_REG_BASE (0x00 + MEMMAP_CHIP_CTRL_REG_BASE) |
| #define CHIP_CTRL_PIN_MUX_REG (RA_Gbl_pinMux + CHIP_CTRL_REG_BASE) |
| #define CHIP_CTRL_BOOT_STRAP_REG (RA_Gbl_bootStrap + CHIP_CTRL_REG_BASE) |
| #define CHIP_CTRL_SYS_PLL_CTL (RA_Gbl_sysPllCtl + CHIP_CTRL_REG_BASE) |
| #define CHIP_CTRL_RA_GBL_CLK_SELECT (RA_Gbl_clkSelect + CHIP_CTRL_REG_BASE) |
| #define CHIP_CTRL_RA_GBL_CLK_SWITCH (RA_Gbl_ClkSwitch + CHIP_CTRL_REG_BASE) |
| #define CHIP_CTRL_RESET_TRIGGER_REG (RA_Gbl_ResetTrigger + CHIP_CTRL_REG_BASE) |
| #define CHIP_CTRL_RESET_STATUS_REG (RA_Gbl_ResetStatus + CHIP_CTRL_REG_BASE) |
| |
| #define CHIP_CPU0_RESET_REG (0x0+MEMMAP_SOC_REG_BASE) |
| |
| #define RESET_CPU0_TRIGGER (bCPUConfig_cpuSoftReset<<BA_CPUConfig_cpuSoftReset) |
| #define RESET_CPU1_TRIGGER (bCPUConfig_cpuSoftReset<<BA_CPUConfig_cpuSoftReset) |
| |
| #define CHIP_CTRL1_CPU0_RWCT (MEMMAP_CHIP_CTRL_REG_BASE + RA_Gbl_ChipCntl1) |
| |
| |
| |
| /* |
| * void * __user_read_heap_bottom(void) |
| */ |
| _heap_bottom: |
| .word __heap_start |
| |
| .global __user_read_heap_bottom |
| __user_read_heap_bottom: |
| LDR r0, _heap_bottom |
| BX lr |
| |
| /* |
| * void * __user_read_heap_top(void) |
| */ |
| _heap_top: |
| .word __heap_end |
| |
| .global __user_read_heap_top |
| __user_read_heap_top: |
| LDR r0, _heap_top |
| BX lr |
| |
| /* |
| * void * __get_commands_table_start_address(void) |
| */ |
| _commands_base: |
| .word 0 |
| |
| .global __get_commands_table_start_address |
| __get_commands_table_start_address: |
| LDR r0, _commands_base |
| ADD r0, #0x1000 /* Allocate 4K bytes for commands */ |
| BX lr |
| |
| |
| /* |
| * unsigned int __get_cpu_id(void) |
| */ |
| |
| .global __get_cpu_id |
| __get_cpu_id: |
| LDR r0, =PROCESSOR_ID_REG_BASE |
| LDR r0, [r0] |
| AND r0, r0, #0x03 |
| BX lr |
| |
| |
| /* |
| * __jump_to_target(void *target_address) |
| */ |
| .global __jump_to_target |
| __jump_to_target: |
| BX r0 |
| |
| |
| |
| /* |
| * __reset_cpu(unsigned int cpu_id, void *address) |
| */ |
| |
| .global __reset_cpu |
| __reset_cpu: |
| STMDB sp!, {r2-r5} |
| |
| bl flush_all_dcache |
| |
| /* |
| * turn off vmeta SRAM |
| */ |
| #if !CDP_A0 |
| ldr r7, =0x0 |
| ldr r6, =(MEMMAP_VPRO_REG_BASE + RA_vProRst_vproBiu) //0xf8000008 |
| str r7, [r6] |
| ldr r6, =(MEMMAP_VPRO_REG_BASE + RA_vProRst_vPro) //0xf8000004 |
| str r7, [r6] |
| #endif |
| |
| /* |
| * processor can not reset itself |
| * using jump to replace reset |
| * but MMU has to be turned off first |
| * r1 holds jump address |
| */ |
| MRC p15, 0, r3, c1, c0, 0 /* read CP15 register 1 into r0 */ |
| BIC r3, r3, #0x1 /* clear bit 0 */ |
| MCR p15, 0, r3, c1, c0, 0 /* write value back */ |
| |
| MOV lr, pc |
| BX r0 |