berlin_tools/bootloader/common/chip/as370/A0/diag_pll.c

/*******************************************************************************
 *                 2017 Synaptics Incorporated. All Rights Reserved            *
 * THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF Synaptics.                   *
 * NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT *
 * OF Synaptics OR ANY THIRD PARTY. Synaptics RESERVES THE RIGHT AT ITS SOLE   *
 * DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO Synaptics.  *
 * THIS CODE IS PROVIDED "AS IS". Synaptics MAKES NO WARRANTIES, EXPRESSED,    *
 * IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.  *
 *                                                                             *
 *******************************************************************************/

#include "diag_pll.h"

int get_vco(unsigned int pllbase)
{
	double vco=0;
	Tvsipll_ctrl pllctrl;
	int n_int, n_frac, m;

	PLL_REG_READ(pllbase, 0, pllctrl.u32[0]);
	PLL_REG_READ(pllbase, 1, pllctrl.u32[1]);
	PLL_REG_GET(pllctrl, DN, n_int);
	PLL_REG_GET(pllctrl, DM, m);
	PLL_REG_GET(pllctrl, FRAC, n_frac);

	double nx = n_int + (double)n_frac / (1 << 24);
	vco = FREF * nx / m;

	return (int)vco;
}

CLOCKO_t get_clocko(unsigned int pllbase)
{
	int bypass;
	CLOCKO_t res;
	int pddp, pddp1, dp, dp1;
	Tvsipll_ctrl pllctrl;

	int vco = get_vco(pllbase);

	PLL_REG_READ(pllbase, 4, pllctrl.u32[4]);
	PLL_REG_GET(pllctrl, BYPASS, bypass);

	if (bypass) {
		res.clocko = FREF;
		res.clocko1 = FREF;
	}
	else {
		PLL_REG_READ(pllbase, 3, pllctrl.u32[3]);
		PLL_REG_GET(pllctrl, PDDP, pddp);
		PLL_REG_GET(pllctrl, PDDP1, pddp1);
		PLL_REG_GET(pllctrl, DP, dp);
		PLL_REG_GET(pllctrl, DP1, dp1);

		res.clocko = pddp == 1 ? 0 : vco / dp;
		res.clocko1 = pddp1 == 1 ? 0 : vco / dp1;
	}

	return res;
}

unsigned int get_pll_base(enum E_PLL_SRC pll)
{
	unsigned int pll_base;

	switch (pll) {
	case DIAG_SYSPLL:
		pll_base = MEMMAP_CHIP_CTRL_REG_BASE + RA_Gbl_sysPll;
		break;
	case DIAG_CPUPLL:
		pll_base = MEMMAP_CA7_REG_BASE + RA_CPU_WRP_PLL_REG;
		break;
	case DIAG_MEMPLL:
		pll_base = MEMMAP_MCTRLSS_REG_BASE + RA_MC6Ctrl_memPll;
		break;
	default:
		assert(0);
		break;
	}

	return pll_base;
}


CLOCKO_t diag_get_cpupll()
{
	unsigned int pllbase = get_pll_base(DIAG_CPUPLL);

	return get_clocko(pllbase);
}