| /* |
| * Copyright (C) 2018 Synaptics Incorporated. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED "AS-IS," AND |
| * SYNAPTICS EXPRESSLY DISCLAIMS ALL EXPRESS AND IMPLIED WARRANTIES, |
| * INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| * A PARTICULAR PURPOSE, AND ANY WARRANTIES OF NON-INFRINGEMENT OF ANY |
| * INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT SHALL SYNAPTICS BE LIABLE |
| * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, OR |
| * CONSEQUENTIAL DAMAGES ARISING OUT OF OR IN CONNECTION WITH THE USE |
| * OF THE INFORMATION CONTAINED IN THIS DOCUMENT, HOWEVER CAUSED AND |
| * BASED ON ANY THEORY OF LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| * NEGLIGENCE OR OTHER TORTIOUS ACTION, AND EVEN IF SYNAPTICS WAS |
| * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. IF A TRIBUNAL OF |
| * COMPETENT JURISDICTION DOES NOT PERMIT THE DISCLAIMER OF DIRECT |
| * DAMAGES OR ANY OTHER DAMAGES, SYNAPTICS' TOTAL CUMULATIVE LIABILITY |
| * TO ANY PARTY SHALL NOT EXCEED ONE HUNDRED U.S. DOLLARS. |
| */ |
| #ifndef usbPHY_h |
| #define usbPHY_h (){} |
| |
| |
| #include "ctypes.h" |
| |
| #pragma pack(1) |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| |
| #ifndef _DOCC_H_BITOPS_ |
| #define _DOCC_H_BITOPS_ (){} |
| |
| #define _bSETMASK_(b) ((b)<32 ? (1<<((b)&31)) : 0) |
| #define _NSETMASK_(msb,lsb) (_bSETMASK_((msb)+1)-_bSETMASK_(lsb)) |
| #define _bCLRMASK_(b) (~_bSETMASK_(b)) |
| #define _NCLRMASK_(msb,lsb) (~_NSETMASK_(msb,lsb)) |
| #define _BFGET_(r,msb,lsb) (_NSETMASK_((msb)-(lsb),0)&((r)>>(lsb))) |
| #define _BFSET_(r,msb,lsb,v) do{ (r)&=_NCLRMASK_(msb,lsb); (r)|=_NSETMASK_(msb,lsb)&((v)<<(lsb)); }while(0) |
| |
| #endif |
| |
| |
| |
| ////// |
| /// |
| /// $INTERFACE usbPHY biu (4,4) |
| /// # # ---------------------------------------------------------- |
| /// @ 0x00000 USB_CTRL0 (P) |
| /// %unsigned 1 HSDRV0 0x0 |
| /// ### |
| /// * High speed drive adjustment. |
| /// * Set to 0 for normal operation, |
| /// * set to 1 fro enhanced driving. |
| /// ### |
| /// %unsigned 1 HSDRV1 0x0 |
| /// ### |
| /// * High speed drive adjustment. |
| /// * Set to 0 for normal operation, |
| /// * set to 1 fro enhanced driving. |
| /// ### |
| /// %unsigned 1 CLK_SEL 0x1 |
| /// ### |
| /// * 12M clock source select signal. Set to 0 to select external clock provide by the crystal connected on IO_XIN, IO_XOUT. Set to 1 to select internal clock provided on I_INT_CLK prot. |
| /// ### |
| /// %unsigned 1 HS_CHIRP_EN 0x0 |
| /// ### |
| /// * Chirp mode swing control |
| /// * 1: enhance chirp mode swing |
| /// * 0: normal chirp mode swing |
| /// ### |
| /// %unsigned 4 RES_CTL_REG 0x8 |
| /// ### |
| /// * Terminal resistance manual setting default: |
| /// * 4'b1000 for typical 45ohm. |
| /// ### |
| /// %unsigned 7 PLL_FB_DIV_CTL 0x5E |
| /// ### |
| /// * PLL feedback divider ratio |
| /// * M = PLL_FB_DIV_CTL[6:0] + 2 |
| /// * 7'b0000000 div2 |
| /// * 7'b0000001 div3 |
| /// * 7'b0000010 div4 |
| /// * 7'b0000011 div5 |
| /// * …... |
| /// * 7'b1111111 div129 |
| /// ### |
| /// %unsigned 1 PLL_LOCK_BYPASS 0x0 |
| /// ### |
| /// * Bypass lock detector |
| /// * 0: CLOCK_READY is gnenrated by PLL lock detector. |
| /// * 1: CLOCK_READY is always high (always lock). |
| /// ### |
| /// %unsigned 3 PLL_PRE_DIV_CTL 0x3 |
| /// ### |
| /// * PLL pre-divider ratio |
| /// * N = PLL_PRE_DIV_CTL[2:0] + 2 when pll_pre_minus0p5 = 0; |
| /// * N = PLL_PRE_DIV_CTL[2:0] + 1.5 when pll_pre_minus0p5 = 1; |
| /// ### |
| /// %unsigned 1 PLL_PRE_MINUS0P5 0x0 |
| /// ### |
| /// * PLL N-0.5 divide ratio |
| /// * N = PLL_PRE_DIV_CTL[2:0] + 2 |
| /// ### |
| /// %unsigned 1 TERM_CAL_EN 0x1 |
| /// ### |
| /// * HS and LFS termination calibration enable signal |
| /// * 1: automatic terminal resistance calibration |
| /// * 0: terminal resistance controlled by RES_CTL_REG[3:0] |
| /// ### |
| /// %unsigned 1 BGR_EN 0x1 |
| /// ### |
| /// * To select either bgr/resistive divider or constant Gm |
| /// * 1 = bgr/resistive divider select. |
| /// * 0 = constant gm select. |
| /// ### |
| /// %unsigned 1 RES_DIV_EN 0x0 |
| /// ### |
| /// * 1 = resistive divider will select bgr_en = 1. |
| /// * 0 = bgr will select when bgr_en = 1; |
| /// ### |
| /// %unsigned 1 RES_SEL 0x1 |
| /// ### |
| /// * To select either external resistance or resistance for calibration. |
| /// * 1 = external resistance. |
| /// * 0 = internal resistance. |
| /// ### |
| /// %unsigned 2 CP_INT_CTRL 0x1 |
| /// ### |
| /// * Integral path CP current control |
| /// ### |
| /// %unsigned 2 DRV_SWING_CTL 0x0 |
| /// %unsigned 2 GM_CTRL 0x1 |
| /// ### |
| /// * Zero resistance value control |
| /// ### |
| /// %unsigned 2 KVCCO_CTRL 0x1 |
| /// ### |
| /// * Integral path kvco control |
| /// ### |
| /// @ 0x00004 USB_CTRL1 (P) |
| /// %unsigned 24 TEST 0x0 |
| /// ### |
| /// * Debug signals for analog logic. |
| /// ### |
| /// %unsigned 5 TEST_MODE 0x0 |
| /// ### |
| /// * I_TEST_MODE[0]: 0-NO BIST, 1-BIST active. |
| /// * {I_TEST_MODE[4], I_TEST_MODE[1]}: |
| /// * 2'b00: High Speed BIST |
| /// * 2'b01: Full Speed BIST |
| /// * 2'b10: Low Speed BIST |
| /// * 2'b11: Low speed packet n FSBUS BIST |
| /// * I_TEST_MODE[2]: 0-8 bit interface BIST; 1-16 bit interface BIST. |
| /// * I_TEST_MODE[3]: 0-digital loop back BIST; 1-analog loop back BIST. |
| /// ### |
| /// %unsigned 3 CP_PROP_CTL 0x4 |
| /// ### |
| /// * Proportional path CP current control. |
| /// ### |
| /// # 0x00008 USB_CTRL11 |
| /// %unsigned 1 DP_PULLDOWN 0x0 |
| /// ### |
| /// * Used during loop back test to control DPPD of PHY. |
| /// ### |
| /// %unsigned 1 DM_PULLDOWN 0x0 |
| /// ### |
| /// * Used during loop back test to control DMPD of PHY. |
| /// ### |
| /// %unsigned 2 OPMODE 0x0 |
| /// ### |
| /// * Used during loop back test to control OPMODE of PHY. |
| /// ### |
| /// %unsigned 1 TXBITSTUFFEN 0x0 |
| /// ### |
| /// * Indicates if data on O_DATAOUT[7:0] needs to be bit stuffed or not |
| /// * 0: disable |
| /// * 1: enable |
| /// * *NOT USED** |
| /// ### |
| /// %unsigned 1 TXBITSTUFFENH 0x0 |
| /// ### |
| /// * Indicates if data on O_DATAOUT[15:8] needs to be bit stuffed or not |
| /// * 0: disable |
| /// * 1: enable |
| /// * *NOT USED** |
| /// ### |
| /// %unsigned 5 DIG_DBG_SEL 0x0 |
| /// ### |
| /// * USBOTG PHY signals are mapped onto 24-bit debug bus based on below selection. |
| /// * USBOTG_DIG_DBG_BUS = USBOTG_DBG_SEL == 5'd0 ? 24'd0 : |
| /// * USBOTG_DBG_SEL == 5'd1 ? |
| /// * ({utmi_dataout[7:0], utmi_txvalid, utmi_txvalidh, utmi_databus16_8, SUSPENDM, utmi_xcvrselect[1:0], |
| /// * utmi_termselect, utmi_opmode[1:0], utmi_txready, utmi_linestate[1:0], utmi_hostdisconnect, |
| /// * utmi_iddig,utmi_sessvld,utmi_vbusvalid}): |
| /// * USBOTG_DBG_SEL == 5'd2 ? |
| /// * ({utmi_dataout[15:8],utmi_txvalid, utmi_txvalidh, utmi_databus16_8, SUSPENDM, utmi_xcvrselect[1:0], |
| /// * utmi_termselect, utmi_opmode[1:0], utmi_txready, utmi_idpullup,utmi_dppulldown,utmi_dmpulldown, |
| /// * utmi_chrgvbus,utmi_dischrgvbus}): |
| /// * USBOTG_DBG_SEL == 5'd3 ? |
| /// * ({utmi_datain[7:0], utmi_rxactive,utmi_rxvalid,utmi_rxvalidh,utmi_rxerr, utmi_databus16_8, utmi_xcvrselect[1:0], |
| /// * utmi_termselect, utmi_opmode[1:0], utmi_linestate[1:0], utmi_hostdisconnect, |
| /// * utmi_iddig,utmi_sessvld,utmi_vbusvalid}): |
| /// * USBOTG_DBG_SEL == 5'd4 ? |
| /// * ({utmi_datain[15:8], utmi_rxactive,utmi_rxvalid,utmi_rxvalidh,utmi_rxerr, SUSPENDM, utmi_xcvrselect[1:0], |
| /// * utmi_termselect, utmi_opmode[1:0], utmi_linestate[1:0], utmi_hostdisconnect, |
| /// * utmi_iddig,utmi_sessvld,utmi_vbusvalid}): |
| /// * USBOTG_DBG_SEL == 5'd5 ? |
| /// * ({internal_probes[19:0],hs_eb_data_dbg,squelch_dbg,hs_oe_dbg,hs_dif_rx_out_dbg}): |
| /// * USBOTG_DBG_SEL == 5'd6 ? internal_probes[43:20] : |
| /// * USBOTG_DBG_SEL == 5'd7 ? {6'd0, internal_probes[61:44]} : |
| /// * USBOTG_DBG_SEL == 5'd8 ? internal_probes_p[0*24+23:0*24]: |
| /// * USBOTG_DBG_SEL == 5'd9 ? internal_probes_p[1*24+23:1*24]: |
| /// * USBOTG_DBG_SEL == 5'd10 ? internal_probes_p[2*24+23:2*24]: |
| /// * USBOTG_DBG_SEL == 5'd11 ? internal_probes_p[3*24+23:3*24]: |
| /// * USBOTG_DBG_SEL == 5'd12 ? internal_probes_p[4*24+23:4*24]: |
| /// * USBOTG_DBG_SEL == 5'd13 ? internal_probes_p[5*24+23:5*24]: |
| /// * USBOTG_DBG_SEL == 5'd14 ? internal_probes_p[6*24+23:6*24]: |
| /// * USBOTG_DBG_SEL == 5'd15 ? internal_probes_p[7*24+23:7*24]: |
| /// * USBOTG_DBG_SEL == 5'd16 ? internal_probes_p[8*24+23:8*24]: |
| /// * 24'd0; |
| /// ### |
| /// %% 21 # Stuffing bits... |
| /// @ 0x0000C USB_PHY_RB (WOC-) |
| /// %unsigned 1 LBK_ERR |
| /// ### |
| /// * Asserted when loop back Error is Detected in test mode |
| /// ### |
| /// %% 31 # Stuffing bits... |
| /// @ 0x00010 USB_RB (R-) |
| /// %unsigned 1 CLK_RDY |
| /// ### |
| /// * Debug signal to show that the internal PLL has locked and is ready. 1: ready; 0: not ready. |
| /// ### |
| /// %unsigned 4 RES_CAL_CODE |
| /// ### |
| /// * Resistance calibration code result, which is sent to register for read. |
| /// ### |
| /// %unsigned 1 RCV_SQ_REG |
| /// ### |
| /// * RCV_SQ register value |
| /// ### |
| /// %unsigned 1 SENRCV_REG |
| /// ### |
| /// * SENRCV register value |
| /// ### |
| /// %unsigned 1 SEPRCV_REG |
| /// ### |
| /// * SEPRCV register value |
| /// ### |
| /// %unsigned 1 CLK_READY_REG |
| /// ### |
| /// * CLK_READY register value |
| /// ### |
| /// %unsigned 1 LFSRCV_REG |
| /// ### |
| /// * LFSRCV register value |
| /// ### |
| /// %unsigned 1 RCV_DED_REG |
| /// ### |
| /// * RCV_DED register value |
| /// ### |
| /// %unsigned 1 ID_A_B_REG |
| /// ### |
| /// * ID_A_B register value |
| /// ### |
| /// %unsigned 1 VBUS_VLD_REG |
| /// ### |
| /// * VBUS_VLD register value |
| /// ### |
| /// %unsigned 1 VSESS_VLD_REG |
| /// ### |
| /// * VSESS_VLD register value |
| /// ### |
| /// %unsigned 1 ADPPRB_REG |
| /// ### |
| /// * ADPPRB register value |
| /// ### |
| /// %unsigned 1 ADPSNS_REG |
| /// ### |
| /// * ADPSNS register value |
| /// ### |
| /// %% 16 # Stuffing bits... |
| /// @ 0x00014 OTG_CORE_CTRL (P) |
| /// %unsigned 1 s_bigendian 0x0 |
| /// ### |
| /// * Controls endianess of ahb slave interface of otg mac |
| /// ### |
| /// %unsigned 1 m_bigendian 0x0 |
| /// ### |
| /// * Controls endianess of ahb master interface of otg mac |
| /// ### |
| /// %unsigned 2 ss_scale_down 0x0 |
| /// ### |
| /// * Used to speed up simulation. |
| /// ### |
| /// %% 28 # Stuffing bits... |
| /// # # ---------------------------------------------------------- |
| /// $ENDOFINTERFACE # size: 24B, bits: 96b, padding: 0B |
| //////////////////////////////////////////////////////////// |
| #ifndef h_usbPHY |
| #define h_usbPHY (){} |
| |
| #define RA_usbPHY_USB_CTRL0 0x0000 |
| |
| #define BA_usbPHY_USB_CTRL0_HSDRV0 0x0000 |
| #define B16usbPHY_USB_CTRL0_HSDRV0 0x0000 |
| #define LSb32usbPHY_USB_CTRL0_HSDRV0 0 |
| #define LSb16usbPHY_USB_CTRL0_HSDRV0 0 |
| #define busbPHY_USB_CTRL0_HSDRV0 1 |
| #define MSK32usbPHY_USB_CTRL0_HSDRV0 0x00000001 |
| |
| #define BA_usbPHY_USB_CTRL0_HSDRV1 0x0000 |
| #define B16usbPHY_USB_CTRL0_HSDRV1 0x0000 |
| #define LSb32usbPHY_USB_CTRL0_HSDRV1 1 |
| #define LSb16usbPHY_USB_CTRL0_HSDRV1 1 |
| #define busbPHY_USB_CTRL0_HSDRV1 1 |
| #define MSK32usbPHY_USB_CTRL0_HSDRV1 0x00000002 |
| |
| #define BA_usbPHY_USB_CTRL0_CLK_SEL 0x0000 |
| #define B16usbPHY_USB_CTRL0_CLK_SEL 0x0000 |
| #define LSb32usbPHY_USB_CTRL0_CLK_SEL 2 |
| #define LSb16usbPHY_USB_CTRL0_CLK_SEL 2 |
| #define busbPHY_USB_CTRL0_CLK_SEL 1 |
| #define MSK32usbPHY_USB_CTRL0_CLK_SEL 0x00000004 |
| |
| #define BA_usbPHY_USB_CTRL0_HS_CHIRP_EN 0x0000 |
| #define B16usbPHY_USB_CTRL0_HS_CHIRP_EN 0x0000 |
| #define LSb32usbPHY_USB_CTRL0_HS_CHIRP_EN 3 |
| #define LSb16usbPHY_USB_CTRL0_HS_CHIRP_EN 3 |
| #define busbPHY_USB_CTRL0_HS_CHIRP_EN 1 |
| #define MSK32usbPHY_USB_CTRL0_HS_CHIRP_EN 0x00000008 |
| |
| #define BA_usbPHY_USB_CTRL0_RES_CTL_REG 0x0000 |
| #define B16usbPHY_USB_CTRL0_RES_CTL_REG 0x0000 |
| #define LSb32usbPHY_USB_CTRL0_RES_CTL_REG 4 |
| #define LSb16usbPHY_USB_CTRL0_RES_CTL_REG 4 |
| #define busbPHY_USB_CTRL0_RES_CTL_REG 4 |
| #define MSK32usbPHY_USB_CTRL0_RES_CTL_REG 0x000000F0 |
| |
| #define BA_usbPHY_USB_CTRL0_PLL_FB_DIV_CTL 0x0001 |
| #define B16usbPHY_USB_CTRL0_PLL_FB_DIV_CTL 0x0000 |
| #define LSb32usbPHY_USB_CTRL0_PLL_FB_DIV_CTL 8 |
| #define LSb16usbPHY_USB_CTRL0_PLL_FB_DIV_CTL 8 |
| #define busbPHY_USB_CTRL0_PLL_FB_DIV_CTL 7 |
| #define MSK32usbPHY_USB_CTRL0_PLL_FB_DIV_CTL 0x00007F00 |
| |
| #define BA_usbPHY_USB_CTRL0_PLL_LOCK_BYPASS 0x0001 |
| #define B16usbPHY_USB_CTRL0_PLL_LOCK_BYPASS 0x0000 |
| #define LSb32usbPHY_USB_CTRL0_PLL_LOCK_BYPASS 15 |
| #define LSb16usbPHY_USB_CTRL0_PLL_LOCK_BYPASS 15 |
| #define busbPHY_USB_CTRL0_PLL_LOCK_BYPASS 1 |
| #define MSK32usbPHY_USB_CTRL0_PLL_LOCK_BYPASS 0x00008000 |
| |
| #define BA_usbPHY_USB_CTRL0_PLL_PRE_DIV_CTL 0x0002 |
| #define B16usbPHY_USB_CTRL0_PLL_PRE_DIV_CTL 0x0002 |
| #define LSb32usbPHY_USB_CTRL0_PLL_PRE_DIV_CTL 16 |
| #define LSb16usbPHY_USB_CTRL0_PLL_PRE_DIV_CTL 0 |
| #define busbPHY_USB_CTRL0_PLL_PRE_DIV_CTL 3 |
| #define MSK32usbPHY_USB_CTRL0_PLL_PRE_DIV_CTL 0x00070000 |
| |
| #define BA_usbPHY_USB_CTRL0_PLL_PRE_MINUS0P5 0x0002 |
| #define B16usbPHY_USB_CTRL0_PLL_PRE_MINUS0P5 0x0002 |
| #define LSb32usbPHY_USB_CTRL0_PLL_PRE_MINUS0P5 19 |
| #define LSb16usbPHY_USB_CTRL0_PLL_PRE_MINUS0P5 3 |
| #define busbPHY_USB_CTRL0_PLL_PRE_MINUS0P5 1 |
| #define MSK32usbPHY_USB_CTRL0_PLL_PRE_MINUS0P5 0x00080000 |
| |
| #define BA_usbPHY_USB_CTRL0_TERM_CAL_EN 0x0002 |
| #define B16usbPHY_USB_CTRL0_TERM_CAL_EN 0x0002 |
| #define LSb32usbPHY_USB_CTRL0_TERM_CAL_EN 20 |
| #define LSb16usbPHY_USB_CTRL0_TERM_CAL_EN 4 |
| #define busbPHY_USB_CTRL0_TERM_CAL_EN 1 |
| #define MSK32usbPHY_USB_CTRL0_TERM_CAL_EN 0x00100000 |
| |
| #define BA_usbPHY_USB_CTRL0_BGR_EN 0x0002 |
| #define B16usbPHY_USB_CTRL0_BGR_EN 0x0002 |
| #define LSb32usbPHY_USB_CTRL0_BGR_EN 21 |
| #define LSb16usbPHY_USB_CTRL0_BGR_EN 5 |
| #define busbPHY_USB_CTRL0_BGR_EN 1 |
| #define MSK32usbPHY_USB_CTRL0_BGR_EN 0x00200000 |
| |
| #define BA_usbPHY_USB_CTRL0_RES_DIV_EN 0x0002 |
| #define B16usbPHY_USB_CTRL0_RES_DIV_EN 0x0002 |
| #define LSb32usbPHY_USB_CTRL0_RES_DIV_EN 22 |
| #define LSb16usbPHY_USB_CTRL0_RES_DIV_EN 6 |
| #define busbPHY_USB_CTRL0_RES_DIV_EN 1 |
| #define MSK32usbPHY_USB_CTRL0_RES_DIV_EN 0x00400000 |
| |
| #define BA_usbPHY_USB_CTRL0_RES_SEL 0x0002 |
| #define B16usbPHY_USB_CTRL0_RES_SEL 0x0002 |
| #define LSb32usbPHY_USB_CTRL0_RES_SEL 23 |
| #define LSb16usbPHY_USB_CTRL0_RES_SEL 7 |
| #define busbPHY_USB_CTRL0_RES_SEL 1 |
| #define MSK32usbPHY_USB_CTRL0_RES_SEL 0x00800000 |
| |
| #define BA_usbPHY_USB_CTRL0_CP_INT_CTRL 0x0003 |
| #define B16usbPHY_USB_CTRL0_CP_INT_CTRL 0x0002 |
| #define LSb32usbPHY_USB_CTRL0_CP_INT_CTRL 24 |
| #define LSb16usbPHY_USB_CTRL0_CP_INT_CTRL 8 |
| #define busbPHY_USB_CTRL0_CP_INT_CTRL 2 |
| #define MSK32usbPHY_USB_CTRL0_CP_INT_CTRL 0x03000000 |
| |
| #define BA_usbPHY_USB_CTRL0_DRV_SWING_CTL 0x0003 |
| #define B16usbPHY_USB_CTRL0_DRV_SWING_CTL 0x0002 |
| #define LSb32usbPHY_USB_CTRL0_DRV_SWING_CTL 26 |
| #define LSb16usbPHY_USB_CTRL0_DRV_SWING_CTL 10 |
| #define busbPHY_USB_CTRL0_DRV_SWING_CTL 2 |
| #define MSK32usbPHY_USB_CTRL0_DRV_SWING_CTL 0x0C000000 |
| |
| #define BA_usbPHY_USB_CTRL0_GM_CTRL 0x0003 |
| #define B16usbPHY_USB_CTRL0_GM_CTRL 0x0002 |
| #define LSb32usbPHY_USB_CTRL0_GM_CTRL 28 |
| #define LSb16usbPHY_USB_CTRL0_GM_CTRL 12 |
| #define busbPHY_USB_CTRL0_GM_CTRL 2 |
| #define MSK32usbPHY_USB_CTRL0_GM_CTRL 0x30000000 |
| |
| #define BA_usbPHY_USB_CTRL0_KVCCO_CTRL 0x0003 |
| #define B16usbPHY_USB_CTRL0_KVCCO_CTRL 0x0002 |
| #define LSb32usbPHY_USB_CTRL0_KVCCO_CTRL 30 |
| #define LSb16usbPHY_USB_CTRL0_KVCCO_CTRL 14 |
| #define busbPHY_USB_CTRL0_KVCCO_CTRL 2 |
| #define MSK32usbPHY_USB_CTRL0_KVCCO_CTRL 0xC0000000 |
| /////////////////////////////////////////////////////////// |
| #define RA_usbPHY_USB_CTRL1 0x0004 |
| |
| #define BA_usbPHY_USB_CTRL1_TEST 0x0004 |
| #define B16usbPHY_USB_CTRL1_TEST 0x0004 |
| #define LSb32usbPHY_USB_CTRL1_TEST 0 |
| #define LSb16usbPHY_USB_CTRL1_TEST 0 |
| #define busbPHY_USB_CTRL1_TEST 24 |
| #define MSK32usbPHY_USB_CTRL1_TEST 0x00FFFFFF |
| |
| #define BA_usbPHY_USB_CTRL1_TEST_MODE 0x0007 |
| #define B16usbPHY_USB_CTRL1_TEST_MODE 0x0006 |
| #define LSb32usbPHY_USB_CTRL1_TEST_MODE 24 |
| #define LSb16usbPHY_USB_CTRL1_TEST_MODE 8 |
| #define busbPHY_USB_CTRL1_TEST_MODE 5 |
| #define MSK32usbPHY_USB_CTRL1_TEST_MODE 0x1F000000 |
| |
| #define BA_usbPHY_USB_CTRL1_CP_PROP_CTL 0x0007 |
| #define B16usbPHY_USB_CTRL1_CP_PROP_CTL 0x0006 |
| #define LSb32usbPHY_USB_CTRL1_CP_PROP_CTL 29 |
| #define LSb16usbPHY_USB_CTRL1_CP_PROP_CTL 13 |
| #define busbPHY_USB_CTRL1_CP_PROP_CTL 3 |
| #define MSK32usbPHY_USB_CTRL1_CP_PROP_CTL 0xE0000000 |
| |
| #define RA_usbPHY_USB_CTRL11 0x0008 |
| |
| #define BA_usbPHY_USB_CTRL1_DP_PULLDOWN 0x0008 |
| #define B16usbPHY_USB_CTRL1_DP_PULLDOWN 0x0008 |
| #define LSb32usbPHY_USB_CTRL1_DP_PULLDOWN 0 |
| #define LSb16usbPHY_USB_CTRL1_DP_PULLDOWN 0 |
| #define busbPHY_USB_CTRL1_DP_PULLDOWN 1 |
| #define MSK32usbPHY_USB_CTRL1_DP_PULLDOWN 0x00000001 |
| |
| #define BA_usbPHY_USB_CTRL1_DM_PULLDOWN 0x0008 |
| #define B16usbPHY_USB_CTRL1_DM_PULLDOWN 0x0008 |
| #define LSb32usbPHY_USB_CTRL1_DM_PULLDOWN 1 |
| #define LSb16usbPHY_USB_CTRL1_DM_PULLDOWN 1 |
| #define busbPHY_USB_CTRL1_DM_PULLDOWN 1 |
| #define MSK32usbPHY_USB_CTRL1_DM_PULLDOWN 0x00000002 |
| |
| #define BA_usbPHY_USB_CTRL1_OPMODE 0x0008 |
| #define B16usbPHY_USB_CTRL1_OPMODE 0x0008 |
| #define LSb32usbPHY_USB_CTRL1_OPMODE 2 |
| #define LSb16usbPHY_USB_CTRL1_OPMODE 2 |
| #define busbPHY_USB_CTRL1_OPMODE 2 |
| #define MSK32usbPHY_USB_CTRL1_OPMODE 0x0000000C |
| |
| #define BA_usbPHY_USB_CTRL1_TXBITSTUFFEN 0x0008 |
| #define B16usbPHY_USB_CTRL1_TXBITSTUFFEN 0x0008 |
| #define LSb32usbPHY_USB_CTRL1_TXBITSTUFFEN 4 |
| #define LSb16usbPHY_USB_CTRL1_TXBITSTUFFEN 4 |
| #define busbPHY_USB_CTRL1_TXBITSTUFFEN 1 |
| #define MSK32usbPHY_USB_CTRL1_TXBITSTUFFEN 0x00000010 |
| |
| #define BA_usbPHY_USB_CTRL1_TXBITSTUFFENH 0x0008 |
| #define B16usbPHY_USB_CTRL1_TXBITSTUFFENH 0x0008 |
| #define LSb32usbPHY_USB_CTRL1_TXBITSTUFFENH 5 |
| #define LSb16usbPHY_USB_CTRL1_TXBITSTUFFENH 5 |
| #define busbPHY_USB_CTRL1_TXBITSTUFFENH 1 |
| #define MSK32usbPHY_USB_CTRL1_TXBITSTUFFENH 0x00000020 |
| |
| #define BA_usbPHY_USB_CTRL1_DIG_DBG_SEL 0x0008 |
| #define B16usbPHY_USB_CTRL1_DIG_DBG_SEL 0x0008 |
| #define LSb32usbPHY_USB_CTRL1_DIG_DBG_SEL 6 |
| #define LSb16usbPHY_USB_CTRL1_DIG_DBG_SEL 6 |
| #define busbPHY_USB_CTRL1_DIG_DBG_SEL 5 |
| #define MSK32usbPHY_USB_CTRL1_DIG_DBG_SEL 0x000007C0 |
| /////////////////////////////////////////////////////////// |
| #define RA_usbPHY_USB_PHY_RB 0x000C |
| |
| #define BA_usbPHY_USB_PHY_RB_LBK_ERR 0x000C |
| #define B16usbPHY_USB_PHY_RB_LBK_ERR 0x000C |
| #define LSb32usbPHY_USB_PHY_RB_LBK_ERR 0 |
| #define LSb16usbPHY_USB_PHY_RB_LBK_ERR 0 |
| #define busbPHY_USB_PHY_RB_LBK_ERR 1 |
| #define MSK32usbPHY_USB_PHY_RB_LBK_ERR 0x00000001 |
| /////////////////////////////////////////////////////////// |
| #define RA_usbPHY_USB_RB 0x0010 |
| |
| #define BA_usbPHY_USB_RB_CLK_RDY 0x0010 |
| #define B16usbPHY_USB_RB_CLK_RDY 0x0010 |
| #define LSb32usbPHY_USB_RB_CLK_RDY 0 |
| #define LSb16usbPHY_USB_RB_CLK_RDY 0 |
| #define busbPHY_USB_RB_CLK_RDY 1 |
| #define MSK32usbPHY_USB_RB_CLK_RDY 0x00000001 |
| |
| #define BA_usbPHY_USB_RB_RES_CAL_CODE 0x0010 |
| #define B16usbPHY_USB_RB_RES_CAL_CODE 0x0010 |
| #define LSb32usbPHY_USB_RB_RES_CAL_CODE 1 |
| #define LSb16usbPHY_USB_RB_RES_CAL_CODE 1 |
| #define busbPHY_USB_RB_RES_CAL_CODE 4 |
| #define MSK32usbPHY_USB_RB_RES_CAL_CODE 0x0000001E |
| |
| #define BA_usbPHY_USB_RB_RCV_SQ_REG 0x0010 |
| #define B16usbPHY_USB_RB_RCV_SQ_REG 0x0010 |
| #define LSb32usbPHY_USB_RB_RCV_SQ_REG 5 |
| #define LSb16usbPHY_USB_RB_RCV_SQ_REG 5 |
| #define busbPHY_USB_RB_RCV_SQ_REG 1 |
| #define MSK32usbPHY_USB_RB_RCV_SQ_REG 0x00000020 |
| |
| #define BA_usbPHY_USB_RB_SENRCV_REG 0x0010 |
| #define B16usbPHY_USB_RB_SENRCV_REG 0x0010 |
| #define LSb32usbPHY_USB_RB_SENRCV_REG 6 |
| #define LSb16usbPHY_USB_RB_SENRCV_REG 6 |
| #define busbPHY_USB_RB_SENRCV_REG 1 |
| #define MSK32usbPHY_USB_RB_SENRCV_REG 0x00000040 |
| |
| #define BA_usbPHY_USB_RB_SEPRCV_REG 0x0010 |
| #define B16usbPHY_USB_RB_SEPRCV_REG 0x0010 |
| #define LSb32usbPHY_USB_RB_SEPRCV_REG 7 |
| #define LSb16usbPHY_USB_RB_SEPRCV_REG 7 |
| #define busbPHY_USB_RB_SEPRCV_REG 1 |
| #define MSK32usbPHY_USB_RB_SEPRCV_REG 0x00000080 |
| |
| #define BA_usbPHY_USB_RB_CLK_READY_REG 0x0011 |
| #define B16usbPHY_USB_RB_CLK_READY_REG 0x0010 |
| #define LSb32usbPHY_USB_RB_CLK_READY_REG 8 |
| #define LSb16usbPHY_USB_RB_CLK_READY_REG 8 |
| #define busbPHY_USB_RB_CLK_READY_REG 1 |
| #define MSK32usbPHY_USB_RB_CLK_READY_REG 0x00000100 |
| |
| #define BA_usbPHY_USB_RB_LFSRCV_REG 0x0011 |
| #define B16usbPHY_USB_RB_LFSRCV_REG 0x0010 |
| #define LSb32usbPHY_USB_RB_LFSRCV_REG 9 |
| #define LSb16usbPHY_USB_RB_LFSRCV_REG 9 |
| #define busbPHY_USB_RB_LFSRCV_REG 1 |
| #define MSK32usbPHY_USB_RB_LFSRCV_REG 0x00000200 |
| |
| #define BA_usbPHY_USB_RB_RCV_DED_REG 0x0011 |
| #define B16usbPHY_USB_RB_RCV_DED_REG 0x0010 |
| #define LSb32usbPHY_USB_RB_RCV_DED_REG 10 |
| #define LSb16usbPHY_USB_RB_RCV_DED_REG 10 |
| #define busbPHY_USB_RB_RCV_DED_REG 1 |
| #define MSK32usbPHY_USB_RB_RCV_DED_REG 0x00000400 |
| |
| #define BA_usbPHY_USB_RB_ID_A_B_REG 0x0011 |
| #define B16usbPHY_USB_RB_ID_A_B_REG 0x0010 |
| #define LSb32usbPHY_USB_RB_ID_A_B_REG 11 |
| #define LSb16usbPHY_USB_RB_ID_A_B_REG 11 |
| #define busbPHY_USB_RB_ID_A_B_REG 1 |
| #define MSK32usbPHY_USB_RB_ID_A_B_REG 0x00000800 |
| |
| #define BA_usbPHY_USB_RB_VBUS_VLD_REG 0x0011 |
| #define B16usbPHY_USB_RB_VBUS_VLD_REG 0x0010 |
| #define LSb32usbPHY_USB_RB_VBUS_VLD_REG 12 |
| #define LSb16usbPHY_USB_RB_VBUS_VLD_REG 12 |
| #define busbPHY_USB_RB_VBUS_VLD_REG 1 |
| #define MSK32usbPHY_USB_RB_VBUS_VLD_REG 0x00001000 |
| |
| #define BA_usbPHY_USB_RB_VSESS_VLD_REG 0x0011 |
| #define B16usbPHY_USB_RB_VSESS_VLD_REG 0x0010 |
| #define LSb32usbPHY_USB_RB_VSESS_VLD_REG 13 |
| #define LSb16usbPHY_USB_RB_VSESS_VLD_REG 13 |
| #define busbPHY_USB_RB_VSESS_VLD_REG 1 |
| #define MSK32usbPHY_USB_RB_VSESS_VLD_REG 0x00002000 |
| |
| #define BA_usbPHY_USB_RB_ADPPRB_REG 0x0011 |
| #define B16usbPHY_USB_RB_ADPPRB_REG 0x0010 |
| #define LSb32usbPHY_USB_RB_ADPPRB_REG 14 |
| #define LSb16usbPHY_USB_RB_ADPPRB_REG 14 |
| #define busbPHY_USB_RB_ADPPRB_REG 1 |
| #define MSK32usbPHY_USB_RB_ADPPRB_REG 0x00004000 |
| |
| #define BA_usbPHY_USB_RB_ADPSNS_REG 0x0011 |
| #define B16usbPHY_USB_RB_ADPSNS_REG 0x0010 |
| #define LSb32usbPHY_USB_RB_ADPSNS_REG 15 |
| #define LSb16usbPHY_USB_RB_ADPSNS_REG 15 |
| #define busbPHY_USB_RB_ADPSNS_REG 1 |
| #define MSK32usbPHY_USB_RB_ADPSNS_REG 0x00008000 |
| /////////////////////////////////////////////////////////// |
| #define RA_usbPHY_OTG_CORE_CTRL 0x0014 |
| |
| #define BA_usbPHY_OTG_CORE_CTRL_s_bigendian 0x0014 |
| #define B16usbPHY_OTG_CORE_CTRL_s_bigendian 0x0014 |
| #define LSb32usbPHY_OTG_CORE_CTRL_s_bigendian 0 |
| #define LSb16usbPHY_OTG_CORE_CTRL_s_bigendian 0 |
| #define busbPHY_OTG_CORE_CTRL_s_bigendian 1 |
| #define MSK32usbPHY_OTG_CORE_CTRL_s_bigendian 0x00000001 |
| |
| #define BA_usbPHY_OTG_CORE_CTRL_m_bigendian 0x0014 |
| #define B16usbPHY_OTG_CORE_CTRL_m_bigendian 0x0014 |
| #define LSb32usbPHY_OTG_CORE_CTRL_m_bigendian 1 |
| #define LSb16usbPHY_OTG_CORE_CTRL_m_bigendian 1 |
| #define busbPHY_OTG_CORE_CTRL_m_bigendian 1 |
| #define MSK32usbPHY_OTG_CORE_CTRL_m_bigendian 0x00000002 |
| |
| #define BA_usbPHY_OTG_CORE_CTRL_ss_scale_down 0x0014 |
| #define B16usbPHY_OTG_CORE_CTRL_ss_scale_down 0x0014 |
| #define LSb32usbPHY_OTG_CORE_CTRL_ss_scale_down 2 |
| #define LSb16usbPHY_OTG_CORE_CTRL_ss_scale_down 2 |
| #define busbPHY_OTG_CORE_CTRL_ss_scale_down 2 |
| #define MSK32usbPHY_OTG_CORE_CTRL_ss_scale_down 0x0000000C |
| /////////////////////////////////////////////////////////// |
| |
| typedef struct SIE_usbPHY { |
| /////////////////////////////////////////////////////////// |
| #define GET32usbPHY_USB_CTRL0_HSDRV0(r32) _BFGET_(r32, 0, 0) |
| #define SET32usbPHY_USB_CTRL0_HSDRV0(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16usbPHY_USB_CTRL0_HSDRV0(r16) _BFGET_(r16, 0, 0) |
| #define SET16usbPHY_USB_CTRL0_HSDRV0(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32usbPHY_USB_CTRL0_HSDRV1(r32) _BFGET_(r32, 1, 1) |
| #define SET32usbPHY_USB_CTRL0_HSDRV1(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16usbPHY_USB_CTRL0_HSDRV1(r16) _BFGET_(r16, 1, 1) |
| #define SET16usbPHY_USB_CTRL0_HSDRV1(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32usbPHY_USB_CTRL0_CLK_SEL(r32) _BFGET_(r32, 2, 2) |
| #define SET32usbPHY_USB_CTRL0_CLK_SEL(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16usbPHY_USB_CTRL0_CLK_SEL(r16) _BFGET_(r16, 2, 2) |
| #define SET16usbPHY_USB_CTRL0_CLK_SEL(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32usbPHY_USB_CTRL0_HS_CHIRP_EN(r32) _BFGET_(r32, 3, 3) |
| #define SET32usbPHY_USB_CTRL0_HS_CHIRP_EN(r32,v) _BFSET_(r32, 3, 3,v) |
| #define GET16usbPHY_USB_CTRL0_HS_CHIRP_EN(r16) _BFGET_(r16, 3, 3) |
| #define SET16usbPHY_USB_CTRL0_HS_CHIRP_EN(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32usbPHY_USB_CTRL0_RES_CTL_REG(r32) _BFGET_(r32, 7, 4) |
| #define SET32usbPHY_USB_CTRL0_RES_CTL_REG(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16usbPHY_USB_CTRL0_RES_CTL_REG(r16) _BFGET_(r16, 7, 4) |
| #define SET16usbPHY_USB_CTRL0_RES_CTL_REG(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define GET32usbPHY_USB_CTRL0_PLL_FB_DIV_CTL(r32) _BFGET_(r32,14, 8) |
| #define SET32usbPHY_USB_CTRL0_PLL_FB_DIV_CTL(r32,v) _BFSET_(r32,14, 8,v) |
| #define GET16usbPHY_USB_CTRL0_PLL_FB_DIV_CTL(r16) _BFGET_(r16,14, 8) |
| #define SET16usbPHY_USB_CTRL0_PLL_FB_DIV_CTL(r16,v) _BFSET_(r16,14, 8,v) |
| |
| #define GET32usbPHY_USB_CTRL0_PLL_LOCK_BYPASS(r32) _BFGET_(r32,15,15) |
| #define SET32usbPHY_USB_CTRL0_PLL_LOCK_BYPASS(r32,v) _BFSET_(r32,15,15,v) |
| #define GET16usbPHY_USB_CTRL0_PLL_LOCK_BYPASS(r16) _BFGET_(r16,15,15) |
| #define SET16usbPHY_USB_CTRL0_PLL_LOCK_BYPASS(r16,v) _BFSET_(r16,15,15,v) |
| |
| #define GET32usbPHY_USB_CTRL0_PLL_PRE_DIV_CTL(r32) _BFGET_(r32,18,16) |
| #define SET32usbPHY_USB_CTRL0_PLL_PRE_DIV_CTL(r32,v) _BFSET_(r32,18,16,v) |
| #define GET16usbPHY_USB_CTRL0_PLL_PRE_DIV_CTL(r16) _BFGET_(r16, 2, 0) |
| #define SET16usbPHY_USB_CTRL0_PLL_PRE_DIV_CTL(r16,v) _BFSET_(r16, 2, 0,v) |
| |
| #define GET32usbPHY_USB_CTRL0_PLL_PRE_MINUS0P5(r32) _BFGET_(r32,19,19) |
| #define SET32usbPHY_USB_CTRL0_PLL_PRE_MINUS0P5(r32,v) _BFSET_(r32,19,19,v) |
| #define GET16usbPHY_USB_CTRL0_PLL_PRE_MINUS0P5(r16) _BFGET_(r16, 3, 3) |
| #define SET16usbPHY_USB_CTRL0_PLL_PRE_MINUS0P5(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32usbPHY_USB_CTRL0_TERM_CAL_EN(r32) _BFGET_(r32,20,20) |
| #define SET32usbPHY_USB_CTRL0_TERM_CAL_EN(r32,v) _BFSET_(r32,20,20,v) |
| #define GET16usbPHY_USB_CTRL0_TERM_CAL_EN(r16) _BFGET_(r16, 4, 4) |
| #define SET16usbPHY_USB_CTRL0_TERM_CAL_EN(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32usbPHY_USB_CTRL0_BGR_EN(r32) _BFGET_(r32,21,21) |
| #define SET32usbPHY_USB_CTRL0_BGR_EN(r32,v) _BFSET_(r32,21,21,v) |
| #define GET16usbPHY_USB_CTRL0_BGR_EN(r16) _BFGET_(r16, 5, 5) |
| #define SET16usbPHY_USB_CTRL0_BGR_EN(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define GET32usbPHY_USB_CTRL0_RES_DIV_EN(r32) _BFGET_(r32,22,22) |
| #define SET32usbPHY_USB_CTRL0_RES_DIV_EN(r32,v) _BFSET_(r32,22,22,v) |
| #define GET16usbPHY_USB_CTRL0_RES_DIV_EN(r16) _BFGET_(r16, 6, 6) |
| #define SET16usbPHY_USB_CTRL0_RES_DIV_EN(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32usbPHY_USB_CTRL0_RES_SEL(r32) _BFGET_(r32,23,23) |
| #define SET32usbPHY_USB_CTRL0_RES_SEL(r32,v) _BFSET_(r32,23,23,v) |
| #define GET16usbPHY_USB_CTRL0_RES_SEL(r16) _BFGET_(r16, 7, 7) |
| #define SET16usbPHY_USB_CTRL0_RES_SEL(r16,v) _BFSET_(r16, 7, 7,v) |
| |
| #define GET32usbPHY_USB_CTRL0_CP_INT_CTRL(r32) _BFGET_(r32,25,24) |
| #define SET32usbPHY_USB_CTRL0_CP_INT_CTRL(r32,v) _BFSET_(r32,25,24,v) |
| #define GET16usbPHY_USB_CTRL0_CP_INT_CTRL(r16) _BFGET_(r16, 9, 8) |
| #define SET16usbPHY_USB_CTRL0_CP_INT_CTRL(r16,v) _BFSET_(r16, 9, 8,v) |
| |
| #define GET32usbPHY_USB_CTRL0_DRV_SWING_CTL(r32) _BFGET_(r32,27,26) |
| #define SET32usbPHY_USB_CTRL0_DRV_SWING_CTL(r32,v) _BFSET_(r32,27,26,v) |
| #define GET16usbPHY_USB_CTRL0_DRV_SWING_CTL(r16) _BFGET_(r16,11,10) |
| #define SET16usbPHY_USB_CTRL0_DRV_SWING_CTL(r16,v) _BFSET_(r16,11,10,v) |
| |
| #define GET32usbPHY_USB_CTRL0_GM_CTRL(r32) _BFGET_(r32,29,28) |
| #define SET32usbPHY_USB_CTRL0_GM_CTRL(r32,v) _BFSET_(r32,29,28,v) |
| #define GET16usbPHY_USB_CTRL0_GM_CTRL(r16) _BFGET_(r16,13,12) |
| #define SET16usbPHY_USB_CTRL0_GM_CTRL(r16,v) _BFSET_(r16,13,12,v) |
| |
| #define GET32usbPHY_USB_CTRL0_KVCCO_CTRL(r32) _BFGET_(r32,31,30) |
| #define SET32usbPHY_USB_CTRL0_KVCCO_CTRL(r32,v) _BFSET_(r32,31,30,v) |
| #define GET16usbPHY_USB_CTRL0_KVCCO_CTRL(r16) _BFGET_(r16,15,14) |
| #define SET16usbPHY_USB_CTRL0_KVCCO_CTRL(r16,v) _BFSET_(r16,15,14,v) |
| |
| #define w32usbPHY_USB_CTRL0 {\ |
| UNSG32 uUSB_CTRL0_HSDRV0 : 1;\ |
| UNSG32 uUSB_CTRL0_HSDRV1 : 1;\ |
| UNSG32 uUSB_CTRL0_CLK_SEL : 1;\ |
| UNSG32 uUSB_CTRL0_HS_CHIRP_EN : 1;\ |
| UNSG32 uUSB_CTRL0_RES_CTL_REG : 4;\ |
| UNSG32 uUSB_CTRL0_PLL_FB_DIV_CTL : 7;\ |
| UNSG32 uUSB_CTRL0_PLL_LOCK_BYPASS : 1;\ |
| UNSG32 uUSB_CTRL0_PLL_PRE_DIV_CTL : 3;\ |
| UNSG32 uUSB_CTRL0_PLL_PRE_MINUS0P5 : 1;\ |
| UNSG32 uUSB_CTRL0_TERM_CAL_EN : 1;\ |
| UNSG32 uUSB_CTRL0_BGR_EN : 1;\ |
| UNSG32 uUSB_CTRL0_RES_DIV_EN : 1;\ |
| UNSG32 uUSB_CTRL0_RES_SEL : 1;\ |
| UNSG32 uUSB_CTRL0_CP_INT_CTRL : 2;\ |
| UNSG32 uUSB_CTRL0_DRV_SWING_CTL : 2;\ |
| UNSG32 uUSB_CTRL0_GM_CTRL : 2;\ |
| UNSG32 uUSB_CTRL0_KVCCO_CTRL : 2;\ |
| } |
| union { UNSG32 u32usbPHY_USB_CTRL0; |
| struct w32usbPHY_USB_CTRL0; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32usbPHY_USB_CTRL1_TEST(r32) _BFGET_(r32,23, 0) |
| #define SET32usbPHY_USB_CTRL1_TEST(r32,v) _BFSET_(r32,23, 0,v) |
| |
| #define GET32usbPHY_USB_CTRL1_TEST_MODE(r32) _BFGET_(r32,28,24) |
| #define SET32usbPHY_USB_CTRL1_TEST_MODE(r32,v) _BFSET_(r32,28,24,v) |
| #define GET16usbPHY_USB_CTRL1_TEST_MODE(r16) _BFGET_(r16,12, 8) |
| #define SET16usbPHY_USB_CTRL1_TEST_MODE(r16,v) _BFSET_(r16,12, 8,v) |
| |
| #define GET32usbPHY_USB_CTRL1_CP_PROP_CTL(r32) _BFGET_(r32,31,29) |
| #define SET32usbPHY_USB_CTRL1_CP_PROP_CTL(r32,v) _BFSET_(r32,31,29,v) |
| #define GET16usbPHY_USB_CTRL1_CP_PROP_CTL(r16) _BFGET_(r16,15,13) |
| #define SET16usbPHY_USB_CTRL1_CP_PROP_CTL(r16,v) _BFSET_(r16,15,13,v) |
| |
| #define w32usbPHY_USB_CTRL1 {\ |
| UNSG32 uUSB_CTRL1_TEST : 24;\ |
| UNSG32 uUSB_CTRL1_TEST_MODE : 5;\ |
| UNSG32 uUSB_CTRL1_CP_PROP_CTL : 3;\ |
| } |
| union { UNSG32 u32usbPHY_USB_CTRL1; |
| struct w32usbPHY_USB_CTRL1; |
| }; |
| #define GET32usbPHY_USB_CTRL1_DP_PULLDOWN(r32) _BFGET_(r32, 0, 0) |
| #define SET32usbPHY_USB_CTRL1_DP_PULLDOWN(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16usbPHY_USB_CTRL1_DP_PULLDOWN(r16) _BFGET_(r16, 0, 0) |
| #define SET16usbPHY_USB_CTRL1_DP_PULLDOWN(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32usbPHY_USB_CTRL1_DM_PULLDOWN(r32) _BFGET_(r32, 1, 1) |
| #define SET32usbPHY_USB_CTRL1_DM_PULLDOWN(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16usbPHY_USB_CTRL1_DM_PULLDOWN(r16) _BFGET_(r16, 1, 1) |
| #define SET16usbPHY_USB_CTRL1_DM_PULLDOWN(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32usbPHY_USB_CTRL1_OPMODE(r32) _BFGET_(r32, 3, 2) |
| #define SET32usbPHY_USB_CTRL1_OPMODE(r32,v) _BFSET_(r32, 3, 2,v) |
| #define GET16usbPHY_USB_CTRL1_OPMODE(r16) _BFGET_(r16, 3, 2) |
| #define SET16usbPHY_USB_CTRL1_OPMODE(r16,v) _BFSET_(r16, 3, 2,v) |
| |
| #define GET32usbPHY_USB_CTRL1_TXBITSTUFFEN(r32) _BFGET_(r32, 4, 4) |
| #define SET32usbPHY_USB_CTRL1_TXBITSTUFFEN(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16usbPHY_USB_CTRL1_TXBITSTUFFEN(r16) _BFGET_(r16, 4, 4) |
| #define SET16usbPHY_USB_CTRL1_TXBITSTUFFEN(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32usbPHY_USB_CTRL1_TXBITSTUFFENH(r32) _BFGET_(r32, 5, 5) |
| #define SET32usbPHY_USB_CTRL1_TXBITSTUFFENH(r32,v) _BFSET_(r32, 5, 5,v) |
| #define GET16usbPHY_USB_CTRL1_TXBITSTUFFENH(r16) _BFGET_(r16, 5, 5) |
| #define SET16usbPHY_USB_CTRL1_TXBITSTUFFENH(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define GET32usbPHY_USB_CTRL1_DIG_DBG_SEL(r32) _BFGET_(r32,10, 6) |
| #define SET32usbPHY_USB_CTRL1_DIG_DBG_SEL(r32,v) _BFSET_(r32,10, 6,v) |
| #define GET16usbPHY_USB_CTRL1_DIG_DBG_SEL(r16) _BFGET_(r16,10, 6) |
| #define SET16usbPHY_USB_CTRL1_DIG_DBG_SEL(r16,v) _BFSET_(r16,10, 6,v) |
| |
| #define w32usbPHY_USB_CTRL11 {\ |
| UNSG32 uUSB_CTRL1_DP_PULLDOWN : 1;\ |
| UNSG32 uUSB_CTRL1_DM_PULLDOWN : 1;\ |
| UNSG32 uUSB_CTRL1_OPMODE : 2;\ |
| UNSG32 uUSB_CTRL1_TXBITSTUFFEN : 1;\ |
| UNSG32 uUSB_CTRL1_TXBITSTUFFENH : 1;\ |
| UNSG32 uUSB_CTRL1_DIG_DBG_SEL : 5;\ |
| UNSG32 RSVDx8_b11 : 21;\ |
| } |
| union { UNSG32 u32usbPHY_USB_CTRL11; |
| struct w32usbPHY_USB_CTRL11; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32usbPHY_USB_PHY_RB_LBK_ERR(r32) _BFGET_(r32, 0, 0) |
| #define SET32usbPHY_USB_PHY_RB_LBK_ERR(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16usbPHY_USB_PHY_RB_LBK_ERR(r16) _BFGET_(r16, 0, 0) |
| #define SET16usbPHY_USB_PHY_RB_LBK_ERR(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32usbPHY_USB_PHY_RB {\ |
| UNSG32 uUSB_PHY_RB_LBK_ERR : 1;\ |
| UNSG32 RSVDxC_b1 : 31;\ |
| } |
| union { UNSG32 u32usbPHY_USB_PHY_RB; |
| struct w32usbPHY_USB_PHY_RB; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32usbPHY_USB_RB_CLK_RDY(r32) _BFGET_(r32, 0, 0) |
| #define SET32usbPHY_USB_RB_CLK_RDY(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16usbPHY_USB_RB_CLK_RDY(r16) _BFGET_(r16, 0, 0) |
| #define SET16usbPHY_USB_RB_CLK_RDY(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32usbPHY_USB_RB_RES_CAL_CODE(r32) _BFGET_(r32, 4, 1) |
| #define SET32usbPHY_USB_RB_RES_CAL_CODE(r32,v) _BFSET_(r32, 4, 1,v) |
| #define GET16usbPHY_USB_RB_RES_CAL_CODE(r16) _BFGET_(r16, 4, 1) |
| #define SET16usbPHY_USB_RB_RES_CAL_CODE(r16,v) _BFSET_(r16, 4, 1,v) |
| |
| #define GET32usbPHY_USB_RB_RCV_SQ_REG(r32) _BFGET_(r32, 5, 5) |
| #define SET32usbPHY_USB_RB_RCV_SQ_REG(r32,v) _BFSET_(r32, 5, 5,v) |
| #define GET16usbPHY_USB_RB_RCV_SQ_REG(r16) _BFGET_(r16, 5, 5) |
| #define SET16usbPHY_USB_RB_RCV_SQ_REG(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define GET32usbPHY_USB_RB_SENRCV_REG(r32) _BFGET_(r32, 6, 6) |
| #define SET32usbPHY_USB_RB_SENRCV_REG(r32,v) _BFSET_(r32, 6, 6,v) |
| #define GET16usbPHY_USB_RB_SENRCV_REG(r16) _BFGET_(r16, 6, 6) |
| #define SET16usbPHY_USB_RB_SENRCV_REG(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32usbPHY_USB_RB_SEPRCV_REG(r32) _BFGET_(r32, 7, 7) |
| #define SET32usbPHY_USB_RB_SEPRCV_REG(r32,v) _BFSET_(r32, 7, 7,v) |
| #define GET16usbPHY_USB_RB_SEPRCV_REG(r16) _BFGET_(r16, 7, 7) |
| #define SET16usbPHY_USB_RB_SEPRCV_REG(r16,v) _BFSET_(r16, 7, 7,v) |
| |
| #define GET32usbPHY_USB_RB_CLK_READY_REG(r32) _BFGET_(r32, 8, 8) |
| #define SET32usbPHY_USB_RB_CLK_READY_REG(r32,v) _BFSET_(r32, 8, 8,v) |
| #define GET16usbPHY_USB_RB_CLK_READY_REG(r16) _BFGET_(r16, 8, 8) |
| #define SET16usbPHY_USB_RB_CLK_READY_REG(r16,v) _BFSET_(r16, 8, 8,v) |
| |
| #define GET32usbPHY_USB_RB_LFSRCV_REG(r32) _BFGET_(r32, 9, 9) |
| #define SET32usbPHY_USB_RB_LFSRCV_REG(r32,v) _BFSET_(r32, 9, 9,v) |
| #define GET16usbPHY_USB_RB_LFSRCV_REG(r16) _BFGET_(r16, 9, 9) |
| #define SET16usbPHY_USB_RB_LFSRCV_REG(r16,v) _BFSET_(r16, 9, 9,v) |
| |
| #define GET32usbPHY_USB_RB_RCV_DED_REG(r32) _BFGET_(r32,10,10) |
| #define SET32usbPHY_USB_RB_RCV_DED_REG(r32,v) _BFSET_(r32,10,10,v) |
| #define GET16usbPHY_USB_RB_RCV_DED_REG(r16) _BFGET_(r16,10,10) |
| #define SET16usbPHY_USB_RB_RCV_DED_REG(r16,v) _BFSET_(r16,10,10,v) |
| |
| #define GET32usbPHY_USB_RB_ID_A_B_REG(r32) _BFGET_(r32,11,11) |
| #define SET32usbPHY_USB_RB_ID_A_B_REG(r32,v) _BFSET_(r32,11,11,v) |
| #define GET16usbPHY_USB_RB_ID_A_B_REG(r16) _BFGET_(r16,11,11) |
| #define SET16usbPHY_USB_RB_ID_A_B_REG(r16,v) _BFSET_(r16,11,11,v) |
| |
| #define GET32usbPHY_USB_RB_VBUS_VLD_REG(r32) _BFGET_(r32,12,12) |
| #define SET32usbPHY_USB_RB_VBUS_VLD_REG(r32,v) _BFSET_(r32,12,12,v) |
| #define GET16usbPHY_USB_RB_VBUS_VLD_REG(r16) _BFGET_(r16,12,12) |
| #define SET16usbPHY_USB_RB_VBUS_VLD_REG(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define GET32usbPHY_USB_RB_VSESS_VLD_REG(r32) _BFGET_(r32,13,13) |
| #define SET32usbPHY_USB_RB_VSESS_VLD_REG(r32,v) _BFSET_(r32,13,13,v) |
| #define GET16usbPHY_USB_RB_VSESS_VLD_REG(r16) _BFGET_(r16,13,13) |
| #define SET16usbPHY_USB_RB_VSESS_VLD_REG(r16,v) _BFSET_(r16,13,13,v) |
| |
| #define GET32usbPHY_USB_RB_ADPPRB_REG(r32) _BFGET_(r32,14,14) |
| #define SET32usbPHY_USB_RB_ADPPRB_REG(r32,v) _BFSET_(r32,14,14,v) |
| #define GET16usbPHY_USB_RB_ADPPRB_REG(r16) _BFGET_(r16,14,14) |
| #define SET16usbPHY_USB_RB_ADPPRB_REG(r16,v) _BFSET_(r16,14,14,v) |
| |
| #define GET32usbPHY_USB_RB_ADPSNS_REG(r32) _BFGET_(r32,15,15) |
| #define SET32usbPHY_USB_RB_ADPSNS_REG(r32,v) _BFSET_(r32,15,15,v) |
| #define GET16usbPHY_USB_RB_ADPSNS_REG(r16) _BFGET_(r16,15,15) |
| #define SET16usbPHY_USB_RB_ADPSNS_REG(r16,v) _BFSET_(r16,15,15,v) |
| |
| #define w32usbPHY_USB_RB {\ |
| UNSG32 uUSB_RB_CLK_RDY : 1;\ |
| UNSG32 uUSB_RB_RES_CAL_CODE : 4;\ |
| UNSG32 uUSB_RB_RCV_SQ_REG : 1;\ |
| UNSG32 uUSB_RB_SENRCV_REG : 1;\ |
| UNSG32 uUSB_RB_SEPRCV_REG : 1;\ |
| UNSG32 uUSB_RB_CLK_READY_REG : 1;\ |
| UNSG32 uUSB_RB_LFSRCV_REG : 1;\ |
| UNSG32 uUSB_RB_RCV_DED_REG : 1;\ |
| UNSG32 uUSB_RB_ID_A_B_REG : 1;\ |
| UNSG32 uUSB_RB_VBUS_VLD_REG : 1;\ |
| UNSG32 uUSB_RB_VSESS_VLD_REG : 1;\ |
| UNSG32 uUSB_RB_ADPPRB_REG : 1;\ |
| UNSG32 uUSB_RB_ADPSNS_REG : 1;\ |
| UNSG32 RSVDx10_b16 : 16;\ |
| } |
| union { UNSG32 u32usbPHY_USB_RB; |
| struct w32usbPHY_USB_RB; |
| }; |
| /////////////////////////////////////////////////////////// |
| #define GET32usbPHY_OTG_CORE_CTRL_s_bigendian(r32) _BFGET_(r32, 0, 0) |
| #define SET32usbPHY_OTG_CORE_CTRL_s_bigendian(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16usbPHY_OTG_CORE_CTRL_s_bigendian(r16) _BFGET_(r16, 0, 0) |
| #define SET16usbPHY_OTG_CORE_CTRL_s_bigendian(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32usbPHY_OTG_CORE_CTRL_m_bigendian(r32) _BFGET_(r32, 1, 1) |
| #define SET32usbPHY_OTG_CORE_CTRL_m_bigendian(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16usbPHY_OTG_CORE_CTRL_m_bigendian(r16) _BFGET_(r16, 1, 1) |
| #define SET16usbPHY_OTG_CORE_CTRL_m_bigendian(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32usbPHY_OTG_CORE_CTRL_ss_scale_down(r32) _BFGET_(r32, 3, 2) |
| #define SET32usbPHY_OTG_CORE_CTRL_ss_scale_down(r32,v) _BFSET_(r32, 3, 2,v) |
| #define GET16usbPHY_OTG_CORE_CTRL_ss_scale_down(r16) _BFGET_(r16, 3, 2) |
| #define SET16usbPHY_OTG_CORE_CTRL_ss_scale_down(r16,v) _BFSET_(r16, 3, 2,v) |
| |
| #define w32usbPHY_OTG_CORE_CTRL {\ |
| UNSG32 uOTG_CORE_CTRL_s_bigendian : 1;\ |
| UNSG32 uOTG_CORE_CTRL_m_bigendian : 1;\ |
| UNSG32 uOTG_CORE_CTRL_ss_scale_down : 2;\ |
| UNSG32 RSVDx14_b4 : 28;\ |
| } |
| union { UNSG32 u32usbPHY_OTG_CORE_CTRL; |
| struct w32usbPHY_OTG_CORE_CTRL; |
| }; |
| /////////////////////////////////////////////////////////// |
| } SIE_usbPHY; |
| |
| typedef union T32usbPHY_USB_CTRL0 |
| { UNSG32 u32; |
| struct w32usbPHY_USB_CTRL0; |
| } T32usbPHY_USB_CTRL0; |
| typedef union T32usbPHY_USB_CTRL1 |
| { UNSG32 u32; |
| struct w32usbPHY_USB_CTRL1; |
| } T32usbPHY_USB_CTRL1; |
| typedef union T32usbPHY_USB_CTRL11 |
| { UNSG32 u32; |
| struct w32usbPHY_USB_CTRL11; |
| } T32usbPHY_USB_CTRL11; |
| typedef union T32usbPHY_USB_PHY_RB |
| { UNSG32 u32; |
| struct w32usbPHY_USB_PHY_RB; |
| } T32usbPHY_USB_PHY_RB; |
| typedef union T32usbPHY_USB_RB |
| { UNSG32 u32; |
| struct w32usbPHY_USB_RB; |
| } T32usbPHY_USB_RB; |
| typedef union T32usbPHY_OTG_CORE_CTRL |
| { UNSG32 u32; |
| struct w32usbPHY_OTG_CORE_CTRL; |
| } T32usbPHY_OTG_CORE_CTRL; |
| /////////////////////////////////////////////////////////// |
| |
| typedef union TusbPHY_USB_CTRL0 |
| { UNSG32 u32[1]; |
| struct { |
| struct w32usbPHY_USB_CTRL0; |
| }; |
| } TusbPHY_USB_CTRL0; |
| typedef union TusbPHY_USB_CTRL1 |
| { UNSG32 u32[2]; |
| struct { |
| struct w32usbPHY_USB_CTRL1; |
| struct w32usbPHY_USB_CTRL11; |
| }; |
| } TusbPHY_USB_CTRL1; |
| typedef union TusbPHY_USB_PHY_RB |
| { UNSG32 u32[1]; |
| struct { |
| struct w32usbPHY_USB_PHY_RB; |
| }; |
| } TusbPHY_USB_PHY_RB; |
| typedef union TusbPHY_USB_RB |
| { UNSG32 u32[1]; |
| struct { |
| struct w32usbPHY_USB_RB; |
| }; |
| } TusbPHY_USB_RB; |
| typedef union TusbPHY_OTG_CORE_CTRL |
| { UNSG32 u32[1]; |
| struct { |
| struct w32usbPHY_OTG_CORE_CTRL; |
| }; |
| } TusbPHY_OTG_CORE_CTRL; |
| |
| /////////////////////////////////////////////////////////// |
| SIGN32 usbPHY_drvrd(SIE_usbPHY *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 usbPHY_drvwr(SIE_usbPHY *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void usbPHY_reset(SIE_usbPHY *p); |
| SIGN32 usbPHY_cmp (SIE_usbPHY *p, SIE_usbPHY *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define usbPHY_check(p,pie,pfx,hLOG) usbPHY_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define usbPHY_print(p, pfx,hLOG) usbPHY_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| ////// |
| /// ENDOFINTERFACE: usbPHY |
| //////////////////////////////////////////////////////////// |
| |
| |
| |
| #ifdef __cplusplus |
| } |
| #endif |
| #pragma pack() |
| |
| #endif |
| ////// |
| /// ENDOFFILE: usbPHY.h |
| //////////////////////////////////////////////////////////// |
| |
