| #ifndef MctrlSS_h |
| #define MctrlSS_h (){} |
| |
| |
| #include "ctypes.h" |
| |
| #pragma pack(1) |
| #ifdef __cplusplus |
| extern "C" { |
| #endif |
| |
| #ifndef _DOCC_H_BITOPS_ |
| #define _DOCC_H_BITOPS_ (){} |
| |
| #define _bSETMASK_(b) ((b)<32 ? (1<<((b)&31)) : 0) |
| #define _NSETMASK_(msb,lsb) (_bSETMASK_((msb)+1)-_bSETMASK_(lsb)) |
| #define _bCLRMASK_(b) (~_bSETMASK_(b)) |
| #define _NCLRMASK_(msb,lsb) (~_NSETMASK_(msb,lsb)) |
| #define _BFGET_(r,msb,lsb) (_NSETMASK_((msb)-(lsb),0)&((r)>>(lsb))) |
| #define _BFSET_(r,msb,lsb,v) do{ (r)&=_NCLRMASK_(msb,lsb); (r)|=_NSETMASK_(msb,lsb)&((v)<<(lsb)); }while(0) |
| |
| #endif |
| #ifndef h_pll |
| #define h_pll (){} |
| |
| #define RA_pll_ctrl 0x0000 |
| |
| #define BA_pll_ctrl_PU 0x0000 |
| #define B16pll_ctrl_PU 0x0000 |
| #define LSb32pll_ctrl_PU 0 |
| #define LSb16pll_ctrl_PU 0 |
| #define bpll_ctrl_PU 1 |
| #define MSK32pll_ctrl_PU 0x00000001 |
| |
| #define BA_pll_ctrl_RESET 0x0000 |
| #define B16pll_ctrl_RESET 0x0000 |
| #define LSb32pll_ctrl_RESET 1 |
| #define LSb16pll_ctrl_RESET 1 |
| #define bpll_ctrl_RESET 1 |
| #define MSK32pll_ctrl_RESET 0x00000002 |
| |
| #define BA_pll_ctrl_AVDD1815_SEL 0x0000 |
| #define B16pll_ctrl_AVDD1815_SEL 0x0000 |
| #define LSb32pll_ctrl_AVDD1815_SEL 2 |
| #define LSb16pll_ctrl_AVDD1815_SEL 2 |
| #define bpll_ctrl_AVDD1815_SEL 1 |
| #define MSK32pll_ctrl_AVDD1815_SEL 0x00000004 |
| |
| #define BA_pll_ctrl_REFDIV 0x0000 |
| #define B16pll_ctrl_REFDIV 0x0000 |
| #define LSb32pll_ctrl_REFDIV 3 |
| #define LSb16pll_ctrl_REFDIV 3 |
| #define bpll_ctrl_REFDIV 9 |
| #define MSK32pll_ctrl_REFDIV 0x00000FF8 |
| |
| #define BA_pll_ctrl_FBDIV 0x0001 |
| #define B16pll_ctrl_FBDIV 0x0000 |
| #define LSb32pll_ctrl_FBDIV 12 |
| #define LSb16pll_ctrl_FBDIV 12 |
| #define bpll_ctrl_FBDIV 9 |
| #define MSK32pll_ctrl_FBDIV 0x001FF000 |
| |
| #define BA_pll_ctrl_VDDM 0x0002 |
| #define B16pll_ctrl_VDDM 0x0002 |
| #define LSb32pll_ctrl_VDDM 21 |
| #define LSb16pll_ctrl_VDDM 5 |
| #define bpll_ctrl_VDDM 2 |
| #define MSK32pll_ctrl_VDDM 0x00600000 |
| |
| #define BA_pll_ctrl_VDDL 0x0002 |
| #define B16pll_ctrl_VDDL 0x0002 |
| #define LSb32pll_ctrl_VDDL 23 |
| #define LSb16pll_ctrl_VDDL 7 |
| #define bpll_ctrl_VDDL 3 |
| #define MSK32pll_ctrl_VDDL 0x03800000 |
| |
| #define BA_pll_ctrl_ICP 0x0003 |
| #define B16pll_ctrl_ICP 0x0002 |
| #define LSb32pll_ctrl_ICP 26 |
| #define LSb16pll_ctrl_ICP 10 |
| #define bpll_ctrl_ICP 4 |
| #define MSK32pll_ctrl_ICP 0x3C000000 |
| |
| #define BA_pll_ctrl_PLL_BW_SEL 0x0003 |
| #define B16pll_ctrl_PLL_BW_SEL 0x0002 |
| #define LSb32pll_ctrl_PLL_BW_SEL 30 |
| #define LSb16pll_ctrl_PLL_BW_SEL 14 |
| #define bpll_ctrl_PLL_BW_SEL 1 |
| #define MSK32pll_ctrl_PLL_BW_SEL 0x40000000 |
| |
| #define RA_pll_ctrl1 0x0004 |
| |
| #define BA_pll_ctrl_KVCO 0x0004 |
| #define B16pll_ctrl_KVCO 0x0004 |
| #define LSb32pll_ctrl_KVCO 0 |
| #define LSb16pll_ctrl_KVCO 0 |
| #define bpll_ctrl_KVCO 4 |
| #define MSK32pll_ctrl_KVCO 0x0000000F |
| |
| #define BA_pll_ctrl_CTUNE 0x0004 |
| #define B16pll_ctrl_CTUNE 0x0004 |
| #define LSb32pll_ctrl_CTUNE 4 |
| #define LSb16pll_ctrl_CTUNE 4 |
| #define bpll_ctrl_CTUNE 2 |
| #define MSK32pll_ctrl_CTUNE 0x00000030 |
| |
| #define BA_pll_ctrl_CLKOUT_DIFF_DIV_SEL 0x0004 |
| #define B16pll_ctrl_CLKOUT_DIFF_DIV_SEL 0x0004 |
| #define LSb32pll_ctrl_CLKOUT_DIFF_DIV_SEL 6 |
| #define LSb16pll_ctrl_CLKOUT_DIFF_DIV_SEL 6 |
| #define bpll_ctrl_CLKOUT_DIFF_DIV_SEL 9 |
| #define MSK32pll_ctrl_CLKOUT_DIFF_DIV_SEL 0x00007FC0 |
| |
| #define BA_pll_ctrl_CLKOUT_SE_DIV_SEL 0x0005 |
| #define B16pll_ctrl_CLKOUT_SE_DIV_SEL 0x0004 |
| #define LSb32pll_ctrl_CLKOUT_SE_DIV_SEL 15 |
| #define LSb16pll_ctrl_CLKOUT_SE_DIV_SEL 15 |
| #define bpll_ctrl_CLKOUT_SE_DIV_SEL 9 |
| #define MSK32pll_ctrl_CLKOUT_SE_DIV_SEL 0x00FF8000 |
| |
| #define BA_pll_ctrl_CLKOUT_SOURCE_SEL 0x0007 |
| #define B16pll_ctrl_CLKOUT_SOURCE_SEL 0x0006 |
| #define LSb32pll_ctrl_CLKOUT_SOURCE_SEL 24 |
| #define LSb16pll_ctrl_CLKOUT_SOURCE_SEL 8 |
| #define bpll_ctrl_CLKOUT_SOURCE_SEL 1 |
| #define MSK32pll_ctrl_CLKOUT_SOURCE_SEL 0x01000000 |
| |
| #define BA_pll_ctrl_CLKOUT_DIFF_EN 0x0007 |
| #define B16pll_ctrl_CLKOUT_DIFF_EN 0x0006 |
| #define LSb32pll_ctrl_CLKOUT_DIFF_EN 25 |
| #define LSb16pll_ctrl_CLKOUT_DIFF_EN 9 |
| #define bpll_ctrl_CLKOUT_DIFF_EN 1 |
| #define MSK32pll_ctrl_CLKOUT_DIFF_EN 0x02000000 |
| |
| #define BA_pll_ctrl_BYPASS_EN 0x0007 |
| #define B16pll_ctrl_BYPASS_EN 0x0006 |
| #define LSb32pll_ctrl_BYPASS_EN 26 |
| #define LSb16pll_ctrl_BYPASS_EN 10 |
| #define bpll_ctrl_BYPASS_EN 1 |
| #define MSK32pll_ctrl_BYPASS_EN 0x04000000 |
| |
| #define BA_pll_ctrl_CLKOUT_SE_GATING_EN 0x0007 |
| #define B16pll_ctrl_CLKOUT_SE_GATING_EN 0x0006 |
| #define LSb32pll_ctrl_CLKOUT_SE_GATING_EN 27 |
| #define LSb16pll_ctrl_CLKOUT_SE_GATING_EN 11 |
| #define bpll_ctrl_CLKOUT_SE_GATING_EN 1 |
| #define MSK32pll_ctrl_CLKOUT_SE_GATING_EN 0x08000000 |
| |
| #define BA_pll_ctrl_FBCLK_EXT_SEL 0x0007 |
| #define B16pll_ctrl_FBCLK_EXT_SEL 0x0006 |
| #define LSb32pll_ctrl_FBCLK_EXT_SEL 28 |
| #define LSb16pll_ctrl_FBCLK_EXT_SEL 12 |
| #define bpll_ctrl_FBCLK_EXT_SEL 1 |
| #define MSK32pll_ctrl_FBCLK_EXT_SEL 0x10000000 |
| |
| #define RA_pll_ctrl2 0x0008 |
| |
| #define BA_pll_ctrl_FBCDLY 0x0008 |
| #define B16pll_ctrl_FBCDLY 0x0008 |
| #define LSb32pll_ctrl_FBCDLY 0 |
| #define LSb16pll_ctrl_FBCDLY 0 |
| #define bpll_ctrl_FBCDLY 6 |
| #define MSK32pll_ctrl_FBCDLY 0x0000003F |
| |
| #define BA_pll_ctrl_FD 0x0008 |
| #define B16pll_ctrl_FD 0x0008 |
| #define LSb32pll_ctrl_FD 6 |
| #define LSb16pll_ctrl_FD 6 |
| #define bpll_ctrl_FD 3 |
| #define MSK32pll_ctrl_FD 0x000001C0 |
| |
| #define BA_pll_ctrl_INTPI 0x0009 |
| #define B16pll_ctrl_INTPI 0x0008 |
| #define LSb32pll_ctrl_INTPI 9 |
| #define LSb16pll_ctrl_INTPI 9 |
| #define bpll_ctrl_INTPI 4 |
| #define MSK32pll_ctrl_INTPI 0x00001E00 |
| |
| #define BA_pll_ctrl_INTPR 0x0009 |
| #define B16pll_ctrl_INTPR 0x0008 |
| #define LSb32pll_ctrl_INTPR 13 |
| #define LSb16pll_ctrl_INTPR 13 |
| #define bpll_ctrl_INTPR 3 |
| #define MSK32pll_ctrl_INTPR 0x0000E000 |
| |
| #define BA_pll_ctrl_PI_EN 0x000A |
| #define B16pll_ctrl_PI_EN 0x000A |
| #define LSb32pll_ctrl_PI_EN 16 |
| #define LSb16pll_ctrl_PI_EN 0 |
| #define bpll_ctrl_PI_EN 1 |
| #define MSK32pll_ctrl_PI_EN 0x00010000 |
| |
| #define BA_pll_ctrl_PI_LOOP_MODE 0x000A |
| #define B16pll_ctrl_PI_LOOP_MODE 0x000A |
| #define LSb32pll_ctrl_PI_LOOP_MODE 17 |
| #define LSb16pll_ctrl_PI_LOOP_MODE 1 |
| #define bpll_ctrl_PI_LOOP_MODE 1 |
| #define MSK32pll_ctrl_PI_LOOP_MODE 0x00020000 |
| |
| #define BA_pll_ctrl_CLK_DET_EN 0x000A |
| #define B16pll_ctrl_CLK_DET_EN 0x000A |
| #define LSb32pll_ctrl_CLK_DET_EN 18 |
| #define LSb16pll_ctrl_CLK_DET_EN 2 |
| #define bpll_ctrl_CLK_DET_EN 1 |
| #define MSK32pll_ctrl_CLK_DET_EN 0x00040000 |
| |
| #define BA_pll_ctrl_RESET_PI 0x000A |
| #define B16pll_ctrl_RESET_PI 0x000A |
| #define LSb32pll_ctrl_RESET_PI 19 |
| #define LSb16pll_ctrl_RESET_PI 3 |
| #define bpll_ctrl_RESET_PI 1 |
| #define MSK32pll_ctrl_RESET_PI 0x00080000 |
| |
| #define BA_pll_ctrl_RESET_SSC 0x000A |
| #define B16pll_ctrl_RESET_SSC 0x000A |
| #define LSb32pll_ctrl_RESET_SSC 20 |
| #define LSb16pll_ctrl_RESET_SSC 4 |
| #define bpll_ctrl_RESET_SSC 1 |
| #define MSK32pll_ctrl_RESET_SSC 0x00100000 |
| |
| #define BA_pll_ctrl_FREQ_OFFSET_EN 0x000A |
| #define B16pll_ctrl_FREQ_OFFSET_EN 0x000A |
| #define LSb32pll_ctrl_FREQ_OFFSET_EN 21 |
| #define LSb16pll_ctrl_FREQ_OFFSET_EN 5 |
| #define bpll_ctrl_FREQ_OFFSET_EN 1 |
| #define MSK32pll_ctrl_FREQ_OFFSET_EN 0x00200000 |
| |
| #define RA_pll_ctrl3 0x000C |
| |
| #define BA_pll_ctrl_FREQ_OFFSET 0x000C |
| #define B16pll_ctrl_FREQ_OFFSET 0x000C |
| #define LSb32pll_ctrl_FREQ_OFFSET 0 |
| #define LSb16pll_ctrl_FREQ_OFFSET 0 |
| #define bpll_ctrl_FREQ_OFFSET 17 |
| #define MSK32pll_ctrl_FREQ_OFFSET 0x0001FFFF |
| |
| #define BA_pll_ctrl_FREQ_OFFSET_MODE_SELECTION 0x000E |
| #define B16pll_ctrl_FREQ_OFFSET_MODE_SELECTION 0x000E |
| #define LSb32pll_ctrl_FREQ_OFFSET_MODE_SELECTION 17 |
| #define LSb16pll_ctrl_FREQ_OFFSET_MODE_SELECTION 1 |
| #define bpll_ctrl_FREQ_OFFSET_MODE_SELECTION 1 |
| #define MSK32pll_ctrl_FREQ_OFFSET_MODE_SELECTION 0x00020000 |
| |
| #define BA_pll_ctrl_FREQ_OFFSET_VALID 0x000E |
| #define B16pll_ctrl_FREQ_OFFSET_VALID 0x000E |
| #define LSb32pll_ctrl_FREQ_OFFSET_VALID 18 |
| #define LSb16pll_ctrl_FREQ_OFFSET_VALID 2 |
| #define bpll_ctrl_FREQ_OFFSET_VALID 1 |
| #define MSK32pll_ctrl_FREQ_OFFSET_VALID 0x00040000 |
| |
| #define BA_pll_ctrl_SSC_CLK_EN 0x000E |
| #define B16pll_ctrl_SSC_CLK_EN 0x000E |
| #define LSb32pll_ctrl_SSC_CLK_EN 19 |
| #define LSb16pll_ctrl_SSC_CLK_EN 3 |
| #define bpll_ctrl_SSC_CLK_EN 1 |
| #define MSK32pll_ctrl_SSC_CLK_EN 0x00080000 |
| |
| #define BA_pll_ctrl_SSC_MODE 0x000E |
| #define B16pll_ctrl_SSC_MODE 0x000E |
| #define LSb32pll_ctrl_SSC_MODE 20 |
| #define LSb16pll_ctrl_SSC_MODE 4 |
| #define bpll_ctrl_SSC_MODE 1 |
| #define MSK32pll_ctrl_SSC_MODE 0x00100000 |
| |
| #define RA_pll_ctrl4 0x0010 |
| |
| #define BA_pll_ctrl_SSC_FREQ_DIV 0x0010 |
| #define B16pll_ctrl_SSC_FREQ_DIV 0x0010 |
| #define LSb32pll_ctrl_SSC_FREQ_DIV 0 |
| #define LSb16pll_ctrl_SSC_FREQ_DIV 0 |
| #define bpll_ctrl_SSC_FREQ_DIV 16 |
| #define MSK32pll_ctrl_SSC_FREQ_DIV 0x0000FFFF |
| |
| #define BA_pll_ctrl_SSC_RNGE 0x0012 |
| #define B16pll_ctrl_SSC_RNGE 0x0012 |
| #define LSb32pll_ctrl_SSC_RNGE 16 |
| #define LSb16pll_ctrl_SSC_RNGE 0 |
| #define bpll_ctrl_SSC_RNGE 11 |
| #define MSK32pll_ctrl_SSC_RNGE 0x07FF0000 |
| |
| #define BA_pll_ctrl_TEST_ANA 0x0013 |
| #define B16pll_ctrl_TEST_ANA 0x0012 |
| #define LSb32pll_ctrl_TEST_ANA 27 |
| #define LSb16pll_ctrl_TEST_ANA 11 |
| #define bpll_ctrl_TEST_ANA 4 |
| #define MSK32pll_ctrl_TEST_ANA 0x78000000 |
| |
| #define RA_pll_ctrl5 0x0014 |
| |
| #define BA_pll_ctrl_RESERVE_IN 0x0014 |
| #define B16pll_ctrl_RESERVE_IN 0x0014 |
| #define LSb32pll_ctrl_RESERVE_IN 0 |
| #define LSb16pll_ctrl_RESERVE_IN 0 |
| #define bpll_ctrl_RESERVE_IN 8 |
| #define MSK32pll_ctrl_RESERVE_IN 0x000000FF |
| |
| #define RA_pll_status 0x0018 |
| |
| #define BA_pll_status_PLL_LOCK 0x0018 |
| #define B16pll_status_PLL_LOCK 0x0018 |
| #define LSb32pll_status_PLL_LOCK 0 |
| #define LSb16pll_status_PLL_LOCK 0 |
| #define bpll_status_PLL_LOCK 1 |
| #define MSK32pll_status_PLL_LOCK 0x00000001 |
| |
| #define BA_pll_status_CLK_CFMOD 0x0018 |
| #define B16pll_status_CLK_CFMOD 0x0018 |
| #define LSb32pll_status_CLK_CFMOD 1 |
| #define LSb16pll_status_CLK_CFMOD 1 |
| #define bpll_status_CLK_CFMOD 1 |
| #define MSK32pll_status_CLK_CFMOD 0x00000002 |
| |
| #define BA_pll_status_CLK_FMOD 0x0018 |
| #define B16pll_status_CLK_FMOD 0x0018 |
| #define LSb32pll_status_CLK_FMOD 2 |
| #define LSb16pll_status_CLK_FMOD 2 |
| #define bpll_status_CLK_FMOD 1 |
| #define MSK32pll_status_CLK_FMOD 0x00000004 |
| |
| #define BA_pll_status_RESERVE_OUT 0x0018 |
| #define B16pll_status_RESERVE_OUT 0x0018 |
| #define LSb32pll_status_RESERVE_OUT 3 |
| #define LSb16pll_status_RESERVE_OUT 3 |
| #define bpll_status_RESERVE_OUT 8 |
| #define MSK32pll_status_RESERVE_OUT 0x000007F8 |
| |
| |
| typedef struct SIE_pll { |
| |
| #define GET32pll_ctrl_PU(r32) _BFGET_(r32, 0, 0) |
| #define SET32pll_ctrl_PU(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16pll_ctrl_PU(r16) _BFGET_(r16, 0, 0) |
| #define SET16pll_ctrl_PU(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32pll_ctrl_RESET(r32) _BFGET_(r32, 1, 1) |
| #define SET32pll_ctrl_RESET(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16pll_ctrl_RESET(r16) _BFGET_(r16, 1, 1) |
| #define SET16pll_ctrl_RESET(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32pll_ctrl_AVDD1815_SEL(r32) _BFGET_(r32, 2, 2) |
| #define SET32pll_ctrl_AVDD1815_SEL(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16pll_ctrl_AVDD1815_SEL(r16) _BFGET_(r16, 2, 2) |
| #define SET16pll_ctrl_AVDD1815_SEL(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32pll_ctrl_REFDIV(r32) _BFGET_(r32,11, 3) |
| #define SET32pll_ctrl_REFDIV(r32,v) _BFSET_(r32,11, 3,v) |
| #define GET16pll_ctrl_REFDIV(r16) _BFGET_(r16,11, 3) |
| #define SET16pll_ctrl_REFDIV(r16,v) _BFSET_(r16,11, 3,v) |
| |
| #define GET32pll_ctrl_FBDIV(r32) _BFGET_(r32,20,12) |
| #define SET32pll_ctrl_FBDIV(r32,v) _BFSET_(r32,20,12,v) |
| |
| #define GET32pll_ctrl_VDDM(r32) _BFGET_(r32,22,21) |
| #define SET32pll_ctrl_VDDM(r32,v) _BFSET_(r32,22,21,v) |
| #define GET16pll_ctrl_VDDM(r16) _BFGET_(r16, 6, 5) |
| #define SET16pll_ctrl_VDDM(r16,v) _BFSET_(r16, 6, 5,v) |
| |
| #define GET32pll_ctrl_VDDL(r32) _BFGET_(r32,25,23) |
| #define SET32pll_ctrl_VDDL(r32,v) _BFSET_(r32,25,23,v) |
| #define GET16pll_ctrl_VDDL(r16) _BFGET_(r16, 9, 7) |
| #define SET16pll_ctrl_VDDL(r16,v) _BFSET_(r16, 9, 7,v) |
| |
| #define GET32pll_ctrl_ICP(r32) _BFGET_(r32,29,26) |
| #define SET32pll_ctrl_ICP(r32,v) _BFSET_(r32,29,26,v) |
| #define GET16pll_ctrl_ICP(r16) _BFGET_(r16,13,10) |
| #define SET16pll_ctrl_ICP(r16,v) _BFSET_(r16,13,10,v) |
| |
| #define GET32pll_ctrl_PLL_BW_SEL(r32) _BFGET_(r32,30,30) |
| #define SET32pll_ctrl_PLL_BW_SEL(r32,v) _BFSET_(r32,30,30,v) |
| #define GET16pll_ctrl_PLL_BW_SEL(r16) _BFGET_(r16,14,14) |
| #define SET16pll_ctrl_PLL_BW_SEL(r16,v) _BFSET_(r16,14,14,v) |
| |
| #define w32pll_ctrl {\ |
| UNSG32 uctrl_PU : 1;\ |
| UNSG32 uctrl_RESET : 1;\ |
| UNSG32 uctrl_AVDD1815_SEL : 1;\ |
| UNSG32 uctrl_REFDIV : 9;\ |
| UNSG32 uctrl_FBDIV : 9;\ |
| UNSG32 uctrl_VDDM : 2;\ |
| UNSG32 uctrl_VDDL : 3;\ |
| UNSG32 uctrl_ICP : 4;\ |
| UNSG32 uctrl_PLL_BW_SEL : 1;\ |
| UNSG32 RSVDx0_b31 : 1;\ |
| } |
| union { UNSG32 u32pll_ctrl; |
| struct w32pll_ctrl; |
| }; |
| #define GET32pll_ctrl_KVCO(r32) _BFGET_(r32, 3, 0) |
| #define SET32pll_ctrl_KVCO(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16pll_ctrl_KVCO(r16) _BFGET_(r16, 3, 0) |
| #define SET16pll_ctrl_KVCO(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32pll_ctrl_CTUNE(r32) _BFGET_(r32, 5, 4) |
| #define SET32pll_ctrl_CTUNE(r32,v) _BFSET_(r32, 5, 4,v) |
| #define GET16pll_ctrl_CTUNE(r16) _BFGET_(r16, 5, 4) |
| #define SET16pll_ctrl_CTUNE(r16,v) _BFSET_(r16, 5, 4,v) |
| |
| #define GET32pll_ctrl_CLKOUT_DIFF_DIV_SEL(r32) _BFGET_(r32,14, 6) |
| #define SET32pll_ctrl_CLKOUT_DIFF_DIV_SEL(r32,v) _BFSET_(r32,14, 6,v) |
| #define GET16pll_ctrl_CLKOUT_DIFF_DIV_SEL(r16) _BFGET_(r16,14, 6) |
| #define SET16pll_ctrl_CLKOUT_DIFF_DIV_SEL(r16,v) _BFSET_(r16,14, 6,v) |
| |
| #define GET32pll_ctrl_CLKOUT_SE_DIV_SEL(r32) _BFGET_(r32,23,15) |
| #define SET32pll_ctrl_CLKOUT_SE_DIV_SEL(r32,v) _BFSET_(r32,23,15,v) |
| |
| #define GET32pll_ctrl_CLKOUT_SOURCE_SEL(r32) _BFGET_(r32,24,24) |
| #define SET32pll_ctrl_CLKOUT_SOURCE_SEL(r32,v) _BFSET_(r32,24,24,v) |
| #define GET16pll_ctrl_CLKOUT_SOURCE_SEL(r16) _BFGET_(r16, 8, 8) |
| #define SET16pll_ctrl_CLKOUT_SOURCE_SEL(r16,v) _BFSET_(r16, 8, 8,v) |
| |
| #define GET32pll_ctrl_CLKOUT_DIFF_EN(r32) _BFGET_(r32,25,25) |
| #define SET32pll_ctrl_CLKOUT_DIFF_EN(r32,v) _BFSET_(r32,25,25,v) |
| #define GET16pll_ctrl_CLKOUT_DIFF_EN(r16) _BFGET_(r16, 9, 9) |
| #define SET16pll_ctrl_CLKOUT_DIFF_EN(r16,v) _BFSET_(r16, 9, 9,v) |
| |
| #define GET32pll_ctrl_BYPASS_EN(r32) _BFGET_(r32,26,26) |
| #define SET32pll_ctrl_BYPASS_EN(r32,v) _BFSET_(r32,26,26,v) |
| #define GET16pll_ctrl_BYPASS_EN(r16) _BFGET_(r16,10,10) |
| #define SET16pll_ctrl_BYPASS_EN(r16,v) _BFSET_(r16,10,10,v) |
| |
| #define GET32pll_ctrl_CLKOUT_SE_GATING_EN(r32) _BFGET_(r32,27,27) |
| #define SET32pll_ctrl_CLKOUT_SE_GATING_EN(r32,v) _BFSET_(r32,27,27,v) |
| #define GET16pll_ctrl_CLKOUT_SE_GATING_EN(r16) _BFGET_(r16,11,11) |
| #define SET16pll_ctrl_CLKOUT_SE_GATING_EN(r16,v) _BFSET_(r16,11,11,v) |
| |
| #define GET32pll_ctrl_FBCLK_EXT_SEL(r32) _BFGET_(r32,28,28) |
| #define SET32pll_ctrl_FBCLK_EXT_SEL(r32,v) _BFSET_(r32,28,28,v) |
| #define GET16pll_ctrl_FBCLK_EXT_SEL(r16) _BFGET_(r16,12,12) |
| #define SET16pll_ctrl_FBCLK_EXT_SEL(r16,v) _BFSET_(r16,12,12,v) |
| |
| #define w32pll_ctrl1 {\ |
| UNSG32 uctrl_KVCO : 4;\ |
| UNSG32 uctrl_CTUNE : 2;\ |
| UNSG32 uctrl_CLKOUT_DIFF_DIV_SEL : 9;\ |
| UNSG32 uctrl_CLKOUT_SE_DIV_SEL : 9;\ |
| UNSG32 uctrl_CLKOUT_SOURCE_SEL : 1;\ |
| UNSG32 uctrl_CLKOUT_DIFF_EN : 1;\ |
| UNSG32 uctrl_BYPASS_EN : 1;\ |
| UNSG32 uctrl_CLKOUT_SE_GATING_EN : 1;\ |
| UNSG32 uctrl_FBCLK_EXT_SEL : 1;\ |
| UNSG32 RSVDx4_b29 : 3;\ |
| } |
| union { UNSG32 u32pll_ctrl1; |
| struct w32pll_ctrl1; |
| }; |
| #define GET32pll_ctrl_FBCDLY(r32) _BFGET_(r32, 5, 0) |
| #define SET32pll_ctrl_FBCDLY(r32,v) _BFSET_(r32, 5, 0,v) |
| #define GET16pll_ctrl_FBCDLY(r16) _BFGET_(r16, 5, 0) |
| #define SET16pll_ctrl_FBCDLY(r16,v) _BFSET_(r16, 5, 0,v) |
| |
| #define GET32pll_ctrl_FD(r32) _BFGET_(r32, 8, 6) |
| #define SET32pll_ctrl_FD(r32,v) _BFSET_(r32, 8, 6,v) |
| #define GET16pll_ctrl_FD(r16) _BFGET_(r16, 8, 6) |
| #define SET16pll_ctrl_FD(r16,v) _BFSET_(r16, 8, 6,v) |
| |
| #define GET32pll_ctrl_INTPI(r32) _BFGET_(r32,12, 9) |
| #define SET32pll_ctrl_INTPI(r32,v) _BFSET_(r32,12, 9,v) |
| #define GET16pll_ctrl_INTPI(r16) _BFGET_(r16,12, 9) |
| #define SET16pll_ctrl_INTPI(r16,v) _BFSET_(r16,12, 9,v) |
| |
| #define GET32pll_ctrl_INTPR(r32) _BFGET_(r32,15,13) |
| #define SET32pll_ctrl_INTPR(r32,v) _BFSET_(r32,15,13,v) |
| #define GET16pll_ctrl_INTPR(r16) _BFGET_(r16,15,13) |
| #define SET16pll_ctrl_INTPR(r16,v) _BFSET_(r16,15,13,v) |
| |
| #define GET32pll_ctrl_PI_EN(r32) _BFGET_(r32,16,16) |
| #define SET32pll_ctrl_PI_EN(r32,v) _BFSET_(r32,16,16,v) |
| #define GET16pll_ctrl_PI_EN(r16) _BFGET_(r16, 0, 0) |
| #define SET16pll_ctrl_PI_EN(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32pll_ctrl_PI_LOOP_MODE(r32) _BFGET_(r32,17,17) |
| #define SET32pll_ctrl_PI_LOOP_MODE(r32,v) _BFSET_(r32,17,17,v) |
| #define GET16pll_ctrl_PI_LOOP_MODE(r16) _BFGET_(r16, 1, 1) |
| #define SET16pll_ctrl_PI_LOOP_MODE(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32pll_ctrl_CLK_DET_EN(r32) _BFGET_(r32,18,18) |
| #define SET32pll_ctrl_CLK_DET_EN(r32,v) _BFSET_(r32,18,18,v) |
| #define GET16pll_ctrl_CLK_DET_EN(r16) _BFGET_(r16, 2, 2) |
| #define SET16pll_ctrl_CLK_DET_EN(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32pll_ctrl_RESET_PI(r32) _BFGET_(r32,19,19) |
| #define SET32pll_ctrl_RESET_PI(r32,v) _BFSET_(r32,19,19,v) |
| #define GET16pll_ctrl_RESET_PI(r16) _BFGET_(r16, 3, 3) |
| #define SET16pll_ctrl_RESET_PI(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32pll_ctrl_RESET_SSC(r32) _BFGET_(r32,20,20) |
| #define SET32pll_ctrl_RESET_SSC(r32,v) _BFSET_(r32,20,20,v) |
| #define GET16pll_ctrl_RESET_SSC(r16) _BFGET_(r16, 4, 4) |
| #define SET16pll_ctrl_RESET_SSC(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define GET32pll_ctrl_FREQ_OFFSET_EN(r32) _BFGET_(r32,21,21) |
| #define SET32pll_ctrl_FREQ_OFFSET_EN(r32,v) _BFSET_(r32,21,21,v) |
| #define GET16pll_ctrl_FREQ_OFFSET_EN(r16) _BFGET_(r16, 5, 5) |
| #define SET16pll_ctrl_FREQ_OFFSET_EN(r16,v) _BFSET_(r16, 5, 5,v) |
| |
| #define w32pll_ctrl2 {\ |
| UNSG32 uctrl_FBCDLY : 6;\ |
| UNSG32 uctrl_FD : 3;\ |
| UNSG32 uctrl_INTPI : 4;\ |
| UNSG32 uctrl_INTPR : 3;\ |
| UNSG32 uctrl_PI_EN : 1;\ |
| UNSG32 uctrl_PI_LOOP_MODE : 1;\ |
| UNSG32 uctrl_CLK_DET_EN : 1;\ |
| UNSG32 uctrl_RESET_PI : 1;\ |
| UNSG32 uctrl_RESET_SSC : 1;\ |
| UNSG32 uctrl_FREQ_OFFSET_EN : 1;\ |
| UNSG32 RSVDx8_b22 : 10;\ |
| } |
| union { UNSG32 u32pll_ctrl2; |
| struct w32pll_ctrl2; |
| }; |
| #define GET32pll_ctrl_FREQ_OFFSET(r32) _BFGET_(r32,16, 0) |
| #define SET32pll_ctrl_FREQ_OFFSET(r32,v) _BFSET_(r32,16, 0,v) |
| |
| #define GET32pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r32) _BFGET_(r32,17,17) |
| #define SET32pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r32,v) _BFSET_(r32,17,17,v) |
| #define GET16pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r16) _BFGET_(r16, 1, 1) |
| #define SET16pll_ctrl_FREQ_OFFSET_MODE_SELECTION(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32pll_ctrl_FREQ_OFFSET_VALID(r32) _BFGET_(r32,18,18) |
| #define SET32pll_ctrl_FREQ_OFFSET_VALID(r32,v) _BFSET_(r32,18,18,v) |
| #define GET16pll_ctrl_FREQ_OFFSET_VALID(r16) _BFGET_(r16, 2, 2) |
| #define SET16pll_ctrl_FREQ_OFFSET_VALID(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32pll_ctrl_SSC_CLK_EN(r32) _BFGET_(r32,19,19) |
| #define SET32pll_ctrl_SSC_CLK_EN(r32,v) _BFSET_(r32,19,19,v) |
| #define GET16pll_ctrl_SSC_CLK_EN(r16) _BFGET_(r16, 3, 3) |
| #define SET16pll_ctrl_SSC_CLK_EN(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32pll_ctrl_SSC_MODE(r32) _BFGET_(r32,20,20) |
| #define SET32pll_ctrl_SSC_MODE(r32,v) _BFSET_(r32,20,20,v) |
| #define GET16pll_ctrl_SSC_MODE(r16) _BFGET_(r16, 4, 4) |
| #define SET16pll_ctrl_SSC_MODE(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define w32pll_ctrl3 {\ |
| UNSG32 uctrl_FREQ_OFFSET : 17;\ |
| UNSG32 uctrl_FREQ_OFFSET_MODE_SELECTION : 1;\ |
| UNSG32 uctrl_FREQ_OFFSET_VALID : 1;\ |
| UNSG32 uctrl_SSC_CLK_EN : 1;\ |
| UNSG32 uctrl_SSC_MODE : 1;\ |
| UNSG32 RSVDxC_b21 : 11;\ |
| } |
| union { UNSG32 u32pll_ctrl3; |
| struct w32pll_ctrl3; |
| }; |
| #define GET32pll_ctrl_SSC_FREQ_DIV(r32) _BFGET_(r32,15, 0) |
| #define SET32pll_ctrl_SSC_FREQ_DIV(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16pll_ctrl_SSC_FREQ_DIV(r16) _BFGET_(r16,15, 0) |
| #define SET16pll_ctrl_SSC_FREQ_DIV(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32pll_ctrl_SSC_RNGE(r32) _BFGET_(r32,26,16) |
| #define SET32pll_ctrl_SSC_RNGE(r32,v) _BFSET_(r32,26,16,v) |
| #define GET16pll_ctrl_SSC_RNGE(r16) _BFGET_(r16,10, 0) |
| #define SET16pll_ctrl_SSC_RNGE(r16,v) _BFSET_(r16,10, 0,v) |
| |
| #define GET32pll_ctrl_TEST_ANA(r32) _BFGET_(r32,30,27) |
| #define SET32pll_ctrl_TEST_ANA(r32,v) _BFSET_(r32,30,27,v) |
| #define GET16pll_ctrl_TEST_ANA(r16) _BFGET_(r16,14,11) |
| #define SET16pll_ctrl_TEST_ANA(r16,v) _BFSET_(r16,14,11,v) |
| |
| #define w32pll_ctrl4 {\ |
| UNSG32 uctrl_SSC_FREQ_DIV : 16;\ |
| UNSG32 uctrl_SSC_RNGE : 11;\ |
| UNSG32 uctrl_TEST_ANA : 4;\ |
| UNSG32 RSVDx10_b31 : 1;\ |
| } |
| union { UNSG32 u32pll_ctrl4; |
| struct w32pll_ctrl4; |
| }; |
| #define GET32pll_ctrl_RESERVE_IN(r32) _BFGET_(r32, 7, 0) |
| #define SET32pll_ctrl_RESERVE_IN(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16pll_ctrl_RESERVE_IN(r16) _BFGET_(r16, 7, 0) |
| #define SET16pll_ctrl_RESERVE_IN(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define w32pll_ctrl5 {\ |
| UNSG32 uctrl_RESERVE_IN : 8;\ |
| UNSG32 RSVDx14_b8 : 24;\ |
| } |
| union { UNSG32 u32pll_ctrl5; |
| struct w32pll_ctrl5; |
| }; |
| |
| #define GET32pll_status_PLL_LOCK(r32) _BFGET_(r32, 0, 0) |
| #define SET32pll_status_PLL_LOCK(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16pll_status_PLL_LOCK(r16) _BFGET_(r16, 0, 0) |
| #define SET16pll_status_PLL_LOCK(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32pll_status_CLK_CFMOD(r32) _BFGET_(r32, 1, 1) |
| #define SET32pll_status_CLK_CFMOD(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16pll_status_CLK_CFMOD(r16) _BFGET_(r16, 1, 1) |
| #define SET16pll_status_CLK_CFMOD(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32pll_status_CLK_FMOD(r32) _BFGET_(r32, 2, 2) |
| #define SET32pll_status_CLK_FMOD(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16pll_status_CLK_FMOD(r16) _BFGET_(r16, 2, 2) |
| #define SET16pll_status_CLK_FMOD(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32pll_status_RESERVE_OUT(r32) _BFGET_(r32,10, 3) |
| #define SET32pll_status_RESERVE_OUT(r32,v) _BFSET_(r32,10, 3,v) |
| #define GET16pll_status_RESERVE_OUT(r16) _BFGET_(r16,10, 3) |
| #define SET16pll_status_RESERVE_OUT(r16,v) _BFSET_(r16,10, 3,v) |
| |
| #define w32pll_status {\ |
| UNSG32 ustatus_PLL_LOCK : 1;\ |
| UNSG32 ustatus_CLK_CFMOD : 1;\ |
| UNSG32 ustatus_CLK_FMOD : 1;\ |
| UNSG32 ustatus_RESERVE_OUT : 8;\ |
| UNSG32 RSVDx18_b11 : 21;\ |
| } |
| union { UNSG32 u32pll_status; |
| struct w32pll_status; |
| }; |
| |
| } SIE_pll; |
| |
| typedef union T32pll_ctrl |
| { UNSG32 u32; |
| struct w32pll_ctrl; |
| } T32pll_ctrl; |
| typedef union T32pll_ctrl1 |
| { UNSG32 u32; |
| struct w32pll_ctrl1; |
| } T32pll_ctrl1; |
| typedef union T32pll_ctrl2 |
| { UNSG32 u32; |
| struct w32pll_ctrl2; |
| } T32pll_ctrl2; |
| typedef union T32pll_ctrl3 |
| { UNSG32 u32; |
| struct w32pll_ctrl3; |
| } T32pll_ctrl3; |
| typedef union T32pll_ctrl4 |
| { UNSG32 u32; |
| struct w32pll_ctrl4; |
| } T32pll_ctrl4; |
| typedef union T32pll_ctrl5 |
| { UNSG32 u32; |
| struct w32pll_ctrl5; |
| } T32pll_ctrl5; |
| typedef union T32pll_status |
| { UNSG32 u32; |
| struct w32pll_status; |
| } T32pll_status; |
| |
| |
| typedef union Tpll_ctrl |
| { UNSG32 u32[6]; |
| struct { |
| struct w32pll_ctrl; |
| struct w32pll_ctrl1; |
| struct w32pll_ctrl2; |
| struct w32pll_ctrl3; |
| struct w32pll_ctrl4; |
| struct w32pll_ctrl5; |
| }; |
| } Tpll_ctrl; |
| typedef union Tpll_status |
| { UNSG32 u32[1]; |
| struct { |
| struct w32pll_status; |
| }; |
| } Tpll_status; |
| |
| |
| SIGN32 pll_drvrd(SIE_pll *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 pll_drvwr(SIE_pll *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void pll_reset(SIE_pll *p); |
| SIGN32 pll_cmp (SIE_pll *p, SIE_pll *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define pll_check(p,pie,pfx,hLOG) pll_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define pll_print(p, pfx,hLOG) pll_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| #ifndef h_AxiPCnt |
| #define h_AxiPCnt (){} |
| |
| #define RA_AxiPCnt_CTRL 0x0000 |
| |
| #define BA_AxiPCnt_CTRL_clear 0x0000 |
| #define B16AxiPCnt_CTRL_clear 0x0000 |
| #define LSb32AxiPCnt_CTRL_clear 0 |
| #define LSb16AxiPCnt_CTRL_clear 0 |
| #define bAxiPCnt_CTRL_clear 1 |
| #define MSK32AxiPCnt_CTRL_clear 0x00000001 |
| |
| #define BA_AxiPCnt_CTRL_enable 0x0000 |
| #define B16AxiPCnt_CTRL_enable 0x0000 |
| #define LSb32AxiPCnt_CTRL_enable 1 |
| #define LSb16AxiPCnt_CTRL_enable 1 |
| #define bAxiPCnt_CTRL_enable 1 |
| #define MSK32AxiPCnt_CTRL_enable 0x00000002 |
| |
| #define RA_AxiPCnt_TOTAL_CNT 0x0004 |
| |
| #define BA_AxiPCnt_TOTAL_CNT_cnt 0x0004 |
| #define B16AxiPCnt_TOTAL_CNT_cnt 0x0004 |
| #define LSb32AxiPCnt_TOTAL_CNT_cnt 0 |
| #define LSb16AxiPCnt_TOTAL_CNT_cnt 0 |
| #define bAxiPCnt_TOTAL_CNT_cnt 32 |
| #define MSK32AxiPCnt_TOTAL_CNT_cnt 0xFFFFFFFF |
| |
| #define RA_AxiPCnt_RWAIT_CNT 0x0008 |
| |
| #define BA_AxiPCnt_RWAIT_CNT_cnt 0x0008 |
| #define B16AxiPCnt_RWAIT_CNT_cnt 0x0008 |
| #define LSb32AxiPCnt_RWAIT_CNT_cnt 0 |
| #define LSb16AxiPCnt_RWAIT_CNT_cnt 0 |
| #define bAxiPCnt_RWAIT_CNT_cnt 32 |
| #define MSK32AxiPCnt_RWAIT_CNT_cnt 0xFFFFFFFF |
| |
| #define RA_AxiPCnt_RDATA_CNT 0x000C |
| |
| #define BA_AxiPCnt_RDATA_CNT_cnt 0x000C |
| #define B16AxiPCnt_RDATA_CNT_cnt 0x000C |
| #define LSb32AxiPCnt_RDATA_CNT_cnt 0 |
| #define LSb16AxiPCnt_RDATA_CNT_cnt 0 |
| #define bAxiPCnt_RDATA_CNT_cnt 32 |
| #define MSK32AxiPCnt_RDATA_CNT_cnt 0xFFFFFFFF |
| |
| #define RA_AxiPCnt_WWAIT_CNT 0x0010 |
| |
| #define BA_AxiPCnt_WWAIT_CNT_cnt 0x0010 |
| #define B16AxiPCnt_WWAIT_CNT_cnt 0x0010 |
| #define LSb32AxiPCnt_WWAIT_CNT_cnt 0 |
| #define LSb16AxiPCnt_WWAIT_CNT_cnt 0 |
| #define bAxiPCnt_WWAIT_CNT_cnt 32 |
| #define MSK32AxiPCnt_WWAIT_CNT_cnt 0xFFFFFFFF |
| |
| #define RA_AxiPCnt_WDATA_CNT 0x0014 |
| |
| #define BA_AxiPCnt_WDATA_CNT_cnt 0x0014 |
| #define B16AxiPCnt_WDATA_CNT_cnt 0x0014 |
| #define LSb32AxiPCnt_WDATA_CNT_cnt 0 |
| #define LSb16AxiPCnt_WDATA_CNT_cnt 0 |
| #define bAxiPCnt_WDATA_CNT_cnt 32 |
| #define MSK32AxiPCnt_WDATA_CNT_cnt 0xFFFFFFFF |
| |
| #define RA_AxiPCnt_OF_STATUS 0x0018 |
| |
| #define BA_AxiPCnt_OF_STATUS_total 0x0018 |
| #define B16AxiPCnt_OF_STATUS_total 0x0018 |
| #define LSb32AxiPCnt_OF_STATUS_total 0 |
| #define LSb16AxiPCnt_OF_STATUS_total 0 |
| #define bAxiPCnt_OF_STATUS_total 1 |
| #define MSK32AxiPCnt_OF_STATUS_total 0x00000001 |
| |
| #define BA_AxiPCnt_OF_STATUS_rwait 0x0018 |
| #define B16AxiPCnt_OF_STATUS_rwait 0x0018 |
| #define LSb32AxiPCnt_OF_STATUS_rwait 1 |
| #define LSb16AxiPCnt_OF_STATUS_rwait 1 |
| #define bAxiPCnt_OF_STATUS_rwait 1 |
| #define MSK32AxiPCnt_OF_STATUS_rwait 0x00000002 |
| |
| #define BA_AxiPCnt_OF_STATUS_rdata 0x0018 |
| #define B16AxiPCnt_OF_STATUS_rdata 0x0018 |
| #define LSb32AxiPCnt_OF_STATUS_rdata 2 |
| #define LSb16AxiPCnt_OF_STATUS_rdata 2 |
| #define bAxiPCnt_OF_STATUS_rdata 1 |
| #define MSK32AxiPCnt_OF_STATUS_rdata 0x00000004 |
| |
| #define BA_AxiPCnt_OF_STATUS_wwait 0x0018 |
| #define B16AxiPCnt_OF_STATUS_wwait 0x0018 |
| #define LSb32AxiPCnt_OF_STATUS_wwait 3 |
| #define LSb16AxiPCnt_OF_STATUS_wwait 3 |
| #define bAxiPCnt_OF_STATUS_wwait 1 |
| #define MSK32AxiPCnt_OF_STATUS_wwait 0x00000008 |
| |
| #define BA_AxiPCnt_OF_STATUS_wdata 0x0018 |
| #define B16AxiPCnt_OF_STATUS_wdata 0x0018 |
| #define LSb32AxiPCnt_OF_STATUS_wdata 4 |
| #define LSb16AxiPCnt_OF_STATUS_wdata 4 |
| #define bAxiPCnt_OF_STATUS_wdata 1 |
| #define MSK32AxiPCnt_OF_STATUS_wdata 0x00000010 |
| |
| |
| typedef struct SIE_AxiPCnt { |
| |
| #define GET32AxiPCnt_CTRL_clear(r32) _BFGET_(r32, 0, 0) |
| #define SET32AxiPCnt_CTRL_clear(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16AxiPCnt_CTRL_clear(r16) _BFGET_(r16, 0, 0) |
| #define SET16AxiPCnt_CTRL_clear(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32AxiPCnt_CTRL_enable(r32) _BFGET_(r32, 1, 1) |
| #define SET32AxiPCnt_CTRL_enable(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16AxiPCnt_CTRL_enable(r16) _BFGET_(r16, 1, 1) |
| #define SET16AxiPCnt_CTRL_enable(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define w32AxiPCnt_CTRL {\ |
| UNSG32 uCTRL_clear : 1;\ |
| UNSG32 uCTRL_enable : 1;\ |
| UNSG32 RSVDx0_b2 : 30;\ |
| } |
| union { UNSG32 u32AxiPCnt_CTRL; |
| struct w32AxiPCnt_CTRL; |
| }; |
| |
| #define GET32AxiPCnt_TOTAL_CNT_cnt(r32) _BFGET_(r32,31, 0) |
| #define SET32AxiPCnt_TOTAL_CNT_cnt(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32AxiPCnt_TOTAL_CNT {\ |
| UNSG32 uTOTAL_CNT_cnt : 32;\ |
| } |
| union { UNSG32 u32AxiPCnt_TOTAL_CNT; |
| struct w32AxiPCnt_TOTAL_CNT; |
| }; |
| |
| #define GET32AxiPCnt_RWAIT_CNT_cnt(r32) _BFGET_(r32,31, 0) |
| #define SET32AxiPCnt_RWAIT_CNT_cnt(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32AxiPCnt_RWAIT_CNT {\ |
| UNSG32 uRWAIT_CNT_cnt : 32;\ |
| } |
| union { UNSG32 u32AxiPCnt_RWAIT_CNT; |
| struct w32AxiPCnt_RWAIT_CNT; |
| }; |
| |
| #define GET32AxiPCnt_RDATA_CNT_cnt(r32) _BFGET_(r32,31, 0) |
| #define SET32AxiPCnt_RDATA_CNT_cnt(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32AxiPCnt_RDATA_CNT {\ |
| UNSG32 uRDATA_CNT_cnt : 32;\ |
| } |
| union { UNSG32 u32AxiPCnt_RDATA_CNT; |
| struct w32AxiPCnt_RDATA_CNT; |
| }; |
| |
| #define GET32AxiPCnt_WWAIT_CNT_cnt(r32) _BFGET_(r32,31, 0) |
| #define SET32AxiPCnt_WWAIT_CNT_cnt(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32AxiPCnt_WWAIT_CNT {\ |
| UNSG32 uWWAIT_CNT_cnt : 32;\ |
| } |
| union { UNSG32 u32AxiPCnt_WWAIT_CNT; |
| struct w32AxiPCnt_WWAIT_CNT; |
| }; |
| |
| #define GET32AxiPCnt_WDATA_CNT_cnt(r32) _BFGET_(r32,31, 0) |
| #define SET32AxiPCnt_WDATA_CNT_cnt(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32AxiPCnt_WDATA_CNT {\ |
| UNSG32 uWDATA_CNT_cnt : 32;\ |
| } |
| union { UNSG32 u32AxiPCnt_WDATA_CNT; |
| struct w32AxiPCnt_WDATA_CNT; |
| }; |
| |
| #define GET32AxiPCnt_OF_STATUS_total(r32) _BFGET_(r32, 0, 0) |
| #define SET32AxiPCnt_OF_STATUS_total(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16AxiPCnt_OF_STATUS_total(r16) _BFGET_(r16, 0, 0) |
| #define SET16AxiPCnt_OF_STATUS_total(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32AxiPCnt_OF_STATUS_rwait(r32) _BFGET_(r32, 1, 1) |
| #define SET32AxiPCnt_OF_STATUS_rwait(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16AxiPCnt_OF_STATUS_rwait(r16) _BFGET_(r16, 1, 1) |
| #define SET16AxiPCnt_OF_STATUS_rwait(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32AxiPCnt_OF_STATUS_rdata(r32) _BFGET_(r32, 2, 2) |
| #define SET32AxiPCnt_OF_STATUS_rdata(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16AxiPCnt_OF_STATUS_rdata(r16) _BFGET_(r16, 2, 2) |
| #define SET16AxiPCnt_OF_STATUS_rdata(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32AxiPCnt_OF_STATUS_wwait(r32) _BFGET_(r32, 3, 3) |
| #define SET32AxiPCnt_OF_STATUS_wwait(r32,v) _BFSET_(r32, 3, 3,v) |
| #define GET16AxiPCnt_OF_STATUS_wwait(r16) _BFGET_(r16, 3, 3) |
| #define SET16AxiPCnt_OF_STATUS_wwait(r16,v) _BFSET_(r16, 3, 3,v) |
| |
| #define GET32AxiPCnt_OF_STATUS_wdata(r32) _BFGET_(r32, 4, 4) |
| #define SET32AxiPCnt_OF_STATUS_wdata(r32,v) _BFSET_(r32, 4, 4,v) |
| #define GET16AxiPCnt_OF_STATUS_wdata(r16) _BFGET_(r16, 4, 4) |
| #define SET16AxiPCnt_OF_STATUS_wdata(r16,v) _BFSET_(r16, 4, 4,v) |
| |
| #define w32AxiPCnt_OF_STATUS {\ |
| UNSG32 uOF_STATUS_total : 1;\ |
| UNSG32 uOF_STATUS_rwait : 1;\ |
| UNSG32 uOF_STATUS_rdata : 1;\ |
| UNSG32 uOF_STATUS_wwait : 1;\ |
| UNSG32 uOF_STATUS_wdata : 1;\ |
| UNSG32 RSVDx18_b5 : 27;\ |
| } |
| union { UNSG32 u32AxiPCnt_OF_STATUS; |
| struct w32AxiPCnt_OF_STATUS; |
| }; |
| |
| } SIE_AxiPCnt; |
| |
| typedef union T32AxiPCnt_CTRL |
| { UNSG32 u32; |
| struct w32AxiPCnt_CTRL; |
| } T32AxiPCnt_CTRL; |
| typedef union T32AxiPCnt_TOTAL_CNT |
| { UNSG32 u32; |
| struct w32AxiPCnt_TOTAL_CNT; |
| } T32AxiPCnt_TOTAL_CNT; |
| typedef union T32AxiPCnt_RWAIT_CNT |
| { UNSG32 u32; |
| struct w32AxiPCnt_RWAIT_CNT; |
| } T32AxiPCnt_RWAIT_CNT; |
| typedef union T32AxiPCnt_RDATA_CNT |
| { UNSG32 u32; |
| struct w32AxiPCnt_RDATA_CNT; |
| } T32AxiPCnt_RDATA_CNT; |
| typedef union T32AxiPCnt_WWAIT_CNT |
| { UNSG32 u32; |
| struct w32AxiPCnt_WWAIT_CNT; |
| } T32AxiPCnt_WWAIT_CNT; |
| typedef union T32AxiPCnt_WDATA_CNT |
| { UNSG32 u32; |
| struct w32AxiPCnt_WDATA_CNT; |
| } T32AxiPCnt_WDATA_CNT; |
| typedef union T32AxiPCnt_OF_STATUS |
| { UNSG32 u32; |
| struct w32AxiPCnt_OF_STATUS; |
| } T32AxiPCnt_OF_STATUS; |
| |
| |
| typedef union TAxiPCnt_CTRL |
| { UNSG32 u32[1]; |
| struct { |
| struct w32AxiPCnt_CTRL; |
| }; |
| } TAxiPCnt_CTRL; |
| typedef union TAxiPCnt_TOTAL_CNT |
| { UNSG32 u32[1]; |
| struct { |
| struct w32AxiPCnt_TOTAL_CNT; |
| }; |
| } TAxiPCnt_TOTAL_CNT; |
| typedef union TAxiPCnt_RWAIT_CNT |
| { UNSG32 u32[1]; |
| struct { |
| struct w32AxiPCnt_RWAIT_CNT; |
| }; |
| } TAxiPCnt_RWAIT_CNT; |
| typedef union TAxiPCnt_RDATA_CNT |
| { UNSG32 u32[1]; |
| struct { |
| struct w32AxiPCnt_RDATA_CNT; |
| }; |
| } TAxiPCnt_RDATA_CNT; |
| typedef union TAxiPCnt_WWAIT_CNT |
| { UNSG32 u32[1]; |
| struct { |
| struct w32AxiPCnt_WWAIT_CNT; |
| }; |
| } TAxiPCnt_WWAIT_CNT; |
| typedef union TAxiPCnt_WDATA_CNT |
| { UNSG32 u32[1]; |
| struct { |
| struct w32AxiPCnt_WDATA_CNT; |
| }; |
| } TAxiPCnt_WDATA_CNT; |
| typedef union TAxiPCnt_OF_STATUS |
| { UNSG32 u32[1]; |
| struct { |
| struct w32AxiPCnt_OF_STATUS; |
| }; |
| } TAxiPCnt_OF_STATUS; |
| |
| |
| SIGN32 AxiPCnt_drvrd(SIE_AxiPCnt *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 AxiPCnt_drvwr(SIE_AxiPCnt *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void AxiPCnt_reset(SIE_AxiPCnt *p); |
| SIGN32 AxiPCnt_cmp (SIE_AxiPCnt *p, SIE_AxiPCnt *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define AxiPCnt_check(p,pie,pfx,hLOG) AxiPCnt_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define AxiPCnt_print(p, pfx,hLOG) AxiPCnt_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| #ifndef h_MctrlSS |
| #define h_MctrlSS (){} |
| |
| #define RA_MctrlSS_MC5_4TO1 0x0000 |
| |
| #define BA_MctrlSS_MC5_4TO1_enable 0x0000 |
| #define B16MctrlSS_MC5_4TO1_enable 0x0000 |
| #define LSb32MctrlSS_MC5_4TO1_enable 0 |
| #define LSb16MctrlSS_MC5_4TO1_enable 0 |
| #define bMctrlSS_MC5_4TO1_enable 1 |
| #define MSK32MctrlSS_MC5_4TO1_enable 0x00000001 |
| |
| #define RA_MctrlSS_AVIO_PRIO 0x0004 |
| |
| #define BA_MctrlSS_AVIO_PRIO_vppDhub 0x0004 |
| #define B16MctrlSS_AVIO_PRIO_vppDhub 0x0004 |
| #define LSb32MctrlSS_AVIO_PRIO_vppDhub 0 |
| #define LSb16MctrlSS_AVIO_PRIO_vppDhub 0 |
| #define bMctrlSS_AVIO_PRIO_vppDhub 4 |
| #define MSK32MctrlSS_AVIO_PRIO_vppDhub 0x0000000F |
| |
| #define BA_MctrlSS_AVIO_PRIO_agVipDhub 0x0004 |
| #define B16MctrlSS_AVIO_PRIO_agVipDhub 0x0004 |
| #define LSb32MctrlSS_AVIO_PRIO_agVipDhub 4 |
| #define LSb16MctrlSS_AVIO_PRIO_agVipDhub 4 |
| #define bMctrlSS_AVIO_PRIO_agVipDhub 4 |
| #define MSK32MctrlSS_AVIO_PRIO_agVipDhub 0x000000F0 |
| |
| #define RA_MctrlSS_ddrPhyLoopBackSrc 0x0008 |
| |
| #define BA_MctrlSS_ddrPhyLoopBackSrc_Control 0x0008 |
| #define B16MctrlSS_ddrPhyLoopBackSrc_Control 0x0008 |
| #define LSb32MctrlSS_ddrPhyLoopBackSrc_Control 0 |
| #define LSb16MctrlSS_ddrPhyLoopBackSrc_Control 0 |
| #define bMctrlSS_ddrPhyLoopBackSrc_Control 1 |
| #define MSK32MctrlSS_ddrPhyLoopBackSrc_Control 0x00000001 |
| |
| #define RA_MctrlSS_ddrPhyLoopBackConfig1 0x000C |
| |
| #define BA_MctrlSS_ddrPhyLoopBackConfig1_TST_MODE 0x000C |
| #define B16MctrlSS_ddrPhyLoopBackConfig1_TST_MODE 0x000C |
| #define LSb32MctrlSS_ddrPhyLoopBackConfig1_TST_MODE 0 |
| #define LSb16MctrlSS_ddrPhyLoopBackConfig1_TST_MODE 0 |
| #define bMctrlSS_ddrPhyLoopBackConfig1_TST_MODE 1 |
| #define MSK32MctrlSS_ddrPhyLoopBackConfig1_TST_MODE 0x00000001 |
| |
| #define BA_MctrlSS_ddrPhyLoopBackConfig1_TST_START 0x000C |
| #define B16MctrlSS_ddrPhyLoopBackConfig1_TST_START 0x000C |
| #define LSb32MctrlSS_ddrPhyLoopBackConfig1_TST_START 1 |
| #define LSb16MctrlSS_ddrPhyLoopBackConfig1_TST_START 1 |
| #define bMctrlSS_ddrPhyLoopBackConfig1_TST_START 1 |
| #define MSK32MctrlSS_ddrPhyLoopBackConfig1_TST_START 0x00000002 |
| |
| #define RA_MctrlSS_ddrPhyLoopBackConfig2 0x0010 |
| |
| #define BA_MctrlSS_ddrPhyLoopBackConfig2_CFG_DATA_DLY 0x0010 |
| #define B16MctrlSS_ddrPhyLoopBackConfig2_CFG_DATA_DLY 0x0010 |
| #define LSb32MctrlSS_ddrPhyLoopBackConfig2_CFG_DATA_DLY 0 |
| #define LSb16MctrlSS_ddrPhyLoopBackConfig2_CFG_DATA_DLY 0 |
| #define bMctrlSS_ddrPhyLoopBackConfig2_CFG_DATA_DLY 5 |
| #define MSK32MctrlSS_ddrPhyLoopBackConfig2_CFG_DATA_DLY 0x0000001F |
| |
| #define BA_MctrlSS_ddrPhyLoopBackConfig2_RSERVRED1 0x0010 |
| #define B16MctrlSS_ddrPhyLoopBackConfig2_RSERVRED1 0x0010 |
| #define LSb32MctrlSS_ddrPhyLoopBackConfig2_RSERVRED1 5 |
| #define LSb16MctrlSS_ddrPhyLoopBackConfig2_RSERVRED1 5 |
| #define bMctrlSS_ddrPhyLoopBackConfig2_RSERVRED1 3 |
| #define MSK32MctrlSS_ddrPhyLoopBackConfig2_RSERVRED1 0x000000E0 |
| |
| #define BA_MctrlSS_ddrPhyLoopBackConfig2_CFG_ADC_DLY 0x0011 |
| #define B16MctrlSS_ddrPhyLoopBackConfig2_CFG_ADC_DLY 0x0010 |
| #define LSb32MctrlSS_ddrPhyLoopBackConfig2_CFG_ADC_DLY 8 |
| #define LSb16MctrlSS_ddrPhyLoopBackConfig2_CFG_ADC_DLY 8 |
| #define bMctrlSS_ddrPhyLoopBackConfig2_CFG_ADC_DLY 5 |
| #define MSK32MctrlSS_ddrPhyLoopBackConfig2_CFG_ADC_DLY 0x00001F00 |
| |
| #define BA_MctrlSS_ddrPhyLoopBackConfig2_RSERVRED2 0x0011 |
| #define B16MctrlSS_ddrPhyLoopBackConfig2_RSERVRED2 0x0010 |
| #define LSb32MctrlSS_ddrPhyLoopBackConfig2_RSERVRED2 13 |
| #define LSb16MctrlSS_ddrPhyLoopBackConfig2_RSERVRED2 13 |
| #define bMctrlSS_ddrPhyLoopBackConfig2_RSERVRED2 2 |
| #define MSK32MctrlSS_ddrPhyLoopBackConfig2_RSERVRED2 0x00006000 |
| |
| #define BA_MctrlSS_ddrPhyLoopBackConfig2_SKIP_CMD_SUBPHY 0x0011 |
| #define B16MctrlSS_ddrPhyLoopBackConfig2_SKIP_CMD_SUBPHY 0x0010 |
| #define LSb32MctrlSS_ddrPhyLoopBackConfig2_SKIP_CMD_SUBPHY 15 |
| #define LSb16MctrlSS_ddrPhyLoopBackConfig2_SKIP_CMD_SUBPHY 15 |
| #define bMctrlSS_ddrPhyLoopBackConfig2_SKIP_CMD_SUBPHY 1 |
| #define MSK32MctrlSS_ddrPhyLoopBackConfig2_SKIP_CMD_SUBPHY 0x00008000 |
| |
| #define RA_MctrlSS_ddrPhyLoopBackConfig3 0x0014 |
| |
| #define BA_MctrlSS_ddrPhyLoopBackConfig3_SEED 0x0014 |
| #define B16MctrlSS_ddrPhyLoopBackConfig3_SEED 0x0014 |
| #define LSb32MctrlSS_ddrPhyLoopBackConfig3_SEED 0 |
| #define LSb16MctrlSS_ddrPhyLoopBackConfig3_SEED 0 |
| #define bMctrlSS_ddrPhyLoopBackConfig3_SEED 32 |
| #define MSK32MctrlSS_ddrPhyLoopBackConfig3_SEED 0xFFFFFFFF |
| |
| #define RA_MctrlSS_ddrPhyLoopBackStatus1 0x0018 |
| |
| #define BA_MctrlSS_ddrPhyLoopBackStatus1_STATUS 0x0018 |
| #define B16MctrlSS_ddrPhyLoopBackStatus1_STATUS 0x0018 |
| #define LSb32MctrlSS_ddrPhyLoopBackStatus1_STATUS 0 |
| #define LSb16MctrlSS_ddrPhyLoopBackStatus1_STATUS 0 |
| #define bMctrlSS_ddrPhyLoopBackStatus1_STATUS 16 |
| #define MSK32MctrlSS_ddrPhyLoopBackStatus1_STATUS 0x0000FFFF |
| |
| #define BA_MctrlSS_ddrPhyLoopBackStatus1_RESERVED 0x001A |
| #define B16MctrlSS_ddrPhyLoopBackStatus1_RESERVED 0x001A |
| #define LSb32MctrlSS_ddrPhyLoopBackStatus1_RESERVED 16 |
| #define LSb16MctrlSS_ddrPhyLoopBackStatus1_RESERVED 0 |
| #define bMctrlSS_ddrPhyLoopBackStatus1_RESERVED 16 |
| #define MSK32MctrlSS_ddrPhyLoopBackStatus1_RESERVED 0xFFFF0000 |
| |
| #define RA_MctrlSS_ddrPhyLoopBackStatus2 0x001C |
| |
| #define BA_MctrlSS_ddrPhyLoopBackStatus2_DONE 0x001C |
| #define B16MctrlSS_ddrPhyLoopBackStatus2_DONE 0x001C |
| #define LSb32MctrlSS_ddrPhyLoopBackStatus2_DONE 0 |
| #define LSb16MctrlSS_ddrPhyLoopBackStatus2_DONE 0 |
| #define bMctrlSS_ddrPhyLoopBackStatus2_DONE 1 |
| #define MSK32MctrlSS_ddrPhyLoopBackStatus2_DONE 0x00000001 |
| |
| #define BA_MctrlSS_ddrPhyLoopBackStatus2_FAIL 0x001C |
| #define B16MctrlSS_ddrPhyLoopBackStatus2_FAIL 0x001C |
| #define LSb32MctrlSS_ddrPhyLoopBackStatus2_FAIL 1 |
| #define LSb16MctrlSS_ddrPhyLoopBackStatus2_FAIL 1 |
| #define bMctrlSS_ddrPhyLoopBackStatus2_FAIL 1 |
| #define MSK32MctrlSS_ddrPhyLoopBackStatus2_FAIL 0x00000002 |
| |
| #define RA_MctrlSS_mc_phy_pd_ctrl 0x0020 |
| |
| #define BA_MctrlSS_mc_phy_pd_ctrl_normal_mode_ch0 0x0020 |
| #define B16MctrlSS_mc_phy_pd_ctrl_normal_mode_ch0 0x0020 |
| #define LSb32MctrlSS_mc_phy_pd_ctrl_normal_mode_ch0 0 |
| #define LSb16MctrlSS_mc_phy_pd_ctrl_normal_mode_ch0 0 |
| #define bMctrlSS_mc_phy_pd_ctrl_normal_mode_ch0 1 |
| #define MSK32MctrlSS_mc_phy_pd_ctrl_normal_mode_ch0 0x00000001 |
| |
| #define BA_MctrlSS_mc_phy_pd_ctrl_pd_en_ch0 0x0020 |
| #define B16MctrlSS_mc_phy_pd_ctrl_pd_en_ch0 0x0020 |
| #define LSb32MctrlSS_mc_phy_pd_ctrl_pd_en_ch0 1 |
| #define LSb16MctrlSS_mc_phy_pd_ctrl_pd_en_ch0 1 |
| #define bMctrlSS_mc_phy_pd_ctrl_pd_en_ch0 1 |
| #define MSK32MctrlSS_mc_phy_pd_ctrl_pd_en_ch0 0x00000002 |
| |
| #define RA_MctrlSS_mc_mstr0_qos 0x0024 |
| |
| #define BA_MctrlSS_mc_mstr0_qos_awqos 0x0024 |
| #define B16MctrlSS_mc_mstr0_qos_awqos 0x0024 |
| #define LSb32MctrlSS_mc_mstr0_qos_awqos 0 |
| #define LSb16MctrlSS_mc_mstr0_qos_awqos 0 |
| #define bMctrlSS_mc_mstr0_qos_awqos 4 |
| #define MSK32MctrlSS_mc_mstr0_qos_awqos 0x0000000F |
| |
| #define BA_MctrlSS_mc_mstr0_qos_arqos 0x0024 |
| #define B16MctrlSS_mc_mstr0_qos_arqos 0x0024 |
| #define LSb32MctrlSS_mc_mstr0_qos_arqos 4 |
| #define LSb16MctrlSS_mc_mstr0_qos_arqos 4 |
| #define bMctrlSS_mc_mstr0_qos_arqos 4 |
| #define MSK32MctrlSS_mc_mstr0_qos_arqos 0x000000F0 |
| |
| #define RA_MctrlSS_mc_mstr1_qos 0x0028 |
| |
| #define BA_MctrlSS_mc_mstr1_qos_awqos 0x0028 |
| #define B16MctrlSS_mc_mstr1_qos_awqos 0x0028 |
| #define LSb32MctrlSS_mc_mstr1_qos_awqos 0 |
| #define LSb16MctrlSS_mc_mstr1_qos_awqos 0 |
| #define bMctrlSS_mc_mstr1_qos_awqos 4 |
| #define MSK32MctrlSS_mc_mstr1_qos_awqos 0x0000000F |
| |
| #define BA_MctrlSS_mc_mstr1_qos_arqos 0x0028 |
| #define B16MctrlSS_mc_mstr1_qos_arqos 0x0028 |
| #define LSb32MctrlSS_mc_mstr1_qos_arqos 4 |
| #define LSb16MctrlSS_mc_mstr1_qos_arqos 4 |
| #define bMctrlSS_mc_mstr1_qos_arqos 4 |
| #define MSK32MctrlSS_mc_mstr1_qos_arqos 0x000000F0 |
| |
| #define RA_MctrlSS_mc_mstr2_qos 0x002C |
| |
| #define BA_MctrlSS_mc_mstr2_qos_awqos 0x002C |
| #define B16MctrlSS_mc_mstr2_qos_awqos 0x002C |
| #define LSb32MctrlSS_mc_mstr2_qos_awqos 0 |
| #define LSb16MctrlSS_mc_mstr2_qos_awqos 0 |
| #define bMctrlSS_mc_mstr2_qos_awqos 4 |
| #define MSK32MctrlSS_mc_mstr2_qos_awqos 0x0000000F |
| |
| #define BA_MctrlSS_mc_mstr2_qos_arqos 0x002C |
| #define B16MctrlSS_mc_mstr2_qos_arqos 0x002C |
| #define LSb32MctrlSS_mc_mstr2_qos_arqos 4 |
| #define LSb16MctrlSS_mc_mstr2_qos_arqos 4 |
| #define bMctrlSS_mc_mstr2_qos_arqos 4 |
| #define MSK32MctrlSS_mc_mstr2_qos_arqos 0x000000F0 |
| |
| #define RA_MctrlSS_mc_mstr3_qos 0x0030 |
| |
| #define BA_MctrlSS_mc_mstr3_qos_awqos 0x0030 |
| #define B16MctrlSS_mc_mstr3_qos_awqos 0x0030 |
| #define LSb32MctrlSS_mc_mstr3_qos_awqos 0 |
| #define LSb16MctrlSS_mc_mstr3_qos_awqos 0 |
| #define bMctrlSS_mc_mstr3_qos_awqos 4 |
| #define MSK32MctrlSS_mc_mstr3_qos_awqos 0x0000000F |
| |
| #define BA_MctrlSS_mc_mstr3_qos_arqos 0x0030 |
| #define B16MctrlSS_mc_mstr3_qos_arqos 0x0030 |
| #define LSb32MctrlSS_mc_mstr3_qos_arqos 4 |
| #define LSb16MctrlSS_mc_mstr3_qos_arqos 4 |
| #define bMctrlSS_mc_mstr3_qos_arqos 4 |
| #define MSK32MctrlSS_mc_mstr3_qos_arqos 0x000000F0 |
| |
| #define RA_MctrlSS_mc_mstr4_qos 0x0034 |
| |
| #define BA_MctrlSS_mc_mstr4_qos_awqos 0x0034 |
| #define B16MctrlSS_mc_mstr4_qos_awqos 0x0034 |
| #define LSb32MctrlSS_mc_mstr4_qos_awqos 0 |
| #define LSb16MctrlSS_mc_mstr4_qos_awqos 0 |
| #define bMctrlSS_mc_mstr4_qos_awqos 4 |
| #define MSK32MctrlSS_mc_mstr4_qos_awqos 0x0000000F |
| |
| #define BA_MctrlSS_mc_mstr4_qos_arqos 0x0034 |
| #define B16MctrlSS_mc_mstr4_qos_arqos 0x0034 |
| #define LSb32MctrlSS_mc_mstr4_qos_arqos 4 |
| #define LSb16MctrlSS_mc_mstr4_qos_arqos 4 |
| #define bMctrlSS_mc_mstr4_qos_arqos 4 |
| #define MSK32MctrlSS_mc_mstr4_qos_arqos 0x000000F0 |
| |
| #define RA_MctrlSS_mc_mstr5_qos 0x0038 |
| |
| #define BA_MctrlSS_mc_mstr5_qos_awqos 0x0038 |
| #define B16MctrlSS_mc_mstr5_qos_awqos 0x0038 |
| #define LSb32MctrlSS_mc_mstr5_qos_awqos 0 |
| #define LSb16MctrlSS_mc_mstr5_qos_awqos 0 |
| #define bMctrlSS_mc_mstr5_qos_awqos 4 |
| #define MSK32MctrlSS_mc_mstr5_qos_awqos 0x0000000F |
| |
| #define BA_MctrlSS_mc_mstr5_qos_arqos 0x0038 |
| #define B16MctrlSS_mc_mstr5_qos_arqos 0x0038 |
| #define LSb32MctrlSS_mc_mstr5_qos_arqos 4 |
| #define LSb16MctrlSS_mc_mstr5_qos_arqos 4 |
| #define bMctrlSS_mc_mstr5_qos_arqos 4 |
| #define MSK32MctrlSS_mc_mstr5_qos_arqos 0x000000F0 |
| |
| #define RA_MctrlSS_mc_mstr6_qos 0x003C |
| |
| #define BA_MctrlSS_mc_mstr6_qos_awqos 0x003C |
| #define B16MctrlSS_mc_mstr6_qos_awqos 0x003C |
| #define LSb32MctrlSS_mc_mstr6_qos_awqos 0 |
| #define LSb16MctrlSS_mc_mstr6_qos_awqos 0 |
| #define bMctrlSS_mc_mstr6_qos_awqos 4 |
| #define MSK32MctrlSS_mc_mstr6_qos_awqos 0x0000000F |
| |
| #define BA_MctrlSS_mc_mstr6_qos_arqos 0x003C |
| #define B16MctrlSS_mc_mstr6_qos_arqos 0x003C |
| #define LSb32MctrlSS_mc_mstr6_qos_arqos 4 |
| #define LSb16MctrlSS_mc_mstr6_qos_arqos 4 |
| #define bMctrlSS_mc_mstr6_qos_arqos 4 |
| #define MSK32MctrlSS_mc_mstr6_qos_arqos 0x000000F0 |
| |
| #define RA_MctrlSS_mc_mstr7_qos 0x0040 |
| |
| #define BA_MctrlSS_mc_mstr7_qos_awqos 0x0040 |
| #define B16MctrlSS_mc_mstr7_qos_awqos 0x0040 |
| #define LSb32MctrlSS_mc_mstr7_qos_awqos 0 |
| #define LSb16MctrlSS_mc_mstr7_qos_awqos 0 |
| #define bMctrlSS_mc_mstr7_qos_awqos 4 |
| #define MSK32MctrlSS_mc_mstr7_qos_awqos 0x0000000F |
| |
| #define BA_MctrlSS_mc_mstr7_qos_arqos 0x0040 |
| #define B16MctrlSS_mc_mstr7_qos_arqos 0x0040 |
| #define LSb32MctrlSS_mc_mstr7_qos_arqos 4 |
| #define LSb16MctrlSS_mc_mstr7_qos_arqos 4 |
| #define bMctrlSS_mc_mstr7_qos_arqos 4 |
| #define MSK32MctrlSS_mc_mstr7_qos_arqos 0x000000F0 |
| |
| #define RA_MctrlSS_mc_hw_phy_dll_update_req 0x0044 |
| |
| #define BA_MctrlSS_mc_hw_phy_dll_update_req_en 0x0044 |
| #define B16MctrlSS_mc_hw_phy_dll_update_req_en 0x0044 |
| #define LSb32MctrlSS_mc_hw_phy_dll_update_req_en 0 |
| #define LSb16MctrlSS_mc_hw_phy_dll_update_req_en 0 |
| #define bMctrlSS_mc_hw_phy_dll_update_req_en 1 |
| #define MSK32MctrlSS_mc_hw_phy_dll_update_req_en 0x00000001 |
| |
| #define RA_MctrlSS_mc_hw_dfc_ctrl 0x0048 |
| |
| #define BA_MctrlSS_mc_hw_dfc_ctrl_reg_table_req 0x0048 |
| #define B16MctrlSS_mc_hw_dfc_ctrl_reg_table_req 0x0048 |
| #define LSb32MctrlSS_mc_hw_dfc_ctrl_reg_table_req 0 |
| #define LSb16MctrlSS_mc_hw_dfc_ctrl_reg_table_req 0 |
| #define bMctrlSS_mc_hw_dfc_ctrl_reg_table_req 1 |
| #define MSK32MctrlSS_mc_hw_dfc_ctrl_reg_table_req 0x00000001 |
| |
| #define BA_MctrlSS_mc_hw_dfc_ctrl_reg_table_type 0x0048 |
| #define B16MctrlSS_mc_hw_dfc_ctrl_reg_table_type 0x0048 |
| #define LSb32MctrlSS_mc_hw_dfc_ctrl_reg_table_type 1 |
| #define LSb16MctrlSS_mc_hw_dfc_ctrl_reg_table_type 1 |
| #define bMctrlSS_mc_hw_dfc_ctrl_reg_table_type 5 |
| #define MSK32MctrlSS_mc_hw_dfc_ctrl_reg_table_type 0x0000003E |
| |
| #define BA_MctrlSS_mc_hw_dfc_ctrl_reg_table_wait_ack 0x0048 |
| #define B16MctrlSS_mc_hw_dfc_ctrl_reg_table_wait_ack 0x0048 |
| #define LSb32MctrlSS_mc_hw_dfc_ctrl_reg_table_wait_ack 6 |
| #define LSb16MctrlSS_mc_hw_dfc_ctrl_reg_table_wait_ack 6 |
| #define bMctrlSS_mc_hw_dfc_ctrl_reg_table_wait_ack 1 |
| #define MSK32MctrlSS_mc_hw_dfc_ctrl_reg_table_wait_ack 0x00000040 |
| |
| #define BA_MctrlSS_mc_hw_dfc_ctrl_sleep_req 0x0048 |
| #define B16MctrlSS_mc_hw_dfc_ctrl_sleep_req 0x0048 |
| #define LSb32MctrlSS_mc_hw_dfc_ctrl_sleep_req 7 |
| #define LSb16MctrlSS_mc_hw_dfc_ctrl_sleep_req 7 |
| #define bMctrlSS_mc_hw_dfc_ctrl_sleep_req 1 |
| #define MSK32MctrlSS_mc_hw_dfc_ctrl_sleep_req 0x00000080 |
| |
| #define BA_MctrlSS_mc_hw_dfc_ctrl_sleep_type 0x0049 |
| #define B16MctrlSS_mc_hw_dfc_ctrl_sleep_type 0x0048 |
| #define LSb32MctrlSS_mc_hw_dfc_ctrl_sleep_type 8 |
| #define LSb16MctrlSS_mc_hw_dfc_ctrl_sleep_type 8 |
| #define bMctrlSS_mc_hw_dfc_ctrl_sleep_type 3 |
| #define MSK32MctrlSS_mc_hw_dfc_ctrl_sleep_type 0x00000700 |
| |
| #define RA_MctrlSS_mc_hw_dfc_sts 0x004C |
| |
| #define BA_MctrlSS_mc_hw_dfc_sts_reg_table_req_ack 0x004C |
| #define B16MctrlSS_mc_hw_dfc_sts_reg_table_req_ack 0x004C |
| #define LSb32MctrlSS_mc_hw_dfc_sts_reg_table_req_ack 0 |
| #define LSb16MctrlSS_mc_hw_dfc_sts_reg_table_req_ack 0 |
| #define bMctrlSS_mc_hw_dfc_sts_reg_table_req_ack 1 |
| #define MSK32MctrlSS_mc_hw_dfc_sts_reg_table_req_ack 0x00000001 |
| |
| #define BA_MctrlSS_mc_hw_dfc_sts_reg_table_wait_req 0x004C |
| #define B16MctrlSS_mc_hw_dfc_sts_reg_table_wait_req 0x004C |
| #define LSb32MctrlSS_mc_hw_dfc_sts_reg_table_wait_req 1 |
| #define LSb16MctrlSS_mc_hw_dfc_sts_reg_table_wait_req 1 |
| #define bMctrlSS_mc_hw_dfc_sts_reg_table_wait_req 1 |
| #define MSK32MctrlSS_mc_hw_dfc_sts_reg_table_wait_req 0x00000002 |
| |
| #define BA_MctrlSS_mc_hw_dfc_sts_sleep_req_ack 0x004C |
| #define B16MctrlSS_mc_hw_dfc_sts_sleep_req_ack 0x004C |
| #define LSb32MctrlSS_mc_hw_dfc_sts_sleep_req_ack 2 |
| #define LSb16MctrlSS_mc_hw_dfc_sts_sleep_req_ack 2 |
| #define bMctrlSS_mc_hw_dfc_sts_sleep_req_ack 1 |
| #define MSK32MctrlSS_mc_hw_dfc_sts_sleep_req_ack 0x00000004 |
| |
| #define RA_MctrlSS_memPll 0x0050 |
| |
| #define RA_MctrlSS_RWTC_31to0 0x006C |
| |
| #define BA_MctrlSS_RWTC_31to0_value 0x006C |
| #define B16MctrlSS_RWTC_31to0_value 0x006C |
| #define LSb32MctrlSS_RWTC_31to0_value 0 |
| #define LSb16MctrlSS_RWTC_31to0_value 0 |
| #define bMctrlSS_RWTC_31to0_value 32 |
| #define MSK32MctrlSS_RWTC_31to0_value 0xFFFFFFFF |
| |
| #define RA_MctrlSS_RWTC_57to32 0x0070 |
| |
| #define BA_MctrlSS_RWTC_57to32_value 0x0070 |
| #define B16MctrlSS_RWTC_57to32_value 0x0070 |
| #define LSb32MctrlSS_RWTC_57to32_value 0 |
| #define LSb16MctrlSS_RWTC_57to32_value 0 |
| #define bMctrlSS_RWTC_57to32_value 26 |
| #define MSK32MctrlSS_RWTC_57to32_value 0x03FFFFFF |
| |
| #define RA_MctrlSS_DDRCLK_VREG_CTRL_0 0x0074 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_0_PU 0x0074 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_0_PU 0x0074 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_0_PU 0 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_0_PU 0 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_0_PU 1 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_0_PU 0x00000001 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_0_LP 0x0074 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_0_LP 0x0074 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_0_LP 1 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_0_LP 1 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_0_LP 1 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_0_LP 0x00000002 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_0_BYPASS 0x0074 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_0_BYPASS 0x0074 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_0_BYPASS 2 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_0_BYPASS 2 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_0_BYPASS 1 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_0_BYPASS 0x00000004 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_0_VSEL 0x0074 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_0_VSEL 0x0074 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_0_VSEL 3 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_0_VSEL 3 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_0_VSEL 3 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_0_VSEL 0x00000038 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_0_TSTMON_EN 0x0074 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_0_TSTMON_EN 0x0074 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_0_TSTMON_EN 6 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_0_TSTMON_EN 6 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_0_TSTMON_EN 1 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_0_TSTMON_EN 0x00000040 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_0_TESTMON 0x0074 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_0_TESTMON 0x0074 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_0_TESTMON 7 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_0_TESTMON 7 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_0_TESTMON 3 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_0_TESTMON 0x00000380 |
| |
| #define RA_MctrlSS_DDRCLK_VREG_CTRL_1 0x0078 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_1_PU 0x0078 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_1_PU 0x0078 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_1_PU 0 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_1_PU 0 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_1_PU 1 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_1_PU 0x00000001 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_1_LP 0x0078 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_1_LP 0x0078 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_1_LP 1 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_1_LP 1 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_1_LP 1 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_1_LP 0x00000002 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_1_BYPASS 0x0078 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_1_BYPASS 0x0078 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_1_BYPASS 2 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_1_BYPASS 2 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_1_BYPASS 1 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_1_BYPASS 0x00000004 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_1_VSEL 0x0078 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_1_VSEL 0x0078 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_1_VSEL 3 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_1_VSEL 3 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_1_VSEL 3 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_1_VSEL 0x00000038 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_1_TSTMON_EN 0x0078 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_1_TSTMON_EN 0x0078 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_1_TSTMON_EN 6 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_1_TSTMON_EN 6 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_1_TSTMON_EN 1 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_1_TSTMON_EN 0x00000040 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_1_TESTMON 0x0078 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_1_TESTMON 0x0078 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_1_TESTMON 7 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_1_TESTMON 7 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_1_TESTMON 3 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_1_TESTMON 0x00000380 |
| |
| #define RA_MctrlSS_DDRCLK_VREG_CTRL_2 0x007C |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_2_PU 0x007C |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_2_PU 0x007C |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_2_PU 0 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_2_PU 0 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_2_PU 1 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_2_PU 0x00000001 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_2_LP 0x007C |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_2_LP 0x007C |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_2_LP 1 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_2_LP 1 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_2_LP 1 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_2_LP 0x00000002 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_2_BYPASS 0x007C |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_2_BYPASS 0x007C |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_2_BYPASS 2 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_2_BYPASS 2 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_2_BYPASS 1 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_2_BYPASS 0x00000004 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_2_VSEL 0x007C |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_2_VSEL 0x007C |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_2_VSEL 3 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_2_VSEL 3 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_2_VSEL 3 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_2_VSEL 0x00000038 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_2_TSTMON_EN 0x007C |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_2_TSTMON_EN 0x007C |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_2_TSTMON_EN 6 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_2_TSTMON_EN 6 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_2_TSTMON_EN 1 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_2_TSTMON_EN 0x00000040 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_2_TESTMON 0x007C |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_2_TESTMON 0x007C |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_2_TESTMON 7 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_2_TESTMON 7 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_2_TESTMON 3 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_2_TESTMON 0x00000380 |
| |
| #define RA_MctrlSS_DDRCLK_VREG_CTRL_3 0x0080 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_3_PU 0x0080 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_3_PU 0x0080 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_3_PU 0 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_3_PU 0 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_3_PU 1 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_3_PU 0x00000001 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_3_LP 0x0080 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_3_LP 0x0080 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_3_LP 1 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_3_LP 1 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_3_LP 1 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_3_LP 0x00000002 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_3_BYPASS 0x0080 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_3_BYPASS 0x0080 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_3_BYPASS 2 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_3_BYPASS 2 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_3_BYPASS 1 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_3_BYPASS 0x00000004 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_3_VSEL 0x0080 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_3_VSEL 0x0080 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_3_VSEL 3 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_3_VSEL 3 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_3_VSEL 3 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_3_VSEL 0x00000038 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_3_TSTMON_EN 0x0080 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_3_TSTMON_EN 0x0080 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_3_TSTMON_EN 6 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_3_TSTMON_EN 6 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_3_TSTMON_EN 1 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_3_TSTMON_EN 0x00000040 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_3_TESTMON 0x0080 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_3_TESTMON 0x0080 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_3_TESTMON 7 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_3_TESTMON 7 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_3_TESTMON 3 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_3_TESTMON 0x00000380 |
| |
| #define RA_MctrlSS_DDRCLK_VREG_CTRL_4 0x0084 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_4_PU 0x0084 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_4_PU 0x0084 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_4_PU 0 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_4_PU 0 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_4_PU 1 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_4_PU 0x00000001 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_4_LP 0x0084 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_4_LP 0x0084 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_4_LP 1 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_4_LP 1 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_4_LP 1 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_4_LP 0x00000002 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_4_BYPASS 0x0084 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_4_BYPASS 0x0084 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_4_BYPASS 2 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_4_BYPASS 2 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_4_BYPASS 1 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_4_BYPASS 0x00000004 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_4_VSEL 0x0084 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_4_VSEL 0x0084 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_4_VSEL 3 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_4_VSEL 3 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_4_VSEL 3 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_4_VSEL 0x00000038 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_4_TSTMON_EN 0x0084 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_4_TSTMON_EN 0x0084 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_4_TSTMON_EN 6 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_4_TSTMON_EN 6 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_4_TSTMON_EN 1 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_4_TSTMON_EN 0x00000040 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_4_TESTMON 0x0084 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_4_TESTMON 0x0084 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_4_TESTMON 7 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_4_TESTMON 7 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_4_TESTMON 3 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_4_TESTMON 0x00000380 |
| |
| #define RA_MctrlSS_DDRCLK_VREG_CTRL_5 0x0088 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_5_PU 0x0088 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_5_PU 0x0088 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_5_PU 0 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_5_PU 0 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_5_PU 1 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_5_PU 0x00000001 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_5_LP 0x0088 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_5_LP 0x0088 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_5_LP 1 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_5_LP 1 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_5_LP 1 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_5_LP 0x00000002 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_5_BYPASS 0x0088 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_5_BYPASS 0x0088 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_5_BYPASS 2 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_5_BYPASS 2 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_5_BYPASS 1 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_5_BYPASS 0x00000004 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_5_VSEL 0x0088 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_5_VSEL 0x0088 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_5_VSEL 3 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_5_VSEL 3 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_5_VSEL 3 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_5_VSEL 0x00000038 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_5_TSTMON_EN 0x0088 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_5_TSTMON_EN 0x0088 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_5_TSTMON_EN 6 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_5_TSTMON_EN 6 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_5_TSTMON_EN 1 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_5_TSTMON_EN 0x00000040 |
| |
| #define BA_MctrlSS_DDRCLK_VREG_CTRL_5_TESTMON 0x0088 |
| #define B16MctrlSS_DDRCLK_VREG_CTRL_5_TESTMON 0x0088 |
| #define LSb32MctrlSS_DDRCLK_VREG_CTRL_5_TESTMON 7 |
| #define LSb16MctrlSS_DDRCLK_VREG_CTRL_5_TESTMON 7 |
| #define bMctrlSS_DDRCLK_VREG_CTRL_5_TESTMON 3 |
| #define MSK32MctrlSS_DDRCLK_VREG_CTRL_5_TESTMON 0x00000380 |
| |
| #define RA_MctrlSS_GFX3D_PC 0x008C |
| |
| #define RA_MctrlSS_DDRScramCtrl 0x8000 |
| |
| #define BA_MctrlSS_DDRScramCtrl_Secure_Key 0x8000 |
| #define B16MctrlSS_DDRScramCtrl_Secure_Key 0x8000 |
| #define LSb32MctrlSS_DDRScramCtrl_Secure_Key 0 |
| #define LSb16MctrlSS_DDRScramCtrl_Secure_Key 0 |
| #define bMctrlSS_DDRScramCtrl_Secure_Key 1 |
| #define MSK32MctrlSS_DDRScramCtrl_Secure_Key 0x00000001 |
| |
| #define BA_MctrlSS_DDRScramCtrl_En 0x8000 |
| #define B16MctrlSS_DDRScramCtrl_En 0x8000 |
| #define LSb32MctrlSS_DDRScramCtrl_En 1 |
| #define LSb16MctrlSS_DDRScramCtrl_En 1 |
| #define bMctrlSS_DDRScramCtrl_En 1 |
| #define MSK32MctrlSS_DDRScramCtrl_En 0x00000002 |
| |
| #define RA_MctrlSS_DDRScramCtrl1 0x8004 |
| |
| #define BA_MctrlSS_DDRScramCtrl_Key0_word0 0x8004 |
| #define B16MctrlSS_DDRScramCtrl_Key0_word0 0x8004 |
| #define LSb32MctrlSS_DDRScramCtrl_Key0_word0 0 |
| #define LSb16MctrlSS_DDRScramCtrl_Key0_word0 0 |
| #define bMctrlSS_DDRScramCtrl_Key0_word0 32 |
| #define MSK32MctrlSS_DDRScramCtrl_Key0_word0 0xFFFFFFFF |
| |
| #define RA_MctrlSS_DDRScramCtrl2 0x8008 |
| |
| #define BA_MctrlSS_DDRScramCtrl_Key0_word1 0x8008 |
| #define B16MctrlSS_DDRScramCtrl_Key0_word1 0x8008 |
| #define LSb32MctrlSS_DDRScramCtrl_Key0_word1 0 |
| #define LSb16MctrlSS_DDRScramCtrl_Key0_word1 0 |
| #define bMctrlSS_DDRScramCtrl_Key0_word1 32 |
| #define MSK32MctrlSS_DDRScramCtrl_Key0_word1 0xFFFFFFFF |
| |
| #define RA_MctrlSS_DDRScramCtrl3 0x800C |
| |
| #define BA_MctrlSS_DDRScramCtrl_Key0_word2 0x800C |
| #define B16MctrlSS_DDRScramCtrl_Key0_word2 0x800C |
| #define LSb32MctrlSS_DDRScramCtrl_Key0_word2 0 |
| #define LSb16MctrlSS_DDRScramCtrl_Key0_word2 0 |
| #define bMctrlSS_DDRScramCtrl_Key0_word2 32 |
| #define MSK32MctrlSS_DDRScramCtrl_Key0_word2 0xFFFFFFFF |
| |
| #define RA_MctrlSS_DDRScramCtrl4 0x8010 |
| |
| #define BA_MctrlSS_DDRScramCtrl_Key0_word3 0x8010 |
| #define B16MctrlSS_DDRScramCtrl_Key0_word3 0x8010 |
| #define LSb32MctrlSS_DDRScramCtrl_Key0_word3 0 |
| #define LSb16MctrlSS_DDRScramCtrl_Key0_word3 0 |
| #define bMctrlSS_DDRScramCtrl_Key0_word3 32 |
| #define MSK32MctrlSS_DDRScramCtrl_Key0_word3 0xFFFFFFFF |
| |
| #define RA_MctrlSS_DDRScramCtrl5 0x8014 |
| |
| #define BA_MctrlSS_DDRScramCtrl_Key0_addr 0x8014 |
| #define B16MctrlSS_DDRScramCtrl_Key0_addr 0x8014 |
| #define LSb32MctrlSS_DDRScramCtrl_Key0_addr 0 |
| #define LSb16MctrlSS_DDRScramCtrl_Key0_addr 0 |
| #define bMctrlSS_DDRScramCtrl_Key0_addr 32 |
| #define MSK32MctrlSS_DDRScramCtrl_Key0_addr 0xFFFFFFFF |
| |
| #define RA_MctrlSS_DDRScramCtrl6 0x8018 |
| |
| #define BA_MctrlSS_DDRScramCtrl_Key0_mask 0x8018 |
| #define B16MctrlSS_DDRScramCtrl_Key0_mask 0x8018 |
| #define LSb32MctrlSS_DDRScramCtrl_Key0_mask 0 |
| #define LSb16MctrlSS_DDRScramCtrl_Key0_mask 0 |
| #define bMctrlSS_DDRScramCtrl_Key0_mask 32 |
| #define MSK32MctrlSS_DDRScramCtrl_Key0_mask 0xFFFFFFFF |
| |
| #define RA_MctrlSS_DDRScramCtrl7 0x801C |
| |
| #define BA_MctrlSS_DDRScramCtrl_Key1_word0 0x801C |
| #define B16MctrlSS_DDRScramCtrl_Key1_word0 0x801C |
| #define LSb32MctrlSS_DDRScramCtrl_Key1_word0 0 |
| #define LSb16MctrlSS_DDRScramCtrl_Key1_word0 0 |
| #define bMctrlSS_DDRScramCtrl_Key1_word0 32 |
| #define MSK32MctrlSS_DDRScramCtrl_Key1_word0 0xFFFFFFFF |
| |
| #define RA_MctrlSS_DDRScramCtrl8 0x8020 |
| |
| #define BA_MctrlSS_DDRScramCtrl_Key1_word1 0x8020 |
| #define B16MctrlSS_DDRScramCtrl_Key1_word1 0x8020 |
| #define LSb32MctrlSS_DDRScramCtrl_Key1_word1 0 |
| #define LSb16MctrlSS_DDRScramCtrl_Key1_word1 0 |
| #define bMctrlSS_DDRScramCtrl_Key1_word1 32 |
| #define MSK32MctrlSS_DDRScramCtrl_Key1_word1 0xFFFFFFFF |
| |
| #define RA_MctrlSS_DDRScramCtrl9 0x8024 |
| |
| #define BA_MctrlSS_DDRScramCtrl_Key1_word2 0x8024 |
| #define B16MctrlSS_DDRScramCtrl_Key1_word2 0x8024 |
| #define LSb32MctrlSS_DDRScramCtrl_Key1_word2 0 |
| #define LSb16MctrlSS_DDRScramCtrl_Key1_word2 0 |
| #define bMctrlSS_DDRScramCtrl_Key1_word2 32 |
| #define MSK32MctrlSS_DDRScramCtrl_Key1_word2 0xFFFFFFFF |
| |
| #define RA_MctrlSS_DDRScramCtrl10 0x8028 |
| |
| #define BA_MctrlSS_DDRScramCtrl_Key1_word3 0x8028 |
| #define B16MctrlSS_DDRScramCtrl_Key1_word3 0x8028 |
| #define LSb32MctrlSS_DDRScramCtrl_Key1_word3 0 |
| #define LSb16MctrlSS_DDRScramCtrl_Key1_word3 0 |
| #define bMctrlSS_DDRScramCtrl_Key1_word3 32 |
| #define MSK32MctrlSS_DDRScramCtrl_Key1_word3 0xFFFFFFFF |
| |
| #define RA_MctrlSS_DDRScramCtrl11 0x802C |
| |
| #define BA_MctrlSS_DDRScramCtrl_Key1_addr 0x802C |
| #define B16MctrlSS_DDRScramCtrl_Key1_addr 0x802C |
| #define LSb32MctrlSS_DDRScramCtrl_Key1_addr 0 |
| #define LSb16MctrlSS_DDRScramCtrl_Key1_addr 0 |
| #define bMctrlSS_DDRScramCtrl_Key1_addr 32 |
| #define MSK32MctrlSS_DDRScramCtrl_Key1_addr 0xFFFFFFFF |
| |
| #define RA_MctrlSS_DDRScramCtrl12 0x8030 |
| |
| #define BA_MctrlSS_DDRScramCtrl_Key1_mask 0x8030 |
| #define B16MctrlSS_DDRScramCtrl_Key1_mask 0x8030 |
| #define LSb32MctrlSS_DDRScramCtrl_Key1_mask 0 |
| #define LSb16MctrlSS_DDRScramCtrl_Key1_mask 0 |
| #define bMctrlSS_DDRScramCtrl_Key1_mask 32 |
| #define MSK32MctrlSS_DDRScramCtrl_Key1_mask 0xFFFFFFFF |
| |
| #define RA_MctrlSS_DDRScramCtrl13 0x8034 |
| |
| #define BA_MctrlSS_DDRScramCtrl_W_latency 0x8034 |
| #define B16MctrlSS_DDRScramCtrl_W_latency 0x8034 |
| #define LSb32MctrlSS_DDRScramCtrl_W_latency 0 |
| #define LSb16MctrlSS_DDRScramCtrl_W_latency 0 |
| #define bMctrlSS_DDRScramCtrl_W_latency 5 |
| #define MSK32MctrlSS_DDRScramCtrl_W_latency 0x0000001F |
| |
| #define BA_MctrlSS_DDRScramCtrl_R_latency 0x8034 |
| #define B16MctrlSS_DDRScramCtrl_R_latency 0x8034 |
| #define LSb32MctrlSS_DDRScramCtrl_R_latency 5 |
| #define LSb16MctrlSS_DDRScramCtrl_R_latency 5 |
| #define bMctrlSS_DDRScramCtrl_R_latency 5 |
| #define MSK32MctrlSS_DDRScramCtrl_R_latency 0x000003E0 |
| |
| #define BA_MctrlSS_DDRScramCtrl_cal_latency 0x8035 |
| #define B16MctrlSS_DDRScramCtrl_cal_latency 0x8034 |
| #define LSb32MctrlSS_DDRScramCtrl_cal_latency 10 |
| #define LSb16MctrlSS_DDRScramCtrl_cal_latency 10 |
| #define bMctrlSS_DDRScramCtrl_cal_latency 4 |
| #define MSK32MctrlSS_DDRScramCtrl_cal_latency 0x00003C00 |
| |
| #define RA_MctrlSS_rz_ctrl 0x8038 |
| |
| #define BA_MctrlSS_rz_ctrl_arrz_pass 0x8038 |
| #define B16MctrlSS_rz_ctrl_arrz_pass 0x8038 |
| #define LSb32MctrlSS_rz_ctrl_arrz_pass 0 |
| #define LSb16MctrlSS_rz_ctrl_arrz_pass 0 |
| #define bMctrlSS_rz_ctrl_arrz_pass 8 |
| #define MSK32MctrlSS_rz_ctrl_arrz_pass 0x000000FF |
| |
| #define BA_MctrlSS_rz_ctrl_awrz_pass 0x8039 |
| #define B16MctrlSS_rz_ctrl_awrz_pass 0x8038 |
| #define LSb32MctrlSS_rz_ctrl_awrz_pass 8 |
| #define LSb16MctrlSS_rz_ctrl_awrz_pass 8 |
| #define bMctrlSS_rz_ctrl_awrz_pass 8 |
| #define MSK32MctrlSS_rz_ctrl_awrz_pass 0x0000FF00 |
| |
| |
| typedef struct SIE_MctrlSS { |
| |
| #define GET32MctrlSS_MC5_4TO1_enable(r32) _BFGET_(r32, 0, 0) |
| #define SET32MctrlSS_MC5_4TO1_enable(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16MctrlSS_MC5_4TO1_enable(r16) _BFGET_(r16, 0, 0) |
| #define SET16MctrlSS_MC5_4TO1_enable(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32MctrlSS_MC5_4TO1 {\ |
| UNSG32 uMC5_4TO1_enable : 1;\ |
| UNSG32 RSVDx0_b1 : 31;\ |
| } |
| union { UNSG32 u32MctrlSS_MC5_4TO1; |
| struct w32MctrlSS_MC5_4TO1; |
| }; |
| |
| #define GET32MctrlSS_AVIO_PRIO_vppDhub(r32) _BFGET_(r32, 3, 0) |
| #define SET32MctrlSS_AVIO_PRIO_vppDhub(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16MctrlSS_AVIO_PRIO_vppDhub(r16) _BFGET_(r16, 3, 0) |
| #define SET16MctrlSS_AVIO_PRIO_vppDhub(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32MctrlSS_AVIO_PRIO_agVipDhub(r32) _BFGET_(r32, 7, 4) |
| #define SET32MctrlSS_AVIO_PRIO_agVipDhub(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16MctrlSS_AVIO_PRIO_agVipDhub(r16) _BFGET_(r16, 7, 4) |
| #define SET16MctrlSS_AVIO_PRIO_agVipDhub(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define w32MctrlSS_AVIO_PRIO {\ |
| UNSG32 uAVIO_PRIO_vppDhub : 4;\ |
| UNSG32 uAVIO_PRIO_agVipDhub : 4;\ |
| UNSG32 RSVDx4_b8 : 24;\ |
| } |
| union { UNSG32 u32MctrlSS_AVIO_PRIO; |
| struct w32MctrlSS_AVIO_PRIO; |
| }; |
| |
| #define GET32MctrlSS_ddrPhyLoopBackSrc_Control(r32) _BFGET_(r32, 0, 0) |
| #define SET32MctrlSS_ddrPhyLoopBackSrc_Control(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16MctrlSS_ddrPhyLoopBackSrc_Control(r16) _BFGET_(r16, 0, 0) |
| #define SET16MctrlSS_ddrPhyLoopBackSrc_Control(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32MctrlSS_ddrPhyLoopBackSrc {\ |
| UNSG32 uddrPhyLoopBackSrc_Control : 1;\ |
| UNSG32 RSVDx8_b1 : 31;\ |
| } |
| union { UNSG32 u32MctrlSS_ddrPhyLoopBackSrc; |
| struct w32MctrlSS_ddrPhyLoopBackSrc; |
| }; |
| |
| #define GET32MctrlSS_ddrPhyLoopBackConfig1_TST_MODE(r32) _BFGET_(r32, 0, 0) |
| #define SET32MctrlSS_ddrPhyLoopBackConfig1_TST_MODE(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16MctrlSS_ddrPhyLoopBackConfig1_TST_MODE(r16) _BFGET_(r16, 0, 0) |
| #define SET16MctrlSS_ddrPhyLoopBackConfig1_TST_MODE(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32MctrlSS_ddrPhyLoopBackConfig1_TST_START(r32) _BFGET_(r32, 1, 1) |
| #define SET32MctrlSS_ddrPhyLoopBackConfig1_TST_START(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16MctrlSS_ddrPhyLoopBackConfig1_TST_START(r16) _BFGET_(r16, 1, 1) |
| #define SET16MctrlSS_ddrPhyLoopBackConfig1_TST_START(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define w32MctrlSS_ddrPhyLoopBackConfig1 {\ |
| UNSG32 uddrPhyLoopBackConfig1_TST_MODE : 1;\ |
| UNSG32 uddrPhyLoopBackConfig1_TST_START : 1;\ |
| UNSG32 RSVDxC_b2 : 30;\ |
| } |
| union { UNSG32 u32MctrlSS_ddrPhyLoopBackConfig1; |
| struct w32MctrlSS_ddrPhyLoopBackConfig1; |
| }; |
| |
| #define GET32MctrlSS_ddrPhyLoopBackConfig2_CFG_DATA_DLY(r32) _BFGET_(r32, 4, 0) |
| #define SET32MctrlSS_ddrPhyLoopBackConfig2_CFG_DATA_DLY(r32,v) _BFSET_(r32, 4, 0,v) |
| #define GET16MctrlSS_ddrPhyLoopBackConfig2_CFG_DATA_DLY(r16) _BFGET_(r16, 4, 0) |
| #define SET16MctrlSS_ddrPhyLoopBackConfig2_CFG_DATA_DLY(r16,v) _BFSET_(r16, 4, 0,v) |
| |
| #define GET32MctrlSS_ddrPhyLoopBackConfig2_RSERVRED1(r32) _BFGET_(r32, 7, 5) |
| #define SET32MctrlSS_ddrPhyLoopBackConfig2_RSERVRED1(r32,v) _BFSET_(r32, 7, 5,v) |
| #define GET16MctrlSS_ddrPhyLoopBackConfig2_RSERVRED1(r16) _BFGET_(r16, 7, 5) |
| #define SET16MctrlSS_ddrPhyLoopBackConfig2_RSERVRED1(r16,v) _BFSET_(r16, 7, 5,v) |
| |
| #define GET32MctrlSS_ddrPhyLoopBackConfig2_CFG_ADC_DLY(r32) _BFGET_(r32,12, 8) |
| #define SET32MctrlSS_ddrPhyLoopBackConfig2_CFG_ADC_DLY(r32,v) _BFSET_(r32,12, 8,v) |
| #define GET16MctrlSS_ddrPhyLoopBackConfig2_CFG_ADC_DLY(r16) _BFGET_(r16,12, 8) |
| #define SET16MctrlSS_ddrPhyLoopBackConfig2_CFG_ADC_DLY(r16,v) _BFSET_(r16,12, 8,v) |
| |
| #define GET32MctrlSS_ddrPhyLoopBackConfig2_RSERVRED2(r32) _BFGET_(r32,14,13) |
| #define SET32MctrlSS_ddrPhyLoopBackConfig2_RSERVRED2(r32,v) _BFSET_(r32,14,13,v) |
| #define GET16MctrlSS_ddrPhyLoopBackConfig2_RSERVRED2(r16) _BFGET_(r16,14,13) |
| #define SET16MctrlSS_ddrPhyLoopBackConfig2_RSERVRED2(r16,v) _BFSET_(r16,14,13,v) |
| |
| #define GET32MctrlSS_ddrPhyLoopBackConfig2_SKIP_CMD_SUBPHY(r32) _BFGET_(r32,15,15) |
| #define SET32MctrlSS_ddrPhyLoopBackConfig2_SKIP_CMD_SUBPHY(r32,v) _BFSET_(r32,15,15,v) |
| #define GET16MctrlSS_ddrPhyLoopBackConfig2_SKIP_CMD_SUBPHY(r16) _BFGET_(r16,15,15) |
| #define SET16MctrlSS_ddrPhyLoopBackConfig2_SKIP_CMD_SUBPHY(r16,v) _BFSET_(r16,15,15,v) |
| |
| #define w32MctrlSS_ddrPhyLoopBackConfig2 {\ |
| UNSG32 uddrPhyLoopBackConfig2_CFG_DATA_DLY : 5;\ |
| UNSG32 uddrPhyLoopBackConfig2_RSERVRED1 : 3;\ |
| UNSG32 uddrPhyLoopBackConfig2_CFG_ADC_DLY : 5;\ |
| UNSG32 uddrPhyLoopBackConfig2_RSERVRED2 : 2;\ |
| UNSG32 uddrPhyLoopBackConfig2_SKIP_CMD_SUBPHY : 1;\ |
| UNSG32 RSVDx10_b16 : 16;\ |
| } |
| union { UNSG32 u32MctrlSS_ddrPhyLoopBackConfig2; |
| struct w32MctrlSS_ddrPhyLoopBackConfig2; |
| }; |
| |
| #define GET32MctrlSS_ddrPhyLoopBackConfig3_SEED(r32) _BFGET_(r32,31, 0) |
| #define SET32MctrlSS_ddrPhyLoopBackConfig3_SEED(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32MctrlSS_ddrPhyLoopBackConfig3 {\ |
| UNSG32 uddrPhyLoopBackConfig3_SEED : 32;\ |
| } |
| union { UNSG32 u32MctrlSS_ddrPhyLoopBackConfig3; |
| struct w32MctrlSS_ddrPhyLoopBackConfig3; |
| }; |
| |
| #define GET32MctrlSS_ddrPhyLoopBackStatus1_STATUS(r32) _BFGET_(r32,15, 0) |
| #define SET32MctrlSS_ddrPhyLoopBackStatus1_STATUS(r32,v) _BFSET_(r32,15, 0,v) |
| #define GET16MctrlSS_ddrPhyLoopBackStatus1_STATUS(r16) _BFGET_(r16,15, 0) |
| #define SET16MctrlSS_ddrPhyLoopBackStatus1_STATUS(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define GET32MctrlSS_ddrPhyLoopBackStatus1_RESERVED(r32) _BFGET_(r32,31,16) |
| #define SET32MctrlSS_ddrPhyLoopBackStatus1_RESERVED(r32,v) _BFSET_(r32,31,16,v) |
| #define GET16MctrlSS_ddrPhyLoopBackStatus1_RESERVED(r16) _BFGET_(r16,15, 0) |
| #define SET16MctrlSS_ddrPhyLoopBackStatus1_RESERVED(r16,v) _BFSET_(r16,15, 0,v) |
| |
| #define w32MctrlSS_ddrPhyLoopBackStatus1 {\ |
| UNSG32 uddrPhyLoopBackStatus1_STATUS : 16;\ |
| UNSG32 uddrPhyLoopBackStatus1_RESERVED : 16;\ |
| } |
| union { UNSG32 u32MctrlSS_ddrPhyLoopBackStatus1; |
| struct w32MctrlSS_ddrPhyLoopBackStatus1; |
| }; |
| |
| #define GET32MctrlSS_ddrPhyLoopBackStatus2_DONE(r32) _BFGET_(r32, 0, 0) |
| #define SET32MctrlSS_ddrPhyLoopBackStatus2_DONE(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16MctrlSS_ddrPhyLoopBackStatus2_DONE(r16) _BFGET_(r16, 0, 0) |
| #define SET16MctrlSS_ddrPhyLoopBackStatus2_DONE(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32MctrlSS_ddrPhyLoopBackStatus2_FAIL(r32) _BFGET_(r32, 1, 1) |
| #define SET32MctrlSS_ddrPhyLoopBackStatus2_FAIL(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16MctrlSS_ddrPhyLoopBackStatus2_FAIL(r16) _BFGET_(r16, 1, 1) |
| #define SET16MctrlSS_ddrPhyLoopBackStatus2_FAIL(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define w32MctrlSS_ddrPhyLoopBackStatus2 {\ |
| UNSG32 uddrPhyLoopBackStatus2_DONE : 1;\ |
| UNSG32 uddrPhyLoopBackStatus2_FAIL : 1;\ |
| UNSG32 RSVDx1C_b2 : 30;\ |
| } |
| union { UNSG32 u32MctrlSS_ddrPhyLoopBackStatus2; |
| struct w32MctrlSS_ddrPhyLoopBackStatus2; |
| }; |
| |
| #define GET32MctrlSS_mc_phy_pd_ctrl_normal_mode_ch0(r32) _BFGET_(r32, 0, 0) |
| #define SET32MctrlSS_mc_phy_pd_ctrl_normal_mode_ch0(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16MctrlSS_mc_phy_pd_ctrl_normal_mode_ch0(r16) _BFGET_(r16, 0, 0) |
| #define SET16MctrlSS_mc_phy_pd_ctrl_normal_mode_ch0(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32MctrlSS_mc_phy_pd_ctrl_pd_en_ch0(r32) _BFGET_(r32, 1, 1) |
| #define SET32MctrlSS_mc_phy_pd_ctrl_pd_en_ch0(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16MctrlSS_mc_phy_pd_ctrl_pd_en_ch0(r16) _BFGET_(r16, 1, 1) |
| #define SET16MctrlSS_mc_phy_pd_ctrl_pd_en_ch0(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define w32MctrlSS_mc_phy_pd_ctrl {\ |
| UNSG32 umc_phy_pd_ctrl_normal_mode_ch0 : 1;\ |
| UNSG32 umc_phy_pd_ctrl_pd_en_ch0 : 1;\ |
| UNSG32 RSVDx20_b2 : 30;\ |
| } |
| union { UNSG32 u32MctrlSS_mc_phy_pd_ctrl; |
| struct w32MctrlSS_mc_phy_pd_ctrl; |
| }; |
| |
| #define GET32MctrlSS_mc_mstr0_qos_awqos(r32) _BFGET_(r32, 3, 0) |
| #define SET32MctrlSS_mc_mstr0_qos_awqos(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16MctrlSS_mc_mstr0_qos_awqos(r16) _BFGET_(r16, 3, 0) |
| #define SET16MctrlSS_mc_mstr0_qos_awqos(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32MctrlSS_mc_mstr0_qos_arqos(r32) _BFGET_(r32, 7, 4) |
| #define SET32MctrlSS_mc_mstr0_qos_arqos(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16MctrlSS_mc_mstr0_qos_arqos(r16) _BFGET_(r16, 7, 4) |
| #define SET16MctrlSS_mc_mstr0_qos_arqos(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define w32MctrlSS_mc_mstr0_qos {\ |
| UNSG32 umc_mstr0_qos_awqos : 4;\ |
| UNSG32 umc_mstr0_qos_arqos : 4;\ |
| UNSG32 RSVDx24_b8 : 24;\ |
| } |
| union { UNSG32 u32MctrlSS_mc_mstr0_qos; |
| struct w32MctrlSS_mc_mstr0_qos; |
| }; |
| |
| #define GET32MctrlSS_mc_mstr1_qos_awqos(r32) _BFGET_(r32, 3, 0) |
| #define SET32MctrlSS_mc_mstr1_qos_awqos(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16MctrlSS_mc_mstr1_qos_awqos(r16) _BFGET_(r16, 3, 0) |
| #define SET16MctrlSS_mc_mstr1_qos_awqos(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32MctrlSS_mc_mstr1_qos_arqos(r32) _BFGET_(r32, 7, 4) |
| #define SET32MctrlSS_mc_mstr1_qos_arqos(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16MctrlSS_mc_mstr1_qos_arqos(r16) _BFGET_(r16, 7, 4) |
| #define SET16MctrlSS_mc_mstr1_qos_arqos(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define w32MctrlSS_mc_mstr1_qos {\ |
| UNSG32 umc_mstr1_qos_awqos : 4;\ |
| UNSG32 umc_mstr1_qos_arqos : 4;\ |
| UNSG32 RSVDx28_b8 : 24;\ |
| } |
| union { UNSG32 u32MctrlSS_mc_mstr1_qos; |
| struct w32MctrlSS_mc_mstr1_qos; |
| }; |
| |
| #define GET32MctrlSS_mc_mstr2_qos_awqos(r32) _BFGET_(r32, 3, 0) |
| #define SET32MctrlSS_mc_mstr2_qos_awqos(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16MctrlSS_mc_mstr2_qos_awqos(r16) _BFGET_(r16, 3, 0) |
| #define SET16MctrlSS_mc_mstr2_qos_awqos(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32MctrlSS_mc_mstr2_qos_arqos(r32) _BFGET_(r32, 7, 4) |
| #define SET32MctrlSS_mc_mstr2_qos_arqos(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16MctrlSS_mc_mstr2_qos_arqos(r16) _BFGET_(r16, 7, 4) |
| #define SET16MctrlSS_mc_mstr2_qos_arqos(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define w32MctrlSS_mc_mstr2_qos {\ |
| UNSG32 umc_mstr2_qos_awqos : 4;\ |
| UNSG32 umc_mstr2_qos_arqos : 4;\ |
| UNSG32 RSVDx2C_b8 : 24;\ |
| } |
| union { UNSG32 u32MctrlSS_mc_mstr2_qos; |
| struct w32MctrlSS_mc_mstr2_qos; |
| }; |
| |
| #define GET32MctrlSS_mc_mstr3_qos_awqos(r32) _BFGET_(r32, 3, 0) |
| #define SET32MctrlSS_mc_mstr3_qos_awqos(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16MctrlSS_mc_mstr3_qos_awqos(r16) _BFGET_(r16, 3, 0) |
| #define SET16MctrlSS_mc_mstr3_qos_awqos(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32MctrlSS_mc_mstr3_qos_arqos(r32) _BFGET_(r32, 7, 4) |
| #define SET32MctrlSS_mc_mstr3_qos_arqos(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16MctrlSS_mc_mstr3_qos_arqos(r16) _BFGET_(r16, 7, 4) |
| #define SET16MctrlSS_mc_mstr3_qos_arqos(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define w32MctrlSS_mc_mstr3_qos {\ |
| UNSG32 umc_mstr3_qos_awqos : 4;\ |
| UNSG32 umc_mstr3_qos_arqos : 4;\ |
| UNSG32 RSVDx30_b8 : 24;\ |
| } |
| union { UNSG32 u32MctrlSS_mc_mstr3_qos; |
| struct w32MctrlSS_mc_mstr3_qos; |
| }; |
| |
| #define GET32MctrlSS_mc_mstr4_qos_awqos(r32) _BFGET_(r32, 3, 0) |
| #define SET32MctrlSS_mc_mstr4_qos_awqos(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16MctrlSS_mc_mstr4_qos_awqos(r16) _BFGET_(r16, 3, 0) |
| #define SET16MctrlSS_mc_mstr4_qos_awqos(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32MctrlSS_mc_mstr4_qos_arqos(r32) _BFGET_(r32, 7, 4) |
| #define SET32MctrlSS_mc_mstr4_qos_arqos(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16MctrlSS_mc_mstr4_qos_arqos(r16) _BFGET_(r16, 7, 4) |
| #define SET16MctrlSS_mc_mstr4_qos_arqos(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define w32MctrlSS_mc_mstr4_qos {\ |
| UNSG32 umc_mstr4_qos_awqos : 4;\ |
| UNSG32 umc_mstr4_qos_arqos : 4;\ |
| UNSG32 RSVDx34_b8 : 24;\ |
| } |
| union { UNSG32 u32MctrlSS_mc_mstr4_qos; |
| struct w32MctrlSS_mc_mstr4_qos; |
| }; |
| |
| #define GET32MctrlSS_mc_mstr5_qos_awqos(r32) _BFGET_(r32, 3, 0) |
| #define SET32MctrlSS_mc_mstr5_qos_awqos(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16MctrlSS_mc_mstr5_qos_awqos(r16) _BFGET_(r16, 3, 0) |
| #define SET16MctrlSS_mc_mstr5_qos_awqos(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32MctrlSS_mc_mstr5_qos_arqos(r32) _BFGET_(r32, 7, 4) |
| #define SET32MctrlSS_mc_mstr5_qos_arqos(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16MctrlSS_mc_mstr5_qos_arqos(r16) _BFGET_(r16, 7, 4) |
| #define SET16MctrlSS_mc_mstr5_qos_arqos(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define w32MctrlSS_mc_mstr5_qos {\ |
| UNSG32 umc_mstr5_qos_awqos : 4;\ |
| UNSG32 umc_mstr5_qos_arqos : 4;\ |
| UNSG32 RSVDx38_b8 : 24;\ |
| } |
| union { UNSG32 u32MctrlSS_mc_mstr5_qos; |
| struct w32MctrlSS_mc_mstr5_qos; |
| }; |
| |
| #define GET32MctrlSS_mc_mstr6_qos_awqos(r32) _BFGET_(r32, 3, 0) |
| #define SET32MctrlSS_mc_mstr6_qos_awqos(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16MctrlSS_mc_mstr6_qos_awqos(r16) _BFGET_(r16, 3, 0) |
| #define SET16MctrlSS_mc_mstr6_qos_awqos(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32MctrlSS_mc_mstr6_qos_arqos(r32) _BFGET_(r32, 7, 4) |
| #define SET32MctrlSS_mc_mstr6_qos_arqos(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16MctrlSS_mc_mstr6_qos_arqos(r16) _BFGET_(r16, 7, 4) |
| #define SET16MctrlSS_mc_mstr6_qos_arqos(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define w32MctrlSS_mc_mstr6_qos {\ |
| UNSG32 umc_mstr6_qos_awqos : 4;\ |
| UNSG32 umc_mstr6_qos_arqos : 4;\ |
| UNSG32 RSVDx3C_b8 : 24;\ |
| } |
| union { UNSG32 u32MctrlSS_mc_mstr6_qos; |
| struct w32MctrlSS_mc_mstr6_qos; |
| }; |
| |
| #define GET32MctrlSS_mc_mstr7_qos_awqos(r32) _BFGET_(r32, 3, 0) |
| #define SET32MctrlSS_mc_mstr7_qos_awqos(r32,v) _BFSET_(r32, 3, 0,v) |
| #define GET16MctrlSS_mc_mstr7_qos_awqos(r16) _BFGET_(r16, 3, 0) |
| #define SET16MctrlSS_mc_mstr7_qos_awqos(r16,v) _BFSET_(r16, 3, 0,v) |
| |
| #define GET32MctrlSS_mc_mstr7_qos_arqos(r32) _BFGET_(r32, 7, 4) |
| #define SET32MctrlSS_mc_mstr7_qos_arqos(r32,v) _BFSET_(r32, 7, 4,v) |
| #define GET16MctrlSS_mc_mstr7_qos_arqos(r16) _BFGET_(r16, 7, 4) |
| #define SET16MctrlSS_mc_mstr7_qos_arqos(r16,v) _BFSET_(r16, 7, 4,v) |
| |
| #define w32MctrlSS_mc_mstr7_qos {\ |
| UNSG32 umc_mstr7_qos_awqos : 4;\ |
| UNSG32 umc_mstr7_qos_arqos : 4;\ |
| UNSG32 RSVDx40_b8 : 24;\ |
| } |
| union { UNSG32 u32MctrlSS_mc_mstr7_qos; |
| struct w32MctrlSS_mc_mstr7_qos; |
| }; |
| |
| #define GET32MctrlSS_mc_hw_phy_dll_update_req_en(r32) _BFGET_(r32, 0, 0) |
| #define SET32MctrlSS_mc_hw_phy_dll_update_req_en(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16MctrlSS_mc_hw_phy_dll_update_req_en(r16) _BFGET_(r16, 0, 0) |
| #define SET16MctrlSS_mc_hw_phy_dll_update_req_en(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define w32MctrlSS_mc_hw_phy_dll_update_req {\ |
| UNSG32 umc_hw_phy_dll_update_req_en : 1;\ |
| UNSG32 RSVDx44_b1 : 31;\ |
| } |
| union { UNSG32 u32MctrlSS_mc_hw_phy_dll_update_req; |
| struct w32MctrlSS_mc_hw_phy_dll_update_req; |
| }; |
| |
| #define GET32MctrlSS_mc_hw_dfc_ctrl_reg_table_req(r32) _BFGET_(r32, 0, 0) |
| #define SET32MctrlSS_mc_hw_dfc_ctrl_reg_table_req(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16MctrlSS_mc_hw_dfc_ctrl_reg_table_req(r16) _BFGET_(r16, 0, 0) |
| #define SET16MctrlSS_mc_hw_dfc_ctrl_reg_table_req(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32MctrlSS_mc_hw_dfc_ctrl_reg_table_type(r32) _BFGET_(r32, 5, 1) |
| #define SET32MctrlSS_mc_hw_dfc_ctrl_reg_table_type(r32,v) _BFSET_(r32, 5, 1,v) |
| #define GET16MctrlSS_mc_hw_dfc_ctrl_reg_table_type(r16) _BFGET_(r16, 5, 1) |
| #define SET16MctrlSS_mc_hw_dfc_ctrl_reg_table_type(r16,v) _BFSET_(r16, 5, 1,v) |
| |
| #define GET32MctrlSS_mc_hw_dfc_ctrl_reg_table_wait_ack(r32) _BFGET_(r32, 6, 6) |
| #define SET32MctrlSS_mc_hw_dfc_ctrl_reg_table_wait_ack(r32,v) _BFSET_(r32, 6, 6,v) |
| #define GET16MctrlSS_mc_hw_dfc_ctrl_reg_table_wait_ack(r16) _BFGET_(r16, 6, 6) |
| #define SET16MctrlSS_mc_hw_dfc_ctrl_reg_table_wait_ack(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32MctrlSS_mc_hw_dfc_ctrl_sleep_req(r32) _BFGET_(r32, 7, 7) |
| #define SET32MctrlSS_mc_hw_dfc_ctrl_sleep_req(r32,v) _BFSET_(r32, 7, 7,v) |
| #define GET16MctrlSS_mc_hw_dfc_ctrl_sleep_req(r16) _BFGET_(r16, 7, 7) |
| #define SET16MctrlSS_mc_hw_dfc_ctrl_sleep_req(r16,v) _BFSET_(r16, 7, 7,v) |
| |
| #define GET32MctrlSS_mc_hw_dfc_ctrl_sleep_type(r32) _BFGET_(r32,10, 8) |
| #define SET32MctrlSS_mc_hw_dfc_ctrl_sleep_type(r32,v) _BFSET_(r32,10, 8,v) |
| #define GET16MctrlSS_mc_hw_dfc_ctrl_sleep_type(r16) _BFGET_(r16,10, 8) |
| #define SET16MctrlSS_mc_hw_dfc_ctrl_sleep_type(r16,v) _BFSET_(r16,10, 8,v) |
| |
| #define w32MctrlSS_mc_hw_dfc_ctrl {\ |
| UNSG32 umc_hw_dfc_ctrl_reg_table_req : 1;\ |
| UNSG32 umc_hw_dfc_ctrl_reg_table_type : 5;\ |
| UNSG32 umc_hw_dfc_ctrl_reg_table_wait_ack : 1;\ |
| UNSG32 umc_hw_dfc_ctrl_sleep_req : 1;\ |
| UNSG32 umc_hw_dfc_ctrl_sleep_type : 3;\ |
| UNSG32 RSVDx48_b11 : 21;\ |
| } |
| union { UNSG32 u32MctrlSS_mc_hw_dfc_ctrl; |
| struct w32MctrlSS_mc_hw_dfc_ctrl; |
| }; |
| |
| #define GET32MctrlSS_mc_hw_dfc_sts_reg_table_req_ack(r32) _BFGET_(r32, 0, 0) |
| #define SET32MctrlSS_mc_hw_dfc_sts_reg_table_req_ack(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16MctrlSS_mc_hw_dfc_sts_reg_table_req_ack(r16) _BFGET_(r16, 0, 0) |
| #define SET16MctrlSS_mc_hw_dfc_sts_reg_table_req_ack(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32MctrlSS_mc_hw_dfc_sts_reg_table_wait_req(r32) _BFGET_(r32, 1, 1) |
| #define SET32MctrlSS_mc_hw_dfc_sts_reg_table_wait_req(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16MctrlSS_mc_hw_dfc_sts_reg_table_wait_req(r16) _BFGET_(r16, 1, 1) |
| #define SET16MctrlSS_mc_hw_dfc_sts_reg_table_wait_req(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32MctrlSS_mc_hw_dfc_sts_sleep_req_ack(r32) _BFGET_(r32, 2, 2) |
| #define SET32MctrlSS_mc_hw_dfc_sts_sleep_req_ack(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16MctrlSS_mc_hw_dfc_sts_sleep_req_ack(r16) _BFGET_(r16, 2, 2) |
| #define SET16MctrlSS_mc_hw_dfc_sts_sleep_req_ack(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define w32MctrlSS_mc_hw_dfc_sts {\ |
| UNSG32 umc_hw_dfc_sts_reg_table_req_ack : 1;\ |
| UNSG32 umc_hw_dfc_sts_reg_table_wait_req : 1;\ |
| UNSG32 umc_hw_dfc_sts_sleep_req_ack : 1;\ |
| UNSG32 RSVDx4C_b3 : 29;\ |
| } |
| union { UNSG32 u32MctrlSS_mc_hw_dfc_sts; |
| struct w32MctrlSS_mc_hw_dfc_sts; |
| }; |
| |
| SIE_pll ie_memPll; |
| |
| #define GET32MctrlSS_RWTC_31to0_value(r32) _BFGET_(r32,31, 0) |
| #define SET32MctrlSS_RWTC_31to0_value(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32MctrlSS_RWTC_31to0 {\ |
| UNSG32 uRWTC_31to0_value : 32;\ |
| } |
| union { UNSG32 u32MctrlSS_RWTC_31to0; |
| struct w32MctrlSS_RWTC_31to0; |
| }; |
| |
| #define GET32MctrlSS_RWTC_57to32_value(r32) _BFGET_(r32,25, 0) |
| #define SET32MctrlSS_RWTC_57to32_value(r32,v) _BFSET_(r32,25, 0,v) |
| |
| #define w32MctrlSS_RWTC_57to32 {\ |
| UNSG32 uRWTC_57to32_value : 26;\ |
| UNSG32 RSVDx70_b26 : 6;\ |
| } |
| union { UNSG32 u32MctrlSS_RWTC_57to32; |
| struct w32MctrlSS_RWTC_57to32; |
| }; |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_0_PU(r32) _BFGET_(r32, 0, 0) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_0_PU(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_0_PU(r16) _BFGET_(r16, 0, 0) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_0_PU(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_0_LP(r32) _BFGET_(r32, 1, 1) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_0_LP(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_0_LP(r16) _BFGET_(r16, 1, 1) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_0_LP(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_0_BYPASS(r32) _BFGET_(r32, 2, 2) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_0_BYPASS(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_0_BYPASS(r16) _BFGET_(r16, 2, 2) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_0_BYPASS(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_0_VSEL(r32) _BFGET_(r32, 5, 3) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_0_VSEL(r32,v) _BFSET_(r32, 5, 3,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_0_VSEL(r16) _BFGET_(r16, 5, 3) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_0_VSEL(r16,v) _BFSET_(r16, 5, 3,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_0_TSTMON_EN(r32) _BFGET_(r32, 6, 6) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_0_TSTMON_EN(r32,v) _BFSET_(r32, 6, 6,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_0_TSTMON_EN(r16) _BFGET_(r16, 6, 6) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_0_TSTMON_EN(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_0_TESTMON(r32) _BFGET_(r32, 9, 7) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_0_TESTMON(r32,v) _BFSET_(r32, 9, 7,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_0_TESTMON(r16) _BFGET_(r16, 9, 7) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_0_TESTMON(r16,v) _BFSET_(r16, 9, 7,v) |
| |
| #define w32MctrlSS_DDRCLK_VREG_CTRL_0 {\ |
| UNSG32 uDDRCLK_VREG_CTRL_0_PU : 1;\ |
| UNSG32 uDDRCLK_VREG_CTRL_0_LP : 1;\ |
| UNSG32 uDDRCLK_VREG_CTRL_0_BYPASS : 1;\ |
| UNSG32 uDDRCLK_VREG_CTRL_0_VSEL : 3;\ |
| UNSG32 uDDRCLK_VREG_CTRL_0_TSTMON_EN : 1;\ |
| UNSG32 uDDRCLK_VREG_CTRL_0_TESTMON : 3;\ |
| UNSG32 RSVDx74_b10 : 22;\ |
| } |
| union { UNSG32 u32MctrlSS_DDRCLK_VREG_CTRL_0; |
| struct w32MctrlSS_DDRCLK_VREG_CTRL_0; |
| }; |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_1_PU(r32) _BFGET_(r32, 0, 0) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_1_PU(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_1_PU(r16) _BFGET_(r16, 0, 0) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_1_PU(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_1_LP(r32) _BFGET_(r32, 1, 1) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_1_LP(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_1_LP(r16) _BFGET_(r16, 1, 1) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_1_LP(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_1_BYPASS(r32) _BFGET_(r32, 2, 2) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_1_BYPASS(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_1_BYPASS(r16) _BFGET_(r16, 2, 2) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_1_BYPASS(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_1_VSEL(r32) _BFGET_(r32, 5, 3) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_1_VSEL(r32,v) _BFSET_(r32, 5, 3,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_1_VSEL(r16) _BFGET_(r16, 5, 3) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_1_VSEL(r16,v) _BFSET_(r16, 5, 3,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_1_TSTMON_EN(r32) _BFGET_(r32, 6, 6) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_1_TSTMON_EN(r32,v) _BFSET_(r32, 6, 6,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_1_TSTMON_EN(r16) _BFGET_(r16, 6, 6) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_1_TSTMON_EN(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_1_TESTMON(r32) _BFGET_(r32, 9, 7) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_1_TESTMON(r32,v) _BFSET_(r32, 9, 7,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_1_TESTMON(r16) _BFGET_(r16, 9, 7) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_1_TESTMON(r16,v) _BFSET_(r16, 9, 7,v) |
| |
| #define w32MctrlSS_DDRCLK_VREG_CTRL_1 {\ |
| UNSG32 uDDRCLK_VREG_CTRL_1_PU : 1;\ |
| UNSG32 uDDRCLK_VREG_CTRL_1_LP : 1;\ |
| UNSG32 uDDRCLK_VREG_CTRL_1_BYPASS : 1;\ |
| UNSG32 uDDRCLK_VREG_CTRL_1_VSEL : 3;\ |
| UNSG32 uDDRCLK_VREG_CTRL_1_TSTMON_EN : 1;\ |
| UNSG32 uDDRCLK_VREG_CTRL_1_TESTMON : 3;\ |
| UNSG32 RSVDx78_b10 : 22;\ |
| } |
| union { UNSG32 u32MctrlSS_DDRCLK_VREG_CTRL_1; |
| struct w32MctrlSS_DDRCLK_VREG_CTRL_1; |
| }; |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_2_PU(r32) _BFGET_(r32, 0, 0) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_2_PU(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_2_PU(r16) _BFGET_(r16, 0, 0) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_2_PU(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_2_LP(r32) _BFGET_(r32, 1, 1) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_2_LP(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_2_LP(r16) _BFGET_(r16, 1, 1) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_2_LP(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_2_BYPASS(r32) _BFGET_(r32, 2, 2) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_2_BYPASS(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_2_BYPASS(r16) _BFGET_(r16, 2, 2) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_2_BYPASS(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_2_VSEL(r32) _BFGET_(r32, 5, 3) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_2_VSEL(r32,v) _BFSET_(r32, 5, 3,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_2_VSEL(r16) _BFGET_(r16, 5, 3) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_2_VSEL(r16,v) _BFSET_(r16, 5, 3,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_2_TSTMON_EN(r32) _BFGET_(r32, 6, 6) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_2_TSTMON_EN(r32,v) _BFSET_(r32, 6, 6,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_2_TSTMON_EN(r16) _BFGET_(r16, 6, 6) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_2_TSTMON_EN(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_2_TESTMON(r32) _BFGET_(r32, 9, 7) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_2_TESTMON(r32,v) _BFSET_(r32, 9, 7,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_2_TESTMON(r16) _BFGET_(r16, 9, 7) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_2_TESTMON(r16,v) _BFSET_(r16, 9, 7,v) |
| |
| #define w32MctrlSS_DDRCLK_VREG_CTRL_2 {\ |
| UNSG32 uDDRCLK_VREG_CTRL_2_PU : 1;\ |
| UNSG32 uDDRCLK_VREG_CTRL_2_LP : 1;\ |
| UNSG32 uDDRCLK_VREG_CTRL_2_BYPASS : 1;\ |
| UNSG32 uDDRCLK_VREG_CTRL_2_VSEL : 3;\ |
| UNSG32 uDDRCLK_VREG_CTRL_2_TSTMON_EN : 1;\ |
| UNSG32 uDDRCLK_VREG_CTRL_2_TESTMON : 3;\ |
| UNSG32 RSVDx7C_b10 : 22;\ |
| } |
| union { UNSG32 u32MctrlSS_DDRCLK_VREG_CTRL_2; |
| struct w32MctrlSS_DDRCLK_VREG_CTRL_2; |
| }; |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_3_PU(r32) _BFGET_(r32, 0, 0) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_3_PU(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_3_PU(r16) _BFGET_(r16, 0, 0) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_3_PU(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_3_LP(r32) _BFGET_(r32, 1, 1) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_3_LP(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_3_LP(r16) _BFGET_(r16, 1, 1) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_3_LP(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_3_BYPASS(r32) _BFGET_(r32, 2, 2) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_3_BYPASS(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_3_BYPASS(r16) _BFGET_(r16, 2, 2) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_3_BYPASS(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_3_VSEL(r32) _BFGET_(r32, 5, 3) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_3_VSEL(r32,v) _BFSET_(r32, 5, 3,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_3_VSEL(r16) _BFGET_(r16, 5, 3) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_3_VSEL(r16,v) _BFSET_(r16, 5, 3,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_3_TSTMON_EN(r32) _BFGET_(r32, 6, 6) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_3_TSTMON_EN(r32,v) _BFSET_(r32, 6, 6,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_3_TSTMON_EN(r16) _BFGET_(r16, 6, 6) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_3_TSTMON_EN(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_3_TESTMON(r32) _BFGET_(r32, 9, 7) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_3_TESTMON(r32,v) _BFSET_(r32, 9, 7,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_3_TESTMON(r16) _BFGET_(r16, 9, 7) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_3_TESTMON(r16,v) _BFSET_(r16, 9, 7,v) |
| |
| #define w32MctrlSS_DDRCLK_VREG_CTRL_3 {\ |
| UNSG32 uDDRCLK_VREG_CTRL_3_PU : 1;\ |
| UNSG32 uDDRCLK_VREG_CTRL_3_LP : 1;\ |
| UNSG32 uDDRCLK_VREG_CTRL_3_BYPASS : 1;\ |
| UNSG32 uDDRCLK_VREG_CTRL_3_VSEL : 3;\ |
| UNSG32 uDDRCLK_VREG_CTRL_3_TSTMON_EN : 1;\ |
| UNSG32 uDDRCLK_VREG_CTRL_3_TESTMON : 3;\ |
| UNSG32 RSVDx80_b10 : 22;\ |
| } |
| union { UNSG32 u32MctrlSS_DDRCLK_VREG_CTRL_3; |
| struct w32MctrlSS_DDRCLK_VREG_CTRL_3; |
| }; |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_4_PU(r32) _BFGET_(r32, 0, 0) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_4_PU(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_4_PU(r16) _BFGET_(r16, 0, 0) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_4_PU(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_4_LP(r32) _BFGET_(r32, 1, 1) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_4_LP(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_4_LP(r16) _BFGET_(r16, 1, 1) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_4_LP(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_4_BYPASS(r32) _BFGET_(r32, 2, 2) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_4_BYPASS(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_4_BYPASS(r16) _BFGET_(r16, 2, 2) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_4_BYPASS(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_4_VSEL(r32) _BFGET_(r32, 5, 3) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_4_VSEL(r32,v) _BFSET_(r32, 5, 3,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_4_VSEL(r16) _BFGET_(r16, 5, 3) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_4_VSEL(r16,v) _BFSET_(r16, 5, 3,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_4_TSTMON_EN(r32) _BFGET_(r32, 6, 6) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_4_TSTMON_EN(r32,v) _BFSET_(r32, 6, 6,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_4_TSTMON_EN(r16) _BFGET_(r16, 6, 6) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_4_TSTMON_EN(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_4_TESTMON(r32) _BFGET_(r32, 9, 7) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_4_TESTMON(r32,v) _BFSET_(r32, 9, 7,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_4_TESTMON(r16) _BFGET_(r16, 9, 7) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_4_TESTMON(r16,v) _BFSET_(r16, 9, 7,v) |
| |
| #define w32MctrlSS_DDRCLK_VREG_CTRL_4 {\ |
| UNSG32 uDDRCLK_VREG_CTRL_4_PU : 1;\ |
| UNSG32 uDDRCLK_VREG_CTRL_4_LP : 1;\ |
| UNSG32 uDDRCLK_VREG_CTRL_4_BYPASS : 1;\ |
| UNSG32 uDDRCLK_VREG_CTRL_4_VSEL : 3;\ |
| UNSG32 uDDRCLK_VREG_CTRL_4_TSTMON_EN : 1;\ |
| UNSG32 uDDRCLK_VREG_CTRL_4_TESTMON : 3;\ |
| UNSG32 RSVDx84_b10 : 22;\ |
| } |
| union { UNSG32 u32MctrlSS_DDRCLK_VREG_CTRL_4; |
| struct w32MctrlSS_DDRCLK_VREG_CTRL_4; |
| }; |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_5_PU(r32) _BFGET_(r32, 0, 0) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_5_PU(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_5_PU(r16) _BFGET_(r16, 0, 0) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_5_PU(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_5_LP(r32) _BFGET_(r32, 1, 1) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_5_LP(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_5_LP(r16) _BFGET_(r16, 1, 1) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_5_LP(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_5_BYPASS(r32) _BFGET_(r32, 2, 2) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_5_BYPASS(r32,v) _BFSET_(r32, 2, 2,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_5_BYPASS(r16) _BFGET_(r16, 2, 2) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_5_BYPASS(r16,v) _BFSET_(r16, 2, 2,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_5_VSEL(r32) _BFGET_(r32, 5, 3) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_5_VSEL(r32,v) _BFSET_(r32, 5, 3,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_5_VSEL(r16) _BFGET_(r16, 5, 3) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_5_VSEL(r16,v) _BFSET_(r16, 5, 3,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_5_TSTMON_EN(r32) _BFGET_(r32, 6, 6) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_5_TSTMON_EN(r32,v) _BFSET_(r32, 6, 6,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_5_TSTMON_EN(r16) _BFGET_(r16, 6, 6) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_5_TSTMON_EN(r16,v) _BFSET_(r16, 6, 6,v) |
| |
| #define GET32MctrlSS_DDRCLK_VREG_CTRL_5_TESTMON(r32) _BFGET_(r32, 9, 7) |
| #define SET32MctrlSS_DDRCLK_VREG_CTRL_5_TESTMON(r32,v) _BFSET_(r32, 9, 7,v) |
| #define GET16MctrlSS_DDRCLK_VREG_CTRL_5_TESTMON(r16) _BFGET_(r16, 9, 7) |
| #define SET16MctrlSS_DDRCLK_VREG_CTRL_5_TESTMON(r16,v) _BFSET_(r16, 9, 7,v) |
| |
| #define w32MctrlSS_DDRCLK_VREG_CTRL_5 {\ |
| UNSG32 uDDRCLK_VREG_CTRL_5_PU : 1;\ |
| UNSG32 uDDRCLK_VREG_CTRL_5_LP : 1;\ |
| UNSG32 uDDRCLK_VREG_CTRL_5_BYPASS : 1;\ |
| UNSG32 uDDRCLK_VREG_CTRL_5_VSEL : 3;\ |
| UNSG32 uDDRCLK_VREG_CTRL_5_TSTMON_EN : 1;\ |
| UNSG32 uDDRCLK_VREG_CTRL_5_TESTMON : 3;\ |
| UNSG32 RSVDx88_b10 : 22;\ |
| } |
| union { UNSG32 u32MctrlSS_DDRCLK_VREG_CTRL_5; |
| struct w32MctrlSS_DDRCLK_VREG_CTRL_5; |
| }; |
| |
| SIE_AxiPCnt ie_GFX3D_PC; |
| |
| UNSG8 RSVDxA8 [32600]; |
| |
| #define GET32MctrlSS_DDRScramCtrl_Secure_Key(r32) _BFGET_(r32, 0, 0) |
| #define SET32MctrlSS_DDRScramCtrl_Secure_Key(r32,v) _BFSET_(r32, 0, 0,v) |
| #define GET16MctrlSS_DDRScramCtrl_Secure_Key(r16) _BFGET_(r16, 0, 0) |
| #define SET16MctrlSS_DDRScramCtrl_Secure_Key(r16,v) _BFSET_(r16, 0, 0,v) |
| |
| #define GET32MctrlSS_DDRScramCtrl_En(r32) _BFGET_(r32, 1, 1) |
| #define SET32MctrlSS_DDRScramCtrl_En(r32,v) _BFSET_(r32, 1, 1,v) |
| #define GET16MctrlSS_DDRScramCtrl_En(r16) _BFGET_(r16, 1, 1) |
| #define SET16MctrlSS_DDRScramCtrl_En(r16,v) _BFSET_(r16, 1, 1,v) |
| |
| #define w32MctrlSS_DDRScramCtrl {\ |
| UNSG32 uDDRScramCtrl_Secure_Key : 1;\ |
| UNSG32 uDDRScramCtrl_En : 1;\ |
| UNSG32 RSVDx8000_b2 : 30;\ |
| } |
| union { UNSG32 u32MctrlSS_DDRScramCtrl; |
| struct w32MctrlSS_DDRScramCtrl; |
| }; |
| #define GET32MctrlSS_DDRScramCtrl_Key0_word0(r32) _BFGET_(r32,31, 0) |
| #define SET32MctrlSS_DDRScramCtrl_Key0_word0(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32MctrlSS_DDRScramCtrl1 {\ |
| UNSG32 uDDRScramCtrl_Key0_word0 : 32;\ |
| } |
| union { UNSG32 u32MctrlSS_DDRScramCtrl1; |
| struct w32MctrlSS_DDRScramCtrl1; |
| }; |
| #define GET32MctrlSS_DDRScramCtrl_Key0_word1(r32) _BFGET_(r32,31, 0) |
| #define SET32MctrlSS_DDRScramCtrl_Key0_word1(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32MctrlSS_DDRScramCtrl2 {\ |
| UNSG32 uDDRScramCtrl_Key0_word1 : 32;\ |
| } |
| union { UNSG32 u32MctrlSS_DDRScramCtrl2; |
| struct w32MctrlSS_DDRScramCtrl2; |
| }; |
| #define GET32MctrlSS_DDRScramCtrl_Key0_word2(r32) _BFGET_(r32,31, 0) |
| #define SET32MctrlSS_DDRScramCtrl_Key0_word2(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32MctrlSS_DDRScramCtrl3 {\ |
| UNSG32 uDDRScramCtrl_Key0_word2 : 32;\ |
| } |
| union { UNSG32 u32MctrlSS_DDRScramCtrl3; |
| struct w32MctrlSS_DDRScramCtrl3; |
| }; |
| #define GET32MctrlSS_DDRScramCtrl_Key0_word3(r32) _BFGET_(r32,31, 0) |
| #define SET32MctrlSS_DDRScramCtrl_Key0_word3(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32MctrlSS_DDRScramCtrl4 {\ |
| UNSG32 uDDRScramCtrl_Key0_word3 : 32;\ |
| } |
| union { UNSG32 u32MctrlSS_DDRScramCtrl4; |
| struct w32MctrlSS_DDRScramCtrl4; |
| }; |
| #define GET32MctrlSS_DDRScramCtrl_Key0_addr(r32) _BFGET_(r32,31, 0) |
| #define SET32MctrlSS_DDRScramCtrl_Key0_addr(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32MctrlSS_DDRScramCtrl5 {\ |
| UNSG32 uDDRScramCtrl_Key0_addr : 32;\ |
| } |
| union { UNSG32 u32MctrlSS_DDRScramCtrl5; |
| struct w32MctrlSS_DDRScramCtrl5; |
| }; |
| #define GET32MctrlSS_DDRScramCtrl_Key0_mask(r32) _BFGET_(r32,31, 0) |
| #define SET32MctrlSS_DDRScramCtrl_Key0_mask(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32MctrlSS_DDRScramCtrl6 {\ |
| UNSG32 uDDRScramCtrl_Key0_mask : 32;\ |
| } |
| union { UNSG32 u32MctrlSS_DDRScramCtrl6; |
| struct w32MctrlSS_DDRScramCtrl6; |
| }; |
| #define GET32MctrlSS_DDRScramCtrl_Key1_word0(r32) _BFGET_(r32,31, 0) |
| #define SET32MctrlSS_DDRScramCtrl_Key1_word0(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32MctrlSS_DDRScramCtrl7 {\ |
| UNSG32 uDDRScramCtrl_Key1_word0 : 32;\ |
| } |
| union { UNSG32 u32MctrlSS_DDRScramCtrl7; |
| struct w32MctrlSS_DDRScramCtrl7; |
| }; |
| #define GET32MctrlSS_DDRScramCtrl_Key1_word1(r32) _BFGET_(r32,31, 0) |
| #define SET32MctrlSS_DDRScramCtrl_Key1_word1(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32MctrlSS_DDRScramCtrl8 {\ |
| UNSG32 uDDRScramCtrl_Key1_word1 : 32;\ |
| } |
| union { UNSG32 u32MctrlSS_DDRScramCtrl8; |
| struct w32MctrlSS_DDRScramCtrl8; |
| }; |
| #define GET32MctrlSS_DDRScramCtrl_Key1_word2(r32) _BFGET_(r32,31, 0) |
| #define SET32MctrlSS_DDRScramCtrl_Key1_word2(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32MctrlSS_DDRScramCtrl9 {\ |
| UNSG32 uDDRScramCtrl_Key1_word2 : 32;\ |
| } |
| union { UNSG32 u32MctrlSS_DDRScramCtrl9; |
| struct w32MctrlSS_DDRScramCtrl9; |
| }; |
| #define GET32MctrlSS_DDRScramCtrl_Key1_word3(r32) _BFGET_(r32,31, 0) |
| #define SET32MctrlSS_DDRScramCtrl_Key1_word3(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32MctrlSS_DDRScramCtrl10 {\ |
| UNSG32 uDDRScramCtrl_Key1_word3 : 32;\ |
| } |
| union { UNSG32 u32MctrlSS_DDRScramCtrl10; |
| struct w32MctrlSS_DDRScramCtrl10; |
| }; |
| #define GET32MctrlSS_DDRScramCtrl_Key1_addr(r32) _BFGET_(r32,31, 0) |
| #define SET32MctrlSS_DDRScramCtrl_Key1_addr(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32MctrlSS_DDRScramCtrl11 {\ |
| UNSG32 uDDRScramCtrl_Key1_addr : 32;\ |
| } |
| union { UNSG32 u32MctrlSS_DDRScramCtrl11; |
| struct w32MctrlSS_DDRScramCtrl11; |
| }; |
| #define GET32MctrlSS_DDRScramCtrl_Key1_mask(r32) _BFGET_(r32,31, 0) |
| #define SET32MctrlSS_DDRScramCtrl_Key1_mask(r32,v) _BFSET_(r32,31, 0,v) |
| |
| #define w32MctrlSS_DDRScramCtrl12 {\ |
| UNSG32 uDDRScramCtrl_Key1_mask : 32;\ |
| } |
| union { UNSG32 u32MctrlSS_DDRScramCtrl12; |
| struct w32MctrlSS_DDRScramCtrl12; |
| }; |
| #define GET32MctrlSS_DDRScramCtrl_W_latency(r32) _BFGET_(r32, 4, 0) |
| #define SET32MctrlSS_DDRScramCtrl_W_latency(r32,v) _BFSET_(r32, 4, 0,v) |
| #define GET16MctrlSS_DDRScramCtrl_W_latency(r16) _BFGET_(r16, 4, 0) |
| #define SET16MctrlSS_DDRScramCtrl_W_latency(r16,v) _BFSET_(r16, 4, 0,v) |
| |
| #define GET32MctrlSS_DDRScramCtrl_R_latency(r32) _BFGET_(r32, 9, 5) |
| #define SET32MctrlSS_DDRScramCtrl_R_latency(r32,v) _BFSET_(r32, 9, 5,v) |
| #define GET16MctrlSS_DDRScramCtrl_R_latency(r16) _BFGET_(r16, 9, 5) |
| #define SET16MctrlSS_DDRScramCtrl_R_latency(r16,v) _BFSET_(r16, 9, 5,v) |
| |
| #define GET32MctrlSS_DDRScramCtrl_cal_latency(r32) _BFGET_(r32,13,10) |
| #define SET32MctrlSS_DDRScramCtrl_cal_latency(r32,v) _BFSET_(r32,13,10,v) |
| #define GET16MctrlSS_DDRScramCtrl_cal_latency(r16) _BFGET_(r16,13,10) |
| #define SET16MctrlSS_DDRScramCtrl_cal_latency(r16,v) _BFSET_(r16,13,10,v) |
| |
| #define w32MctrlSS_DDRScramCtrl13 {\ |
| UNSG32 uDDRScramCtrl_W_latency : 5;\ |
| UNSG32 uDDRScramCtrl_R_latency : 5;\ |
| UNSG32 uDDRScramCtrl_cal_latency : 4;\ |
| UNSG32 RSVDx8034_b14 : 18;\ |
| } |
| union { UNSG32 u32MctrlSS_DDRScramCtrl13; |
| struct w32MctrlSS_DDRScramCtrl13; |
| }; |
| |
| #define GET32MctrlSS_rz_ctrl_arrz_pass(r32) _BFGET_(r32, 7, 0) |
| #define SET32MctrlSS_rz_ctrl_arrz_pass(r32,v) _BFSET_(r32, 7, 0,v) |
| #define GET16MctrlSS_rz_ctrl_arrz_pass(r16) _BFGET_(r16, 7, 0) |
| #define SET16MctrlSS_rz_ctrl_arrz_pass(r16,v) _BFSET_(r16, 7, 0,v) |
| |
| #define GET32MctrlSS_rz_ctrl_awrz_pass(r32) _BFGET_(r32,15, 8) |
| #define SET32MctrlSS_rz_ctrl_awrz_pass(r32,v) _BFSET_(r32,15, 8,v) |
| #define GET16MctrlSS_rz_ctrl_awrz_pass(r16) _BFGET_(r16,15, 8) |
| #define SET16MctrlSS_rz_ctrl_awrz_pass(r16,v) _BFSET_(r16,15, 8,v) |
| |
| #define w32MctrlSS_rz_ctrl {\ |
| UNSG32 urz_ctrl_arrz_pass : 8;\ |
| UNSG32 urz_ctrl_awrz_pass : 8;\ |
| UNSG32 RSVDx8038_b16 : 16;\ |
| } |
| union { UNSG32 u32MctrlSS_rz_ctrl; |
| struct w32MctrlSS_rz_ctrl; |
| }; |
| |
| } SIE_MctrlSS; |
| |
| typedef union T32MctrlSS_MC5_4TO1 |
| { UNSG32 u32; |
| struct w32MctrlSS_MC5_4TO1; |
| } T32MctrlSS_MC5_4TO1; |
| typedef union T32MctrlSS_AVIO_PRIO |
| { UNSG32 u32; |
| struct w32MctrlSS_AVIO_PRIO; |
| } T32MctrlSS_AVIO_PRIO; |
| typedef union T32MctrlSS_ddrPhyLoopBackSrc |
| { UNSG32 u32; |
| struct w32MctrlSS_ddrPhyLoopBackSrc; |
| } T32MctrlSS_ddrPhyLoopBackSrc; |
| typedef union T32MctrlSS_ddrPhyLoopBackConfig1 |
| { UNSG32 u32; |
| struct w32MctrlSS_ddrPhyLoopBackConfig1; |
| } T32MctrlSS_ddrPhyLoopBackConfig1; |
| typedef union T32MctrlSS_ddrPhyLoopBackConfig2 |
| { UNSG32 u32; |
| struct w32MctrlSS_ddrPhyLoopBackConfig2; |
| } T32MctrlSS_ddrPhyLoopBackConfig2; |
| typedef union T32MctrlSS_ddrPhyLoopBackConfig3 |
| { UNSG32 u32; |
| struct w32MctrlSS_ddrPhyLoopBackConfig3; |
| } T32MctrlSS_ddrPhyLoopBackConfig3; |
| typedef union T32MctrlSS_ddrPhyLoopBackStatus1 |
| { UNSG32 u32; |
| struct w32MctrlSS_ddrPhyLoopBackStatus1; |
| } T32MctrlSS_ddrPhyLoopBackStatus1; |
| typedef union T32MctrlSS_ddrPhyLoopBackStatus2 |
| { UNSG32 u32; |
| struct w32MctrlSS_ddrPhyLoopBackStatus2; |
| } T32MctrlSS_ddrPhyLoopBackStatus2; |
| typedef union T32MctrlSS_mc_phy_pd_ctrl |
| { UNSG32 u32; |
| struct w32MctrlSS_mc_phy_pd_ctrl; |
| } T32MctrlSS_mc_phy_pd_ctrl; |
| typedef union T32MctrlSS_mc_mstr0_qos |
| { UNSG32 u32; |
| struct w32MctrlSS_mc_mstr0_qos; |
| } T32MctrlSS_mc_mstr0_qos; |
| typedef union T32MctrlSS_mc_mstr1_qos |
| { UNSG32 u32; |
| struct w32MctrlSS_mc_mstr1_qos; |
| } T32MctrlSS_mc_mstr1_qos; |
| typedef union T32MctrlSS_mc_mstr2_qos |
| { UNSG32 u32; |
| struct w32MctrlSS_mc_mstr2_qos; |
| } T32MctrlSS_mc_mstr2_qos; |
| typedef union T32MctrlSS_mc_mstr3_qos |
| { UNSG32 u32; |
| struct w32MctrlSS_mc_mstr3_qos; |
| } T32MctrlSS_mc_mstr3_qos; |
| typedef union T32MctrlSS_mc_mstr4_qos |
| { UNSG32 u32; |
| struct w32MctrlSS_mc_mstr4_qos; |
| } T32MctrlSS_mc_mstr4_qos; |
| typedef union T32MctrlSS_mc_mstr5_qos |
| { UNSG32 u32; |
| struct w32MctrlSS_mc_mstr5_qos; |
| } T32MctrlSS_mc_mstr5_qos; |
| typedef union T32MctrlSS_mc_mstr6_qos |
| { UNSG32 u32; |
| struct w32MctrlSS_mc_mstr6_qos; |
| } T32MctrlSS_mc_mstr6_qos; |
| typedef union T32MctrlSS_mc_mstr7_qos |
| { UNSG32 u32; |
| struct w32MctrlSS_mc_mstr7_qos; |
| } T32MctrlSS_mc_mstr7_qos; |
| typedef union T32MctrlSS_mc_hw_phy_dll_update_req |
| { UNSG32 u32; |
| struct w32MctrlSS_mc_hw_phy_dll_update_req; |
| } T32MctrlSS_mc_hw_phy_dll_update_req; |
| typedef union T32MctrlSS_mc_hw_dfc_ctrl |
| { UNSG32 u32; |
| struct w32MctrlSS_mc_hw_dfc_ctrl; |
| } T32MctrlSS_mc_hw_dfc_ctrl; |
| typedef union T32MctrlSS_mc_hw_dfc_sts |
| { UNSG32 u32; |
| struct w32MctrlSS_mc_hw_dfc_sts; |
| } T32MctrlSS_mc_hw_dfc_sts; |
| typedef union T32MctrlSS_RWTC_31to0 |
| { UNSG32 u32; |
| struct w32MctrlSS_RWTC_31to0; |
| } T32MctrlSS_RWTC_31to0; |
| typedef union T32MctrlSS_RWTC_57to32 |
| { UNSG32 u32; |
| struct w32MctrlSS_RWTC_57to32; |
| } T32MctrlSS_RWTC_57to32; |
| typedef union T32MctrlSS_DDRCLK_VREG_CTRL_0 |
| { UNSG32 u32; |
| struct w32MctrlSS_DDRCLK_VREG_CTRL_0; |
| } T32MctrlSS_DDRCLK_VREG_CTRL_0; |
| typedef union T32MctrlSS_DDRCLK_VREG_CTRL_1 |
| { UNSG32 u32; |
| struct w32MctrlSS_DDRCLK_VREG_CTRL_1; |
| } T32MctrlSS_DDRCLK_VREG_CTRL_1; |
| typedef union T32MctrlSS_DDRCLK_VREG_CTRL_2 |
| { UNSG32 u32; |
| struct w32MctrlSS_DDRCLK_VREG_CTRL_2; |
| } T32MctrlSS_DDRCLK_VREG_CTRL_2; |
| typedef union T32MctrlSS_DDRCLK_VREG_CTRL_3 |
| { UNSG32 u32; |
| struct w32MctrlSS_DDRCLK_VREG_CTRL_3; |
| } T32MctrlSS_DDRCLK_VREG_CTRL_3; |
| typedef union T32MctrlSS_DDRCLK_VREG_CTRL_4 |
| { UNSG32 u32; |
| struct w32MctrlSS_DDRCLK_VREG_CTRL_4; |
| } T32MctrlSS_DDRCLK_VREG_CTRL_4; |
| typedef union T32MctrlSS_DDRCLK_VREG_CTRL_5 |
| { UNSG32 u32; |
| struct w32MctrlSS_DDRCLK_VREG_CTRL_5; |
| } T32MctrlSS_DDRCLK_VREG_CTRL_5; |
| typedef union T32MctrlSS_DDRScramCtrl |
| { UNSG32 u32; |
| struct w32MctrlSS_DDRScramCtrl; |
| } T32MctrlSS_DDRScramCtrl; |
| typedef union T32MctrlSS_DDRScramCtrl1 |
| { UNSG32 u32; |
| struct w32MctrlSS_DDRScramCtrl1; |
| } T32MctrlSS_DDRScramCtrl1; |
| typedef union T32MctrlSS_DDRScramCtrl2 |
| { UNSG32 u32; |
| struct w32MctrlSS_DDRScramCtrl2; |
| } T32MctrlSS_DDRScramCtrl2; |
| typedef union T32MctrlSS_DDRScramCtrl3 |
| { UNSG32 u32; |
| struct w32MctrlSS_DDRScramCtrl3; |
| } T32MctrlSS_DDRScramCtrl3; |
| typedef union T32MctrlSS_DDRScramCtrl4 |
| { UNSG32 u32; |
| struct w32MctrlSS_DDRScramCtrl4; |
| } T32MctrlSS_DDRScramCtrl4; |
| typedef union T32MctrlSS_DDRScramCtrl5 |
| { UNSG32 u32; |
| struct w32MctrlSS_DDRScramCtrl5; |
| } T32MctrlSS_DDRScramCtrl5; |
| typedef union T32MctrlSS_DDRScramCtrl6 |
| { UNSG32 u32; |
| struct w32MctrlSS_DDRScramCtrl6; |
| } T32MctrlSS_DDRScramCtrl6; |
| typedef union T32MctrlSS_DDRScramCtrl7 |
| { UNSG32 u32; |
| struct w32MctrlSS_DDRScramCtrl7; |
| } T32MctrlSS_DDRScramCtrl7; |
| typedef union T32MctrlSS_DDRScramCtrl8 |
| { UNSG32 u32; |
| struct w32MctrlSS_DDRScramCtrl8; |
| } T32MctrlSS_DDRScramCtrl8; |
| typedef union T32MctrlSS_DDRScramCtrl9 |
| { UNSG32 u32; |
| struct w32MctrlSS_DDRScramCtrl9; |
| } T32MctrlSS_DDRScramCtrl9; |
| typedef union T32MctrlSS_DDRScramCtrl10 |
| { UNSG32 u32; |
| struct w32MctrlSS_DDRScramCtrl10; |
| } T32MctrlSS_DDRScramCtrl10; |
| typedef union T32MctrlSS_DDRScramCtrl11 |
| { UNSG32 u32; |
| struct w32MctrlSS_DDRScramCtrl11; |
| } T32MctrlSS_DDRScramCtrl11; |
| typedef union T32MctrlSS_DDRScramCtrl12 |
| { UNSG32 u32; |
| struct w32MctrlSS_DDRScramCtrl12; |
| } T32MctrlSS_DDRScramCtrl12; |
| typedef union T32MctrlSS_DDRScramCtrl13 |
| { UNSG32 u32; |
| struct w32MctrlSS_DDRScramCtrl13; |
| } T32MctrlSS_DDRScramCtrl13; |
| typedef union T32MctrlSS_rz_ctrl |
| { UNSG32 u32; |
| struct w32MctrlSS_rz_ctrl; |
| } T32MctrlSS_rz_ctrl; |
| |
| |
| typedef union TMctrlSS_MC5_4TO1 |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_MC5_4TO1; |
| }; |
| } TMctrlSS_MC5_4TO1; |
| typedef union TMctrlSS_AVIO_PRIO |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_AVIO_PRIO; |
| }; |
| } TMctrlSS_AVIO_PRIO; |
| typedef union TMctrlSS_ddrPhyLoopBackSrc |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_ddrPhyLoopBackSrc; |
| }; |
| } TMctrlSS_ddrPhyLoopBackSrc; |
| typedef union TMctrlSS_ddrPhyLoopBackConfig1 |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_ddrPhyLoopBackConfig1; |
| }; |
| } TMctrlSS_ddrPhyLoopBackConfig1; |
| typedef union TMctrlSS_ddrPhyLoopBackConfig2 |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_ddrPhyLoopBackConfig2; |
| }; |
| } TMctrlSS_ddrPhyLoopBackConfig2; |
| typedef union TMctrlSS_ddrPhyLoopBackConfig3 |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_ddrPhyLoopBackConfig3; |
| }; |
| } TMctrlSS_ddrPhyLoopBackConfig3; |
| typedef union TMctrlSS_ddrPhyLoopBackStatus1 |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_ddrPhyLoopBackStatus1; |
| }; |
| } TMctrlSS_ddrPhyLoopBackStatus1; |
| typedef union TMctrlSS_ddrPhyLoopBackStatus2 |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_ddrPhyLoopBackStatus2; |
| }; |
| } TMctrlSS_ddrPhyLoopBackStatus2; |
| typedef union TMctrlSS_mc_phy_pd_ctrl |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_mc_phy_pd_ctrl; |
| }; |
| } TMctrlSS_mc_phy_pd_ctrl; |
| typedef union TMctrlSS_mc_mstr0_qos |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_mc_mstr0_qos; |
| }; |
| } TMctrlSS_mc_mstr0_qos; |
| typedef union TMctrlSS_mc_mstr1_qos |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_mc_mstr1_qos; |
| }; |
| } TMctrlSS_mc_mstr1_qos; |
| typedef union TMctrlSS_mc_mstr2_qos |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_mc_mstr2_qos; |
| }; |
| } TMctrlSS_mc_mstr2_qos; |
| typedef union TMctrlSS_mc_mstr3_qos |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_mc_mstr3_qos; |
| }; |
| } TMctrlSS_mc_mstr3_qos; |
| typedef union TMctrlSS_mc_mstr4_qos |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_mc_mstr4_qos; |
| }; |
| } TMctrlSS_mc_mstr4_qos; |
| typedef union TMctrlSS_mc_mstr5_qos |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_mc_mstr5_qos; |
| }; |
| } TMctrlSS_mc_mstr5_qos; |
| typedef union TMctrlSS_mc_mstr6_qos |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_mc_mstr6_qos; |
| }; |
| } TMctrlSS_mc_mstr6_qos; |
| typedef union TMctrlSS_mc_mstr7_qos |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_mc_mstr7_qos; |
| }; |
| } TMctrlSS_mc_mstr7_qos; |
| typedef union TMctrlSS_mc_hw_phy_dll_update_req |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_mc_hw_phy_dll_update_req; |
| }; |
| } TMctrlSS_mc_hw_phy_dll_update_req; |
| typedef union TMctrlSS_mc_hw_dfc_ctrl |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_mc_hw_dfc_ctrl; |
| }; |
| } TMctrlSS_mc_hw_dfc_ctrl; |
| typedef union TMctrlSS_mc_hw_dfc_sts |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_mc_hw_dfc_sts; |
| }; |
| } TMctrlSS_mc_hw_dfc_sts; |
| typedef union TMctrlSS_RWTC_31to0 |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_RWTC_31to0; |
| }; |
| } TMctrlSS_RWTC_31to0; |
| typedef union TMctrlSS_RWTC_57to32 |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_RWTC_57to32; |
| }; |
| } TMctrlSS_RWTC_57to32; |
| typedef union TMctrlSS_DDRCLK_VREG_CTRL_0 |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_DDRCLK_VREG_CTRL_0; |
| }; |
| } TMctrlSS_DDRCLK_VREG_CTRL_0; |
| typedef union TMctrlSS_DDRCLK_VREG_CTRL_1 |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_DDRCLK_VREG_CTRL_1; |
| }; |
| } TMctrlSS_DDRCLK_VREG_CTRL_1; |
| typedef union TMctrlSS_DDRCLK_VREG_CTRL_2 |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_DDRCLK_VREG_CTRL_2; |
| }; |
| } TMctrlSS_DDRCLK_VREG_CTRL_2; |
| typedef union TMctrlSS_DDRCLK_VREG_CTRL_3 |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_DDRCLK_VREG_CTRL_3; |
| }; |
| } TMctrlSS_DDRCLK_VREG_CTRL_3; |
| typedef union TMctrlSS_DDRCLK_VREG_CTRL_4 |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_DDRCLK_VREG_CTRL_4; |
| }; |
| } TMctrlSS_DDRCLK_VREG_CTRL_4; |
| typedef union TMctrlSS_DDRCLK_VREG_CTRL_5 |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_DDRCLK_VREG_CTRL_5; |
| }; |
| } TMctrlSS_DDRCLK_VREG_CTRL_5; |
| typedef union TMctrlSS_DDRScramCtrl |
| { UNSG32 u32[14]; |
| struct { |
| struct w32MctrlSS_DDRScramCtrl; |
| struct w32MctrlSS_DDRScramCtrl1; |
| struct w32MctrlSS_DDRScramCtrl2; |
| struct w32MctrlSS_DDRScramCtrl3; |
| struct w32MctrlSS_DDRScramCtrl4; |
| struct w32MctrlSS_DDRScramCtrl5; |
| struct w32MctrlSS_DDRScramCtrl6; |
| struct w32MctrlSS_DDRScramCtrl7; |
| struct w32MctrlSS_DDRScramCtrl8; |
| struct w32MctrlSS_DDRScramCtrl9; |
| struct w32MctrlSS_DDRScramCtrl10; |
| struct w32MctrlSS_DDRScramCtrl11; |
| struct w32MctrlSS_DDRScramCtrl12; |
| struct w32MctrlSS_DDRScramCtrl13; |
| }; |
| } TMctrlSS_DDRScramCtrl; |
| typedef union TMctrlSS_rz_ctrl |
| { UNSG32 u32[1]; |
| struct { |
| struct w32MctrlSS_rz_ctrl; |
| }; |
| } TMctrlSS_rz_ctrl; |
| |
| |
| SIGN32 MctrlSS_drvrd(SIE_MctrlSS *p, UNSG32 base, SIGN32 mem, SIGN32 tst); |
| SIGN32 MctrlSS_drvwr(SIE_MctrlSS *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd); |
| void MctrlSS_reset(SIE_MctrlSS *p); |
| SIGN32 MctrlSS_cmp (SIE_MctrlSS *p, SIE_MctrlSS *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst); |
| #define MctrlSS_check(p,pie,pfx,hLOG) MctrlSS_cmp(p,pie,pfx,(void*)(hLOG),0,0) |
| #define MctrlSS_print(p, pfx,hLOG) MctrlSS_cmp(p,0, pfx,(void*)(hLOG),0,0) |
| |
| #endif |
| |
| |
| |
| |
| |
| |
| #ifdef __cplusplus |
| } |
| #endif |
| #pragma pack() |
| |
| #endif |
