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nest-open-source / manifest_repos / bootloader / e809e064761c7f427b0a6d8f2461cf2194a86b29 / . / berlin_tools / bootloader / common / include / chip / as370 / A0 / SysMgr.h
blob: 5a7253f6930d7f461533e2a66e31bee9c65e5144 [file] [log] [blame]
//////
/// don't edit! auto-generated by docc: SysMgr.h
////////////////////////////////////////////////////////////
#ifndef SysMgr_h
#define SysMgr_h (){}
#include "ctypes.h"
#pragma pack(1)
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _DOCC_H_BITOPS_
#define _DOCC_H_BITOPS_ (){}
#define _bSETMASK_(b) ((b)<32 ? (1<<((b)&31)) : 0)
#define _NSETMASK_(msb,lsb) (_bSETMASK_((msb)+1)-_bSETMASK_(lsb))
#define _bCLRMASK_(b) (~_bSETMASK_(b))
#define _NCLRMASK_(msb,lsb) (~_NSETMASK_(msb,lsb))
#define _BFGET_(r,msb,lsb) (_NSETMASK_((msb)-(lsb),0)&((r)>>(lsb)))
#define _BFSET_(r,msb,lsb,v) do{ (r)&=_NCLRMASK_(msb,lsb); (r)|=_NSETMASK_(msb,lsb)&((v)<<(lsb)); }while(0)
#endif
//////
///
/// $INTERFACE BYTE (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 edid_byte (P)
/// %unsigned 8 val
/// ###
/// * One byte of EDID SRAM
/// * End of Color EDID_BYTE definition.
/// ###
/// %% 24 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 4B, bits: 8b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_BYTE
#define h_BYTE (){}
#define RA_BYTE_edid_byte 0x0000
#define BA_BYTE_edid_byte_val 0x0000
#define B16BYTE_edid_byte_val 0x0000
#define LSb32BYTE_edid_byte_val 0
#define LSb16BYTE_edid_byte_val 0
#define bBYTE_edid_byte_val 8
#define MSK32BYTE_edid_byte_val 0x000000FF
///////////////////////////////////////////////////////////
typedef struct SIE_BYTE {
///////////////////////////////////////////////////////////
#define GET32BYTE_edid_byte_val(r32) _BFGET_(r32, 7, 0)
#define SET32BYTE_edid_byte_val(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16BYTE_edid_byte_val(r16) _BFGET_(r16, 7, 0)
#define SET16BYTE_edid_byte_val(r16,v) _BFSET_(r16, 7, 0,v)
#define w32BYTE_edid_byte {\
UNSG32 uedid_byte_val : 8;\
UNSG32 RSVDx0_b8 : 24;\
}
union { UNSG32 u32BYTE_edid_byte;
struct w32BYTE_edid_byte;
};
///////////////////////////////////////////////////////////
} SIE_BYTE;
typedef union T32BYTE_edid_byte
{ UNSG32 u32;
struct w32BYTE_edid_byte;
} T32BYTE_edid_byte;
///////////////////////////////////////////////////////////
typedef union TBYTE_edid_byte
{ UNSG32 u32[1];
struct {
struct w32BYTE_edid_byte;
};
} TBYTE_edid_byte;
///////////////////////////////////////////////////////////
SIGN32 BYTE_drvrd(SIE_BYTE *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 BYTE_drvwr(SIE_BYTE *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void BYTE_reset(SIE_BYTE *p);
SIGN32 BYTE_cmp (SIE_BYTE *p, SIE_BYTE *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define BYTE_check(p,pie,pfx,hLOG) BYTE_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define BYTE_print(p, pfx,hLOG) BYTE_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: BYTE
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE EDID_SRAM (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 (P)
/// # 0x00000 sram
/// $BYTE sram MEM [256]
/// ###
/// * 256x8 SRAM for EDID
/// * End of Color EDID_SRAM definition.
/// ###
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 1024B, bits: 32b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_EDID_SRAM
#define h_EDID_SRAM (){}
#define RA_EDID_SRAM_sram 0x0000
///////////////////////////////////////////////////////////
typedef struct SIE_EDID_SRAM {
///////////////////////////////////////////////////////////
SIE_BYTE ie_sram[256];
///////////////////////////////////////////////////////////
} SIE_EDID_SRAM;
///////////////////////////////////////////////////////////
SIGN32 EDID_SRAM_drvrd(SIE_EDID_SRAM *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 EDID_SRAM_drvwr(SIE_EDID_SRAM *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void EDID_SRAM_reset(SIE_EDID_SRAM *p);
SIGN32 EDID_SRAM_cmp (SIE_EDID_SRAM *p, SIE_EDID_SRAM *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define EDID_SRAM_check(p,pie,pfx,hLOG) EDID_SRAM_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define EDID_SRAM_print(p, pfx,hLOG) EDID_SRAM_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: EDID_SRAM
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE EDID biu (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 (P)
/// # 0x00000 sram
/// $EDID_SRAM sram MEM
/// ###
/// * EDID SRAM
/// ###
/// @ 0x00400 I2C_CTRL (P)
/// ###
/// * EDID I2C control register
/// ###
/// %unsigned 1 en 0x0
/// ###
/// * 0: EDID I2C slave disabled.
/// * 1: EDID I2C slave enabled.
/// ###
/// %unsigned 7 slv_addr 0x50
/// ###
/// * This is the slave address of EDID I2C slave on a DDC bus. This slave address is excluding read_write bit and its value should be 0x50 (0xA0 for write and 0xA1 for read when read_write bit is included) always. Programming different values is given for debugging purpose.
/// * biuHDRX.v
/// ###
/// %unsigned 1 cpu_wr_done 0x0
/// ###
/// * HDMI-RX has 256 bytes of EDID memory (one segment), in EDDC mode there are maximum 127 segments. To facilitate these 127 segments, an interrupt is raised whenever 0xA0 slave address is received. For this interrupt CPU should read the segment pointer value and copy 256 bytes of this EDID segment from its internal storage to EDID memory and set this bit.
/// * 0: CPU not yet wrote EDID memory.
/// * 1: CPU wrote EDID memory.
/// ###
/// %unsigned 1 cpu_wr_done_ac_dis 0x0
/// ###
/// * 0: cpu_wr_done auto clear enabled.
/// * 1: cpu_wr_done auto clear disabled.
/// * In non EDDC mode, there will be only one segment of EDID, so S/W doesnot require interrupts to change segments. Once EDID is properly written into EDID memory set cpu_wr_done bit and this bit.
/// ###
/// %unsigned 1 mem_cen_sel 0x0
/// ###
/// * 0:H/W generated dynamic CEn is selected for EDID SRAM.
/// * 1:S/W static CEn (EDID_I2C_CTRL.mem_cen) is selected for EDID SRAM.
/// ###
/// %unsigned 1 mem_cen 0x0
/// ###
/// * 0: EDID SRAM is enabled.
/// * 1:EDID SRAM is disabled.
/// * This bit is connected to EDID SRAM CEn (Active low Chip Enable) input if EDID_I2C-CTRL.mem_cen_sel bit is “1”.
/// ###
/// %% 20 # Stuffing bits...
/// @ 0x00404 I2C_ST (R-)
/// ###
/// * EDID segment pointer register
/// ###
/// %unsigned 8 seg_ptr
/// ###
/// * EDDC EDID segment pointer value, transmitted by host (HDMI transmitter).
/// ###
/// %unsigned 1 cpu_wr_done_st
/// ###
/// * This bit is set when EDID_I2C_CTRL_cpu_wr_done bit is set. This bit will be auto cleared when next read transaction is started unless cpu_wr_done_ac_dis bit is set.
/// ###
/// %% 23 # Stuffing bits...
/// @ 0x00408 (W-)
/// # # Stuffing bytes...
/// %% 8128
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 2048B, bits: 53b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_EDID
#define h_EDID (){}
#define RA_EDID_sram 0x0000
///////////////////////////////////////////////////////////
#define RA_EDID_I2C_CTRL 0x0400
#define BA_EDID_I2C_CTRL_en 0x0400
#define B16EDID_I2C_CTRL_en 0x0400
#define LSb32EDID_I2C_CTRL_en 0
#define LSb16EDID_I2C_CTRL_en 0
#define bEDID_I2C_CTRL_en 1
#define MSK32EDID_I2C_CTRL_en 0x00000001
#define BA_EDID_I2C_CTRL_slv_addr 0x0400
#define B16EDID_I2C_CTRL_slv_addr 0x0400
#define LSb32EDID_I2C_CTRL_slv_addr 1
#define LSb16EDID_I2C_CTRL_slv_addr 1
#define bEDID_I2C_CTRL_slv_addr 7
#define MSK32EDID_I2C_CTRL_slv_addr 0x000000FE
#define BA_EDID_I2C_CTRL_cpu_wr_done 0x0401
#define B16EDID_I2C_CTRL_cpu_wr_done 0x0400
#define LSb32EDID_I2C_CTRL_cpu_wr_done 8
#define LSb16EDID_I2C_CTRL_cpu_wr_done 8
#define bEDID_I2C_CTRL_cpu_wr_done 1
#define MSK32EDID_I2C_CTRL_cpu_wr_done 0x00000100
#define BA_EDID_I2C_CTRL_cpu_wr_done_ac_dis 0x0401
#define B16EDID_I2C_CTRL_cpu_wr_done_ac_dis 0x0400
#define LSb32EDID_I2C_CTRL_cpu_wr_done_ac_dis 9
#define LSb16EDID_I2C_CTRL_cpu_wr_done_ac_dis 9
#define bEDID_I2C_CTRL_cpu_wr_done_ac_dis 1
#define MSK32EDID_I2C_CTRL_cpu_wr_done_ac_dis 0x00000200
#define BA_EDID_I2C_CTRL_mem_cen_sel 0x0401
#define B16EDID_I2C_CTRL_mem_cen_sel 0x0400
#define LSb32EDID_I2C_CTRL_mem_cen_sel 10
#define LSb16EDID_I2C_CTRL_mem_cen_sel 10
#define bEDID_I2C_CTRL_mem_cen_sel 1
#define MSK32EDID_I2C_CTRL_mem_cen_sel 0x00000400
#define BA_EDID_I2C_CTRL_mem_cen 0x0401
#define B16EDID_I2C_CTRL_mem_cen 0x0400
#define LSb32EDID_I2C_CTRL_mem_cen 11
#define LSb16EDID_I2C_CTRL_mem_cen 11
#define bEDID_I2C_CTRL_mem_cen 1
#define MSK32EDID_I2C_CTRL_mem_cen 0x00000800
///////////////////////////////////////////////////////////
#define RA_EDID_I2C_ST 0x0404
#define BA_EDID_I2C_ST_seg_ptr 0x0404
#define B16EDID_I2C_ST_seg_ptr 0x0404
#define LSb32EDID_I2C_ST_seg_ptr 0
#define LSb16EDID_I2C_ST_seg_ptr 0
#define bEDID_I2C_ST_seg_ptr 8
#define MSK32EDID_I2C_ST_seg_ptr 0x000000FF
#define BA_EDID_I2C_ST_cpu_wr_done_st 0x0405
#define B16EDID_I2C_ST_cpu_wr_done_st 0x0404
#define LSb32EDID_I2C_ST_cpu_wr_done_st 8
#define LSb16EDID_I2C_ST_cpu_wr_done_st 8
#define bEDID_I2C_ST_cpu_wr_done_st 1
#define MSK32EDID_I2C_ST_cpu_wr_done_st 0x00000100
///////////////////////////////////////////////////////////
typedef struct SIE_EDID {
///////////////////////////////////////////////////////////
SIE_EDID_SRAM ie_sram;
///////////////////////////////////////////////////////////
#define GET32EDID_I2C_CTRL_en(r32) _BFGET_(r32, 0, 0)
#define SET32EDID_I2C_CTRL_en(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16EDID_I2C_CTRL_en(r16) _BFGET_(r16, 0, 0)
#define SET16EDID_I2C_CTRL_en(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32EDID_I2C_CTRL_slv_addr(r32) _BFGET_(r32, 7, 1)
#define SET32EDID_I2C_CTRL_slv_addr(r32,v) _BFSET_(r32, 7, 1,v)
#define GET16EDID_I2C_CTRL_slv_addr(r16) _BFGET_(r16, 7, 1)
#define SET16EDID_I2C_CTRL_slv_addr(r16,v) _BFSET_(r16, 7, 1,v)
#define GET32EDID_I2C_CTRL_cpu_wr_done(r32) _BFGET_(r32, 8, 8)
#define SET32EDID_I2C_CTRL_cpu_wr_done(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16EDID_I2C_CTRL_cpu_wr_done(r16) _BFGET_(r16, 8, 8)
#define SET16EDID_I2C_CTRL_cpu_wr_done(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32EDID_I2C_CTRL_cpu_wr_done_ac_dis(r32) _BFGET_(r32, 9, 9)
#define SET32EDID_I2C_CTRL_cpu_wr_done_ac_dis(r32,v) _BFSET_(r32, 9, 9,v)
#define GET16EDID_I2C_CTRL_cpu_wr_done_ac_dis(r16) _BFGET_(r16, 9, 9)
#define SET16EDID_I2C_CTRL_cpu_wr_done_ac_dis(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32EDID_I2C_CTRL_mem_cen_sel(r32) _BFGET_(r32,10,10)
#define SET32EDID_I2C_CTRL_mem_cen_sel(r32,v) _BFSET_(r32,10,10,v)
#define GET16EDID_I2C_CTRL_mem_cen_sel(r16) _BFGET_(r16,10,10)
#define SET16EDID_I2C_CTRL_mem_cen_sel(r16,v) _BFSET_(r16,10,10,v)
#define GET32EDID_I2C_CTRL_mem_cen(r32) _BFGET_(r32,11,11)
#define SET32EDID_I2C_CTRL_mem_cen(r32,v) _BFSET_(r32,11,11,v)
#define GET16EDID_I2C_CTRL_mem_cen(r16) _BFGET_(r16,11,11)
#define SET16EDID_I2C_CTRL_mem_cen(r16,v) _BFSET_(r16,11,11,v)
#define w32EDID_I2C_CTRL {\
UNSG32 uI2C_CTRL_en : 1;\
UNSG32 uI2C_CTRL_slv_addr : 7;\
UNSG32 uI2C_CTRL_cpu_wr_done : 1;\
UNSG32 uI2C_CTRL_cpu_wr_done_ac_dis : 1;\
UNSG32 uI2C_CTRL_mem_cen_sel : 1;\
UNSG32 uI2C_CTRL_mem_cen : 1;\
UNSG32 RSVDx400_b12 : 20;\
}
union { UNSG32 u32EDID_I2C_CTRL;
struct w32EDID_I2C_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32EDID_I2C_ST_seg_ptr(r32) _BFGET_(r32, 7, 0)
#define SET32EDID_I2C_ST_seg_ptr(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16EDID_I2C_ST_seg_ptr(r16) _BFGET_(r16, 7, 0)
#define SET16EDID_I2C_ST_seg_ptr(r16,v) _BFSET_(r16, 7, 0,v)
#define GET32EDID_I2C_ST_cpu_wr_done_st(r32) _BFGET_(r32, 8, 8)
#define SET32EDID_I2C_ST_cpu_wr_done_st(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16EDID_I2C_ST_cpu_wr_done_st(r16) _BFGET_(r16, 8, 8)
#define SET16EDID_I2C_ST_cpu_wr_done_st(r16,v) _BFSET_(r16, 8, 8,v)
#define w32EDID_I2C_ST {\
UNSG32 uI2C_ST_seg_ptr : 8;\
UNSG32 uI2C_ST_cpu_wr_done_st : 1;\
UNSG32 RSVDx404_b9 : 23;\
}
union { UNSG32 u32EDID_I2C_ST;
struct w32EDID_I2C_ST;
};
///////////////////////////////////////////////////////////
UNSG8 RSVDx408 [1016];
///////////////////////////////////////////////////////////
} SIE_EDID;
typedef union T32EDID_I2C_CTRL
{ UNSG32 u32;
struct w32EDID_I2C_CTRL;
} T32EDID_I2C_CTRL;
typedef union T32EDID_I2C_ST
{ UNSG32 u32;
struct w32EDID_I2C_ST;
} T32EDID_I2C_ST;
///////////////////////////////////////////////////////////
typedef union TEDID_I2C_CTRL
{ UNSG32 u32[1];
struct {
struct w32EDID_I2C_CTRL;
};
} TEDID_I2C_CTRL;
typedef union TEDID_I2C_ST
{ UNSG32 u32[1];
struct {
struct w32EDID_I2C_ST;
};
} TEDID_I2C_ST;
///////////////////////////////////////////////////////////
SIGN32 EDID_drvrd(SIE_EDID *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 EDID_drvwr(SIE_EDID *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void EDID_reset(SIE_EDID *p);
SIGN32 EDID_cmp (SIE_EDID *p, SIE_EDID *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define EDID_check(p,pie,pfx,hLOG) EDID_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define EDID_print(p, pfx,hLOG) EDID_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: EDID
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE padRing (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (P-)
/// %unsigned 1 REG_PDB_CORE 0x1
/// : NORMAL 0x1
/// : PWRDN 0x0
/// ###
/// * When REG_PDB_CORE is logic '1', the regulator works in normal mode and consumes ~60uA current at typical 25degC. When REG_PDB_CORE is logic '0', the regulator works in power-down mode and consumes ~6uA current at typical 25degC.
/// ###
/// %unsigned 1 REF_INT_EN 0x1
/// : NORMAL 0x1
/// : REF_DOWN 0x0
/// ###
/// * When REF_INT_EN='1', REF/REF_FT is generated internally. When REF_INT_EN='0', the internal REF circuit is powered down and the REF signal is brought down to 0.
/// * Since we do not use HSIN pads in bg3, we do not use this setting.
/// ###
/// %unsigned 1 V18EN_CORE 0x0
/// %unsigned 1 V25EN_CORE 0x0
/// ###
/// * V18EN_CORE and V25EN_CORE are settings for different IO supply level
/// * V18EN_CORE=0,V25EN_CORE=0 : 3.3V
/// * V18EN_CORE=0,V25EN_CORE=1 : 2.5V
/// * V18EN_CORE=1,V25EN_CORE=X : 1.5V, 1.5V or 1.8V
/// ###
/// %unsigned 4 ZP 0x0
/// ###
/// * ZP[3:0] is used to program PMOS output driver strength for PADXDC_HSIOB. ZP[3:0]='1111' is the strongest setting.
/// ###
/// %unsigned 4 ZN 0x0
/// ###
/// * ZN[3:0] is used to program NMOS output driver strength for PADXDC_HSIOB. ZN[3:0]='1111' is the strongest setting.
/// ###
/// %unsigned 4 CAL_ZP 0x0
/// ###
/// * ZN / ZP signals for calibration pad.
/// * ZN / ZP signals of the output impedance calibration pad and the functional I/O pad should be separated.
/// ###
/// %unsigned 4 CAL_ZN 0x0
/// ###
/// * ZN / ZP signals for calibration pad.
/// * ZN / ZP signals of the output impedance calibration pad and the functional I/O pad should be separated.
/// ###
/// %unsigned 1 CAL_P_EN 0x0
/// ###
/// * CAL_P_EN is active high core signal. Needs to be asserted high to start the PMOS driver calibration
/// ###
/// %unsigned 1 CAL_N_EN 0x0
/// ###
/// * CAL_N_EN is active high core signal. Needs to be asserted high to start the NMOS driver calibration. PMOS driver has to be calibrated first, and ZP_AFT_CAL[3:0] need to be set to the calibrated PMOS settings before CAL_N_EN is asserted high
/// ###
/// %unsigned 1 ODR_EN 0x1
/// ###
/// * When off-chip resistor is used, please set ODR_EN=0. When internal resistor is used for calibration, please set ODR_EN=1 and choose a proper ODR[2:0] setting to achieve desired driver strength.
/// ###
/// %unsigned 3 ODR 0x0
/// ###
/// * ODR[2:0] is used to adjust the internal reference resistor value for calibration without external resistor. ODR_EN need to be set to '1' to enable internal resistor.
/// ###
/// %unsigned 4 ZP_AFT_CAL 0x0
/// ###
/// * ZP_AFT_CAL[3:0] are active high signals at the core signal level. They should be fed in by the registers that stores the settings after the PMOS driver calibration
/// ###
/// %% 2 # Stuffing bits...
/// @ 0x00004 status (R-)
/// %unsigned 1 CAL_P_INC
/// ###
/// * CAL_P_INC is the output of the comparator. When the pad voltage is lower than the internal reference voltage, CAL_P_INC is high (i.e. the output impedance of PMOS is higher than the desired impedance).
/// * In a calibration loop, CAL_P_INC high can be interpreted as a signal to increment ZP[3:0].
/// ###
/// %unsigned 1 CAL_N_INC
/// ###
/// * CAL_N_INC is the output of the comparator. When the pad voltage is higher than the internal reference voltage, CAL_N_INC is high (i.e. the output impedance of NMOS is higher than the desired impedance). In a calibration loop, CAL_N_INC high can be interpreted as a signal to increment ZN[3:0].
/// ###
/// %% 30 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 8B, bits: 32b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_padRing
#define h_padRing (){}
#define RA_padRing_ctrl 0x0000
#define BA_padRing_ctrl_REG_PDB_CORE 0x0000
#define B16padRing_ctrl_REG_PDB_CORE 0x0000
#define LSb32padRing_ctrl_REG_PDB_CORE 0
#define LSb16padRing_ctrl_REG_PDB_CORE 0
#define bpadRing_ctrl_REG_PDB_CORE 1
#define MSK32padRing_ctrl_REG_PDB_CORE 0x00000001
#define padRing_ctrl_REG_PDB_CORE_NORMAL 0x1
#define padRing_ctrl_REG_PDB_CORE_PWRDN 0x0
#define BA_padRing_ctrl_REF_INT_EN 0x0000
#define B16padRing_ctrl_REF_INT_EN 0x0000
#define LSb32padRing_ctrl_REF_INT_EN 1
#define LSb16padRing_ctrl_REF_INT_EN 1
#define bpadRing_ctrl_REF_INT_EN 1
#define MSK32padRing_ctrl_REF_INT_EN 0x00000002
#define padRing_ctrl_REF_INT_EN_NORMAL 0x1
#define padRing_ctrl_REF_INT_EN_REF_DOWN 0x0
#define BA_padRing_ctrl_V18EN_CORE 0x0000
#define B16padRing_ctrl_V18EN_CORE 0x0000
#define LSb32padRing_ctrl_V18EN_CORE 2
#define LSb16padRing_ctrl_V18EN_CORE 2
#define bpadRing_ctrl_V18EN_CORE 1
#define MSK32padRing_ctrl_V18EN_CORE 0x00000004
#define BA_padRing_ctrl_V25EN_CORE 0x0000
#define B16padRing_ctrl_V25EN_CORE 0x0000
#define LSb32padRing_ctrl_V25EN_CORE 3
#define LSb16padRing_ctrl_V25EN_CORE 3
#define bpadRing_ctrl_V25EN_CORE 1
#define MSK32padRing_ctrl_V25EN_CORE 0x00000008
#define BA_padRing_ctrl_ZP 0x0000
#define B16padRing_ctrl_ZP 0x0000
#define LSb32padRing_ctrl_ZP 4
#define LSb16padRing_ctrl_ZP 4
#define bpadRing_ctrl_ZP 4
#define MSK32padRing_ctrl_ZP 0x000000F0
#define BA_padRing_ctrl_ZN 0x0001
#define B16padRing_ctrl_ZN 0x0000
#define LSb32padRing_ctrl_ZN 8
#define LSb16padRing_ctrl_ZN 8
#define bpadRing_ctrl_ZN 4
#define MSK32padRing_ctrl_ZN 0x00000F00
#define BA_padRing_ctrl_CAL_ZP 0x0001
#define B16padRing_ctrl_CAL_ZP 0x0000
#define LSb32padRing_ctrl_CAL_ZP 12
#define LSb16padRing_ctrl_CAL_ZP 12
#define bpadRing_ctrl_CAL_ZP 4
#define MSK32padRing_ctrl_CAL_ZP 0x0000F000
#define BA_padRing_ctrl_CAL_ZN 0x0002
#define B16padRing_ctrl_CAL_ZN 0x0002
#define LSb32padRing_ctrl_CAL_ZN 16
#define LSb16padRing_ctrl_CAL_ZN 0
#define bpadRing_ctrl_CAL_ZN 4
#define MSK32padRing_ctrl_CAL_ZN 0x000F0000
#define BA_padRing_ctrl_CAL_P_EN 0x0002
#define B16padRing_ctrl_CAL_P_EN 0x0002
#define LSb32padRing_ctrl_CAL_P_EN 20
#define LSb16padRing_ctrl_CAL_P_EN 4
#define bpadRing_ctrl_CAL_P_EN 1
#define MSK32padRing_ctrl_CAL_P_EN 0x00100000
#define BA_padRing_ctrl_CAL_N_EN 0x0002
#define B16padRing_ctrl_CAL_N_EN 0x0002
#define LSb32padRing_ctrl_CAL_N_EN 21
#define LSb16padRing_ctrl_CAL_N_EN 5
#define bpadRing_ctrl_CAL_N_EN 1
#define MSK32padRing_ctrl_CAL_N_EN 0x00200000
#define BA_padRing_ctrl_ODR_EN 0x0002
#define B16padRing_ctrl_ODR_EN 0x0002
#define LSb32padRing_ctrl_ODR_EN 22
#define LSb16padRing_ctrl_ODR_EN 6
#define bpadRing_ctrl_ODR_EN 1
#define MSK32padRing_ctrl_ODR_EN 0x00400000
#define BA_padRing_ctrl_ODR 0x0002
#define B16padRing_ctrl_ODR 0x0002
#define LSb32padRing_ctrl_ODR 23
#define LSb16padRing_ctrl_ODR 7
#define bpadRing_ctrl_ODR 3
#define MSK32padRing_ctrl_ODR 0x03800000
#define BA_padRing_ctrl_ZP_AFT_CAL 0x0003
#define B16padRing_ctrl_ZP_AFT_CAL 0x0002
#define LSb32padRing_ctrl_ZP_AFT_CAL 26
#define LSb16padRing_ctrl_ZP_AFT_CAL 10
#define bpadRing_ctrl_ZP_AFT_CAL 4
#define MSK32padRing_ctrl_ZP_AFT_CAL 0x3C000000
///////////////////////////////////////////////////////////
#define RA_padRing_status 0x0004
#define BA_padRing_status_CAL_P_INC 0x0004
#define B16padRing_status_CAL_P_INC 0x0004
#define LSb32padRing_status_CAL_P_INC 0
#define LSb16padRing_status_CAL_P_INC 0
#define bpadRing_status_CAL_P_INC 1
#define MSK32padRing_status_CAL_P_INC 0x00000001
#define BA_padRing_status_CAL_N_INC 0x0004
#define B16padRing_status_CAL_N_INC 0x0004
#define LSb32padRing_status_CAL_N_INC 1
#define LSb16padRing_status_CAL_N_INC 1
#define bpadRing_status_CAL_N_INC 1
#define MSK32padRing_status_CAL_N_INC 0x00000002
///////////////////////////////////////////////////////////
typedef struct SIE_padRing {
///////////////////////////////////////////////////////////
#define GET32padRing_ctrl_REG_PDB_CORE(r32) _BFGET_(r32, 0, 0)
#define SET32padRing_ctrl_REG_PDB_CORE(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16padRing_ctrl_REG_PDB_CORE(r16) _BFGET_(r16, 0, 0)
#define SET16padRing_ctrl_REG_PDB_CORE(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32padRing_ctrl_REF_INT_EN(r32) _BFGET_(r32, 1, 1)
#define SET32padRing_ctrl_REF_INT_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16padRing_ctrl_REF_INT_EN(r16) _BFGET_(r16, 1, 1)
#define SET16padRing_ctrl_REF_INT_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32padRing_ctrl_V18EN_CORE(r32) _BFGET_(r32, 2, 2)
#define SET32padRing_ctrl_V18EN_CORE(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16padRing_ctrl_V18EN_CORE(r16) _BFGET_(r16, 2, 2)
#define SET16padRing_ctrl_V18EN_CORE(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32padRing_ctrl_V25EN_CORE(r32) _BFGET_(r32, 3, 3)
#define SET32padRing_ctrl_V25EN_CORE(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16padRing_ctrl_V25EN_CORE(r16) _BFGET_(r16, 3, 3)
#define SET16padRing_ctrl_V25EN_CORE(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32padRing_ctrl_ZP(r32) _BFGET_(r32, 7, 4)
#define SET32padRing_ctrl_ZP(r32,v) _BFSET_(r32, 7, 4,v)
#define GET16padRing_ctrl_ZP(r16) _BFGET_(r16, 7, 4)
#define SET16padRing_ctrl_ZP(r16,v) _BFSET_(r16, 7, 4,v)
#define GET32padRing_ctrl_ZN(r32) _BFGET_(r32,11, 8)
#define SET32padRing_ctrl_ZN(r32,v) _BFSET_(r32,11, 8,v)
#define GET16padRing_ctrl_ZN(r16) _BFGET_(r16,11, 8)
#define SET16padRing_ctrl_ZN(r16,v) _BFSET_(r16,11, 8,v)
#define GET32padRing_ctrl_CAL_ZP(r32) _BFGET_(r32,15,12)
#define SET32padRing_ctrl_CAL_ZP(r32,v) _BFSET_(r32,15,12,v)
#define GET16padRing_ctrl_CAL_ZP(r16) _BFGET_(r16,15,12)
#define SET16padRing_ctrl_CAL_ZP(r16,v) _BFSET_(r16,15,12,v)
#define GET32padRing_ctrl_CAL_ZN(r32) _BFGET_(r32,19,16)
#define SET32padRing_ctrl_CAL_ZN(r32,v) _BFSET_(r32,19,16,v)
#define GET16padRing_ctrl_CAL_ZN(r16) _BFGET_(r16, 3, 0)
#define SET16padRing_ctrl_CAL_ZN(r16,v) _BFSET_(r16, 3, 0,v)
#define GET32padRing_ctrl_CAL_P_EN(r32) _BFGET_(r32,20,20)
#define SET32padRing_ctrl_CAL_P_EN(r32,v) _BFSET_(r32,20,20,v)
#define GET16padRing_ctrl_CAL_P_EN(r16) _BFGET_(r16, 4, 4)
#define SET16padRing_ctrl_CAL_P_EN(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32padRing_ctrl_CAL_N_EN(r32) _BFGET_(r32,21,21)
#define SET32padRing_ctrl_CAL_N_EN(r32,v) _BFSET_(r32,21,21,v)
#define GET16padRing_ctrl_CAL_N_EN(r16) _BFGET_(r16, 5, 5)
#define SET16padRing_ctrl_CAL_N_EN(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32padRing_ctrl_ODR_EN(r32) _BFGET_(r32,22,22)
#define SET32padRing_ctrl_ODR_EN(r32,v) _BFSET_(r32,22,22,v)
#define GET16padRing_ctrl_ODR_EN(r16) _BFGET_(r16, 6, 6)
#define SET16padRing_ctrl_ODR_EN(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32padRing_ctrl_ODR(r32) _BFGET_(r32,25,23)
#define SET32padRing_ctrl_ODR(r32,v) _BFSET_(r32,25,23,v)
#define GET16padRing_ctrl_ODR(r16) _BFGET_(r16, 9, 7)
#define SET16padRing_ctrl_ODR(r16,v) _BFSET_(r16, 9, 7,v)
#define GET32padRing_ctrl_ZP_AFT_CAL(r32) _BFGET_(r32,29,26)
#define SET32padRing_ctrl_ZP_AFT_CAL(r32,v) _BFSET_(r32,29,26,v)
#define GET16padRing_ctrl_ZP_AFT_CAL(r16) _BFGET_(r16,13,10)
#define SET16padRing_ctrl_ZP_AFT_CAL(r16,v) _BFSET_(r16,13,10,v)
#define w32padRing_ctrl {\
UNSG32 uctrl_REG_PDB_CORE : 1;\
UNSG32 uctrl_REF_INT_EN : 1;\
UNSG32 uctrl_V18EN_CORE : 1;\
UNSG32 uctrl_V25EN_CORE : 1;\
UNSG32 uctrl_ZP : 4;\
UNSG32 uctrl_ZN : 4;\
UNSG32 uctrl_CAL_ZP : 4;\
UNSG32 uctrl_CAL_ZN : 4;\
UNSG32 uctrl_CAL_P_EN : 1;\
UNSG32 uctrl_CAL_N_EN : 1;\
UNSG32 uctrl_ODR_EN : 1;\
UNSG32 uctrl_ODR : 3;\
UNSG32 uctrl_ZP_AFT_CAL : 4;\
UNSG32 RSVDx0_b30 : 2;\
}
union { UNSG32 u32padRing_ctrl;
struct w32padRing_ctrl;
};
///////////////////////////////////////////////////////////
#define GET32padRing_status_CAL_P_INC(r32) _BFGET_(r32, 0, 0)
#define SET32padRing_status_CAL_P_INC(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16padRing_status_CAL_P_INC(r16) _BFGET_(r16, 0, 0)
#define SET16padRing_status_CAL_P_INC(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32padRing_status_CAL_N_INC(r32) _BFGET_(r32, 1, 1)
#define SET32padRing_status_CAL_N_INC(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16padRing_status_CAL_N_INC(r16) _BFGET_(r16, 1, 1)
#define SET16padRing_status_CAL_N_INC(r16,v) _BFSET_(r16, 1, 1,v)
#define w32padRing_status {\
UNSG32 ustatus_CAL_P_INC : 1;\
UNSG32 ustatus_CAL_N_INC : 1;\
UNSG32 RSVDx4_b2 : 30;\
}
union { UNSG32 u32padRing_status;
struct w32padRing_status;
};
///////////////////////////////////////////////////////////
} SIE_padRing;
typedef union T32padRing_ctrl
{ UNSG32 u32;
struct w32padRing_ctrl;
} T32padRing_ctrl;
typedef union T32padRing_status
{ UNSG32 u32;
struct w32padRing_status;
} T32padRing_status;
///////////////////////////////////////////////////////////
typedef union TpadRing_ctrl
{ UNSG32 u32[1];
struct {
struct w32padRing_ctrl;
};
} TpadRing_ctrl;
typedef union TpadRing_status
{ UNSG32 u32[1];
struct {
struct w32padRing_status;
};
} TpadRing_status;
///////////////////////////////////////////////////////////
SIGN32 padRing_drvrd(SIE_padRing *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 padRing_drvwr(SIE_padRing *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void padRing_reset(SIE_padRing *p);
SIGN32 padRing_cmp (SIE_padRing *p, SIE_padRing *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define padRing_check(p,pie,pfx,hLOG) padRing_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define padRing_print(p, pfx,hLOG) padRing_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: padRing
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE padRingV18 (4,4)
/// ###
/// * Default voltage setting is 1.8V
/// ###
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (P-)
/// %unsigned 1 REG_PDB_CORE 0x1
/// : NORMAL 0x1
/// : PWRDN 0x0
/// ###
/// * When REG_PDB_CORE is logic '1', the regulator works in normal mode and consumes ~60uA current at typical 25degC. When REG_PDB_CORE is logic '0', the regulator works in power-down mode and consumes ~6uA current at typical 25degC.
/// ###
/// %unsigned 1 REF_INT_EN 0x1
/// : NORMAL 0x1
/// : REF_DOWN 0x0
/// ###
/// * When REF_INT_EN='1', REF/REF_FT is generated internally. When REF_INT_EN='0', the internal REF circuit is powered down and the REF signal is brought down to 0.
/// * Since we do not use HSIN pads in bg3, we do not use this setting.
/// ###
/// %unsigned 1 V18EN_CORE 0x1
/// %unsigned 1 V25EN_CORE 0x0
/// ###
/// * V18EN_CORE and V25EN_CORE are settings for different IO supply level
/// * V18EN_CORE=0,V25EN_CORE=0 : 3.3V
/// * V18EN_CORE=0,V25EN_CORE=1 : 2.5V
/// * V18EN_CORE=1,V25EN_CORE=X : 1.5V, 1.5V or 1.8V
/// ###
/// %unsigned 4 ZP 0x0
/// ###
/// * ZP[3:0] is used to program PMOS output driver strength for PADXDC_HSIOB. ZP[3:0]='1111' is the strongest setting.
/// ###
/// %unsigned 4 ZN 0x0
/// ###
/// * ZN[3:0] is used to program NMOS output driver strength for PADXDC_HSIOB. ZN[3:0]='1111' is the strongest setting.
/// ###
/// %unsigned 4 CAL_ZP 0x0
/// ###
/// * ZN / ZP signals for calibration pad.
/// * ZN / ZP signals of the output impedance calibration pad and the functional I/O pad should be separated.
/// ###
/// %unsigned 4 CAL_ZN 0x0
/// ###
/// * ZN / ZP signals for calibration pad.
/// * ZN / ZP signals of the output impedance calibration pad and the functional I/O pad should be separated.
/// ###
/// %unsigned 1 CAL_P_EN 0x0
/// ###
/// * CAL_P_EN is active high core signal. Needs to be asserted high to start the PMOS driver calibration
/// ###
/// %unsigned 1 CAL_N_EN 0x0
/// ###
/// * CAL_N_EN is active high core signal. Needs to be asserted high to start the NMOS driver calibration. PMOS driver has to be calibrated first, and ZP_AFT_CAL[3:0] need to be set to the calibrated PMOS settings before CAL_N_EN is asserted high
/// ###
/// %unsigned 1 ODR_EN 0x1
/// ###
/// * When off-chip resistor is used, please set ODR_EN=0. When internal resistor is used for calibration, please set ODR_EN=1 and choose a proper ODR[2:0] setting to achieve desired driver strength.
/// ###
/// %unsigned 3 ODR 0x0
/// ###
/// * ODR[2:0] is used to adjust the internal reference resistor value for calibration without external resistor. ODR_EN need to be set to '1' to enable internal resistor.
/// ###
/// %unsigned 4 ZP_AFT_CAL 0x0
/// ###
/// * ZP_AFT_CAL[3:0] are active high signals at the core signal level. They should be fed in by the registers that stores the settings after the PMOS driver calibration
/// ###
/// %% 2 # Stuffing bits...
/// @ 0x00004 status (R-)
/// %unsigned 1 CAL_P_INC
/// ###
/// * CAL_P_INC is the output of the comparator. When the pad voltage is lower than the internal reference voltage, CAL_P_INC is high (i.e. the output impedance of PMOS is higher than the desired impedance).
/// * In a calibration loop, CAL_P_INC high can be interpreted as a signal to increment ZP[3:0].
/// ###
/// %unsigned 1 CAL_N_INC
/// ###
/// * CAL_N_INC is the output of the comparator. When the pad voltage is higher than the internal reference voltage, CAL_N_INC is high (i.e. the output impedance of NMOS is higher than the desired impedance). In a calibration loop, CAL_N_INC high can be interpreted as a signal to increment ZN[3:0].
/// ###
/// %% 30 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 8B, bits: 32b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_padRingV18
#define h_padRingV18 (){}
#define RA_padRingV18_ctrl 0x0000
#define BA_padRingV18_ctrl_REG_PDB_CORE 0x0000
#define B16padRingV18_ctrl_REG_PDB_CORE 0x0000
#define LSb32padRingV18_ctrl_REG_PDB_CORE 0
#define LSb16padRingV18_ctrl_REG_PDB_CORE 0
#define bpadRingV18_ctrl_REG_PDB_CORE 1
#define MSK32padRingV18_ctrl_REG_PDB_CORE 0x00000001
#define padRingV18_ctrl_REG_PDB_CORE_NORMAL 0x1
#define padRingV18_ctrl_REG_PDB_CORE_PWRDN 0x0
#define BA_padRingV18_ctrl_REF_INT_EN 0x0000
#define B16padRingV18_ctrl_REF_INT_EN 0x0000
#define LSb32padRingV18_ctrl_REF_INT_EN 1
#define LSb16padRingV18_ctrl_REF_INT_EN 1
#define bpadRingV18_ctrl_REF_INT_EN 1
#define MSK32padRingV18_ctrl_REF_INT_EN 0x00000002
#define padRingV18_ctrl_REF_INT_EN_NORMAL 0x1
#define padRingV18_ctrl_REF_INT_EN_REF_DOWN 0x0
#define BA_padRingV18_ctrl_V18EN_CORE 0x0000
#define B16padRingV18_ctrl_V18EN_CORE 0x0000
#define LSb32padRingV18_ctrl_V18EN_CORE 2
#define LSb16padRingV18_ctrl_V18EN_CORE 2
#define bpadRingV18_ctrl_V18EN_CORE 1
#define MSK32padRingV18_ctrl_V18EN_CORE 0x00000004
#define BA_padRingV18_ctrl_V25EN_CORE 0x0000
#define B16padRingV18_ctrl_V25EN_CORE 0x0000
#define LSb32padRingV18_ctrl_V25EN_CORE 3
#define LSb16padRingV18_ctrl_V25EN_CORE 3
#define bpadRingV18_ctrl_V25EN_CORE 1
#define MSK32padRingV18_ctrl_V25EN_CORE 0x00000008
#define BA_padRingV18_ctrl_ZP 0x0000
#define B16padRingV18_ctrl_ZP 0x0000
#define LSb32padRingV18_ctrl_ZP 4
#define LSb16padRingV18_ctrl_ZP 4
#define bpadRingV18_ctrl_ZP 4
#define MSK32padRingV18_ctrl_ZP 0x000000F0
#define BA_padRingV18_ctrl_ZN 0x0001
#define B16padRingV18_ctrl_ZN 0x0000
#define LSb32padRingV18_ctrl_ZN 8
#define LSb16padRingV18_ctrl_ZN 8
#define bpadRingV18_ctrl_ZN 4
#define MSK32padRingV18_ctrl_ZN 0x00000F00
#define BA_padRingV18_ctrl_CAL_ZP 0x0001
#define B16padRingV18_ctrl_CAL_ZP 0x0000
#define LSb32padRingV18_ctrl_CAL_ZP 12
#define LSb16padRingV18_ctrl_CAL_ZP 12
#define bpadRingV18_ctrl_CAL_ZP 4
#define MSK32padRingV18_ctrl_CAL_ZP 0x0000F000
#define BA_padRingV18_ctrl_CAL_ZN 0x0002
#define B16padRingV18_ctrl_CAL_ZN 0x0002
#define LSb32padRingV18_ctrl_CAL_ZN 16
#define LSb16padRingV18_ctrl_CAL_ZN 0
#define bpadRingV18_ctrl_CAL_ZN 4
#define MSK32padRingV18_ctrl_CAL_ZN 0x000F0000
#define BA_padRingV18_ctrl_CAL_P_EN 0x0002
#define B16padRingV18_ctrl_CAL_P_EN 0x0002
#define LSb32padRingV18_ctrl_CAL_P_EN 20
#define LSb16padRingV18_ctrl_CAL_P_EN 4
#define bpadRingV18_ctrl_CAL_P_EN 1
#define MSK32padRingV18_ctrl_CAL_P_EN 0x00100000
#define BA_padRingV18_ctrl_CAL_N_EN 0x0002
#define B16padRingV18_ctrl_CAL_N_EN 0x0002
#define LSb32padRingV18_ctrl_CAL_N_EN 21
#define LSb16padRingV18_ctrl_CAL_N_EN 5
#define bpadRingV18_ctrl_CAL_N_EN 1
#define MSK32padRingV18_ctrl_CAL_N_EN 0x00200000
#define BA_padRingV18_ctrl_ODR_EN 0x0002
#define B16padRingV18_ctrl_ODR_EN 0x0002
#define LSb32padRingV18_ctrl_ODR_EN 22
#define LSb16padRingV18_ctrl_ODR_EN 6
#define bpadRingV18_ctrl_ODR_EN 1
#define MSK32padRingV18_ctrl_ODR_EN 0x00400000
#define BA_padRingV18_ctrl_ODR 0x0002
#define B16padRingV18_ctrl_ODR 0x0002
#define LSb32padRingV18_ctrl_ODR 23
#define LSb16padRingV18_ctrl_ODR 7
#define bpadRingV18_ctrl_ODR 3
#define MSK32padRingV18_ctrl_ODR 0x03800000
#define BA_padRingV18_ctrl_ZP_AFT_CAL 0x0003
#define B16padRingV18_ctrl_ZP_AFT_CAL 0x0002
#define LSb32padRingV18_ctrl_ZP_AFT_CAL 26
#define LSb16padRingV18_ctrl_ZP_AFT_CAL 10
#define bpadRingV18_ctrl_ZP_AFT_CAL 4
#define MSK32padRingV18_ctrl_ZP_AFT_CAL 0x3C000000
///////////////////////////////////////////////////////////
#define RA_padRingV18_status 0x0004
#define BA_padRingV18_status_CAL_P_INC 0x0004
#define B16padRingV18_status_CAL_P_INC 0x0004
#define LSb32padRingV18_status_CAL_P_INC 0
#define LSb16padRingV18_status_CAL_P_INC 0
#define bpadRingV18_status_CAL_P_INC 1
#define MSK32padRingV18_status_CAL_P_INC 0x00000001
#define BA_padRingV18_status_CAL_N_INC 0x0004
#define B16padRingV18_status_CAL_N_INC 0x0004
#define LSb32padRingV18_status_CAL_N_INC 1
#define LSb16padRingV18_status_CAL_N_INC 1
#define bpadRingV18_status_CAL_N_INC 1
#define MSK32padRingV18_status_CAL_N_INC 0x00000002
///////////////////////////////////////////////////////////
typedef struct SIE_padRingV18 {
///////////////////////////////////////////////////////////
#define GET32padRingV18_ctrl_REG_PDB_CORE(r32) _BFGET_(r32, 0, 0)
#define SET32padRingV18_ctrl_REG_PDB_CORE(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16padRingV18_ctrl_REG_PDB_CORE(r16) _BFGET_(r16, 0, 0)
#define SET16padRingV18_ctrl_REG_PDB_CORE(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32padRingV18_ctrl_REF_INT_EN(r32) _BFGET_(r32, 1, 1)
#define SET32padRingV18_ctrl_REF_INT_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16padRingV18_ctrl_REF_INT_EN(r16) _BFGET_(r16, 1, 1)
#define SET16padRingV18_ctrl_REF_INT_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32padRingV18_ctrl_V18EN_CORE(r32) _BFGET_(r32, 2, 2)
#define SET32padRingV18_ctrl_V18EN_CORE(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16padRingV18_ctrl_V18EN_CORE(r16) _BFGET_(r16, 2, 2)
#define SET16padRingV18_ctrl_V18EN_CORE(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32padRingV18_ctrl_V25EN_CORE(r32) _BFGET_(r32, 3, 3)
#define SET32padRingV18_ctrl_V25EN_CORE(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16padRingV18_ctrl_V25EN_CORE(r16) _BFGET_(r16, 3, 3)
#define SET16padRingV18_ctrl_V25EN_CORE(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32padRingV18_ctrl_ZP(r32) _BFGET_(r32, 7, 4)
#define SET32padRingV18_ctrl_ZP(r32,v) _BFSET_(r32, 7, 4,v)
#define GET16padRingV18_ctrl_ZP(r16) _BFGET_(r16, 7, 4)
#define SET16padRingV18_ctrl_ZP(r16,v) _BFSET_(r16, 7, 4,v)
#define GET32padRingV18_ctrl_ZN(r32) _BFGET_(r32,11, 8)
#define SET32padRingV18_ctrl_ZN(r32,v) _BFSET_(r32,11, 8,v)
#define GET16padRingV18_ctrl_ZN(r16) _BFGET_(r16,11, 8)
#define SET16padRingV18_ctrl_ZN(r16,v) _BFSET_(r16,11, 8,v)
#define GET32padRingV18_ctrl_CAL_ZP(r32) _BFGET_(r32,15,12)
#define SET32padRingV18_ctrl_CAL_ZP(r32,v) _BFSET_(r32,15,12,v)
#define GET16padRingV18_ctrl_CAL_ZP(r16) _BFGET_(r16,15,12)
#define SET16padRingV18_ctrl_CAL_ZP(r16,v) _BFSET_(r16,15,12,v)
#define GET32padRingV18_ctrl_CAL_ZN(r32) _BFGET_(r32,19,16)
#define SET32padRingV18_ctrl_CAL_ZN(r32,v) _BFSET_(r32,19,16,v)
#define GET16padRingV18_ctrl_CAL_ZN(r16) _BFGET_(r16, 3, 0)
#define SET16padRingV18_ctrl_CAL_ZN(r16,v) _BFSET_(r16, 3, 0,v)
#define GET32padRingV18_ctrl_CAL_P_EN(r32) _BFGET_(r32,20,20)
#define SET32padRingV18_ctrl_CAL_P_EN(r32,v) _BFSET_(r32,20,20,v)
#define GET16padRingV18_ctrl_CAL_P_EN(r16) _BFGET_(r16, 4, 4)
#define SET16padRingV18_ctrl_CAL_P_EN(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32padRingV18_ctrl_CAL_N_EN(r32) _BFGET_(r32,21,21)
#define SET32padRingV18_ctrl_CAL_N_EN(r32,v) _BFSET_(r32,21,21,v)
#define GET16padRingV18_ctrl_CAL_N_EN(r16) _BFGET_(r16, 5, 5)
#define SET16padRingV18_ctrl_CAL_N_EN(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32padRingV18_ctrl_ODR_EN(r32) _BFGET_(r32,22,22)
#define SET32padRingV18_ctrl_ODR_EN(r32,v) _BFSET_(r32,22,22,v)
#define GET16padRingV18_ctrl_ODR_EN(r16) _BFGET_(r16, 6, 6)
#define SET16padRingV18_ctrl_ODR_EN(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32padRingV18_ctrl_ODR(r32) _BFGET_(r32,25,23)
#define SET32padRingV18_ctrl_ODR(r32,v) _BFSET_(r32,25,23,v)
#define GET16padRingV18_ctrl_ODR(r16) _BFGET_(r16, 9, 7)
#define SET16padRingV18_ctrl_ODR(r16,v) _BFSET_(r16, 9, 7,v)
#define GET32padRingV18_ctrl_ZP_AFT_CAL(r32) _BFGET_(r32,29,26)
#define SET32padRingV18_ctrl_ZP_AFT_CAL(r32,v) _BFSET_(r32,29,26,v)
#define GET16padRingV18_ctrl_ZP_AFT_CAL(r16) _BFGET_(r16,13,10)
#define SET16padRingV18_ctrl_ZP_AFT_CAL(r16,v) _BFSET_(r16,13,10,v)
#define w32padRingV18_ctrl {\
UNSG32 uctrl_REG_PDB_CORE : 1;\
UNSG32 uctrl_REF_INT_EN : 1;\
UNSG32 uctrl_V18EN_CORE : 1;\
UNSG32 uctrl_V25EN_CORE : 1;\
UNSG32 uctrl_ZP : 4;\
UNSG32 uctrl_ZN : 4;\
UNSG32 uctrl_CAL_ZP : 4;\
UNSG32 uctrl_CAL_ZN : 4;\
UNSG32 uctrl_CAL_P_EN : 1;\
UNSG32 uctrl_CAL_N_EN : 1;\
UNSG32 uctrl_ODR_EN : 1;\
UNSG32 uctrl_ODR : 3;\
UNSG32 uctrl_ZP_AFT_CAL : 4;\
UNSG32 RSVDx0_b30 : 2;\
}
union { UNSG32 u32padRingV18_ctrl;
struct w32padRingV18_ctrl;
};
///////////////////////////////////////////////////////////
#define GET32padRingV18_status_CAL_P_INC(r32) _BFGET_(r32, 0, 0)
#define SET32padRingV18_status_CAL_P_INC(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16padRingV18_status_CAL_P_INC(r16) _BFGET_(r16, 0, 0)
#define SET16padRingV18_status_CAL_P_INC(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32padRingV18_status_CAL_N_INC(r32) _BFGET_(r32, 1, 1)
#define SET32padRingV18_status_CAL_N_INC(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16padRingV18_status_CAL_N_INC(r16) _BFGET_(r16, 1, 1)
#define SET16padRingV18_status_CAL_N_INC(r16,v) _BFSET_(r16, 1, 1,v)
#define w32padRingV18_status {\
UNSG32 ustatus_CAL_P_INC : 1;\
UNSG32 ustatus_CAL_N_INC : 1;\
UNSG32 RSVDx4_b2 : 30;\
}
union { UNSG32 u32padRingV18_status;
struct w32padRingV18_status;
};
///////////////////////////////////////////////////////////
} SIE_padRingV18;
typedef union T32padRingV18_ctrl
{ UNSG32 u32;
struct w32padRingV18_ctrl;
} T32padRingV18_ctrl;
typedef union T32padRingV18_status
{ UNSG32 u32;
struct w32padRingV18_status;
} T32padRingV18_status;
///////////////////////////////////////////////////////////
typedef union TpadRingV18_ctrl
{ UNSG32 u32[1];
struct {
struct w32padRingV18_ctrl;
};
} TpadRingV18_ctrl;
typedef union TpadRingV18_status
{ UNSG32 u32[1];
struct {
struct w32padRingV18_status;
};
} TpadRingV18_status;
///////////////////////////////////////////////////////////
SIGN32 padRingV18_drvrd(SIE_padRingV18 *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 padRingV18_drvwr(SIE_padRingV18 *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void padRingV18_reset(SIE_padRingV18 *p);
SIGN32 padRingV18_cmp (SIE_padRingV18 *p, SIE_padRingV18 *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define padRingV18_check(p,pie,pfx,hLOG) padRingV18_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define padRingV18_print(p, pfx,hLOG) padRingV18_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: padRingV18
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE HSpadRing (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (P-)
/// %unsigned 1 V12EN 0x0
/// ###
/// * V12_EN=0 is for 1.8V normal mode, V12_EN=1 is to enable 1.2V high-speed mode.
/// * At 1.8V (V12_EN=0), DIO12OB pad performance is similar to DIOB.
/// ###
/// %unsigned 5 ZP 0x1F
/// ###
/// * ZP[4:0] is used to program PMOS output driver strength for PAD18DIOB.
/// * 50 Ohm driver (lower speed ~100MHz)
/// * 01111: TYP CORNER
/// * 10101: SLOW CORNER
/// * 01011: FAST CORNER
/// * 33 Ohm driver (strong driver for high-speed ~200MHz)
/// * 10111: TYP CORNER
/// * 11111: SLOW CORNER
/// * 10000: FAST CORNER
/// ###
/// %unsigned 5 ZN 0x1F
/// ###
/// * ZN[4:0] is used to program NMOS output driver strength for PAD18DIOB.
/// * 50 Ohm driver (lower speed ~100MHz)
/// * 01111: TYP CORNER
/// * 10101: SLOW CORNER
/// * 01011: FAST CORNER
/// * 33 Ohm driver (strong driver for high-speed ~200MHz)
/// * 10111: TYP CORNER
/// * 11111: SLOW CORNER
/// * 10000: FAST CORNER
/// ###
/// %% 21 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 4B, bits: 11b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_HSpadRing
#define h_HSpadRing (){}
#define RA_HSpadRing_ctrl 0x0000
#define BA_HSpadRing_ctrl_V12EN 0x0000
#define B16HSpadRing_ctrl_V12EN 0x0000
#define LSb32HSpadRing_ctrl_V12EN 0
#define LSb16HSpadRing_ctrl_V12EN 0
#define bHSpadRing_ctrl_V12EN 1
#define MSK32HSpadRing_ctrl_V12EN 0x00000001
#define BA_HSpadRing_ctrl_ZP 0x0000
#define B16HSpadRing_ctrl_ZP 0x0000
#define LSb32HSpadRing_ctrl_ZP 1
#define LSb16HSpadRing_ctrl_ZP 1
#define bHSpadRing_ctrl_ZP 5
#define MSK32HSpadRing_ctrl_ZP 0x0000003E
#define BA_HSpadRing_ctrl_ZN 0x0000
#define B16HSpadRing_ctrl_ZN 0x0000
#define LSb32HSpadRing_ctrl_ZN 6
#define LSb16HSpadRing_ctrl_ZN 6
#define bHSpadRing_ctrl_ZN 5
#define MSK32HSpadRing_ctrl_ZN 0x000007C0
///////////////////////////////////////////////////////////
typedef struct SIE_HSpadRing {
///////////////////////////////////////////////////////////
#define GET32HSpadRing_ctrl_V12EN(r32) _BFGET_(r32, 0, 0)
#define SET32HSpadRing_ctrl_V12EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16HSpadRing_ctrl_V12EN(r16) _BFGET_(r16, 0, 0)
#define SET16HSpadRing_ctrl_V12EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32HSpadRing_ctrl_ZP(r32) _BFGET_(r32, 5, 1)
#define SET32HSpadRing_ctrl_ZP(r32,v) _BFSET_(r32, 5, 1,v)
#define GET16HSpadRing_ctrl_ZP(r16) _BFGET_(r16, 5, 1)
#define SET16HSpadRing_ctrl_ZP(r16,v) _BFSET_(r16, 5, 1,v)
#define GET32HSpadRing_ctrl_ZN(r32) _BFGET_(r32,10, 6)
#define SET32HSpadRing_ctrl_ZN(r32,v) _BFSET_(r32,10, 6,v)
#define GET16HSpadRing_ctrl_ZN(r16) _BFGET_(r16,10, 6)
#define SET16HSpadRing_ctrl_ZN(r16,v) _BFSET_(r16,10, 6,v)
#define w32HSpadRing_ctrl {\
UNSG32 uctrl_V12EN : 1;\
UNSG32 uctrl_ZP : 5;\
UNSG32 uctrl_ZN : 5;\
UNSG32 RSVDx0_b11 : 21;\
}
union { UNSG32 u32HSpadRing_ctrl;
struct w32HSpadRing_ctrl;
};
///////////////////////////////////////////////////////////
} SIE_HSpadRing;
typedef union T32HSpadRing_ctrl
{ UNSG32 u32;
struct w32HSpadRing_ctrl;
} T32HSpadRing_ctrl;
///////////////////////////////////////////////////////////
typedef union THSpadRing_ctrl
{ UNSG32 u32[1];
struct {
struct w32HSpadRing_ctrl;
};
} THSpadRing_ctrl;
///////////////////////////////////////////////////////////
SIGN32 HSpadRing_drvrd(SIE_HSpadRing *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 HSpadRing_drvwr(SIE_HSpadRing *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void HSpadRing_reset(SIE_HSpadRing *p);
SIGN32 HSpadRing_cmp (SIE_HSpadRing *p, SIE_HSpadRing *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define HSpadRing_check(p,pie,pfx,hLOG) HSpadRing_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define HSpadRing_print(p, pfx,hLOG) HSpadRing_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: HSpadRing
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE FLpadRing (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (P-)
/// %unsigned 1 REG_PDB_CORE 0x0
/// ###
/// * Active low signal to place pads in power-down mode by driving ring signal LOW_VDDB_R = 0 PDB_CORE = 0, power-down
/// * PDB_CORE = 1, normal mode
/// ###
/// %unsigned 2 ODT_EN 0x0
/// ###
/// * Active high, controls / enables the on-die termination for signal pads. Do Not Scan
/// * 00 - ODT off
/// * 01 - 150ohm ODT
/// * 10 - 75ohm ODT
/// * 11 - 50ohm ODT
/// ###
/// %unsigned 5 ZP 0xF
/// ###
/// * Active high, controls the output driver pull-up network driving strength by selecting proper number of PMOS fingers to be turned on (All 0s = no fingers = tri-stated). Do Not Scan
/// ###
/// %unsigned 5 ZN 0xF
/// ###
/// * Active high, controls the output driver pull-down network driving strength by selecting proper number of NMOS fingers to be turned on (All 0s = no fingers = tri-stated). Do Not Scan
/// ###
/// %% 19 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 4B, bits: 13b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_FLpadRing
#define h_FLpadRing (){}
#define RA_FLpadRing_ctrl 0x0000
#define BA_FLpadRing_ctrl_REG_PDB_CORE 0x0000
#define B16FLpadRing_ctrl_REG_PDB_CORE 0x0000
#define LSb32FLpadRing_ctrl_REG_PDB_CORE 0
#define LSb16FLpadRing_ctrl_REG_PDB_CORE 0
#define bFLpadRing_ctrl_REG_PDB_CORE 1
#define MSK32FLpadRing_ctrl_REG_PDB_CORE 0x00000001
#define BA_FLpadRing_ctrl_ODT_EN 0x0000
#define B16FLpadRing_ctrl_ODT_EN 0x0000
#define LSb32FLpadRing_ctrl_ODT_EN 1
#define LSb16FLpadRing_ctrl_ODT_EN 1
#define bFLpadRing_ctrl_ODT_EN 2
#define MSK32FLpadRing_ctrl_ODT_EN 0x00000006
#define BA_FLpadRing_ctrl_ZP 0x0000
#define B16FLpadRing_ctrl_ZP 0x0000
#define LSb32FLpadRing_ctrl_ZP 3
#define LSb16FLpadRing_ctrl_ZP 3
#define bFLpadRing_ctrl_ZP 5
#define MSK32FLpadRing_ctrl_ZP 0x000000F8
#define BA_FLpadRing_ctrl_ZN 0x0001
#define B16FLpadRing_ctrl_ZN 0x0000
#define LSb32FLpadRing_ctrl_ZN 8
#define LSb16FLpadRing_ctrl_ZN 8
#define bFLpadRing_ctrl_ZN 5
#define MSK32FLpadRing_ctrl_ZN 0x00001F00
///////////////////////////////////////////////////////////
typedef struct SIE_FLpadRing {
///////////////////////////////////////////////////////////
#define GET32FLpadRing_ctrl_REG_PDB_CORE(r32) _BFGET_(r32, 0, 0)
#define SET32FLpadRing_ctrl_REG_PDB_CORE(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16FLpadRing_ctrl_REG_PDB_CORE(r16) _BFGET_(r16, 0, 0)
#define SET16FLpadRing_ctrl_REG_PDB_CORE(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32FLpadRing_ctrl_ODT_EN(r32) _BFGET_(r32, 2, 1)
#define SET32FLpadRing_ctrl_ODT_EN(r32,v) _BFSET_(r32, 2, 1,v)
#define GET16FLpadRing_ctrl_ODT_EN(r16) _BFGET_(r16, 2, 1)
#define SET16FLpadRing_ctrl_ODT_EN(r16,v) _BFSET_(r16, 2, 1,v)
#define GET32FLpadRing_ctrl_ZP(r32) _BFGET_(r32, 7, 3)
#define SET32FLpadRing_ctrl_ZP(r32,v) _BFSET_(r32, 7, 3,v)
#define GET16FLpadRing_ctrl_ZP(r16) _BFGET_(r16, 7, 3)
#define SET16FLpadRing_ctrl_ZP(r16,v) _BFSET_(r16, 7, 3,v)
#define GET32FLpadRing_ctrl_ZN(r32) _BFGET_(r32,12, 8)
#define SET32FLpadRing_ctrl_ZN(r32,v) _BFSET_(r32,12, 8,v)
#define GET16FLpadRing_ctrl_ZN(r16) _BFGET_(r16,12, 8)
#define SET16FLpadRing_ctrl_ZN(r16,v) _BFSET_(r16,12, 8,v)
#define w32FLpadRing_ctrl {\
UNSG32 uctrl_REG_PDB_CORE : 1;\
UNSG32 uctrl_ODT_EN : 2;\
UNSG32 uctrl_ZP : 5;\
UNSG32 uctrl_ZN : 5;\
UNSG32 RSVDx0_b13 : 19;\
}
union { UNSG32 u32FLpadRing_ctrl;
struct w32FLpadRing_ctrl;
};
///////////////////////////////////////////////////////////
} SIE_FLpadRing;
typedef union T32FLpadRing_ctrl
{ UNSG32 u32;
struct w32FLpadRing_ctrl;
} T32FLpadRing_ctrl;
///////////////////////////////////////////////////////////
typedef union TFLpadRing_ctrl
{ UNSG32 u32[1];
struct {
struct w32FLpadRing_ctrl;
};
} TFLpadRing_ctrl;
///////////////////////////////////////////////////////////
SIGN32 FLpadRing_drvrd(SIE_FLpadRing *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 FLpadRing_drvwr(SIE_FLpadRing *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void FLpadRing_reset(SIE_FLpadRing *p);
SIGN32 FLpadRing_cmp (SIE_FLpadRing *p, SIE_FLpadRing *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define FLpadRing_check(p,pie,pfx,hLOG) FLpadRing_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define FLpadRing_print(p, pfx,hLOG) FLpadRing_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: FLpadRing
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE EMMC_PHY_PAD (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (P-)
/// %unsigned 1 PWRDN 0x0
/// ###
/// * 0:Normal use
/// * 1: tristate pad and turn off termination
/// ###
/// %unsigned 1 PU 0x0
/// ###
/// * 0: Disable Pullup for DQ
/// * 1: Enable Pullup for DQ
/// ###
/// %unsigned 1 PD 0x0
/// ###
/// * 0: Disable Pulldown for DQ
/// * 1; Enable Pulldown for DQ
/// ###
/// %unsigned 1 RECEN 0x1
/// ###
/// * 0:disable receiver for DQ
/// * 1: enable receiver for DQ
/// ###
/// %unsigned 1 RCVTYPE 0x1
/// ###
/// * 0: differential receiver
/// * 1: CMOS receiver
/// ###
/// %% 27 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 4B, bits: 5b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_EMMC_PHY_PAD
#define h_EMMC_PHY_PAD (){}
#define RA_EMMC_PHY_PAD_ctrl 0x0000
#define BA_EMMC_PHY_PAD_ctrl_PWRDN 0x0000
#define B16EMMC_PHY_PAD_ctrl_PWRDN 0x0000
#define LSb32EMMC_PHY_PAD_ctrl_PWRDN 0
#define LSb16EMMC_PHY_PAD_ctrl_PWRDN 0
#define bEMMC_PHY_PAD_ctrl_PWRDN 1
#define MSK32EMMC_PHY_PAD_ctrl_PWRDN 0x00000001
#define BA_EMMC_PHY_PAD_ctrl_PU 0x0000
#define B16EMMC_PHY_PAD_ctrl_PU 0x0000
#define LSb32EMMC_PHY_PAD_ctrl_PU 1
#define LSb16EMMC_PHY_PAD_ctrl_PU 1
#define bEMMC_PHY_PAD_ctrl_PU 1
#define MSK32EMMC_PHY_PAD_ctrl_PU 0x00000002
#define BA_EMMC_PHY_PAD_ctrl_PD 0x0000
#define B16EMMC_PHY_PAD_ctrl_PD 0x0000
#define LSb32EMMC_PHY_PAD_ctrl_PD 2
#define LSb16EMMC_PHY_PAD_ctrl_PD 2
#define bEMMC_PHY_PAD_ctrl_PD 1
#define MSK32EMMC_PHY_PAD_ctrl_PD 0x00000004
#define BA_EMMC_PHY_PAD_ctrl_RECEN 0x0000
#define B16EMMC_PHY_PAD_ctrl_RECEN 0x0000
#define LSb32EMMC_PHY_PAD_ctrl_RECEN 3
#define LSb16EMMC_PHY_PAD_ctrl_RECEN 3
#define bEMMC_PHY_PAD_ctrl_RECEN 1
#define MSK32EMMC_PHY_PAD_ctrl_RECEN 0x00000008
#define BA_EMMC_PHY_PAD_ctrl_RCVTYPE 0x0000
#define B16EMMC_PHY_PAD_ctrl_RCVTYPE 0x0000
#define LSb32EMMC_PHY_PAD_ctrl_RCVTYPE 4
#define LSb16EMMC_PHY_PAD_ctrl_RCVTYPE 4
#define bEMMC_PHY_PAD_ctrl_RCVTYPE 1
#define MSK32EMMC_PHY_PAD_ctrl_RCVTYPE 0x00000010
///////////////////////////////////////////////////////////
typedef struct SIE_EMMC_PHY_PAD {
///////////////////////////////////////////////////////////
#define GET32EMMC_PHY_PAD_ctrl_PWRDN(r32) _BFGET_(r32, 0, 0)
#define SET32EMMC_PHY_PAD_ctrl_PWRDN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16EMMC_PHY_PAD_ctrl_PWRDN(r16) _BFGET_(r16, 0, 0)
#define SET16EMMC_PHY_PAD_ctrl_PWRDN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32EMMC_PHY_PAD_ctrl_PU(r32) _BFGET_(r32, 1, 1)
#define SET32EMMC_PHY_PAD_ctrl_PU(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16EMMC_PHY_PAD_ctrl_PU(r16) _BFGET_(r16, 1, 1)
#define SET16EMMC_PHY_PAD_ctrl_PU(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32EMMC_PHY_PAD_ctrl_PD(r32) _BFGET_(r32, 2, 2)
#define SET32EMMC_PHY_PAD_ctrl_PD(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16EMMC_PHY_PAD_ctrl_PD(r16) _BFGET_(r16, 2, 2)
#define SET16EMMC_PHY_PAD_ctrl_PD(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32EMMC_PHY_PAD_ctrl_RECEN(r32) _BFGET_(r32, 3, 3)
#define SET32EMMC_PHY_PAD_ctrl_RECEN(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16EMMC_PHY_PAD_ctrl_RECEN(r16) _BFGET_(r16, 3, 3)
#define SET16EMMC_PHY_PAD_ctrl_RECEN(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32EMMC_PHY_PAD_ctrl_RCVTYPE(r32) _BFGET_(r32, 4, 4)
#define SET32EMMC_PHY_PAD_ctrl_RCVTYPE(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16EMMC_PHY_PAD_ctrl_RCVTYPE(r16) _BFGET_(r16, 4, 4)
#define SET16EMMC_PHY_PAD_ctrl_RCVTYPE(r16,v) _BFSET_(r16, 4, 4,v)
#define w32EMMC_PHY_PAD_ctrl {\
UNSG32 uctrl_PWRDN : 1;\
UNSG32 uctrl_PU : 1;\
UNSG32 uctrl_PD : 1;\
UNSG32 uctrl_RECEN : 1;\
UNSG32 uctrl_RCVTYPE : 1;\
UNSG32 RSVDx0_b5 : 27;\
}
union { UNSG32 u32EMMC_PHY_PAD_ctrl;
struct w32EMMC_PHY_PAD_ctrl;
};
///////////////////////////////////////////////////////////
} SIE_EMMC_PHY_PAD;
typedef union T32EMMC_PHY_PAD_ctrl
{ UNSG32 u32;
struct w32EMMC_PHY_PAD_ctrl;
} T32EMMC_PHY_PAD_ctrl;
///////////////////////////////////////////////////////////
typedef union TEMMC_PHY_PAD_ctrl
{ UNSG32 u32[1];
struct {
struct w32EMMC_PHY_PAD_ctrl;
};
} TEMMC_PHY_PAD_ctrl;
///////////////////////////////////////////////////////////
SIGN32 EMMC_PHY_PAD_drvrd(SIE_EMMC_PHY_PAD *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 EMMC_PHY_PAD_drvwr(SIE_EMMC_PHY_PAD *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void EMMC_PHY_PAD_reset(SIE_EMMC_PHY_PAD *p);
SIGN32 EMMC_PHY_PAD_cmp (SIE_EMMC_PHY_PAD *p, SIE_EMMC_PHY_PAD *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define EMMC_PHY_PAD_check(p,pie,pfx,hLOG) EMMC_PHY_PAD_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define EMMC_PHY_PAD_print(p, pfx,hLOG) EMMC_PHY_PAD_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: EMMC_PHY_PAD
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE EMMC_DRVCNTL (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (P-)
/// %unsigned 1 ODT_SEL0 0x0
/// ###
/// * On Die Termination
/// ###
/// %unsigned 1 ODT_SEL1 0x0
/// ###
/// * On Die Termination
/// ###
/// %unsigned 5 ZPR 0x1F
/// ###
/// * P Driver Per-finger drive strength. Controls the P-side output drive strength.
/// ###
/// %unsigned 5 ZNR 0x1F
/// ###
/// * N Driver Per-finger drive strenth. Controls the N-side output drive strength.
/// ###
/// %unsigned 1 ZD 0x1
/// ###
/// * Reserved
/// ###
/// %% 19 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 4B, bits: 13b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_EMMC_DRVCNTL
#define h_EMMC_DRVCNTL (){}
#define RA_EMMC_DRVCNTL_ctrl 0x0000
#define BA_EMMC_DRVCNTL_ctrl_ODT_SEL0 0x0000
#define B16EMMC_DRVCNTL_ctrl_ODT_SEL0 0x0000
#define LSb32EMMC_DRVCNTL_ctrl_ODT_SEL0 0
#define LSb16EMMC_DRVCNTL_ctrl_ODT_SEL0 0
#define bEMMC_DRVCNTL_ctrl_ODT_SEL0 1
#define MSK32EMMC_DRVCNTL_ctrl_ODT_SEL0 0x00000001
#define BA_EMMC_DRVCNTL_ctrl_ODT_SEL1 0x0000
#define B16EMMC_DRVCNTL_ctrl_ODT_SEL1 0x0000
#define LSb32EMMC_DRVCNTL_ctrl_ODT_SEL1 1
#define LSb16EMMC_DRVCNTL_ctrl_ODT_SEL1 1
#define bEMMC_DRVCNTL_ctrl_ODT_SEL1 1
#define MSK32EMMC_DRVCNTL_ctrl_ODT_SEL1 0x00000002
#define BA_EMMC_DRVCNTL_ctrl_ZPR 0x0000
#define B16EMMC_DRVCNTL_ctrl_ZPR 0x0000
#define LSb32EMMC_DRVCNTL_ctrl_ZPR 2
#define LSb16EMMC_DRVCNTL_ctrl_ZPR 2
#define bEMMC_DRVCNTL_ctrl_ZPR 5
#define MSK32EMMC_DRVCNTL_ctrl_ZPR 0x0000007C
#define BA_EMMC_DRVCNTL_ctrl_ZNR 0x0000
#define B16EMMC_DRVCNTL_ctrl_ZNR 0x0000
#define LSb32EMMC_DRVCNTL_ctrl_ZNR 7
#define LSb16EMMC_DRVCNTL_ctrl_ZNR 7
#define bEMMC_DRVCNTL_ctrl_ZNR 5
#define MSK32EMMC_DRVCNTL_ctrl_ZNR 0x00000F80
#define BA_EMMC_DRVCNTL_ctrl_ZD 0x0001
#define B16EMMC_DRVCNTL_ctrl_ZD 0x0000
#define LSb32EMMC_DRVCNTL_ctrl_ZD 12
#define LSb16EMMC_DRVCNTL_ctrl_ZD 12
#define bEMMC_DRVCNTL_ctrl_ZD 1
#define MSK32EMMC_DRVCNTL_ctrl_ZD 0x00001000
///////////////////////////////////////////////////////////
typedef struct SIE_EMMC_DRVCNTL {
///////////////////////////////////////////////////////////
#define GET32EMMC_DRVCNTL_ctrl_ODT_SEL0(r32) _BFGET_(r32, 0, 0)
#define SET32EMMC_DRVCNTL_ctrl_ODT_SEL0(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16EMMC_DRVCNTL_ctrl_ODT_SEL0(r16) _BFGET_(r16, 0, 0)
#define SET16EMMC_DRVCNTL_ctrl_ODT_SEL0(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32EMMC_DRVCNTL_ctrl_ODT_SEL1(r32) _BFGET_(r32, 1, 1)
#define SET32EMMC_DRVCNTL_ctrl_ODT_SEL1(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16EMMC_DRVCNTL_ctrl_ODT_SEL1(r16) _BFGET_(r16, 1, 1)
#define SET16EMMC_DRVCNTL_ctrl_ODT_SEL1(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32EMMC_DRVCNTL_ctrl_ZPR(r32) _BFGET_(r32, 6, 2)
#define SET32EMMC_DRVCNTL_ctrl_ZPR(r32,v) _BFSET_(r32, 6, 2,v)
#define GET16EMMC_DRVCNTL_ctrl_ZPR(r16) _BFGET_(r16, 6, 2)
#define SET16EMMC_DRVCNTL_ctrl_ZPR(r16,v) _BFSET_(r16, 6, 2,v)
#define GET32EMMC_DRVCNTL_ctrl_ZNR(r32) _BFGET_(r32,11, 7)
#define SET32EMMC_DRVCNTL_ctrl_ZNR(r32,v) _BFSET_(r32,11, 7,v)
#define GET16EMMC_DRVCNTL_ctrl_ZNR(r16) _BFGET_(r16,11, 7)
#define SET16EMMC_DRVCNTL_ctrl_ZNR(r16,v) _BFSET_(r16,11, 7,v)
#define GET32EMMC_DRVCNTL_ctrl_ZD(r32) _BFGET_(r32,12,12)
#define SET32EMMC_DRVCNTL_ctrl_ZD(r32,v) _BFSET_(r32,12,12,v)
#define GET16EMMC_DRVCNTL_ctrl_ZD(r16) _BFGET_(r16,12,12)
#define SET16EMMC_DRVCNTL_ctrl_ZD(r16,v) _BFSET_(r16,12,12,v)
#define w32EMMC_DRVCNTL_ctrl {\
UNSG32 uctrl_ODT_SEL0 : 1;\
UNSG32 uctrl_ODT_SEL1 : 1;\
UNSG32 uctrl_ZPR : 5;\
UNSG32 uctrl_ZNR : 5;\
UNSG32 uctrl_ZD : 1;\
UNSG32 RSVDx0_b13 : 19;\
}
union { UNSG32 u32EMMC_DRVCNTL_ctrl;
struct w32EMMC_DRVCNTL_ctrl;
};
///////////////////////////////////////////////////////////
} SIE_EMMC_DRVCNTL;
typedef union T32EMMC_DRVCNTL_ctrl
{ UNSG32 u32;
struct w32EMMC_DRVCNTL_ctrl;
} T32EMMC_DRVCNTL_ctrl;
///////////////////////////////////////////////////////////
typedef union TEMMC_DRVCNTL_ctrl
{ UNSG32 u32[1];
struct {
struct w32EMMC_DRVCNTL_ctrl;
};
} TEMMC_DRVCNTL_ctrl;
///////////////////////////////////////////////////////////
SIGN32 EMMC_DRVCNTL_drvrd(SIE_EMMC_DRVCNTL *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 EMMC_DRVCNTL_drvwr(SIE_EMMC_DRVCNTL *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void EMMC_DRVCNTL_reset(SIE_EMMC_DRVCNTL *p);
SIGN32 EMMC_DRVCNTL_cmp (SIE_EMMC_DRVCNTL *p, SIE_EMMC_DRVCNTL *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define EMMC_DRVCNTL_check(p,pie,pfx,hLOG) EMMC_DRVCNTL_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define EMMC_DRVCNTL_print(p, pfx,hLOG) EMMC_DRVCNTL_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: EMMC_DRVCNTL
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE EMMCS28_PAD (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 ctrl (P-)
/// %unsigned 1 REG_PDB_CORE 0x1
/// ###
/// * 0: PWRDN
/// * 1: NORMAL
/// * When REG_PDB_CORE is logic “1”, the regulator works in normal mode and consumes ~60uA current at typical 25degC. When REG_PDB_CORE is logic “0”, the regulator works in power-down mode and consumes ~6uA current at typical 25degC.
/// ###
/// %unsigned 1 V18EN_CORE 0x0
/// %unsigned 1 V25EN_CORE 0x0
/// ###
/// * V18EN_CORE and V25EN_CORE are settings for different IO supply level.
/// * V18EN_CORE=0, V25EN-CORE=0: 3.3V
/// * V18EN_CORE=0,V25EN_CORE=1: 2.5V
/// * V18EN_CORE=1,V25EN_CORE=X: 1.5V, 1.5V or 1.8V.
/// ###
/// %unsigned 5 ZP 0x1F
/// ###
/// * ZP[3:0] is used to program PMOS output driver strength for PADXDC_HSIOB.
/// * ZP[3:0] = “1111” is the strongest setting.
/// ###
/// %unsigned 5 ZN 0x1F
/// ###
/// * ZN[3:0] is used to program NMOS output driver strength for PADXDC_HSIOB.
/// * ZN[3:0] = “1111” is the strongest setting.
/// ###
/// %unsigned 1 PDB_CORE 0x1
/// ###
/// * Active low signal to place pads in power-down mode by driving ring signal LOW_VDDB_R=0;
/// * 0: power-down
/// * 1: normal mode
/// * This signal is not to be mistaken with REG_PDB_CORE. REG_PDB_CORE is to power-down the regulator and make all signal pads tristated.
/// ###
/// %% 18 # Stuffing bits...
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 4B, bits: 14b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_EMMCS28_PAD
#define h_EMMCS28_PAD (){}
#define RA_EMMCS28_PAD_ctrl 0x0000
#define BA_EMMCS28_PAD_ctrl_REG_PDB_CORE 0x0000
#define B16EMMCS28_PAD_ctrl_REG_PDB_CORE 0x0000
#define LSb32EMMCS28_PAD_ctrl_REG_PDB_CORE 0
#define LSb16EMMCS28_PAD_ctrl_REG_PDB_CORE 0
#define bEMMCS28_PAD_ctrl_REG_PDB_CORE 1
#define MSK32EMMCS28_PAD_ctrl_REG_PDB_CORE 0x00000001
#define BA_EMMCS28_PAD_ctrl_V18EN_CORE 0x0000
#define B16EMMCS28_PAD_ctrl_V18EN_CORE 0x0000
#define LSb32EMMCS28_PAD_ctrl_V18EN_CORE 1
#define LSb16EMMCS28_PAD_ctrl_V18EN_CORE 1
#define bEMMCS28_PAD_ctrl_V18EN_CORE 1
#define MSK32EMMCS28_PAD_ctrl_V18EN_CORE 0x00000002
#define BA_EMMCS28_PAD_ctrl_V25EN_CORE 0x0000
#define B16EMMCS28_PAD_ctrl_V25EN_CORE 0x0000
#define LSb32EMMCS28_PAD_ctrl_V25EN_CORE 2
#define LSb16EMMCS28_PAD_ctrl_V25EN_CORE 2
#define bEMMCS28_PAD_ctrl_V25EN_CORE 1
#define MSK32EMMCS28_PAD_ctrl_V25EN_CORE 0x00000004
#define BA_EMMCS28_PAD_ctrl_ZP 0x0000
#define B16EMMCS28_PAD_ctrl_ZP 0x0000
#define LSb32EMMCS28_PAD_ctrl_ZP 3
#define LSb16EMMCS28_PAD_ctrl_ZP 3
#define bEMMCS28_PAD_ctrl_ZP 5
#define MSK32EMMCS28_PAD_ctrl_ZP 0x000000F8
#define BA_EMMCS28_PAD_ctrl_ZN 0x0001
#define B16EMMCS28_PAD_ctrl_ZN 0x0000
#define LSb32EMMCS28_PAD_ctrl_ZN 8
#define LSb16EMMCS28_PAD_ctrl_ZN 8
#define bEMMCS28_PAD_ctrl_ZN 5
#define MSK32EMMCS28_PAD_ctrl_ZN 0x00001F00
#define BA_EMMCS28_PAD_ctrl_PDB_CORE 0x0001
#define B16EMMCS28_PAD_ctrl_PDB_CORE 0x0000
#define LSb32EMMCS28_PAD_ctrl_PDB_CORE 13
#define LSb16EMMCS28_PAD_ctrl_PDB_CORE 13
#define bEMMCS28_PAD_ctrl_PDB_CORE 1
#define MSK32EMMCS28_PAD_ctrl_PDB_CORE 0x00002000
///////////////////////////////////////////////////////////
typedef struct SIE_EMMCS28_PAD {
///////////////////////////////////////////////////////////
#define GET32EMMCS28_PAD_ctrl_REG_PDB_CORE(r32) _BFGET_(r32, 0, 0)
#define SET32EMMCS28_PAD_ctrl_REG_PDB_CORE(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16EMMCS28_PAD_ctrl_REG_PDB_CORE(r16) _BFGET_(r16, 0, 0)
#define SET16EMMCS28_PAD_ctrl_REG_PDB_CORE(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32EMMCS28_PAD_ctrl_V18EN_CORE(r32) _BFGET_(r32, 1, 1)
#define SET32EMMCS28_PAD_ctrl_V18EN_CORE(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16EMMCS28_PAD_ctrl_V18EN_CORE(r16) _BFGET_(r16, 1, 1)
#define SET16EMMCS28_PAD_ctrl_V18EN_CORE(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32EMMCS28_PAD_ctrl_V25EN_CORE(r32) _BFGET_(r32, 2, 2)
#define SET32EMMCS28_PAD_ctrl_V25EN_CORE(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16EMMCS28_PAD_ctrl_V25EN_CORE(r16) _BFGET_(r16, 2, 2)
#define SET16EMMCS28_PAD_ctrl_V25EN_CORE(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32EMMCS28_PAD_ctrl_ZP(r32) _BFGET_(r32, 7, 3)
#define SET32EMMCS28_PAD_ctrl_ZP(r32,v) _BFSET_(r32, 7, 3,v)
#define GET16EMMCS28_PAD_ctrl_ZP(r16) _BFGET_(r16, 7, 3)
#define SET16EMMCS28_PAD_ctrl_ZP(r16,v) _BFSET_(r16, 7, 3,v)
#define GET32EMMCS28_PAD_ctrl_ZN(r32) _BFGET_(r32,12, 8)
#define SET32EMMCS28_PAD_ctrl_ZN(r32,v) _BFSET_(r32,12, 8,v)
#define GET16EMMCS28_PAD_ctrl_ZN(r16) _BFGET_(r16,12, 8)
#define SET16EMMCS28_PAD_ctrl_ZN(r16,v) _BFSET_(r16,12, 8,v)
#define GET32EMMCS28_PAD_ctrl_PDB_CORE(r32) _BFGET_(r32,13,13)
#define SET32EMMCS28_PAD_ctrl_PDB_CORE(r32,v) _BFSET_(r32,13,13,v)
#define GET16EMMCS28_PAD_ctrl_PDB_CORE(r16) _BFGET_(r16,13,13)
#define SET16EMMCS28_PAD_ctrl_PDB_CORE(r16,v) _BFSET_(r16,13,13,v)
#define w32EMMCS28_PAD_ctrl {\
UNSG32 uctrl_REG_PDB_CORE : 1;\
UNSG32 uctrl_V18EN_CORE : 1;\
UNSG32 uctrl_V25EN_CORE : 1;\
UNSG32 uctrl_ZP : 5;\
UNSG32 uctrl_ZN : 5;\
UNSG32 uctrl_PDB_CORE : 1;\
UNSG32 RSVDx0_b14 : 18;\
}
union { UNSG32 u32EMMCS28_PAD_ctrl;
struct w32EMMCS28_PAD_ctrl;
};
///////////////////////////////////////////////////////////
} SIE_EMMCS28_PAD;
typedef union T32EMMCS28_PAD_ctrl
{ UNSG32 u32;
struct w32EMMCS28_PAD_ctrl;
} T32EMMCS28_PAD_ctrl;
///////////////////////////////////////////////////////////
typedef union TEMMCS28_PAD_ctrl
{ UNSG32 u32[1];
struct {
struct w32EMMCS28_PAD_ctrl;
};
} TEMMCS28_PAD_ctrl;
///////////////////////////////////////////////////////////
SIGN32 EMMCS28_PAD_drvrd(SIE_EMMCS28_PAD *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 EMMCS28_PAD_drvwr(SIE_EMMCS28_PAD *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void EMMCS28_PAD_reset(SIE_EMMCS28_PAD *p);
SIGN32 EMMCS28_PAD_cmp (SIE_EMMCS28_PAD *p, SIE_EMMCS28_PAD *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define EMMCS28_PAD_check(p,pie,pfx,hLOG) EMMCS28_PAD_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define EMMCS28_PAD_print(p, pfx,hLOG) EMMCS28_PAD_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: EMMCS28_PAD
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE smSysCtl biu (4,4)
/// # # ----------------------------------------------------------
/// @ 0x00000 SM_ID (R-)
/// ###
/// * SM ID information
/// ###
/// %unsigned 4 REV_ID 0xA
/// ###
/// * SM revision ID
/// ###
/// %unsigned 16 PART_ID 0x7788
/// ###
/// * SM part number ID
/// ###
/// %unsigned 12 MFC_ID 0x8D
/// ###
/// * SM manufacture
/// ###
/// @ 0x00004 SM_CPU_CTRL (RW)
/// ###
/// * SM CPU control
/// ###
/// %unsigned 1 CPU_RST_GO 0x0
/// ###
/// * SM CPU reset control
/// * 0: assert CPU reset
/// * 1: de-assert CPU reset
/// ###
/// %unsigned 1 CPU_VINITHI 0x0
/// ###
/// * High exception vector address select
/// * 0: starts from 0x0000_0000
/// * 1: starts from 0xFFFF_0000
/// ###
/// %unsigned 1 CPU_INITRAM 0x1
/// ###
/// * TCM enable at reset
/// * 0: TCM disable at reet
/// * 1: TCM is enabled at reset
/// ###
/// %unsigned 1 CPU_BIGEND 0x0
/// ###
/// * SM CPU endian status
/// * 0: little endian
/// * 1: big endian
/// ###
/// %% 28 # Stuffing bits...
/// @ 0x00008 SM_RST_CTRL (RW-)
/// ###
/// * SM reset control
/// ###
/// %unsigned 1 SOC_RST_GO 0x1
/// ###
/// * Berlin SoC reset control
/// * 0: assert Berlin SoC reset
/// * 1: de-assert Berlin SoC reset
/// ###
/// %unsigned 1 APB_RST_GO 0x1
/// ###
/// * SM APB component reset control, write 1 to assert APB reset. This reset automatically de-assert after 3 SM system clocks
/// * 0: assert APB reset, de-assert automatically
/// * 1: no effect
/// ###
/// %unsigned 1 SXBAR_RST_GO 0x1
/// ###
/// * SM crossbar reset control, write 1 to assert SXBAR reset. This reset automatically de-assert after 3 SM system clocks
/// * 0: assert SXBAR reset, de-assert automatically.
/// * 1: no effect
/// ###
/// %unsigned 1 WOL_RST_GO 0x1
/// ###
/// * WOL reset control.
/// * 0: assert WOL reset.
/// * 1: de-assert WOL reset.
/// ###
/// %unsigned 1 FEPHY_RST_GO 0x1
/// ###
/// * FEPHY reset control.
/// * 0: assert FEPHY reset.
/// * 1: de-assert FEPHY reset.
/// ###
/// %% 27 # Stuffing bits...
/// @ 0x0000C SM_RST_STATUS (RW)
/// ###
/// * SM reset status control
/// ###
/// %unsigned 1 RST_WD_0 0x0
/// ###
/// * Watch dog 0 status
/// * 0: no watch dog 0 event happen
/// * 1: watch dog 0 event happen
/// ###
/// %unsigned 1 RST_WD_1 0x0
/// ###
/// * Watch dog 1 status
/// * 0: no watch dog 1 event happen
/// * 1: watch dog 1 event happen
/// ###
/// %unsigned 1 RST_WD_2 0x0
/// ###
/// * Watch dog 2 status
/// * 0: no watch dog 2 event happen
/// * 1: watch dog 2 event happen
/// ###
/// %% 29 # Stuffing bits...
/// @ 0x00010 SM_STRP_STATUS (RW)
/// ###
/// * SM power strapping status control
/// ###
/// %unsigned 1 BOOT_MODE 0x0
/// ###
/// * SM to SOC RSTn mode select0: SM_SOC_RSTOn_DO_FMmodule releasing waits for SoCRstCnt but does not wait for SM_PWR_OK(mode_0 of SM_FE_LED[1], system will assert this signal when SOC core power is ready).1: SM_SOC_RSTOn_DO_FMmodule releasing waits for both SoCRstCnt  and SM_PWR_OK.
/// ###
/// %unsigned 1 STRP_1 0x0
/// ###
/// * Reserved
/// ###
/// %unsigned 1 STRP_2 0x0
/// ###
/// * Reserved
/// ###
/// %unsigned 1 STRP_3 0x0
/// ###
/// * Reserved
/// ###
/// %% 28 # Stuffing bits...
/// @ 0x00014 SM_CTRL (RW-)
/// ###
/// * SM misc control
/// ###
/// %unsigned 1 ISO_EN 0x0
/// ###
/// * Isolation cell enable
/// * 0: disable
/// * 1: enable
/// ###
/// %unsigned 1 SM2SOC_SW_INTR 0x0
/// ###
/// * SM to SOC software interrupt
/// * 0: disable
/// * 1: enable
/// ###
/// %unsigned 1 SOC2SM_SW_INTR 0x1
/// ###
/// * SOC to SM software interrupt, connects to IRQ13, active low
/// * 0: enable
/// * 1: disable
/// ###
/// %unsigned 2 REV_0 0x0
/// ###
/// * Reserved
/// ###
/// %unsigned 4 ADC_SEL 0x7
/// ###
/// * ADC input selection
/// * 4'h0: ADC_IN[0]
/// * 4'h1: ADC_IN[1]
/// * 4'h2: ADC_IN[2]
/// * 4'h3: ADC_IN[3]
/// * 4'h4: ADC_IN[4]
/// * 4'h5: ADC_IN[5]
/// * 4'h6: ADC_IN[6]
/// * 4'h7: ADC_IN[7]
/// * 4'h8: ADC_IN[8]
/// * 4'h9: ADC_IN[9]
/// * 4'hA: ADC_IN[10]
/// * 4'hB: ADC_IN[11]
/// * 4'hC: ADC_IN[12]
/// * 4'hD: ADC_IN[13]
/// * 4'hE: ADC_IN[14]
/// * 4'hF: ADC_IN[15]
/// ###
/// %unsigned 1 ADC_PU 0x0
/// ###
/// * SM ADC power control
/// * 0: power-down
/// * 1: power-up
/// ###
/// %unsigned 2 ADC_CKSEL 0x3
/// ###
/// * ADC internal clock divider selection
/// * 2'h0: ck / 2
/// * 2'h1: ck / 3
/// * 2'h2: ck / 4
/// * 2'h3: ck / 8
/// ###
/// %unsigned 1 ADC_START 0x0
/// ###
/// * Start ADC digitalization process, write 1 to start ADC digitalization. This bit automatically clear after receiving ADC done signal
/// * 0: no effect
/// * 1: Start ADC digitalization, clear automatically.
/// ###
/// %unsigned 1 ADC_RESET 0x1
/// ###
/// * ADC reset control input, active high.
/// * ‘1’: the digital circuitry is held in reset .
/// * ‘0’: the digital circuitry is enabled and the analog circuitry will be powered up if ADC_PU_SAR11=1, BG_RDY11=1, and VAA is present.
/// ###
/// %unsigned 1 ADC_BG_RDY 0x0
/// ###
/// * bandgap reference block is powered up and ready
/// ###
/// %unsigned 1 ADC_CONT 0x0
/// ###
/// * continuous mode vs. single-shot mode
/// * 0: ADC is in single-shot conversion operating mode.
/// * 1: ADC is in continuous conversion operating mode.
/// ###
/// %unsigned 1 ADC_BUF_EN 0x0
/// ###
/// * enables analog ADC input buffer
/// ###
/// %unsigned 1 ADC_VREF_SEL 0x0
/// ###
/// * selects ext. reference vs. int. ref.
/// ###
/// %unsigned 1 ADC_ROTATE_SEL 0x0
/// ###
/// * Orientation bit
/// ###
/// %unsigned 1 TSEN_EN 0x0
/// ###
/// * Temperature sensor measurement enable signal. It should last for complete TS measurement cycles and will be deserted by DATA_RDY. When asserted, measurement gets started. uC should wait till DATA_RDY= 1 to desert TS_EN.
/// ###
/// %unsigned 1 TSEN_CLK_EN 0x0
/// ###
/// * Enable to the divby50 clock divider circuit to generate clock TSEN_CLK
/// ###
/// %unsigned 1 TSEN_CLK_SEL 0x0
/// ###
/// * CLK_SEL= 1 will choose 2.5MHz clock, otherwise 1.25MHz will be chosen.
/// ###
/// %unsigned 1 TSEN_MODE_SEL 0x0
/// ###
/// * MODE_SEL= 1 will choose 10 ~ 50 degree Centigrade temperature testing range, otherwise 0 ~ 125 degree Centigrade temperature testing range will be chosen.
/// ###
/// %unsigned 2 TSEN_ADC_CAL 0x0
/// ###
/// * ADC calibration mode select bits from uC. 00 = normal function 10 = gain calibration function 01 = offset calibration (0.6V) 11 = Not used
/// ###
/// %unsigned 5 TSEN_ADC_TST_SEL 0x0
/// ###
/// * DC test point select signal
/// ###
/// %unsigned 1 TSEN_RESET 0x1
/// ###
/// * 1'b1 to reset TSEN after power up
/// ###
/// %unsigned 1 TSEN_ADC_ISO_EN 0x0
/// ###
/// * It's used as digital power availability indicator for digital 1.1V power domain and analog 1.8V power domain isolation purpose.
/// ###
/// # 0x00018 SM_CTRL1
/// %unsigned 1 EDID_INTR_CLR 0x0
/// ###
/// * Clears the edid interrupt
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x0001C SM_ADC_CTRL (P-)
/// ###
/// * SM ADCs Control
/// ###
/// %unsigned 5 TSEN_DAT_LT 0x0
/// ###
/// * Delay interms of pclk after data ready at which the data is to be latched
/// ###
/// %unsigned 5 ADC_DAT_LT 0x0
/// ###
/// * Delay interms of pclk after data ready at which the data is to be latched
/// ###
/// %% 22 # Stuffing bits...
/// @ 0x00020 SM_ADC_STATUS (RW-)
/// ###
/// * SM ADC status and interrupt enable
/// ###
/// %unsigned 1 CH0_DATA_RDY 0x0
/// ###
/// * ADC channel 0 data ready, write 0 to clear interrupt, write 1 won't effect anything
/// * 0: no valid data
/// * 1: data ready to read
/// ###
/// %unsigned 1 CH1_DATA_RDY 0x0
/// ###
/// * ADC channel 1 data ready, write 0 to clear interrupt, write 1 won't effect anything
/// * 0: no valid data
/// * 1: data ready to read
/// ###
/// %unsigned 1 CH2_DATA_RDY 0x0
/// ###
/// * ADC channel 2 data ready, write 0 to clear interrupt, write 1 won't effect anything
/// * 0: no valid data
/// * 1: data ready to read
/// ###
/// %unsigned 1 CH3_DATA_RDY 0x0
/// ###
/// * ADC channel 3 data ready, write 0 to clear interrupt, write 1 won't effect anything
/// * 0: no valid data
/// * 1: data ready to read
/// ###
/// %unsigned 1 CH4_DATA_RDY 0x0
/// ###
/// * ADC channel 4 data ready, write 0 to clear interrupt, write 1 won't effect anything
/// * 0: no valid data
/// * 1: data ready to read
/// ###
/// %unsigned 1 CH5_DATA_RDY 0x0
/// ###
/// * ADC channel 5 data ready, write 0 to clear interrupt, write 1 won't effect anything
/// * 0: no valid data
/// * 1: data ready to read
/// ###
/// %unsigned 1 CH6_DATA_RDY 0x0
/// ###
/// * ADC channel 6 data ready, write 0 to clear interrupt, write 1 won't effect anything
/// * 0: no valid data
/// * 1: data ready to read
/// ###
/// %unsigned 1 CH7_DATA_RDY 0x0
/// ###
/// * ADC channel 7 data ready, write 0 to clear interrupt, write 1 won't effect anything
/// * 0: no valid data
/// * 1: data ready to read
/// ###
/// %unsigned 1 CH8_DATA_RDY 0x0
/// ###
/// * ADC channel 8 data ready, write 0 to clear interrupt, write 1 won't effect anything
/// * 0: no valid data
/// * 1: data ready to read
/// ###
/// %unsigned 1 CH9_DATA_RDY 0x0
/// ###
/// * ADC channel 9 data ready, write 0 to clear interrupt, write 1 won't effect anything
/// * 0: no valid data
/// * 1: data ready to read
/// ###
/// %unsigned 1 CH10_DATA_RDY 0x0
/// ###
/// * ADC channel 10 data ready, write 0 to clear interrupt, write 1 won't effect anything
/// * 0: no valid data
/// * 1: data ready to read
/// ###
/// %unsigned 1 CH11_DATA_RDY 0x0
/// ###
/// * ADC channel 11 data ready, write 0 to clear interrupt, write 1 won't effect anything
/// * 0: no valid data
/// * 1: data ready to read
/// ###
/// %unsigned 1 CH12_DATA_RDY 0x0
/// ###
/// * ADC channel 12 data ready, write 0 to clear interrupt, write 1 won't effect anything
/// * 0: no valid data
/// * 1: data ready to read
/// ###
/// %unsigned 1 CH13_DATA_RDY 0x0
/// ###
/// * ADC channel 13 data ready, write 0 to clear interrupt, write 1 won't effect anything
/// * 0: no valid data
/// * 1: data ready to read
/// ###
/// %unsigned 1 CH14_DATA_RDY 0x0
/// ###
/// * ADC channel 14 data ready, write 0 to clear interrupt, write 1 won't effect anything
/// * 0: no valid data
/// * 1: data ready to read
/// ###
/// %unsigned 1 CH15_DATA_RDY 0x0
/// ###
/// * ADC channel 15 data ready, write 0 to clear interrupt, write 1 won't effect anything
/// * 0: no valid data
/// * 1: data ready to read
/// ###
/// %unsigned 1 CH0_INT_EN 0x0
/// ###
/// * ADC channel 0 interrupt enable
/// * 0: disable
/// * 1: enable
/// ###
/// %unsigned 1 CH1_INT_EN 0x0
/// ###
/// * ADC channel 1 interrupt enable
/// * 0: disable
/// * 1: enable
/// ###
/// %unsigned 1 CH2_INT_EN 0x0
/// ###
/// * ADC channel 2 interrupt enable
/// * 0: disable
/// * 1: enable
/// ###
/// %unsigned 1 CH3_INT_EN 0x0
/// ###
/// * ADC channel 3 interrupt enable
/// * 0: disable
/// * 1: enable
/// ###
/// %unsigned 1 CH4_INT_EN 0x0
/// ###
/// * ADC channel 4 interrupt enable
/// * 0: disable
/// * 1: enable
/// ###
/// %unsigned 1 CH5_INT_EN 0x0
/// ###
/// * ADC channel 5 interrupt enable
/// * 0: disable
/// * 1: enable
/// ###
/// %unsigned 1 CH6_INT_EN 0x0
/// ###
/// * ADC channel 6 interrupt enable
/// * 0: disable
/// * 1: enable
/// ###
/// %unsigned 1 CH7_INT_EN 0x0
/// ###
/// * ADC channel 7 interrupt enable
/// * 0: disable
/// * 1: enable
/// ###
/// %unsigned 1 CH8_INT_EN 0x0
/// ###
/// * ADC channel 8 interrupt enable
/// * 0: disable
/// * 1: enable
/// ###
/// %unsigned 1 CH9_INT_EN 0x0
/// ###
/// * ADC channel 9 interrupt enable
/// * 0: disable
/// * 1: enable
/// ###
/// %unsigned 1 CH10_INT_EN 0x0
/// ###
/// * ADC channel 10 interrupt enable
/// * 0: disable
/// * 1: enable
/// ###
/// %unsigned 1 CH11_INT_EN 0x0
/// ###
/// * ADC channel 11 interrupt enable
/// * 0: disable
/// * 1: enable
/// ###
/// %unsigned 1 CH12_INT_EN 0x0
/// ###
/// * ADC channel 12 interrupt enable
/// * 0: disable
/// * 1: enable
/// ###
/// %unsigned 1 CH13_INT_EN 0x0
/// ###
/// * ADC channel 13 interrupt enable
/// * 0: disable
/// * 1: enable
/// ###
/// %unsigned 1 CH14_INT_EN 0x0
/// ###
/// * ADC channel 14 interrupt enable
/// * 0: disable
/// * 1: enable
/// ###
/// %unsigned 1 CH15_INT_EN 0x0
/// ###
/// * ADC channel 15 interrupt enable
/// * 0: disable
/// * 1: enable
/// ###
/// @ 0x00024 SM_ADC_DATA (R-)
/// ###
/// * SM ADC digitalized data
/// ###
/// %unsigned 10 ADC_DATA 0x0
/// ###
/// * ADC data
/// ###
/// %% 22 # Stuffing bits...
/// @ 0x00028 TSEN_ADC_STATUS (RW)
/// ###
/// * SM TSEN ADC status and interrupt enable
/// ###
/// %unsigned 1 DATA_RDY 0x0
/// ###
/// * ADC data ready, write 0 to clear interrupt, write 1 won't effect anything
/// * 0: no valid data
/// * 1: data ready to read
/// ###
/// %unsigned 1 INT_EN 0x0
/// ###
/// * ADC interrupt enable
/// * 0: disable
/// * 1: enable
/// ###
/// %% 30 # Stuffing bits...
/// @ 0x0002C TSEN_ADC_DATA (R-)
/// ###
/// * SM TSEN ADC digitalized data
/// ###
/// %unsigned 12 ADC_DATA 0x0
/// ###
/// * 12-bit post-average and calibration TSEN result.
/// * Data format is signed 12-bit with sign bit on the 1st MSB.
/// ###
/// %% 20 # Stuffing bits...
/// @ 0x00030 TSEN_CHK_CTRL (P-)
/// ###
/// * SM TSEN Data Thresholds
/// ###
/// %unsigned 12 TSEN_DATA_MAX 0xFFF
/// ###
/// * Maximum value used to check against TSEN_DATA
/// ###
/// %unsigned 12 TSEN_DATA_MIN 0x0
/// ###
/// * Minimum value used to check against TSEN_DATA
/// ###
/// %unsigned 1 TSEN_OVERHEAT_SEL 0x0
/// ###
/// * 0: Overheat flag uses TSEN_MAX_FAIL
/// * 1: Overheat flag uses TSEN_MIN_FAIL
/// ###
/// %% 7 # Stuffing bits...
/// @ 0x00034 TSEN_DATA_STATUS (R-)
/// ###
/// * SM TSEN Data Threshold Check Status
/// ###
/// %unsigned 1 TSEN_MAX_FAIL 0x0
/// ###
/// * 0: TSEN_DATA <= TSEN_DATA_MAX
/// * 1: TSEN_DATA > TSEN_DATA_MAX
/// ###
/// %unsigned 1 TSEN_MIN_FAIL 0x0
/// ###
/// * 0: TSEN_DATA >= TSEN_DATA_MIN
/// * 1: TSEN_DATA < TSEN_DATA_MIN
/// ###
/// %% 30 # Stuffing bits...
/// @ 0x00038 SM_BOOT_STATUS (RW)
/// ###
/// * SM Software Boot status
/// ###
/// %unsigned 32 MODE 0x0
/// ###
/// * Used by software only to store boot up status. HW can only clean to 0 with POR
/// ###
/// @ 0x0003C SM_LDO_CTRL (RW)
/// ###
/// * SM LDO control & status register
/// ###
/// %unsigned 3 TEST_SEL 0x0
/// ###
/// * Select output of test mux (VDD domain)
/// ###
/// %unsigned 3 VOUT_SEL 0x0
/// ###
/// * Select LDO output voltage (VDD domain)
/// * 000 : 0.9V
/// * 001 : 0.75V
/// * 010 : 0.80V
/// * 011 : 0.85V
/// * 100 : 0.90V
/// * 101 : 0.95V
/// * 110 : 1.00V
/// * 111 : 1.05V
/// ###
/// %unsigned 1 TEST_EN 0x0
/// ###
/// * Enable test mux (VDD domain )
/// ###
/// %unsigned 1 LDO_RDY 0x0
/// ###
/// * Assert the LDO ready
/// ###
/// %unsigned 1 CHP_EN_1P1 0x0
/// %unsigned 1 ICLAMP_EN_1P1 0x0
/// %unsigned 5 RSVD_HI 0x1F
/// %unsigned 5 RSVD_LO 0x0
/// %unsigned 2 ZERO_SEL 0x0
/// ###
/// * Zero location select
/// * 00:80KOhm
/// ###
/// %unsigned 2 POLE_SEL 0x0
/// ###
/// * Pole location select
/// * 00:50KOhm, 0.5pF
/// ###
/// %unsigned 2 MON_VDD1P8_SEL 0x0
/// ###
/// * VDD1P8 voltage monitor threshold select
/// * 00:1.44V
/// * 01:1.53V
/// * 10:1.62V
/// * 11:1.71V
/// ###
/// %unsigned 2 DLY_SEL 0x0
/// ###
/// * Delay time select
/// * 00:7.5ms
/// ###
/// %unsigned 1 EN_ZERO_SEL 0x0
/// ###
/// * Enable Zero Insertion control
/// * 0:Disable zero insertion
/// * 1:Enable zero insertion
/// ###
/// %unsigned 1 EN_POLE_SEL 0x0
/// ###
/// * Enable Pole Insertion Select
/// * 0:Disable pole insertion
/// * 1:Enable pole insertion
/// ###
/// %unsigned 1 PD_MON_VDD1P8 0x0
/// ###
/// * Power down VDD1P8 monitor select
/// * 0:Power up VDD1P8 monitor
/// * 1:Power down VDD1P8 monitor circuit
/// ###
/// %unsigned 1 MON_VDD1P8_OUT 0x0
/// ###
/// * Output signal of VDD1P8 monitor
/// * 0: VDD1P8 above threshold voltage
/// * 1: VDD1P8 below threshold voltage
/// ###
/// @ 0x00040 SM_WDT_MASK (P-)
/// ###
/// * SM WDT Mask
/// ###
/// %unsigned 3 SM_RST 0x7
/// ###
/// * WDT reset mask bit for SM reset signal.
/// * 1 : disable WDT (0,1,2) timeout to reset SM for each WDT
/// ###
/// %unsigned 3 SOC_RST 0x7
/// ###
/// * WDT reset mask bit for SOC reset signal.
/// * 1 : disable WDT (0,1,2) timeout to reset SOC for each WDT
/// ###
/// %% 26 # Stuffing bits...
/// @ 0x00044 SM_CLK_CTRL (P-)
/// ###
/// * SM Clock control register
/// ###
/// %unsigned 1 tsenClkSel 0x0
/// ###
/// * Tsen clock select
/// * 0 : 2.5MHz
/// * 1 : 1.25MHz
/// ###
/// %unsigned 1 tsenClkEn 0x1
/// ###
/// * Tsen Clock Enable
/// * 0 : disabled
/// * 1 : enabled
/// ###
/// %unsigned 1 ssmiiTxClkSel 0x0
/// ###
/// * SSMI Interface transmit clock select
/// * 0 : 2.5MHz
/// * 1 : 25MHz
/// ###
/// %unsigned 1 ssmiiTxClkEn 0x1
/// ###
/// * SSMI Interface transmit clock enable
/// * 0 : disabled
/// * 1 : enabled
/// ###
/// %% 28 # Stuffing bits...
/// @ 0x00048 smAnaGrpCtl (RW)
/// ###
/// * SM Analog group registers
/// ###
/// %unsigned 1 pu 0x1
/// ###
/// * Power-up signal for the whole block
/// * 1: power-up
/// * 0: power-down
/// ###
/// %unsigned 2 bgSel 0x1
/// ###
/// * Selects the reference Voltage
/// * 00:0.575V
/// * 01:0.6V
/// * 10:0.625V
/// * 11:0.65V
/// ###
/// %unsigned 1 puXtl 0x1
/// ###
/// * Power-up signal for the XTL OSC circuit.
/// * 1: Power-up XTAL
/// * 0: power-down XTAL
/// ###
/// %unsigned 1 bypass 0x0
/// ###
/// * OSC bypass control
/// * 1: in bypass mode
/// * 0: in osc mode
/// * **INTERNAL_ONLY***
/// ###
/// %unsigned 1 gainX2 0x0
/// ###
/// * Gain control
/// * 1: 2x buffer size 30M-50MHz
/// * 0: 1x buffer size 10-30MHz
/// ###
/// %unsigned 2 selClkDigDiv1 0x0
/// ###
/// * Selection of clock division ratio for CLKOUT_DIG[0]
/// * 00: divided by 1
/// * 01: divided by 2
/// * 10: divided by 4
/// * 11: divided by 8
/// ###
/// %unsigned 2 selClkDigDiv2 0x0
/// ###
/// * Selection of clock division ratio for CLKOUT_DIG[1]
/// * 00: divided by 1
/// * 01: divided by 2
/// * 10: divided by 4
/// * 11: divided by 8
/// ###
/// %unsigned 2 selClkDigDiv3 0x0
/// ###
/// * Selection of clock division ratio for CLKOUT_DIG[2]
/// * 00: divided by 1
/// * 01: divided by 2
/// * 10: divided by 4
/// * 11: divided by 8
/// ###
/// %unsigned 2 selClkDigDiv4 0x0
/// ###
/// * Selection of clock division ratio for CLKOUT_DIG[3]
/// * 00: divided by 1
/// * 01: divided by 2
/// * 10: divided by 4
/// * 11: divided by 8
/// ###
/// %unsigned 1 puOsc 0x0
/// ###
/// * Power-up control for the free-running ring oscillator
/// ###
/// %unsigned 2 speedOsc 0x2
/// ###
/// * Speed selection for the frequency of CLKOUT_OSC
/// * 00: 9 MHz +/-20%
/// * 01: 12MHz +/-20%
/// * 10: 16 MHz +/-20%
/// * 11: 20 MHz +/-20%
/// ###
/// %unsigned 4 testAna 0x0
/// ###
/// * Analog test control bits.
/// ###
/// %unsigned 1 bgRdy 0x0
/// ###
/// * BG Ready status bit.
/// ###
/// %unsigned 10 reserve_in 0x11F
/// ###
/// * Reserved Input Register Pins
/// ###
/// # 0x0004C smAnaGrpCtl1
/// %unsigned 1 xtl_pecl_sel 0x1
/// ###
/// * Choose Regulator Supply “ON”
/// * For XTAL Or PECL “On”
/// * When XTL_PECL_SEL = 1, PU_XTL = 1, regulator supply for XTAL ON, regulator supply for PECL OFF then choose XTAL output clock for final clock CLKOUT_ANA[3:0], CLKOUT_DIG[3:0] and REFCLKC1, REFCLKC2.
/// * When XTL_PECL_SEL= 0, PU_PECL= 1 then choose output clock CLKOUT_ANA[3:0], CLKOUT_DIG[3:0] , REFCLKC1 and REFCLKC2 from PECL output.
/// ###
/// %unsigned 2 vreg_1p4v_sel 0x1
/// ###
/// * XTAL 1.2V Select. Selects 1.2V voltage for the crystal. (XTAL_VDDR1P2V)
/// * 00: 1.17V
/// * 01: 1.2V
/// * 10: 1.23V
/// * 11: 1.26V.
/// ###
/// %unsigned 3 vreg_0p9v_sel_xtl 0x3
/// ###
/// * Regulator0.9V Select. Voltage(XTAL_VDDR0P9V)
/// * 000: XTAL_VDDR1P2-10mV*36
/// * 001: XTAL_VDDR1P2-10mV*34
/// * 010: XTAL_VDDR1P2-10mV*32
/// * 011: XTAL_VDDR1P2-10mV*30
/// * 100: XTAL_VDDR1P2-10mV*28
/// * 101: XTAL_VDDR1P2-10mV*26
/// * 110: XTAL_VDDR1P2-10mV*24
/// * 111: XTAL_VDDR1P2-10mV*22
/// ###
/// %unsigned 3 vreg_0p9v_sel_pecl 0x3
/// ###
/// * Regulator0.9V Select. Voltage(PECL_VDDR0P9V)
/// * 000: XTAL_VDDR1P2-10 mV*36
/// * 001: XTAL_VDDR1P2-10 mV*34
/// * 010: XTAL_VDDR1P2-10 mV*32
/// * 011: XTAL_VDDR1P2-10 mV*30
/// * 100: XTAL_VDDR1P2-10 mV*28
/// * 101: XTAL_VDDR1P2-10 mV*26
/// * 110: XTAL_VDDR1P2-10 mV*24
/// * 111: XTAL_VDDR1P2-10 mV*22
/// ###
/// %unsigned 1 term 0x1
/// ###
/// * PECL Internal Block Common Mode Voltage Control. When PECL_EN = 1,
/// * 1. DC coupling:
/// * common mode 1.0V ~1.2V TERM = 0
/// * common mode1.2V~1.4V TERM = 1
/// * 2. Input clock AC coupling, TERM must be set to 0.
/// * When PECL_EN = 0, set TERM = 1.
/// ###
/// %unsigned 1 pu_pecl 0x0
/// ###
/// * Power-Up Signal For PECL Circuit Select.
/// * 1: Power-up PECL
/// * 0: Power-down PECL
/// ###
/// %unsigned 1 pecl_en 0x0
/// ###
/// * PECL Level or CMOS Level Input Port Select.
/// * 1: REFCLKP and REFCLKN are PECL level differential input.
/// * 0: REFCLKP and REFCLKN are CMOS level input from the REFCLKP port.
/// ###
/// %unsigned 1 pu_limiter 0x0
/// ###
/// * Power-Up Signal For Limiter Circuit Select.
/// * 1: Power-up limiter
/// * 0: power-down limiter
/// ###
/// %unsigned 1 limiter_dc_clk_en 0x0
/// ###
/// * When = 0, LIMITER_DC_CLK has no clock output
/// * When = 1, LIMITER_DC_CLK has clock output.
/// ###
/// %unsigned 2 ipp_adj 0x1
/// ###
/// * IPP_ADJ Current Select.
/// * IPP_ADJ[1:0] IPP Current
/// * 00 .........................197%
/// * 01 .........................100%
/// * 10..........................103%
/// * 111........................ 107%
/// ###
/// %unsigned 2 icc_adj 0x1
/// ###
/// * ICC_ADJ Current Select.
/// * ICC_ADJ[1:0] ICC Current
/// * 00 .........................197%
/// * 01 .........................100%
/// * 10..........................103%
/// * 111........................ 107%
/// ###
/// %unsigned 2 ixtal 0x1
/// ###
/// * XTAL Block Current Change.
/// * 00: 100 uA
/// * 01: 150 uA
/// * 10: 200 uA
/// * 11: 250 uA.
/// ###
/// %unsigned 1 icc10u_in_sel 0x0
/// ###
/// * CLKOUT_OSC ICC Current Select
/// * 1: Use external ICC current for CLKOUT_OSC. Feed external constant 10 uA current to ICC10U_IN.
/// * 0: Use internal ICC current for CLKOUT_OSC. ICC10U_IN can be tied low.
/// ###
/// %unsigned 6 reserve_out 0x3F
/// ###
/// * Reserve Out
/// ###
/// %% 5 # Stuffing bits...
/// @ 0x00050 POR_status (R-)
/// %unsigned 1 POR_AVDD33
/// ###
/// * The output of POR_AVDD33 from SOC without SM isolation. For monitor purpose
/// ###
/// %unsigned 1 POR_AVDD
/// ###
/// * The output of POR_AVDD from SOC without isolation. For monitor purpose
/// ###
/// %unsigned 1 POR_VDD_SOC
/// ###
/// * The output of POR_VDD from SOC without SM isolation. For monitor purpose
/// ###
/// %unsigned 1 POR_VDD_CPU
/// ###
/// * The output of POR_VDD from cpu without SM isolation. For monitor purpose.
/// ###
/// %% 28 # Stuffing bits...
/// @ 0x00054 SM_CORE_CTRL (RW)
/// ###
/// * SM core control for pad(padring 1)
/// * not used in BG4CT
/// * Please use SM_GLOBAL_PADRING SM_GPIO_PADRING SM_I2C_PADRING
/// ###
/// %unsigned 1 PAD_REG_PDB_CORE 0x1
/// %unsigned 1 PAD_V18EN_CORE 0x0
/// %unsigned 1 PAD_V25EN_CORE 0x0
/// %unsigned 4 PAD_ZP 0x0
/// %unsigned 4 PAD_ZN 0x0
/// %% 21 # Stuffing bits...
/// @ 0x00058 SM_TEST (R-)
/// ###
/// * SM ADC Test Results
/// ###
/// %unsigned 1 ADC_TEST_FAIL 0x0
/// ###
/// * ADC Test result bit
/// * 1: ADC data is not in the valid window
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x0005C SM_TEST_DATA0 (P-)
/// ###
/// * SM ADC Test Registers High
/// ###
/// %unsigned 10 ADC_DATA_HIGH 0x0
/// ###
/// * ADC test data upper boundary
/// ###
/// %% 22 # Stuffing bits...
/// @ 0x00060 SM_TEST_DATA1 (P-)
/// ###
/// * SM ADC Test Registers Low
/// ###
/// %unsigned 10 ADC_DATA_LOW 0x0
/// ###
/// * ADC test data Lower boundary
/// ###
/// %% 22 # Stuffing bits...
/// @ 0x00064 SM_RWTC_CTRL_0 (P-)
/// ###
/// * SM memory strength control register 0
/// ###
/// %unsigned 4 RF1P_LOW 0xA
/// ###
/// * RF1P memory RWTC control for LOW SPEED
/// ###
/// %unsigned 4 RF1P_HIGH 0xA
/// ###
/// * RF1P memory RWTC control for HIGH SPEED
/// ###
/// %unsigned 4 RF2P_LOW 0x5
/// ###
/// * RF2P memory RWTC control for LOW SPEED
/// ###
/// %unsigned 4 RF2P_HIGH 0x5
/// ###
/// * RF2P memory RWTC control for HIGH SPEED
/// ###
/// %unsigned 4 SR1P_LOW 0x9
/// ###
/// * SR1P memory RWTC control for LOW SPEED
/// ###
/// %unsigned 4 SR1P_HIGH 0x9
/// ###
/// * SR1P memory RWTC control for HIGH SPEED
/// ###
/// %unsigned 4 SR2P_LOW 0x9
/// ###
/// * SR2P memory RWTC control for LOW SPEED
/// ###
/// %unsigned 4 SR2P_HIGH 0x9
/// ###
/// * SR2P memory RWTC control for HIGH SPEED
/// ###
/// @ 0x00068 SM_RWTC_CTRL_1 (P-)
/// ###
/// * SM memory strength control register 1
/// ###
/// %unsigned 5 ROM_LOW 0x1E
/// ###
/// * ROM memory RWTC control for LOW SPEED
/// ###
/// %unsigned 5 ROM_HIGH 0x1E
/// ###
/// * ROM memory RWTC control for HIGH SPEED
/// ###
/// %unsigned 4 RF2P_NH 0x6
/// ###
/// * SM doesn't have the mem type.
/// ###
/// %unsigned 4 RF2R2W_NH
/// ###
/// * SM doesn't have the mem type.
/// ###
/// %unsigned 4 SR1P_LVT
/// ###
/// * SM doesn't have the mem type.
/// ###
/// %unsigned 4 SR2P_LVT
/// ###
/// * SM doesn't have the mem type.
/// ###
/// %% 6 # Stuffing bits...
/// @ 0x0006C SM_PORT_SEL_CTRL (P-)
/// %unsigned 1 TW2 0x0
/// ###
/// * Not used
/// ###
/// %unsigned 1 URT1 0x0
/// ###
/// * Not used
/// ###
/// %unsigned 1 FE_MDIO 0x0
/// ###
/// * 0: from eth mac
/// * 1: from pad for test
/// ###
/// %% 29 # Stuffing bits...
/// @ 0x00070 TSEN_ADC_RAW_DATA (R-)
/// ###
/// * SM TSEN ADC RAW DATA for debug purpose
/// ###
/// %unsigned 12 TSEN_DATA_RAW 0x0
/// ###
/// * ADC 12-bit raw data for debug purpose
/// ###
/// %% 20 # Stuffing bits...
/// @ 0x00074 TSEN_ADC_CLK_DIV (P-)
/// ###
/// * TSEN ADC_clock dividers
/// ###
/// %unsigned 3 ADC_DIV 0x0
/// %unsigned 4 TSEN_DIV 0x1
/// ###
/// * Clock divider set. Select TSEN internal operating frequency.
/// * ‘0000’: divide-by-32.(500KHz if main clock is 16MHz).
/// * ‘0001’: divide-by-48. (500KHz~521KHz if main clock is 24MHz~25MHz).
/// * ‘0010’: divide-by-64. (500KHz if main clock is 32MHz).
/// * ‘0011’: divide-by-80. (450KHz~550KHz if main clock is 36MHz~44MHz).
/// * ‘0100’: divide-by-94. (468KHz~532KHz if main clock is 44MHz~50MHz).
/// * ‘0101’: divide-by-112. (450KHz~550KHz if main clock is 50.4MHz~61.5MHz).
/// * ‘0110’: divide-by-132. (466KHz~532KHz if main clock is 61.5MHz~70.2MHz).
/// * ‘0111’: divide-by-150. (468KHz~528KHz if main clock is 70.2MHz~79.2MHz).
/// * ‘1000’: divide-by-168. (471KHz~524KHz if main clock is 79.2MHz~88MHz).
/// * ‘1001’: divide-by-184. (478KHz~526KHz if main clock is 88MHz~96.8MHz).
/// * ‘1010’: divide-by-210. (461KHz~545KHz if main clock is 96.8MHz~114.4MHz).
/// * ‘1011’: divide-by-246. - 13 – (465KHz~537KHz if main clock is 114.4MHz~132MHz).
/// * ‘1100’: divide-by-282. (468KHz~530KHz if main clock is 132MHz~149.6MHz).
/// * ‘1101’: divide-by-326. (459KHz~540KHz if main clock is 149.6MHz~176MHz).
/// * ‘1110’: divide-by-376. (468KHz~532KHz if main clock is 176MHz~200MHz).
/// * ‘1111’ reserved
/// ###
/// %% 25 # Stuffing bits...
/// @ 0x00078 TSEN_ADC_CTRL (P-)
/// ###
/// * TSEN ADC control registers
/// ###
/// %unsigned 8 ADC_VREF_ADJ 0x34
/// ###
/// * Used for trimming the reference voltage based on correction factors determined during manufacturing test.
/// ###
/// %unsigned 1 TSEN_START 0x0
/// %unsigned 3 TSEN_AVG_NUM 0x3
/// ###
/// * Temperature measurement result averaging:
/// * ‘000’: no average
/// * ‘001’: average 2
/// * ‘010’: average 4
/// * ‘011’: average 8
/// * ‘100’: reserved
/// * ‘101’: reserved
/// * ‘110’: reserved
/// * ‘111’: reserved
/// ###
/// %unsigned 1 TSEN_EXT_EN 0x0
/// %unsigned 2 TSEN_CHOP_EN 0x3
/// ###
/// * Chopper enable bits.
/// * ‘00’: all choppers are off.
/// * ‘01’: TSEN chopper is on, cap swap is off
/// * ‘10’: TSEN cap swap is off, cap swap is on
/// * ‘11’: all choppers are on
/// ###
/// %unsigned 2 TSEN_CAL 0x2
/// ###
/// * ADC foreground calibration select
/// * ‘00’: automatic self-cal skipped, TSEN in normal mode.
/// * ‘01’: automatic self-cal skipped, TSEN in ADC gain cal mode.
/// * ‘10’: automatic self-cal enforced, TSEN in normal mode.
/// * ‘11’: automatic self-cal enforced, TSEN in ADC gain cal mode.
/// ###
/// %unsigned 4 TSEN_RSVD 0xC
/// ###
/// * Reserved bits.
/// ###
/// %unsigned 1 BG_CHP_SEL 0x0
/// ###
/// * Chopper enable signal(1.1V):
/// * 0 disable, the settling time is 4us,
/// * 1 enable, the settling time is 12us0
/// ###
/// %unsigned 4 BG_DTRIM 0x7
/// ###
/// * Band gap curve trimming control signal(1.1V)
/// * 0000:1.219V
/// * ……….
/// * 0111:1.232V
/// * 1111:1.247V
/// ###
/// %% 6 # Stuffing bits...
/// @ 0x0007C TSEN_ADC_DBG (P-)
/// ###
/// * Tsen ADC debug register.
/// ###
/// %unsigned 2 TSEN_RAW_SEL 0x0
/// ###
/// * Default 2'b00
/// * Digital raw data select bits:
/// * '00' =12-b post-avg post_cal tsen measurement data in code (Raw1 reg)
/// * '01' =12-b post-avg but pre-cal tsen measurement data in code (Raw2 reg)
/// * '10' = 12-b self cal data in code (Raw3 reg)
/// * '11' =12-b pre-avg tsen measurement data in code (Raw4 reg)
/// ###
/// %% 30 # Stuffing bits...
/// @ 0x00080 SM_DUMMY_REG (RW)
/// ###
/// * Dummy Register for ECOs and Etc
/// ###
/// %unsigned 32 REG0 0x0
/// ###
/// * 32-bit Dummy Spare Register
/// ###
/// @ 0x00084 FEPHY_CTRL (P)
/// ###
/// * Configuration registers for Fast Ethernet PHY
/// ###
/// %unsigned 5 ext_pwrdn_a 0x1
/// ###
/// * When ext_pwrdn_a transitions from 1 to 0 register 0.11 set to 1'b0
/// * When ext_pwrdn_a transitions from 0 to 1 register 0.11 set to 1'b1
/// ###
/// %unsigned 3 pd_aneg_mode_a 0x0
/// ###
/// * Port 0 Autoneg default setup:
/// * 000 = force 10T
/// * 001 = force 100T
/// * 010 = advertise all 10/100 capabilities
/// * 011 = reserved
/// * 1xx = force 100FX
/// ###
/// %unsigned 5 pd_phyadr_a 0x0
/// ###
/// * Starting PHY address for Port0
/// * Port 1 PHY address = Port 0 PHY address + 1
/// * Port 2 PHY address = Port 1 PHY address + 1
/// * Port 3 PHY address = Port 2 PHY address + 1
/// * Port 4 PHY address = Port 3 PHY address + 1
/// ###
/// %unsigned 3 pd_led_config_a 0x0
/// ###
/// * change led registers 24:8:0 default
/// * 000 : 001 000 101
/// * 001 : 000 001 101
/// * 010 : 000 001 101
/// * 011 : 000 000 001
/// * 1xx : 000 000 101
/// * and change register 22.15:0 default
/// * 000: 0100 0100 0101 1000
/// * 001: 0100 0101 0100 1000
/// * 010: 0100 0010 0100 1010
/// * 011: 0100 1000 1010 0100
/// * 100: 0100 0010 0101 1000
/// * 101, 11x: 0100 1010 0100 0100
/// ###
/// %unsigned 5 yy_pecl_sdet_a 0x0
/// ###
/// * 100FX signale detect, only bit 0 for port 0 useful
/// ###
/// %unsigned 1 ps_en_eee10t_s 0x0
/// ###
/// * Enable EEE 10T. Compliant with EEE draft 1.2.
/// ###
/// %unsigned 1 ps_en_eee100t_s 0x0
/// ###
/// * Enable EEE 100T. Compliant with EEE draft 1.2
/// ###
/// %unsigned 1 pd_burnin_a 0x0
/// ###
/// * 1:put PHY in burn-in mode
/// * In Burnin a LFSR will drive RX. Hook up RX to TX to make chip in burnin
/// ###
/// %unsigned 1 pd_ena_edet_a 0x0
/// ###
/// * Enable Energy detect.
/// * It is sampled on the deassertion of hardware reset
/// * and set the default of register 16.14
/// ###
/// %unsigned 1 pd_ena_xc_a 0x0
/// ###
/// * 1:Enable Auto-crossover, 0:Disable Auto-cross
/// * sets the default of register 16.5:4
/// ###
/// %unsigned 1 ext_coma_a 0x0
/// ###
/// * To shut off FPHY operation if not in use to save power
/// ###
/// %% 5 # Stuffing bits...
/// @ 0x00088 FEPHY_STS (R-)
/// %unsigned 1 misc_speed_s 0x0
/// ###
/// * Speed indicator; 1:100M; 0:10M
/// ###
/// %unsigned 1 misc_duplex_s 0x0
/// ###
/// * Duplex indicator; 1:full-duplex;0:half-duplex
/// ###
/// %unsigned 1 misc_hcd_resolved_s 0x0
/// ###
/// * Speed resolved; 1:resolved;0:not-resolved
/// ###
/// %unsigned 1 misc_link_s 0x0
/// ###
/// * Link status; 1:up; 0:dowm
/// ###
/// %unsigned 1 misc_lpi_s 0x0
/// ###
/// * LPI state; 1: in LPI state; 0 : normal state. The
/// * misc_lpi_s signal shows PHY EEE capability status.
/// * Same as register 17.9
/// ###
/// %unsigned 1 misc_rx_lpi_s 0x0
/// ###
/// * PHY Rx in lpi state
/// ###
/// %unsigned 1 misc_pause_s 0x0
/// ###
/// * Pause indicator; 1: pause; 0: normal
/// ###
/// %unsigned 1 misc_lp_pause_s 0x0
/// ###
/// * Link partner pause indicator; 1: pause; 0:normal
/// ###
/// %unsigned 1 misc_int_s 0x0
/// ###
/// * Port interrupt; 1:interrupt; 0:no interrupt
/// ###
/// %unsigned 1 misc_edet_status_s 0x0
/// ###
/// * Energy detect status; 1: detected; 0:no-detected
/// ###
/// %unsigned 1 tx_latency_mark_a 0x0
/// ###
/// * Transmit enable after TX FIFO
/// ###
/// %unsigned 1 misc_por_reset 0x0
/// ###
/// * Power on reset from analog com
/// ###
/// %% 20 # Stuffing bits...
/// @ 0x0008C SRAM_PWR_CTRL (P-)
/// %unsigned 3 sm_pwr_sram_pwr_ctl 0x0
/// ###
/// * {PDWN,PDLVMC,PDFVSSM} used to control memory leakage.
/// * Default value 000.
/// * Program 110 to reduce leakage when memory not used.
/// ###
/// %% 29 # Stuffing bits...
/// @ 0x00090 SM_POR_AVDD (P-)
/// ###
/// * Bypass POR_AVDD and POR_AVDD33 in case voltage monitor is no longer needed for AVDD33/AVDD18
/// ###
/// %unsigned 1 BYPASS 0x0
/// ###
/// * POR_AVDD and POR_AVDD33 are always enable during boot-up.
/// * This register can bypass POR_AVDD and POR_AVDD33 after boot-up to disable the voltage-monitor feature.
/// ###
/// %unsigned 1 BYPASS_3P3 0x0
/// %% 30 # Stuffing bits...
/// @ 0x00094 (P)
/// # 0x00094 SM_GLOBAL_PADRING
/// $padRing SM_GLOBAL_PADRING REG
/// ###
/// * padRing1
/// ###
/// @ 0x0009C (P)
/// # 0x0009C SM_GPIO_PADRING
/// $padRing SM_GPIO_PADRING REG
/// ###
/// * padRing2
/// ###
/// @ 0x000A4 (P)
/// # 0x000A4 SM_I2C_PADRING
/// $padRing SM_I2C_PADRING REG
/// ###
/// * padRing3
/// ###
/// @ 0x000AC DDC_PAD_CTRL (P-)
/// %unsigned 3 ZN_SM_TW2_SCL 0x0
/// ###
/// * slew rate control for SM_TW2_SCL
/// ###
/// %unsigned 3 ZN_SM_TW2_SDA 0x0
/// ###
/// * slew rate control for SM_TW2_SDA
/// ###
/// %unsigned 3 ZN_SM_TW3_SCL 0x0
/// ###
/// * slew rate control for SM_TW3_SCL
/// ###
/// %unsigned 3 ZN_SM_TW3_SDA 0x0
/// ###
/// * slew rate control for SM_TW3_SDA
/// ###
/// %unsigned 3 ZN_RX_EDDC_SCL 0x0
/// ###
/// * slew rate control for RX_EDDC_SCL
/// ###
/// %unsigned 3 ZN_RX_EDDC_SDA 0x0
/// ###
/// * slew rate control for RX_EDDC_SDA
/// ###
/// %% 14 # Stuffing bits...
/// @ 0x000B0 SM_PWR_OK (R-)
/// %unsigned 1 status
/// ###
/// * SM_PWR_OK status register
/// ###
/// %% 31 # Stuffing bits...
/// @ 0x000B4 (W-)
/// # # Stuffing bytes...
/// %% 6752
/// @ 0x00400 (P)
/// # 0x00400 EDID
/// $EDID EDID REG
/// @ 0x00C00 smPinMuxCntlBus (P-)
/// %unsigned 3 SM_URT0_TXD 0x0
/// ###
/// * smPinMuxCntlBus[0*3+2:0*3] pinMux Control for SM_URT0_TXD
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// %unsigned 3 SM_URT0_RXD 0x0
/// ###
/// * smPinMuxCntlBus[1*3+2:1*3] pinMux Control for SM_URT0_RXD
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// %unsigned 3 SM_URT1_TXD 0x0
/// ###
/// * smPinMuxCntlBus[2*3+2:2*3] pinMux Control for SM_URT1_TXD
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_3 0x3
/// : MODE_4 0x4
/// : MODE_5 0x5
/// : MODE_6 0x6
/// : MODE_7 0x7
/// %unsigned 3 SM_URT1_RXD 0x0
/// ###
/// * smPinMuxCntlBus[3*3+2:3*3] pinMux Control for SM_URT1_RXD
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_3 0x3
/// : MODE_4 0x4
/// : MODE_7 0x7
/// %unsigned 3 SM_SPI2_SS0n 0x0
/// ###
/// * smPinMuxCntlBus[4*3+2:4*3] pinMux Control for SM_SPI2_SS0n
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// %unsigned 3 SM_SPI2_SS1n 0x0
/// ###
/// * smPinMuxCntlBus[5*3+2:5*3] pinMux Control for SM_SPI2_SS1n
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// %unsigned 3 SM_SPI2_SS2n 0x0
/// ###
/// * smPinMuxCntlBus[6*3+2:6*3] pinMux Control for SM_SPI2_SS2n
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_3 0x3
/// : MODE_4 0x4
/// : MODE_5 0x5
/// : MODE_6 0x6
/// %unsigned 3 SM_SPI2_SS3n 0x0
/// ###
/// * smPinMuxCntlBus[7*3+2:7*3] pinMux Control for SM_SPI2_SS3n
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// : MODE_3 0x3
/// : MODE_4 0x4
/// : MODE_6 0x6
/// %unsigned 3 SM_SPI2_SDO 0x0
/// ###
/// * smPinMuxCntlBus[8*3+2:8*3] pinMux Control for SM_SPI2_SDO
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// %unsigned 3 SM_SPI2_SDI 0x0
/// ###
/// * smPinMuxCntlBus[9*3+2:9*3] pinMux Control for SM_SPI2_SDI
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// %% 2 # Stuffing bits...
/// # 0x00C04 smPinMuxCntlBus1
/// %unsigned 3 SM_SPI2_SCLK 0x0
/// ###
/// * smPinMuxCntlBus[10*3+2:10*3] pinMux Control for SM_SPI2_SCLK
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// %unsigned 3 SM_FE_LED0 0x0
/// ###
/// * smPinMuxCntlBus[11*3+2:11*3] pinMux Control for SM_FE_LED[0]
/// ###
/// : MODE_0 0x0
/// : MODE_2 0x2
/// : MODE_7 0x7
/// %unsigned 3 SM_FE_LED1 0x0
/// ###
/// * smPinMuxCntlBus[12*3+2:12*3] pinMux Control for SM_FE_LED[1]
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// %unsigned 3 SM_FE_LED2 0x0
/// ###
/// * smPinMuxCntlBus[13*3+2:13*3] pinMux Control for SM_FE_LED[2]
/// ###
/// : MODE_0 0x0
/// : MODE_2 0x2
/// : MODE_7 0x7
/// %unsigned 3 SM_HDMI_HPD 0x0
/// ###
/// * smPinMuxCntlBus[14*3+2:14*3] pinMux Control for SM_HDMI_HPD
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// %unsigned 3 SM_HDMI_CEC 0x0
/// ###
/// * smPinMuxCntlBus[15*3+2:15*3] pinMux Control for SM_HDMI_CEC
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// %unsigned 3 SM_TW2_SCL 0x0
/// ###
/// * smPinMuxCntlBus[16*3+2:16*3] pinMux Control for SM_TW2_SCL
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// %unsigned 3 SM_TW2_SDA 0x0
/// ###
/// * smPinMuxCntlBus[17*3+2:17*3] pinMux Control for SM_TW2_SDA
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// %unsigned 3 SM_TW3_SCL 0x0
/// ###
/// * smPinMuxCntlBus[18*3+2:18*3] pinMux Control for SM_TW3_SCL
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// %unsigned 3 SM_TW3_SDA 0x0
/// ###
/// * smPinMuxCntlBus[19*3+2:19*3] pinMux Control for SM_TW3_SDA
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// %% 2 # Stuffing bits...
/// # 0x00C08 smPinMuxCntlBus2
/// %unsigned 3 SM_RX_EDDC_SCL 0x0
/// ###
/// * smPinMuxCntlBus[20*3+2:20*3] pinMux Control for SM_RX_EDDC_SCL
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// %unsigned 3 SM_RX_EDDC_SDA 0x0
/// ###
/// * smPinMuxCntlBus[21*3+2:21*3] pinMux Control for SM_RX_EDDC_SDA
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// %unsigned 3 SM_HDMIRX_HPD 0x0
/// ###
/// * smPinMuxCntlBus[22*3+2:22*3] pinMux Control for SM_HDMIRX_HPD
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// %unsigned 3 SM_TMS 0x0
/// ###
/// * smPinMuxCntlBus[23*3+2:23*3] pinMux Control for SM_TMS
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// : MODE_3 0x3
/// %unsigned 3 SM_TDI 0x0
/// ###
/// * smPinMuxCntlBus[24*3+2:24*3] pinMux Control for SM_TDI
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// : MODE_2 0x2
/// : MODE_3 0x3
/// %unsigned 3 SM_TDO 0x0
/// ###
/// * smPinMuxCntlBus[25*3+2:25*3] pinMux Control for SM_TDO
/// ###
/// : MODE_0 0x0
/// : MODE_1 0x1
/// %% 14 # Stuffing bits...
/// @ 0x00C0C SM_URT0_TXDCntl (P-)
/// ###
/// * Pad Control for SM_URT0_TXD
/// ###
/// %unsigned 1 PD_EN 0x1
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x00C10 SM_URT0_RXDCntl (P-)
/// ###
/// * Pad Control for SM_URT0_RXD
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x00C14 SM_URT1_TXDCntl (P-)
/// ###
/// * Pad Control for SM_URT1_TXD
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x00C18 SM_URT1_RXDCntl (P-)
/// ###
/// * Pad Control for SM_URT1_RXD
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x00C1C SM_SPI2_SS0nCntl (P-)
/// ###
/// * Pad Control for SM_SPI2_SS0n
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x00C20 SM_SPI2_SS1nCntl (P-)
/// ###
/// * Pad Control for SM_SPI2_SS1n
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x00C24 SM_SPI2_SS2nCntl (P-)
/// ###
/// * Pad Control for SM_SPI2_SS2n
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x00C28 SM_SPI2_SS3nCntl (P-)
/// ###
/// * Pad Control for SM_SPI2_SS3n
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x00C2C SM_SPI2_SDOCntl (P-)
/// ###
/// * Pad Control for SM_SPI2_SDO
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x00C30 SM_SPI2_SDICntl (P-)
/// ###
/// * Pad Control for SM_SPI2_SDI
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x00C34 SM_SPI2_SCLKCntl (P-)
/// ###
/// * Pad Control for SM_SPI2_SCLK
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x00C38 SM_FE_LED0Cntl (P-)
/// ###
/// * Pad Control for SM_FE_LED[0]
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x00C3C SM_FE_LED1Cntl (P-)
/// ###
/// * Pad Control for SM_FE_LED[1]
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x00C40 SM_FE_LED2Cntl (P-)
/// ###
/// * Pad Control for SM_FE_LED[2]
/// ###
/// %unsigned 1 PD_EN 0x0
/// %unsigned 1 PU_EN 0x0
/// %% 30 # Stuffing bits...
/// @ 0x00C44 (W-)
/// # # Stuffing bytes...
/// %% 7648
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 4096B, bits: 801b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_smSysCtl
#define h_smSysCtl (){}
#define RA_smSysCtl_SM_ID 0x0000
#define BA_smSysCtl_SM_ID_REV_ID 0x0000
#define B16smSysCtl_SM_ID_REV_ID 0x0000
#define LSb32smSysCtl_SM_ID_REV_ID 0
#define LSb16smSysCtl_SM_ID_REV_ID 0
#define bsmSysCtl_SM_ID_REV_ID 4
#define MSK32smSysCtl_SM_ID_REV_ID 0x0000000F
#define BA_smSysCtl_SM_ID_PART_ID 0x0000
#define B16smSysCtl_SM_ID_PART_ID 0x0000
#define LSb32smSysCtl_SM_ID_PART_ID 4
#define LSb16smSysCtl_SM_ID_PART_ID 4
#define bsmSysCtl_SM_ID_PART_ID 16
#define MSK32smSysCtl_SM_ID_PART_ID 0x000FFFF0
#define BA_smSysCtl_SM_ID_MFC_ID 0x0002
#define B16smSysCtl_SM_ID_MFC_ID 0x0002
#define LSb32smSysCtl_SM_ID_MFC_ID 20
#define LSb16smSysCtl_SM_ID_MFC_ID 4
#define bsmSysCtl_SM_ID_MFC_ID 12
#define MSK32smSysCtl_SM_ID_MFC_ID 0xFFF00000
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_CPU_CTRL 0x0004
#define BA_smSysCtl_SM_CPU_CTRL_CPU_RST_GO 0x0004
#define B16smSysCtl_SM_CPU_CTRL_CPU_RST_GO 0x0004
#define LSb32smSysCtl_SM_CPU_CTRL_CPU_RST_GO 0
#define LSb16smSysCtl_SM_CPU_CTRL_CPU_RST_GO 0
#define bsmSysCtl_SM_CPU_CTRL_CPU_RST_GO 1
#define MSK32smSysCtl_SM_CPU_CTRL_CPU_RST_GO 0x00000001
#define BA_smSysCtl_SM_CPU_CTRL_CPU_VINITHI 0x0004
#define B16smSysCtl_SM_CPU_CTRL_CPU_VINITHI 0x0004
#define LSb32smSysCtl_SM_CPU_CTRL_CPU_VINITHI 1
#define LSb16smSysCtl_SM_CPU_CTRL_CPU_VINITHI 1
#define bsmSysCtl_SM_CPU_CTRL_CPU_VINITHI 1
#define MSK32smSysCtl_SM_CPU_CTRL_CPU_VINITHI 0x00000002
#define BA_smSysCtl_SM_CPU_CTRL_CPU_INITRAM 0x0004
#define B16smSysCtl_SM_CPU_CTRL_CPU_INITRAM 0x0004
#define LSb32smSysCtl_SM_CPU_CTRL_CPU_INITRAM 2
#define LSb16smSysCtl_SM_CPU_CTRL_CPU_INITRAM 2
#define bsmSysCtl_SM_CPU_CTRL_CPU_INITRAM 1
#define MSK32smSysCtl_SM_CPU_CTRL_CPU_INITRAM 0x00000004
#define BA_smSysCtl_SM_CPU_CTRL_CPU_BIGEND 0x0004
#define B16smSysCtl_SM_CPU_CTRL_CPU_BIGEND 0x0004
#define LSb32smSysCtl_SM_CPU_CTRL_CPU_BIGEND 3
#define LSb16smSysCtl_SM_CPU_CTRL_CPU_BIGEND 3
#define bsmSysCtl_SM_CPU_CTRL_CPU_BIGEND 1
#define MSK32smSysCtl_SM_CPU_CTRL_CPU_BIGEND 0x00000008
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_RST_CTRL 0x0008
#define BA_smSysCtl_SM_RST_CTRL_SOC_RST_GO 0x0008
#define B16smSysCtl_SM_RST_CTRL_SOC_RST_GO 0x0008
#define LSb32smSysCtl_SM_RST_CTRL_SOC_RST_GO 0
#define LSb16smSysCtl_SM_RST_CTRL_SOC_RST_GO 0
#define bsmSysCtl_SM_RST_CTRL_SOC_RST_GO 1
#define MSK32smSysCtl_SM_RST_CTRL_SOC_RST_GO 0x00000001
#define BA_smSysCtl_SM_RST_CTRL_APB_RST_GO 0x0008
#define B16smSysCtl_SM_RST_CTRL_APB_RST_GO 0x0008
#define LSb32smSysCtl_SM_RST_CTRL_APB_RST_GO 1
#define LSb16smSysCtl_SM_RST_CTRL_APB_RST_GO 1
#define bsmSysCtl_SM_RST_CTRL_APB_RST_GO 1
#define MSK32smSysCtl_SM_RST_CTRL_APB_RST_GO 0x00000002
#define BA_smSysCtl_SM_RST_CTRL_SXBAR_RST_GO 0x0008
#define B16smSysCtl_SM_RST_CTRL_SXBAR_RST_GO 0x0008
#define LSb32smSysCtl_SM_RST_CTRL_SXBAR_RST_GO 2
#define LSb16smSysCtl_SM_RST_CTRL_SXBAR_RST_GO 2
#define bsmSysCtl_SM_RST_CTRL_SXBAR_RST_GO 1
#define MSK32smSysCtl_SM_RST_CTRL_SXBAR_RST_GO 0x00000004
#define BA_smSysCtl_SM_RST_CTRL_WOL_RST_GO 0x0008
#define B16smSysCtl_SM_RST_CTRL_WOL_RST_GO 0x0008
#define LSb32smSysCtl_SM_RST_CTRL_WOL_RST_GO 3
#define LSb16smSysCtl_SM_RST_CTRL_WOL_RST_GO 3
#define bsmSysCtl_SM_RST_CTRL_WOL_RST_GO 1
#define MSK32smSysCtl_SM_RST_CTRL_WOL_RST_GO 0x00000008
#define BA_smSysCtl_SM_RST_CTRL_FEPHY_RST_GO 0x0008
#define B16smSysCtl_SM_RST_CTRL_FEPHY_RST_GO 0x0008
#define LSb32smSysCtl_SM_RST_CTRL_FEPHY_RST_GO 4
#define LSb16smSysCtl_SM_RST_CTRL_FEPHY_RST_GO 4
#define bsmSysCtl_SM_RST_CTRL_FEPHY_RST_GO 1
#define MSK32smSysCtl_SM_RST_CTRL_FEPHY_RST_GO 0x00000010
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_RST_STATUS 0x000C
#define BA_smSysCtl_SM_RST_STATUS_RST_WD_0 0x000C
#define B16smSysCtl_SM_RST_STATUS_RST_WD_0 0x000C
#define LSb32smSysCtl_SM_RST_STATUS_RST_WD_0 0
#define LSb16smSysCtl_SM_RST_STATUS_RST_WD_0 0
#define bsmSysCtl_SM_RST_STATUS_RST_WD_0 1
#define MSK32smSysCtl_SM_RST_STATUS_RST_WD_0 0x00000001
#define BA_smSysCtl_SM_RST_STATUS_RST_WD_1 0x000C
#define B16smSysCtl_SM_RST_STATUS_RST_WD_1 0x000C
#define LSb32smSysCtl_SM_RST_STATUS_RST_WD_1 1
#define LSb16smSysCtl_SM_RST_STATUS_RST_WD_1 1
#define bsmSysCtl_SM_RST_STATUS_RST_WD_1 1
#define MSK32smSysCtl_SM_RST_STATUS_RST_WD_1 0x00000002
#define BA_smSysCtl_SM_RST_STATUS_RST_WD_2 0x000C
#define B16smSysCtl_SM_RST_STATUS_RST_WD_2 0x000C
#define LSb32smSysCtl_SM_RST_STATUS_RST_WD_2 2
#define LSb16smSysCtl_SM_RST_STATUS_RST_WD_2 2
#define bsmSysCtl_SM_RST_STATUS_RST_WD_2 1
#define MSK32smSysCtl_SM_RST_STATUS_RST_WD_2 0x00000004
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_STRP_STATUS 0x0010
#define BA_smSysCtl_SM_STRP_STATUS_BOOT_MODE 0x0010
#define B16smSysCtl_SM_STRP_STATUS_BOOT_MODE 0x0010
#define LSb32smSysCtl_SM_STRP_STATUS_BOOT_MODE 0
#define LSb16smSysCtl_SM_STRP_STATUS_BOOT_MODE 0
#define bsmSysCtl_SM_STRP_STATUS_BOOT_MODE 1
#define MSK32smSysCtl_SM_STRP_STATUS_BOOT_MODE 0x00000001
#define BA_smSysCtl_SM_STRP_STATUS_STRP_1 0x0010
#define B16smSysCtl_SM_STRP_STATUS_STRP_1 0x0010
#define LSb32smSysCtl_SM_STRP_STATUS_STRP_1 1
#define LSb16smSysCtl_SM_STRP_STATUS_STRP_1 1
#define bsmSysCtl_SM_STRP_STATUS_STRP_1 1
#define MSK32smSysCtl_SM_STRP_STATUS_STRP_1 0x00000002
#define BA_smSysCtl_SM_STRP_STATUS_STRP_2 0x0010
#define B16smSysCtl_SM_STRP_STATUS_STRP_2 0x0010
#define LSb32smSysCtl_SM_STRP_STATUS_STRP_2 2
#define LSb16smSysCtl_SM_STRP_STATUS_STRP_2 2
#define bsmSysCtl_SM_STRP_STATUS_STRP_2 1
#define MSK32smSysCtl_SM_STRP_STATUS_STRP_2 0x00000004
#define BA_smSysCtl_SM_STRP_STATUS_STRP_3 0x0010
#define B16smSysCtl_SM_STRP_STATUS_STRP_3 0x0010
#define LSb32smSysCtl_SM_STRP_STATUS_STRP_3 3
#define LSb16smSysCtl_SM_STRP_STATUS_STRP_3 3
#define bsmSysCtl_SM_STRP_STATUS_STRP_3 1
#define MSK32smSysCtl_SM_STRP_STATUS_STRP_3 0x00000008
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_CTRL 0x0014
#define BA_smSysCtl_SM_CTRL_ISO_EN 0x0014
#define B16smSysCtl_SM_CTRL_ISO_EN 0x0014
#define LSb32smSysCtl_SM_CTRL_ISO_EN 0
#define LSb16smSysCtl_SM_CTRL_ISO_EN 0
#define bsmSysCtl_SM_CTRL_ISO_EN 1
#define MSK32smSysCtl_SM_CTRL_ISO_EN 0x00000001
#define BA_smSysCtl_SM_CTRL_SM2SOC_SW_INTR 0x0014
#define B16smSysCtl_SM_CTRL_SM2SOC_SW_INTR 0x0014
#define LSb32smSysCtl_SM_CTRL_SM2SOC_SW_INTR 1
#define LSb16smSysCtl_SM_CTRL_SM2SOC_SW_INTR 1
#define bsmSysCtl_SM_CTRL_SM2SOC_SW_INTR 1
#define MSK32smSysCtl_SM_CTRL_SM2SOC_SW_INTR 0x00000002
#define BA_smSysCtl_SM_CTRL_SOC2SM_SW_INTR 0x0014
#define B16smSysCtl_SM_CTRL_SOC2SM_SW_INTR 0x0014
#define LSb32smSysCtl_SM_CTRL_SOC2SM_SW_INTR 2
#define LSb16smSysCtl_SM_CTRL_SOC2SM_SW_INTR 2
#define bsmSysCtl_SM_CTRL_SOC2SM_SW_INTR 1
#define MSK32smSysCtl_SM_CTRL_SOC2SM_SW_INTR 0x00000004
#define BA_smSysCtl_SM_CTRL_REV_0 0x0014
#define B16smSysCtl_SM_CTRL_REV_0 0x0014
#define LSb32smSysCtl_SM_CTRL_REV_0 3
#define LSb16smSysCtl_SM_CTRL_REV_0 3
#define bsmSysCtl_SM_CTRL_REV_0 2
#define MSK32smSysCtl_SM_CTRL_REV_0 0x00000018
#define BA_smSysCtl_SM_CTRL_ADC_SEL 0x0014
#define B16smSysCtl_SM_CTRL_ADC_SEL 0x0014
#define LSb32smSysCtl_SM_CTRL_ADC_SEL 5
#define LSb16smSysCtl_SM_CTRL_ADC_SEL 5
#define bsmSysCtl_SM_CTRL_ADC_SEL 4
#define MSK32smSysCtl_SM_CTRL_ADC_SEL 0x000001E0
#define BA_smSysCtl_SM_CTRL_ADC_PU 0x0015
#define B16smSysCtl_SM_CTRL_ADC_PU 0x0014
#define LSb32smSysCtl_SM_CTRL_ADC_PU 9
#define LSb16smSysCtl_SM_CTRL_ADC_PU 9
#define bsmSysCtl_SM_CTRL_ADC_PU 1
#define MSK32smSysCtl_SM_CTRL_ADC_PU 0x00000200
#define BA_smSysCtl_SM_CTRL_ADC_CKSEL 0x0015
#define B16smSysCtl_SM_CTRL_ADC_CKSEL 0x0014
#define LSb32smSysCtl_SM_CTRL_ADC_CKSEL 10
#define LSb16smSysCtl_SM_CTRL_ADC_CKSEL 10
#define bsmSysCtl_SM_CTRL_ADC_CKSEL 2
#define MSK32smSysCtl_SM_CTRL_ADC_CKSEL 0x00000C00
#define BA_smSysCtl_SM_CTRL_ADC_START 0x0015
#define B16smSysCtl_SM_CTRL_ADC_START 0x0014
#define LSb32smSysCtl_SM_CTRL_ADC_START 12
#define LSb16smSysCtl_SM_CTRL_ADC_START 12
#define bsmSysCtl_SM_CTRL_ADC_START 1
#define MSK32smSysCtl_SM_CTRL_ADC_START 0x00001000
#define BA_smSysCtl_SM_CTRL_ADC_RESET 0x0015
#define B16smSysCtl_SM_CTRL_ADC_RESET 0x0014
#define LSb32smSysCtl_SM_CTRL_ADC_RESET 13
#define LSb16smSysCtl_SM_CTRL_ADC_RESET 13
#define bsmSysCtl_SM_CTRL_ADC_RESET 1
#define MSK32smSysCtl_SM_CTRL_ADC_RESET 0x00002000
#define BA_smSysCtl_SM_CTRL_ADC_BG_RDY 0x0015
#define B16smSysCtl_SM_CTRL_ADC_BG_RDY 0x0014
#define LSb32smSysCtl_SM_CTRL_ADC_BG_RDY 14
#define LSb16smSysCtl_SM_CTRL_ADC_BG_RDY 14
#define bsmSysCtl_SM_CTRL_ADC_BG_RDY 1
#define MSK32smSysCtl_SM_CTRL_ADC_BG_RDY 0x00004000
#define BA_smSysCtl_SM_CTRL_ADC_CONT 0x0015
#define B16smSysCtl_SM_CTRL_ADC_CONT 0x0014
#define LSb32smSysCtl_SM_CTRL_ADC_CONT 15
#define LSb16smSysCtl_SM_CTRL_ADC_CONT 15
#define bsmSysCtl_SM_CTRL_ADC_CONT 1
#define MSK32smSysCtl_SM_CTRL_ADC_CONT 0x00008000
#define BA_smSysCtl_SM_CTRL_ADC_BUF_EN 0x0016
#define B16smSysCtl_SM_CTRL_ADC_BUF_EN 0x0016
#define LSb32smSysCtl_SM_CTRL_ADC_BUF_EN 16
#define LSb16smSysCtl_SM_CTRL_ADC_BUF_EN 0
#define bsmSysCtl_SM_CTRL_ADC_BUF_EN 1
#define MSK32smSysCtl_SM_CTRL_ADC_BUF_EN 0x00010000
#define BA_smSysCtl_SM_CTRL_ADC_VREF_SEL 0x0016
#define B16smSysCtl_SM_CTRL_ADC_VREF_SEL 0x0016
#define LSb32smSysCtl_SM_CTRL_ADC_VREF_SEL 17
#define LSb16smSysCtl_SM_CTRL_ADC_VREF_SEL 1
#define bsmSysCtl_SM_CTRL_ADC_VREF_SEL 1
#define MSK32smSysCtl_SM_CTRL_ADC_VREF_SEL 0x00020000
#define BA_smSysCtl_SM_CTRL_ADC_ROTATE_SEL 0x0016
#define B16smSysCtl_SM_CTRL_ADC_ROTATE_SEL 0x0016
#define LSb32smSysCtl_SM_CTRL_ADC_ROTATE_SEL 18
#define LSb16smSysCtl_SM_CTRL_ADC_ROTATE_SEL 2
#define bsmSysCtl_SM_CTRL_ADC_ROTATE_SEL 1
#define MSK32smSysCtl_SM_CTRL_ADC_ROTATE_SEL 0x00040000
#define BA_smSysCtl_SM_CTRL_TSEN_EN 0x0016
#define B16smSysCtl_SM_CTRL_TSEN_EN 0x0016
#define LSb32smSysCtl_SM_CTRL_TSEN_EN 19
#define LSb16smSysCtl_SM_CTRL_TSEN_EN 3
#define bsmSysCtl_SM_CTRL_TSEN_EN 1
#define MSK32smSysCtl_SM_CTRL_TSEN_EN 0x00080000
#define BA_smSysCtl_SM_CTRL_TSEN_CLK_EN 0x0016
#define B16smSysCtl_SM_CTRL_TSEN_CLK_EN 0x0016
#define LSb32smSysCtl_SM_CTRL_TSEN_CLK_EN 20
#define LSb16smSysCtl_SM_CTRL_TSEN_CLK_EN 4
#define bsmSysCtl_SM_CTRL_TSEN_CLK_EN 1
#define MSK32smSysCtl_SM_CTRL_TSEN_CLK_EN 0x00100000
#define BA_smSysCtl_SM_CTRL_TSEN_CLK_SEL 0x0016
#define B16smSysCtl_SM_CTRL_TSEN_CLK_SEL 0x0016
#define LSb32smSysCtl_SM_CTRL_TSEN_CLK_SEL 21
#define LSb16smSysCtl_SM_CTRL_TSEN_CLK_SEL 5
#define bsmSysCtl_SM_CTRL_TSEN_CLK_SEL 1
#define MSK32smSysCtl_SM_CTRL_TSEN_CLK_SEL 0x00200000
#define BA_smSysCtl_SM_CTRL_TSEN_MODE_SEL 0x0016
#define B16smSysCtl_SM_CTRL_TSEN_MODE_SEL 0x0016
#define LSb32smSysCtl_SM_CTRL_TSEN_MODE_SEL 22
#define LSb16smSysCtl_SM_CTRL_TSEN_MODE_SEL 6
#define bsmSysCtl_SM_CTRL_TSEN_MODE_SEL 1
#define MSK32smSysCtl_SM_CTRL_TSEN_MODE_SEL 0x00400000
#define BA_smSysCtl_SM_CTRL_TSEN_ADC_CAL 0x0016
#define B16smSysCtl_SM_CTRL_TSEN_ADC_CAL 0x0016
#define LSb32smSysCtl_SM_CTRL_TSEN_ADC_CAL 23
#define LSb16smSysCtl_SM_CTRL_TSEN_ADC_CAL 7
#define bsmSysCtl_SM_CTRL_TSEN_ADC_CAL 2
#define MSK32smSysCtl_SM_CTRL_TSEN_ADC_CAL 0x01800000
#define BA_smSysCtl_SM_CTRL_TSEN_ADC_TST_SEL 0x0017
#define B16smSysCtl_SM_CTRL_TSEN_ADC_TST_SEL 0x0016
#define LSb32smSysCtl_SM_CTRL_TSEN_ADC_TST_SEL 25
#define LSb16smSysCtl_SM_CTRL_TSEN_ADC_TST_SEL 9
#define bsmSysCtl_SM_CTRL_TSEN_ADC_TST_SEL 5
#define MSK32smSysCtl_SM_CTRL_TSEN_ADC_TST_SEL 0x3E000000
#define BA_smSysCtl_SM_CTRL_TSEN_RESET 0x0017
#define B16smSysCtl_SM_CTRL_TSEN_RESET 0x0016
#define LSb32smSysCtl_SM_CTRL_TSEN_RESET 30
#define LSb16smSysCtl_SM_CTRL_TSEN_RESET 14
#define bsmSysCtl_SM_CTRL_TSEN_RESET 1
#define MSK32smSysCtl_SM_CTRL_TSEN_RESET 0x40000000
#define BA_smSysCtl_SM_CTRL_TSEN_ADC_ISO_EN 0x0017
#define B16smSysCtl_SM_CTRL_TSEN_ADC_ISO_EN 0x0016
#define LSb32smSysCtl_SM_CTRL_TSEN_ADC_ISO_EN 31
#define LSb16smSysCtl_SM_CTRL_TSEN_ADC_ISO_EN 15
#define bsmSysCtl_SM_CTRL_TSEN_ADC_ISO_EN 1
#define MSK32smSysCtl_SM_CTRL_TSEN_ADC_ISO_EN 0x80000000
#define RA_smSysCtl_SM_CTRL1 0x0018
#define BA_smSysCtl_SM_CTRL_EDID_INTR_CLR 0x0018
#define B16smSysCtl_SM_CTRL_EDID_INTR_CLR 0x0018
#define LSb32smSysCtl_SM_CTRL_EDID_INTR_CLR 0
#define LSb16smSysCtl_SM_CTRL_EDID_INTR_CLR 0
#define bsmSysCtl_SM_CTRL_EDID_INTR_CLR 1
#define MSK32smSysCtl_SM_CTRL_EDID_INTR_CLR 0x00000001
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_ADC_CTRL 0x001C
#define BA_smSysCtl_SM_ADC_CTRL_TSEN_DAT_LT 0x001C
#define B16smSysCtl_SM_ADC_CTRL_TSEN_DAT_LT 0x001C
#define LSb32smSysCtl_SM_ADC_CTRL_TSEN_DAT_LT 0
#define LSb16smSysCtl_SM_ADC_CTRL_TSEN_DAT_LT 0
#define bsmSysCtl_SM_ADC_CTRL_TSEN_DAT_LT 5
#define MSK32smSysCtl_SM_ADC_CTRL_TSEN_DAT_LT 0x0000001F
#define BA_smSysCtl_SM_ADC_CTRL_ADC_DAT_LT 0x001C
#define B16smSysCtl_SM_ADC_CTRL_ADC_DAT_LT 0x001C
#define LSb32smSysCtl_SM_ADC_CTRL_ADC_DAT_LT 5
#define LSb16smSysCtl_SM_ADC_CTRL_ADC_DAT_LT 5
#define bsmSysCtl_SM_ADC_CTRL_ADC_DAT_LT 5
#define MSK32smSysCtl_SM_ADC_CTRL_ADC_DAT_LT 0x000003E0
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_ADC_STATUS 0x0020
#define BA_smSysCtl_SM_ADC_STATUS_CH0_DATA_RDY 0x0020
#define B16smSysCtl_SM_ADC_STATUS_CH0_DATA_RDY 0x0020
#define LSb32smSysCtl_SM_ADC_STATUS_CH0_DATA_RDY 0
#define LSb16smSysCtl_SM_ADC_STATUS_CH0_DATA_RDY 0
#define bsmSysCtl_SM_ADC_STATUS_CH0_DATA_RDY 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH0_DATA_RDY 0x00000001
#define BA_smSysCtl_SM_ADC_STATUS_CH1_DATA_RDY 0x0020
#define B16smSysCtl_SM_ADC_STATUS_CH1_DATA_RDY 0x0020
#define LSb32smSysCtl_SM_ADC_STATUS_CH1_DATA_RDY 1
#define LSb16smSysCtl_SM_ADC_STATUS_CH1_DATA_RDY 1
#define bsmSysCtl_SM_ADC_STATUS_CH1_DATA_RDY 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH1_DATA_RDY 0x00000002
#define BA_smSysCtl_SM_ADC_STATUS_CH2_DATA_RDY 0x0020
#define B16smSysCtl_SM_ADC_STATUS_CH2_DATA_RDY 0x0020
#define LSb32smSysCtl_SM_ADC_STATUS_CH2_DATA_RDY 2
#define LSb16smSysCtl_SM_ADC_STATUS_CH2_DATA_RDY 2
#define bsmSysCtl_SM_ADC_STATUS_CH2_DATA_RDY 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH2_DATA_RDY 0x00000004
#define BA_smSysCtl_SM_ADC_STATUS_CH3_DATA_RDY 0x0020
#define B16smSysCtl_SM_ADC_STATUS_CH3_DATA_RDY 0x0020
#define LSb32smSysCtl_SM_ADC_STATUS_CH3_DATA_RDY 3
#define LSb16smSysCtl_SM_ADC_STATUS_CH3_DATA_RDY 3
#define bsmSysCtl_SM_ADC_STATUS_CH3_DATA_RDY 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH3_DATA_RDY 0x00000008
#define BA_smSysCtl_SM_ADC_STATUS_CH4_DATA_RDY 0x0020
#define B16smSysCtl_SM_ADC_STATUS_CH4_DATA_RDY 0x0020
#define LSb32smSysCtl_SM_ADC_STATUS_CH4_DATA_RDY 4
#define LSb16smSysCtl_SM_ADC_STATUS_CH4_DATA_RDY 4
#define bsmSysCtl_SM_ADC_STATUS_CH4_DATA_RDY 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH4_DATA_RDY 0x00000010
#define BA_smSysCtl_SM_ADC_STATUS_CH5_DATA_RDY 0x0020
#define B16smSysCtl_SM_ADC_STATUS_CH5_DATA_RDY 0x0020
#define LSb32smSysCtl_SM_ADC_STATUS_CH5_DATA_RDY 5
#define LSb16smSysCtl_SM_ADC_STATUS_CH5_DATA_RDY 5
#define bsmSysCtl_SM_ADC_STATUS_CH5_DATA_RDY 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH5_DATA_RDY 0x00000020
#define BA_smSysCtl_SM_ADC_STATUS_CH6_DATA_RDY 0x0020
#define B16smSysCtl_SM_ADC_STATUS_CH6_DATA_RDY 0x0020
#define LSb32smSysCtl_SM_ADC_STATUS_CH6_DATA_RDY 6
#define LSb16smSysCtl_SM_ADC_STATUS_CH6_DATA_RDY 6
#define bsmSysCtl_SM_ADC_STATUS_CH6_DATA_RDY 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH6_DATA_RDY 0x00000040
#define BA_smSysCtl_SM_ADC_STATUS_CH7_DATA_RDY 0x0020
#define B16smSysCtl_SM_ADC_STATUS_CH7_DATA_RDY 0x0020
#define LSb32smSysCtl_SM_ADC_STATUS_CH7_DATA_RDY 7
#define LSb16smSysCtl_SM_ADC_STATUS_CH7_DATA_RDY 7
#define bsmSysCtl_SM_ADC_STATUS_CH7_DATA_RDY 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH7_DATA_RDY 0x00000080
#define BA_smSysCtl_SM_ADC_STATUS_CH8_DATA_RDY 0x0021
#define B16smSysCtl_SM_ADC_STATUS_CH8_DATA_RDY 0x0020
#define LSb32smSysCtl_SM_ADC_STATUS_CH8_DATA_RDY 8
#define LSb16smSysCtl_SM_ADC_STATUS_CH8_DATA_RDY 8
#define bsmSysCtl_SM_ADC_STATUS_CH8_DATA_RDY 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH8_DATA_RDY 0x00000100
#define BA_smSysCtl_SM_ADC_STATUS_CH9_DATA_RDY 0x0021
#define B16smSysCtl_SM_ADC_STATUS_CH9_DATA_RDY 0x0020
#define LSb32smSysCtl_SM_ADC_STATUS_CH9_DATA_RDY 9
#define LSb16smSysCtl_SM_ADC_STATUS_CH9_DATA_RDY 9
#define bsmSysCtl_SM_ADC_STATUS_CH9_DATA_RDY 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH9_DATA_RDY 0x00000200
#define BA_smSysCtl_SM_ADC_STATUS_CH10_DATA_RDY 0x0021
#define B16smSysCtl_SM_ADC_STATUS_CH10_DATA_RDY 0x0020
#define LSb32smSysCtl_SM_ADC_STATUS_CH10_DATA_RDY 10
#define LSb16smSysCtl_SM_ADC_STATUS_CH10_DATA_RDY 10
#define bsmSysCtl_SM_ADC_STATUS_CH10_DATA_RDY 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH10_DATA_RDY 0x00000400
#define BA_smSysCtl_SM_ADC_STATUS_CH11_DATA_RDY 0x0021
#define B16smSysCtl_SM_ADC_STATUS_CH11_DATA_RDY 0x0020
#define LSb32smSysCtl_SM_ADC_STATUS_CH11_DATA_RDY 11
#define LSb16smSysCtl_SM_ADC_STATUS_CH11_DATA_RDY 11
#define bsmSysCtl_SM_ADC_STATUS_CH11_DATA_RDY 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH11_DATA_RDY 0x00000800
#define BA_smSysCtl_SM_ADC_STATUS_CH12_DATA_RDY 0x0021
#define B16smSysCtl_SM_ADC_STATUS_CH12_DATA_RDY 0x0020
#define LSb32smSysCtl_SM_ADC_STATUS_CH12_DATA_RDY 12
#define LSb16smSysCtl_SM_ADC_STATUS_CH12_DATA_RDY 12
#define bsmSysCtl_SM_ADC_STATUS_CH12_DATA_RDY 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH12_DATA_RDY 0x00001000
#define BA_smSysCtl_SM_ADC_STATUS_CH13_DATA_RDY 0x0021
#define B16smSysCtl_SM_ADC_STATUS_CH13_DATA_RDY 0x0020
#define LSb32smSysCtl_SM_ADC_STATUS_CH13_DATA_RDY 13
#define LSb16smSysCtl_SM_ADC_STATUS_CH13_DATA_RDY 13
#define bsmSysCtl_SM_ADC_STATUS_CH13_DATA_RDY 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH13_DATA_RDY 0x00002000
#define BA_smSysCtl_SM_ADC_STATUS_CH14_DATA_RDY 0x0021
#define B16smSysCtl_SM_ADC_STATUS_CH14_DATA_RDY 0x0020
#define LSb32smSysCtl_SM_ADC_STATUS_CH14_DATA_RDY 14
#define LSb16smSysCtl_SM_ADC_STATUS_CH14_DATA_RDY 14
#define bsmSysCtl_SM_ADC_STATUS_CH14_DATA_RDY 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH14_DATA_RDY 0x00004000
#define BA_smSysCtl_SM_ADC_STATUS_CH15_DATA_RDY 0x0021
#define B16smSysCtl_SM_ADC_STATUS_CH15_DATA_RDY 0x0020
#define LSb32smSysCtl_SM_ADC_STATUS_CH15_DATA_RDY 15
#define LSb16smSysCtl_SM_ADC_STATUS_CH15_DATA_RDY 15
#define bsmSysCtl_SM_ADC_STATUS_CH15_DATA_RDY 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH15_DATA_RDY 0x00008000
#define BA_smSysCtl_SM_ADC_STATUS_CH0_INT_EN 0x0022
#define B16smSysCtl_SM_ADC_STATUS_CH0_INT_EN 0x0022
#define LSb32smSysCtl_SM_ADC_STATUS_CH0_INT_EN 16
#define LSb16smSysCtl_SM_ADC_STATUS_CH0_INT_EN 0
#define bsmSysCtl_SM_ADC_STATUS_CH0_INT_EN 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH0_INT_EN 0x00010000
#define BA_smSysCtl_SM_ADC_STATUS_CH1_INT_EN 0x0022
#define B16smSysCtl_SM_ADC_STATUS_CH1_INT_EN 0x0022
#define LSb32smSysCtl_SM_ADC_STATUS_CH1_INT_EN 17
#define LSb16smSysCtl_SM_ADC_STATUS_CH1_INT_EN 1
#define bsmSysCtl_SM_ADC_STATUS_CH1_INT_EN 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH1_INT_EN 0x00020000
#define BA_smSysCtl_SM_ADC_STATUS_CH2_INT_EN 0x0022
#define B16smSysCtl_SM_ADC_STATUS_CH2_INT_EN 0x0022
#define LSb32smSysCtl_SM_ADC_STATUS_CH2_INT_EN 18
#define LSb16smSysCtl_SM_ADC_STATUS_CH2_INT_EN 2
#define bsmSysCtl_SM_ADC_STATUS_CH2_INT_EN 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH2_INT_EN 0x00040000
#define BA_smSysCtl_SM_ADC_STATUS_CH3_INT_EN 0x0022
#define B16smSysCtl_SM_ADC_STATUS_CH3_INT_EN 0x0022
#define LSb32smSysCtl_SM_ADC_STATUS_CH3_INT_EN 19
#define LSb16smSysCtl_SM_ADC_STATUS_CH3_INT_EN 3
#define bsmSysCtl_SM_ADC_STATUS_CH3_INT_EN 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH3_INT_EN 0x00080000
#define BA_smSysCtl_SM_ADC_STATUS_CH4_INT_EN 0x0022
#define B16smSysCtl_SM_ADC_STATUS_CH4_INT_EN 0x0022
#define LSb32smSysCtl_SM_ADC_STATUS_CH4_INT_EN 20
#define LSb16smSysCtl_SM_ADC_STATUS_CH4_INT_EN 4
#define bsmSysCtl_SM_ADC_STATUS_CH4_INT_EN 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH4_INT_EN 0x00100000
#define BA_smSysCtl_SM_ADC_STATUS_CH5_INT_EN 0x0022
#define B16smSysCtl_SM_ADC_STATUS_CH5_INT_EN 0x0022
#define LSb32smSysCtl_SM_ADC_STATUS_CH5_INT_EN 21
#define LSb16smSysCtl_SM_ADC_STATUS_CH5_INT_EN 5
#define bsmSysCtl_SM_ADC_STATUS_CH5_INT_EN 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH5_INT_EN 0x00200000
#define BA_smSysCtl_SM_ADC_STATUS_CH6_INT_EN 0x0022
#define B16smSysCtl_SM_ADC_STATUS_CH6_INT_EN 0x0022
#define LSb32smSysCtl_SM_ADC_STATUS_CH6_INT_EN 22
#define LSb16smSysCtl_SM_ADC_STATUS_CH6_INT_EN 6
#define bsmSysCtl_SM_ADC_STATUS_CH6_INT_EN 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH6_INT_EN 0x00400000
#define BA_smSysCtl_SM_ADC_STATUS_CH7_INT_EN 0x0022
#define B16smSysCtl_SM_ADC_STATUS_CH7_INT_EN 0x0022
#define LSb32smSysCtl_SM_ADC_STATUS_CH7_INT_EN 23
#define LSb16smSysCtl_SM_ADC_STATUS_CH7_INT_EN 7
#define bsmSysCtl_SM_ADC_STATUS_CH7_INT_EN 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH7_INT_EN 0x00800000
#define BA_smSysCtl_SM_ADC_STATUS_CH8_INT_EN 0x0023
#define B16smSysCtl_SM_ADC_STATUS_CH8_INT_EN 0x0022
#define LSb32smSysCtl_SM_ADC_STATUS_CH8_INT_EN 24
#define LSb16smSysCtl_SM_ADC_STATUS_CH8_INT_EN 8
#define bsmSysCtl_SM_ADC_STATUS_CH8_INT_EN 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH8_INT_EN 0x01000000
#define BA_smSysCtl_SM_ADC_STATUS_CH9_INT_EN 0x0023
#define B16smSysCtl_SM_ADC_STATUS_CH9_INT_EN 0x0022
#define LSb32smSysCtl_SM_ADC_STATUS_CH9_INT_EN 25
#define LSb16smSysCtl_SM_ADC_STATUS_CH9_INT_EN 9
#define bsmSysCtl_SM_ADC_STATUS_CH9_INT_EN 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH9_INT_EN 0x02000000
#define BA_smSysCtl_SM_ADC_STATUS_CH10_INT_EN 0x0023
#define B16smSysCtl_SM_ADC_STATUS_CH10_INT_EN 0x0022
#define LSb32smSysCtl_SM_ADC_STATUS_CH10_INT_EN 26
#define LSb16smSysCtl_SM_ADC_STATUS_CH10_INT_EN 10
#define bsmSysCtl_SM_ADC_STATUS_CH10_INT_EN 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH10_INT_EN 0x04000000
#define BA_smSysCtl_SM_ADC_STATUS_CH11_INT_EN 0x0023
#define B16smSysCtl_SM_ADC_STATUS_CH11_INT_EN 0x0022
#define LSb32smSysCtl_SM_ADC_STATUS_CH11_INT_EN 27
#define LSb16smSysCtl_SM_ADC_STATUS_CH11_INT_EN 11
#define bsmSysCtl_SM_ADC_STATUS_CH11_INT_EN 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH11_INT_EN 0x08000000
#define BA_smSysCtl_SM_ADC_STATUS_CH12_INT_EN 0x0023
#define B16smSysCtl_SM_ADC_STATUS_CH12_INT_EN 0x0022
#define LSb32smSysCtl_SM_ADC_STATUS_CH12_INT_EN 28
#define LSb16smSysCtl_SM_ADC_STATUS_CH12_INT_EN 12
#define bsmSysCtl_SM_ADC_STATUS_CH12_INT_EN 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH12_INT_EN 0x10000000
#define BA_smSysCtl_SM_ADC_STATUS_CH13_INT_EN 0x0023
#define B16smSysCtl_SM_ADC_STATUS_CH13_INT_EN 0x0022
#define LSb32smSysCtl_SM_ADC_STATUS_CH13_INT_EN 29
#define LSb16smSysCtl_SM_ADC_STATUS_CH13_INT_EN 13
#define bsmSysCtl_SM_ADC_STATUS_CH13_INT_EN 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH13_INT_EN 0x20000000
#define BA_smSysCtl_SM_ADC_STATUS_CH14_INT_EN 0x0023
#define B16smSysCtl_SM_ADC_STATUS_CH14_INT_EN 0x0022
#define LSb32smSysCtl_SM_ADC_STATUS_CH14_INT_EN 30
#define LSb16smSysCtl_SM_ADC_STATUS_CH14_INT_EN 14
#define bsmSysCtl_SM_ADC_STATUS_CH14_INT_EN 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH14_INT_EN 0x40000000
#define BA_smSysCtl_SM_ADC_STATUS_CH15_INT_EN 0x0023
#define B16smSysCtl_SM_ADC_STATUS_CH15_INT_EN 0x0022
#define LSb32smSysCtl_SM_ADC_STATUS_CH15_INT_EN 31
#define LSb16smSysCtl_SM_ADC_STATUS_CH15_INT_EN 15
#define bsmSysCtl_SM_ADC_STATUS_CH15_INT_EN 1
#define MSK32smSysCtl_SM_ADC_STATUS_CH15_INT_EN 0x80000000
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_ADC_DATA 0x0024
#define BA_smSysCtl_SM_ADC_DATA_ADC_DATA 0x0024
#define B16smSysCtl_SM_ADC_DATA_ADC_DATA 0x0024
#define LSb32smSysCtl_SM_ADC_DATA_ADC_DATA 0
#define LSb16smSysCtl_SM_ADC_DATA_ADC_DATA 0
#define bsmSysCtl_SM_ADC_DATA_ADC_DATA 10
#define MSK32smSysCtl_SM_ADC_DATA_ADC_DATA 0x000003FF
///////////////////////////////////////////////////////////
#define RA_smSysCtl_TSEN_ADC_STATUS 0x0028
#define BA_smSysCtl_TSEN_ADC_STATUS_DATA_RDY 0x0028
#define B16smSysCtl_TSEN_ADC_STATUS_DATA_RDY 0x0028
#define LSb32smSysCtl_TSEN_ADC_STATUS_DATA_RDY 0
#define LSb16smSysCtl_TSEN_ADC_STATUS_DATA_RDY 0
#define bsmSysCtl_TSEN_ADC_STATUS_DATA_RDY 1
#define MSK32smSysCtl_TSEN_ADC_STATUS_DATA_RDY 0x00000001
#define BA_smSysCtl_TSEN_ADC_STATUS_INT_EN 0x0028
#define B16smSysCtl_TSEN_ADC_STATUS_INT_EN 0x0028
#define LSb32smSysCtl_TSEN_ADC_STATUS_INT_EN 1
#define LSb16smSysCtl_TSEN_ADC_STATUS_INT_EN 1
#define bsmSysCtl_TSEN_ADC_STATUS_INT_EN 1
#define MSK32smSysCtl_TSEN_ADC_STATUS_INT_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_smSysCtl_TSEN_ADC_DATA 0x002C
#define BA_smSysCtl_TSEN_ADC_DATA_ADC_DATA 0x002C
#define B16smSysCtl_TSEN_ADC_DATA_ADC_DATA 0x002C
#define LSb32smSysCtl_TSEN_ADC_DATA_ADC_DATA 0
#define LSb16smSysCtl_TSEN_ADC_DATA_ADC_DATA 0
#define bsmSysCtl_TSEN_ADC_DATA_ADC_DATA 12
#define MSK32smSysCtl_TSEN_ADC_DATA_ADC_DATA 0x00000FFF
///////////////////////////////////////////////////////////
#define RA_smSysCtl_TSEN_CHK_CTRL 0x0030
#define BA_smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MAX 0x0030
#define B16smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MAX 0x0030
#define LSb32smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MAX 0
#define LSb16smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MAX 0
#define bsmSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MAX 12
#define MSK32smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MAX 0x00000FFF
#define BA_smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MIN 0x0031
#define B16smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MIN 0x0030
#define LSb32smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MIN 12
#define LSb16smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MIN 12
#define bsmSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MIN 12
#define MSK32smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MIN 0x00FFF000
#define BA_smSysCtl_TSEN_CHK_CTRL_TSEN_OVERHEAT_SEL 0x0033
#define B16smSysCtl_TSEN_CHK_CTRL_TSEN_OVERHEAT_SEL 0x0032
#define LSb32smSysCtl_TSEN_CHK_CTRL_TSEN_OVERHEAT_SEL 24
#define LSb16smSysCtl_TSEN_CHK_CTRL_TSEN_OVERHEAT_SEL 8
#define bsmSysCtl_TSEN_CHK_CTRL_TSEN_OVERHEAT_SEL 1
#define MSK32smSysCtl_TSEN_CHK_CTRL_TSEN_OVERHEAT_SEL 0x01000000
///////////////////////////////////////////////////////////
#define RA_smSysCtl_TSEN_DATA_STATUS 0x0034
#define BA_smSysCtl_TSEN_DATA_STATUS_TSEN_MAX_FAIL 0x0034
#define B16smSysCtl_TSEN_DATA_STATUS_TSEN_MAX_FAIL 0x0034
#define LSb32smSysCtl_TSEN_DATA_STATUS_TSEN_MAX_FAIL 0
#define LSb16smSysCtl_TSEN_DATA_STATUS_TSEN_MAX_FAIL 0
#define bsmSysCtl_TSEN_DATA_STATUS_TSEN_MAX_FAIL 1
#define MSK32smSysCtl_TSEN_DATA_STATUS_TSEN_MAX_FAIL 0x00000001
#define BA_smSysCtl_TSEN_DATA_STATUS_TSEN_MIN_FAIL 0x0034
#define B16smSysCtl_TSEN_DATA_STATUS_TSEN_MIN_FAIL 0x0034
#define LSb32smSysCtl_TSEN_DATA_STATUS_TSEN_MIN_FAIL 1
#define LSb16smSysCtl_TSEN_DATA_STATUS_TSEN_MIN_FAIL 1
#define bsmSysCtl_TSEN_DATA_STATUS_TSEN_MIN_FAIL 1
#define MSK32smSysCtl_TSEN_DATA_STATUS_TSEN_MIN_FAIL 0x00000002
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_BOOT_STATUS 0x0038
#define BA_smSysCtl_SM_BOOT_STATUS_MODE 0x0038
#define B16smSysCtl_SM_BOOT_STATUS_MODE 0x0038
#define LSb32smSysCtl_SM_BOOT_STATUS_MODE 0
#define LSb16smSysCtl_SM_BOOT_STATUS_MODE 0
#define bsmSysCtl_SM_BOOT_STATUS_MODE 32
#define MSK32smSysCtl_SM_BOOT_STATUS_MODE 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_LDO_CTRL 0x003C
#define BA_smSysCtl_SM_LDO_CTRL_TEST_SEL 0x003C
#define B16smSysCtl_SM_LDO_CTRL_TEST_SEL 0x003C
#define LSb32smSysCtl_SM_LDO_CTRL_TEST_SEL 0
#define LSb16smSysCtl_SM_LDO_CTRL_TEST_SEL 0
#define bsmSysCtl_SM_LDO_CTRL_TEST_SEL 3
#define MSK32smSysCtl_SM_LDO_CTRL_TEST_SEL 0x00000007
#define BA_smSysCtl_SM_LDO_CTRL_VOUT_SEL 0x003C
#define B16smSysCtl_SM_LDO_CTRL_VOUT_SEL 0x003C
#define LSb32smSysCtl_SM_LDO_CTRL_VOUT_SEL 3
#define LSb16smSysCtl_SM_LDO_CTRL_VOUT_SEL 3
#define bsmSysCtl_SM_LDO_CTRL_VOUT_SEL 3
#define MSK32smSysCtl_SM_LDO_CTRL_VOUT_SEL 0x00000038
#define BA_smSysCtl_SM_LDO_CTRL_TEST_EN 0x003C
#define B16smSysCtl_SM_LDO_CTRL_TEST_EN 0x003C
#define LSb32smSysCtl_SM_LDO_CTRL_TEST_EN 6
#define LSb16smSysCtl_SM_LDO_CTRL_TEST_EN 6
#define bsmSysCtl_SM_LDO_CTRL_TEST_EN 1
#define MSK32smSysCtl_SM_LDO_CTRL_TEST_EN 0x00000040
#define BA_smSysCtl_SM_LDO_CTRL_LDO_RDY 0x003C
#define B16smSysCtl_SM_LDO_CTRL_LDO_RDY 0x003C
#define LSb32smSysCtl_SM_LDO_CTRL_LDO_RDY 7
#define LSb16smSysCtl_SM_LDO_CTRL_LDO_RDY 7
#define bsmSysCtl_SM_LDO_CTRL_LDO_RDY 1
#define MSK32smSysCtl_SM_LDO_CTRL_LDO_RDY 0x00000080
#define BA_smSysCtl_SM_LDO_CTRL_CHP_EN_1P1 0x003D
#define B16smSysCtl_SM_LDO_CTRL_CHP_EN_1P1 0x003C
#define LSb32smSysCtl_SM_LDO_CTRL_CHP_EN_1P1 8
#define LSb16smSysCtl_SM_LDO_CTRL_CHP_EN_1P1 8
#define bsmSysCtl_SM_LDO_CTRL_CHP_EN_1P1 1
#define MSK32smSysCtl_SM_LDO_CTRL_CHP_EN_1P1 0x00000100
#define BA_smSysCtl_SM_LDO_CTRL_ICLAMP_EN_1P1 0x003D
#define B16smSysCtl_SM_LDO_CTRL_ICLAMP_EN_1P1 0x003C
#define LSb32smSysCtl_SM_LDO_CTRL_ICLAMP_EN_1P1 9
#define LSb16smSysCtl_SM_LDO_CTRL_ICLAMP_EN_1P1 9
#define bsmSysCtl_SM_LDO_CTRL_ICLAMP_EN_1P1 1
#define MSK32smSysCtl_SM_LDO_CTRL_ICLAMP_EN_1P1 0x00000200
#define BA_smSysCtl_SM_LDO_CTRL_RSVD_HI 0x003D
#define B16smSysCtl_SM_LDO_CTRL_RSVD_HI 0x003C
#define LSb32smSysCtl_SM_LDO_CTRL_RSVD_HI 10
#define LSb16smSysCtl_SM_LDO_CTRL_RSVD_HI 10
#define bsmSysCtl_SM_LDO_CTRL_RSVD_HI 5
#define MSK32smSysCtl_SM_LDO_CTRL_RSVD_HI 0x00007C00
#define BA_smSysCtl_SM_LDO_CTRL_RSVD_LO 0x003D
#define B16smSysCtl_SM_LDO_CTRL_RSVD_LO 0x003C
#define LSb32smSysCtl_SM_LDO_CTRL_RSVD_LO 15
#define LSb16smSysCtl_SM_LDO_CTRL_RSVD_LO 15
#define bsmSysCtl_SM_LDO_CTRL_RSVD_LO 5
#define MSK32smSysCtl_SM_LDO_CTRL_RSVD_LO 0x000F8000
#define BA_smSysCtl_SM_LDO_CTRL_ZERO_SEL 0x003E
#define B16smSysCtl_SM_LDO_CTRL_ZERO_SEL 0x003E
#define LSb32smSysCtl_SM_LDO_CTRL_ZERO_SEL 20
#define LSb16smSysCtl_SM_LDO_CTRL_ZERO_SEL 4
#define bsmSysCtl_SM_LDO_CTRL_ZERO_SEL 2
#define MSK32smSysCtl_SM_LDO_CTRL_ZERO_SEL 0x00300000
#define BA_smSysCtl_SM_LDO_CTRL_POLE_SEL 0x003E
#define B16smSysCtl_SM_LDO_CTRL_POLE_SEL 0x003E
#define LSb32smSysCtl_SM_LDO_CTRL_POLE_SEL 22
#define LSb16smSysCtl_SM_LDO_CTRL_POLE_SEL 6
#define bsmSysCtl_SM_LDO_CTRL_POLE_SEL 2
#define MSK32smSysCtl_SM_LDO_CTRL_POLE_SEL 0x00C00000
#define BA_smSysCtl_SM_LDO_CTRL_MON_VDD1P8_SEL 0x003F
#define B16smSysCtl_SM_LDO_CTRL_MON_VDD1P8_SEL 0x003E
#define LSb32smSysCtl_SM_LDO_CTRL_MON_VDD1P8_SEL 24
#define LSb16smSysCtl_SM_LDO_CTRL_MON_VDD1P8_SEL 8
#define bsmSysCtl_SM_LDO_CTRL_MON_VDD1P8_SEL 2
#define MSK32smSysCtl_SM_LDO_CTRL_MON_VDD1P8_SEL 0x03000000
#define BA_smSysCtl_SM_LDO_CTRL_DLY_SEL 0x003F
#define B16smSysCtl_SM_LDO_CTRL_DLY_SEL 0x003E
#define LSb32smSysCtl_SM_LDO_CTRL_DLY_SEL 26
#define LSb16smSysCtl_SM_LDO_CTRL_DLY_SEL 10
#define bsmSysCtl_SM_LDO_CTRL_DLY_SEL 2
#define MSK32smSysCtl_SM_LDO_CTRL_DLY_SEL 0x0C000000
#define BA_smSysCtl_SM_LDO_CTRL_EN_ZERO_SEL 0x003F
#define B16smSysCtl_SM_LDO_CTRL_EN_ZERO_SEL 0x003E
#define LSb32smSysCtl_SM_LDO_CTRL_EN_ZERO_SEL 28
#define LSb16smSysCtl_SM_LDO_CTRL_EN_ZERO_SEL 12
#define bsmSysCtl_SM_LDO_CTRL_EN_ZERO_SEL 1
#define MSK32smSysCtl_SM_LDO_CTRL_EN_ZERO_SEL 0x10000000
#define BA_smSysCtl_SM_LDO_CTRL_EN_POLE_SEL 0x003F
#define B16smSysCtl_SM_LDO_CTRL_EN_POLE_SEL 0x003E
#define LSb32smSysCtl_SM_LDO_CTRL_EN_POLE_SEL 29
#define LSb16smSysCtl_SM_LDO_CTRL_EN_POLE_SEL 13
#define bsmSysCtl_SM_LDO_CTRL_EN_POLE_SEL 1
#define MSK32smSysCtl_SM_LDO_CTRL_EN_POLE_SEL 0x20000000
#define BA_smSysCtl_SM_LDO_CTRL_PD_MON_VDD1P8 0x003F
#define B16smSysCtl_SM_LDO_CTRL_PD_MON_VDD1P8 0x003E
#define LSb32smSysCtl_SM_LDO_CTRL_PD_MON_VDD1P8 30
#define LSb16smSysCtl_SM_LDO_CTRL_PD_MON_VDD1P8 14
#define bsmSysCtl_SM_LDO_CTRL_PD_MON_VDD1P8 1
#define MSK32smSysCtl_SM_LDO_CTRL_PD_MON_VDD1P8 0x40000000
#define BA_smSysCtl_SM_LDO_CTRL_MON_VDD1P8_OUT 0x003F
#define B16smSysCtl_SM_LDO_CTRL_MON_VDD1P8_OUT 0x003E
#define LSb32smSysCtl_SM_LDO_CTRL_MON_VDD1P8_OUT 31
#define LSb16smSysCtl_SM_LDO_CTRL_MON_VDD1P8_OUT 15
#define bsmSysCtl_SM_LDO_CTRL_MON_VDD1P8_OUT 1
#define MSK32smSysCtl_SM_LDO_CTRL_MON_VDD1P8_OUT 0x80000000
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_WDT_MASK 0x0040
#define BA_smSysCtl_SM_WDT_MASK_SM_RST 0x0040
#define B16smSysCtl_SM_WDT_MASK_SM_RST 0x0040
#define LSb32smSysCtl_SM_WDT_MASK_SM_RST 0
#define LSb16smSysCtl_SM_WDT_MASK_SM_RST 0
#define bsmSysCtl_SM_WDT_MASK_SM_RST 3
#define MSK32smSysCtl_SM_WDT_MASK_SM_RST 0x00000007
#define BA_smSysCtl_SM_WDT_MASK_SOC_RST 0x0040
#define B16smSysCtl_SM_WDT_MASK_SOC_RST 0x0040
#define LSb32smSysCtl_SM_WDT_MASK_SOC_RST 3
#define LSb16smSysCtl_SM_WDT_MASK_SOC_RST 3
#define bsmSysCtl_SM_WDT_MASK_SOC_RST 3
#define MSK32smSysCtl_SM_WDT_MASK_SOC_RST 0x00000038
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_CLK_CTRL 0x0044
#define BA_smSysCtl_SM_CLK_CTRL_tsenClkSel 0x0044
#define B16smSysCtl_SM_CLK_CTRL_tsenClkSel 0x0044
#define LSb32smSysCtl_SM_CLK_CTRL_tsenClkSel 0
#define LSb16smSysCtl_SM_CLK_CTRL_tsenClkSel 0
#define bsmSysCtl_SM_CLK_CTRL_tsenClkSel 1
#define MSK32smSysCtl_SM_CLK_CTRL_tsenClkSel 0x00000001
#define BA_smSysCtl_SM_CLK_CTRL_tsenClkEn 0x0044
#define B16smSysCtl_SM_CLK_CTRL_tsenClkEn 0x0044
#define LSb32smSysCtl_SM_CLK_CTRL_tsenClkEn 1
#define LSb16smSysCtl_SM_CLK_CTRL_tsenClkEn 1
#define bsmSysCtl_SM_CLK_CTRL_tsenClkEn 1
#define MSK32smSysCtl_SM_CLK_CTRL_tsenClkEn 0x00000002
#define BA_smSysCtl_SM_CLK_CTRL_ssmiiTxClkSel 0x0044
#define B16smSysCtl_SM_CLK_CTRL_ssmiiTxClkSel 0x0044
#define LSb32smSysCtl_SM_CLK_CTRL_ssmiiTxClkSel 2
#define LSb16smSysCtl_SM_CLK_CTRL_ssmiiTxClkSel 2
#define bsmSysCtl_SM_CLK_CTRL_ssmiiTxClkSel 1
#define MSK32smSysCtl_SM_CLK_CTRL_ssmiiTxClkSel 0x00000004
#define BA_smSysCtl_SM_CLK_CTRL_ssmiiTxClkEn 0x0044
#define B16smSysCtl_SM_CLK_CTRL_ssmiiTxClkEn 0x0044
#define LSb32smSysCtl_SM_CLK_CTRL_ssmiiTxClkEn 3
#define LSb16smSysCtl_SM_CLK_CTRL_ssmiiTxClkEn 3
#define bsmSysCtl_SM_CLK_CTRL_ssmiiTxClkEn 1
#define MSK32smSysCtl_SM_CLK_CTRL_ssmiiTxClkEn 0x00000008
///////////////////////////////////////////////////////////
#define RA_smSysCtl_smAnaGrpCtl 0x0048
#define BA_smSysCtl_smAnaGrpCtl_pu 0x0048
#define B16smSysCtl_smAnaGrpCtl_pu 0x0048
#define LSb32smSysCtl_smAnaGrpCtl_pu 0
#define LSb16smSysCtl_smAnaGrpCtl_pu 0
#define bsmSysCtl_smAnaGrpCtl_pu 1
#define MSK32smSysCtl_smAnaGrpCtl_pu 0x00000001
#define BA_smSysCtl_smAnaGrpCtl_bgSel 0x0048
#define B16smSysCtl_smAnaGrpCtl_bgSel 0x0048
#define LSb32smSysCtl_smAnaGrpCtl_bgSel 1
#define LSb16smSysCtl_smAnaGrpCtl_bgSel 1
#define bsmSysCtl_smAnaGrpCtl_bgSel 2
#define MSK32smSysCtl_smAnaGrpCtl_bgSel 0x00000006
#define BA_smSysCtl_smAnaGrpCtl_puXtl 0x0048
#define B16smSysCtl_smAnaGrpCtl_puXtl 0x0048
#define LSb32smSysCtl_smAnaGrpCtl_puXtl 3
#define LSb16smSysCtl_smAnaGrpCtl_puXtl 3
#define bsmSysCtl_smAnaGrpCtl_puXtl 1
#define MSK32smSysCtl_smAnaGrpCtl_puXtl 0x00000008
#define BA_smSysCtl_smAnaGrpCtl_bypass 0x0048
#define B16smSysCtl_smAnaGrpCtl_bypass 0x0048
#define LSb32smSysCtl_smAnaGrpCtl_bypass 4
#define LSb16smSysCtl_smAnaGrpCtl_bypass 4
#define bsmSysCtl_smAnaGrpCtl_bypass 1
#define MSK32smSysCtl_smAnaGrpCtl_bypass 0x00000010
#define BA_smSysCtl_smAnaGrpCtl_gainX2 0x0048
#define B16smSysCtl_smAnaGrpCtl_gainX2 0x0048
#define LSb32smSysCtl_smAnaGrpCtl_gainX2 5
#define LSb16smSysCtl_smAnaGrpCtl_gainX2 5
#define bsmSysCtl_smAnaGrpCtl_gainX2 1
#define MSK32smSysCtl_smAnaGrpCtl_gainX2 0x00000020
#define BA_smSysCtl_smAnaGrpCtl_selClkDigDiv1 0x0048
#define B16smSysCtl_smAnaGrpCtl_selClkDigDiv1 0x0048
#define LSb32smSysCtl_smAnaGrpCtl_selClkDigDiv1 6
#define LSb16smSysCtl_smAnaGrpCtl_selClkDigDiv1 6
#define bsmSysCtl_smAnaGrpCtl_selClkDigDiv1 2
#define MSK32smSysCtl_smAnaGrpCtl_selClkDigDiv1 0x000000C0
#define BA_smSysCtl_smAnaGrpCtl_selClkDigDiv2 0x0049
#define B16smSysCtl_smAnaGrpCtl_selClkDigDiv2 0x0048
#define LSb32smSysCtl_smAnaGrpCtl_selClkDigDiv2 8
#define LSb16smSysCtl_smAnaGrpCtl_selClkDigDiv2 8
#define bsmSysCtl_smAnaGrpCtl_selClkDigDiv2 2
#define MSK32smSysCtl_smAnaGrpCtl_selClkDigDiv2 0x00000300
#define BA_smSysCtl_smAnaGrpCtl_selClkDigDiv3 0x0049
#define B16smSysCtl_smAnaGrpCtl_selClkDigDiv3 0x0048
#define LSb32smSysCtl_smAnaGrpCtl_selClkDigDiv3 10
#define LSb16smSysCtl_smAnaGrpCtl_selClkDigDiv3 10
#define bsmSysCtl_smAnaGrpCtl_selClkDigDiv3 2
#define MSK32smSysCtl_smAnaGrpCtl_selClkDigDiv3 0x00000C00
#define BA_smSysCtl_smAnaGrpCtl_selClkDigDiv4 0x0049
#define B16smSysCtl_smAnaGrpCtl_selClkDigDiv4 0x0048
#define LSb32smSysCtl_smAnaGrpCtl_selClkDigDiv4 12
#define LSb16smSysCtl_smAnaGrpCtl_selClkDigDiv4 12
#define bsmSysCtl_smAnaGrpCtl_selClkDigDiv4 2
#define MSK32smSysCtl_smAnaGrpCtl_selClkDigDiv4 0x00003000
#define BA_smSysCtl_smAnaGrpCtl_puOsc 0x0049
#define B16smSysCtl_smAnaGrpCtl_puOsc 0x0048
#define LSb32smSysCtl_smAnaGrpCtl_puOsc 14
#define LSb16smSysCtl_smAnaGrpCtl_puOsc 14
#define bsmSysCtl_smAnaGrpCtl_puOsc 1
#define MSK32smSysCtl_smAnaGrpCtl_puOsc 0x00004000
#define BA_smSysCtl_smAnaGrpCtl_speedOsc 0x0049
#define B16smSysCtl_smAnaGrpCtl_speedOsc 0x0048
#define LSb32smSysCtl_smAnaGrpCtl_speedOsc 15
#define LSb16smSysCtl_smAnaGrpCtl_speedOsc 15
#define bsmSysCtl_smAnaGrpCtl_speedOsc 2
#define MSK32smSysCtl_smAnaGrpCtl_speedOsc 0x00018000
#define BA_smSysCtl_smAnaGrpCtl_testAna 0x004A
#define B16smSysCtl_smAnaGrpCtl_testAna 0x004A
#define LSb32smSysCtl_smAnaGrpCtl_testAna 17
#define LSb16smSysCtl_smAnaGrpCtl_testAna 1
#define bsmSysCtl_smAnaGrpCtl_testAna 4
#define MSK32smSysCtl_smAnaGrpCtl_testAna 0x001E0000
#define BA_smSysCtl_smAnaGrpCtl_bgRdy 0x004A
#define B16smSysCtl_smAnaGrpCtl_bgRdy 0x004A
#define LSb32smSysCtl_smAnaGrpCtl_bgRdy 21
#define LSb16smSysCtl_smAnaGrpCtl_bgRdy 5
#define bsmSysCtl_smAnaGrpCtl_bgRdy 1
#define MSK32smSysCtl_smAnaGrpCtl_bgRdy 0x00200000
#define BA_smSysCtl_smAnaGrpCtl_reserve_in 0x004A
#define B16smSysCtl_smAnaGrpCtl_reserve_in 0x004A
#define LSb32smSysCtl_smAnaGrpCtl_reserve_in 22
#define LSb16smSysCtl_smAnaGrpCtl_reserve_in 6
#define bsmSysCtl_smAnaGrpCtl_reserve_in 10
#define MSK32smSysCtl_smAnaGrpCtl_reserve_in 0xFFC00000
#define RA_smSysCtl_smAnaGrpCtl1 0x004C
#define BA_smSysCtl_smAnaGrpCtl_xtl_pecl_sel 0x004C
#define B16smSysCtl_smAnaGrpCtl_xtl_pecl_sel 0x004C
#define LSb32smSysCtl_smAnaGrpCtl_xtl_pecl_sel 0
#define LSb16smSysCtl_smAnaGrpCtl_xtl_pecl_sel 0
#define bsmSysCtl_smAnaGrpCtl_xtl_pecl_sel 1
#define MSK32smSysCtl_smAnaGrpCtl_xtl_pecl_sel 0x00000001
#define BA_smSysCtl_smAnaGrpCtl_vreg_1p4v_sel 0x004C
#define B16smSysCtl_smAnaGrpCtl_vreg_1p4v_sel 0x004C
#define LSb32smSysCtl_smAnaGrpCtl_vreg_1p4v_sel 1
#define LSb16smSysCtl_smAnaGrpCtl_vreg_1p4v_sel 1
#define bsmSysCtl_smAnaGrpCtl_vreg_1p4v_sel 2
#define MSK32smSysCtl_smAnaGrpCtl_vreg_1p4v_sel 0x00000006
#define BA_smSysCtl_smAnaGrpCtl_vreg_0p9v_sel_xtl 0x004C
#define B16smSysCtl_smAnaGrpCtl_vreg_0p9v_sel_xtl 0x004C
#define LSb32smSysCtl_smAnaGrpCtl_vreg_0p9v_sel_xtl 3
#define LSb16smSysCtl_smAnaGrpCtl_vreg_0p9v_sel_xtl 3
#define bsmSysCtl_smAnaGrpCtl_vreg_0p9v_sel_xtl 3
#define MSK32smSysCtl_smAnaGrpCtl_vreg_0p9v_sel_xtl 0x00000038
#define BA_smSysCtl_smAnaGrpCtl_vreg_0p9v_sel_pecl 0x004C
#define B16smSysCtl_smAnaGrpCtl_vreg_0p9v_sel_pecl 0x004C
#define LSb32smSysCtl_smAnaGrpCtl_vreg_0p9v_sel_pecl 6
#define LSb16smSysCtl_smAnaGrpCtl_vreg_0p9v_sel_pecl 6
#define bsmSysCtl_smAnaGrpCtl_vreg_0p9v_sel_pecl 3
#define MSK32smSysCtl_smAnaGrpCtl_vreg_0p9v_sel_pecl 0x000001C0
#define BA_smSysCtl_smAnaGrpCtl_term 0x004D
#define B16smSysCtl_smAnaGrpCtl_term 0x004C
#define LSb32smSysCtl_smAnaGrpCtl_term 9
#define LSb16smSysCtl_smAnaGrpCtl_term 9
#define bsmSysCtl_smAnaGrpCtl_term 1
#define MSK32smSysCtl_smAnaGrpCtl_term 0x00000200
#define BA_smSysCtl_smAnaGrpCtl_pu_pecl 0x004D
#define B16smSysCtl_smAnaGrpCtl_pu_pecl 0x004C
#define LSb32smSysCtl_smAnaGrpCtl_pu_pecl 10
#define LSb16smSysCtl_smAnaGrpCtl_pu_pecl 10
#define bsmSysCtl_smAnaGrpCtl_pu_pecl 1
#define MSK32smSysCtl_smAnaGrpCtl_pu_pecl 0x00000400
#define BA_smSysCtl_smAnaGrpCtl_pecl_en 0x004D
#define B16smSysCtl_smAnaGrpCtl_pecl_en 0x004C
#define LSb32smSysCtl_smAnaGrpCtl_pecl_en 11
#define LSb16smSysCtl_smAnaGrpCtl_pecl_en 11
#define bsmSysCtl_smAnaGrpCtl_pecl_en 1
#define MSK32smSysCtl_smAnaGrpCtl_pecl_en 0x00000800
#define BA_smSysCtl_smAnaGrpCtl_pu_limiter 0x004D
#define B16smSysCtl_smAnaGrpCtl_pu_limiter 0x004C
#define LSb32smSysCtl_smAnaGrpCtl_pu_limiter 12
#define LSb16smSysCtl_smAnaGrpCtl_pu_limiter 12
#define bsmSysCtl_smAnaGrpCtl_pu_limiter 1
#define MSK32smSysCtl_smAnaGrpCtl_pu_limiter 0x00001000
#define BA_smSysCtl_smAnaGrpCtl_limiter_dc_clk_en 0x004D
#define B16smSysCtl_smAnaGrpCtl_limiter_dc_clk_en 0x004C
#define LSb32smSysCtl_smAnaGrpCtl_limiter_dc_clk_en 13
#define LSb16smSysCtl_smAnaGrpCtl_limiter_dc_clk_en 13
#define bsmSysCtl_smAnaGrpCtl_limiter_dc_clk_en 1
#define MSK32smSysCtl_smAnaGrpCtl_limiter_dc_clk_en 0x00002000
#define BA_smSysCtl_smAnaGrpCtl_ipp_adj 0x004D
#define B16smSysCtl_smAnaGrpCtl_ipp_adj 0x004C
#define LSb32smSysCtl_smAnaGrpCtl_ipp_adj 14
#define LSb16smSysCtl_smAnaGrpCtl_ipp_adj 14
#define bsmSysCtl_smAnaGrpCtl_ipp_adj 2
#define MSK32smSysCtl_smAnaGrpCtl_ipp_adj 0x0000C000
#define BA_smSysCtl_smAnaGrpCtl_icc_adj 0x004E
#define B16smSysCtl_smAnaGrpCtl_icc_adj 0x004E
#define LSb32smSysCtl_smAnaGrpCtl_icc_adj 16
#define LSb16smSysCtl_smAnaGrpCtl_icc_adj 0
#define bsmSysCtl_smAnaGrpCtl_icc_adj 2
#define MSK32smSysCtl_smAnaGrpCtl_icc_adj 0x00030000
#define BA_smSysCtl_smAnaGrpCtl_ixtal 0x004E
#define B16smSysCtl_smAnaGrpCtl_ixtal 0x004E
#define LSb32smSysCtl_smAnaGrpCtl_ixtal 18
#define LSb16smSysCtl_smAnaGrpCtl_ixtal 2
#define bsmSysCtl_smAnaGrpCtl_ixtal 2
#define MSK32smSysCtl_smAnaGrpCtl_ixtal 0x000C0000
#define BA_smSysCtl_smAnaGrpCtl_icc10u_in_sel 0x004E
#define B16smSysCtl_smAnaGrpCtl_icc10u_in_sel 0x004E
#define LSb32smSysCtl_smAnaGrpCtl_icc10u_in_sel 20
#define LSb16smSysCtl_smAnaGrpCtl_icc10u_in_sel 4
#define bsmSysCtl_smAnaGrpCtl_icc10u_in_sel 1
#define MSK32smSysCtl_smAnaGrpCtl_icc10u_in_sel 0x00100000
#define BA_smSysCtl_smAnaGrpCtl_reserve_out 0x004E
#define B16smSysCtl_smAnaGrpCtl_reserve_out 0x004E
#define LSb32smSysCtl_smAnaGrpCtl_reserve_out 21
#define LSb16smSysCtl_smAnaGrpCtl_reserve_out 5
#define bsmSysCtl_smAnaGrpCtl_reserve_out 6
#define MSK32smSysCtl_smAnaGrpCtl_reserve_out 0x07E00000
///////////////////////////////////////////////////////////
#define RA_smSysCtl_POR_status 0x0050
#define BA_smSysCtl_POR_status_POR_AVDD33 0x0050
#define B16smSysCtl_POR_status_POR_AVDD33 0x0050
#define LSb32smSysCtl_POR_status_POR_AVDD33 0
#define LSb16smSysCtl_POR_status_POR_AVDD33 0
#define bsmSysCtl_POR_status_POR_AVDD33 1
#define MSK32smSysCtl_POR_status_POR_AVDD33 0x00000001
#define BA_smSysCtl_POR_status_POR_AVDD 0x0050
#define B16smSysCtl_POR_status_POR_AVDD 0x0050
#define LSb32smSysCtl_POR_status_POR_AVDD 1
#define LSb16smSysCtl_POR_status_POR_AVDD 1
#define bsmSysCtl_POR_status_POR_AVDD 1
#define MSK32smSysCtl_POR_status_POR_AVDD 0x00000002
#define BA_smSysCtl_POR_status_POR_VDD_SOC 0x0050
#define B16smSysCtl_POR_status_POR_VDD_SOC 0x0050
#define LSb32smSysCtl_POR_status_POR_VDD_SOC 2
#define LSb16smSysCtl_POR_status_POR_VDD_SOC 2
#define bsmSysCtl_POR_status_POR_VDD_SOC 1
#define MSK32smSysCtl_POR_status_POR_VDD_SOC 0x00000004
#define BA_smSysCtl_POR_status_POR_VDD_CPU 0x0050
#define B16smSysCtl_POR_status_POR_VDD_CPU 0x0050
#define LSb32smSysCtl_POR_status_POR_VDD_CPU 3
#define LSb16smSysCtl_POR_status_POR_VDD_CPU 3
#define bsmSysCtl_POR_status_POR_VDD_CPU 1
#define MSK32smSysCtl_POR_status_POR_VDD_CPU 0x00000008
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_CORE_CTRL 0x0054
#define BA_smSysCtl_SM_CORE_CTRL_PAD_REG_PDB_CORE 0x0054
#define B16smSysCtl_SM_CORE_CTRL_PAD_REG_PDB_CORE 0x0054
#define LSb32smSysCtl_SM_CORE_CTRL_PAD_REG_PDB_CORE 0
#define LSb16smSysCtl_SM_CORE_CTRL_PAD_REG_PDB_CORE 0
#define bsmSysCtl_SM_CORE_CTRL_PAD_REG_PDB_CORE 1
#define MSK32smSysCtl_SM_CORE_CTRL_PAD_REG_PDB_CORE 0x00000001
#define BA_smSysCtl_SM_CORE_CTRL_PAD_V18EN_CORE 0x0054
#define B16smSysCtl_SM_CORE_CTRL_PAD_V18EN_CORE 0x0054
#define LSb32smSysCtl_SM_CORE_CTRL_PAD_V18EN_CORE 1
#define LSb16smSysCtl_SM_CORE_CTRL_PAD_V18EN_CORE 1
#define bsmSysCtl_SM_CORE_CTRL_PAD_V18EN_CORE 1
#define MSK32smSysCtl_SM_CORE_CTRL_PAD_V18EN_CORE 0x00000002
#define BA_smSysCtl_SM_CORE_CTRL_PAD_V25EN_CORE 0x0054
#define B16smSysCtl_SM_CORE_CTRL_PAD_V25EN_CORE 0x0054
#define LSb32smSysCtl_SM_CORE_CTRL_PAD_V25EN_CORE 2
#define LSb16smSysCtl_SM_CORE_CTRL_PAD_V25EN_CORE 2
#define bsmSysCtl_SM_CORE_CTRL_PAD_V25EN_CORE 1
#define MSK32smSysCtl_SM_CORE_CTRL_PAD_V25EN_CORE 0x00000004
#define BA_smSysCtl_SM_CORE_CTRL_PAD_ZP 0x0054
#define B16smSysCtl_SM_CORE_CTRL_PAD_ZP 0x0054
#define LSb32smSysCtl_SM_CORE_CTRL_PAD_ZP 3
#define LSb16smSysCtl_SM_CORE_CTRL_PAD_ZP 3
#define bsmSysCtl_SM_CORE_CTRL_PAD_ZP 4
#define MSK32smSysCtl_SM_CORE_CTRL_PAD_ZP 0x00000078
#define BA_smSysCtl_SM_CORE_CTRL_PAD_ZN 0x0054
#define B16smSysCtl_SM_CORE_CTRL_PAD_ZN 0x0054
#define LSb32smSysCtl_SM_CORE_CTRL_PAD_ZN 7
#define LSb16smSysCtl_SM_CORE_CTRL_PAD_ZN 7
#define bsmSysCtl_SM_CORE_CTRL_PAD_ZN 4
#define MSK32smSysCtl_SM_CORE_CTRL_PAD_ZN 0x00000780
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_TEST 0x0058
#define BA_smSysCtl_SM_TEST_ADC_TEST_FAIL 0x0058
#define B16smSysCtl_SM_TEST_ADC_TEST_FAIL 0x0058
#define LSb32smSysCtl_SM_TEST_ADC_TEST_FAIL 0
#define LSb16smSysCtl_SM_TEST_ADC_TEST_FAIL 0
#define bsmSysCtl_SM_TEST_ADC_TEST_FAIL 1
#define MSK32smSysCtl_SM_TEST_ADC_TEST_FAIL 0x00000001
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_TEST_DATA0 0x005C
#define BA_smSysCtl_SM_TEST_DATA0_ADC_DATA_HIGH 0x005C
#define B16smSysCtl_SM_TEST_DATA0_ADC_DATA_HIGH 0x005C
#define LSb32smSysCtl_SM_TEST_DATA0_ADC_DATA_HIGH 0
#define LSb16smSysCtl_SM_TEST_DATA0_ADC_DATA_HIGH 0
#define bsmSysCtl_SM_TEST_DATA0_ADC_DATA_HIGH 10
#define MSK32smSysCtl_SM_TEST_DATA0_ADC_DATA_HIGH 0x000003FF
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_TEST_DATA1 0x0060
#define BA_smSysCtl_SM_TEST_DATA1_ADC_DATA_LOW 0x0060
#define B16smSysCtl_SM_TEST_DATA1_ADC_DATA_LOW 0x0060
#define LSb32smSysCtl_SM_TEST_DATA1_ADC_DATA_LOW 0
#define LSb16smSysCtl_SM_TEST_DATA1_ADC_DATA_LOW 0
#define bsmSysCtl_SM_TEST_DATA1_ADC_DATA_LOW 10
#define MSK32smSysCtl_SM_TEST_DATA1_ADC_DATA_LOW 0x000003FF
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_RWTC_CTRL_0 0x0064
#define BA_smSysCtl_SM_RWTC_CTRL_0_RF1P_LOW 0x0064
#define B16smSysCtl_SM_RWTC_CTRL_0_RF1P_LOW 0x0064
#define LSb32smSysCtl_SM_RWTC_CTRL_0_RF1P_LOW 0
#define LSb16smSysCtl_SM_RWTC_CTRL_0_RF1P_LOW 0
#define bsmSysCtl_SM_RWTC_CTRL_0_RF1P_LOW 4
#define MSK32smSysCtl_SM_RWTC_CTRL_0_RF1P_LOW 0x0000000F
#define BA_smSysCtl_SM_RWTC_CTRL_0_RF1P_HIGH 0x0064
#define B16smSysCtl_SM_RWTC_CTRL_0_RF1P_HIGH 0x0064
#define LSb32smSysCtl_SM_RWTC_CTRL_0_RF1P_HIGH 4
#define LSb16smSysCtl_SM_RWTC_CTRL_0_RF1P_HIGH 4
#define bsmSysCtl_SM_RWTC_CTRL_0_RF1P_HIGH 4
#define MSK32smSysCtl_SM_RWTC_CTRL_0_RF1P_HIGH 0x000000F0
#define BA_smSysCtl_SM_RWTC_CTRL_0_RF2P_LOW 0x0065
#define B16smSysCtl_SM_RWTC_CTRL_0_RF2P_LOW 0x0064
#define LSb32smSysCtl_SM_RWTC_CTRL_0_RF2P_LOW 8
#define LSb16smSysCtl_SM_RWTC_CTRL_0_RF2P_LOW 8
#define bsmSysCtl_SM_RWTC_CTRL_0_RF2P_LOW 4
#define MSK32smSysCtl_SM_RWTC_CTRL_0_RF2P_LOW 0x00000F00
#define BA_smSysCtl_SM_RWTC_CTRL_0_RF2P_HIGH 0x0065
#define B16smSysCtl_SM_RWTC_CTRL_0_RF2P_HIGH 0x0064
#define LSb32smSysCtl_SM_RWTC_CTRL_0_RF2P_HIGH 12
#define LSb16smSysCtl_SM_RWTC_CTRL_0_RF2P_HIGH 12
#define bsmSysCtl_SM_RWTC_CTRL_0_RF2P_HIGH 4
#define MSK32smSysCtl_SM_RWTC_CTRL_0_RF2P_HIGH 0x0000F000
#define BA_smSysCtl_SM_RWTC_CTRL_0_SR1P_LOW 0x0066
#define B16smSysCtl_SM_RWTC_CTRL_0_SR1P_LOW 0x0066
#define LSb32smSysCtl_SM_RWTC_CTRL_0_SR1P_LOW 16
#define LSb16smSysCtl_SM_RWTC_CTRL_0_SR1P_LOW 0
#define bsmSysCtl_SM_RWTC_CTRL_0_SR1P_LOW 4
#define MSK32smSysCtl_SM_RWTC_CTRL_0_SR1P_LOW 0x000F0000
#define BA_smSysCtl_SM_RWTC_CTRL_0_SR1P_HIGH 0x0066
#define B16smSysCtl_SM_RWTC_CTRL_0_SR1P_HIGH 0x0066
#define LSb32smSysCtl_SM_RWTC_CTRL_0_SR1P_HIGH 20
#define LSb16smSysCtl_SM_RWTC_CTRL_0_SR1P_HIGH 4
#define bsmSysCtl_SM_RWTC_CTRL_0_SR1P_HIGH 4
#define MSK32smSysCtl_SM_RWTC_CTRL_0_SR1P_HIGH 0x00F00000
#define BA_smSysCtl_SM_RWTC_CTRL_0_SR2P_LOW 0x0067
#define B16smSysCtl_SM_RWTC_CTRL_0_SR2P_LOW 0x0066
#define LSb32smSysCtl_SM_RWTC_CTRL_0_SR2P_LOW 24
#define LSb16smSysCtl_SM_RWTC_CTRL_0_SR2P_LOW 8
#define bsmSysCtl_SM_RWTC_CTRL_0_SR2P_LOW 4
#define MSK32smSysCtl_SM_RWTC_CTRL_0_SR2P_LOW 0x0F000000
#define BA_smSysCtl_SM_RWTC_CTRL_0_SR2P_HIGH 0x0067
#define B16smSysCtl_SM_RWTC_CTRL_0_SR2P_HIGH 0x0066
#define LSb32smSysCtl_SM_RWTC_CTRL_0_SR2P_HIGH 28
#define LSb16smSysCtl_SM_RWTC_CTRL_0_SR2P_HIGH 12
#define bsmSysCtl_SM_RWTC_CTRL_0_SR2P_HIGH 4
#define MSK32smSysCtl_SM_RWTC_CTRL_0_SR2P_HIGH 0xF0000000
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_RWTC_CTRL_1 0x0068
#define BA_smSysCtl_SM_RWTC_CTRL_1_ROM_LOW 0x0068
#define B16smSysCtl_SM_RWTC_CTRL_1_ROM_LOW 0x0068
#define LSb32smSysCtl_SM_RWTC_CTRL_1_ROM_LOW 0
#define LSb16smSysCtl_SM_RWTC_CTRL_1_ROM_LOW 0
#define bsmSysCtl_SM_RWTC_CTRL_1_ROM_LOW 5
#define MSK32smSysCtl_SM_RWTC_CTRL_1_ROM_LOW 0x0000001F
#define BA_smSysCtl_SM_RWTC_CTRL_1_ROM_HIGH 0x0068
#define B16smSysCtl_SM_RWTC_CTRL_1_ROM_HIGH 0x0068
#define LSb32smSysCtl_SM_RWTC_CTRL_1_ROM_HIGH 5
#define LSb16smSysCtl_SM_RWTC_CTRL_1_ROM_HIGH 5
#define bsmSysCtl_SM_RWTC_CTRL_1_ROM_HIGH 5
#define MSK32smSysCtl_SM_RWTC_CTRL_1_ROM_HIGH 0x000003E0
#define BA_smSysCtl_SM_RWTC_CTRL_1_RF2P_NH 0x0069
#define B16smSysCtl_SM_RWTC_CTRL_1_RF2P_NH 0x0068
#define LSb32smSysCtl_SM_RWTC_CTRL_1_RF2P_NH 10
#define LSb16smSysCtl_SM_RWTC_CTRL_1_RF2P_NH 10
#define bsmSysCtl_SM_RWTC_CTRL_1_RF2P_NH 4
#define MSK32smSysCtl_SM_RWTC_CTRL_1_RF2P_NH 0x00003C00
#define BA_smSysCtl_SM_RWTC_CTRL_1_RF2R2W_NH 0x0069
#define B16smSysCtl_SM_RWTC_CTRL_1_RF2R2W_NH 0x0068
#define LSb32smSysCtl_SM_RWTC_CTRL_1_RF2R2W_NH 14
#define LSb16smSysCtl_SM_RWTC_CTRL_1_RF2R2W_NH 14
#define bsmSysCtl_SM_RWTC_CTRL_1_RF2R2W_NH 4
#define MSK32smSysCtl_SM_RWTC_CTRL_1_RF2R2W_NH 0x0003C000
#define BA_smSysCtl_SM_RWTC_CTRL_1_SR1P_LVT 0x006A
#define B16smSysCtl_SM_RWTC_CTRL_1_SR1P_LVT 0x006A
#define LSb32smSysCtl_SM_RWTC_CTRL_1_SR1P_LVT 18
#define LSb16smSysCtl_SM_RWTC_CTRL_1_SR1P_LVT 2
#define bsmSysCtl_SM_RWTC_CTRL_1_SR1P_LVT 4
#define MSK32smSysCtl_SM_RWTC_CTRL_1_SR1P_LVT 0x003C0000
#define BA_smSysCtl_SM_RWTC_CTRL_1_SR2P_LVT 0x006A
#define B16smSysCtl_SM_RWTC_CTRL_1_SR2P_LVT 0x006A
#define LSb32smSysCtl_SM_RWTC_CTRL_1_SR2P_LVT 22
#define LSb16smSysCtl_SM_RWTC_CTRL_1_SR2P_LVT 6
#define bsmSysCtl_SM_RWTC_CTRL_1_SR2P_LVT 4
#define MSK32smSysCtl_SM_RWTC_CTRL_1_SR2P_LVT 0x03C00000
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_PORT_SEL_CTRL 0x006C
#define BA_smSysCtl_SM_PORT_SEL_CTRL_TW2 0x006C
#define B16smSysCtl_SM_PORT_SEL_CTRL_TW2 0x006C
#define LSb32smSysCtl_SM_PORT_SEL_CTRL_TW2 0
#define LSb16smSysCtl_SM_PORT_SEL_CTRL_TW2 0
#define bsmSysCtl_SM_PORT_SEL_CTRL_TW2 1
#define MSK32smSysCtl_SM_PORT_SEL_CTRL_TW2 0x00000001
#define BA_smSysCtl_SM_PORT_SEL_CTRL_URT1 0x006C
#define B16smSysCtl_SM_PORT_SEL_CTRL_URT1 0x006C
#define LSb32smSysCtl_SM_PORT_SEL_CTRL_URT1 1
#define LSb16smSysCtl_SM_PORT_SEL_CTRL_URT1 1
#define bsmSysCtl_SM_PORT_SEL_CTRL_URT1 1
#define MSK32smSysCtl_SM_PORT_SEL_CTRL_URT1 0x00000002
#define BA_smSysCtl_SM_PORT_SEL_CTRL_FE_MDIO 0x006C
#define B16smSysCtl_SM_PORT_SEL_CTRL_FE_MDIO 0x006C
#define LSb32smSysCtl_SM_PORT_SEL_CTRL_FE_MDIO 2
#define LSb16smSysCtl_SM_PORT_SEL_CTRL_FE_MDIO 2
#define bsmSysCtl_SM_PORT_SEL_CTRL_FE_MDIO 1
#define MSK32smSysCtl_SM_PORT_SEL_CTRL_FE_MDIO 0x00000004
///////////////////////////////////////////////////////////
#define RA_smSysCtl_TSEN_ADC_RAW_DATA 0x0070
#define BA_smSysCtl_TSEN_ADC_RAW_DATA_TSEN_DATA_RAW 0x0070
#define B16smSysCtl_TSEN_ADC_RAW_DATA_TSEN_DATA_RAW 0x0070
#define LSb32smSysCtl_TSEN_ADC_RAW_DATA_TSEN_DATA_RAW 0
#define LSb16smSysCtl_TSEN_ADC_RAW_DATA_TSEN_DATA_RAW 0
#define bsmSysCtl_TSEN_ADC_RAW_DATA_TSEN_DATA_RAW 12
#define MSK32smSysCtl_TSEN_ADC_RAW_DATA_TSEN_DATA_RAW 0x00000FFF
///////////////////////////////////////////////////////////
#define RA_smSysCtl_TSEN_ADC_CLK_DIV 0x0074
#define BA_smSysCtl_TSEN_ADC_CLK_DIV_ADC_DIV 0x0074
#define B16smSysCtl_TSEN_ADC_CLK_DIV_ADC_DIV 0x0074
#define LSb32smSysCtl_TSEN_ADC_CLK_DIV_ADC_DIV 0
#define LSb16smSysCtl_TSEN_ADC_CLK_DIV_ADC_DIV 0
#define bsmSysCtl_TSEN_ADC_CLK_DIV_ADC_DIV 3
#define MSK32smSysCtl_TSEN_ADC_CLK_DIV_ADC_DIV 0x00000007
#define BA_smSysCtl_TSEN_ADC_CLK_DIV_TSEN_DIV 0x0074
#define B16smSysCtl_TSEN_ADC_CLK_DIV_TSEN_DIV 0x0074
#define LSb32smSysCtl_TSEN_ADC_CLK_DIV_TSEN_DIV 3
#define LSb16smSysCtl_TSEN_ADC_CLK_DIV_TSEN_DIV 3
#define bsmSysCtl_TSEN_ADC_CLK_DIV_TSEN_DIV 4
#define MSK32smSysCtl_TSEN_ADC_CLK_DIV_TSEN_DIV 0x00000078
///////////////////////////////////////////////////////////
#define RA_smSysCtl_TSEN_ADC_CTRL 0x0078
#define BA_smSysCtl_TSEN_ADC_CTRL_ADC_VREF_ADJ 0x0078
#define B16smSysCtl_TSEN_ADC_CTRL_ADC_VREF_ADJ 0x0078
#define LSb32smSysCtl_TSEN_ADC_CTRL_ADC_VREF_ADJ 0
#define LSb16smSysCtl_TSEN_ADC_CTRL_ADC_VREF_ADJ 0
#define bsmSysCtl_TSEN_ADC_CTRL_ADC_VREF_ADJ 8
#define MSK32smSysCtl_TSEN_ADC_CTRL_ADC_VREF_ADJ 0x000000FF
#define BA_smSysCtl_TSEN_ADC_CTRL_TSEN_START 0x0079
#define B16smSysCtl_TSEN_ADC_CTRL_TSEN_START 0x0078
#define LSb32smSysCtl_TSEN_ADC_CTRL_TSEN_START 8
#define LSb16smSysCtl_TSEN_ADC_CTRL_TSEN_START 8
#define bsmSysCtl_TSEN_ADC_CTRL_TSEN_START 1
#define MSK32smSysCtl_TSEN_ADC_CTRL_TSEN_START 0x00000100
#define BA_smSysCtl_TSEN_ADC_CTRL_TSEN_AVG_NUM 0x0079
#define B16smSysCtl_TSEN_ADC_CTRL_TSEN_AVG_NUM 0x0078
#define LSb32smSysCtl_TSEN_ADC_CTRL_TSEN_AVG_NUM 9
#define LSb16smSysCtl_TSEN_ADC_CTRL_TSEN_AVG_NUM 9
#define bsmSysCtl_TSEN_ADC_CTRL_TSEN_AVG_NUM 3
#define MSK32smSysCtl_TSEN_ADC_CTRL_TSEN_AVG_NUM 0x00000E00
#define BA_smSysCtl_TSEN_ADC_CTRL_TSEN_EXT_EN 0x0079
#define B16smSysCtl_TSEN_ADC_CTRL_TSEN_EXT_EN 0x0078
#define LSb32smSysCtl_TSEN_ADC_CTRL_TSEN_EXT_EN 12
#define LSb16smSysCtl_TSEN_ADC_CTRL_TSEN_EXT_EN 12
#define bsmSysCtl_TSEN_ADC_CTRL_TSEN_EXT_EN 1
#define MSK32smSysCtl_TSEN_ADC_CTRL_TSEN_EXT_EN 0x00001000
#define BA_smSysCtl_TSEN_ADC_CTRL_TSEN_CHOP_EN 0x0079
#define B16smSysCtl_TSEN_ADC_CTRL_TSEN_CHOP_EN 0x0078
#define LSb32smSysCtl_TSEN_ADC_CTRL_TSEN_CHOP_EN 13
#define LSb16smSysCtl_TSEN_ADC_CTRL_TSEN_CHOP_EN 13
#define bsmSysCtl_TSEN_ADC_CTRL_TSEN_CHOP_EN 2
#define MSK32smSysCtl_TSEN_ADC_CTRL_TSEN_CHOP_EN 0x00006000
#define BA_smSysCtl_TSEN_ADC_CTRL_TSEN_CAL 0x0079
#define B16smSysCtl_TSEN_ADC_CTRL_TSEN_CAL 0x0078
#define LSb32smSysCtl_TSEN_ADC_CTRL_TSEN_CAL 15
#define LSb16smSysCtl_TSEN_ADC_CTRL_TSEN_CAL 15
#define bsmSysCtl_TSEN_ADC_CTRL_TSEN_CAL 2
#define MSK32smSysCtl_TSEN_ADC_CTRL_TSEN_CAL 0x00018000
#define BA_smSysCtl_TSEN_ADC_CTRL_TSEN_RSVD 0x007A
#define B16smSysCtl_TSEN_ADC_CTRL_TSEN_RSVD 0x007A
#define LSb32smSysCtl_TSEN_ADC_CTRL_TSEN_RSVD 17
#define LSb16smSysCtl_TSEN_ADC_CTRL_TSEN_RSVD 1
#define bsmSysCtl_TSEN_ADC_CTRL_TSEN_RSVD 4
#define MSK32smSysCtl_TSEN_ADC_CTRL_TSEN_RSVD 0x001E0000
#define BA_smSysCtl_TSEN_ADC_CTRL_BG_CHP_SEL 0x007A
#define B16smSysCtl_TSEN_ADC_CTRL_BG_CHP_SEL 0x007A
#define LSb32smSysCtl_TSEN_ADC_CTRL_BG_CHP_SEL 21
#define LSb16smSysCtl_TSEN_ADC_CTRL_BG_CHP_SEL 5
#define bsmSysCtl_TSEN_ADC_CTRL_BG_CHP_SEL 1
#define MSK32smSysCtl_TSEN_ADC_CTRL_BG_CHP_SEL 0x00200000
#define BA_smSysCtl_TSEN_ADC_CTRL_BG_DTRIM 0x007A
#define B16smSysCtl_TSEN_ADC_CTRL_BG_DTRIM 0x007A
#define LSb32smSysCtl_TSEN_ADC_CTRL_BG_DTRIM 22
#define LSb16smSysCtl_TSEN_ADC_CTRL_BG_DTRIM 6
#define bsmSysCtl_TSEN_ADC_CTRL_BG_DTRIM 4
#define MSK32smSysCtl_TSEN_ADC_CTRL_BG_DTRIM 0x03C00000
///////////////////////////////////////////////////////////
#define RA_smSysCtl_TSEN_ADC_DBG 0x007C
#define BA_smSysCtl_TSEN_ADC_DBG_TSEN_RAW_SEL 0x007C
#define B16smSysCtl_TSEN_ADC_DBG_TSEN_RAW_SEL 0x007C
#define LSb32smSysCtl_TSEN_ADC_DBG_TSEN_RAW_SEL 0
#define LSb16smSysCtl_TSEN_ADC_DBG_TSEN_RAW_SEL 0
#define bsmSysCtl_TSEN_ADC_DBG_TSEN_RAW_SEL 2
#define MSK32smSysCtl_TSEN_ADC_DBG_TSEN_RAW_SEL 0x00000003
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_DUMMY_REG 0x0080
#define BA_smSysCtl_SM_DUMMY_REG_REG0 0x0080
#define B16smSysCtl_SM_DUMMY_REG_REG0 0x0080
#define LSb32smSysCtl_SM_DUMMY_REG_REG0 0
#define LSb16smSysCtl_SM_DUMMY_REG_REG0 0
#define bsmSysCtl_SM_DUMMY_REG_REG0 32
#define MSK32smSysCtl_SM_DUMMY_REG_REG0 0xFFFFFFFF
///////////////////////////////////////////////////////////
#define RA_smSysCtl_FEPHY_CTRL 0x0084
#define BA_smSysCtl_FEPHY_CTRL_ext_pwrdn_a 0x0084
#define B16smSysCtl_FEPHY_CTRL_ext_pwrdn_a 0x0084
#define LSb32smSysCtl_FEPHY_CTRL_ext_pwrdn_a 0
#define LSb16smSysCtl_FEPHY_CTRL_ext_pwrdn_a 0
#define bsmSysCtl_FEPHY_CTRL_ext_pwrdn_a 5
#define MSK32smSysCtl_FEPHY_CTRL_ext_pwrdn_a 0x0000001F
#define BA_smSysCtl_FEPHY_CTRL_pd_aneg_mode_a 0x0084
#define B16smSysCtl_FEPHY_CTRL_pd_aneg_mode_a 0x0084
#define LSb32smSysCtl_FEPHY_CTRL_pd_aneg_mode_a 5
#define LSb16smSysCtl_FEPHY_CTRL_pd_aneg_mode_a 5
#define bsmSysCtl_FEPHY_CTRL_pd_aneg_mode_a 3
#define MSK32smSysCtl_FEPHY_CTRL_pd_aneg_mode_a 0x000000E0
#define BA_smSysCtl_FEPHY_CTRL_pd_phyadr_a 0x0085
#define B16smSysCtl_FEPHY_CTRL_pd_phyadr_a 0x0084
#define LSb32smSysCtl_FEPHY_CTRL_pd_phyadr_a 8
#define LSb16smSysCtl_FEPHY_CTRL_pd_phyadr_a 8
#define bsmSysCtl_FEPHY_CTRL_pd_phyadr_a 5
#define MSK32smSysCtl_FEPHY_CTRL_pd_phyadr_a 0x00001F00
#define BA_smSysCtl_FEPHY_CTRL_pd_led_config_a 0x0085
#define B16smSysCtl_FEPHY_CTRL_pd_led_config_a 0x0084
#define LSb32smSysCtl_FEPHY_CTRL_pd_led_config_a 13
#define LSb16smSysCtl_FEPHY_CTRL_pd_led_config_a 13
#define bsmSysCtl_FEPHY_CTRL_pd_led_config_a 3
#define MSK32smSysCtl_FEPHY_CTRL_pd_led_config_a 0x0000E000
#define BA_smSysCtl_FEPHY_CTRL_yy_pecl_sdet_a 0x0086
#define B16smSysCtl_FEPHY_CTRL_yy_pecl_sdet_a 0x0086
#define LSb32smSysCtl_FEPHY_CTRL_yy_pecl_sdet_a 16
#define LSb16smSysCtl_FEPHY_CTRL_yy_pecl_sdet_a 0
#define bsmSysCtl_FEPHY_CTRL_yy_pecl_sdet_a 5
#define MSK32smSysCtl_FEPHY_CTRL_yy_pecl_sdet_a 0x001F0000
#define BA_smSysCtl_FEPHY_CTRL_ps_en_eee10t_s 0x0086
#define B16smSysCtl_FEPHY_CTRL_ps_en_eee10t_s 0x0086
#define LSb32smSysCtl_FEPHY_CTRL_ps_en_eee10t_s 21
#define LSb16smSysCtl_FEPHY_CTRL_ps_en_eee10t_s 5
#define bsmSysCtl_FEPHY_CTRL_ps_en_eee10t_s 1
#define MSK32smSysCtl_FEPHY_CTRL_ps_en_eee10t_s 0x00200000
#define BA_smSysCtl_FEPHY_CTRL_ps_en_eee100t_s 0x0086
#define B16smSysCtl_FEPHY_CTRL_ps_en_eee100t_s 0x0086
#define LSb32smSysCtl_FEPHY_CTRL_ps_en_eee100t_s 22
#define LSb16smSysCtl_FEPHY_CTRL_ps_en_eee100t_s 6
#define bsmSysCtl_FEPHY_CTRL_ps_en_eee100t_s 1
#define MSK32smSysCtl_FEPHY_CTRL_ps_en_eee100t_s 0x00400000
#define BA_smSysCtl_FEPHY_CTRL_pd_burnin_a 0x0086
#define B16smSysCtl_FEPHY_CTRL_pd_burnin_a 0x0086
#define LSb32smSysCtl_FEPHY_CTRL_pd_burnin_a 23
#define LSb16smSysCtl_FEPHY_CTRL_pd_burnin_a 7
#define bsmSysCtl_FEPHY_CTRL_pd_burnin_a 1
#define MSK32smSysCtl_FEPHY_CTRL_pd_burnin_a 0x00800000
#define BA_smSysCtl_FEPHY_CTRL_pd_ena_edet_a 0x0087
#define B16smSysCtl_FEPHY_CTRL_pd_ena_edet_a 0x0086
#define LSb32smSysCtl_FEPHY_CTRL_pd_ena_edet_a 24
#define LSb16smSysCtl_FEPHY_CTRL_pd_ena_edet_a 8
#define bsmSysCtl_FEPHY_CTRL_pd_ena_edet_a 1
#define MSK32smSysCtl_FEPHY_CTRL_pd_ena_edet_a 0x01000000
#define BA_smSysCtl_FEPHY_CTRL_pd_ena_xc_a 0x0087
#define B16smSysCtl_FEPHY_CTRL_pd_ena_xc_a 0x0086
#define LSb32smSysCtl_FEPHY_CTRL_pd_ena_xc_a 25
#define LSb16smSysCtl_FEPHY_CTRL_pd_ena_xc_a 9
#define bsmSysCtl_FEPHY_CTRL_pd_ena_xc_a 1
#define MSK32smSysCtl_FEPHY_CTRL_pd_ena_xc_a 0x02000000
#define BA_smSysCtl_FEPHY_CTRL_ext_coma_a 0x0087
#define B16smSysCtl_FEPHY_CTRL_ext_coma_a 0x0086
#define LSb32smSysCtl_FEPHY_CTRL_ext_coma_a 26
#define LSb16smSysCtl_FEPHY_CTRL_ext_coma_a 10
#define bsmSysCtl_FEPHY_CTRL_ext_coma_a 1
#define MSK32smSysCtl_FEPHY_CTRL_ext_coma_a 0x04000000
///////////////////////////////////////////////////////////
#define RA_smSysCtl_FEPHY_STS 0x0088
#define BA_smSysCtl_FEPHY_STS_misc_speed_s 0x0088
#define B16smSysCtl_FEPHY_STS_misc_speed_s 0x0088
#define LSb32smSysCtl_FEPHY_STS_misc_speed_s 0
#define LSb16smSysCtl_FEPHY_STS_misc_speed_s 0
#define bsmSysCtl_FEPHY_STS_misc_speed_s 1
#define MSK32smSysCtl_FEPHY_STS_misc_speed_s 0x00000001
#define BA_smSysCtl_FEPHY_STS_misc_duplex_s 0x0088
#define B16smSysCtl_FEPHY_STS_misc_duplex_s 0x0088
#define LSb32smSysCtl_FEPHY_STS_misc_duplex_s 1
#define LSb16smSysCtl_FEPHY_STS_misc_duplex_s 1
#define bsmSysCtl_FEPHY_STS_misc_duplex_s 1
#define MSK32smSysCtl_FEPHY_STS_misc_duplex_s 0x00000002
#define BA_smSysCtl_FEPHY_STS_misc_hcd_resolved_s 0x0088
#define B16smSysCtl_FEPHY_STS_misc_hcd_resolved_s 0x0088
#define LSb32smSysCtl_FEPHY_STS_misc_hcd_resolved_s 2
#define LSb16smSysCtl_FEPHY_STS_misc_hcd_resolved_s 2
#define bsmSysCtl_FEPHY_STS_misc_hcd_resolved_s 1
#define MSK32smSysCtl_FEPHY_STS_misc_hcd_resolved_s 0x00000004
#define BA_smSysCtl_FEPHY_STS_misc_link_s 0x0088
#define B16smSysCtl_FEPHY_STS_misc_link_s 0x0088
#define LSb32smSysCtl_FEPHY_STS_misc_link_s 3
#define LSb16smSysCtl_FEPHY_STS_misc_link_s 3
#define bsmSysCtl_FEPHY_STS_misc_link_s 1
#define MSK32smSysCtl_FEPHY_STS_misc_link_s 0x00000008
#define BA_smSysCtl_FEPHY_STS_misc_lpi_s 0x0088
#define B16smSysCtl_FEPHY_STS_misc_lpi_s 0x0088
#define LSb32smSysCtl_FEPHY_STS_misc_lpi_s 4
#define LSb16smSysCtl_FEPHY_STS_misc_lpi_s 4
#define bsmSysCtl_FEPHY_STS_misc_lpi_s 1
#define MSK32smSysCtl_FEPHY_STS_misc_lpi_s 0x00000010
#define BA_smSysCtl_FEPHY_STS_misc_rx_lpi_s 0x0088
#define B16smSysCtl_FEPHY_STS_misc_rx_lpi_s 0x0088
#define LSb32smSysCtl_FEPHY_STS_misc_rx_lpi_s 5
#define LSb16smSysCtl_FEPHY_STS_misc_rx_lpi_s 5
#define bsmSysCtl_FEPHY_STS_misc_rx_lpi_s 1
#define MSK32smSysCtl_FEPHY_STS_misc_rx_lpi_s 0x00000020
#define BA_smSysCtl_FEPHY_STS_misc_pause_s 0x0088
#define B16smSysCtl_FEPHY_STS_misc_pause_s 0x0088
#define LSb32smSysCtl_FEPHY_STS_misc_pause_s 6
#define LSb16smSysCtl_FEPHY_STS_misc_pause_s 6
#define bsmSysCtl_FEPHY_STS_misc_pause_s 1
#define MSK32smSysCtl_FEPHY_STS_misc_pause_s 0x00000040
#define BA_smSysCtl_FEPHY_STS_misc_lp_pause_s 0x0088
#define B16smSysCtl_FEPHY_STS_misc_lp_pause_s 0x0088
#define LSb32smSysCtl_FEPHY_STS_misc_lp_pause_s 7
#define LSb16smSysCtl_FEPHY_STS_misc_lp_pause_s 7
#define bsmSysCtl_FEPHY_STS_misc_lp_pause_s 1
#define MSK32smSysCtl_FEPHY_STS_misc_lp_pause_s 0x00000080
#define BA_smSysCtl_FEPHY_STS_misc_int_s 0x0089
#define B16smSysCtl_FEPHY_STS_misc_int_s 0x0088
#define LSb32smSysCtl_FEPHY_STS_misc_int_s 8
#define LSb16smSysCtl_FEPHY_STS_misc_int_s 8
#define bsmSysCtl_FEPHY_STS_misc_int_s 1
#define MSK32smSysCtl_FEPHY_STS_misc_int_s 0x00000100
#define BA_smSysCtl_FEPHY_STS_misc_edet_status_s 0x0089
#define B16smSysCtl_FEPHY_STS_misc_edet_status_s 0x0088
#define LSb32smSysCtl_FEPHY_STS_misc_edet_status_s 9
#define LSb16smSysCtl_FEPHY_STS_misc_edet_status_s 9
#define bsmSysCtl_FEPHY_STS_misc_edet_status_s 1
#define MSK32smSysCtl_FEPHY_STS_misc_edet_status_s 0x00000200
#define BA_smSysCtl_FEPHY_STS_tx_latency_mark_a 0x0089
#define B16smSysCtl_FEPHY_STS_tx_latency_mark_a 0x0088
#define LSb32smSysCtl_FEPHY_STS_tx_latency_mark_a 10
#define LSb16smSysCtl_FEPHY_STS_tx_latency_mark_a 10
#define bsmSysCtl_FEPHY_STS_tx_latency_mark_a 1
#define MSK32smSysCtl_FEPHY_STS_tx_latency_mark_a 0x00000400
#define BA_smSysCtl_FEPHY_STS_misc_por_reset 0x0089
#define B16smSysCtl_FEPHY_STS_misc_por_reset 0x0088
#define LSb32smSysCtl_FEPHY_STS_misc_por_reset 11
#define LSb16smSysCtl_FEPHY_STS_misc_por_reset 11
#define bsmSysCtl_FEPHY_STS_misc_por_reset 1
#define MSK32smSysCtl_FEPHY_STS_misc_por_reset 0x00000800
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SRAM_PWR_CTRL 0x008C
#define BA_smSysCtl_SRAM_PWR_CTRL_sm_pwr_sram_pwr_ctl 0x008C
#define B16smSysCtl_SRAM_PWR_CTRL_sm_pwr_sram_pwr_ctl 0x008C
#define LSb32smSysCtl_SRAM_PWR_CTRL_sm_pwr_sram_pwr_ctl 0
#define LSb16smSysCtl_SRAM_PWR_CTRL_sm_pwr_sram_pwr_ctl 0
#define bsmSysCtl_SRAM_PWR_CTRL_sm_pwr_sram_pwr_ctl 3
#define MSK32smSysCtl_SRAM_PWR_CTRL_sm_pwr_sram_pwr_ctl 0x00000007
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_POR_AVDD 0x0090
#define BA_smSysCtl_SM_POR_AVDD_BYPASS 0x0090
#define B16smSysCtl_SM_POR_AVDD_BYPASS 0x0090
#define LSb32smSysCtl_SM_POR_AVDD_BYPASS 0
#define LSb16smSysCtl_SM_POR_AVDD_BYPASS 0
#define bsmSysCtl_SM_POR_AVDD_BYPASS 1
#define MSK32smSysCtl_SM_POR_AVDD_BYPASS 0x00000001
#define BA_smSysCtl_SM_POR_AVDD_BYPASS_3P3 0x0090
#define B16smSysCtl_SM_POR_AVDD_BYPASS_3P3 0x0090
#define LSb32smSysCtl_SM_POR_AVDD_BYPASS_3P3 1
#define LSb16smSysCtl_SM_POR_AVDD_BYPASS_3P3 1
#define bsmSysCtl_SM_POR_AVDD_BYPASS_3P3 1
#define MSK32smSysCtl_SM_POR_AVDD_BYPASS_3P3 0x00000002
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_GLOBAL_PADRING 0x0094
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_GPIO_PADRING 0x009C
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_I2C_PADRING 0x00A4
///////////////////////////////////////////////////////////
#define RA_smSysCtl_DDC_PAD_CTRL 0x00AC
#define BA_smSysCtl_DDC_PAD_CTRL_ZN_SM_TW2_SCL 0x00AC
#define B16smSysCtl_DDC_PAD_CTRL_ZN_SM_TW2_SCL 0x00AC
#define LSb32smSysCtl_DDC_PAD_CTRL_ZN_SM_TW2_SCL 0
#define LSb16smSysCtl_DDC_PAD_CTRL_ZN_SM_TW2_SCL 0
#define bsmSysCtl_DDC_PAD_CTRL_ZN_SM_TW2_SCL 3
#define MSK32smSysCtl_DDC_PAD_CTRL_ZN_SM_TW2_SCL 0x00000007
#define BA_smSysCtl_DDC_PAD_CTRL_ZN_SM_TW2_SDA 0x00AC
#define B16smSysCtl_DDC_PAD_CTRL_ZN_SM_TW2_SDA 0x00AC
#define LSb32smSysCtl_DDC_PAD_CTRL_ZN_SM_TW2_SDA 3
#define LSb16smSysCtl_DDC_PAD_CTRL_ZN_SM_TW2_SDA 3
#define bsmSysCtl_DDC_PAD_CTRL_ZN_SM_TW2_SDA 3
#define MSK32smSysCtl_DDC_PAD_CTRL_ZN_SM_TW2_SDA 0x00000038
#define BA_smSysCtl_DDC_PAD_CTRL_ZN_SM_TW3_SCL 0x00AC
#define B16smSysCtl_DDC_PAD_CTRL_ZN_SM_TW3_SCL 0x00AC
#define LSb32smSysCtl_DDC_PAD_CTRL_ZN_SM_TW3_SCL 6
#define LSb16smSysCtl_DDC_PAD_CTRL_ZN_SM_TW3_SCL 6
#define bsmSysCtl_DDC_PAD_CTRL_ZN_SM_TW3_SCL 3
#define MSK32smSysCtl_DDC_PAD_CTRL_ZN_SM_TW3_SCL 0x000001C0
#define BA_smSysCtl_DDC_PAD_CTRL_ZN_SM_TW3_SDA 0x00AD
#define B16smSysCtl_DDC_PAD_CTRL_ZN_SM_TW3_SDA 0x00AC
#define LSb32smSysCtl_DDC_PAD_CTRL_ZN_SM_TW3_SDA 9
#define LSb16smSysCtl_DDC_PAD_CTRL_ZN_SM_TW3_SDA 9
#define bsmSysCtl_DDC_PAD_CTRL_ZN_SM_TW3_SDA 3
#define MSK32smSysCtl_DDC_PAD_CTRL_ZN_SM_TW3_SDA 0x00000E00
#define BA_smSysCtl_DDC_PAD_CTRL_ZN_RX_EDDC_SCL 0x00AD
#define B16smSysCtl_DDC_PAD_CTRL_ZN_RX_EDDC_SCL 0x00AC
#define LSb32smSysCtl_DDC_PAD_CTRL_ZN_RX_EDDC_SCL 12
#define LSb16smSysCtl_DDC_PAD_CTRL_ZN_RX_EDDC_SCL 12
#define bsmSysCtl_DDC_PAD_CTRL_ZN_RX_EDDC_SCL 3
#define MSK32smSysCtl_DDC_PAD_CTRL_ZN_RX_EDDC_SCL 0x00007000
#define BA_smSysCtl_DDC_PAD_CTRL_ZN_RX_EDDC_SDA 0x00AD
#define B16smSysCtl_DDC_PAD_CTRL_ZN_RX_EDDC_SDA 0x00AC
#define LSb32smSysCtl_DDC_PAD_CTRL_ZN_RX_EDDC_SDA 15
#define LSb16smSysCtl_DDC_PAD_CTRL_ZN_RX_EDDC_SDA 15
#define bsmSysCtl_DDC_PAD_CTRL_ZN_RX_EDDC_SDA 3
#define MSK32smSysCtl_DDC_PAD_CTRL_ZN_RX_EDDC_SDA 0x00038000
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_PWR_OK 0x00B0
#define BA_smSysCtl_SM_PWR_OK_status 0x00B0
#define B16smSysCtl_SM_PWR_OK_status 0x00B0
#define LSb32smSysCtl_SM_PWR_OK_status 0
#define LSb16smSysCtl_SM_PWR_OK_status 0
#define bsmSysCtl_SM_PWR_OK_status 1
#define MSK32smSysCtl_SM_PWR_OK_status 0x00000001
///////////////////////////////////////////////////////////
#define RA_smSysCtl_EDID 0x0400
///////////////////////////////////////////////////////////
#define RA_smSysCtl_smPinMuxCntlBus 0x0C00
#define BA_smSysCtl_smPinMuxCntlBus_SM_URT0_TXD 0x0C00
#define B16smSysCtl_smPinMuxCntlBus_SM_URT0_TXD 0x0C00
#define LSb32smSysCtl_smPinMuxCntlBus_SM_URT0_TXD 0
#define LSb16smSysCtl_smPinMuxCntlBus_SM_URT0_TXD 0
#define bsmSysCtl_smPinMuxCntlBus_SM_URT0_TXD 3
#define MSK32smSysCtl_smPinMuxCntlBus_SM_URT0_TXD 0x00000007
#define smSysCtl_smPinMuxCntlBus_SM_URT0_TXD_MODE_0 0x0
#define smSysCtl_smPinMuxCntlBus_SM_URT0_TXD_MODE_1 0x1
#define BA_smSysCtl_smPinMuxCntlBus_SM_URT0_RXD 0x0C00
#define B16smSysCtl_smPinMuxCntlBus_SM_URT0_RXD 0x0C00
#define LSb32smSysCtl_smPinMuxCntlBus_SM_URT0_RXD 3
#define LSb16smSysCtl_smPinMuxCntlBus_SM_URT0_RXD 3
#define bsmSysCtl_smPinMuxCntlBus_SM_URT0_RXD 3
#define MSK32smSysCtl_smPinMuxCntlBus_SM_URT0_RXD 0x00000038
#define smSysCtl_smPinMuxCntlBus_SM_URT0_RXD_MODE_0 0x0
#define smSysCtl_smPinMuxCntlBus_SM_URT0_RXD_MODE_1 0x1
#define BA_smSysCtl_smPinMuxCntlBus_SM_URT1_TXD 0x0C00
#define B16smSysCtl_smPinMuxCntlBus_SM_URT1_TXD 0x0C00
#define LSb32smSysCtl_smPinMuxCntlBus_SM_URT1_TXD 6
#define LSb16smSysCtl_smPinMuxCntlBus_SM_URT1_TXD 6
#define bsmSysCtl_smPinMuxCntlBus_SM_URT1_TXD 3
#define MSK32smSysCtl_smPinMuxCntlBus_SM_URT1_TXD 0x000001C0
#define smSysCtl_smPinMuxCntlBus_SM_URT1_TXD_MODE_0 0x0
#define smSysCtl_smPinMuxCntlBus_SM_URT1_TXD_MODE_1 0x1
#define smSysCtl_smPinMuxCntlBus_SM_URT1_TXD_MODE_3 0x3
#define smSysCtl_smPinMuxCntlBus_SM_URT1_TXD_MODE_4 0x4
#define smSysCtl_smPinMuxCntlBus_SM_URT1_TXD_MODE_5 0x5
#define smSysCtl_smPinMuxCntlBus_SM_URT1_TXD_MODE_6 0x6
#define smSysCtl_smPinMuxCntlBus_SM_URT1_TXD_MODE_7 0x7
#define BA_smSysCtl_smPinMuxCntlBus_SM_URT1_RXD 0x0C01
#define B16smSysCtl_smPinMuxCntlBus_SM_URT1_RXD 0x0C00
#define LSb32smSysCtl_smPinMuxCntlBus_SM_URT1_RXD 9
#define LSb16smSysCtl_smPinMuxCntlBus_SM_URT1_RXD 9
#define bsmSysCtl_smPinMuxCntlBus_SM_URT1_RXD 3
#define MSK32smSysCtl_smPinMuxCntlBus_SM_URT1_RXD 0x00000E00
#define smSysCtl_smPinMuxCntlBus_SM_URT1_RXD_MODE_0 0x0
#define smSysCtl_smPinMuxCntlBus_SM_URT1_RXD_MODE_1 0x1
#define smSysCtl_smPinMuxCntlBus_SM_URT1_RXD_MODE_3 0x3
#define smSysCtl_smPinMuxCntlBus_SM_URT1_RXD_MODE_4 0x4
#define smSysCtl_smPinMuxCntlBus_SM_URT1_RXD_MODE_7 0x7
#define BA_smSysCtl_smPinMuxCntlBus_SM_SPI2_SS0n 0x0C01
#define B16smSysCtl_smPinMuxCntlBus_SM_SPI2_SS0n 0x0C00
#define LSb32smSysCtl_smPinMuxCntlBus_SM_SPI2_SS0n 12
#define LSb16smSysCtl_smPinMuxCntlBus_SM_SPI2_SS0n 12
#define bsmSysCtl_smPinMuxCntlBus_SM_SPI2_SS0n 3
#define MSK32smSysCtl_smPinMuxCntlBus_SM_SPI2_SS0n 0x00007000
#define smSysCtl_smPinMuxCntlBus_SM_SPI2_SS0n_MODE_0 0x0
#define smSysCtl_smPinMuxCntlBus_SM_SPI2_SS0n_MODE_1 0x1
#define BA_smSysCtl_smPinMuxCntlBus_SM_SPI2_SS1n 0x0C01
#define B16smSysCtl_smPinMuxCntlBus_SM_SPI2_SS1n 0x0C00
#define LSb32smSysCtl_smPinMuxCntlBus_SM_SPI2_SS1n 15
#define LSb16smSysCtl_smPinMuxCntlBus_SM_SPI2_SS1n 15
#define bsmSysCtl_smPinMuxCntlBus_SM_SPI2_SS1n 3
#define MSK32smSysCtl_smPinMuxCntlBus_SM_SPI2_SS1n 0x00038000
#define smSysCtl_smPinMuxCntlBus_SM_SPI2_SS1n_MODE_0 0x0
#define smSysCtl_smPinMuxCntlBus_SM_SPI2_SS1n_MODE_1 0x1
#define smSysCtl_smPinMuxCntlBus_SM_SPI2_SS1n_MODE_2 0x2
#define BA_smSysCtl_smPinMuxCntlBus_SM_SPI2_SS2n 0x0C02
#define B16smSysCtl_smPinMuxCntlBus_SM_SPI2_SS2n 0x0C02
#define LSb32smSysCtl_smPinMuxCntlBus_SM_SPI2_SS2n 18
#define LSb16smSysCtl_smPinMuxCntlBus_SM_SPI2_SS2n 2
#define bsmSysCtl_smPinMuxCntlBus_SM_SPI2_SS2n 3
#define MSK32smSysCtl_smPinMuxCntlBus_SM_SPI2_SS2n 0x001C0000
#define smSysCtl_smPinMuxCntlBus_SM_SPI2_SS2n_MODE_0 0x0
#define smSysCtl_smPinMuxCntlBus_SM_SPI2_SS2n_MODE_1 0x1
#define smSysCtl_smPinMuxCntlBus_SM_SPI2_SS2n_MODE_3 0x3
#define smSysCtl_smPinMuxCntlBus_SM_SPI2_SS2n_MODE_4 0x4
#define smSysCtl_smPinMuxCntlBus_SM_SPI2_SS2n_MODE_5 0x5
#define smSysCtl_smPinMuxCntlBus_SM_SPI2_SS2n_MODE_6 0x6
#define BA_smSysCtl_smPinMuxCntlBus_SM_SPI2_SS3n 0x0C02
#define B16smSysCtl_smPinMuxCntlBus_SM_SPI2_SS3n 0x0C02
#define LSb32smSysCtl_smPinMuxCntlBus_SM_SPI2_SS3n 21
#define LSb16smSysCtl_smPinMuxCntlBus_SM_SPI2_SS3n 5
#define bsmSysCtl_smPinMuxCntlBus_SM_SPI2_SS3n 3
#define MSK32smSysCtl_smPinMuxCntlBus_SM_SPI2_SS3n 0x00E00000
#define smSysCtl_smPinMuxCntlBus_SM_SPI2_SS3n_MODE_0 0x0
#define smSysCtl_smPinMuxCntlBus_SM_SPI2_SS3n_MODE_1 0x1
#define smSysCtl_smPinMuxCntlBus_SM_SPI2_SS3n_MODE_2 0x2
#define smSysCtl_smPinMuxCntlBus_SM_SPI2_SS3n_MODE_3 0x3
#define smSysCtl_smPinMuxCntlBus_SM_SPI2_SS3n_MODE_4 0x4
#define smSysCtl_smPinMuxCntlBus_SM_SPI2_SS3n_MODE_6 0x6
#define BA_smSysCtl_smPinMuxCntlBus_SM_SPI2_SDO 0x0C03
#define B16smSysCtl_smPinMuxCntlBus_SM_SPI2_SDO 0x0C02
#define LSb32smSysCtl_smPinMuxCntlBus_SM_SPI2_SDO 24
#define LSb16smSysCtl_smPinMuxCntlBus_SM_SPI2_SDO 8
#define bsmSysCtl_smPinMuxCntlBus_SM_SPI2_SDO 3
#define MSK32smSysCtl_smPinMuxCntlBus_SM_SPI2_SDO 0x07000000
#define smSysCtl_smPinMuxCntlBus_SM_SPI2_SDO_MODE_0 0x0
#define smSysCtl_smPinMuxCntlBus_SM_SPI2_SDO_MODE_1 0x1
#define BA_smSysCtl_smPinMuxCntlBus_SM_SPI2_SDI 0x0C03
#define B16smSysCtl_smPinMuxCntlBus_SM_SPI2_SDI 0x0C02
#define LSb32smSysCtl_smPinMuxCntlBus_SM_SPI2_SDI 27
#define LSb16smSysCtl_smPinMuxCntlBus_SM_SPI2_SDI 11
#define bsmSysCtl_smPinMuxCntlBus_SM_SPI2_SDI 3
#define MSK32smSysCtl_smPinMuxCntlBus_SM_SPI2_SDI 0x38000000
#define smSysCtl_smPinMuxCntlBus_SM_SPI2_SDI_MODE_0 0x0
#define smSysCtl_smPinMuxCntlBus_SM_SPI2_SDI_MODE_1 0x1
#define RA_smSysCtl_smPinMuxCntlBus1 0x0C04
#define BA_smSysCtl_smPinMuxCntlBus_SM_SPI2_SCLK 0x0C04
#define B16smSysCtl_smPinMuxCntlBus_SM_SPI2_SCLK 0x0C04
#define LSb32smSysCtl_smPinMuxCntlBus_SM_SPI2_SCLK 0
#define LSb16smSysCtl_smPinMuxCntlBus_SM_SPI2_SCLK 0
#define bsmSysCtl_smPinMuxCntlBus_SM_SPI2_SCLK 3
#define MSK32smSysCtl_smPinMuxCntlBus_SM_SPI2_SCLK 0x00000007
#define smSysCtl_smPinMuxCntlBus_SM_SPI2_SCLK_MODE_0 0x0
#define smSysCtl_smPinMuxCntlBus_SM_SPI2_SCLK_MODE_1 0x1
#define BA_smSysCtl_smPinMuxCntlBus_SM_FE_LED0 0x0C04
#define B16smSysCtl_smPinMuxCntlBus_SM_FE_LED0 0x0C04
#define LSb32smSysCtl_smPinMuxCntlBus_SM_FE_LED0 3
#define LSb16smSysCtl_smPinMuxCntlBus_SM_FE_LED0 3
#define bsmSysCtl_smPinMuxCntlBus_SM_FE_LED0 3
#define MSK32smSysCtl_smPinMuxCntlBus_SM_FE_LED0 0x00000038
#define smSysCtl_smPinMuxCntlBus_SM_FE_LED0_MODE_0 0x0
#define smSysCtl_smPinMuxCntlBus_SM_FE_LED0_MODE_2 0x2
#define smSysCtl_smPinMuxCntlBus_SM_FE_LED0_MODE_7 0x7
#define BA_smSysCtl_smPinMuxCntlBus_SM_FE_LED1 0x0C04
#define B16smSysCtl_smPinMuxCntlBus_SM_FE_LED1 0x0C04
#define LSb32smSysCtl_smPinMuxCntlBus_SM_FE_LED1 6
#define LSb16smSysCtl_smPinMuxCntlBus_SM_FE_LED1 6
#define bsmSysCtl_smPinMuxCntlBus_SM_FE_LED1 3
#define MSK32smSysCtl_smPinMuxCntlBus_SM_FE_LED1 0x000001C0
#define smSysCtl_smPinMuxCntlBus_SM_FE_LED1_MODE_0 0x0
#define smSysCtl_smPinMuxCntlBus_SM_FE_LED1_MODE_1 0x1
#define smSysCtl_smPinMuxCntlBus_SM_FE_LED1_MODE_2 0x2
#define BA_smSysCtl_smPinMuxCntlBus_SM_FE_LED2 0x0C05
#define B16smSysCtl_smPinMuxCntlBus_SM_FE_LED2 0x0C04
#define LSb32smSysCtl_smPinMuxCntlBus_SM_FE_LED2 9
#define LSb16smSysCtl_smPinMuxCntlBus_SM_FE_LED2 9
#define bsmSysCtl_smPinMuxCntlBus_SM_FE_LED2 3
#define MSK32smSysCtl_smPinMuxCntlBus_SM_FE_LED2 0x00000E00
#define smSysCtl_smPinMuxCntlBus_SM_FE_LED2_MODE_0 0x0
#define smSysCtl_smPinMuxCntlBus_SM_FE_LED2_MODE_2 0x2
#define smSysCtl_smPinMuxCntlBus_SM_FE_LED2_MODE_7 0x7
#define BA_smSysCtl_smPinMuxCntlBus_SM_HDMI_HPD 0x0C05
#define B16smSysCtl_smPinMuxCntlBus_SM_HDMI_HPD 0x0C04
#define LSb32smSysCtl_smPinMuxCntlBus_SM_HDMI_HPD 12
#define LSb16smSysCtl_smPinMuxCntlBus_SM_HDMI_HPD 12
#define bsmSysCtl_smPinMuxCntlBus_SM_HDMI_HPD 3
#define MSK32smSysCtl_smPinMuxCntlBus_SM_HDMI_HPD 0x00007000
#define smSysCtl_smPinMuxCntlBus_SM_HDMI_HPD_MODE_0 0x0
#define smSysCtl_smPinMuxCntlBus_SM_HDMI_HPD_MODE_1 0x1
#define BA_smSysCtl_smPinMuxCntlBus_SM_HDMI_CEC 0x0C05
#define B16smSysCtl_smPinMuxCntlBus_SM_HDMI_CEC 0x0C04
#define LSb32smSysCtl_smPinMuxCntlBus_SM_HDMI_CEC 15
#define LSb16smSysCtl_smPinMuxCntlBus_SM_HDMI_CEC 15
#define bsmSysCtl_smPinMuxCntlBus_SM_HDMI_CEC 3
#define MSK32smSysCtl_smPinMuxCntlBus_SM_HDMI_CEC 0x00038000
#define smSysCtl_smPinMuxCntlBus_SM_HDMI_CEC_MODE_0 0x0
#define smSysCtl_smPinMuxCntlBus_SM_HDMI_CEC_MODE_1 0x1
#define BA_smSysCtl_smPinMuxCntlBus_SM_TW2_SCL 0x0C06
#define B16smSysCtl_smPinMuxCntlBus_SM_TW2_SCL 0x0C06
#define LSb32smSysCtl_smPinMuxCntlBus_SM_TW2_SCL 18
#define LSb16smSysCtl_smPinMuxCntlBus_SM_TW2_SCL 2
#define bsmSysCtl_smPinMuxCntlBus_SM_TW2_SCL 3
#define MSK32smSysCtl_smPinMuxCntlBus_SM_TW2_SCL 0x001C0000
#define smSysCtl_smPinMuxCntlBus_SM_TW2_SCL_MODE_0 0x0
#define smSysCtl_smPinMuxCntlBus_SM_TW2_SCL_MODE_1 0x1
#define smSysCtl_smPinMuxCntlBus_SM_TW2_SCL_MODE_2 0x2
#define BA_smSysCtl_smPinMuxCntlBus_SM_TW2_SDA 0x0C06
#define B16smSysCtl_smPinMuxCntlBus_SM_TW2_SDA 0x0C06
#define LSb32smSysCtl_smPinMuxCntlBus_SM_TW2_SDA 21
#define LSb16smSysCtl_smPinMuxCntlBus_SM_TW2_SDA 5
#define bsmSysCtl_smPinMuxCntlBus_SM_TW2_SDA 3
#define MSK32smSysCtl_smPinMuxCntlBus_SM_TW2_SDA 0x00E00000
#define smSysCtl_smPinMuxCntlBus_SM_TW2_SDA_MODE_0 0x0
#define smSysCtl_smPinMuxCntlBus_SM_TW2_SDA_MODE_1 0x1
#define BA_smSysCtl_smPinMuxCntlBus_SM_TW3_SCL 0x0C07
#define B16smSysCtl_smPinMuxCntlBus_SM_TW3_SCL 0x0C06
#define LSb32smSysCtl_smPinMuxCntlBus_SM_TW3_SCL 24
#define LSb16smSysCtl_smPinMuxCntlBus_SM_TW3_SCL 8
#define bsmSysCtl_smPinMuxCntlBus_SM_TW3_SCL 3
#define MSK32smSysCtl_smPinMuxCntlBus_SM_TW3_SCL 0x07000000
#define smSysCtl_smPinMuxCntlBus_SM_TW3_SCL_MODE_0 0x0
#define smSysCtl_smPinMuxCntlBus_SM_TW3_SCL_MODE_1 0x1
#define smSysCtl_smPinMuxCntlBus_SM_TW3_SCL_MODE_2 0x2
#define BA_smSysCtl_smPinMuxCntlBus_SM_TW3_SDA 0x0C07
#define B16smSysCtl_smPinMuxCntlBus_SM_TW3_SDA 0x0C06
#define LSb32smSysCtl_smPinMuxCntlBus_SM_TW3_SDA 27
#define LSb16smSysCtl_smPinMuxCntlBus_SM_TW3_SDA 11
#define bsmSysCtl_smPinMuxCntlBus_SM_TW3_SDA 3
#define MSK32smSysCtl_smPinMuxCntlBus_SM_TW3_SDA 0x38000000
#define smSysCtl_smPinMuxCntlBus_SM_TW3_SDA_MODE_0 0x0
#define smSysCtl_smPinMuxCntlBus_SM_TW3_SDA_MODE_1 0x1
#define RA_smSysCtl_smPinMuxCntlBus2 0x0C08
#define BA_smSysCtl_smPinMuxCntlBus_SM_RX_EDDC_SCL 0x0C08
#define B16smSysCtl_smPinMuxCntlBus_SM_RX_EDDC_SCL 0x0C08
#define LSb32smSysCtl_smPinMuxCntlBus_SM_RX_EDDC_SCL 0
#define LSb16smSysCtl_smPinMuxCntlBus_SM_RX_EDDC_SCL 0
#define bsmSysCtl_smPinMuxCntlBus_SM_RX_EDDC_SCL 3
#define MSK32smSysCtl_smPinMuxCntlBus_SM_RX_EDDC_SCL 0x00000007
#define smSysCtl_smPinMuxCntlBus_SM_RX_EDDC_SCL_MODE_0 0x0
#define smSysCtl_smPinMuxCntlBus_SM_RX_EDDC_SCL_MODE_1 0x1
#define BA_smSysCtl_smPinMuxCntlBus_SM_RX_EDDC_SDA 0x0C08
#define B16smSysCtl_smPinMuxCntlBus_SM_RX_EDDC_SDA 0x0C08
#define LSb32smSysCtl_smPinMuxCntlBus_SM_RX_EDDC_SDA 3
#define LSb16smSysCtl_smPinMuxCntlBus_SM_RX_EDDC_SDA 3
#define bsmSysCtl_smPinMuxCntlBus_SM_RX_EDDC_SDA 3
#define MSK32smSysCtl_smPinMuxCntlBus_SM_RX_EDDC_SDA 0x00000038
#define smSysCtl_smPinMuxCntlBus_SM_RX_EDDC_SDA_MODE_0 0x0
#define smSysCtl_smPinMuxCntlBus_SM_RX_EDDC_SDA_MODE_1 0x1
#define BA_smSysCtl_smPinMuxCntlBus_SM_HDMIRX_HPD 0x0C08
#define B16smSysCtl_smPinMuxCntlBus_SM_HDMIRX_HPD 0x0C08
#define LSb32smSysCtl_smPinMuxCntlBus_SM_HDMIRX_HPD 6
#define LSb16smSysCtl_smPinMuxCntlBus_SM_HDMIRX_HPD 6
#define bsmSysCtl_smPinMuxCntlBus_SM_HDMIRX_HPD 3
#define MSK32smSysCtl_smPinMuxCntlBus_SM_HDMIRX_HPD 0x000001C0
#define smSysCtl_smPinMuxCntlBus_SM_HDMIRX_HPD_MODE_0 0x0
#define smSysCtl_smPinMuxCntlBus_SM_HDMIRX_HPD_MODE_1 0x1
#define BA_smSysCtl_smPinMuxCntlBus_SM_TMS 0x0C09
#define B16smSysCtl_smPinMuxCntlBus_SM_TMS 0x0C08
#define LSb32smSysCtl_smPinMuxCntlBus_SM_TMS 9
#define LSb16smSysCtl_smPinMuxCntlBus_SM_TMS 9
#define bsmSysCtl_smPinMuxCntlBus_SM_TMS 3
#define MSK32smSysCtl_smPinMuxCntlBus_SM_TMS 0x00000E00
#define smSysCtl_smPinMuxCntlBus_SM_TMS_MODE_0 0x0
#define smSysCtl_smPinMuxCntlBus_SM_TMS_MODE_1 0x1
#define smSysCtl_smPinMuxCntlBus_SM_TMS_MODE_2 0x2
#define smSysCtl_smPinMuxCntlBus_SM_TMS_MODE_3 0x3
#define BA_smSysCtl_smPinMuxCntlBus_SM_TDI 0x0C09
#define B16smSysCtl_smPinMuxCntlBus_SM_TDI 0x0C08
#define LSb32smSysCtl_smPinMuxCntlBus_SM_TDI 12
#define LSb16smSysCtl_smPinMuxCntlBus_SM_TDI 12
#define bsmSysCtl_smPinMuxCntlBus_SM_TDI 3
#define MSK32smSysCtl_smPinMuxCntlBus_SM_TDI 0x00007000
#define smSysCtl_smPinMuxCntlBus_SM_TDI_MODE_0 0x0
#define smSysCtl_smPinMuxCntlBus_SM_TDI_MODE_1 0x1
#define smSysCtl_smPinMuxCntlBus_SM_TDI_MODE_2 0x2
#define smSysCtl_smPinMuxCntlBus_SM_TDI_MODE_3 0x3
#define BA_smSysCtl_smPinMuxCntlBus_SM_TDO 0x0C09
#define B16smSysCtl_smPinMuxCntlBus_SM_TDO 0x0C08
#define LSb32smSysCtl_smPinMuxCntlBus_SM_TDO 15
#define LSb16smSysCtl_smPinMuxCntlBus_SM_TDO 15
#define bsmSysCtl_smPinMuxCntlBus_SM_TDO 3
#define MSK32smSysCtl_smPinMuxCntlBus_SM_TDO 0x00038000
#define smSysCtl_smPinMuxCntlBus_SM_TDO_MODE_0 0x0
#define smSysCtl_smPinMuxCntlBus_SM_TDO_MODE_1 0x1
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_URT0_TXDCntl 0x0C0C
#define BA_smSysCtl_SM_URT0_TXDCntl_PD_EN 0x0C0C
#define B16smSysCtl_SM_URT0_TXDCntl_PD_EN 0x0C0C
#define LSb32smSysCtl_SM_URT0_TXDCntl_PD_EN 0
#define LSb16smSysCtl_SM_URT0_TXDCntl_PD_EN 0
#define bsmSysCtl_SM_URT0_TXDCntl_PD_EN 1
#define MSK32smSysCtl_SM_URT0_TXDCntl_PD_EN 0x00000001
#define BA_smSysCtl_SM_URT0_TXDCntl_PU_EN 0x0C0C
#define B16smSysCtl_SM_URT0_TXDCntl_PU_EN 0x0C0C
#define LSb32smSysCtl_SM_URT0_TXDCntl_PU_EN 1
#define LSb16smSysCtl_SM_URT0_TXDCntl_PU_EN 1
#define bsmSysCtl_SM_URT0_TXDCntl_PU_EN 1
#define MSK32smSysCtl_SM_URT0_TXDCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_URT0_RXDCntl 0x0C10
#define BA_smSysCtl_SM_URT0_RXDCntl_PD_EN 0x0C10
#define B16smSysCtl_SM_URT0_RXDCntl_PD_EN 0x0C10
#define LSb32smSysCtl_SM_URT0_RXDCntl_PD_EN 0
#define LSb16smSysCtl_SM_URT0_RXDCntl_PD_EN 0
#define bsmSysCtl_SM_URT0_RXDCntl_PD_EN 1
#define MSK32smSysCtl_SM_URT0_RXDCntl_PD_EN 0x00000001
#define BA_smSysCtl_SM_URT0_RXDCntl_PU_EN 0x0C10
#define B16smSysCtl_SM_URT0_RXDCntl_PU_EN 0x0C10
#define LSb32smSysCtl_SM_URT0_RXDCntl_PU_EN 1
#define LSb16smSysCtl_SM_URT0_RXDCntl_PU_EN 1
#define bsmSysCtl_SM_URT0_RXDCntl_PU_EN 1
#define MSK32smSysCtl_SM_URT0_RXDCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_URT1_TXDCntl 0x0C14
#define BA_smSysCtl_SM_URT1_TXDCntl_PD_EN 0x0C14
#define B16smSysCtl_SM_URT1_TXDCntl_PD_EN 0x0C14
#define LSb32smSysCtl_SM_URT1_TXDCntl_PD_EN 0
#define LSb16smSysCtl_SM_URT1_TXDCntl_PD_EN 0
#define bsmSysCtl_SM_URT1_TXDCntl_PD_EN 1
#define MSK32smSysCtl_SM_URT1_TXDCntl_PD_EN 0x00000001
#define BA_smSysCtl_SM_URT1_TXDCntl_PU_EN 0x0C14
#define B16smSysCtl_SM_URT1_TXDCntl_PU_EN 0x0C14
#define LSb32smSysCtl_SM_URT1_TXDCntl_PU_EN 1
#define LSb16smSysCtl_SM_URT1_TXDCntl_PU_EN 1
#define bsmSysCtl_SM_URT1_TXDCntl_PU_EN 1
#define MSK32smSysCtl_SM_URT1_TXDCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_URT1_RXDCntl 0x0C18
#define BA_smSysCtl_SM_URT1_RXDCntl_PD_EN 0x0C18
#define B16smSysCtl_SM_URT1_RXDCntl_PD_EN 0x0C18
#define LSb32smSysCtl_SM_URT1_RXDCntl_PD_EN 0
#define LSb16smSysCtl_SM_URT1_RXDCntl_PD_EN 0
#define bsmSysCtl_SM_URT1_RXDCntl_PD_EN 1
#define MSK32smSysCtl_SM_URT1_RXDCntl_PD_EN 0x00000001
#define BA_smSysCtl_SM_URT1_RXDCntl_PU_EN 0x0C18
#define B16smSysCtl_SM_URT1_RXDCntl_PU_EN 0x0C18
#define LSb32smSysCtl_SM_URT1_RXDCntl_PU_EN 1
#define LSb16smSysCtl_SM_URT1_RXDCntl_PU_EN 1
#define bsmSysCtl_SM_URT1_RXDCntl_PU_EN 1
#define MSK32smSysCtl_SM_URT1_RXDCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_SPI2_SS0nCntl 0x0C1C
#define BA_smSysCtl_SM_SPI2_SS0nCntl_PD_EN 0x0C1C
#define B16smSysCtl_SM_SPI2_SS0nCntl_PD_EN 0x0C1C
#define LSb32smSysCtl_SM_SPI2_SS0nCntl_PD_EN 0
#define LSb16smSysCtl_SM_SPI2_SS0nCntl_PD_EN 0
#define bsmSysCtl_SM_SPI2_SS0nCntl_PD_EN 1
#define MSK32smSysCtl_SM_SPI2_SS0nCntl_PD_EN 0x00000001
#define BA_smSysCtl_SM_SPI2_SS0nCntl_PU_EN 0x0C1C
#define B16smSysCtl_SM_SPI2_SS0nCntl_PU_EN 0x0C1C
#define LSb32smSysCtl_SM_SPI2_SS0nCntl_PU_EN 1
#define LSb16smSysCtl_SM_SPI2_SS0nCntl_PU_EN 1
#define bsmSysCtl_SM_SPI2_SS0nCntl_PU_EN 1
#define MSK32smSysCtl_SM_SPI2_SS0nCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_SPI2_SS1nCntl 0x0C20
#define BA_smSysCtl_SM_SPI2_SS1nCntl_PD_EN 0x0C20
#define B16smSysCtl_SM_SPI2_SS1nCntl_PD_EN 0x0C20
#define LSb32smSysCtl_SM_SPI2_SS1nCntl_PD_EN 0
#define LSb16smSysCtl_SM_SPI2_SS1nCntl_PD_EN 0
#define bsmSysCtl_SM_SPI2_SS1nCntl_PD_EN 1
#define MSK32smSysCtl_SM_SPI2_SS1nCntl_PD_EN 0x00000001
#define BA_smSysCtl_SM_SPI2_SS1nCntl_PU_EN 0x0C20
#define B16smSysCtl_SM_SPI2_SS1nCntl_PU_EN 0x0C20
#define LSb32smSysCtl_SM_SPI2_SS1nCntl_PU_EN 1
#define LSb16smSysCtl_SM_SPI2_SS1nCntl_PU_EN 1
#define bsmSysCtl_SM_SPI2_SS1nCntl_PU_EN 1
#define MSK32smSysCtl_SM_SPI2_SS1nCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_SPI2_SS2nCntl 0x0C24
#define BA_smSysCtl_SM_SPI2_SS2nCntl_PD_EN 0x0C24
#define B16smSysCtl_SM_SPI2_SS2nCntl_PD_EN 0x0C24
#define LSb32smSysCtl_SM_SPI2_SS2nCntl_PD_EN 0
#define LSb16smSysCtl_SM_SPI2_SS2nCntl_PD_EN 0
#define bsmSysCtl_SM_SPI2_SS2nCntl_PD_EN 1
#define MSK32smSysCtl_SM_SPI2_SS2nCntl_PD_EN 0x00000001
#define BA_smSysCtl_SM_SPI2_SS2nCntl_PU_EN 0x0C24
#define B16smSysCtl_SM_SPI2_SS2nCntl_PU_EN 0x0C24
#define LSb32smSysCtl_SM_SPI2_SS2nCntl_PU_EN 1
#define LSb16smSysCtl_SM_SPI2_SS2nCntl_PU_EN 1
#define bsmSysCtl_SM_SPI2_SS2nCntl_PU_EN 1
#define MSK32smSysCtl_SM_SPI2_SS2nCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_SPI2_SS3nCntl 0x0C28
#define BA_smSysCtl_SM_SPI2_SS3nCntl_PD_EN 0x0C28
#define B16smSysCtl_SM_SPI2_SS3nCntl_PD_EN 0x0C28
#define LSb32smSysCtl_SM_SPI2_SS3nCntl_PD_EN 0
#define LSb16smSysCtl_SM_SPI2_SS3nCntl_PD_EN 0
#define bsmSysCtl_SM_SPI2_SS3nCntl_PD_EN 1
#define MSK32smSysCtl_SM_SPI2_SS3nCntl_PD_EN 0x00000001
#define BA_smSysCtl_SM_SPI2_SS3nCntl_PU_EN 0x0C28
#define B16smSysCtl_SM_SPI2_SS3nCntl_PU_EN 0x0C28
#define LSb32smSysCtl_SM_SPI2_SS3nCntl_PU_EN 1
#define LSb16smSysCtl_SM_SPI2_SS3nCntl_PU_EN 1
#define bsmSysCtl_SM_SPI2_SS3nCntl_PU_EN 1
#define MSK32smSysCtl_SM_SPI2_SS3nCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_SPI2_SDOCntl 0x0C2C
#define BA_smSysCtl_SM_SPI2_SDOCntl_PD_EN 0x0C2C
#define B16smSysCtl_SM_SPI2_SDOCntl_PD_EN 0x0C2C
#define LSb32smSysCtl_SM_SPI2_SDOCntl_PD_EN 0
#define LSb16smSysCtl_SM_SPI2_SDOCntl_PD_EN 0
#define bsmSysCtl_SM_SPI2_SDOCntl_PD_EN 1
#define MSK32smSysCtl_SM_SPI2_SDOCntl_PD_EN 0x00000001
#define BA_smSysCtl_SM_SPI2_SDOCntl_PU_EN 0x0C2C
#define B16smSysCtl_SM_SPI2_SDOCntl_PU_EN 0x0C2C
#define LSb32smSysCtl_SM_SPI2_SDOCntl_PU_EN 1
#define LSb16smSysCtl_SM_SPI2_SDOCntl_PU_EN 1
#define bsmSysCtl_SM_SPI2_SDOCntl_PU_EN 1
#define MSK32smSysCtl_SM_SPI2_SDOCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_SPI2_SDICntl 0x0C30
#define BA_smSysCtl_SM_SPI2_SDICntl_PD_EN 0x0C30
#define B16smSysCtl_SM_SPI2_SDICntl_PD_EN 0x0C30
#define LSb32smSysCtl_SM_SPI2_SDICntl_PD_EN 0
#define LSb16smSysCtl_SM_SPI2_SDICntl_PD_EN 0
#define bsmSysCtl_SM_SPI2_SDICntl_PD_EN 1
#define MSK32smSysCtl_SM_SPI2_SDICntl_PD_EN 0x00000001
#define BA_smSysCtl_SM_SPI2_SDICntl_PU_EN 0x0C30
#define B16smSysCtl_SM_SPI2_SDICntl_PU_EN 0x0C30
#define LSb32smSysCtl_SM_SPI2_SDICntl_PU_EN 1
#define LSb16smSysCtl_SM_SPI2_SDICntl_PU_EN 1
#define bsmSysCtl_SM_SPI2_SDICntl_PU_EN 1
#define MSK32smSysCtl_SM_SPI2_SDICntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_SPI2_SCLKCntl 0x0C34
#define BA_smSysCtl_SM_SPI2_SCLKCntl_PD_EN 0x0C34
#define B16smSysCtl_SM_SPI2_SCLKCntl_PD_EN 0x0C34
#define LSb32smSysCtl_SM_SPI2_SCLKCntl_PD_EN 0
#define LSb16smSysCtl_SM_SPI2_SCLKCntl_PD_EN 0
#define bsmSysCtl_SM_SPI2_SCLKCntl_PD_EN 1
#define MSK32smSysCtl_SM_SPI2_SCLKCntl_PD_EN 0x00000001
#define BA_smSysCtl_SM_SPI2_SCLKCntl_PU_EN 0x0C34
#define B16smSysCtl_SM_SPI2_SCLKCntl_PU_EN 0x0C34
#define LSb32smSysCtl_SM_SPI2_SCLKCntl_PU_EN 1
#define LSb16smSysCtl_SM_SPI2_SCLKCntl_PU_EN 1
#define bsmSysCtl_SM_SPI2_SCLKCntl_PU_EN 1
#define MSK32smSysCtl_SM_SPI2_SCLKCntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_FE_LED0Cntl 0x0C38
#define BA_smSysCtl_SM_FE_LED0Cntl_PD_EN 0x0C38
#define B16smSysCtl_SM_FE_LED0Cntl_PD_EN 0x0C38
#define LSb32smSysCtl_SM_FE_LED0Cntl_PD_EN 0
#define LSb16smSysCtl_SM_FE_LED0Cntl_PD_EN 0
#define bsmSysCtl_SM_FE_LED0Cntl_PD_EN 1
#define MSK32smSysCtl_SM_FE_LED0Cntl_PD_EN 0x00000001
#define BA_smSysCtl_SM_FE_LED0Cntl_PU_EN 0x0C38
#define B16smSysCtl_SM_FE_LED0Cntl_PU_EN 0x0C38
#define LSb32smSysCtl_SM_FE_LED0Cntl_PU_EN 1
#define LSb16smSysCtl_SM_FE_LED0Cntl_PU_EN 1
#define bsmSysCtl_SM_FE_LED0Cntl_PU_EN 1
#define MSK32smSysCtl_SM_FE_LED0Cntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_FE_LED1Cntl 0x0C3C
#define BA_smSysCtl_SM_FE_LED1Cntl_PD_EN 0x0C3C
#define B16smSysCtl_SM_FE_LED1Cntl_PD_EN 0x0C3C
#define LSb32smSysCtl_SM_FE_LED1Cntl_PD_EN 0
#define LSb16smSysCtl_SM_FE_LED1Cntl_PD_EN 0
#define bsmSysCtl_SM_FE_LED1Cntl_PD_EN 1
#define MSK32smSysCtl_SM_FE_LED1Cntl_PD_EN 0x00000001
#define BA_smSysCtl_SM_FE_LED1Cntl_PU_EN 0x0C3C
#define B16smSysCtl_SM_FE_LED1Cntl_PU_EN 0x0C3C
#define LSb32smSysCtl_SM_FE_LED1Cntl_PU_EN 1
#define LSb16smSysCtl_SM_FE_LED1Cntl_PU_EN 1
#define bsmSysCtl_SM_FE_LED1Cntl_PU_EN 1
#define MSK32smSysCtl_SM_FE_LED1Cntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
#define RA_smSysCtl_SM_FE_LED2Cntl 0x0C40
#define BA_smSysCtl_SM_FE_LED2Cntl_PD_EN 0x0C40
#define B16smSysCtl_SM_FE_LED2Cntl_PD_EN 0x0C40
#define LSb32smSysCtl_SM_FE_LED2Cntl_PD_EN 0
#define LSb16smSysCtl_SM_FE_LED2Cntl_PD_EN 0
#define bsmSysCtl_SM_FE_LED2Cntl_PD_EN 1
#define MSK32smSysCtl_SM_FE_LED2Cntl_PD_EN 0x00000001
#define BA_smSysCtl_SM_FE_LED2Cntl_PU_EN 0x0C40
#define B16smSysCtl_SM_FE_LED2Cntl_PU_EN 0x0C40
#define LSb32smSysCtl_SM_FE_LED2Cntl_PU_EN 1
#define LSb16smSysCtl_SM_FE_LED2Cntl_PU_EN 1
#define bsmSysCtl_SM_FE_LED2Cntl_PU_EN 1
#define MSK32smSysCtl_SM_FE_LED2Cntl_PU_EN 0x00000002
///////////////////////////////////////////////////////////
typedef struct SIE_smSysCtl {
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_ID_REV_ID(r32) _BFGET_(r32, 3, 0)
#define SET32smSysCtl_SM_ID_REV_ID(r32,v) _BFSET_(r32, 3, 0,v)
#define GET16smSysCtl_SM_ID_REV_ID(r16) _BFGET_(r16, 3, 0)
#define SET16smSysCtl_SM_ID_REV_ID(r16,v) _BFSET_(r16, 3, 0,v)
#define GET32smSysCtl_SM_ID_PART_ID(r32) _BFGET_(r32,19, 4)
#define SET32smSysCtl_SM_ID_PART_ID(r32,v) _BFSET_(r32,19, 4,v)
#define GET32smSysCtl_SM_ID_MFC_ID(r32) _BFGET_(r32,31,20)
#define SET32smSysCtl_SM_ID_MFC_ID(r32,v) _BFSET_(r32,31,20,v)
#define GET16smSysCtl_SM_ID_MFC_ID(r16) _BFGET_(r16,15, 4)
#define SET16smSysCtl_SM_ID_MFC_ID(r16,v) _BFSET_(r16,15, 4,v)
#define w32smSysCtl_SM_ID {\
UNSG32 uSM_ID_REV_ID : 4;\
UNSG32 uSM_ID_PART_ID : 16;\
UNSG32 uSM_ID_MFC_ID : 12;\
}
union { UNSG32 u32smSysCtl_SM_ID;
struct w32smSysCtl_SM_ID;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_CPU_CTRL_CPU_RST_GO(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_CPU_CTRL_CPU_RST_GO(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_CPU_CTRL_CPU_RST_GO(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_CPU_CTRL_CPU_RST_GO(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_SM_CPU_CTRL_CPU_VINITHI(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_SM_CPU_CTRL_CPU_VINITHI(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_SM_CPU_CTRL_CPU_VINITHI(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_SM_CPU_CTRL_CPU_VINITHI(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32smSysCtl_SM_CPU_CTRL_CPU_INITRAM(r32) _BFGET_(r32, 2, 2)
#define SET32smSysCtl_SM_CPU_CTRL_CPU_INITRAM(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16smSysCtl_SM_CPU_CTRL_CPU_INITRAM(r16) _BFGET_(r16, 2, 2)
#define SET16smSysCtl_SM_CPU_CTRL_CPU_INITRAM(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32smSysCtl_SM_CPU_CTRL_CPU_BIGEND(r32) _BFGET_(r32, 3, 3)
#define SET32smSysCtl_SM_CPU_CTRL_CPU_BIGEND(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16smSysCtl_SM_CPU_CTRL_CPU_BIGEND(r16) _BFGET_(r16, 3, 3)
#define SET16smSysCtl_SM_CPU_CTRL_CPU_BIGEND(r16,v) _BFSET_(r16, 3, 3,v)
#define w32smSysCtl_SM_CPU_CTRL {\
UNSG32 uSM_CPU_CTRL_CPU_RST_GO : 1;\
UNSG32 uSM_CPU_CTRL_CPU_VINITHI : 1;\
UNSG32 uSM_CPU_CTRL_CPU_INITRAM : 1;\
UNSG32 uSM_CPU_CTRL_CPU_BIGEND : 1;\
UNSG32 RSVDx4_b4 : 28;\
}
union { UNSG32 u32smSysCtl_SM_CPU_CTRL;
struct w32smSysCtl_SM_CPU_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_RST_CTRL_SOC_RST_GO(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_RST_CTRL_SOC_RST_GO(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_RST_CTRL_SOC_RST_GO(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_RST_CTRL_SOC_RST_GO(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_SM_RST_CTRL_APB_RST_GO(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_SM_RST_CTRL_APB_RST_GO(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_SM_RST_CTRL_APB_RST_GO(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_SM_RST_CTRL_APB_RST_GO(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32smSysCtl_SM_RST_CTRL_SXBAR_RST_GO(r32) _BFGET_(r32, 2, 2)
#define SET32smSysCtl_SM_RST_CTRL_SXBAR_RST_GO(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16smSysCtl_SM_RST_CTRL_SXBAR_RST_GO(r16) _BFGET_(r16, 2, 2)
#define SET16smSysCtl_SM_RST_CTRL_SXBAR_RST_GO(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32smSysCtl_SM_RST_CTRL_WOL_RST_GO(r32) _BFGET_(r32, 3, 3)
#define SET32smSysCtl_SM_RST_CTRL_WOL_RST_GO(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16smSysCtl_SM_RST_CTRL_WOL_RST_GO(r16) _BFGET_(r16, 3, 3)
#define SET16smSysCtl_SM_RST_CTRL_WOL_RST_GO(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32smSysCtl_SM_RST_CTRL_FEPHY_RST_GO(r32) _BFGET_(r32, 4, 4)
#define SET32smSysCtl_SM_RST_CTRL_FEPHY_RST_GO(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16smSysCtl_SM_RST_CTRL_FEPHY_RST_GO(r16) _BFGET_(r16, 4, 4)
#define SET16smSysCtl_SM_RST_CTRL_FEPHY_RST_GO(r16,v) _BFSET_(r16, 4, 4,v)
#define w32smSysCtl_SM_RST_CTRL {\
UNSG32 uSM_RST_CTRL_SOC_RST_GO : 1;\
UNSG32 uSM_RST_CTRL_APB_RST_GO : 1;\
UNSG32 uSM_RST_CTRL_SXBAR_RST_GO : 1;\
UNSG32 uSM_RST_CTRL_WOL_RST_GO : 1;\
UNSG32 uSM_RST_CTRL_FEPHY_RST_GO : 1;\
UNSG32 RSVDx8_b5 : 27;\
}
union { UNSG32 u32smSysCtl_SM_RST_CTRL;
struct w32smSysCtl_SM_RST_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_RST_STATUS_RST_WD_0(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_RST_STATUS_RST_WD_0(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_RST_STATUS_RST_WD_0(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_RST_STATUS_RST_WD_0(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_SM_RST_STATUS_RST_WD_1(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_SM_RST_STATUS_RST_WD_1(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_SM_RST_STATUS_RST_WD_1(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_SM_RST_STATUS_RST_WD_1(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32smSysCtl_SM_RST_STATUS_RST_WD_2(r32) _BFGET_(r32, 2, 2)
#define SET32smSysCtl_SM_RST_STATUS_RST_WD_2(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16smSysCtl_SM_RST_STATUS_RST_WD_2(r16) _BFGET_(r16, 2, 2)
#define SET16smSysCtl_SM_RST_STATUS_RST_WD_2(r16,v) _BFSET_(r16, 2, 2,v)
#define w32smSysCtl_SM_RST_STATUS {\
UNSG32 uSM_RST_STATUS_RST_WD_0 : 1;\
UNSG32 uSM_RST_STATUS_RST_WD_1 : 1;\
UNSG32 uSM_RST_STATUS_RST_WD_2 : 1;\
UNSG32 RSVDxC_b3 : 29;\
}
union { UNSG32 u32smSysCtl_SM_RST_STATUS;
struct w32smSysCtl_SM_RST_STATUS;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_STRP_STATUS_BOOT_MODE(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_STRP_STATUS_BOOT_MODE(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_STRP_STATUS_BOOT_MODE(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_STRP_STATUS_BOOT_MODE(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_SM_STRP_STATUS_STRP_1(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_SM_STRP_STATUS_STRP_1(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_SM_STRP_STATUS_STRP_1(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_SM_STRP_STATUS_STRP_1(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32smSysCtl_SM_STRP_STATUS_STRP_2(r32) _BFGET_(r32, 2, 2)
#define SET32smSysCtl_SM_STRP_STATUS_STRP_2(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16smSysCtl_SM_STRP_STATUS_STRP_2(r16) _BFGET_(r16, 2, 2)
#define SET16smSysCtl_SM_STRP_STATUS_STRP_2(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32smSysCtl_SM_STRP_STATUS_STRP_3(r32) _BFGET_(r32, 3, 3)
#define SET32smSysCtl_SM_STRP_STATUS_STRP_3(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16smSysCtl_SM_STRP_STATUS_STRP_3(r16) _BFGET_(r16, 3, 3)
#define SET16smSysCtl_SM_STRP_STATUS_STRP_3(r16,v) _BFSET_(r16, 3, 3,v)
#define w32smSysCtl_SM_STRP_STATUS {\
UNSG32 uSM_STRP_STATUS_BOOT_MODE : 1;\
UNSG32 uSM_STRP_STATUS_STRP_1 : 1;\
UNSG32 uSM_STRP_STATUS_STRP_2 : 1;\
UNSG32 uSM_STRP_STATUS_STRP_3 : 1;\
UNSG32 RSVDx10_b4 : 28;\
}
union { UNSG32 u32smSysCtl_SM_STRP_STATUS;
struct w32smSysCtl_SM_STRP_STATUS;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_CTRL_ISO_EN(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_CTRL_ISO_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_CTRL_ISO_EN(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_CTRL_ISO_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_SM_CTRL_SM2SOC_SW_INTR(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_SM_CTRL_SM2SOC_SW_INTR(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_SM_CTRL_SM2SOC_SW_INTR(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_SM_CTRL_SM2SOC_SW_INTR(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32smSysCtl_SM_CTRL_SOC2SM_SW_INTR(r32) _BFGET_(r32, 2, 2)
#define SET32smSysCtl_SM_CTRL_SOC2SM_SW_INTR(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16smSysCtl_SM_CTRL_SOC2SM_SW_INTR(r16) _BFGET_(r16, 2, 2)
#define SET16smSysCtl_SM_CTRL_SOC2SM_SW_INTR(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32smSysCtl_SM_CTRL_REV_0(r32) _BFGET_(r32, 4, 3)
#define SET32smSysCtl_SM_CTRL_REV_0(r32,v) _BFSET_(r32, 4, 3,v)
#define GET16smSysCtl_SM_CTRL_REV_0(r16) _BFGET_(r16, 4, 3)
#define SET16smSysCtl_SM_CTRL_REV_0(r16,v) _BFSET_(r16, 4, 3,v)
#define GET32smSysCtl_SM_CTRL_ADC_SEL(r32) _BFGET_(r32, 8, 5)
#define SET32smSysCtl_SM_CTRL_ADC_SEL(r32,v) _BFSET_(r32, 8, 5,v)
#define GET16smSysCtl_SM_CTRL_ADC_SEL(r16) _BFGET_(r16, 8, 5)
#define SET16smSysCtl_SM_CTRL_ADC_SEL(r16,v) _BFSET_(r16, 8, 5,v)
#define GET32smSysCtl_SM_CTRL_ADC_PU(r32) _BFGET_(r32, 9, 9)
#define SET32smSysCtl_SM_CTRL_ADC_PU(r32,v) _BFSET_(r32, 9, 9,v)
#define GET16smSysCtl_SM_CTRL_ADC_PU(r16) _BFGET_(r16, 9, 9)
#define SET16smSysCtl_SM_CTRL_ADC_PU(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32smSysCtl_SM_CTRL_ADC_CKSEL(r32) _BFGET_(r32,11,10)
#define SET32smSysCtl_SM_CTRL_ADC_CKSEL(r32,v) _BFSET_(r32,11,10,v)
#define GET16smSysCtl_SM_CTRL_ADC_CKSEL(r16) _BFGET_(r16,11,10)
#define SET16smSysCtl_SM_CTRL_ADC_CKSEL(r16,v) _BFSET_(r16,11,10,v)
#define GET32smSysCtl_SM_CTRL_ADC_START(r32) _BFGET_(r32,12,12)
#define SET32smSysCtl_SM_CTRL_ADC_START(r32,v) _BFSET_(r32,12,12,v)
#define GET16smSysCtl_SM_CTRL_ADC_START(r16) _BFGET_(r16,12,12)
#define SET16smSysCtl_SM_CTRL_ADC_START(r16,v) _BFSET_(r16,12,12,v)
#define GET32smSysCtl_SM_CTRL_ADC_RESET(r32) _BFGET_(r32,13,13)
#define SET32smSysCtl_SM_CTRL_ADC_RESET(r32,v) _BFSET_(r32,13,13,v)
#define GET16smSysCtl_SM_CTRL_ADC_RESET(r16) _BFGET_(r16,13,13)
#define SET16smSysCtl_SM_CTRL_ADC_RESET(r16,v) _BFSET_(r16,13,13,v)
#define GET32smSysCtl_SM_CTRL_ADC_BG_RDY(r32) _BFGET_(r32,14,14)
#define SET32smSysCtl_SM_CTRL_ADC_BG_RDY(r32,v) _BFSET_(r32,14,14,v)
#define GET16smSysCtl_SM_CTRL_ADC_BG_RDY(r16) _BFGET_(r16,14,14)
#define SET16smSysCtl_SM_CTRL_ADC_BG_RDY(r16,v) _BFSET_(r16,14,14,v)
#define GET32smSysCtl_SM_CTRL_ADC_CONT(r32) _BFGET_(r32,15,15)
#define SET32smSysCtl_SM_CTRL_ADC_CONT(r32,v) _BFSET_(r32,15,15,v)
#define GET16smSysCtl_SM_CTRL_ADC_CONT(r16) _BFGET_(r16,15,15)
#define SET16smSysCtl_SM_CTRL_ADC_CONT(r16,v) _BFSET_(r16,15,15,v)
#define GET32smSysCtl_SM_CTRL_ADC_BUF_EN(r32) _BFGET_(r32,16,16)
#define SET32smSysCtl_SM_CTRL_ADC_BUF_EN(r32,v) _BFSET_(r32,16,16,v)
#define GET16smSysCtl_SM_CTRL_ADC_BUF_EN(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_CTRL_ADC_BUF_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_SM_CTRL_ADC_VREF_SEL(r32) _BFGET_(r32,17,17)
#define SET32smSysCtl_SM_CTRL_ADC_VREF_SEL(r32,v) _BFSET_(r32,17,17,v)
#define GET16smSysCtl_SM_CTRL_ADC_VREF_SEL(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_SM_CTRL_ADC_VREF_SEL(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32smSysCtl_SM_CTRL_ADC_ROTATE_SEL(r32) _BFGET_(r32,18,18)
#define SET32smSysCtl_SM_CTRL_ADC_ROTATE_SEL(r32,v) _BFSET_(r32,18,18,v)
#define GET16smSysCtl_SM_CTRL_ADC_ROTATE_SEL(r16) _BFGET_(r16, 2, 2)
#define SET16smSysCtl_SM_CTRL_ADC_ROTATE_SEL(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32smSysCtl_SM_CTRL_TSEN_EN(r32) _BFGET_(r32,19,19)
#define SET32smSysCtl_SM_CTRL_TSEN_EN(r32,v) _BFSET_(r32,19,19,v)
#define GET16smSysCtl_SM_CTRL_TSEN_EN(r16) _BFGET_(r16, 3, 3)
#define SET16smSysCtl_SM_CTRL_TSEN_EN(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32smSysCtl_SM_CTRL_TSEN_CLK_EN(r32) _BFGET_(r32,20,20)
#define SET32smSysCtl_SM_CTRL_TSEN_CLK_EN(r32,v) _BFSET_(r32,20,20,v)
#define GET16smSysCtl_SM_CTRL_TSEN_CLK_EN(r16) _BFGET_(r16, 4, 4)
#define SET16smSysCtl_SM_CTRL_TSEN_CLK_EN(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32smSysCtl_SM_CTRL_TSEN_CLK_SEL(r32) _BFGET_(r32,21,21)
#define SET32smSysCtl_SM_CTRL_TSEN_CLK_SEL(r32,v) _BFSET_(r32,21,21,v)
#define GET16smSysCtl_SM_CTRL_TSEN_CLK_SEL(r16) _BFGET_(r16, 5, 5)
#define SET16smSysCtl_SM_CTRL_TSEN_CLK_SEL(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32smSysCtl_SM_CTRL_TSEN_MODE_SEL(r32) _BFGET_(r32,22,22)
#define SET32smSysCtl_SM_CTRL_TSEN_MODE_SEL(r32,v) _BFSET_(r32,22,22,v)
#define GET16smSysCtl_SM_CTRL_TSEN_MODE_SEL(r16) _BFGET_(r16, 6, 6)
#define SET16smSysCtl_SM_CTRL_TSEN_MODE_SEL(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32smSysCtl_SM_CTRL_TSEN_ADC_CAL(r32) _BFGET_(r32,24,23)
#define SET32smSysCtl_SM_CTRL_TSEN_ADC_CAL(r32,v) _BFSET_(r32,24,23,v)
#define GET16smSysCtl_SM_CTRL_TSEN_ADC_CAL(r16) _BFGET_(r16, 8, 7)
#define SET16smSysCtl_SM_CTRL_TSEN_ADC_CAL(r16,v) _BFSET_(r16, 8, 7,v)
#define GET32smSysCtl_SM_CTRL_TSEN_ADC_TST_SEL(r32) _BFGET_(r32,29,25)
#define SET32smSysCtl_SM_CTRL_TSEN_ADC_TST_SEL(r32,v) _BFSET_(r32,29,25,v)
#define GET16smSysCtl_SM_CTRL_TSEN_ADC_TST_SEL(r16) _BFGET_(r16,13, 9)
#define SET16smSysCtl_SM_CTRL_TSEN_ADC_TST_SEL(r16,v) _BFSET_(r16,13, 9,v)
#define GET32smSysCtl_SM_CTRL_TSEN_RESET(r32) _BFGET_(r32,30,30)
#define SET32smSysCtl_SM_CTRL_TSEN_RESET(r32,v) _BFSET_(r32,30,30,v)
#define GET16smSysCtl_SM_CTRL_TSEN_RESET(r16) _BFGET_(r16,14,14)
#define SET16smSysCtl_SM_CTRL_TSEN_RESET(r16,v) _BFSET_(r16,14,14,v)
#define GET32smSysCtl_SM_CTRL_TSEN_ADC_ISO_EN(r32) _BFGET_(r32,31,31)
#define SET32smSysCtl_SM_CTRL_TSEN_ADC_ISO_EN(r32,v) _BFSET_(r32,31,31,v)
#define GET16smSysCtl_SM_CTRL_TSEN_ADC_ISO_EN(r16) _BFGET_(r16,15,15)
#define SET16smSysCtl_SM_CTRL_TSEN_ADC_ISO_EN(r16,v) _BFSET_(r16,15,15,v)
#define w32smSysCtl_SM_CTRL {\
UNSG32 uSM_CTRL_ISO_EN : 1;\
UNSG32 uSM_CTRL_SM2SOC_SW_INTR : 1;\
UNSG32 uSM_CTRL_SOC2SM_SW_INTR : 1;\
UNSG32 uSM_CTRL_REV_0 : 2;\
UNSG32 uSM_CTRL_ADC_SEL : 4;\
UNSG32 uSM_CTRL_ADC_PU : 1;\
UNSG32 uSM_CTRL_ADC_CKSEL : 2;\
UNSG32 uSM_CTRL_ADC_START : 1;\
UNSG32 uSM_CTRL_ADC_RESET : 1;\
UNSG32 uSM_CTRL_ADC_BG_RDY : 1;\
UNSG32 uSM_CTRL_ADC_CONT : 1;\
UNSG32 uSM_CTRL_ADC_BUF_EN : 1;\
UNSG32 uSM_CTRL_ADC_VREF_SEL : 1;\
UNSG32 uSM_CTRL_ADC_ROTATE_SEL : 1;\
UNSG32 uSM_CTRL_TSEN_EN : 1;\
UNSG32 uSM_CTRL_TSEN_CLK_EN : 1;\
UNSG32 uSM_CTRL_TSEN_CLK_SEL : 1;\
UNSG32 uSM_CTRL_TSEN_MODE_SEL : 1;\
UNSG32 uSM_CTRL_TSEN_ADC_CAL : 2;\
UNSG32 uSM_CTRL_TSEN_ADC_TST_SEL : 5;\
UNSG32 uSM_CTRL_TSEN_RESET : 1;\
UNSG32 uSM_CTRL_TSEN_ADC_ISO_EN : 1;\
}
union { UNSG32 u32smSysCtl_SM_CTRL;
struct w32smSysCtl_SM_CTRL;
};
#define GET32smSysCtl_SM_CTRL_EDID_INTR_CLR(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_CTRL_EDID_INTR_CLR(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_CTRL_EDID_INTR_CLR(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_CTRL_EDID_INTR_CLR(r16,v) _BFSET_(r16, 0, 0,v)
#define w32smSysCtl_SM_CTRL1 {\
UNSG32 uSM_CTRL_EDID_INTR_CLR : 1;\
UNSG32 RSVDx18_b1 : 31;\
}
union { UNSG32 u32smSysCtl_SM_CTRL1;
struct w32smSysCtl_SM_CTRL1;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_ADC_CTRL_TSEN_DAT_LT(r32) _BFGET_(r32, 4, 0)
#define SET32smSysCtl_SM_ADC_CTRL_TSEN_DAT_LT(r32,v) _BFSET_(r32, 4, 0,v)
#define GET16smSysCtl_SM_ADC_CTRL_TSEN_DAT_LT(r16) _BFGET_(r16, 4, 0)
#define SET16smSysCtl_SM_ADC_CTRL_TSEN_DAT_LT(r16,v) _BFSET_(r16, 4, 0,v)
#define GET32smSysCtl_SM_ADC_CTRL_ADC_DAT_LT(r32) _BFGET_(r32, 9, 5)
#define SET32smSysCtl_SM_ADC_CTRL_ADC_DAT_LT(r32,v) _BFSET_(r32, 9, 5,v)
#define GET16smSysCtl_SM_ADC_CTRL_ADC_DAT_LT(r16) _BFGET_(r16, 9, 5)
#define SET16smSysCtl_SM_ADC_CTRL_ADC_DAT_LT(r16,v) _BFSET_(r16, 9, 5,v)
#define w32smSysCtl_SM_ADC_CTRL {\
UNSG32 uSM_ADC_CTRL_TSEN_DAT_LT : 5;\
UNSG32 uSM_ADC_CTRL_ADC_DAT_LT : 5;\
UNSG32 RSVDx1C_b10 : 22;\
}
union { UNSG32 u32smSysCtl_SM_ADC_CTRL;
struct w32smSysCtl_SM_ADC_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_ADC_STATUS_CH0_DATA_RDY(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_ADC_STATUS_CH0_DATA_RDY(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH0_DATA_RDY(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_ADC_STATUS_CH0_DATA_RDY(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH1_DATA_RDY(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_SM_ADC_STATUS_CH1_DATA_RDY(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH1_DATA_RDY(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_SM_ADC_STATUS_CH1_DATA_RDY(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH2_DATA_RDY(r32) _BFGET_(r32, 2, 2)
#define SET32smSysCtl_SM_ADC_STATUS_CH2_DATA_RDY(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH2_DATA_RDY(r16) _BFGET_(r16, 2, 2)
#define SET16smSysCtl_SM_ADC_STATUS_CH2_DATA_RDY(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH3_DATA_RDY(r32) _BFGET_(r32, 3, 3)
#define SET32smSysCtl_SM_ADC_STATUS_CH3_DATA_RDY(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH3_DATA_RDY(r16) _BFGET_(r16, 3, 3)
#define SET16smSysCtl_SM_ADC_STATUS_CH3_DATA_RDY(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH4_DATA_RDY(r32) _BFGET_(r32, 4, 4)
#define SET32smSysCtl_SM_ADC_STATUS_CH4_DATA_RDY(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH4_DATA_RDY(r16) _BFGET_(r16, 4, 4)
#define SET16smSysCtl_SM_ADC_STATUS_CH4_DATA_RDY(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH5_DATA_RDY(r32) _BFGET_(r32, 5, 5)
#define SET32smSysCtl_SM_ADC_STATUS_CH5_DATA_RDY(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH5_DATA_RDY(r16) _BFGET_(r16, 5, 5)
#define SET16smSysCtl_SM_ADC_STATUS_CH5_DATA_RDY(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH6_DATA_RDY(r32) _BFGET_(r32, 6, 6)
#define SET32smSysCtl_SM_ADC_STATUS_CH6_DATA_RDY(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH6_DATA_RDY(r16) _BFGET_(r16, 6, 6)
#define SET16smSysCtl_SM_ADC_STATUS_CH6_DATA_RDY(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH7_DATA_RDY(r32) _BFGET_(r32, 7, 7)
#define SET32smSysCtl_SM_ADC_STATUS_CH7_DATA_RDY(r32,v) _BFSET_(r32, 7, 7,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH7_DATA_RDY(r16) _BFGET_(r16, 7, 7)
#define SET16smSysCtl_SM_ADC_STATUS_CH7_DATA_RDY(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH8_DATA_RDY(r32) _BFGET_(r32, 8, 8)
#define SET32smSysCtl_SM_ADC_STATUS_CH8_DATA_RDY(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH8_DATA_RDY(r16) _BFGET_(r16, 8, 8)
#define SET16smSysCtl_SM_ADC_STATUS_CH8_DATA_RDY(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH9_DATA_RDY(r32) _BFGET_(r32, 9, 9)
#define SET32smSysCtl_SM_ADC_STATUS_CH9_DATA_RDY(r32,v) _BFSET_(r32, 9, 9,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH9_DATA_RDY(r16) _BFGET_(r16, 9, 9)
#define SET16smSysCtl_SM_ADC_STATUS_CH9_DATA_RDY(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH10_DATA_RDY(r32) _BFGET_(r32,10,10)
#define SET32smSysCtl_SM_ADC_STATUS_CH10_DATA_RDY(r32,v) _BFSET_(r32,10,10,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH10_DATA_RDY(r16) _BFGET_(r16,10,10)
#define SET16smSysCtl_SM_ADC_STATUS_CH10_DATA_RDY(r16,v) _BFSET_(r16,10,10,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH11_DATA_RDY(r32) _BFGET_(r32,11,11)
#define SET32smSysCtl_SM_ADC_STATUS_CH11_DATA_RDY(r32,v) _BFSET_(r32,11,11,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH11_DATA_RDY(r16) _BFGET_(r16,11,11)
#define SET16smSysCtl_SM_ADC_STATUS_CH11_DATA_RDY(r16,v) _BFSET_(r16,11,11,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH12_DATA_RDY(r32) _BFGET_(r32,12,12)
#define SET32smSysCtl_SM_ADC_STATUS_CH12_DATA_RDY(r32,v) _BFSET_(r32,12,12,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH12_DATA_RDY(r16) _BFGET_(r16,12,12)
#define SET16smSysCtl_SM_ADC_STATUS_CH12_DATA_RDY(r16,v) _BFSET_(r16,12,12,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH13_DATA_RDY(r32) _BFGET_(r32,13,13)
#define SET32smSysCtl_SM_ADC_STATUS_CH13_DATA_RDY(r32,v) _BFSET_(r32,13,13,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH13_DATA_RDY(r16) _BFGET_(r16,13,13)
#define SET16smSysCtl_SM_ADC_STATUS_CH13_DATA_RDY(r16,v) _BFSET_(r16,13,13,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH14_DATA_RDY(r32) _BFGET_(r32,14,14)
#define SET32smSysCtl_SM_ADC_STATUS_CH14_DATA_RDY(r32,v) _BFSET_(r32,14,14,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH14_DATA_RDY(r16) _BFGET_(r16,14,14)
#define SET16smSysCtl_SM_ADC_STATUS_CH14_DATA_RDY(r16,v) _BFSET_(r16,14,14,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH15_DATA_RDY(r32) _BFGET_(r32,15,15)
#define SET32smSysCtl_SM_ADC_STATUS_CH15_DATA_RDY(r32,v) _BFSET_(r32,15,15,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH15_DATA_RDY(r16) _BFGET_(r16,15,15)
#define SET16smSysCtl_SM_ADC_STATUS_CH15_DATA_RDY(r16,v) _BFSET_(r16,15,15,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH0_INT_EN(r32) _BFGET_(r32,16,16)
#define SET32smSysCtl_SM_ADC_STATUS_CH0_INT_EN(r32,v) _BFSET_(r32,16,16,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH0_INT_EN(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_ADC_STATUS_CH0_INT_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH1_INT_EN(r32) _BFGET_(r32,17,17)
#define SET32smSysCtl_SM_ADC_STATUS_CH1_INT_EN(r32,v) _BFSET_(r32,17,17,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH1_INT_EN(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_SM_ADC_STATUS_CH1_INT_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH2_INT_EN(r32) _BFGET_(r32,18,18)
#define SET32smSysCtl_SM_ADC_STATUS_CH2_INT_EN(r32,v) _BFSET_(r32,18,18,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH2_INT_EN(r16) _BFGET_(r16, 2, 2)
#define SET16smSysCtl_SM_ADC_STATUS_CH2_INT_EN(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH3_INT_EN(r32) _BFGET_(r32,19,19)
#define SET32smSysCtl_SM_ADC_STATUS_CH3_INT_EN(r32,v) _BFSET_(r32,19,19,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH3_INT_EN(r16) _BFGET_(r16, 3, 3)
#define SET16smSysCtl_SM_ADC_STATUS_CH3_INT_EN(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH4_INT_EN(r32) _BFGET_(r32,20,20)
#define SET32smSysCtl_SM_ADC_STATUS_CH4_INT_EN(r32,v) _BFSET_(r32,20,20,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH4_INT_EN(r16) _BFGET_(r16, 4, 4)
#define SET16smSysCtl_SM_ADC_STATUS_CH4_INT_EN(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH5_INT_EN(r32) _BFGET_(r32,21,21)
#define SET32smSysCtl_SM_ADC_STATUS_CH5_INT_EN(r32,v) _BFSET_(r32,21,21,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH5_INT_EN(r16) _BFGET_(r16, 5, 5)
#define SET16smSysCtl_SM_ADC_STATUS_CH5_INT_EN(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH6_INT_EN(r32) _BFGET_(r32,22,22)
#define SET32smSysCtl_SM_ADC_STATUS_CH6_INT_EN(r32,v) _BFSET_(r32,22,22,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH6_INT_EN(r16) _BFGET_(r16, 6, 6)
#define SET16smSysCtl_SM_ADC_STATUS_CH6_INT_EN(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH7_INT_EN(r32) _BFGET_(r32,23,23)
#define SET32smSysCtl_SM_ADC_STATUS_CH7_INT_EN(r32,v) _BFSET_(r32,23,23,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH7_INT_EN(r16) _BFGET_(r16, 7, 7)
#define SET16smSysCtl_SM_ADC_STATUS_CH7_INT_EN(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH8_INT_EN(r32) _BFGET_(r32,24,24)
#define SET32smSysCtl_SM_ADC_STATUS_CH8_INT_EN(r32,v) _BFSET_(r32,24,24,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH8_INT_EN(r16) _BFGET_(r16, 8, 8)
#define SET16smSysCtl_SM_ADC_STATUS_CH8_INT_EN(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH9_INT_EN(r32) _BFGET_(r32,25,25)
#define SET32smSysCtl_SM_ADC_STATUS_CH9_INT_EN(r32,v) _BFSET_(r32,25,25,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH9_INT_EN(r16) _BFGET_(r16, 9, 9)
#define SET16smSysCtl_SM_ADC_STATUS_CH9_INT_EN(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH10_INT_EN(r32) _BFGET_(r32,26,26)
#define SET32smSysCtl_SM_ADC_STATUS_CH10_INT_EN(r32,v) _BFSET_(r32,26,26,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH10_INT_EN(r16) _BFGET_(r16,10,10)
#define SET16smSysCtl_SM_ADC_STATUS_CH10_INT_EN(r16,v) _BFSET_(r16,10,10,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH11_INT_EN(r32) _BFGET_(r32,27,27)
#define SET32smSysCtl_SM_ADC_STATUS_CH11_INT_EN(r32,v) _BFSET_(r32,27,27,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH11_INT_EN(r16) _BFGET_(r16,11,11)
#define SET16smSysCtl_SM_ADC_STATUS_CH11_INT_EN(r16,v) _BFSET_(r16,11,11,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH12_INT_EN(r32) _BFGET_(r32,28,28)
#define SET32smSysCtl_SM_ADC_STATUS_CH12_INT_EN(r32,v) _BFSET_(r32,28,28,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH12_INT_EN(r16) _BFGET_(r16,12,12)
#define SET16smSysCtl_SM_ADC_STATUS_CH12_INT_EN(r16,v) _BFSET_(r16,12,12,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH13_INT_EN(r32) _BFGET_(r32,29,29)
#define SET32smSysCtl_SM_ADC_STATUS_CH13_INT_EN(r32,v) _BFSET_(r32,29,29,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH13_INT_EN(r16) _BFGET_(r16,13,13)
#define SET16smSysCtl_SM_ADC_STATUS_CH13_INT_EN(r16,v) _BFSET_(r16,13,13,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH14_INT_EN(r32) _BFGET_(r32,30,30)
#define SET32smSysCtl_SM_ADC_STATUS_CH14_INT_EN(r32,v) _BFSET_(r32,30,30,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH14_INT_EN(r16) _BFGET_(r16,14,14)
#define SET16smSysCtl_SM_ADC_STATUS_CH14_INT_EN(r16,v) _BFSET_(r16,14,14,v)
#define GET32smSysCtl_SM_ADC_STATUS_CH15_INT_EN(r32) _BFGET_(r32,31,31)
#define SET32smSysCtl_SM_ADC_STATUS_CH15_INT_EN(r32,v) _BFSET_(r32,31,31,v)
#define GET16smSysCtl_SM_ADC_STATUS_CH15_INT_EN(r16) _BFGET_(r16,15,15)
#define SET16smSysCtl_SM_ADC_STATUS_CH15_INT_EN(r16,v) _BFSET_(r16,15,15,v)
#define w32smSysCtl_SM_ADC_STATUS {\
UNSG32 uSM_ADC_STATUS_CH0_DATA_RDY : 1;\
UNSG32 uSM_ADC_STATUS_CH1_DATA_RDY : 1;\
UNSG32 uSM_ADC_STATUS_CH2_DATA_RDY : 1;\
UNSG32 uSM_ADC_STATUS_CH3_DATA_RDY : 1;\
UNSG32 uSM_ADC_STATUS_CH4_DATA_RDY : 1;\
UNSG32 uSM_ADC_STATUS_CH5_DATA_RDY : 1;\
UNSG32 uSM_ADC_STATUS_CH6_DATA_RDY : 1;\
UNSG32 uSM_ADC_STATUS_CH7_DATA_RDY : 1;\
UNSG32 uSM_ADC_STATUS_CH8_DATA_RDY : 1;\
UNSG32 uSM_ADC_STATUS_CH9_DATA_RDY : 1;\
UNSG32 uSM_ADC_STATUS_CH10_DATA_RDY : 1;\
UNSG32 uSM_ADC_STATUS_CH11_DATA_RDY : 1;\
UNSG32 uSM_ADC_STATUS_CH12_DATA_RDY : 1;\
UNSG32 uSM_ADC_STATUS_CH13_DATA_RDY : 1;\
UNSG32 uSM_ADC_STATUS_CH14_DATA_RDY : 1;\
UNSG32 uSM_ADC_STATUS_CH15_DATA_RDY : 1;\
UNSG32 uSM_ADC_STATUS_CH0_INT_EN : 1;\
UNSG32 uSM_ADC_STATUS_CH1_INT_EN : 1;\
UNSG32 uSM_ADC_STATUS_CH2_INT_EN : 1;\
UNSG32 uSM_ADC_STATUS_CH3_INT_EN : 1;\
UNSG32 uSM_ADC_STATUS_CH4_INT_EN : 1;\
UNSG32 uSM_ADC_STATUS_CH5_INT_EN : 1;\
UNSG32 uSM_ADC_STATUS_CH6_INT_EN : 1;\
UNSG32 uSM_ADC_STATUS_CH7_INT_EN : 1;\
UNSG32 uSM_ADC_STATUS_CH8_INT_EN : 1;\
UNSG32 uSM_ADC_STATUS_CH9_INT_EN : 1;\
UNSG32 uSM_ADC_STATUS_CH10_INT_EN : 1;\
UNSG32 uSM_ADC_STATUS_CH11_INT_EN : 1;\
UNSG32 uSM_ADC_STATUS_CH12_INT_EN : 1;\
UNSG32 uSM_ADC_STATUS_CH13_INT_EN : 1;\
UNSG32 uSM_ADC_STATUS_CH14_INT_EN : 1;\
UNSG32 uSM_ADC_STATUS_CH15_INT_EN : 1;\
}
union { UNSG32 u32smSysCtl_SM_ADC_STATUS;
struct w32smSysCtl_SM_ADC_STATUS;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_ADC_DATA_ADC_DATA(r32) _BFGET_(r32, 9, 0)
#define SET32smSysCtl_SM_ADC_DATA_ADC_DATA(r32,v) _BFSET_(r32, 9, 0,v)
#define GET16smSysCtl_SM_ADC_DATA_ADC_DATA(r16) _BFGET_(r16, 9, 0)
#define SET16smSysCtl_SM_ADC_DATA_ADC_DATA(r16,v) _BFSET_(r16, 9, 0,v)
#define w32smSysCtl_SM_ADC_DATA {\
UNSG32 uSM_ADC_DATA_ADC_DATA : 10;\
UNSG32 RSVDx24_b10 : 22;\
}
union { UNSG32 u32smSysCtl_SM_ADC_DATA;
struct w32smSysCtl_SM_ADC_DATA;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_TSEN_ADC_STATUS_DATA_RDY(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_TSEN_ADC_STATUS_DATA_RDY(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_TSEN_ADC_STATUS_DATA_RDY(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_TSEN_ADC_STATUS_DATA_RDY(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_TSEN_ADC_STATUS_INT_EN(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_TSEN_ADC_STATUS_INT_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_TSEN_ADC_STATUS_INT_EN(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_TSEN_ADC_STATUS_INT_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32smSysCtl_TSEN_ADC_STATUS {\
UNSG32 uTSEN_ADC_STATUS_DATA_RDY : 1;\
UNSG32 uTSEN_ADC_STATUS_INT_EN : 1;\
UNSG32 RSVDx28_b2 : 30;\
}
union { UNSG32 u32smSysCtl_TSEN_ADC_STATUS;
struct w32smSysCtl_TSEN_ADC_STATUS;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_TSEN_ADC_DATA_ADC_DATA(r32) _BFGET_(r32,11, 0)
#define SET32smSysCtl_TSEN_ADC_DATA_ADC_DATA(r32,v) _BFSET_(r32,11, 0,v)
#define GET16smSysCtl_TSEN_ADC_DATA_ADC_DATA(r16) _BFGET_(r16,11, 0)
#define SET16smSysCtl_TSEN_ADC_DATA_ADC_DATA(r16,v) _BFSET_(r16,11, 0,v)
#define w32smSysCtl_TSEN_ADC_DATA {\
UNSG32 uTSEN_ADC_DATA_ADC_DATA : 12;\
UNSG32 RSVDx2C_b12 : 20;\
}
union { UNSG32 u32smSysCtl_TSEN_ADC_DATA;
struct w32smSysCtl_TSEN_ADC_DATA;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MAX(r32) _BFGET_(r32,11, 0)
#define SET32smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MAX(r32,v) _BFSET_(r32,11, 0,v)
#define GET16smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MAX(r16) _BFGET_(r16,11, 0)
#define SET16smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MAX(r16,v) _BFSET_(r16,11, 0,v)
#define GET32smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MIN(r32) _BFGET_(r32,23,12)
#define SET32smSysCtl_TSEN_CHK_CTRL_TSEN_DATA_MIN(r32,v) _BFSET_(r32,23,12,v)
#define GET32smSysCtl_TSEN_CHK_CTRL_TSEN_OVERHEAT_SEL(r32) _BFGET_(r32,24,24)
#define SET32smSysCtl_TSEN_CHK_CTRL_TSEN_OVERHEAT_SEL(r32,v) _BFSET_(r32,24,24,v)
#define GET16smSysCtl_TSEN_CHK_CTRL_TSEN_OVERHEAT_SEL(r16) _BFGET_(r16, 8, 8)
#define SET16smSysCtl_TSEN_CHK_CTRL_TSEN_OVERHEAT_SEL(r16,v) _BFSET_(r16, 8, 8,v)
#define w32smSysCtl_TSEN_CHK_CTRL {\
UNSG32 uTSEN_CHK_CTRL_TSEN_DATA_MAX : 12;\
UNSG32 uTSEN_CHK_CTRL_TSEN_DATA_MIN : 12;\
UNSG32 uTSEN_CHK_CTRL_TSEN_OVERHEAT_SEL : 1;\
UNSG32 RSVDx30_b25 : 7;\
}
union { UNSG32 u32smSysCtl_TSEN_CHK_CTRL;
struct w32smSysCtl_TSEN_CHK_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_TSEN_DATA_STATUS_TSEN_MAX_FAIL(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_TSEN_DATA_STATUS_TSEN_MAX_FAIL(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_TSEN_DATA_STATUS_TSEN_MAX_FAIL(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_TSEN_DATA_STATUS_TSEN_MAX_FAIL(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_TSEN_DATA_STATUS_TSEN_MIN_FAIL(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_TSEN_DATA_STATUS_TSEN_MIN_FAIL(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_TSEN_DATA_STATUS_TSEN_MIN_FAIL(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_TSEN_DATA_STATUS_TSEN_MIN_FAIL(r16,v) _BFSET_(r16, 1, 1,v)
#define w32smSysCtl_TSEN_DATA_STATUS {\
UNSG32 uTSEN_DATA_STATUS_TSEN_MAX_FAIL : 1;\
UNSG32 uTSEN_DATA_STATUS_TSEN_MIN_FAIL : 1;\
UNSG32 RSVDx34_b2 : 30;\
}
union { UNSG32 u32smSysCtl_TSEN_DATA_STATUS;
struct w32smSysCtl_TSEN_DATA_STATUS;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_BOOT_STATUS_MODE(r32) _BFGET_(r32,31, 0)
#define SET32smSysCtl_SM_BOOT_STATUS_MODE(r32,v) _BFSET_(r32,31, 0,v)
#define w32smSysCtl_SM_BOOT_STATUS {\
UNSG32 uSM_BOOT_STATUS_MODE : 32;\
}
union { UNSG32 u32smSysCtl_SM_BOOT_STATUS;
struct w32smSysCtl_SM_BOOT_STATUS;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_LDO_CTRL_TEST_SEL(r32) _BFGET_(r32, 2, 0)
#define SET32smSysCtl_SM_LDO_CTRL_TEST_SEL(r32,v) _BFSET_(r32, 2, 0,v)
#define GET16smSysCtl_SM_LDO_CTRL_TEST_SEL(r16) _BFGET_(r16, 2, 0)
#define SET16smSysCtl_SM_LDO_CTRL_TEST_SEL(r16,v) _BFSET_(r16, 2, 0,v)
#define GET32smSysCtl_SM_LDO_CTRL_VOUT_SEL(r32) _BFGET_(r32, 5, 3)
#define SET32smSysCtl_SM_LDO_CTRL_VOUT_SEL(r32,v) _BFSET_(r32, 5, 3,v)
#define GET16smSysCtl_SM_LDO_CTRL_VOUT_SEL(r16) _BFGET_(r16, 5, 3)
#define SET16smSysCtl_SM_LDO_CTRL_VOUT_SEL(r16,v) _BFSET_(r16, 5, 3,v)
#define GET32smSysCtl_SM_LDO_CTRL_TEST_EN(r32) _BFGET_(r32, 6, 6)
#define SET32smSysCtl_SM_LDO_CTRL_TEST_EN(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16smSysCtl_SM_LDO_CTRL_TEST_EN(r16) _BFGET_(r16, 6, 6)
#define SET16smSysCtl_SM_LDO_CTRL_TEST_EN(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32smSysCtl_SM_LDO_CTRL_LDO_RDY(r32) _BFGET_(r32, 7, 7)
#define SET32smSysCtl_SM_LDO_CTRL_LDO_RDY(r32,v) _BFSET_(r32, 7, 7,v)
#define GET16smSysCtl_SM_LDO_CTRL_LDO_RDY(r16) _BFGET_(r16, 7, 7)
#define SET16smSysCtl_SM_LDO_CTRL_LDO_RDY(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32smSysCtl_SM_LDO_CTRL_CHP_EN_1P1(r32) _BFGET_(r32, 8, 8)
#define SET32smSysCtl_SM_LDO_CTRL_CHP_EN_1P1(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16smSysCtl_SM_LDO_CTRL_CHP_EN_1P1(r16) _BFGET_(r16, 8, 8)
#define SET16smSysCtl_SM_LDO_CTRL_CHP_EN_1P1(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32smSysCtl_SM_LDO_CTRL_ICLAMP_EN_1P1(r32) _BFGET_(r32, 9, 9)
#define SET32smSysCtl_SM_LDO_CTRL_ICLAMP_EN_1P1(r32,v) _BFSET_(r32, 9, 9,v)
#define GET16smSysCtl_SM_LDO_CTRL_ICLAMP_EN_1P1(r16) _BFGET_(r16, 9, 9)
#define SET16smSysCtl_SM_LDO_CTRL_ICLAMP_EN_1P1(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32smSysCtl_SM_LDO_CTRL_RSVD_HI(r32) _BFGET_(r32,14,10)
#define SET32smSysCtl_SM_LDO_CTRL_RSVD_HI(r32,v) _BFSET_(r32,14,10,v)
#define GET16smSysCtl_SM_LDO_CTRL_RSVD_HI(r16) _BFGET_(r16,14,10)
#define SET16smSysCtl_SM_LDO_CTRL_RSVD_HI(r16,v) _BFSET_(r16,14,10,v)
#define GET32smSysCtl_SM_LDO_CTRL_RSVD_LO(r32) _BFGET_(r32,19,15)
#define SET32smSysCtl_SM_LDO_CTRL_RSVD_LO(r32,v) _BFSET_(r32,19,15,v)
#define GET32smSysCtl_SM_LDO_CTRL_ZERO_SEL(r32) _BFGET_(r32,21,20)
#define SET32smSysCtl_SM_LDO_CTRL_ZERO_SEL(r32,v) _BFSET_(r32,21,20,v)
#define GET16smSysCtl_SM_LDO_CTRL_ZERO_SEL(r16) _BFGET_(r16, 5, 4)
#define SET16smSysCtl_SM_LDO_CTRL_ZERO_SEL(r16,v) _BFSET_(r16, 5, 4,v)
#define GET32smSysCtl_SM_LDO_CTRL_POLE_SEL(r32) _BFGET_(r32,23,22)
#define SET32smSysCtl_SM_LDO_CTRL_POLE_SEL(r32,v) _BFSET_(r32,23,22,v)
#define GET16smSysCtl_SM_LDO_CTRL_POLE_SEL(r16) _BFGET_(r16, 7, 6)
#define SET16smSysCtl_SM_LDO_CTRL_POLE_SEL(r16,v) _BFSET_(r16, 7, 6,v)
#define GET32smSysCtl_SM_LDO_CTRL_MON_VDD1P8_SEL(r32) _BFGET_(r32,25,24)
#define SET32smSysCtl_SM_LDO_CTRL_MON_VDD1P8_SEL(r32,v) _BFSET_(r32,25,24,v)
#define GET16smSysCtl_SM_LDO_CTRL_MON_VDD1P8_SEL(r16) _BFGET_(r16, 9, 8)
#define SET16smSysCtl_SM_LDO_CTRL_MON_VDD1P8_SEL(r16,v) _BFSET_(r16, 9, 8,v)
#define GET32smSysCtl_SM_LDO_CTRL_DLY_SEL(r32) _BFGET_(r32,27,26)
#define SET32smSysCtl_SM_LDO_CTRL_DLY_SEL(r32,v) _BFSET_(r32,27,26,v)
#define GET16smSysCtl_SM_LDO_CTRL_DLY_SEL(r16) _BFGET_(r16,11,10)
#define SET16smSysCtl_SM_LDO_CTRL_DLY_SEL(r16,v) _BFSET_(r16,11,10,v)
#define GET32smSysCtl_SM_LDO_CTRL_EN_ZERO_SEL(r32) _BFGET_(r32,28,28)
#define SET32smSysCtl_SM_LDO_CTRL_EN_ZERO_SEL(r32,v) _BFSET_(r32,28,28,v)
#define GET16smSysCtl_SM_LDO_CTRL_EN_ZERO_SEL(r16) _BFGET_(r16,12,12)
#define SET16smSysCtl_SM_LDO_CTRL_EN_ZERO_SEL(r16,v) _BFSET_(r16,12,12,v)
#define GET32smSysCtl_SM_LDO_CTRL_EN_POLE_SEL(r32) _BFGET_(r32,29,29)
#define SET32smSysCtl_SM_LDO_CTRL_EN_POLE_SEL(r32,v) _BFSET_(r32,29,29,v)
#define GET16smSysCtl_SM_LDO_CTRL_EN_POLE_SEL(r16) _BFGET_(r16,13,13)
#define SET16smSysCtl_SM_LDO_CTRL_EN_POLE_SEL(r16,v) _BFSET_(r16,13,13,v)
#define GET32smSysCtl_SM_LDO_CTRL_PD_MON_VDD1P8(r32) _BFGET_(r32,30,30)
#define SET32smSysCtl_SM_LDO_CTRL_PD_MON_VDD1P8(r32,v) _BFSET_(r32,30,30,v)
#define GET16smSysCtl_SM_LDO_CTRL_PD_MON_VDD1P8(r16) _BFGET_(r16,14,14)
#define SET16smSysCtl_SM_LDO_CTRL_PD_MON_VDD1P8(r16,v) _BFSET_(r16,14,14,v)
#define GET32smSysCtl_SM_LDO_CTRL_MON_VDD1P8_OUT(r32) _BFGET_(r32,31,31)
#define SET32smSysCtl_SM_LDO_CTRL_MON_VDD1P8_OUT(r32,v) _BFSET_(r32,31,31,v)
#define GET16smSysCtl_SM_LDO_CTRL_MON_VDD1P8_OUT(r16) _BFGET_(r16,15,15)
#define SET16smSysCtl_SM_LDO_CTRL_MON_VDD1P8_OUT(r16,v) _BFSET_(r16,15,15,v)
#define w32smSysCtl_SM_LDO_CTRL {\
UNSG32 uSM_LDO_CTRL_TEST_SEL : 3;\
UNSG32 uSM_LDO_CTRL_VOUT_SEL : 3;\
UNSG32 uSM_LDO_CTRL_TEST_EN : 1;\
UNSG32 uSM_LDO_CTRL_LDO_RDY : 1;\
UNSG32 uSM_LDO_CTRL_CHP_EN_1P1 : 1;\
UNSG32 uSM_LDO_CTRL_ICLAMP_EN_1P1 : 1;\
UNSG32 uSM_LDO_CTRL_RSVD_HI : 5;\
UNSG32 uSM_LDO_CTRL_RSVD_LO : 5;\
UNSG32 uSM_LDO_CTRL_ZERO_SEL : 2;\
UNSG32 uSM_LDO_CTRL_POLE_SEL : 2;\
UNSG32 uSM_LDO_CTRL_MON_VDD1P8_SEL : 2;\
UNSG32 uSM_LDO_CTRL_DLY_SEL : 2;\
UNSG32 uSM_LDO_CTRL_EN_ZERO_SEL : 1;\
UNSG32 uSM_LDO_CTRL_EN_POLE_SEL : 1;\
UNSG32 uSM_LDO_CTRL_PD_MON_VDD1P8 : 1;\
UNSG32 uSM_LDO_CTRL_MON_VDD1P8_OUT : 1;\
}
union { UNSG32 u32smSysCtl_SM_LDO_CTRL;
struct w32smSysCtl_SM_LDO_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_WDT_MASK_SM_RST(r32) _BFGET_(r32, 2, 0)
#define SET32smSysCtl_SM_WDT_MASK_SM_RST(r32,v) _BFSET_(r32, 2, 0,v)
#define GET16smSysCtl_SM_WDT_MASK_SM_RST(r16) _BFGET_(r16, 2, 0)
#define SET16smSysCtl_SM_WDT_MASK_SM_RST(r16,v) _BFSET_(r16, 2, 0,v)
#define GET32smSysCtl_SM_WDT_MASK_SOC_RST(r32) _BFGET_(r32, 5, 3)
#define SET32smSysCtl_SM_WDT_MASK_SOC_RST(r32,v) _BFSET_(r32, 5, 3,v)
#define GET16smSysCtl_SM_WDT_MASK_SOC_RST(r16) _BFGET_(r16, 5, 3)
#define SET16smSysCtl_SM_WDT_MASK_SOC_RST(r16,v) _BFSET_(r16, 5, 3,v)
#define w32smSysCtl_SM_WDT_MASK {\
UNSG32 uSM_WDT_MASK_SM_RST : 3;\
UNSG32 uSM_WDT_MASK_SOC_RST : 3;\
UNSG32 RSVDx40_b6 : 26;\
}
union { UNSG32 u32smSysCtl_SM_WDT_MASK;
struct w32smSysCtl_SM_WDT_MASK;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_CLK_CTRL_tsenClkSel(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_CLK_CTRL_tsenClkSel(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_CLK_CTRL_tsenClkSel(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_CLK_CTRL_tsenClkSel(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_SM_CLK_CTRL_tsenClkEn(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_SM_CLK_CTRL_tsenClkEn(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_SM_CLK_CTRL_tsenClkEn(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_SM_CLK_CTRL_tsenClkEn(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32smSysCtl_SM_CLK_CTRL_ssmiiTxClkSel(r32) _BFGET_(r32, 2, 2)
#define SET32smSysCtl_SM_CLK_CTRL_ssmiiTxClkSel(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16smSysCtl_SM_CLK_CTRL_ssmiiTxClkSel(r16) _BFGET_(r16, 2, 2)
#define SET16smSysCtl_SM_CLK_CTRL_ssmiiTxClkSel(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32smSysCtl_SM_CLK_CTRL_ssmiiTxClkEn(r32) _BFGET_(r32, 3, 3)
#define SET32smSysCtl_SM_CLK_CTRL_ssmiiTxClkEn(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16smSysCtl_SM_CLK_CTRL_ssmiiTxClkEn(r16) _BFGET_(r16, 3, 3)
#define SET16smSysCtl_SM_CLK_CTRL_ssmiiTxClkEn(r16,v) _BFSET_(r16, 3, 3,v)
#define w32smSysCtl_SM_CLK_CTRL {\
UNSG32 uSM_CLK_CTRL_tsenClkSel : 1;\
UNSG32 uSM_CLK_CTRL_tsenClkEn : 1;\
UNSG32 uSM_CLK_CTRL_ssmiiTxClkSel : 1;\
UNSG32 uSM_CLK_CTRL_ssmiiTxClkEn : 1;\
UNSG32 RSVDx44_b4 : 28;\
}
union { UNSG32 u32smSysCtl_SM_CLK_CTRL;
struct w32smSysCtl_SM_CLK_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_smAnaGrpCtl_pu(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_smAnaGrpCtl_pu(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_smAnaGrpCtl_pu(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_smAnaGrpCtl_pu(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_smAnaGrpCtl_bgSel(r32) _BFGET_(r32, 2, 1)
#define SET32smSysCtl_smAnaGrpCtl_bgSel(r32,v) _BFSET_(r32, 2, 1,v)
#define GET16smSysCtl_smAnaGrpCtl_bgSel(r16) _BFGET_(r16, 2, 1)
#define SET16smSysCtl_smAnaGrpCtl_bgSel(r16,v) _BFSET_(r16, 2, 1,v)
#define GET32smSysCtl_smAnaGrpCtl_puXtl(r32) _BFGET_(r32, 3, 3)
#define SET32smSysCtl_smAnaGrpCtl_puXtl(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16smSysCtl_smAnaGrpCtl_puXtl(r16) _BFGET_(r16, 3, 3)
#define SET16smSysCtl_smAnaGrpCtl_puXtl(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32smSysCtl_smAnaGrpCtl_bypass(r32) _BFGET_(r32, 4, 4)
#define SET32smSysCtl_smAnaGrpCtl_bypass(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16smSysCtl_smAnaGrpCtl_bypass(r16) _BFGET_(r16, 4, 4)
#define SET16smSysCtl_smAnaGrpCtl_bypass(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32smSysCtl_smAnaGrpCtl_gainX2(r32) _BFGET_(r32, 5, 5)
#define SET32smSysCtl_smAnaGrpCtl_gainX2(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16smSysCtl_smAnaGrpCtl_gainX2(r16) _BFGET_(r16, 5, 5)
#define SET16smSysCtl_smAnaGrpCtl_gainX2(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32smSysCtl_smAnaGrpCtl_selClkDigDiv1(r32) _BFGET_(r32, 7, 6)
#define SET32smSysCtl_smAnaGrpCtl_selClkDigDiv1(r32,v) _BFSET_(r32, 7, 6,v)
#define GET16smSysCtl_smAnaGrpCtl_selClkDigDiv1(r16) _BFGET_(r16, 7, 6)
#define SET16smSysCtl_smAnaGrpCtl_selClkDigDiv1(r16,v) _BFSET_(r16, 7, 6,v)
#define GET32smSysCtl_smAnaGrpCtl_selClkDigDiv2(r32) _BFGET_(r32, 9, 8)
#define SET32smSysCtl_smAnaGrpCtl_selClkDigDiv2(r32,v) _BFSET_(r32, 9, 8,v)
#define GET16smSysCtl_smAnaGrpCtl_selClkDigDiv2(r16) _BFGET_(r16, 9, 8)
#define SET16smSysCtl_smAnaGrpCtl_selClkDigDiv2(r16,v) _BFSET_(r16, 9, 8,v)
#define GET32smSysCtl_smAnaGrpCtl_selClkDigDiv3(r32) _BFGET_(r32,11,10)
#define SET32smSysCtl_smAnaGrpCtl_selClkDigDiv3(r32,v) _BFSET_(r32,11,10,v)
#define GET16smSysCtl_smAnaGrpCtl_selClkDigDiv3(r16) _BFGET_(r16,11,10)
#define SET16smSysCtl_smAnaGrpCtl_selClkDigDiv3(r16,v) _BFSET_(r16,11,10,v)
#define GET32smSysCtl_smAnaGrpCtl_selClkDigDiv4(r32) _BFGET_(r32,13,12)
#define SET32smSysCtl_smAnaGrpCtl_selClkDigDiv4(r32,v) _BFSET_(r32,13,12,v)
#define GET16smSysCtl_smAnaGrpCtl_selClkDigDiv4(r16) _BFGET_(r16,13,12)
#define SET16smSysCtl_smAnaGrpCtl_selClkDigDiv4(r16,v) _BFSET_(r16,13,12,v)
#define GET32smSysCtl_smAnaGrpCtl_puOsc(r32) _BFGET_(r32,14,14)
#define SET32smSysCtl_smAnaGrpCtl_puOsc(r32,v) _BFSET_(r32,14,14,v)
#define GET16smSysCtl_smAnaGrpCtl_puOsc(r16) _BFGET_(r16,14,14)
#define SET16smSysCtl_smAnaGrpCtl_puOsc(r16,v) _BFSET_(r16,14,14,v)
#define GET32smSysCtl_smAnaGrpCtl_speedOsc(r32) _BFGET_(r32,16,15)
#define SET32smSysCtl_smAnaGrpCtl_speedOsc(r32,v) _BFSET_(r32,16,15,v)
#define GET32smSysCtl_smAnaGrpCtl_testAna(r32) _BFGET_(r32,20,17)
#define SET32smSysCtl_smAnaGrpCtl_testAna(r32,v) _BFSET_(r32,20,17,v)
#define GET16smSysCtl_smAnaGrpCtl_testAna(r16) _BFGET_(r16, 4, 1)
#define SET16smSysCtl_smAnaGrpCtl_testAna(r16,v) _BFSET_(r16, 4, 1,v)
#define GET32smSysCtl_smAnaGrpCtl_bgRdy(r32) _BFGET_(r32,21,21)
#define SET32smSysCtl_smAnaGrpCtl_bgRdy(r32,v) _BFSET_(r32,21,21,v)
#define GET16smSysCtl_smAnaGrpCtl_bgRdy(r16) _BFGET_(r16, 5, 5)
#define SET16smSysCtl_smAnaGrpCtl_bgRdy(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32smSysCtl_smAnaGrpCtl_reserve_in(r32) _BFGET_(r32,31,22)
#define SET32smSysCtl_smAnaGrpCtl_reserve_in(r32,v) _BFSET_(r32,31,22,v)
#define GET16smSysCtl_smAnaGrpCtl_reserve_in(r16) _BFGET_(r16,15, 6)
#define SET16smSysCtl_smAnaGrpCtl_reserve_in(r16,v) _BFSET_(r16,15, 6,v)
#define w32smSysCtl_smAnaGrpCtl {\
UNSG32 usmAnaGrpCtl_pu : 1;\
UNSG32 usmAnaGrpCtl_bgSel : 2;\
UNSG32 usmAnaGrpCtl_puXtl : 1;\
UNSG32 usmAnaGrpCtl_bypass : 1;\
UNSG32 usmAnaGrpCtl_gainX2 : 1;\
UNSG32 usmAnaGrpCtl_selClkDigDiv1 : 2;\
UNSG32 usmAnaGrpCtl_selClkDigDiv2 : 2;\
UNSG32 usmAnaGrpCtl_selClkDigDiv3 : 2;\
UNSG32 usmAnaGrpCtl_selClkDigDiv4 : 2;\
UNSG32 usmAnaGrpCtl_puOsc : 1;\
UNSG32 usmAnaGrpCtl_speedOsc : 2;\
UNSG32 usmAnaGrpCtl_testAna : 4;\
UNSG32 usmAnaGrpCtl_bgRdy : 1;\
UNSG32 usmAnaGrpCtl_reserve_in : 10;\
}
union { UNSG32 u32smSysCtl_smAnaGrpCtl;
struct w32smSysCtl_smAnaGrpCtl;
};
#define GET32smSysCtl_smAnaGrpCtl_xtl_pecl_sel(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_smAnaGrpCtl_xtl_pecl_sel(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_smAnaGrpCtl_xtl_pecl_sel(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_smAnaGrpCtl_xtl_pecl_sel(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_smAnaGrpCtl_vreg_1p4v_sel(r32) _BFGET_(r32, 2, 1)
#define SET32smSysCtl_smAnaGrpCtl_vreg_1p4v_sel(r32,v) _BFSET_(r32, 2, 1,v)
#define GET16smSysCtl_smAnaGrpCtl_vreg_1p4v_sel(r16) _BFGET_(r16, 2, 1)
#define SET16smSysCtl_smAnaGrpCtl_vreg_1p4v_sel(r16,v) _BFSET_(r16, 2, 1,v)
#define GET32smSysCtl_smAnaGrpCtl_vreg_0p9v_sel_xtl(r32) _BFGET_(r32, 5, 3)
#define SET32smSysCtl_smAnaGrpCtl_vreg_0p9v_sel_xtl(r32,v) _BFSET_(r32, 5, 3,v)
#define GET16smSysCtl_smAnaGrpCtl_vreg_0p9v_sel_xtl(r16) _BFGET_(r16, 5, 3)
#define SET16smSysCtl_smAnaGrpCtl_vreg_0p9v_sel_xtl(r16,v) _BFSET_(r16, 5, 3,v)
#define GET32smSysCtl_smAnaGrpCtl_vreg_0p9v_sel_pecl(r32) _BFGET_(r32, 8, 6)
#define SET32smSysCtl_smAnaGrpCtl_vreg_0p9v_sel_pecl(r32,v) _BFSET_(r32, 8, 6,v)
#define GET16smSysCtl_smAnaGrpCtl_vreg_0p9v_sel_pecl(r16) _BFGET_(r16, 8, 6)
#define SET16smSysCtl_smAnaGrpCtl_vreg_0p9v_sel_pecl(r16,v) _BFSET_(r16, 8, 6,v)
#define GET32smSysCtl_smAnaGrpCtl_term(r32) _BFGET_(r32, 9, 9)
#define SET32smSysCtl_smAnaGrpCtl_term(r32,v) _BFSET_(r32, 9, 9,v)
#define GET16smSysCtl_smAnaGrpCtl_term(r16) _BFGET_(r16, 9, 9)
#define SET16smSysCtl_smAnaGrpCtl_term(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32smSysCtl_smAnaGrpCtl_pu_pecl(r32) _BFGET_(r32,10,10)
#define SET32smSysCtl_smAnaGrpCtl_pu_pecl(r32,v) _BFSET_(r32,10,10,v)
#define GET16smSysCtl_smAnaGrpCtl_pu_pecl(r16) _BFGET_(r16,10,10)
#define SET16smSysCtl_smAnaGrpCtl_pu_pecl(r16,v) _BFSET_(r16,10,10,v)
#define GET32smSysCtl_smAnaGrpCtl_pecl_en(r32) _BFGET_(r32,11,11)
#define SET32smSysCtl_smAnaGrpCtl_pecl_en(r32,v) _BFSET_(r32,11,11,v)
#define GET16smSysCtl_smAnaGrpCtl_pecl_en(r16) _BFGET_(r16,11,11)
#define SET16smSysCtl_smAnaGrpCtl_pecl_en(r16,v) _BFSET_(r16,11,11,v)
#define GET32smSysCtl_smAnaGrpCtl_pu_limiter(r32) _BFGET_(r32,12,12)
#define SET32smSysCtl_smAnaGrpCtl_pu_limiter(r32,v) _BFSET_(r32,12,12,v)
#define GET16smSysCtl_smAnaGrpCtl_pu_limiter(r16) _BFGET_(r16,12,12)
#define SET16smSysCtl_smAnaGrpCtl_pu_limiter(r16,v) _BFSET_(r16,12,12,v)
#define GET32smSysCtl_smAnaGrpCtl_limiter_dc_clk_en(r32) _BFGET_(r32,13,13)
#define SET32smSysCtl_smAnaGrpCtl_limiter_dc_clk_en(r32,v) _BFSET_(r32,13,13,v)
#define GET16smSysCtl_smAnaGrpCtl_limiter_dc_clk_en(r16) _BFGET_(r16,13,13)
#define SET16smSysCtl_smAnaGrpCtl_limiter_dc_clk_en(r16,v) _BFSET_(r16,13,13,v)
#define GET32smSysCtl_smAnaGrpCtl_ipp_adj(r32) _BFGET_(r32,15,14)
#define SET32smSysCtl_smAnaGrpCtl_ipp_adj(r32,v) _BFSET_(r32,15,14,v)
#define GET16smSysCtl_smAnaGrpCtl_ipp_adj(r16) _BFGET_(r16,15,14)
#define SET16smSysCtl_smAnaGrpCtl_ipp_adj(r16,v) _BFSET_(r16,15,14,v)
#define GET32smSysCtl_smAnaGrpCtl_icc_adj(r32) _BFGET_(r32,17,16)
#define SET32smSysCtl_smAnaGrpCtl_icc_adj(r32,v) _BFSET_(r32,17,16,v)
#define GET16smSysCtl_smAnaGrpCtl_icc_adj(r16) _BFGET_(r16, 1, 0)
#define SET16smSysCtl_smAnaGrpCtl_icc_adj(r16,v) _BFSET_(r16, 1, 0,v)
#define GET32smSysCtl_smAnaGrpCtl_ixtal(r32) _BFGET_(r32,19,18)
#define SET32smSysCtl_smAnaGrpCtl_ixtal(r32,v) _BFSET_(r32,19,18,v)
#define GET16smSysCtl_smAnaGrpCtl_ixtal(r16) _BFGET_(r16, 3, 2)
#define SET16smSysCtl_smAnaGrpCtl_ixtal(r16,v) _BFSET_(r16, 3, 2,v)
#define GET32smSysCtl_smAnaGrpCtl_icc10u_in_sel(r32) _BFGET_(r32,20,20)
#define SET32smSysCtl_smAnaGrpCtl_icc10u_in_sel(r32,v) _BFSET_(r32,20,20,v)
#define GET16smSysCtl_smAnaGrpCtl_icc10u_in_sel(r16) _BFGET_(r16, 4, 4)
#define SET16smSysCtl_smAnaGrpCtl_icc10u_in_sel(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32smSysCtl_smAnaGrpCtl_reserve_out(r32) _BFGET_(r32,26,21)
#define SET32smSysCtl_smAnaGrpCtl_reserve_out(r32,v) _BFSET_(r32,26,21,v)
#define GET16smSysCtl_smAnaGrpCtl_reserve_out(r16) _BFGET_(r16,10, 5)
#define SET16smSysCtl_smAnaGrpCtl_reserve_out(r16,v) _BFSET_(r16,10, 5,v)
#define w32smSysCtl_smAnaGrpCtl1 {\
UNSG32 usmAnaGrpCtl_xtl_pecl_sel : 1;\
UNSG32 usmAnaGrpCtl_vreg_1p4v_sel : 2;\
UNSG32 usmAnaGrpCtl_vreg_0p9v_sel_xtl : 3;\
UNSG32 usmAnaGrpCtl_vreg_0p9v_sel_pecl : 3;\
UNSG32 usmAnaGrpCtl_term : 1;\
UNSG32 usmAnaGrpCtl_pu_pecl : 1;\
UNSG32 usmAnaGrpCtl_pecl_en : 1;\
UNSG32 usmAnaGrpCtl_pu_limiter : 1;\
UNSG32 usmAnaGrpCtl_limiter_dc_clk_en : 1;\
UNSG32 usmAnaGrpCtl_ipp_adj : 2;\
UNSG32 usmAnaGrpCtl_icc_adj : 2;\
UNSG32 usmAnaGrpCtl_ixtal : 2;\
UNSG32 usmAnaGrpCtl_icc10u_in_sel : 1;\
UNSG32 usmAnaGrpCtl_reserve_out : 6;\
UNSG32 RSVDx4C_b27 : 5;\
}
union { UNSG32 u32smSysCtl_smAnaGrpCtl1;
struct w32smSysCtl_smAnaGrpCtl1;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_POR_status_POR_AVDD33(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_POR_status_POR_AVDD33(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_POR_status_POR_AVDD33(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_POR_status_POR_AVDD33(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_POR_status_POR_AVDD(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_POR_status_POR_AVDD(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_POR_status_POR_AVDD(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_POR_status_POR_AVDD(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32smSysCtl_POR_status_POR_VDD_SOC(r32) _BFGET_(r32, 2, 2)
#define SET32smSysCtl_POR_status_POR_VDD_SOC(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16smSysCtl_POR_status_POR_VDD_SOC(r16) _BFGET_(r16, 2, 2)
#define SET16smSysCtl_POR_status_POR_VDD_SOC(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32smSysCtl_POR_status_POR_VDD_CPU(r32) _BFGET_(r32, 3, 3)
#define SET32smSysCtl_POR_status_POR_VDD_CPU(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16smSysCtl_POR_status_POR_VDD_CPU(r16) _BFGET_(r16, 3, 3)
#define SET16smSysCtl_POR_status_POR_VDD_CPU(r16,v) _BFSET_(r16, 3, 3,v)
#define w32smSysCtl_POR_status {\
UNSG32 uPOR_status_POR_AVDD33 : 1;\
UNSG32 uPOR_status_POR_AVDD : 1;\
UNSG32 uPOR_status_POR_VDD_SOC : 1;\
UNSG32 uPOR_status_POR_VDD_CPU : 1;\
UNSG32 RSVDx50_b4 : 28;\
}
union { UNSG32 u32smSysCtl_POR_status;
struct w32smSysCtl_POR_status;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_CORE_CTRL_PAD_REG_PDB_CORE(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_CORE_CTRL_PAD_REG_PDB_CORE(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_CORE_CTRL_PAD_REG_PDB_CORE(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_CORE_CTRL_PAD_REG_PDB_CORE(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_SM_CORE_CTRL_PAD_V18EN_CORE(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_SM_CORE_CTRL_PAD_V18EN_CORE(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_SM_CORE_CTRL_PAD_V18EN_CORE(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_SM_CORE_CTRL_PAD_V18EN_CORE(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32smSysCtl_SM_CORE_CTRL_PAD_V25EN_CORE(r32) _BFGET_(r32, 2, 2)
#define SET32smSysCtl_SM_CORE_CTRL_PAD_V25EN_CORE(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16smSysCtl_SM_CORE_CTRL_PAD_V25EN_CORE(r16) _BFGET_(r16, 2, 2)
#define SET16smSysCtl_SM_CORE_CTRL_PAD_V25EN_CORE(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32smSysCtl_SM_CORE_CTRL_PAD_ZP(r32) _BFGET_(r32, 6, 3)
#define SET32smSysCtl_SM_CORE_CTRL_PAD_ZP(r32,v) _BFSET_(r32, 6, 3,v)
#define GET16smSysCtl_SM_CORE_CTRL_PAD_ZP(r16) _BFGET_(r16, 6, 3)
#define SET16smSysCtl_SM_CORE_CTRL_PAD_ZP(r16,v) _BFSET_(r16, 6, 3,v)
#define GET32smSysCtl_SM_CORE_CTRL_PAD_ZN(r32) _BFGET_(r32,10, 7)
#define SET32smSysCtl_SM_CORE_CTRL_PAD_ZN(r32,v) _BFSET_(r32,10, 7,v)
#define GET16smSysCtl_SM_CORE_CTRL_PAD_ZN(r16) _BFGET_(r16,10, 7)
#define SET16smSysCtl_SM_CORE_CTRL_PAD_ZN(r16,v) _BFSET_(r16,10, 7,v)
#define w32smSysCtl_SM_CORE_CTRL {\
UNSG32 uSM_CORE_CTRL_PAD_REG_PDB_CORE : 1;\
UNSG32 uSM_CORE_CTRL_PAD_V18EN_CORE : 1;\
UNSG32 uSM_CORE_CTRL_PAD_V25EN_CORE : 1;\
UNSG32 uSM_CORE_CTRL_PAD_ZP : 4;\
UNSG32 uSM_CORE_CTRL_PAD_ZN : 4;\
UNSG32 RSVDx54_b11 : 21;\
}
union { UNSG32 u32smSysCtl_SM_CORE_CTRL;
struct w32smSysCtl_SM_CORE_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_TEST_ADC_TEST_FAIL(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_TEST_ADC_TEST_FAIL(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_TEST_ADC_TEST_FAIL(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_TEST_ADC_TEST_FAIL(r16,v) _BFSET_(r16, 0, 0,v)
#define w32smSysCtl_SM_TEST {\
UNSG32 uSM_TEST_ADC_TEST_FAIL : 1;\
UNSG32 RSVDx58_b1 : 31;\
}
union { UNSG32 u32smSysCtl_SM_TEST;
struct w32smSysCtl_SM_TEST;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_TEST_DATA0_ADC_DATA_HIGH(r32) _BFGET_(r32, 9, 0)
#define SET32smSysCtl_SM_TEST_DATA0_ADC_DATA_HIGH(r32,v) _BFSET_(r32, 9, 0,v)
#define GET16smSysCtl_SM_TEST_DATA0_ADC_DATA_HIGH(r16) _BFGET_(r16, 9, 0)
#define SET16smSysCtl_SM_TEST_DATA0_ADC_DATA_HIGH(r16,v) _BFSET_(r16, 9, 0,v)
#define w32smSysCtl_SM_TEST_DATA0 {\
UNSG32 uSM_TEST_DATA0_ADC_DATA_HIGH : 10;\
UNSG32 RSVDx5C_b10 : 22;\
}
union { UNSG32 u32smSysCtl_SM_TEST_DATA0;
struct w32smSysCtl_SM_TEST_DATA0;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_TEST_DATA1_ADC_DATA_LOW(r32) _BFGET_(r32, 9, 0)
#define SET32smSysCtl_SM_TEST_DATA1_ADC_DATA_LOW(r32,v) _BFSET_(r32, 9, 0,v)
#define GET16smSysCtl_SM_TEST_DATA1_ADC_DATA_LOW(r16) _BFGET_(r16, 9, 0)
#define SET16smSysCtl_SM_TEST_DATA1_ADC_DATA_LOW(r16,v) _BFSET_(r16, 9, 0,v)
#define w32smSysCtl_SM_TEST_DATA1 {\
UNSG32 uSM_TEST_DATA1_ADC_DATA_LOW : 10;\
UNSG32 RSVDx60_b10 : 22;\
}
union { UNSG32 u32smSysCtl_SM_TEST_DATA1;
struct w32smSysCtl_SM_TEST_DATA1;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_RWTC_CTRL_0_RF1P_LOW(r32) _BFGET_(r32, 3, 0)
#define SET32smSysCtl_SM_RWTC_CTRL_0_RF1P_LOW(r32,v) _BFSET_(r32, 3, 0,v)
#define GET16smSysCtl_SM_RWTC_CTRL_0_RF1P_LOW(r16) _BFGET_(r16, 3, 0)
#define SET16smSysCtl_SM_RWTC_CTRL_0_RF1P_LOW(r16,v) _BFSET_(r16, 3, 0,v)
#define GET32smSysCtl_SM_RWTC_CTRL_0_RF1P_HIGH(r32) _BFGET_(r32, 7, 4)
#define SET32smSysCtl_SM_RWTC_CTRL_0_RF1P_HIGH(r32,v) _BFSET_(r32, 7, 4,v)
#define GET16smSysCtl_SM_RWTC_CTRL_0_RF1P_HIGH(r16) _BFGET_(r16, 7, 4)
#define SET16smSysCtl_SM_RWTC_CTRL_0_RF1P_HIGH(r16,v) _BFSET_(r16, 7, 4,v)
#define GET32smSysCtl_SM_RWTC_CTRL_0_RF2P_LOW(r32) _BFGET_(r32,11, 8)
#define SET32smSysCtl_SM_RWTC_CTRL_0_RF2P_LOW(r32,v) _BFSET_(r32,11, 8,v)
#define GET16smSysCtl_SM_RWTC_CTRL_0_RF2P_LOW(r16) _BFGET_(r16,11, 8)
#define SET16smSysCtl_SM_RWTC_CTRL_0_RF2P_LOW(r16,v) _BFSET_(r16,11, 8,v)
#define GET32smSysCtl_SM_RWTC_CTRL_0_RF2P_HIGH(r32) _BFGET_(r32,15,12)
#define SET32smSysCtl_SM_RWTC_CTRL_0_RF2P_HIGH(r32,v) _BFSET_(r32,15,12,v)
#define GET16smSysCtl_SM_RWTC_CTRL_0_RF2P_HIGH(r16) _BFGET_(r16,15,12)
#define SET16smSysCtl_SM_RWTC_CTRL_0_RF2P_HIGH(r16,v) _BFSET_(r16,15,12,v)
#define GET32smSysCtl_SM_RWTC_CTRL_0_SR1P_LOW(r32) _BFGET_(r32,19,16)
#define SET32smSysCtl_SM_RWTC_CTRL_0_SR1P_LOW(r32,v) _BFSET_(r32,19,16,v)
#define GET16smSysCtl_SM_RWTC_CTRL_0_SR1P_LOW(r16) _BFGET_(r16, 3, 0)
#define SET16smSysCtl_SM_RWTC_CTRL_0_SR1P_LOW(r16,v) _BFSET_(r16, 3, 0,v)
#define GET32smSysCtl_SM_RWTC_CTRL_0_SR1P_HIGH(r32) _BFGET_(r32,23,20)
#define SET32smSysCtl_SM_RWTC_CTRL_0_SR1P_HIGH(r32,v) _BFSET_(r32,23,20,v)
#define GET16smSysCtl_SM_RWTC_CTRL_0_SR1P_HIGH(r16) _BFGET_(r16, 7, 4)
#define SET16smSysCtl_SM_RWTC_CTRL_0_SR1P_HIGH(r16,v) _BFSET_(r16, 7, 4,v)
#define GET32smSysCtl_SM_RWTC_CTRL_0_SR2P_LOW(r32) _BFGET_(r32,27,24)
#define SET32smSysCtl_SM_RWTC_CTRL_0_SR2P_LOW(r32,v) _BFSET_(r32,27,24,v)
#define GET16smSysCtl_SM_RWTC_CTRL_0_SR2P_LOW(r16) _BFGET_(r16,11, 8)
#define SET16smSysCtl_SM_RWTC_CTRL_0_SR2P_LOW(r16,v) _BFSET_(r16,11, 8,v)
#define GET32smSysCtl_SM_RWTC_CTRL_0_SR2P_HIGH(r32) _BFGET_(r32,31,28)
#define SET32smSysCtl_SM_RWTC_CTRL_0_SR2P_HIGH(r32,v) _BFSET_(r32,31,28,v)
#define GET16smSysCtl_SM_RWTC_CTRL_0_SR2P_HIGH(r16) _BFGET_(r16,15,12)
#define SET16smSysCtl_SM_RWTC_CTRL_0_SR2P_HIGH(r16,v) _BFSET_(r16,15,12,v)
#define w32smSysCtl_SM_RWTC_CTRL_0 {\
UNSG32 uSM_RWTC_CTRL_0_RF1P_LOW : 4;\
UNSG32 uSM_RWTC_CTRL_0_RF1P_HIGH : 4;\
UNSG32 uSM_RWTC_CTRL_0_RF2P_LOW : 4;\
UNSG32 uSM_RWTC_CTRL_0_RF2P_HIGH : 4;\
UNSG32 uSM_RWTC_CTRL_0_SR1P_LOW : 4;\
UNSG32 uSM_RWTC_CTRL_0_SR1P_HIGH : 4;\
UNSG32 uSM_RWTC_CTRL_0_SR2P_LOW : 4;\
UNSG32 uSM_RWTC_CTRL_0_SR2P_HIGH : 4;\
}
union { UNSG32 u32smSysCtl_SM_RWTC_CTRL_0;
struct w32smSysCtl_SM_RWTC_CTRL_0;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_RWTC_CTRL_1_ROM_LOW(r32) _BFGET_(r32, 4, 0)
#define SET32smSysCtl_SM_RWTC_CTRL_1_ROM_LOW(r32,v) _BFSET_(r32, 4, 0,v)
#define GET16smSysCtl_SM_RWTC_CTRL_1_ROM_LOW(r16) _BFGET_(r16, 4, 0)
#define SET16smSysCtl_SM_RWTC_CTRL_1_ROM_LOW(r16,v) _BFSET_(r16, 4, 0,v)
#define GET32smSysCtl_SM_RWTC_CTRL_1_ROM_HIGH(r32) _BFGET_(r32, 9, 5)
#define SET32smSysCtl_SM_RWTC_CTRL_1_ROM_HIGH(r32,v) _BFSET_(r32, 9, 5,v)
#define GET16smSysCtl_SM_RWTC_CTRL_1_ROM_HIGH(r16) _BFGET_(r16, 9, 5)
#define SET16smSysCtl_SM_RWTC_CTRL_1_ROM_HIGH(r16,v) _BFSET_(r16, 9, 5,v)
#define GET32smSysCtl_SM_RWTC_CTRL_1_RF2P_NH(r32) _BFGET_(r32,13,10)
#define SET32smSysCtl_SM_RWTC_CTRL_1_RF2P_NH(r32,v) _BFSET_(r32,13,10,v)
#define GET16smSysCtl_SM_RWTC_CTRL_1_RF2P_NH(r16) _BFGET_(r16,13,10)
#define SET16smSysCtl_SM_RWTC_CTRL_1_RF2P_NH(r16,v) _BFSET_(r16,13,10,v)
#define GET32smSysCtl_SM_RWTC_CTRL_1_RF2R2W_NH(r32) _BFGET_(r32,17,14)
#define SET32smSysCtl_SM_RWTC_CTRL_1_RF2R2W_NH(r32,v) _BFSET_(r32,17,14,v)
#define GET32smSysCtl_SM_RWTC_CTRL_1_SR1P_LVT(r32) _BFGET_(r32,21,18)
#define SET32smSysCtl_SM_RWTC_CTRL_1_SR1P_LVT(r32,v) _BFSET_(r32,21,18,v)
#define GET16smSysCtl_SM_RWTC_CTRL_1_SR1P_LVT(r16) _BFGET_(r16, 5, 2)
#define SET16smSysCtl_SM_RWTC_CTRL_1_SR1P_LVT(r16,v) _BFSET_(r16, 5, 2,v)
#define GET32smSysCtl_SM_RWTC_CTRL_1_SR2P_LVT(r32) _BFGET_(r32,25,22)
#define SET32smSysCtl_SM_RWTC_CTRL_1_SR2P_LVT(r32,v) _BFSET_(r32,25,22,v)
#define GET16smSysCtl_SM_RWTC_CTRL_1_SR2P_LVT(r16) _BFGET_(r16, 9, 6)
#define SET16smSysCtl_SM_RWTC_CTRL_1_SR2P_LVT(r16,v) _BFSET_(r16, 9, 6,v)
#define w32smSysCtl_SM_RWTC_CTRL_1 {\
UNSG32 uSM_RWTC_CTRL_1_ROM_LOW : 5;\
UNSG32 uSM_RWTC_CTRL_1_ROM_HIGH : 5;\
UNSG32 uSM_RWTC_CTRL_1_RF2P_NH : 4;\
UNSG32 uSM_RWTC_CTRL_1_RF2R2W_NH : 4;\
UNSG32 uSM_RWTC_CTRL_1_SR1P_LVT : 4;\
UNSG32 uSM_RWTC_CTRL_1_SR2P_LVT : 4;\
UNSG32 RSVDx68_b26 : 6;\
}
union { UNSG32 u32smSysCtl_SM_RWTC_CTRL_1;
struct w32smSysCtl_SM_RWTC_CTRL_1;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_PORT_SEL_CTRL_TW2(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_PORT_SEL_CTRL_TW2(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_PORT_SEL_CTRL_TW2(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_PORT_SEL_CTRL_TW2(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_SM_PORT_SEL_CTRL_URT1(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_SM_PORT_SEL_CTRL_URT1(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_SM_PORT_SEL_CTRL_URT1(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_SM_PORT_SEL_CTRL_URT1(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32smSysCtl_SM_PORT_SEL_CTRL_FE_MDIO(r32) _BFGET_(r32, 2, 2)
#define SET32smSysCtl_SM_PORT_SEL_CTRL_FE_MDIO(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16smSysCtl_SM_PORT_SEL_CTRL_FE_MDIO(r16) _BFGET_(r16, 2, 2)
#define SET16smSysCtl_SM_PORT_SEL_CTRL_FE_MDIO(r16,v) _BFSET_(r16, 2, 2,v)
#define w32smSysCtl_SM_PORT_SEL_CTRL {\
UNSG32 uSM_PORT_SEL_CTRL_TW2 : 1;\
UNSG32 uSM_PORT_SEL_CTRL_URT1 : 1;\
UNSG32 uSM_PORT_SEL_CTRL_FE_MDIO : 1;\
UNSG32 RSVDx6C_b3 : 29;\
}
union { UNSG32 u32smSysCtl_SM_PORT_SEL_CTRL;
struct w32smSysCtl_SM_PORT_SEL_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_TSEN_ADC_RAW_DATA_TSEN_DATA_RAW(r32) _BFGET_(r32,11, 0)
#define SET32smSysCtl_TSEN_ADC_RAW_DATA_TSEN_DATA_RAW(r32,v) _BFSET_(r32,11, 0,v)
#define GET16smSysCtl_TSEN_ADC_RAW_DATA_TSEN_DATA_RAW(r16) _BFGET_(r16,11, 0)
#define SET16smSysCtl_TSEN_ADC_RAW_DATA_TSEN_DATA_RAW(r16,v) _BFSET_(r16,11, 0,v)
#define w32smSysCtl_TSEN_ADC_RAW_DATA {\
UNSG32 uTSEN_ADC_RAW_DATA_TSEN_DATA_RAW : 12;\
UNSG32 RSVDx70_b12 : 20;\
}
union { UNSG32 u32smSysCtl_TSEN_ADC_RAW_DATA;
struct w32smSysCtl_TSEN_ADC_RAW_DATA;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_TSEN_ADC_CLK_DIV_ADC_DIV(r32) _BFGET_(r32, 2, 0)
#define SET32smSysCtl_TSEN_ADC_CLK_DIV_ADC_DIV(r32,v) _BFSET_(r32, 2, 0,v)
#define GET16smSysCtl_TSEN_ADC_CLK_DIV_ADC_DIV(r16) _BFGET_(r16, 2, 0)
#define SET16smSysCtl_TSEN_ADC_CLK_DIV_ADC_DIV(r16,v) _BFSET_(r16, 2, 0,v)
#define GET32smSysCtl_TSEN_ADC_CLK_DIV_TSEN_DIV(r32) _BFGET_(r32, 6, 3)
#define SET32smSysCtl_TSEN_ADC_CLK_DIV_TSEN_DIV(r32,v) _BFSET_(r32, 6, 3,v)
#define GET16smSysCtl_TSEN_ADC_CLK_DIV_TSEN_DIV(r16) _BFGET_(r16, 6, 3)
#define SET16smSysCtl_TSEN_ADC_CLK_DIV_TSEN_DIV(r16,v) _BFSET_(r16, 6, 3,v)
#define w32smSysCtl_TSEN_ADC_CLK_DIV {\
UNSG32 uTSEN_ADC_CLK_DIV_ADC_DIV : 3;\
UNSG32 uTSEN_ADC_CLK_DIV_TSEN_DIV : 4;\
UNSG32 RSVDx74_b7 : 25;\
}
union { UNSG32 u32smSysCtl_TSEN_ADC_CLK_DIV;
struct w32smSysCtl_TSEN_ADC_CLK_DIV;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_TSEN_ADC_CTRL_ADC_VREF_ADJ(r32) _BFGET_(r32, 7, 0)
#define SET32smSysCtl_TSEN_ADC_CTRL_ADC_VREF_ADJ(r32,v) _BFSET_(r32, 7, 0,v)
#define GET16smSysCtl_TSEN_ADC_CTRL_ADC_VREF_ADJ(r16) _BFGET_(r16, 7, 0)
#define SET16smSysCtl_TSEN_ADC_CTRL_ADC_VREF_ADJ(r16,v) _BFSET_(r16, 7, 0,v)
#define GET32smSysCtl_TSEN_ADC_CTRL_TSEN_START(r32) _BFGET_(r32, 8, 8)
#define SET32smSysCtl_TSEN_ADC_CTRL_TSEN_START(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16smSysCtl_TSEN_ADC_CTRL_TSEN_START(r16) _BFGET_(r16, 8, 8)
#define SET16smSysCtl_TSEN_ADC_CTRL_TSEN_START(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32smSysCtl_TSEN_ADC_CTRL_TSEN_AVG_NUM(r32) _BFGET_(r32,11, 9)
#define SET32smSysCtl_TSEN_ADC_CTRL_TSEN_AVG_NUM(r32,v) _BFSET_(r32,11, 9,v)
#define GET16smSysCtl_TSEN_ADC_CTRL_TSEN_AVG_NUM(r16) _BFGET_(r16,11, 9)
#define SET16smSysCtl_TSEN_ADC_CTRL_TSEN_AVG_NUM(r16,v) _BFSET_(r16,11, 9,v)
#define GET32smSysCtl_TSEN_ADC_CTRL_TSEN_EXT_EN(r32) _BFGET_(r32,12,12)
#define SET32smSysCtl_TSEN_ADC_CTRL_TSEN_EXT_EN(r32,v) _BFSET_(r32,12,12,v)
#define GET16smSysCtl_TSEN_ADC_CTRL_TSEN_EXT_EN(r16) _BFGET_(r16,12,12)
#define SET16smSysCtl_TSEN_ADC_CTRL_TSEN_EXT_EN(r16,v) _BFSET_(r16,12,12,v)
#define GET32smSysCtl_TSEN_ADC_CTRL_TSEN_CHOP_EN(r32) _BFGET_(r32,14,13)
#define SET32smSysCtl_TSEN_ADC_CTRL_TSEN_CHOP_EN(r32,v) _BFSET_(r32,14,13,v)
#define GET16smSysCtl_TSEN_ADC_CTRL_TSEN_CHOP_EN(r16) _BFGET_(r16,14,13)
#define SET16smSysCtl_TSEN_ADC_CTRL_TSEN_CHOP_EN(r16,v) _BFSET_(r16,14,13,v)
#define GET32smSysCtl_TSEN_ADC_CTRL_TSEN_CAL(r32) _BFGET_(r32,16,15)
#define SET32smSysCtl_TSEN_ADC_CTRL_TSEN_CAL(r32,v) _BFSET_(r32,16,15,v)
#define GET32smSysCtl_TSEN_ADC_CTRL_TSEN_RSVD(r32) _BFGET_(r32,20,17)
#define SET32smSysCtl_TSEN_ADC_CTRL_TSEN_RSVD(r32,v) _BFSET_(r32,20,17,v)
#define GET16smSysCtl_TSEN_ADC_CTRL_TSEN_RSVD(r16) _BFGET_(r16, 4, 1)
#define SET16smSysCtl_TSEN_ADC_CTRL_TSEN_RSVD(r16,v) _BFSET_(r16, 4, 1,v)
#define GET32smSysCtl_TSEN_ADC_CTRL_BG_CHP_SEL(r32) _BFGET_(r32,21,21)
#define SET32smSysCtl_TSEN_ADC_CTRL_BG_CHP_SEL(r32,v) _BFSET_(r32,21,21,v)
#define GET16smSysCtl_TSEN_ADC_CTRL_BG_CHP_SEL(r16) _BFGET_(r16, 5, 5)
#define SET16smSysCtl_TSEN_ADC_CTRL_BG_CHP_SEL(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32smSysCtl_TSEN_ADC_CTRL_BG_DTRIM(r32) _BFGET_(r32,25,22)
#define SET32smSysCtl_TSEN_ADC_CTRL_BG_DTRIM(r32,v) _BFSET_(r32,25,22,v)
#define GET16smSysCtl_TSEN_ADC_CTRL_BG_DTRIM(r16) _BFGET_(r16, 9, 6)
#define SET16smSysCtl_TSEN_ADC_CTRL_BG_DTRIM(r16,v) _BFSET_(r16, 9, 6,v)
#define w32smSysCtl_TSEN_ADC_CTRL {\
UNSG32 uTSEN_ADC_CTRL_ADC_VREF_ADJ : 8;\
UNSG32 uTSEN_ADC_CTRL_TSEN_START : 1;\
UNSG32 uTSEN_ADC_CTRL_TSEN_AVG_NUM : 3;\
UNSG32 uTSEN_ADC_CTRL_TSEN_EXT_EN : 1;\
UNSG32 uTSEN_ADC_CTRL_TSEN_CHOP_EN : 2;\
UNSG32 uTSEN_ADC_CTRL_TSEN_CAL : 2;\
UNSG32 uTSEN_ADC_CTRL_TSEN_RSVD : 4;\
UNSG32 uTSEN_ADC_CTRL_BG_CHP_SEL : 1;\
UNSG32 uTSEN_ADC_CTRL_BG_DTRIM : 4;\
UNSG32 RSVDx78_b26 : 6;\
}
union { UNSG32 u32smSysCtl_TSEN_ADC_CTRL;
struct w32smSysCtl_TSEN_ADC_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_TSEN_ADC_DBG_TSEN_RAW_SEL(r32) _BFGET_(r32, 1, 0)
#define SET32smSysCtl_TSEN_ADC_DBG_TSEN_RAW_SEL(r32,v) _BFSET_(r32, 1, 0,v)
#define GET16smSysCtl_TSEN_ADC_DBG_TSEN_RAW_SEL(r16) _BFGET_(r16, 1, 0)
#define SET16smSysCtl_TSEN_ADC_DBG_TSEN_RAW_SEL(r16,v) _BFSET_(r16, 1, 0,v)
#define w32smSysCtl_TSEN_ADC_DBG {\
UNSG32 uTSEN_ADC_DBG_TSEN_RAW_SEL : 2;\
UNSG32 RSVDx7C_b2 : 30;\
}
union { UNSG32 u32smSysCtl_TSEN_ADC_DBG;
struct w32smSysCtl_TSEN_ADC_DBG;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_DUMMY_REG_REG0(r32) _BFGET_(r32,31, 0)
#define SET32smSysCtl_SM_DUMMY_REG_REG0(r32,v) _BFSET_(r32,31, 0,v)
#define w32smSysCtl_SM_DUMMY_REG {\
UNSG32 uSM_DUMMY_REG_REG0 : 32;\
}
union { UNSG32 u32smSysCtl_SM_DUMMY_REG;
struct w32smSysCtl_SM_DUMMY_REG;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_FEPHY_CTRL_ext_pwrdn_a(r32) _BFGET_(r32, 4, 0)
#define SET32smSysCtl_FEPHY_CTRL_ext_pwrdn_a(r32,v) _BFSET_(r32, 4, 0,v)
#define GET16smSysCtl_FEPHY_CTRL_ext_pwrdn_a(r16) _BFGET_(r16, 4, 0)
#define SET16smSysCtl_FEPHY_CTRL_ext_pwrdn_a(r16,v) _BFSET_(r16, 4, 0,v)
#define GET32smSysCtl_FEPHY_CTRL_pd_aneg_mode_a(r32) _BFGET_(r32, 7, 5)
#define SET32smSysCtl_FEPHY_CTRL_pd_aneg_mode_a(r32,v) _BFSET_(r32, 7, 5,v)
#define GET16smSysCtl_FEPHY_CTRL_pd_aneg_mode_a(r16) _BFGET_(r16, 7, 5)
#define SET16smSysCtl_FEPHY_CTRL_pd_aneg_mode_a(r16,v) _BFSET_(r16, 7, 5,v)
#define GET32smSysCtl_FEPHY_CTRL_pd_phyadr_a(r32) _BFGET_(r32,12, 8)
#define SET32smSysCtl_FEPHY_CTRL_pd_phyadr_a(r32,v) _BFSET_(r32,12, 8,v)
#define GET16smSysCtl_FEPHY_CTRL_pd_phyadr_a(r16) _BFGET_(r16,12, 8)
#define SET16smSysCtl_FEPHY_CTRL_pd_phyadr_a(r16,v) _BFSET_(r16,12, 8,v)
#define GET32smSysCtl_FEPHY_CTRL_pd_led_config_a(r32) _BFGET_(r32,15,13)
#define SET32smSysCtl_FEPHY_CTRL_pd_led_config_a(r32,v) _BFSET_(r32,15,13,v)
#define GET16smSysCtl_FEPHY_CTRL_pd_led_config_a(r16) _BFGET_(r16,15,13)
#define SET16smSysCtl_FEPHY_CTRL_pd_led_config_a(r16,v) _BFSET_(r16,15,13,v)
#define GET32smSysCtl_FEPHY_CTRL_yy_pecl_sdet_a(r32) _BFGET_(r32,20,16)
#define SET32smSysCtl_FEPHY_CTRL_yy_pecl_sdet_a(r32,v) _BFSET_(r32,20,16,v)
#define GET16smSysCtl_FEPHY_CTRL_yy_pecl_sdet_a(r16) _BFGET_(r16, 4, 0)
#define SET16smSysCtl_FEPHY_CTRL_yy_pecl_sdet_a(r16,v) _BFSET_(r16, 4, 0,v)
#define GET32smSysCtl_FEPHY_CTRL_ps_en_eee10t_s(r32) _BFGET_(r32,21,21)
#define SET32smSysCtl_FEPHY_CTRL_ps_en_eee10t_s(r32,v) _BFSET_(r32,21,21,v)
#define GET16smSysCtl_FEPHY_CTRL_ps_en_eee10t_s(r16) _BFGET_(r16, 5, 5)
#define SET16smSysCtl_FEPHY_CTRL_ps_en_eee10t_s(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32smSysCtl_FEPHY_CTRL_ps_en_eee100t_s(r32) _BFGET_(r32,22,22)
#define SET32smSysCtl_FEPHY_CTRL_ps_en_eee100t_s(r32,v) _BFSET_(r32,22,22,v)
#define GET16smSysCtl_FEPHY_CTRL_ps_en_eee100t_s(r16) _BFGET_(r16, 6, 6)
#define SET16smSysCtl_FEPHY_CTRL_ps_en_eee100t_s(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32smSysCtl_FEPHY_CTRL_pd_burnin_a(r32) _BFGET_(r32,23,23)
#define SET32smSysCtl_FEPHY_CTRL_pd_burnin_a(r32,v) _BFSET_(r32,23,23,v)
#define GET16smSysCtl_FEPHY_CTRL_pd_burnin_a(r16) _BFGET_(r16, 7, 7)
#define SET16smSysCtl_FEPHY_CTRL_pd_burnin_a(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32smSysCtl_FEPHY_CTRL_pd_ena_edet_a(r32) _BFGET_(r32,24,24)
#define SET32smSysCtl_FEPHY_CTRL_pd_ena_edet_a(r32,v) _BFSET_(r32,24,24,v)
#define GET16smSysCtl_FEPHY_CTRL_pd_ena_edet_a(r16) _BFGET_(r16, 8, 8)
#define SET16smSysCtl_FEPHY_CTRL_pd_ena_edet_a(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32smSysCtl_FEPHY_CTRL_pd_ena_xc_a(r32) _BFGET_(r32,25,25)
#define SET32smSysCtl_FEPHY_CTRL_pd_ena_xc_a(r32,v) _BFSET_(r32,25,25,v)
#define GET16smSysCtl_FEPHY_CTRL_pd_ena_xc_a(r16) _BFGET_(r16, 9, 9)
#define SET16smSysCtl_FEPHY_CTRL_pd_ena_xc_a(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32smSysCtl_FEPHY_CTRL_ext_coma_a(r32) _BFGET_(r32,26,26)
#define SET32smSysCtl_FEPHY_CTRL_ext_coma_a(r32,v) _BFSET_(r32,26,26,v)
#define GET16smSysCtl_FEPHY_CTRL_ext_coma_a(r16) _BFGET_(r16,10,10)
#define SET16smSysCtl_FEPHY_CTRL_ext_coma_a(r16,v) _BFSET_(r16,10,10,v)
#define w32smSysCtl_FEPHY_CTRL {\
UNSG32 uFEPHY_CTRL_ext_pwrdn_a : 5;\
UNSG32 uFEPHY_CTRL_pd_aneg_mode_a : 3;\
UNSG32 uFEPHY_CTRL_pd_phyadr_a : 5;\
UNSG32 uFEPHY_CTRL_pd_led_config_a : 3;\
UNSG32 uFEPHY_CTRL_yy_pecl_sdet_a : 5;\
UNSG32 uFEPHY_CTRL_ps_en_eee10t_s : 1;\
UNSG32 uFEPHY_CTRL_ps_en_eee100t_s : 1;\
UNSG32 uFEPHY_CTRL_pd_burnin_a : 1;\
UNSG32 uFEPHY_CTRL_pd_ena_edet_a : 1;\
UNSG32 uFEPHY_CTRL_pd_ena_xc_a : 1;\
UNSG32 uFEPHY_CTRL_ext_coma_a : 1;\
UNSG32 RSVDx84_b27 : 5;\
}
union { UNSG32 u32smSysCtl_FEPHY_CTRL;
struct w32smSysCtl_FEPHY_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_FEPHY_STS_misc_speed_s(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_FEPHY_STS_misc_speed_s(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_FEPHY_STS_misc_speed_s(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_FEPHY_STS_misc_speed_s(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_FEPHY_STS_misc_duplex_s(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_FEPHY_STS_misc_duplex_s(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_FEPHY_STS_misc_duplex_s(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_FEPHY_STS_misc_duplex_s(r16,v) _BFSET_(r16, 1, 1,v)
#define GET32smSysCtl_FEPHY_STS_misc_hcd_resolved_s(r32) _BFGET_(r32, 2, 2)
#define SET32smSysCtl_FEPHY_STS_misc_hcd_resolved_s(r32,v) _BFSET_(r32, 2, 2,v)
#define GET16smSysCtl_FEPHY_STS_misc_hcd_resolved_s(r16) _BFGET_(r16, 2, 2)
#define SET16smSysCtl_FEPHY_STS_misc_hcd_resolved_s(r16,v) _BFSET_(r16, 2, 2,v)
#define GET32smSysCtl_FEPHY_STS_misc_link_s(r32) _BFGET_(r32, 3, 3)
#define SET32smSysCtl_FEPHY_STS_misc_link_s(r32,v) _BFSET_(r32, 3, 3,v)
#define GET16smSysCtl_FEPHY_STS_misc_link_s(r16) _BFGET_(r16, 3, 3)
#define SET16smSysCtl_FEPHY_STS_misc_link_s(r16,v) _BFSET_(r16, 3, 3,v)
#define GET32smSysCtl_FEPHY_STS_misc_lpi_s(r32) _BFGET_(r32, 4, 4)
#define SET32smSysCtl_FEPHY_STS_misc_lpi_s(r32,v) _BFSET_(r32, 4, 4,v)
#define GET16smSysCtl_FEPHY_STS_misc_lpi_s(r16) _BFGET_(r16, 4, 4)
#define SET16smSysCtl_FEPHY_STS_misc_lpi_s(r16,v) _BFSET_(r16, 4, 4,v)
#define GET32smSysCtl_FEPHY_STS_misc_rx_lpi_s(r32) _BFGET_(r32, 5, 5)
#define SET32smSysCtl_FEPHY_STS_misc_rx_lpi_s(r32,v) _BFSET_(r32, 5, 5,v)
#define GET16smSysCtl_FEPHY_STS_misc_rx_lpi_s(r16) _BFGET_(r16, 5, 5)
#define SET16smSysCtl_FEPHY_STS_misc_rx_lpi_s(r16,v) _BFSET_(r16, 5, 5,v)
#define GET32smSysCtl_FEPHY_STS_misc_pause_s(r32) _BFGET_(r32, 6, 6)
#define SET32smSysCtl_FEPHY_STS_misc_pause_s(r32,v) _BFSET_(r32, 6, 6,v)
#define GET16smSysCtl_FEPHY_STS_misc_pause_s(r16) _BFGET_(r16, 6, 6)
#define SET16smSysCtl_FEPHY_STS_misc_pause_s(r16,v) _BFSET_(r16, 6, 6,v)
#define GET32smSysCtl_FEPHY_STS_misc_lp_pause_s(r32) _BFGET_(r32, 7, 7)
#define SET32smSysCtl_FEPHY_STS_misc_lp_pause_s(r32,v) _BFSET_(r32, 7, 7,v)
#define GET16smSysCtl_FEPHY_STS_misc_lp_pause_s(r16) _BFGET_(r16, 7, 7)
#define SET16smSysCtl_FEPHY_STS_misc_lp_pause_s(r16,v) _BFSET_(r16, 7, 7,v)
#define GET32smSysCtl_FEPHY_STS_misc_int_s(r32) _BFGET_(r32, 8, 8)
#define SET32smSysCtl_FEPHY_STS_misc_int_s(r32,v) _BFSET_(r32, 8, 8,v)
#define GET16smSysCtl_FEPHY_STS_misc_int_s(r16) _BFGET_(r16, 8, 8)
#define SET16smSysCtl_FEPHY_STS_misc_int_s(r16,v) _BFSET_(r16, 8, 8,v)
#define GET32smSysCtl_FEPHY_STS_misc_edet_status_s(r32) _BFGET_(r32, 9, 9)
#define SET32smSysCtl_FEPHY_STS_misc_edet_status_s(r32,v) _BFSET_(r32, 9, 9,v)
#define GET16smSysCtl_FEPHY_STS_misc_edet_status_s(r16) _BFGET_(r16, 9, 9)
#define SET16smSysCtl_FEPHY_STS_misc_edet_status_s(r16,v) _BFSET_(r16, 9, 9,v)
#define GET32smSysCtl_FEPHY_STS_tx_latency_mark_a(r32) _BFGET_(r32,10,10)
#define SET32smSysCtl_FEPHY_STS_tx_latency_mark_a(r32,v) _BFSET_(r32,10,10,v)
#define GET16smSysCtl_FEPHY_STS_tx_latency_mark_a(r16) _BFGET_(r16,10,10)
#define SET16smSysCtl_FEPHY_STS_tx_latency_mark_a(r16,v) _BFSET_(r16,10,10,v)
#define GET32smSysCtl_FEPHY_STS_misc_por_reset(r32) _BFGET_(r32,11,11)
#define SET32smSysCtl_FEPHY_STS_misc_por_reset(r32,v) _BFSET_(r32,11,11,v)
#define GET16smSysCtl_FEPHY_STS_misc_por_reset(r16) _BFGET_(r16,11,11)
#define SET16smSysCtl_FEPHY_STS_misc_por_reset(r16,v) _BFSET_(r16,11,11,v)
#define w32smSysCtl_FEPHY_STS {\
UNSG32 uFEPHY_STS_misc_speed_s : 1;\
UNSG32 uFEPHY_STS_misc_duplex_s : 1;\
UNSG32 uFEPHY_STS_misc_hcd_resolved_s : 1;\
UNSG32 uFEPHY_STS_misc_link_s : 1;\
UNSG32 uFEPHY_STS_misc_lpi_s : 1;\
UNSG32 uFEPHY_STS_misc_rx_lpi_s : 1;\
UNSG32 uFEPHY_STS_misc_pause_s : 1;\
UNSG32 uFEPHY_STS_misc_lp_pause_s : 1;\
UNSG32 uFEPHY_STS_misc_int_s : 1;\
UNSG32 uFEPHY_STS_misc_edet_status_s : 1;\
UNSG32 uFEPHY_STS_tx_latency_mark_a : 1;\
UNSG32 uFEPHY_STS_misc_por_reset : 1;\
UNSG32 RSVDx88_b12 : 20;\
}
union { UNSG32 u32smSysCtl_FEPHY_STS;
struct w32smSysCtl_FEPHY_STS;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SRAM_PWR_CTRL_sm_pwr_sram_pwr_ctl(r32) _BFGET_(r32, 2, 0)
#define SET32smSysCtl_SRAM_PWR_CTRL_sm_pwr_sram_pwr_ctl(r32,v) _BFSET_(r32, 2, 0,v)
#define GET16smSysCtl_SRAM_PWR_CTRL_sm_pwr_sram_pwr_ctl(r16) _BFGET_(r16, 2, 0)
#define SET16smSysCtl_SRAM_PWR_CTRL_sm_pwr_sram_pwr_ctl(r16,v) _BFSET_(r16, 2, 0,v)
#define w32smSysCtl_SRAM_PWR_CTRL {\
UNSG32 uSRAM_PWR_CTRL_sm_pwr_sram_pwr_ctl : 3;\
UNSG32 RSVDx8C_b3 : 29;\
}
union { UNSG32 u32smSysCtl_SRAM_PWR_CTRL;
struct w32smSysCtl_SRAM_PWR_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_POR_AVDD_BYPASS(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_POR_AVDD_BYPASS(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_POR_AVDD_BYPASS(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_POR_AVDD_BYPASS(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_SM_POR_AVDD_BYPASS_3P3(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_SM_POR_AVDD_BYPASS_3P3(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_SM_POR_AVDD_BYPASS_3P3(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_SM_POR_AVDD_BYPASS_3P3(r16,v) _BFSET_(r16, 1, 1,v)
#define w32smSysCtl_SM_POR_AVDD {\
UNSG32 uSM_POR_AVDD_BYPASS : 1;\
UNSG32 uSM_POR_AVDD_BYPASS_3P3 : 1;\
UNSG32 RSVDx90_b2 : 30;\
}
union { UNSG32 u32smSysCtl_SM_POR_AVDD;
struct w32smSysCtl_SM_POR_AVDD;
};
///////////////////////////////////////////////////////////
SIE_padRing ie_SM_GLOBAL_PADRING;
///////////////////////////////////////////////////////////
SIE_padRing ie_SM_GPIO_PADRING;
///////////////////////////////////////////////////////////
SIE_padRing ie_SM_I2C_PADRING;
///////////////////////////////////////////////////////////
#define GET32smSysCtl_DDC_PAD_CTRL_ZN_SM_TW2_SCL(r32) _BFGET_(r32, 2, 0)
#define SET32smSysCtl_DDC_PAD_CTRL_ZN_SM_TW2_SCL(r32,v) _BFSET_(r32, 2, 0,v)
#define GET16smSysCtl_DDC_PAD_CTRL_ZN_SM_TW2_SCL(r16) _BFGET_(r16, 2, 0)
#define SET16smSysCtl_DDC_PAD_CTRL_ZN_SM_TW2_SCL(r16,v) _BFSET_(r16, 2, 0,v)
#define GET32smSysCtl_DDC_PAD_CTRL_ZN_SM_TW2_SDA(r32) _BFGET_(r32, 5, 3)
#define SET32smSysCtl_DDC_PAD_CTRL_ZN_SM_TW2_SDA(r32,v) _BFSET_(r32, 5, 3,v)
#define GET16smSysCtl_DDC_PAD_CTRL_ZN_SM_TW2_SDA(r16) _BFGET_(r16, 5, 3)
#define SET16smSysCtl_DDC_PAD_CTRL_ZN_SM_TW2_SDA(r16,v) _BFSET_(r16, 5, 3,v)
#define GET32smSysCtl_DDC_PAD_CTRL_ZN_SM_TW3_SCL(r32) _BFGET_(r32, 8, 6)
#define SET32smSysCtl_DDC_PAD_CTRL_ZN_SM_TW3_SCL(r32,v) _BFSET_(r32, 8, 6,v)
#define GET16smSysCtl_DDC_PAD_CTRL_ZN_SM_TW3_SCL(r16) _BFGET_(r16, 8, 6)
#define SET16smSysCtl_DDC_PAD_CTRL_ZN_SM_TW3_SCL(r16,v) _BFSET_(r16, 8, 6,v)
#define GET32smSysCtl_DDC_PAD_CTRL_ZN_SM_TW3_SDA(r32) _BFGET_(r32,11, 9)
#define SET32smSysCtl_DDC_PAD_CTRL_ZN_SM_TW3_SDA(r32,v) _BFSET_(r32,11, 9,v)
#define GET16smSysCtl_DDC_PAD_CTRL_ZN_SM_TW3_SDA(r16) _BFGET_(r16,11, 9)
#define SET16smSysCtl_DDC_PAD_CTRL_ZN_SM_TW3_SDA(r16,v) _BFSET_(r16,11, 9,v)
#define GET32smSysCtl_DDC_PAD_CTRL_ZN_RX_EDDC_SCL(r32) _BFGET_(r32,14,12)
#define SET32smSysCtl_DDC_PAD_CTRL_ZN_RX_EDDC_SCL(r32,v) _BFSET_(r32,14,12,v)
#define GET16smSysCtl_DDC_PAD_CTRL_ZN_RX_EDDC_SCL(r16) _BFGET_(r16,14,12)
#define SET16smSysCtl_DDC_PAD_CTRL_ZN_RX_EDDC_SCL(r16,v) _BFSET_(r16,14,12,v)
#define GET32smSysCtl_DDC_PAD_CTRL_ZN_RX_EDDC_SDA(r32) _BFGET_(r32,17,15)
#define SET32smSysCtl_DDC_PAD_CTRL_ZN_RX_EDDC_SDA(r32,v) _BFSET_(r32,17,15,v)
#define w32smSysCtl_DDC_PAD_CTRL {\
UNSG32 uDDC_PAD_CTRL_ZN_SM_TW2_SCL : 3;\
UNSG32 uDDC_PAD_CTRL_ZN_SM_TW2_SDA : 3;\
UNSG32 uDDC_PAD_CTRL_ZN_SM_TW3_SCL : 3;\
UNSG32 uDDC_PAD_CTRL_ZN_SM_TW3_SDA : 3;\
UNSG32 uDDC_PAD_CTRL_ZN_RX_EDDC_SCL : 3;\
UNSG32 uDDC_PAD_CTRL_ZN_RX_EDDC_SDA : 3;\
UNSG32 RSVDxAC_b18 : 14;\
}
union { UNSG32 u32smSysCtl_DDC_PAD_CTRL;
struct w32smSysCtl_DDC_PAD_CTRL;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_PWR_OK_status(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_PWR_OK_status(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_PWR_OK_status(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_PWR_OK_status(r16,v) _BFSET_(r16, 0, 0,v)
#define w32smSysCtl_SM_PWR_OK {\
UNSG32 uSM_PWR_OK_status : 1;\
UNSG32 RSVDxB0_b1 : 31;\
}
union { UNSG32 u32smSysCtl_SM_PWR_OK;
struct w32smSysCtl_SM_PWR_OK;
};
///////////////////////////////////////////////////////////
UNSG8 RSVDxB4 [844];
///////////////////////////////////////////////////////////
SIE_EDID ie_EDID;
///////////////////////////////////////////////////////////
#define GET32smSysCtl_smPinMuxCntlBus_SM_URT0_TXD(r32) _BFGET_(r32, 2, 0)
#define SET32smSysCtl_smPinMuxCntlBus_SM_URT0_TXD(r32,v) _BFSET_(r32, 2, 0,v)
#define GET16smSysCtl_smPinMuxCntlBus_SM_URT0_TXD(r16) _BFGET_(r16, 2, 0)
#define SET16smSysCtl_smPinMuxCntlBus_SM_URT0_TXD(r16,v) _BFSET_(r16, 2, 0,v)
#define GET32smSysCtl_smPinMuxCntlBus_SM_URT0_RXD(r32) _BFGET_(r32, 5, 3)
#define SET32smSysCtl_smPinMuxCntlBus_SM_URT0_RXD(r32,v) _BFSET_(r32, 5, 3,v)
#define GET16smSysCtl_smPinMuxCntlBus_SM_URT0_RXD(r16) _BFGET_(r16, 5, 3)
#define SET16smSysCtl_smPinMuxCntlBus_SM_URT0_RXD(r16,v) _BFSET_(r16, 5, 3,v)
#define GET32smSysCtl_smPinMuxCntlBus_SM_URT1_TXD(r32) _BFGET_(r32, 8, 6)
#define SET32smSysCtl_smPinMuxCntlBus_SM_URT1_TXD(r32,v) _BFSET_(r32, 8, 6,v)
#define GET16smSysCtl_smPinMuxCntlBus_SM_URT1_TXD(r16) _BFGET_(r16, 8, 6)
#define SET16smSysCtl_smPinMuxCntlBus_SM_URT1_TXD(r16,v) _BFSET_(r16, 8, 6,v)
#define GET32smSysCtl_smPinMuxCntlBus_SM_URT1_RXD(r32) _BFGET_(r32,11, 9)
#define SET32smSysCtl_smPinMuxCntlBus_SM_URT1_RXD(r32,v) _BFSET_(r32,11, 9,v)
#define GET16smSysCtl_smPinMuxCntlBus_SM_URT1_RXD(r16) _BFGET_(r16,11, 9)
#define SET16smSysCtl_smPinMuxCntlBus_SM_URT1_RXD(r16,v) _BFSET_(r16,11, 9,v)
#define GET32smSysCtl_smPinMuxCntlBus_SM_SPI2_SS0n(r32) _BFGET_(r32,14,12)
#define SET32smSysCtl_smPinMuxCntlBus_SM_SPI2_SS0n(r32,v) _BFSET_(r32,14,12,v)
#define GET16smSysCtl_smPinMuxCntlBus_SM_SPI2_SS0n(r16) _BFGET_(r16,14,12)
#define SET16smSysCtl_smPinMuxCntlBus_SM_SPI2_SS0n(r16,v) _BFSET_(r16,14,12,v)
#define GET32smSysCtl_smPinMuxCntlBus_SM_SPI2_SS1n(r32) _BFGET_(r32,17,15)
#define SET32smSysCtl_smPinMuxCntlBus_SM_SPI2_SS1n(r32,v) _BFSET_(r32,17,15,v)
#define GET32smSysCtl_smPinMuxCntlBus_SM_SPI2_SS2n(r32) _BFGET_(r32,20,18)
#define SET32smSysCtl_smPinMuxCntlBus_SM_SPI2_SS2n(r32,v) _BFSET_(r32,20,18,v)
#define GET16smSysCtl_smPinMuxCntlBus_SM_SPI2_SS2n(r16) _BFGET_(r16, 4, 2)
#define SET16smSysCtl_smPinMuxCntlBus_SM_SPI2_SS2n(r16,v) _BFSET_(r16, 4, 2,v)
#define GET32smSysCtl_smPinMuxCntlBus_SM_SPI2_SS3n(r32) _BFGET_(r32,23,21)
#define SET32smSysCtl_smPinMuxCntlBus_SM_SPI2_SS3n(r32,v) _BFSET_(r32,23,21,v)
#define GET16smSysCtl_smPinMuxCntlBus_SM_SPI2_SS3n(r16) _BFGET_(r16, 7, 5)
#define SET16smSysCtl_smPinMuxCntlBus_SM_SPI2_SS3n(r16,v) _BFSET_(r16, 7, 5,v)
#define GET32smSysCtl_smPinMuxCntlBus_SM_SPI2_SDO(r32) _BFGET_(r32,26,24)
#define SET32smSysCtl_smPinMuxCntlBus_SM_SPI2_SDO(r32,v) _BFSET_(r32,26,24,v)
#define GET16smSysCtl_smPinMuxCntlBus_SM_SPI2_SDO(r16) _BFGET_(r16,10, 8)
#define SET16smSysCtl_smPinMuxCntlBus_SM_SPI2_SDO(r16,v) _BFSET_(r16,10, 8,v)
#define GET32smSysCtl_smPinMuxCntlBus_SM_SPI2_SDI(r32) _BFGET_(r32,29,27)
#define SET32smSysCtl_smPinMuxCntlBus_SM_SPI2_SDI(r32,v) _BFSET_(r32,29,27,v)
#define GET16smSysCtl_smPinMuxCntlBus_SM_SPI2_SDI(r16) _BFGET_(r16,13,11)
#define SET16smSysCtl_smPinMuxCntlBus_SM_SPI2_SDI(r16,v) _BFSET_(r16,13,11,v)
#define w32smSysCtl_smPinMuxCntlBus {\
UNSG32 usmPinMuxCntlBus_SM_URT0_TXD : 3;\
UNSG32 usmPinMuxCntlBus_SM_URT0_RXD : 3;\
UNSG32 usmPinMuxCntlBus_SM_URT1_TXD : 3;\
UNSG32 usmPinMuxCntlBus_SM_URT1_RXD : 3;\
UNSG32 usmPinMuxCntlBus_SM_SPI2_SS0n : 3;\
UNSG32 usmPinMuxCntlBus_SM_SPI2_SS1n : 3;\
UNSG32 usmPinMuxCntlBus_SM_SPI2_SS2n : 3;\
UNSG32 usmPinMuxCntlBus_SM_SPI2_SS3n : 3;\
UNSG32 usmPinMuxCntlBus_SM_SPI2_SDO : 3;\
UNSG32 usmPinMuxCntlBus_SM_SPI2_SDI : 3;\
UNSG32 RSVDxC00_b30 : 2;\
}
union { UNSG32 u32smSysCtl_smPinMuxCntlBus;
struct w32smSysCtl_smPinMuxCntlBus;
};
#define GET32smSysCtl_smPinMuxCntlBus_SM_SPI2_SCLK(r32) _BFGET_(r32, 2, 0)
#define SET32smSysCtl_smPinMuxCntlBus_SM_SPI2_SCLK(r32,v) _BFSET_(r32, 2, 0,v)
#define GET16smSysCtl_smPinMuxCntlBus_SM_SPI2_SCLK(r16) _BFGET_(r16, 2, 0)
#define SET16smSysCtl_smPinMuxCntlBus_SM_SPI2_SCLK(r16,v) _BFSET_(r16, 2, 0,v)
#define GET32smSysCtl_smPinMuxCntlBus_SM_FE_LED0(r32) _BFGET_(r32, 5, 3)
#define SET32smSysCtl_smPinMuxCntlBus_SM_FE_LED0(r32,v) _BFSET_(r32, 5, 3,v)
#define GET16smSysCtl_smPinMuxCntlBus_SM_FE_LED0(r16) _BFGET_(r16, 5, 3)
#define SET16smSysCtl_smPinMuxCntlBus_SM_FE_LED0(r16,v) _BFSET_(r16, 5, 3,v)
#define GET32smSysCtl_smPinMuxCntlBus_SM_FE_LED1(r32) _BFGET_(r32, 8, 6)
#define SET32smSysCtl_smPinMuxCntlBus_SM_FE_LED1(r32,v) _BFSET_(r32, 8, 6,v)
#define GET16smSysCtl_smPinMuxCntlBus_SM_FE_LED1(r16) _BFGET_(r16, 8, 6)
#define SET16smSysCtl_smPinMuxCntlBus_SM_FE_LED1(r16,v) _BFSET_(r16, 8, 6,v)
#define GET32smSysCtl_smPinMuxCntlBus_SM_FE_LED2(r32) _BFGET_(r32,11, 9)
#define SET32smSysCtl_smPinMuxCntlBus_SM_FE_LED2(r32,v) _BFSET_(r32,11, 9,v)
#define GET16smSysCtl_smPinMuxCntlBus_SM_FE_LED2(r16) _BFGET_(r16,11, 9)
#define SET16smSysCtl_smPinMuxCntlBus_SM_FE_LED2(r16,v) _BFSET_(r16,11, 9,v)
#define GET32smSysCtl_smPinMuxCntlBus_SM_HDMI_HPD(r32) _BFGET_(r32,14,12)
#define SET32smSysCtl_smPinMuxCntlBus_SM_HDMI_HPD(r32,v) _BFSET_(r32,14,12,v)
#define GET16smSysCtl_smPinMuxCntlBus_SM_HDMI_HPD(r16) _BFGET_(r16,14,12)
#define SET16smSysCtl_smPinMuxCntlBus_SM_HDMI_HPD(r16,v) _BFSET_(r16,14,12,v)
#define GET32smSysCtl_smPinMuxCntlBus_SM_HDMI_CEC(r32) _BFGET_(r32,17,15)
#define SET32smSysCtl_smPinMuxCntlBus_SM_HDMI_CEC(r32,v) _BFSET_(r32,17,15,v)
#define GET32smSysCtl_smPinMuxCntlBus_SM_TW2_SCL(r32) _BFGET_(r32,20,18)
#define SET32smSysCtl_smPinMuxCntlBus_SM_TW2_SCL(r32,v) _BFSET_(r32,20,18,v)
#define GET16smSysCtl_smPinMuxCntlBus_SM_TW2_SCL(r16) _BFGET_(r16, 4, 2)
#define SET16smSysCtl_smPinMuxCntlBus_SM_TW2_SCL(r16,v) _BFSET_(r16, 4, 2,v)
#define GET32smSysCtl_smPinMuxCntlBus_SM_TW2_SDA(r32) _BFGET_(r32,23,21)
#define SET32smSysCtl_smPinMuxCntlBus_SM_TW2_SDA(r32,v) _BFSET_(r32,23,21,v)
#define GET16smSysCtl_smPinMuxCntlBus_SM_TW2_SDA(r16) _BFGET_(r16, 7, 5)
#define SET16smSysCtl_smPinMuxCntlBus_SM_TW2_SDA(r16,v) _BFSET_(r16, 7, 5,v)
#define GET32smSysCtl_smPinMuxCntlBus_SM_TW3_SCL(r32) _BFGET_(r32,26,24)
#define SET32smSysCtl_smPinMuxCntlBus_SM_TW3_SCL(r32,v) _BFSET_(r32,26,24,v)
#define GET16smSysCtl_smPinMuxCntlBus_SM_TW3_SCL(r16) _BFGET_(r16,10, 8)
#define SET16smSysCtl_smPinMuxCntlBus_SM_TW3_SCL(r16,v) _BFSET_(r16,10, 8,v)
#define GET32smSysCtl_smPinMuxCntlBus_SM_TW3_SDA(r32) _BFGET_(r32,29,27)
#define SET32smSysCtl_smPinMuxCntlBus_SM_TW3_SDA(r32,v) _BFSET_(r32,29,27,v)
#define GET16smSysCtl_smPinMuxCntlBus_SM_TW3_SDA(r16) _BFGET_(r16,13,11)
#define SET16smSysCtl_smPinMuxCntlBus_SM_TW3_SDA(r16,v) _BFSET_(r16,13,11,v)
#define w32smSysCtl_smPinMuxCntlBus1 {\
UNSG32 usmPinMuxCntlBus_SM_SPI2_SCLK : 3;\
UNSG32 usmPinMuxCntlBus_SM_FE_LED0 : 3;\
UNSG32 usmPinMuxCntlBus_SM_FE_LED1 : 3;\
UNSG32 usmPinMuxCntlBus_SM_FE_LED2 : 3;\
UNSG32 usmPinMuxCntlBus_SM_HDMI_HPD : 3;\
UNSG32 usmPinMuxCntlBus_SM_HDMI_CEC : 3;\
UNSG32 usmPinMuxCntlBus_SM_TW2_SCL : 3;\
UNSG32 usmPinMuxCntlBus_SM_TW2_SDA : 3;\
UNSG32 usmPinMuxCntlBus_SM_TW3_SCL : 3;\
UNSG32 usmPinMuxCntlBus_SM_TW3_SDA : 3;\
UNSG32 RSVDxC04_b30 : 2;\
}
union { UNSG32 u32smSysCtl_smPinMuxCntlBus1;
struct w32smSysCtl_smPinMuxCntlBus1;
};
#define GET32smSysCtl_smPinMuxCntlBus_SM_RX_EDDC_SCL(r32) _BFGET_(r32, 2, 0)
#define SET32smSysCtl_smPinMuxCntlBus_SM_RX_EDDC_SCL(r32,v) _BFSET_(r32, 2, 0,v)
#define GET16smSysCtl_smPinMuxCntlBus_SM_RX_EDDC_SCL(r16) _BFGET_(r16, 2, 0)
#define SET16smSysCtl_smPinMuxCntlBus_SM_RX_EDDC_SCL(r16,v) _BFSET_(r16, 2, 0,v)
#define GET32smSysCtl_smPinMuxCntlBus_SM_RX_EDDC_SDA(r32) _BFGET_(r32, 5, 3)
#define SET32smSysCtl_smPinMuxCntlBus_SM_RX_EDDC_SDA(r32,v) _BFSET_(r32, 5, 3,v)
#define GET16smSysCtl_smPinMuxCntlBus_SM_RX_EDDC_SDA(r16) _BFGET_(r16, 5, 3)
#define SET16smSysCtl_smPinMuxCntlBus_SM_RX_EDDC_SDA(r16,v) _BFSET_(r16, 5, 3,v)
#define GET32smSysCtl_smPinMuxCntlBus_SM_HDMIRX_HPD(r32) _BFGET_(r32, 8, 6)
#define SET32smSysCtl_smPinMuxCntlBus_SM_HDMIRX_HPD(r32,v) _BFSET_(r32, 8, 6,v)
#define GET16smSysCtl_smPinMuxCntlBus_SM_HDMIRX_HPD(r16) _BFGET_(r16, 8, 6)
#define SET16smSysCtl_smPinMuxCntlBus_SM_HDMIRX_HPD(r16,v) _BFSET_(r16, 8, 6,v)
#define GET32smSysCtl_smPinMuxCntlBus_SM_TMS(r32) _BFGET_(r32,11, 9)
#define SET32smSysCtl_smPinMuxCntlBus_SM_TMS(r32,v) _BFSET_(r32,11, 9,v)
#define GET16smSysCtl_smPinMuxCntlBus_SM_TMS(r16) _BFGET_(r16,11, 9)
#define SET16smSysCtl_smPinMuxCntlBus_SM_TMS(r16,v) _BFSET_(r16,11, 9,v)
#define GET32smSysCtl_smPinMuxCntlBus_SM_TDI(r32) _BFGET_(r32,14,12)
#define SET32smSysCtl_smPinMuxCntlBus_SM_TDI(r32,v) _BFSET_(r32,14,12,v)
#define GET16smSysCtl_smPinMuxCntlBus_SM_TDI(r16) _BFGET_(r16,14,12)
#define SET16smSysCtl_smPinMuxCntlBus_SM_TDI(r16,v) _BFSET_(r16,14,12,v)
#define GET32smSysCtl_smPinMuxCntlBus_SM_TDO(r32) _BFGET_(r32,17,15)
#define SET32smSysCtl_smPinMuxCntlBus_SM_TDO(r32,v) _BFSET_(r32,17,15,v)
#define w32smSysCtl_smPinMuxCntlBus2 {\
UNSG32 usmPinMuxCntlBus_SM_RX_EDDC_SCL : 3;\
UNSG32 usmPinMuxCntlBus_SM_RX_EDDC_SDA : 3;\
UNSG32 usmPinMuxCntlBus_SM_HDMIRX_HPD : 3;\
UNSG32 usmPinMuxCntlBus_SM_TMS : 3;\
UNSG32 usmPinMuxCntlBus_SM_TDI : 3;\
UNSG32 usmPinMuxCntlBus_SM_TDO : 3;\
UNSG32 RSVDxC08_b18 : 14;\
}
union { UNSG32 u32smSysCtl_smPinMuxCntlBus2;
struct w32smSysCtl_smPinMuxCntlBus2;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_URT0_TXDCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_URT0_TXDCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_URT0_TXDCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_URT0_TXDCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_SM_URT0_TXDCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_SM_URT0_TXDCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_SM_URT0_TXDCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_SM_URT0_TXDCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32smSysCtl_SM_URT0_TXDCntl {\
UNSG32 uSM_URT0_TXDCntl_PD_EN : 1;\
UNSG32 uSM_URT0_TXDCntl_PU_EN : 1;\
UNSG32 RSVDxC0C_b2 : 30;\
}
union { UNSG32 u32smSysCtl_SM_URT0_TXDCntl;
struct w32smSysCtl_SM_URT0_TXDCntl;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_URT0_RXDCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_URT0_RXDCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_URT0_RXDCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_URT0_RXDCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_SM_URT0_RXDCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_SM_URT0_RXDCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_SM_URT0_RXDCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_SM_URT0_RXDCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32smSysCtl_SM_URT0_RXDCntl {\
UNSG32 uSM_URT0_RXDCntl_PD_EN : 1;\
UNSG32 uSM_URT0_RXDCntl_PU_EN : 1;\
UNSG32 RSVDxC10_b2 : 30;\
}
union { UNSG32 u32smSysCtl_SM_URT0_RXDCntl;
struct w32smSysCtl_SM_URT0_RXDCntl;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_URT1_TXDCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_URT1_TXDCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_URT1_TXDCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_URT1_TXDCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_SM_URT1_TXDCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_SM_URT1_TXDCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_SM_URT1_TXDCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_SM_URT1_TXDCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32smSysCtl_SM_URT1_TXDCntl {\
UNSG32 uSM_URT1_TXDCntl_PD_EN : 1;\
UNSG32 uSM_URT1_TXDCntl_PU_EN : 1;\
UNSG32 RSVDxC14_b2 : 30;\
}
union { UNSG32 u32smSysCtl_SM_URT1_TXDCntl;
struct w32smSysCtl_SM_URT1_TXDCntl;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_URT1_RXDCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_URT1_RXDCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_URT1_RXDCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_URT1_RXDCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_SM_URT1_RXDCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_SM_URT1_RXDCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_SM_URT1_RXDCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_SM_URT1_RXDCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32smSysCtl_SM_URT1_RXDCntl {\
UNSG32 uSM_URT1_RXDCntl_PD_EN : 1;\
UNSG32 uSM_URT1_RXDCntl_PU_EN : 1;\
UNSG32 RSVDxC18_b2 : 30;\
}
union { UNSG32 u32smSysCtl_SM_URT1_RXDCntl;
struct w32smSysCtl_SM_URT1_RXDCntl;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_SPI2_SS0nCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_SPI2_SS0nCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_SPI2_SS0nCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_SPI2_SS0nCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_SM_SPI2_SS0nCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_SM_SPI2_SS0nCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_SM_SPI2_SS0nCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_SM_SPI2_SS0nCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32smSysCtl_SM_SPI2_SS0nCntl {\
UNSG32 uSM_SPI2_SS0nCntl_PD_EN : 1;\
UNSG32 uSM_SPI2_SS0nCntl_PU_EN : 1;\
UNSG32 RSVDxC1C_b2 : 30;\
}
union { UNSG32 u32smSysCtl_SM_SPI2_SS0nCntl;
struct w32smSysCtl_SM_SPI2_SS0nCntl;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_SPI2_SS1nCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_SPI2_SS1nCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_SPI2_SS1nCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_SPI2_SS1nCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_SM_SPI2_SS1nCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_SM_SPI2_SS1nCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_SM_SPI2_SS1nCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_SM_SPI2_SS1nCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32smSysCtl_SM_SPI2_SS1nCntl {\
UNSG32 uSM_SPI2_SS1nCntl_PD_EN : 1;\
UNSG32 uSM_SPI2_SS1nCntl_PU_EN : 1;\
UNSG32 RSVDxC20_b2 : 30;\
}
union { UNSG32 u32smSysCtl_SM_SPI2_SS1nCntl;
struct w32smSysCtl_SM_SPI2_SS1nCntl;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_SPI2_SS2nCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_SPI2_SS2nCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_SPI2_SS2nCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_SPI2_SS2nCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_SM_SPI2_SS2nCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_SM_SPI2_SS2nCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_SM_SPI2_SS2nCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_SM_SPI2_SS2nCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32smSysCtl_SM_SPI2_SS2nCntl {\
UNSG32 uSM_SPI2_SS2nCntl_PD_EN : 1;\
UNSG32 uSM_SPI2_SS2nCntl_PU_EN : 1;\
UNSG32 RSVDxC24_b2 : 30;\
}
union { UNSG32 u32smSysCtl_SM_SPI2_SS2nCntl;
struct w32smSysCtl_SM_SPI2_SS2nCntl;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_SPI2_SS3nCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_SPI2_SS3nCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_SPI2_SS3nCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_SPI2_SS3nCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_SM_SPI2_SS3nCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_SM_SPI2_SS3nCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_SM_SPI2_SS3nCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_SM_SPI2_SS3nCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32smSysCtl_SM_SPI2_SS3nCntl {\
UNSG32 uSM_SPI2_SS3nCntl_PD_EN : 1;\
UNSG32 uSM_SPI2_SS3nCntl_PU_EN : 1;\
UNSG32 RSVDxC28_b2 : 30;\
}
union { UNSG32 u32smSysCtl_SM_SPI2_SS3nCntl;
struct w32smSysCtl_SM_SPI2_SS3nCntl;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_SPI2_SDOCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_SPI2_SDOCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_SPI2_SDOCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_SPI2_SDOCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_SM_SPI2_SDOCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_SM_SPI2_SDOCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_SM_SPI2_SDOCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_SM_SPI2_SDOCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32smSysCtl_SM_SPI2_SDOCntl {\
UNSG32 uSM_SPI2_SDOCntl_PD_EN : 1;\
UNSG32 uSM_SPI2_SDOCntl_PU_EN : 1;\
UNSG32 RSVDxC2C_b2 : 30;\
}
union { UNSG32 u32smSysCtl_SM_SPI2_SDOCntl;
struct w32smSysCtl_SM_SPI2_SDOCntl;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_SPI2_SDICntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_SPI2_SDICntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_SPI2_SDICntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_SPI2_SDICntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_SM_SPI2_SDICntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_SM_SPI2_SDICntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_SM_SPI2_SDICntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_SM_SPI2_SDICntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32smSysCtl_SM_SPI2_SDICntl {\
UNSG32 uSM_SPI2_SDICntl_PD_EN : 1;\
UNSG32 uSM_SPI2_SDICntl_PU_EN : 1;\
UNSG32 RSVDxC30_b2 : 30;\
}
union { UNSG32 u32smSysCtl_SM_SPI2_SDICntl;
struct w32smSysCtl_SM_SPI2_SDICntl;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_SPI2_SCLKCntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_SPI2_SCLKCntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_SPI2_SCLKCntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_SPI2_SCLKCntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_SM_SPI2_SCLKCntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_SM_SPI2_SCLKCntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_SM_SPI2_SCLKCntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_SM_SPI2_SCLKCntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32smSysCtl_SM_SPI2_SCLKCntl {\
UNSG32 uSM_SPI2_SCLKCntl_PD_EN : 1;\
UNSG32 uSM_SPI2_SCLKCntl_PU_EN : 1;\
UNSG32 RSVDxC34_b2 : 30;\
}
union { UNSG32 u32smSysCtl_SM_SPI2_SCLKCntl;
struct w32smSysCtl_SM_SPI2_SCLKCntl;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_FE_LED0Cntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_FE_LED0Cntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_FE_LED0Cntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_FE_LED0Cntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_SM_FE_LED0Cntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_SM_FE_LED0Cntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_SM_FE_LED0Cntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_SM_FE_LED0Cntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32smSysCtl_SM_FE_LED0Cntl {\
UNSG32 uSM_FE_LED0Cntl_PD_EN : 1;\
UNSG32 uSM_FE_LED0Cntl_PU_EN : 1;\
UNSG32 RSVDxC38_b2 : 30;\
}
union { UNSG32 u32smSysCtl_SM_FE_LED0Cntl;
struct w32smSysCtl_SM_FE_LED0Cntl;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_FE_LED1Cntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_FE_LED1Cntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_FE_LED1Cntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_FE_LED1Cntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_SM_FE_LED1Cntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_SM_FE_LED1Cntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_SM_FE_LED1Cntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_SM_FE_LED1Cntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32smSysCtl_SM_FE_LED1Cntl {\
UNSG32 uSM_FE_LED1Cntl_PD_EN : 1;\
UNSG32 uSM_FE_LED1Cntl_PU_EN : 1;\
UNSG32 RSVDxC3C_b2 : 30;\
}
union { UNSG32 u32smSysCtl_SM_FE_LED1Cntl;
struct w32smSysCtl_SM_FE_LED1Cntl;
};
///////////////////////////////////////////////////////////
#define GET32smSysCtl_SM_FE_LED2Cntl_PD_EN(r32) _BFGET_(r32, 0, 0)
#define SET32smSysCtl_SM_FE_LED2Cntl_PD_EN(r32,v) _BFSET_(r32, 0, 0,v)
#define GET16smSysCtl_SM_FE_LED2Cntl_PD_EN(r16) _BFGET_(r16, 0, 0)
#define SET16smSysCtl_SM_FE_LED2Cntl_PD_EN(r16,v) _BFSET_(r16, 0, 0,v)
#define GET32smSysCtl_SM_FE_LED2Cntl_PU_EN(r32) _BFGET_(r32, 1, 1)
#define SET32smSysCtl_SM_FE_LED2Cntl_PU_EN(r32,v) _BFSET_(r32, 1, 1,v)
#define GET16smSysCtl_SM_FE_LED2Cntl_PU_EN(r16) _BFGET_(r16, 1, 1)
#define SET16smSysCtl_SM_FE_LED2Cntl_PU_EN(r16,v) _BFSET_(r16, 1, 1,v)
#define w32smSysCtl_SM_FE_LED2Cntl {\
UNSG32 uSM_FE_LED2Cntl_PD_EN : 1;\
UNSG32 uSM_FE_LED2Cntl_PU_EN : 1;\
UNSG32 RSVDxC40_b2 : 30;\
}
union { UNSG32 u32smSysCtl_SM_FE_LED2Cntl;
struct w32smSysCtl_SM_FE_LED2Cntl;
};
///////////////////////////////////////////////////////////
UNSG8 RSVDxC44 [956];
///////////////////////////////////////////////////////////
} SIE_smSysCtl;
typedef union T32smSysCtl_SM_ID
{ UNSG32 u32;
struct w32smSysCtl_SM_ID;
} T32smSysCtl_SM_ID;
typedef union T32smSysCtl_SM_CPU_CTRL
{ UNSG32 u32;
struct w32smSysCtl_SM_CPU_CTRL;
} T32smSysCtl_SM_CPU_CTRL;
typedef union T32smSysCtl_SM_RST_CTRL
{ UNSG32 u32;
struct w32smSysCtl_SM_RST_CTRL;
} T32smSysCtl_SM_RST_CTRL;
typedef union T32smSysCtl_SM_RST_STATUS
{ UNSG32 u32;
struct w32smSysCtl_SM_RST_STATUS;
} T32smSysCtl_SM_RST_STATUS;
typedef union T32smSysCtl_SM_STRP_STATUS
{ UNSG32 u32;
struct w32smSysCtl_SM_STRP_STATUS;
} T32smSysCtl_SM_STRP_STATUS;
typedef union T32smSysCtl_SM_CTRL
{ UNSG32 u32;
struct w32smSysCtl_SM_CTRL;
} T32smSysCtl_SM_CTRL;
typedef union T32smSysCtl_SM_CTRL1
{ UNSG32 u32;
struct w32smSysCtl_SM_CTRL1;
} T32smSysCtl_SM_CTRL1;
typedef union T32smSysCtl_SM_ADC_CTRL
{ UNSG32 u32;
struct w32smSysCtl_SM_ADC_CTRL;
} T32smSysCtl_SM_ADC_CTRL;
typedef union T32smSysCtl_SM_ADC_STATUS
{ UNSG32 u32;
struct w32smSysCtl_SM_ADC_STATUS;
} T32smSysCtl_SM_ADC_STATUS;
typedef union T32smSysCtl_SM_ADC_DATA
{ UNSG32 u32;
struct w32smSysCtl_SM_ADC_DATA;
} T32smSysCtl_SM_ADC_DATA;
typedef union T32smSysCtl_TSEN_ADC_STATUS
{ UNSG32 u32;
struct w32smSysCtl_TSEN_ADC_STATUS;
} T32smSysCtl_TSEN_ADC_STATUS;
typedef union T32smSysCtl_TSEN_ADC_DATA
{ UNSG32 u32;
struct w32smSysCtl_TSEN_ADC_DATA;
} T32smSysCtl_TSEN_ADC_DATA;
typedef union T32smSysCtl_TSEN_CHK_CTRL
{ UNSG32 u32;
struct w32smSysCtl_TSEN_CHK_CTRL;
} T32smSysCtl_TSEN_CHK_CTRL;
typedef union T32smSysCtl_TSEN_DATA_STATUS
{ UNSG32 u32;
struct w32smSysCtl_TSEN_DATA_STATUS;
} T32smSysCtl_TSEN_DATA_STATUS;
typedef union T32smSysCtl_SM_BOOT_STATUS
{ UNSG32 u32;
struct w32smSysCtl_SM_BOOT_STATUS;
} T32smSysCtl_SM_BOOT_STATUS;
typedef union T32smSysCtl_SM_LDO_CTRL
{ UNSG32 u32;
struct w32smSysCtl_SM_LDO_CTRL;
} T32smSysCtl_SM_LDO_CTRL;
typedef union T32smSysCtl_SM_WDT_MASK
{ UNSG32 u32;
struct w32smSysCtl_SM_WDT_MASK;
} T32smSysCtl_SM_WDT_MASK;
typedef union T32smSysCtl_SM_CLK_CTRL
{ UNSG32 u32;
struct w32smSysCtl_SM_CLK_CTRL;
} T32smSysCtl_SM_CLK_CTRL;
typedef union T32smSysCtl_smAnaGrpCtl
{ UNSG32 u32;
struct w32smSysCtl_smAnaGrpCtl;
} T32smSysCtl_smAnaGrpCtl;
typedef union T32smSysCtl_smAnaGrpCtl1
{ UNSG32 u32;
struct w32smSysCtl_smAnaGrpCtl1;
} T32smSysCtl_smAnaGrpCtl1;
typedef union T32smSysCtl_POR_status
{ UNSG32 u32;
struct w32smSysCtl_POR_status;
} T32smSysCtl_POR_status;
typedef union T32smSysCtl_SM_CORE_CTRL
{ UNSG32 u32;
struct w32smSysCtl_SM_CORE_CTRL;
} T32smSysCtl_SM_CORE_CTRL;
typedef union T32smSysCtl_SM_TEST
{ UNSG32 u32;
struct w32smSysCtl_SM_TEST;
} T32smSysCtl_SM_TEST;
typedef union T32smSysCtl_SM_TEST_DATA0
{ UNSG32 u32;
struct w32smSysCtl_SM_TEST_DATA0;
} T32smSysCtl_SM_TEST_DATA0;
typedef union T32smSysCtl_SM_TEST_DATA1
{ UNSG32 u32;
struct w32smSysCtl_SM_TEST_DATA1;
} T32smSysCtl_SM_TEST_DATA1;
typedef union T32smSysCtl_SM_RWTC_CTRL_0
{ UNSG32 u32;
struct w32smSysCtl_SM_RWTC_CTRL_0;
} T32smSysCtl_SM_RWTC_CTRL_0;
typedef union T32smSysCtl_SM_RWTC_CTRL_1
{ UNSG32 u32;
struct w32smSysCtl_SM_RWTC_CTRL_1;
} T32smSysCtl_SM_RWTC_CTRL_1;
typedef union T32smSysCtl_SM_PORT_SEL_CTRL
{ UNSG32 u32;
struct w32smSysCtl_SM_PORT_SEL_CTRL;
} T32smSysCtl_SM_PORT_SEL_CTRL;
typedef union T32smSysCtl_TSEN_ADC_RAW_DATA
{ UNSG32 u32;
struct w32smSysCtl_TSEN_ADC_RAW_DATA;
} T32smSysCtl_TSEN_ADC_RAW_DATA;
typedef union T32smSysCtl_TSEN_ADC_CLK_DIV
{ UNSG32 u32;
struct w32smSysCtl_TSEN_ADC_CLK_DIV;
} T32smSysCtl_TSEN_ADC_CLK_DIV;
typedef union T32smSysCtl_TSEN_ADC_CTRL
{ UNSG32 u32;
struct w32smSysCtl_TSEN_ADC_CTRL;
} T32smSysCtl_TSEN_ADC_CTRL;
typedef union T32smSysCtl_TSEN_ADC_DBG
{ UNSG32 u32;
struct w32smSysCtl_TSEN_ADC_DBG;
} T32smSysCtl_TSEN_ADC_DBG;
typedef union T32smSysCtl_SM_DUMMY_REG
{ UNSG32 u32;
struct w32smSysCtl_SM_DUMMY_REG;
} T32smSysCtl_SM_DUMMY_REG;
typedef union T32smSysCtl_FEPHY_CTRL
{ UNSG32 u32;
struct w32smSysCtl_FEPHY_CTRL;
} T32smSysCtl_FEPHY_CTRL;
typedef union T32smSysCtl_FEPHY_STS
{ UNSG32 u32;
struct w32smSysCtl_FEPHY_STS;
} T32smSysCtl_FEPHY_STS;
typedef union T32smSysCtl_SRAM_PWR_CTRL
{ UNSG32 u32;
struct w32smSysCtl_SRAM_PWR_CTRL;
} T32smSysCtl_SRAM_PWR_CTRL;
typedef union T32smSysCtl_SM_POR_AVDD
{ UNSG32 u32;
struct w32smSysCtl_SM_POR_AVDD;
} T32smSysCtl_SM_POR_AVDD;
typedef union T32smSysCtl_DDC_PAD_CTRL
{ UNSG32 u32;
struct w32smSysCtl_DDC_PAD_CTRL;
} T32smSysCtl_DDC_PAD_CTRL;
typedef union T32smSysCtl_SM_PWR_OK
{ UNSG32 u32;
struct w32smSysCtl_SM_PWR_OK;
} T32smSysCtl_SM_PWR_OK;
typedef union T32smSysCtl_smPinMuxCntlBus
{ UNSG32 u32;
struct w32smSysCtl_smPinMuxCntlBus;
} T32smSysCtl_smPinMuxCntlBus;
typedef union T32smSysCtl_smPinMuxCntlBus1
{ UNSG32 u32;
struct w32smSysCtl_smPinMuxCntlBus1;
} T32smSysCtl_smPinMuxCntlBus1;
typedef union T32smSysCtl_smPinMuxCntlBus2
{ UNSG32 u32;
struct w32smSysCtl_smPinMuxCntlBus2;
} T32smSysCtl_smPinMuxCntlBus2;
typedef union T32smSysCtl_SM_URT0_TXDCntl
{ UNSG32 u32;
struct w32smSysCtl_SM_URT0_TXDCntl;
} T32smSysCtl_SM_URT0_TXDCntl;
typedef union T32smSysCtl_SM_URT0_RXDCntl
{ UNSG32 u32;
struct w32smSysCtl_SM_URT0_RXDCntl;
} T32smSysCtl_SM_URT0_RXDCntl;
typedef union T32smSysCtl_SM_URT1_TXDCntl
{ UNSG32 u32;
struct w32smSysCtl_SM_URT1_TXDCntl;
} T32smSysCtl_SM_URT1_TXDCntl;
typedef union T32smSysCtl_SM_URT1_RXDCntl
{ UNSG32 u32;
struct w32smSysCtl_SM_URT1_RXDCntl;
} T32smSysCtl_SM_URT1_RXDCntl;
typedef union T32smSysCtl_SM_SPI2_SS0nCntl
{ UNSG32 u32;
struct w32smSysCtl_SM_SPI2_SS0nCntl;
} T32smSysCtl_SM_SPI2_SS0nCntl;
typedef union T32smSysCtl_SM_SPI2_SS1nCntl
{ UNSG32 u32;
struct w32smSysCtl_SM_SPI2_SS1nCntl;
} T32smSysCtl_SM_SPI2_SS1nCntl;
typedef union T32smSysCtl_SM_SPI2_SS2nCntl
{ UNSG32 u32;
struct w32smSysCtl_SM_SPI2_SS2nCntl;
} T32smSysCtl_SM_SPI2_SS2nCntl;
typedef union T32smSysCtl_SM_SPI2_SS3nCntl
{ UNSG32 u32;
struct w32smSysCtl_SM_SPI2_SS3nCntl;
} T32smSysCtl_SM_SPI2_SS3nCntl;
typedef union T32smSysCtl_SM_SPI2_SDOCntl
{ UNSG32 u32;
struct w32smSysCtl_SM_SPI2_SDOCntl;
} T32smSysCtl_SM_SPI2_SDOCntl;
typedef union T32smSysCtl_SM_SPI2_SDICntl
{ UNSG32 u32;
struct w32smSysCtl_SM_SPI2_SDICntl;
} T32smSysCtl_SM_SPI2_SDICntl;
typedef union T32smSysCtl_SM_SPI2_SCLKCntl
{ UNSG32 u32;
struct w32smSysCtl_SM_SPI2_SCLKCntl;
} T32smSysCtl_SM_SPI2_SCLKCntl;
typedef union T32smSysCtl_SM_FE_LED0Cntl
{ UNSG32 u32;
struct w32smSysCtl_SM_FE_LED0Cntl;
} T32smSysCtl_SM_FE_LED0Cntl;
typedef union T32smSysCtl_SM_FE_LED1Cntl
{ UNSG32 u32;
struct w32smSysCtl_SM_FE_LED1Cntl;
} T32smSysCtl_SM_FE_LED1Cntl;
typedef union T32smSysCtl_SM_FE_LED2Cntl
{ UNSG32 u32;
struct w32smSysCtl_SM_FE_LED2Cntl;
} T32smSysCtl_SM_FE_LED2Cntl;
///////////////////////////////////////////////////////////
typedef union TsmSysCtl_SM_ID
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_ID;
};
} TsmSysCtl_SM_ID;
typedef union TsmSysCtl_SM_CPU_CTRL
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_CPU_CTRL;
};
} TsmSysCtl_SM_CPU_CTRL;
typedef union TsmSysCtl_SM_RST_CTRL
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_RST_CTRL;
};
} TsmSysCtl_SM_RST_CTRL;
typedef union TsmSysCtl_SM_RST_STATUS
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_RST_STATUS;
};
} TsmSysCtl_SM_RST_STATUS;
typedef union TsmSysCtl_SM_STRP_STATUS
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_STRP_STATUS;
};
} TsmSysCtl_SM_STRP_STATUS;
typedef union TsmSysCtl_SM_CTRL
{ UNSG32 u32[2];
struct {
struct w32smSysCtl_SM_CTRL;
struct w32smSysCtl_SM_CTRL1;
};
} TsmSysCtl_SM_CTRL;
typedef union TsmSysCtl_SM_ADC_CTRL
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_ADC_CTRL;
};
} TsmSysCtl_SM_ADC_CTRL;
typedef union TsmSysCtl_SM_ADC_STATUS
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_ADC_STATUS;
};
} TsmSysCtl_SM_ADC_STATUS;
typedef union TsmSysCtl_SM_ADC_DATA
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_ADC_DATA;
};
} TsmSysCtl_SM_ADC_DATA;
typedef union TsmSysCtl_TSEN_ADC_STATUS
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_TSEN_ADC_STATUS;
};
} TsmSysCtl_TSEN_ADC_STATUS;
typedef union TsmSysCtl_TSEN_ADC_DATA
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_TSEN_ADC_DATA;
};
} TsmSysCtl_TSEN_ADC_DATA;
typedef union TsmSysCtl_TSEN_CHK_CTRL
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_TSEN_CHK_CTRL;
};
} TsmSysCtl_TSEN_CHK_CTRL;
typedef union TsmSysCtl_TSEN_DATA_STATUS
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_TSEN_DATA_STATUS;
};
} TsmSysCtl_TSEN_DATA_STATUS;
typedef union TsmSysCtl_SM_BOOT_STATUS
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_BOOT_STATUS;
};
} TsmSysCtl_SM_BOOT_STATUS;
typedef union TsmSysCtl_SM_LDO_CTRL
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_LDO_CTRL;
};
} TsmSysCtl_SM_LDO_CTRL;
typedef union TsmSysCtl_SM_WDT_MASK
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_WDT_MASK;
};
} TsmSysCtl_SM_WDT_MASK;
typedef union TsmSysCtl_SM_CLK_CTRL
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_CLK_CTRL;
};
} TsmSysCtl_SM_CLK_CTRL;
typedef union TsmSysCtl_smAnaGrpCtl
{ UNSG32 u32[2];
struct {
struct w32smSysCtl_smAnaGrpCtl;
struct w32smSysCtl_smAnaGrpCtl1;
};
} TsmSysCtl_smAnaGrpCtl;
typedef union TsmSysCtl_POR_status
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_POR_status;
};
} TsmSysCtl_POR_status;
typedef union TsmSysCtl_SM_CORE_CTRL
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_CORE_CTRL;
};
} TsmSysCtl_SM_CORE_CTRL;
typedef union TsmSysCtl_SM_TEST
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_TEST;
};
} TsmSysCtl_SM_TEST;
typedef union TsmSysCtl_SM_TEST_DATA0
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_TEST_DATA0;
};
} TsmSysCtl_SM_TEST_DATA0;
typedef union TsmSysCtl_SM_TEST_DATA1
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_TEST_DATA1;
};
} TsmSysCtl_SM_TEST_DATA1;
typedef union TsmSysCtl_SM_RWTC_CTRL_0
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_RWTC_CTRL_0;
};
} TsmSysCtl_SM_RWTC_CTRL_0;
typedef union TsmSysCtl_SM_RWTC_CTRL_1
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_RWTC_CTRL_1;
};
} TsmSysCtl_SM_RWTC_CTRL_1;
typedef union TsmSysCtl_SM_PORT_SEL_CTRL
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_PORT_SEL_CTRL;
};
} TsmSysCtl_SM_PORT_SEL_CTRL;
typedef union TsmSysCtl_TSEN_ADC_RAW_DATA
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_TSEN_ADC_RAW_DATA;
};
} TsmSysCtl_TSEN_ADC_RAW_DATA;
typedef union TsmSysCtl_TSEN_ADC_CLK_DIV
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_TSEN_ADC_CLK_DIV;
};
} TsmSysCtl_TSEN_ADC_CLK_DIV;
typedef union TsmSysCtl_TSEN_ADC_CTRL
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_TSEN_ADC_CTRL;
};
} TsmSysCtl_TSEN_ADC_CTRL;
typedef union TsmSysCtl_TSEN_ADC_DBG
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_TSEN_ADC_DBG;
};
} TsmSysCtl_TSEN_ADC_DBG;
typedef union TsmSysCtl_SM_DUMMY_REG
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_DUMMY_REG;
};
} TsmSysCtl_SM_DUMMY_REG;
typedef union TsmSysCtl_FEPHY_CTRL
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_FEPHY_CTRL;
};
} TsmSysCtl_FEPHY_CTRL;
typedef union TsmSysCtl_FEPHY_STS
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_FEPHY_STS;
};
} TsmSysCtl_FEPHY_STS;
typedef union TsmSysCtl_SRAM_PWR_CTRL
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SRAM_PWR_CTRL;
};
} TsmSysCtl_SRAM_PWR_CTRL;
typedef union TsmSysCtl_SM_POR_AVDD
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_POR_AVDD;
};
} TsmSysCtl_SM_POR_AVDD;
typedef union TsmSysCtl_DDC_PAD_CTRL
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_DDC_PAD_CTRL;
};
} TsmSysCtl_DDC_PAD_CTRL;
typedef union TsmSysCtl_SM_PWR_OK
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_PWR_OK;
};
} TsmSysCtl_SM_PWR_OK;
typedef union TsmSysCtl_smPinMuxCntlBus
{ UNSG32 u32[3];
struct {
struct w32smSysCtl_smPinMuxCntlBus;
struct w32smSysCtl_smPinMuxCntlBus1;
struct w32smSysCtl_smPinMuxCntlBus2;
};
} TsmSysCtl_smPinMuxCntlBus;
typedef union TsmSysCtl_SM_URT0_TXDCntl
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_URT0_TXDCntl;
};
} TsmSysCtl_SM_URT0_TXDCntl;
typedef union TsmSysCtl_SM_URT0_RXDCntl
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_URT0_RXDCntl;
};
} TsmSysCtl_SM_URT0_RXDCntl;
typedef union TsmSysCtl_SM_URT1_TXDCntl
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_URT1_TXDCntl;
};
} TsmSysCtl_SM_URT1_TXDCntl;
typedef union TsmSysCtl_SM_URT1_RXDCntl
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_URT1_RXDCntl;
};
} TsmSysCtl_SM_URT1_RXDCntl;
typedef union TsmSysCtl_SM_SPI2_SS0nCntl
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_SPI2_SS0nCntl;
};
} TsmSysCtl_SM_SPI2_SS0nCntl;
typedef union TsmSysCtl_SM_SPI2_SS1nCntl
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_SPI2_SS1nCntl;
};
} TsmSysCtl_SM_SPI2_SS1nCntl;
typedef union TsmSysCtl_SM_SPI2_SS2nCntl
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_SPI2_SS2nCntl;
};
} TsmSysCtl_SM_SPI2_SS2nCntl;
typedef union TsmSysCtl_SM_SPI2_SS3nCntl
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_SPI2_SS3nCntl;
};
} TsmSysCtl_SM_SPI2_SS3nCntl;
typedef union TsmSysCtl_SM_SPI2_SDOCntl
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_SPI2_SDOCntl;
};
} TsmSysCtl_SM_SPI2_SDOCntl;
typedef union TsmSysCtl_SM_SPI2_SDICntl
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_SPI2_SDICntl;
};
} TsmSysCtl_SM_SPI2_SDICntl;
typedef union TsmSysCtl_SM_SPI2_SCLKCntl
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_SPI2_SCLKCntl;
};
} TsmSysCtl_SM_SPI2_SCLKCntl;
typedef union TsmSysCtl_SM_FE_LED0Cntl
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_FE_LED0Cntl;
};
} TsmSysCtl_SM_FE_LED0Cntl;
typedef union TsmSysCtl_SM_FE_LED1Cntl
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_FE_LED1Cntl;
};
} TsmSysCtl_SM_FE_LED1Cntl;
typedef union TsmSysCtl_SM_FE_LED2Cntl
{ UNSG32 u32[1];
struct {
struct w32smSysCtl_SM_FE_LED2Cntl;
};
} TsmSysCtl_SM_FE_LED2Cntl;
///////////////////////////////////////////////////////////
SIGN32 smSysCtl_drvrd(SIE_smSysCtl *p, UNSG32 base, SIGN32 mem, SIGN32 tst);
SIGN32 smSysCtl_drvwr(SIE_smSysCtl *p, UNSG32 base, SIGN32 mem, SIGN32 tst, UNSG32 *pcmd);
void smSysCtl_reset(SIE_smSysCtl *p);
SIGN32 smSysCtl_cmp (SIE_smSysCtl *p, SIE_smSysCtl *pie, char *pfx, void *hLOG, SIGN32 mem, SIGN32 tst);
#define smSysCtl_check(p,pie,pfx,hLOG) smSysCtl_cmp(p,pie,pfx,(void*)(hLOG),0,0)
#define smSysCtl_print(p, pfx,hLOG) smSysCtl_cmp(p,0, pfx,(void*)(hLOG),0,0)
#endif
//////
/// ENDOFINTERFACE: smSysCtl
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE SM_MEMMAP (4,4)
/// # # ----------------------------------------------------------
/// : ITCM_BASE 0x0
/// : ITCM_SIZE 0x20000
/// : ITCM_DEC_BIT 0x11
/// : DTCM_BASE 0x4000000
/// : DTCM_SIZE 0x20000
/// : DTCM_DEC_BIT 0x11
/// : SMAPB_BASE 0x10000000
/// : SMAPB_SIZE 0x10000
/// : SMAPB_DEC_BIT 0x10
/// : SSRAM_BASE 0x40000000
/// : SSRAM_SIZE 0x10000
/// : SSRAM_DEC_BIT 0x10
/// : WOL_BASE 0x10010000
/// : WOL_SIZE 0x1000
/// : WOL_DEC_BIT 0xC
/// : CEC_BASE 0x10011000
/// : CEC_SIZE 0x1000
/// : CEC_DEC_BIT 0xC
/// : SMREG_BASE 0x10012000
/// : SMREG_SIZE 0x1000
/// : SMREG_DEC_BIT 0xC
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 0B, bits: 0b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_SM_MEMMAP
#define h_SM_MEMMAP (){}
#define SM_MEMMAP_ITCM_BASE 0x0
#define SM_MEMMAP_ITCM_SIZE 0x20000
#define SM_MEMMAP_ITCM_DEC_BIT 0x11
#define SM_MEMMAP_DTCM_BASE 0x4000000
#define SM_MEMMAP_DTCM_SIZE 0x20000
#define SM_MEMMAP_DTCM_DEC_BIT 0x11
#define SM_MEMMAP_SMAPB_BASE 0x10000000
#define SM_MEMMAP_SMAPB_SIZE 0x10000
#define SM_MEMMAP_SMAPB_DEC_BIT 0x10
#define SM_MEMMAP_SSRAM_BASE 0x40000000
#define SM_MEMMAP_SSRAM_SIZE 0x10000
#define SM_MEMMAP_SSRAM_DEC_BIT 0x10
#define SM_MEMMAP_WOL_BASE 0x10010000
#define SM_MEMMAP_WOL_SIZE 0x1000
#define SM_MEMMAP_WOL_DEC_BIT 0xC
#define SM_MEMMAP_CEC_BASE 0x10011000
#define SM_MEMMAP_CEC_SIZE 0x1000
#define SM_MEMMAP_CEC_DEC_BIT 0xC
#define SM_MEMMAP_SMREG_BASE 0x10012000
#define SM_MEMMAP_SMREG_SIZE 0x1000
#define SM_MEMMAP_SMREG_DEC_BIT 0xC
///////////////////////////////////////////////////////////
#endif
//////
/// ENDOFINTERFACE: SM_MEMMAP
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE SM_IRQ (4,4)
/// # # ----------------------------------------------------------
/// : WDT_0 0x0
/// : WDT_1 0x1
/// : WDT_2 0x2
/// : RSVD0 0x3
/// : GPIO_1 0x4
/// : SSI 0x5
/// : I2C_0 0x6
/// : I2C_1 0x7
/// : UART_0 0x8
/// : UART_1 0x9
/// : RSVD1 0xA
/// : GPIO_0 0xB
/// : ADC 0xC
/// : SOC2SMSWInt 0xD
/// : TSEN 0xE
/// : WOL 0xF
/// : CEC 0x10
/// : FIFO_Intr_en 0x11
/// : ETH1_Int 0x12
/// : HPD 0x13
/// : HPD_INV 0x14
/// : Timer0_Intr0 0x15
/// : Timer1_Intr0 0x16
/// : Timer1_Intr1 0x17
/// : Timer1_Intr2 0x18
/// : Timer1_Intr3 0x19
/// : Timer1_Intr4 0x1A
/// : Timer1_Intr5 0x1B
/// : Timer1_Intr6 0x1C
/// : Timer1_Intr7 0x1D
/// : HDMIRXPWR5V 0x1E
/// : HDMIRXPWR5V_INV 0x1F
/// : EDID 0x20
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 0B, bits: 0b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_SM_IRQ
#define h_SM_IRQ (){}
#define SM_IRQ_WDT_0 0x0
#define SM_IRQ_WDT_1 0x1
#define SM_IRQ_WDT_2 0x2
#define SM_IRQ_RSVD0 0x3
#define SM_IRQ_GPIO_1 0x4
#define SM_IRQ_SSI 0x5
#define SM_IRQ_I2C_0 0x6
#define SM_IRQ_I2C_1 0x7
#define SM_IRQ_UART_0 0x8
#define SM_IRQ_UART_1 0x9
#define SM_IRQ_RSVD1 0xA
#define SM_IRQ_GPIO_0 0xB
#define SM_IRQ_ADC 0xC
#define SM_IRQ_SOC2SMSWInt 0xD
#define SM_IRQ_TSEN 0xE
#define SM_IRQ_WOL 0xF
#define SM_IRQ_CEC 0x10
#define SM_IRQ_FIFO_Intr_en 0x11
#define SM_IRQ_ETH1_Int 0x12
#define SM_IRQ_HPD 0x13
#define SM_IRQ_HPD_INV 0x14
#define SM_IRQ_Timer0_Intr0 0x15
#define SM_IRQ_Timer1_Intr0 0x16
#define SM_IRQ_Timer1_Intr1 0x17
#define SM_IRQ_Timer1_Intr2 0x18
#define SM_IRQ_Timer1_Intr3 0x19
#define SM_IRQ_Timer1_Intr4 0x1A
#define SM_IRQ_Timer1_Intr5 0x1B
#define SM_IRQ_Timer1_Intr6 0x1C
#define SM_IRQ_Timer1_Intr7 0x1D
#define SM_IRQ_HDMIRXPWR5V 0x1E
#define SM_IRQ_HDMIRXPWR5V_INV 0x1F
#define SM_IRQ_EDID 0x20
///////////////////////////////////////////////////////////
#endif
//////
/// ENDOFINTERFACE: SM_IRQ
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE SM_APB (4,4)
/// # # ----------------------------------------------------------
/// : ICTL_0 0x0
/// : ICTL_1 0x1000
/// : ICTL_2 0x2000
/// : WDT_0 0x3000
/// : WDT_1 0x4000
/// : WDT_2 0x5000
/// : Timer_0 0x6000
/// : Timer_1 0x7000
/// : GPIO_0 0x8000
/// : GPIO_1 0x9000
/// : SSI 0xA000
/// : I2C_0 0xB000
/// : I2C_1 0xC000
/// : UART_0 0xD000
/// : UART_1 0xE000
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 0B, bits: 0b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_SM_APB
#define h_SM_APB (){}
#define SM_APB_ICTL_0 0x0
#define SM_APB_ICTL_1 0x1000
#define SM_APB_ICTL_2 0x2000
#define SM_APB_WDT_0 0x3000
#define SM_APB_WDT_1 0x4000
#define SM_APB_WDT_2 0x5000
#define SM_APB_Timer_0 0x6000
#define SM_APB_Timer_1 0x7000
#define SM_APB_GPIO_0 0x8000
#define SM_APB_GPIO_1 0x9000
#define SM_APB_SSI 0xA000
#define SM_APB_I2C_0 0xB000
#define SM_APB_I2C_1 0xC000
#define SM_APB_UART_0 0xD000
#define SM_APB_UART_1 0xE000
///////////////////////////////////////////////////////////
#endif
//////
/// ENDOFINTERFACE: SM_APB
////////////////////////////////////////////////////////////
//////
///
/// $INTERFACE SOC_SM_MEMMAP (4,4)
/// # # ----------------------------------------------------------
/// : ITCM_BASE 0xF7F80000
/// : ITCM_SIZE 0x20000
/// : ITCM_DEC_BIT 0x11
/// : DTCM_BASE 0xF7FA0000
/// : DTCM_SIZE 0x20000
/// : DTCM_DEC_BIT 0x11
/// : SMAPB_BASE 0xF7FC0000
/// : SMAPB_SIZE 0x10000
/// : SMAPB_DEC_BIT 0x10
/// : SSRAM_BASE 0xF7FD0000
/// : SSRAM_SIZE 0x10000
/// : SSRAM_DEC_BIT 0x10
/// : WOL_BASE 0xF7FE0000
/// : WOL_SIZE 0x1000
/// : WOL_DEC_BIT 0xC
/// : CEC_BASE 0xF7FE1000
/// : CEC_SIZE 0x1000
/// : CEC_DEC_BIT 0xC
/// : SMREG_BASE 0xF7FE2000
/// : SMREG_SIZE 0x1000
/// : SMREG_DEC_BIT 0xC
/// # # ----------------------------------------------------------
/// $ENDOFINTERFACE # size: 0B, bits: 0b, padding: 0B
////////////////////////////////////////////////////////////
#ifndef h_SOC_SM_MEMMAP
#define h_SOC_SM_MEMMAP (){}
#define SOC_SM_MEMMAP_ITCM_BASE 0xF7F80000
#define SOC_SM_MEMMAP_ITCM_SIZE 0x20000
#define SOC_SM_MEMMAP_ITCM_DEC_BIT 0x11
#define SOC_SM_MEMMAP_DTCM_BASE 0xF7FA0000
#define SOC_SM_MEMMAP_DTCM_SIZE 0x20000
#define SOC_SM_MEMMAP_DTCM_DEC_BIT 0x11
#define SOC_SM_MEMMAP_SMAPB_BASE 0xF7FC0000
#define SOC_SM_MEMMAP_SMAPB_SIZE 0x10000
#define SOC_SM_MEMMAP_SMAPB_DEC_BIT 0x10
#define SOC_SM_MEMMAP_SSRAM_BASE 0xF7FD0000
#define SOC_SM_MEMMAP_SSRAM_SIZE 0x10000
#define SOC_SM_MEMMAP_SSRAM_DEC_BIT 0x10
#define SOC_SM_MEMMAP_WOL_BASE 0xF7FE0000
#define SOC_SM_MEMMAP_WOL_SIZE 0x1000
#define SOC_SM_MEMMAP_WOL_DEC_BIT 0xC
#define SOC_SM_MEMMAP_CEC_BASE 0xF7FE1000
#define SOC_SM_MEMMAP_CEC_SIZE 0x1000
#define SOC_SM_MEMMAP_CEC_DEC_BIT 0xC
#define SOC_SM_MEMMAP_SMREG_BASE 0xF7FE2000
#define SOC_SM_MEMMAP_SMREG_SIZE 0x1000
#define SOC_SM_MEMMAP_SMREG_DEC_BIT 0xC
///////////////////////////////////////////////////////////
#endif
//////
/// ENDOFINTERFACE: SOC_SM_MEMMAP
////////////////////////////////////////////////////////////
#ifdef __cplusplus
}
#endif
#pragma pack()
#endif
//////
/// ENDOFFILE: SysMgr.h
////////////////////////////////////////////////////////////