berlin_tools/bootloader/common/include/chip/as370/A0/hdmiRxPipe.h - manifest_repos/bootloader - Git at Google

 /*
  * Copyright Marvell Semiconductor, Inc. 2006. All rights reserved.
  *
  * Register address mapping configure file for rom testing code.
  */

 #ifndef	__hdmiRxPipe_H__
 #define	__hdmiRxPipe_H__

 	#define	RA_TG_PL_X                                     0x0000
 	#define	BA_TG_PL_X_start                               0x0000
 	#define	B16TG_PL_X_start                               0x0000
 	#define	LSb32TG_PL_X_start                                  0
 	#define	LSb16TG_PL_X_start                                  0
 	#define	bTG_PL_X_start                               13
 	#define	MSK32TG_PL_X_start                                  0x00001FFF
 	#define	BA_TG_PL_X_end                                 0x0001
 	#define	B16TG_PL_X_end                                 0x0000
 	#define	LSb32TG_PL_X_end                                    13
 	#define	LSb16TG_PL_X_end                                    13
 	#define	bTG_PL_X_end                                 13
 	#define	MSK32TG_PL_X_end                                    0x03FFE000
 	#define	RA_TG_PL_Y                                     0x0004
 	#define	BA_TG_PL_Y_start                               0x0004
 	#define	B16TG_PL_Y_start                               0x0004
 	#define	LSb32TG_PL_Y_start                                  0
 	#define	LSb16TG_PL_Y_start                                  0
 	#define	bTG_PL_Y_start                               12
 	#define	MSK32TG_PL_Y_start                                  0x00000FFF
 	#define	BA_TG_PL_Y_end                                 0x0005
 	#define	B16TG_PL_Y_end                                 0x0004
 	#define	LSb32TG_PL_Y_end                                    12
 	#define	LSb16TG_PL_Y_end                                    12
 	#define	bTG_PL_Y_end                                 12
 	#define	MSK32TG_PL_Y_end                                    0x00FFF000
 	#define	RA_TG_PRG_CTRL                                 0x0000
 	#define	BA_TG_PRG_CTRL_mode                            0x0000
 	#define	B16TG_PRG_CTRL_mode                            0x0000
 	#define	LSb32TG_PRG_CTRL_mode                               0
 	#define	LSb16TG_PRG_CTRL_mode                               0
 	#define	bTG_PRG_CTRL_mode                            2
 	#define	MSK32TG_PRG_CTRL_mode                               0x00000003
 	#define	BA_TG_PRG_CTRL_lwin                            0x0000
 	#define	B16TG_PRG_CTRL_lwin                            0x0000
 	#define	LSb32TG_PRG_CTRL_lwin                               2
 	#define	LSb16TG_PRG_CTRL_lwin                               2
 	#define	bTG_PRG_CTRL_lwin                            8
 	#define	MSK32TG_PRG_CTRL_lwin                               0x000003FC
 	#define	BA_TG_PRG_CTRL_frst                            0x0001
 	#define	B16TG_PRG_CTRL_frst                            0x0000
 	#define	LSb32TG_PRG_CTRL_frst                               10
 	#define	LSb16TG_PRG_CTRL_frst                               10
 	#define	bTG_PRG_CTRL_frst                            12
 	#define	MSK32TG_PRG_CTRL_frst                               0x003FFC00
 	#define	BA_TG_PRG_CTRL_freeze                          0x0002
 	#define	B16TG_PRG_CTRL_freeze                          0x0002
 	#define	LSb32TG_PRG_CTRL_freeze                             22
 	#define	LSb16TG_PRG_CTRL_freeze                             6
 	#define	bTG_PRG_CTRL_freeze                          10
 	#define	MSK32TG_PRG_CTRL_freeze                             0xFFC00000
 	#define	RA_TG_PRG_CTRL1                                0x0004
 	#define	BA_TG_PRG_CTRL1_sync_ctrl                      0x0004
 	#define	B16TG_PRG_CTRL1_sync_ctrl                      0x0004
 	#define	LSb32TG_PRG_CTRL1_sync_ctrl                         0
 	#define	LSb16TG_PRG_CTRL1_sync_ctrl                         0
 	#define	bTG_PRG_CTRL1_sync_ctrl                      2
 	#define	MSK32TG_PRG_CTRL1_sync_ctrl                         0x00000003
 	#define	BA_TG_PRG_CTRL1_res_change_en                  0x0004
 	#define	B16TG_PRG_CTRL1_res_change_en                  0x0004
 	#define	LSb32TG_PRG_CTRL1_res_change_en                     2
 	#define	LSb16TG_PRG_CTRL1_res_change_en                     2
 	#define	bTG_PRG_CTRL1_res_change_en                  9
 	#define	MSK32TG_PRG_CTRL1_res_change_en                     0x000007FC
 	#define	RA_TG_PRG_Total                                0x0008
 	#define	BA_TG_PRG_Total_vertical                       0x0008
 	#define	B16TG_PRG_Total_vertical                       0x0008
 	#define	LSb32TG_PRG_Total_vertical                          0
 	#define	LSb16TG_PRG_Total_vertical                          0
 	#define	bTG_PRG_Total_vertical                       12
 	#define	MSK32TG_PRG_Total_vertical                          0x00000FFF
 	#define	BA_TG_PRG_Total_horizontal                     0x0009
 	#define	B16TG_PRG_Total_horizontal                     0x0008
 	#define	LSb32TG_PRG_Total_horizontal                        12
 	#define	LSb16TG_PRG_Total_horizontal                        12
 	#define	bTG_PRG_Total_horizontal                     13
 	#define	MSK32TG_PRG_Total_horizontal                        0x01FFF000
 	#define	RA_TG_PRG_Initial                              0x000C
 	#define	BA_TG_PRG_Initial_xi                           0x000C
 	#define	B16TG_PRG_Initial_xi                           0x000C
 	#define	LSb32TG_PRG_Initial_xi                              0
 	#define	LSb16TG_PRG_Initial_xi                              0
 	#define	bTG_PRG_Initial_xi                           13
 	#define	MSK32TG_PRG_Initial_xi                              0x00001FFF
 	#define	BA_TG_PRG_Initial_yi                           0x000D
 	#define	B16TG_PRG_Initial_yi                           0x000C
 	#define	LSb32TG_PRG_Initial_yi                              13
 	#define	LSb16TG_PRG_Initial_yi                              13
 	#define	bTG_PRG_Initial_yi                           12
 	#define	MSK32TG_PRG_Initial_yi                              0x01FFE000
 	#define	RA_TG_PRG_HSYNC                                0x0010
 	#define	BA_TG_PRG_HSYNC_h_start                        0x0010
 	#define	B16TG_PRG_HSYNC_h_start                        0x0010
 	#define	LSb32TG_PRG_HSYNC_h_start                           0
 	#define	LSb16TG_PRG_HSYNC_h_start                           0
 	#define	bTG_PRG_HSYNC_h_start                        13
 	#define	MSK32TG_PRG_HSYNC_h_start                           0x00001FFF
 	#define	BA_TG_PRG_HSYNC_h_end                          0x0011
 	#define	B16TG_PRG_HSYNC_h_end                          0x0010
 	#define	LSb32TG_PRG_HSYNC_h_end                             13
 	#define	LSb16TG_PRG_HSYNC_h_end                             13
 	#define	bTG_PRG_HSYNC_h_end                          13
 	#define	MSK32TG_PRG_HSYNC_h_end                             0x03FFE000
 	#define	RA_TG_PRG_VSYNC                                0x0014
 	#define	BA_TG_PRG_VSYNC_v_start                        0x0014
 	#define	B16TG_PRG_VSYNC_v_start                        0x0014
 	#define	LSb32TG_PRG_VSYNC_v_start                           0
 	#define	LSb16TG_PRG_VSYNC_v_start                           0
 	#define	bTG_PRG_VSYNC_v_start                        12
 	#define	MSK32TG_PRG_VSYNC_v_start                           0x00000FFF
 	#define	BA_TG_PRG_VSYNC_v_end                          0x0015
 	#define	B16TG_PRG_VSYNC_v_end                          0x0014
 	#define	LSb32TG_PRG_VSYNC_v_end                             12
 	#define	LSb16TG_PRG_VSYNC_v_end                             12
 	#define	bTG_PRG_VSYNC_v_end                          12
 	#define	MSK32TG_PRG_VSYNC_v_end                             0x00FFF000
 	#define	RA_TG_PRG_VS                                   0x0018
 	#define	BA_TG_PRG_VS_h_start                           0x0018
 	#define	B16TG_PRG_VS_h_start                           0x0018
 	#define	LSb32TG_PRG_VS_h_start                              0
 	#define	LSb16TG_PRG_VS_h_start                              0
 	#define	bTG_PRG_VS_h_start                           13
 	#define	MSK32TG_PRG_VS_h_start                              0x00001FFF
 	#define	BA_TG_PRG_VS_h_end                             0x0019
 	#define	B16TG_PRG_VS_h_end                             0x0018
 	#define	LSb32TG_PRG_VS_h_end                                13
 	#define	LSb16TG_PRG_VS_h_end                                13
 	#define	bTG_PRG_VS_h_end                             13
 	#define	MSK32TG_PRG_VS_h_end                                0x03FFE000
 	#define	RA_TG_PRG_FT                                   0x001C
 	#define	BA_TG_PRG_FT_frame                             0x001C
 	#define	B16TG_PRG_FT_frame                             0x001C
 	#define	LSb32TG_PRG_FT_frame                                0
 	#define	LSb16TG_PRG_FT_frame                                0
 	#define	bTG_PRG_FT_frame                             8
 	#define	MSK32TG_PRG_FT_frame                                0x000000FF
 	#define	RA_TG_PRG_VX                                   0x0020
 	#define	BA_TG_PRG_VX_vx                                0x0020
 	#define	B16TG_PRG_VX_vx                                0x0020
 	#define	LSb32TG_PRG_VX_vx                                   0
 	#define	LSb16TG_PRG_VX_vx                                   0
 	#define	bTG_PRG_VX_vx                                13
 	#define	MSK32TG_PRG_VX_vx                                   0x00001FFF
 	#define	RA_TG_INIT                                     0x0000
 	#define	BA_TG_INIT_Y                                   0x0000
 	#define	B16TG_INIT_Y                                   0x0000
 	#define	LSb32TG_INIT_Y                                      0
 	#define	LSb16TG_INIT_Y                                      0
 	#define	bTG_INIT_Y                                   16
 	#define	MSK32TG_INIT_Y                                      0x0000FFFF
 	#define	BA_TG_INIT_X                                   0x0002
 	#define	B16TG_INIT_X                                   0x0002
 	#define	LSb32TG_INIT_X                                      16
 	#define	LSb16TG_INIT_X                                      0
 	#define	bTG_INIT_X                                   16
 	#define	MSK32TG_INIT_X                                      0xFFFF0000
 	#define	RA_TG_SIZE                                     0x0004
 	#define	BA_TG_SIZE_Y                                   0x0004
 	#define	B16TG_SIZE_Y                                   0x0004
 	#define	LSb32TG_SIZE_Y                                      0
 	#define	LSb16TG_SIZE_Y                                      0
 	#define	bTG_SIZE_Y                                   16
 	#define	MSK32TG_SIZE_Y                                      0x0000FFFF
 	#define	BA_TG_SIZE_X                                   0x0006
 	#define	B16TG_SIZE_X                                   0x0006
 	#define	LSb32TG_SIZE_X                                      16
 	#define	LSb16TG_SIZE_X                                      0
 	#define	bTG_SIZE_X                                   16
 	#define	MSK32TG_SIZE_X                                      0xFFFF0000
 	#define	RA_TG_HS                                       0x0008
 	#define	BA_TG_HS_FE                                    0x0008
 	#define	B16TG_HS_FE                                    0x0008
 	#define	LSb32TG_HS_FE                                       0
 	#define	LSb16TG_HS_FE                                       0
 	#define	bTG_HS_FE                                    16
 	#define	MSK32TG_HS_FE                                       0x0000FFFF
 	#define	BA_TG_HS_BE                                    0x000A
 	#define	B16TG_HS_BE                                    0x000A
 	#define	LSb32TG_HS_BE                                       16
 	#define	LSb16TG_HS_BE                                       0
 	#define	bTG_HS_BE                                    16
 	#define	MSK32TG_HS_BE                                       0xFFFF0000
 	#define	RA_TG_HB                                       0x000C
 	#define	BA_TG_HB_FE                                    0x000C
 	#define	B16TG_HB_FE                                    0x000C
 	#define	LSb32TG_HB_FE                                       0
 	#define	LSb16TG_HB_FE                                       0
 	#define	bTG_HB_FE                                    16
 	#define	MSK32TG_HB_FE                                       0x0000FFFF
 	#define	BA_TG_HB_BE                                    0x000E
 	#define	B16TG_HB_BE                                    0x000E
 	#define	LSb32TG_HB_BE                                       16
 	#define	LSb16TG_HB_BE                                       0
 	#define	bTG_HB_BE                                    16
 	#define	MSK32TG_HB_BE                                       0xFFFF0000
 	#define	RA_TG_HB_CR                                    0x0010
 	#define	BA_TG_HB_CR_FE                                 0x0010
 	#define	B16TG_HB_CR_FE                                 0x0010
 	#define	LSb32TG_HB_CR_FE                                    0
 	#define	LSb16TG_HB_CR_FE                                    0
 	#define	bTG_HB_CR_FE                                 16
 	#define	MSK32TG_HB_CR_FE                                    0x0000FFFF
 	#define	BA_TG_HB_CR_BE                                 0x0012
 	#define	B16TG_HB_CR_BE                                 0x0012
 	#define	LSb32TG_HB_CR_BE                                    16
 	#define	LSb16TG_HB_CR_BE                                    0
 	#define	bTG_HB_CR_BE                                 16
 	#define	MSK32TG_HB_CR_BE                                    0xFFFF0000
 	#define	RA_TG_HB_CR2                                   0x0014
 	#define	BA_TG_HB_CR2_FE                                0x0014
 	#define	B16TG_HB_CR2_FE                                0x0014
 	#define	LSb32TG_HB_CR2_FE                                   0
 	#define	LSb16TG_HB_CR2_FE                                   0
 	#define	bTG_HB_CR2_FE                                16
 	#define	MSK32TG_HB_CR2_FE                                   0x0000FFFF
 	#define	BA_TG_HB_CR2_BE                                0x0016
 	#define	B16TG_HB_CR2_BE                                0x0016
 	#define	LSb32TG_HB_CR2_BE                                   16
 	#define	LSb16TG_HB_CR2_BE                                   0
 	#define	bTG_HB_CR2_BE                                16
 	#define	MSK32TG_HB_CR2_BE                                   0xFFFF0000
 	#define	RA_TG_VS0                                      0x0018
 	#define	BA_TG_VS0_FE                                   0x0018
 	#define	B16TG_VS0_FE                                   0x0018
 	#define	LSb32TG_VS0_FE                                      0
 	#define	LSb16TG_VS0_FE                                      0
 	#define	bTG_VS0_FE                                   16
 	#define	MSK32TG_VS0_FE                                      0x0000FFFF
 	#define	BA_TG_VS0_BE                                   0x001A
 	#define	B16TG_VS0_BE                                   0x001A
 	#define	LSb32TG_VS0_BE                                      16
 	#define	LSb16TG_VS0_BE                                      0
 	#define	bTG_VS0_BE                                   16
 	#define	MSK32TG_VS0_BE                                      0xFFFF0000
 	#define	RA_TG_VS1                                      0x001C
 	#define	BA_TG_VS1_FE                                   0x001C
 	#define	B16TG_VS1_FE                                   0x001C
 	#define	LSb32TG_VS1_FE                                      0
 	#define	LSb16TG_VS1_FE                                      0
 	#define	bTG_VS1_FE                                   16
 	#define	MSK32TG_VS1_FE                                      0x0000FFFF
 	#define	BA_TG_VS1_BE                                   0x001E
 	#define	B16TG_VS1_BE                                   0x001E
 	#define	LSb32TG_VS1_BE                                      16
 	#define	LSb16TG_VS1_BE                                      0
 	#define	bTG_VS1_BE                                   16
 	#define	MSK32TG_VS1_BE                                      0xFFFF0000
 	#define	RA_TG_VB0                                      0x0020
 	#define	BA_TG_VB0_FE                                   0x0020
 	#define	B16TG_VB0_FE                                   0x0020
 	#define	LSb32TG_VB0_FE                                      0
 	#define	LSb16TG_VB0_FE                                      0
 	#define	bTG_VB0_FE                                   16
 	#define	MSK32TG_VB0_FE                                      0x0000FFFF
 	#define	BA_TG_VB0_BE                                   0x0022
 	#define	B16TG_VB0_BE                                   0x0022
 	#define	LSb32TG_VB0_BE                                      16
 	#define	LSb16TG_VB0_BE                                      0
 	#define	bTG_VB0_BE                                   16
 	#define	MSK32TG_VB0_BE                                      0xFFFF0000
 	#define	RA_TG_VB0_CR                                   0x0024
 	#define	BA_TG_VB0_CR_FE                                0x0024
 	#define	B16TG_VB0_CR_FE                                0x0024
 	#define	LSb32TG_VB0_CR_FE                                   0
 	#define	LSb16TG_VB0_CR_FE                                   0
 	#define	bTG_VB0_CR_FE                                16
 	#define	MSK32TG_VB0_CR_FE                                   0x0000FFFF
 	#define	BA_TG_VB0_CR_BE                                0x0026
 	#define	B16TG_VB0_CR_BE                                0x0026
 	#define	LSb32TG_VB0_CR_BE                                   16
 	#define	LSb16TG_VB0_CR_BE                                   0
 	#define	bTG_VB0_CR_BE                                16
 	#define	MSK32TG_VB0_CR_BE                                   0xFFFF0000
 	#define	RA_TG_VB0_CR2                                  0x0028
 	#define	BA_TG_VB0_CR2_FE                               0x0028
 	#define	B16TG_VB0_CR2_FE                               0x0028
 	#define	LSb32TG_VB0_CR2_FE                                  0
 	#define	LSb16TG_VB0_CR2_FE                                  0
 	#define	bTG_VB0_CR2_FE                               16
 	#define	MSK32TG_VB0_CR2_FE                                  0x0000FFFF
 	#define	BA_TG_VB0_CR2_BE                               0x002A
 	#define	B16TG_VB0_CR2_BE                               0x002A
 	#define	LSb32TG_VB0_CR2_BE                                  16
 	#define	LSb16TG_VB0_CR2_BE                                  0
 	#define	bTG_VB0_CR2_BE                               16
 	#define	MSK32TG_VB0_CR2_BE                                  0xFFFF0000
 	#define	RA_TG_VB1                                      0x002C
 	#define	BA_TG_VB1_FE                                   0x002C
 	#define	B16TG_VB1_FE                                   0x002C
 	#define	LSb32TG_VB1_FE                                      0
 	#define	LSb16TG_VB1_FE                                      0
 	#define	bTG_VB1_FE                                   16
 	#define	MSK32TG_VB1_FE                                      0x0000FFFF
 	#define	BA_TG_VB1_BE                                   0x002E
 	#define	B16TG_VB1_BE                                   0x002E
 	#define	LSb32TG_VB1_BE                                      16
 	#define	LSb16TG_VB1_BE                                      0
 	#define	bTG_VB1_BE                                   16
 	#define	MSK32TG_VB1_BE                                      0xFFFF0000
 	#define	RA_TG_SCAN                                     0x0030
 	#define	BA_TG_SCAN_MODE                                0x0030
 	#define	B16TG_SCAN_MODE                                0x0030
 	#define	LSb32TG_SCAN_MODE                                   0
 	#define	LSb16TG_SCAN_MODE                                   0
 	#define	bTG_SCAN_MODE                                1
 	#define	MSK32TG_SCAN_MODE                                   0x00000001
 	#define	TG_SCAN_MODE_PROG                                        0x0
 	#define	TG_SCAN_MODE_INTER                                       0x1
 	#define	RA_TG_INTPOS                                   0x0034
 	#define	BA_TG_INTPOS_FRAME                             0x0034
 	#define	B16TG_INTPOS_FRAME                             0x0034
 	#define	LSb32TG_INTPOS_FRAME                                0
 	#define	LSb16TG_INTPOS_FRAME                                0
 	#define	bTG_INTPOS_FRAME                             16
 	#define	MSK32TG_INTPOS_FRAME                                0x0000FFFF
 	#define	BA_TG_INTPOS_FIELD                             0x0036
 	#define	B16TG_INTPOS_FIELD                             0x0036
 	#define	LSb32TG_INTPOS_FIELD                                16
 	#define	LSb16TG_INTPOS_FIELD                                0
 	#define	bTG_INTPOS_FIELD                             16
 	#define	MSK32TG_INTPOS_FIELD                                0xFFFF0000
 	#define	RA_TG_MODE                                     0x0038
 	#define	BA_TG_MODE_EN                                  0x0038
 	#define	B16TG_MODE_EN                                  0x0038
 	#define	LSb32TG_MODE_EN                                     0
 	#define	LSb16TG_MODE_EN                                     0
 	#define	bTG_MODE_EN                                  1
 	#define	MSK32TG_MODE_EN                                     0x00000001
 	#define	TG_MODE_EN_MASTER                                        0x0
 	#define	TG_MODE_EN_SLAVE                                         0x1
 	#define	RA_TG_HVREF                                    0x003C
 	#define	BA_TG_HVREF_SEL                                0x003C
 	#define	B16TG_HVREF_SEL                                0x003C
 	#define	LSb32TG_HVREF_SEL                                   0
 	#define	LSb16TG_HVREF_SEL                                   0
 	#define	bTG_HVREF_SEL                                1
 	#define	MSK32TG_HVREF_SEL                                   0x00000001
 	#define	TG_HVREF_SEL_SYNC                                        0x0
 	#define	TG_HVREF_SEL_BLANK                                       0x1
 	#define	BA_TG_HVREF_POL                                0x003C
 	#define	B16TG_HVREF_POL                                0x003C
 	#define	LSb32TG_HVREF_POL                                   1
 	#define	LSb16TG_HVREF_POL                                   1
 	#define	bTG_HVREF_POL                                1
 	#define	MSK32TG_HVREF_POL                                   0x00000002
 	#define	TG_HVREF_POL_NEG_PULSE                                   0x0
 	#define	TG_HVREF_POL_POS_PULSE                                   0x1
 	#define	RA_BITMAP40_SEL                                0x0000
 	#define	BA_BITMAP40_SEL_BIT_POS0                       0x0000
 	#define	B16BITMAP40_SEL_BIT_POS0                       0x0000
 	#define	LSb32BITMAP40_SEL_BIT_POS0                          0
 	#define	LSb16BITMAP40_SEL_BIT_POS0                          0
 	#define	bBITMAP40_SEL_BIT_POS0                       6
 	#define	MSK32BITMAP40_SEL_BIT_POS0                          0x0000003F
 	#define	BA_BITMAP40_SEL_BIT_POS1                       0x0000
 	#define	B16BITMAP40_SEL_BIT_POS1                       0x0000
 	#define	LSb32BITMAP40_SEL_BIT_POS1                          6
 	#define	LSb16BITMAP40_SEL_BIT_POS1                          6
 	#define	bBITMAP40_SEL_BIT_POS1                       6
 	#define	MSK32BITMAP40_SEL_BIT_POS1                          0x00000FC0
 	#define	BA_BITMAP40_SEL_BIT_POS2                       0x0001
 	#define	B16BITMAP40_SEL_BIT_POS2                       0x0000
 	#define	LSb32BITMAP40_SEL_BIT_POS2                          12
 	#define	LSb16BITMAP40_SEL_BIT_POS2                          12
 	#define	bBITMAP40_SEL_BIT_POS2                       6
 	#define	MSK32BITMAP40_SEL_BIT_POS2                          0x0003F000
 	#define	BA_BITMAP40_SEL_BIT_POS3                       0x0002
 	#define	B16BITMAP40_SEL_BIT_POS3                       0x0002
 	#define	LSb32BITMAP40_SEL_BIT_POS3                          18
 	#define	LSb16BITMAP40_SEL_BIT_POS3                          2
 	#define	bBITMAP40_SEL_BIT_POS3                       6
 	#define	MSK32BITMAP40_SEL_BIT_POS3                          0x00FC0000
 	#define	BA_BITMAP40_SEL_BIT_POS4                       0x0003
 	#define	B16BITMAP40_SEL_BIT_POS4                       0x0002
 	#define	LSb32BITMAP40_SEL_BIT_POS4                          24
 	#define	LSb16BITMAP40_SEL_BIT_POS4                          8
 	#define	bBITMAP40_SEL_BIT_POS4                       6
 	#define	MSK32BITMAP40_SEL_BIT_POS4                          0x3F000000
 	#define	RA_BITMAP40_SEL1                               0x0004
 	#define	BA_BITMAP40_SEL_BIT_POS5                       0x0004
 	#define	B16BITMAP40_SEL_BIT_POS5                       0x0004
 	#define	LSb32BITMAP40_SEL_BIT_POS5                          0
 	#define	LSb16BITMAP40_SEL_BIT_POS5                          0
 	#define	bBITMAP40_SEL_BIT_POS5                       6
 	#define	MSK32BITMAP40_SEL_BIT_POS5                          0x0000003F
 	#define	BA_BITMAP40_SEL_BIT_POS6                       0x0004
 	#define	B16BITMAP40_SEL_BIT_POS6                       0x0004
 	#define	LSb32BITMAP40_SEL_BIT_POS6                          6
 	#define	LSb16BITMAP40_SEL_BIT_POS6                          6
 	#define	bBITMAP40_SEL_BIT_POS6                       6
 	#define	MSK32BITMAP40_SEL_BIT_POS6                          0x00000FC0
 	#define	BA_BITMAP40_SEL_BIT_POS7                       0x0005
 	#define	B16BITMAP40_SEL_BIT_POS7                       0x0004
 	#define	LSb32BITMAP40_SEL_BIT_POS7                          12
 	#define	LSb16BITMAP40_SEL_BIT_POS7                          12
 	#define	bBITMAP40_SEL_BIT_POS7                       6
 	#define	MSK32BITMAP40_SEL_BIT_POS7                          0x0003F000
 	#define	BA_BITMAP40_SEL_BIT_POS8                       0x0006
 	#define	B16BITMAP40_SEL_BIT_POS8                       0x0006
 	#define	LSb32BITMAP40_SEL_BIT_POS8                          18
 	#define	LSb16BITMAP40_SEL_BIT_POS8                          2
 	#define	bBITMAP40_SEL_BIT_POS8                       6
 	#define	MSK32BITMAP40_SEL_BIT_POS8                          0x00FC0000
 	#define	BA_BITMAP40_SEL_BIT_POS9                       0x0007
 	#define	B16BITMAP40_SEL_BIT_POS9                       0x0006
 	#define	LSb32BITMAP40_SEL_BIT_POS9                          24
 	#define	LSb16BITMAP40_SEL_BIT_POS9                          8
 	#define	bBITMAP40_SEL_BIT_POS9                       6
 	#define	MSK32BITMAP40_SEL_BIT_POS9                          0x3F000000
 	#define	RA_BITMAP40_SEL2                               0x0008
 	#define	BA_BITMAP40_SEL_BIT_POS10                      0x0008
 	#define	B16BITMAP40_SEL_BIT_POS10                      0x0008
 	#define	LSb32BITMAP40_SEL_BIT_POS10                         0
 	#define	LSb16BITMAP40_SEL_BIT_POS10                         0
 	#define	bBITMAP40_SEL_BIT_POS10                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS10                         0x0000003F
 	#define	BA_BITMAP40_SEL_BIT_POS11                      0x0008
 	#define	B16BITMAP40_SEL_BIT_POS11                      0x0008
 	#define	LSb32BITMAP40_SEL_BIT_POS11                         6
 	#define	LSb16BITMAP40_SEL_BIT_POS11                         6
 	#define	bBITMAP40_SEL_BIT_POS11                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS11                         0x00000FC0
 	#define	BA_BITMAP40_SEL_BIT_POS12                      0x0009
 	#define	B16BITMAP40_SEL_BIT_POS12                      0x0008
 	#define	LSb32BITMAP40_SEL_BIT_POS12                         12
 	#define	LSb16BITMAP40_SEL_BIT_POS12                         12
 	#define	bBITMAP40_SEL_BIT_POS12                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS12                         0x0003F000
 	#define	BA_BITMAP40_SEL_BIT_POS13                      0x000A
 	#define	B16BITMAP40_SEL_BIT_POS13                      0x000A
 	#define	LSb32BITMAP40_SEL_BIT_POS13                         18
 	#define	LSb16BITMAP40_SEL_BIT_POS13                         2
 	#define	bBITMAP40_SEL_BIT_POS13                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS13                         0x00FC0000
 	#define	BA_BITMAP40_SEL_BIT_POS14                      0x000B
 	#define	B16BITMAP40_SEL_BIT_POS14                      0x000A
 	#define	LSb32BITMAP40_SEL_BIT_POS14                         24
 	#define	LSb16BITMAP40_SEL_BIT_POS14                         8
 	#define	bBITMAP40_SEL_BIT_POS14                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS14                         0x3F000000
 	#define	RA_BITMAP40_SEL3                               0x000C
 	#define	BA_BITMAP40_SEL_BIT_POS15                      0x000C
 	#define	B16BITMAP40_SEL_BIT_POS15                      0x000C
 	#define	LSb32BITMAP40_SEL_BIT_POS15                         0
 	#define	LSb16BITMAP40_SEL_BIT_POS15                         0
 	#define	bBITMAP40_SEL_BIT_POS15                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS15                         0x0000003F
 	#define	BA_BITMAP40_SEL_BIT_POS16                      0x000C
 	#define	B16BITMAP40_SEL_BIT_POS16                      0x000C
 	#define	LSb32BITMAP40_SEL_BIT_POS16                         6
 	#define	LSb16BITMAP40_SEL_BIT_POS16                         6
 	#define	bBITMAP40_SEL_BIT_POS16                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS16                         0x00000FC0
 	#define	BA_BITMAP40_SEL_BIT_POS17                      0x000D
 	#define	B16BITMAP40_SEL_BIT_POS17                      0x000C
 	#define	LSb32BITMAP40_SEL_BIT_POS17                         12
 	#define	LSb16BITMAP40_SEL_BIT_POS17                         12
 	#define	bBITMAP40_SEL_BIT_POS17                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS17                         0x0003F000
 	#define	BA_BITMAP40_SEL_BIT_POS18                      0x000E
 	#define	B16BITMAP40_SEL_BIT_POS18                      0x000E
 	#define	LSb32BITMAP40_SEL_BIT_POS18                         18
 	#define	LSb16BITMAP40_SEL_BIT_POS18                         2
 	#define	bBITMAP40_SEL_BIT_POS18                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS18                         0x00FC0000
 	#define	BA_BITMAP40_SEL_BIT_POS19                      0x000F
 	#define	B16BITMAP40_SEL_BIT_POS19                      0x000E
 	#define	LSb32BITMAP40_SEL_BIT_POS19                         24
 	#define	LSb16BITMAP40_SEL_BIT_POS19                         8
 	#define	bBITMAP40_SEL_BIT_POS19                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS19                         0x3F000000
 	#define	RA_BITMAP40_SEL4                               0x0010
 	#define	BA_BITMAP40_SEL_BIT_POS20                      0x0010
 	#define	B16BITMAP40_SEL_BIT_POS20                      0x0010
 	#define	LSb32BITMAP40_SEL_BIT_POS20                         0
 	#define	LSb16BITMAP40_SEL_BIT_POS20                         0
 	#define	bBITMAP40_SEL_BIT_POS20                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS20                         0x0000003F
 	#define	BA_BITMAP40_SEL_BIT_POS21                      0x0010
 	#define	B16BITMAP40_SEL_BIT_POS21                      0x0010
 	#define	LSb32BITMAP40_SEL_BIT_POS21                         6
 	#define	LSb16BITMAP40_SEL_BIT_POS21                         6
 	#define	bBITMAP40_SEL_BIT_POS21                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS21                         0x00000FC0
 	#define	BA_BITMAP40_SEL_BIT_POS22                      0x0011
 	#define	B16BITMAP40_SEL_BIT_POS22                      0x0010
 	#define	LSb32BITMAP40_SEL_BIT_POS22                         12
 	#define	LSb16BITMAP40_SEL_BIT_POS22                         12
 	#define	bBITMAP40_SEL_BIT_POS22                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS22                         0x0003F000
 	#define	BA_BITMAP40_SEL_BIT_POS23                      0x0012
 	#define	B16BITMAP40_SEL_BIT_POS23                      0x0012
 	#define	LSb32BITMAP40_SEL_BIT_POS23                         18
 	#define	LSb16BITMAP40_SEL_BIT_POS23                         2
 	#define	bBITMAP40_SEL_BIT_POS23                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS23                         0x00FC0000
 	#define	BA_BITMAP40_SEL_BIT_POS24                      0x0013
 	#define	B16BITMAP40_SEL_BIT_POS24                      0x0012
 	#define	LSb32BITMAP40_SEL_BIT_POS24                         24
 	#define	LSb16BITMAP40_SEL_BIT_POS24                         8
 	#define	bBITMAP40_SEL_BIT_POS24                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS24                         0x3F000000
 	#define	RA_BITMAP40_SEL5                               0x0014
 	#define	BA_BITMAP40_SEL_BIT_POS25                      0x0014
 	#define	B16BITMAP40_SEL_BIT_POS25                      0x0014
 	#define	LSb32BITMAP40_SEL_BIT_POS25                         0
 	#define	LSb16BITMAP40_SEL_BIT_POS25                         0
 	#define	bBITMAP40_SEL_BIT_POS25                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS25                         0x0000003F
 	#define	BA_BITMAP40_SEL_BIT_POS26                      0x0014
 	#define	B16BITMAP40_SEL_BIT_POS26                      0x0014
 	#define	LSb32BITMAP40_SEL_BIT_POS26                         6
 	#define	LSb16BITMAP40_SEL_BIT_POS26                         6
 	#define	bBITMAP40_SEL_BIT_POS26                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS26                         0x00000FC0
 	#define	BA_BITMAP40_SEL_BIT_POS27                      0x0015
 	#define	B16BITMAP40_SEL_BIT_POS27                      0x0014
 	#define	LSb32BITMAP40_SEL_BIT_POS27                         12
 	#define	LSb16BITMAP40_SEL_BIT_POS27                         12
 	#define	bBITMAP40_SEL_BIT_POS27                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS27                         0x0003F000
 	#define	BA_BITMAP40_SEL_BIT_POS28                      0x0016
 	#define	B16BITMAP40_SEL_BIT_POS28                      0x0016
 	#define	LSb32BITMAP40_SEL_BIT_POS28                         18
 	#define	LSb16BITMAP40_SEL_BIT_POS28                         2
 	#define	bBITMAP40_SEL_BIT_POS28                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS28                         0x00FC0000
 	#define	BA_BITMAP40_SEL_BIT_POS29                      0x0017
 	#define	B16BITMAP40_SEL_BIT_POS29                      0x0016
 	#define	LSb32BITMAP40_SEL_BIT_POS29                         24
 	#define	LSb16BITMAP40_SEL_BIT_POS29                         8
 	#define	bBITMAP40_SEL_BIT_POS29                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS29                         0x3F000000
 	#define	RA_BITMAP40_SEL6                               0x0018
 	#define	BA_BITMAP40_SEL_BIT_POS30                      0x0018
 	#define	B16BITMAP40_SEL_BIT_POS30                      0x0018
 	#define	LSb32BITMAP40_SEL_BIT_POS30                         0
 	#define	LSb16BITMAP40_SEL_BIT_POS30                         0
 	#define	bBITMAP40_SEL_BIT_POS30                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS30                         0x0000003F
 	#define	BA_BITMAP40_SEL_BIT_POS31                      0x0018
 	#define	B16BITMAP40_SEL_BIT_POS31                      0x0018
 	#define	LSb32BITMAP40_SEL_BIT_POS31                         6
 	#define	LSb16BITMAP40_SEL_BIT_POS31                         6
 	#define	bBITMAP40_SEL_BIT_POS31                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS31                         0x00000FC0
 	#define	BA_BITMAP40_SEL_BIT_POS32                      0x0019
 	#define	B16BITMAP40_SEL_BIT_POS32                      0x0018
 	#define	LSb32BITMAP40_SEL_BIT_POS32                         12
 	#define	LSb16BITMAP40_SEL_BIT_POS32                         12
 	#define	bBITMAP40_SEL_BIT_POS32                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS32                         0x0003F000
 	#define	BA_BITMAP40_SEL_BIT_POS33                      0x001A
 	#define	B16BITMAP40_SEL_BIT_POS33                      0x001A
 	#define	LSb32BITMAP40_SEL_BIT_POS33                         18
 	#define	LSb16BITMAP40_SEL_BIT_POS33                         2
 	#define	bBITMAP40_SEL_BIT_POS33                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS33                         0x00FC0000
 	#define	BA_BITMAP40_SEL_BIT_POS34                      0x001B
 	#define	B16BITMAP40_SEL_BIT_POS34                      0x001A
 	#define	LSb32BITMAP40_SEL_BIT_POS34                         24
 	#define	LSb16BITMAP40_SEL_BIT_POS34                         8
 	#define	bBITMAP40_SEL_BIT_POS34                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS34                         0x3F000000
 	#define	RA_BITMAP40_SEL7                               0x001C
 	#define	BA_BITMAP40_SEL_BIT_POS35                      0x001C
 	#define	B16BITMAP40_SEL_BIT_POS35                      0x001C
 	#define	LSb32BITMAP40_SEL_BIT_POS35                         0
 	#define	LSb16BITMAP40_SEL_BIT_POS35                         0
 	#define	bBITMAP40_SEL_BIT_POS35                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS35                         0x0000003F
 	#define	BA_BITMAP40_SEL_BIT_POS36                      0x001C
 	#define	B16BITMAP40_SEL_BIT_POS36                      0x001C
 	#define	LSb32BITMAP40_SEL_BIT_POS36                         6
 	#define	LSb16BITMAP40_SEL_BIT_POS36                         6
 	#define	bBITMAP40_SEL_BIT_POS36                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS36                         0x00000FC0
 	#define	BA_BITMAP40_SEL_BIT_POS37                      0x001D
 	#define	B16BITMAP40_SEL_BIT_POS37                      0x001C
 	#define	LSb32BITMAP40_SEL_BIT_POS37                         12
 	#define	LSb16BITMAP40_SEL_BIT_POS37                         12
 	#define	bBITMAP40_SEL_BIT_POS37                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS37                         0x0003F000
 	#define	BA_BITMAP40_SEL_BIT_POS38                      0x001E
 	#define	B16BITMAP40_SEL_BIT_POS38                      0x001E
 	#define	LSb32BITMAP40_SEL_BIT_POS38                         18
 	#define	LSb16BITMAP40_SEL_BIT_POS38                         2
 	#define	bBITMAP40_SEL_BIT_POS38                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS38                         0x00FC0000
 	#define	BA_BITMAP40_SEL_BIT_POS39                      0x001F
 	#define	B16BITMAP40_SEL_BIT_POS39                      0x001E
 	#define	LSb32BITMAP40_SEL_BIT_POS39                         24
 	#define	LSb16BITMAP40_SEL_BIT_POS39                         8
 	#define	bBITMAP40_SEL_BIT_POS39                      6
 	#define	MSK32BITMAP40_SEL_BIT_POS39                         0x3F000000
 	#define	RA_BITMAP20_SEL                                0x0000
 	#define	BA_BITMAP20_SEL_BIT_POS0                       0x0000
 	#define	B16BITMAP20_SEL_BIT_POS0                       0x0000
 	#define	LSb32BITMAP20_SEL_BIT_POS0                          0
 	#define	LSb16BITMAP20_SEL_BIT_POS0                          0
 	#define	bBITMAP20_SEL_BIT_POS0                       5
 	#define	MSK32BITMAP20_SEL_BIT_POS0                          0x0000001F
 	#define	BA_BITMAP20_SEL_BIT_POS1                       0x0000
 	#define	B16BITMAP20_SEL_BIT_POS1                       0x0000
 	#define	LSb32BITMAP20_SEL_BIT_POS1                          5
 	#define	LSb16BITMAP20_SEL_BIT_POS1                          5
 	#define	bBITMAP20_SEL_BIT_POS1                       5
 	#define	MSK32BITMAP20_SEL_BIT_POS1                          0x000003E0
 	#define	BA_BITMAP20_SEL_BIT_POS2                       0x0001
 	#define	B16BITMAP20_SEL_BIT_POS2                       0x0000
 	#define	LSb32BITMAP20_SEL_BIT_POS2                          10
 	#define	LSb16BITMAP20_SEL_BIT_POS2                          10
 	#define	bBITMAP20_SEL_BIT_POS2                       5
 	#define	MSK32BITMAP20_SEL_BIT_POS2                          0x00007C00
 	#define	BA_BITMAP20_SEL_BIT_POS3                       0x0001
 	#define	B16BITMAP20_SEL_BIT_POS3                       0x0000
 	#define	LSb32BITMAP20_SEL_BIT_POS3                          15
 	#define	LSb16BITMAP20_SEL_BIT_POS3                          15
 	#define	bBITMAP20_SEL_BIT_POS3                       5
 	#define	MSK32BITMAP20_SEL_BIT_POS3                          0x000F8000
 	#define	BA_BITMAP20_SEL_BIT_POS4                       0x0002
 	#define	B16BITMAP20_SEL_BIT_POS4                       0x0002
 	#define	LSb32BITMAP20_SEL_BIT_POS4                          20
 	#define	LSb16BITMAP20_SEL_BIT_POS4                          4
 	#define	bBITMAP20_SEL_BIT_POS4                       5
 	#define	MSK32BITMAP20_SEL_BIT_POS4                          0x01F00000
 	#define	BA_BITMAP20_SEL_BIT_POS5                       0x0003
 	#define	B16BITMAP20_SEL_BIT_POS5                       0x0002
 	#define	LSb32BITMAP20_SEL_BIT_POS5                          25
 	#define	LSb16BITMAP20_SEL_BIT_POS5                          9
 	#define	bBITMAP20_SEL_BIT_POS5                       5
 	#define	MSK32BITMAP20_SEL_BIT_POS5                          0x3E000000
 	#define	RA_BITMAP20_SEL1                               0x0004
 	#define	BA_BITMAP20_SEL_BIT_POS6                       0x0004
 	#define	B16BITMAP20_SEL_BIT_POS6                       0x0004
 	#define	LSb32BITMAP20_SEL_BIT_POS6                          0
 	#define	LSb16BITMAP20_SEL_BIT_POS6                          0
 	#define	bBITMAP20_SEL_BIT_POS6                       5
 	#define	MSK32BITMAP20_SEL_BIT_POS6                          0x0000001F
 	#define	BA_BITMAP20_SEL_BIT_POS7                       0x0004
 	#define	B16BITMAP20_SEL_BIT_POS7                       0x0004
 	#define	LSb32BITMAP20_SEL_BIT_POS7                          5
 	#define	LSb16BITMAP20_SEL_BIT_POS7                          5
 	#define	bBITMAP20_SEL_BIT_POS7                       5
 	#define	MSK32BITMAP20_SEL_BIT_POS7                          0x000003E0
 	#define	BA_BITMAP20_SEL_BIT_POS8                       0x0005
 	#define	B16BITMAP20_SEL_BIT_POS8                       0x0004
 	#define	LSb32BITMAP20_SEL_BIT_POS8                          10
 	#define	LSb16BITMAP20_SEL_BIT_POS8                          10
 	#define	bBITMAP20_SEL_BIT_POS8                       5
 	#define	MSK32BITMAP20_SEL_BIT_POS8                          0x00007C00
 	#define	BA_BITMAP20_SEL_BIT_POS9                       0x0005
 	#define	B16BITMAP20_SEL_BIT_POS9                       0x0004
 	#define	LSb32BITMAP20_SEL_BIT_POS9                          15
 	#define	LSb16BITMAP20_SEL_BIT_POS9                          15
 	#define	bBITMAP20_SEL_BIT_POS9                       5
 	#define	MSK32BITMAP20_SEL_BIT_POS9                          0x000F8000
 	#define	BA_BITMAP20_SEL_BIT_POS10                      0x0006
 	#define	B16BITMAP20_SEL_BIT_POS10                      0x0006
 	#define	LSb32BITMAP20_SEL_BIT_POS10                         20
 	#define	LSb16BITMAP20_SEL_BIT_POS10                         4
 	#define	bBITMAP20_SEL_BIT_POS10                      5
 	#define	MSK32BITMAP20_SEL_BIT_POS10                         0x01F00000
 	#define	BA_BITMAP20_SEL_BIT_POS11                      0x0007
 	#define	B16BITMAP20_SEL_BIT_POS11                      0x0006
 	#define	LSb32BITMAP20_SEL_BIT_POS11                         25
 	#define	LSb16BITMAP20_SEL_BIT_POS11                         9
 	#define	bBITMAP20_SEL_BIT_POS11                      5
 	#define	MSK32BITMAP20_SEL_BIT_POS11                         0x3E000000
 	#define	RA_BITMAP20_SEL2                               0x0008
 	#define	BA_BITMAP20_SEL_BIT_POS12                      0x0008
 	#define	B16BITMAP20_SEL_BIT_POS12                      0x0008
 	#define	LSb32BITMAP20_SEL_BIT_POS12                         0
 	#define	LSb16BITMAP20_SEL_BIT_POS12                         0
 	#define	bBITMAP20_SEL_BIT_POS12                      5
 	#define	MSK32BITMAP20_SEL_BIT_POS12                         0x0000001F
 	#define	BA_BITMAP20_SEL_BIT_POS13                      0x0008
 	#define	B16BITMAP20_SEL_BIT_POS13                      0x0008
 	#define	LSb32BITMAP20_SEL_BIT_POS13                         5
 	#define	LSb16BITMAP20_SEL_BIT_POS13                         5
 	#define	bBITMAP20_SEL_BIT_POS13                      5
 	#define	MSK32BITMAP20_SEL_BIT_POS13                         0x000003E0
 	#define	BA_BITMAP20_SEL_BIT_POS14                      0x0009
 	#define	B16BITMAP20_SEL_BIT_POS14                      0x0008
 	#define	LSb32BITMAP20_SEL_BIT_POS14                         10
 	#define	LSb16BITMAP20_SEL_BIT_POS14                         10
 	#define	bBITMAP20_SEL_BIT_POS14                      5
 	#define	MSK32BITMAP20_SEL_BIT_POS14                         0x00007C00
 	#define	BA_BITMAP20_SEL_BIT_POS15                      0x0009
 	#define	B16BITMAP20_SEL_BIT_POS15                      0x0008
 	#define	LSb32BITMAP20_SEL_BIT_POS15                         15
 	#define	LSb16BITMAP20_SEL_BIT_POS15                         15
 	#define	bBITMAP20_SEL_BIT_POS15                      5
 	#define	MSK32BITMAP20_SEL_BIT_POS15                         0x000F8000
 	#define	BA_BITMAP20_SEL_BIT_POS16                      0x000A
 	#define	B16BITMAP20_SEL_BIT_POS16                      0x000A
 	#define	LSb32BITMAP20_SEL_BIT_POS16                         20
 	#define	LSb16BITMAP20_SEL_BIT_POS16                         4
 	#define	bBITMAP20_SEL_BIT_POS16                      5
 	#define	MSK32BITMAP20_SEL_BIT_POS16                         0x01F00000
 	#define	BA_BITMAP20_SEL_BIT_POS17                      0x000B
 	#define	B16BITMAP20_SEL_BIT_POS17                      0x000A
 	#define	LSb32BITMAP20_SEL_BIT_POS17                         25
 	#define	LSb16BITMAP20_SEL_BIT_POS17                         9
 	#define	bBITMAP20_SEL_BIT_POS17                      5
 	#define	MSK32BITMAP20_SEL_BIT_POS17                         0x3E000000
 	#define	RA_BITMAP20_SEL3                               0x000C
 	#define	BA_BITMAP20_SEL_BIT_POS18                      0x000C
 	#define	B16BITMAP20_SEL_BIT_POS18                      0x000C
 	#define	LSb32BITMAP20_SEL_BIT_POS18                         0
 	#define	LSb16BITMAP20_SEL_BIT_POS18                         0
 	#define	bBITMAP20_SEL_BIT_POS18                      5
 	#define	MSK32BITMAP20_SEL_BIT_POS18                         0x0000001F
 	#define	BA_BITMAP20_SEL_BIT_POS19                      0x000C
 	#define	B16BITMAP20_SEL_BIT_POS19                      0x000C
 	#define	LSb32BITMAP20_SEL_BIT_POS19                         5
 	#define	LSb16BITMAP20_SEL_BIT_POS19                         5
 	#define	bBITMAP20_SEL_BIT_POS19                      5
 	#define	MSK32BITMAP20_SEL_BIT_POS19                         0x000003E0
 	#define	RA_BITMAP32_SEL                                0x0000
 	#define	BA_BITMAP32_SEL_BIT_POS0                       0x0000
 	#define	B16BITMAP32_SEL_BIT_POS0                       0x0000
 	#define	LSb32BITMAP32_SEL_BIT_POS0                          0
 	#define	LSb16BITMAP32_SEL_BIT_POS0                          0
 	#define	bBITMAP32_SEL_BIT_POS0                       5
 	#define	MSK32BITMAP32_SEL_BIT_POS0                          0x0000001F
 	#define	BA_BITMAP32_SEL_BIT_POS1                       0x0000
 	#define	B16BITMAP32_SEL_BIT_POS1                       0x0000
 	#define	LSb32BITMAP32_SEL_BIT_POS1                          5
 	#define	LSb16BITMAP32_SEL_BIT_POS1                          5
 	#define	bBITMAP32_SEL_BIT_POS1                       5
 	#define	MSK32BITMAP32_SEL_BIT_POS1                          0x000003E0
 	#define	BA_BITMAP32_SEL_BIT_POS2                       0x0001
 	#define	B16BITMAP32_SEL_BIT_POS2                       0x0000
 	#define	LSb32BITMAP32_SEL_BIT_POS2                          10
 	#define	LSb16BITMAP32_SEL_BIT_POS2                          10
 	#define	bBITMAP32_SEL_BIT_POS2                       5
 	#define	MSK32BITMAP32_SEL_BIT_POS2                          0x00007C00
 	#define	BA_BITMAP32_SEL_BIT_POS3                       0x0001
 	#define	B16BITMAP32_SEL_BIT_POS3                       0x0000
 	#define	LSb32BITMAP32_SEL_BIT_POS3                          15
 	#define	LSb16BITMAP32_SEL_BIT_POS3                          15
 	#define	bBITMAP32_SEL_BIT_POS3                       5
 	#define	MSK32BITMAP32_SEL_BIT_POS3                          0x000F8000
 	#define	BA_BITMAP32_SEL_BIT_POS4                       0x0002
 	#define	B16BITMAP32_SEL_BIT_POS4                       0x0002
 	#define	LSb32BITMAP32_SEL_BIT_POS4                          20
 	#define	LSb16BITMAP32_SEL_BIT_POS4                          4
 	#define	bBITMAP32_SEL_BIT_POS4                       5
 	#define	MSK32BITMAP32_SEL_BIT_POS4                          0x01F00000
 	#define	BA_BITMAP32_SEL_BIT_POS5                       0x0003
 	#define	B16BITMAP32_SEL_BIT_POS5                       0x0002
 	#define	LSb32BITMAP32_SEL_BIT_POS5                          25
 	#define	LSb16BITMAP32_SEL_BIT_POS5                          9
 	#define	bBITMAP32_SEL_BIT_POS5                       5
 	#define	MSK32BITMAP32_SEL_BIT_POS5                          0x3E000000
 	#define	RA_BITMAP32_SEL1                               0x0004
 	#define	BA_BITMAP32_SEL_BIT_POS6                       0x0004
 	#define	B16BITMAP32_SEL_BIT_POS6                       0x0004
 	#define	LSb32BITMAP32_SEL_BIT_POS6                          0
 	#define	LSb16BITMAP32_SEL_BIT_POS6                          0
 	#define	bBITMAP32_SEL_BIT_POS6                       5
 	#define	MSK32BITMAP32_SEL_BIT_POS6                          0x0000001F
 	#define	BA_BITMAP32_SEL_BIT_POS7                       0x0004
 	#define	B16BITMAP32_SEL_BIT_POS7                       0x0004
 	#define	LSb32BITMAP32_SEL_BIT_POS7                          5
 	#define	LSb16BITMAP32_SEL_BIT_POS7                          5
 	#define	bBITMAP32_SEL_BIT_POS7                       5
 	#define	MSK32BITMAP32_SEL_BIT_POS7                          0x000003E0
 	#define	BA_BITMAP32_SEL_BIT_POS8                       0x0005
 	#define	B16BITMAP32_SEL_BIT_POS8                       0x0004
 	#define	LSb32BITMAP32_SEL_BIT_POS8                          10
 	#define	LSb16BITMAP32_SEL_BIT_POS8                          10
 	#define	bBITMAP32_SEL_BIT_POS8                       5
 	#define	MSK32BITMAP32_SEL_BIT_POS8                          0x00007C00
 	#define	BA_BITMAP32_SEL_BIT_POS9                       0x0005
 	#define	B16BITMAP32_SEL_BIT_POS9                       0x0004
 	#define	LSb32BITMAP32_SEL_BIT_POS9                          15
 	#define	LSb16BITMAP32_SEL_BIT_POS9                          15
 	#define	bBITMAP32_SEL_BIT_POS9                       5
 	#define	MSK32BITMAP32_SEL_BIT_POS9                          0x000F8000
 	#define	BA_BITMAP32_SEL_BIT_POS10                      0x0006
 	#define	B16BITMAP32_SEL_BIT_POS10                      0x0006
 	#define	LSb32BITMAP32_SEL_BIT_POS10                         20
 	#define	LSb16BITMAP32_SEL_BIT_POS10                         4
 	#define	bBITMAP32_SEL_BIT_POS10                      5
 	#define	MSK32BITMAP32_SEL_BIT_POS10                         0x01F00000
 	#define	BA_BITMAP32_SEL_BIT_POS11                      0x0007
 	#define	B16BITMAP32_SEL_BIT_POS11                      0x0006
 	#define	LSb32BITMAP32_SEL_BIT_POS11                         25
 	#define	LSb16BITMAP32_SEL_BIT_POS11                         9
 	#define	bBITMAP32_SEL_BIT_POS11                      5
 	#define	MSK32BITMAP32_SEL_BIT_POS11                         0x3E000000
 	#define	RA_BITMAP32_SEL2                               0x0008
 	#define	BA_BITMAP32_SEL_BIT_POS12                      0x0008
 	#define	B16BITMAP32_SEL_BIT_POS12                      0x0008
 	#define	LSb32BITMAP32_SEL_BIT_POS12                         0
 	#define	LSb16BITMAP32_SEL_BIT_POS12                         0
 	#define	bBITMAP32_SEL_BIT_POS12                      5
 	#define	MSK32BITMAP32_SEL_BIT_POS12                         0x0000001F
 	#define	BA_BITMAP32_SEL_BIT_POS13                      0x0008
 	#define	B16BITMAP32_SEL_BIT_POS13                      0x0008
 	#define	LSb32BITMAP32_SEL_BIT_POS13                         5
 	#define	LSb16BITMAP32_SEL_BIT_POS13                         5
 	#define	bBITMAP32_SEL_BIT_POS13                      5
 	#define	MSK32BITMAP32_SEL_BIT_POS13                         0x000003E0
 	#define	BA_BITMAP32_SEL_BIT_POS14                      0x0009
 	#define	B16BITMAP32_SEL_BIT_POS14                      0x0008
 	#define	LSb32BITMAP32_SEL_BIT_POS14                         10
 	#define	LSb16BITMAP32_SEL_BIT_POS14                         10
 	#define	bBITMAP32_SEL_BIT_POS14                      5
 	#define	MSK32BITMAP32_SEL_BIT_POS14                         0x00007C00
 	#define	BA_BITMAP32_SEL_BIT_POS15                      0x0009
 	#define	B16BITMAP32_SEL_BIT_POS15                      0x0008
 	#define	LSb32BITMAP32_SEL_BIT_POS15                         15
 	#define	LSb16BITMAP32_SEL_BIT_POS15                         15
 	#define	bBITMAP32_SEL_BIT_POS15                      5
 	#define	MSK32BITMAP32_SEL_BIT_POS15                         0x000F8000
 	#define	BA_BITMAP32_SEL_BIT_POS16                      0x000A
 	#define	B16BITMAP32_SEL_BIT_POS16                      0x000A
 	#define	LSb32BITMAP32_SEL_BIT_POS16                         20
 	#define	LSb16BITMAP32_SEL_BIT_POS16                         4
 	#define	bBITMAP32_SEL_BIT_POS16                      5
 	#define	MSK32BITMAP32_SEL_BIT_POS16                         0x01F00000
 	#define	BA_BITMAP32_SEL_BIT_POS17                      0x000B
 	#define	B16BITMAP32_SEL_BIT_POS17                      0x000A
 	#define	LSb32BITMAP32_SEL_BIT_POS17                         25
 	#define	LSb16BITMAP32_SEL_BIT_POS17                         9
 	#define	bBITMAP32_SEL_BIT_POS17                      5
 	#define	MSK32BITMAP32_SEL_BIT_POS17                         0x3E000000
 	#define	RA_BITMAP32_SEL3                               0x000C
 	#define	BA_BITMAP32_SEL_BIT_POS18                      0x000C
 	#define	B16BITMAP32_SEL_BIT_POS18                      0x000C
 	#define	LSb32BITMAP32_SEL_BIT_POS18                         0
 	#define	LSb16BITMAP32_SEL_BIT_POS18                         0
 	#define	bBITMAP32_SEL_BIT_POS18                      5
 	#define	MSK32BITMAP32_SEL_BIT_POS18                         0x0000001F
 	#define	BA_BITMAP32_SEL_BIT_POS19                      0x000C
 	#define	B16BITMAP32_SEL_BIT_POS19                      0x000C
 	#define	LSb32BITMAP32_SEL_BIT_POS19                         5
 	#define	LSb16BITMAP32_SEL_BIT_POS19                         5
 	#define	bBITMAP32_SEL_BIT_POS19                      5
 	#define	MSK32BITMAP32_SEL_BIT_POS19                         0x000003E0
 	#define	BA_BITMAP32_SEL_BIT_POS20                      0x000D
 	#define	B16BITMAP32_SEL_BIT_POS20                      0x000C
 	#define	LSb32BITMAP32_SEL_BIT_POS20                         10
 	#define	LSb16BITMAP32_SEL_BIT_POS20                         10
 	#define	bBITMAP32_SEL_BIT_POS20                      5
 	#define	MSK32BITMAP32_SEL_BIT_POS20                         0x00007C00
 	#define	BA_BITMAP32_SEL_BIT_POS21                      0x000D
 	#define	B16BITMAP32_SEL_BIT_POS21                      0x000C
 	#define	LSb32BITMAP32_SEL_BIT_POS21                         15
 	#define	LSb16BITMAP32_SEL_BIT_POS21                         15
 	#define	bBITMAP32_SEL_BIT_POS21                      5
 	#define	MSK32BITMAP32_SEL_BIT_POS21                         0x000F8000
 	#define	BA_BITMAP32_SEL_BIT_POS22                      0x000E
 	#define	B16BITMAP32_SEL_BIT_POS22                      0x000E
 	#define	LSb32BITMAP32_SEL_BIT_POS22                         20
 	#define	LSb16BITMAP32_SEL_BIT_POS22                         4
 	#define	bBITMAP32_SEL_BIT_POS22                      5
 	#define	MSK32BITMAP32_SEL_BIT_POS22                         0x01F00000
 	#define	BA_BITMAP32_SEL_BIT_POS23                      0x000F
 	#define	B16BITMAP32_SEL_BIT_POS23                      0x000E
 	#define	LSb32BITMAP32_SEL_BIT_POS23                         25
 	#define	LSb16BITMAP32_SEL_BIT_POS23                         9
 	#define	bBITMAP32_SEL_BIT_POS23                      5
 	#define	MSK32BITMAP32_SEL_BIT_POS23                         0x3E000000
 	#define	RA_BITMAP32_SEL4                               0x0010
 	#define	BA_BITMAP32_SEL_BIT_POS24                      0x0010
 	#define	B16BITMAP32_SEL_BIT_POS24                      0x0010
 	#define	LSb32BITMAP32_SEL_BIT_POS24                         0
 	#define	LSb16BITMAP32_SEL_BIT_POS24                         0
 	#define	bBITMAP32_SEL_BIT_POS24                      5
 	#define	MSK32BITMAP32_SEL_BIT_POS24                         0x0000001F
 	#define	BA_BITMAP32_SEL_BIT_POS25                      0x0010
 	#define	B16BITMAP32_SEL_BIT_POS25                      0x0010
 	#define	LSb32BITMAP32_SEL_BIT_POS25                         5
 	#define	LSb16BITMAP32_SEL_BIT_POS25                         5
 	#define	bBITMAP32_SEL_BIT_POS25                      5
 	#define	MSK32BITMAP32_SEL_BIT_POS25                         0x000003E0
 	#define	BA_BITMAP32_SEL_BIT_POS26                      0x0011
 	#define	B16BITMAP32_SEL_BIT_POS26                      0x0010
 	#define	LSb32BITMAP32_SEL_BIT_POS26                         10
 	#define	LSb16BITMAP32_SEL_BIT_POS26                         10
 	#define	bBITMAP32_SEL_BIT_POS26                      5
 	#define	MSK32BITMAP32_SEL_BIT_POS26                         0x00007C00
 	#define	BA_BITMAP32_SEL_BIT_POS27                      0x0011
 	#define	B16BITMAP32_SEL_BIT_POS27                      0x0010
 	#define	LSb32BITMAP32_SEL_BIT_POS27                         15
 	#define	LSb16BITMAP32_SEL_BIT_POS27                         15
 	#define	bBITMAP32_SEL_BIT_POS27                      5
 	#define	MSK32BITMAP32_SEL_BIT_POS27                         0x000F8000
 	#define	BA_BITMAP32_SEL_BIT_POS28                      0x0012
 	#define	B16BITMAP32_SEL_BIT_POS28                      0x0012
 	#define	LSb32BITMAP32_SEL_BIT_POS28                         20
 	#define	LSb16BITMAP32_SEL_BIT_POS28                         4
 	#define	bBITMAP32_SEL_BIT_POS28                      5
 	#define	MSK32BITMAP32_SEL_BIT_POS28                         0x01F00000
 	#define	BA_BITMAP32_SEL_BIT_POS29                      0x0013
 	#define	B16BITMAP32_SEL_BIT_POS29                      0x0012
 	#define	LSb32BITMAP32_SEL_BIT_POS29                         25
 	#define	LSb16BITMAP32_SEL_BIT_POS29                         9
 	#define	bBITMAP32_SEL_BIT_POS29                      5
 	#define	MSK32BITMAP32_SEL_BIT_POS29                         0x3E000000
 	#define	RA_BITMAP32_SEL5                               0x0014
 	#define	BA_BITMAP32_SEL_BIT_POS30                      0x0014
 	#define	B16BITMAP32_SEL_BIT_POS30                      0x0014
 	#define	LSb32BITMAP32_SEL_BIT_POS30                         0
 	#define	LSb16BITMAP32_SEL_BIT_POS30                         0
 	#define	bBITMAP32_SEL_BIT_POS30                      5
 	#define	MSK32BITMAP32_SEL_BIT_POS30                         0x0000001F
 	#define	BA_BITMAP32_SEL_BIT_POS31                      0x0014
 	#define	B16BITMAP32_SEL_BIT_POS31                      0x0014
 	#define	LSb32BITMAP32_SEL_BIT_POS31                         5
 	#define	LSb16BITMAP32_SEL_BIT_POS31                         5
 	#define	bBITMAP32_SEL_BIT_POS31                      5
 	#define	MSK32BITMAP32_SEL_BIT_POS31                         0x000003E0
 	#define	RA_BITMAP16_SEL                                0x0000
 	#define	BA_BITMAP16_SEL_BIT_POS0                       0x0000
 	#define	B16BITMAP16_SEL_BIT_POS0                       0x0000
 	#define	LSb32BITMAP16_SEL_BIT_POS0                          0
 	#define	LSb16BITMAP16_SEL_BIT_POS0                          0
 	#define	bBITMAP16_SEL_BIT_POS0                       4
 	#define	MSK32BITMAP16_SEL_BIT_POS0                          0x0000000F
 	#define	BA_BITMAP16_SEL_BIT_POS1                       0x0000
 	#define	B16BITMAP16_SEL_BIT_POS1                       0x0000
 	#define	LSb32BITMAP16_SEL_BIT_POS1                          4
 	#define	LSb16BITMAP16_SEL_BIT_POS1                          4
 	#define	bBITMAP16_SEL_BIT_POS1                       4
 	#define	MSK32BITMAP16_SEL_BIT_POS1                          0x000000F0
 	#define	BA_BITMAP16_SEL_BIT_POS2                       0x0001
 	#define	B16BITMAP16_SEL_BIT_POS2                       0x0000
 	#define	LSb32BITMAP16_SEL_BIT_POS2                          8
 	#define	LSb16BITMAP16_SEL_BIT_POS2                          8
 	#define	bBITMAP16_SEL_BIT_POS2                       4
 	#define	MSK32BITMAP16_SEL_BIT_POS2                          0x00000F00
 	#define	BA_BITMAP16_SEL_BIT_POS3                       0x0001
 	#define	B16BITMAP16_SEL_BIT_POS3                       0x0000
 	#define	LSb32BITMAP16_SEL_BIT_POS3                          12
 	#define	LSb16BITMAP16_SEL_BIT_POS3                          12
 	#define	bBITMAP16_SEL_BIT_POS3                       4
 	#define	MSK32BITMAP16_SEL_BIT_POS3                          0x0000F000
 	#define	BA_BITMAP16_SEL_BIT_POS4                       0x0002
 	#define	B16BITMAP16_SEL_BIT_POS4                       0x0002
 	#define	LSb32BITMAP16_SEL_BIT_POS4                          16
 	#define	LSb16BITMAP16_SEL_BIT_POS4                          0
 	#define	bBITMAP16_SEL_BIT_POS4                       4
 	#define	MSK32BITMAP16_SEL_BIT_POS4                          0x000F0000
 	#define	BA_BITMAP16_SEL_BIT_POS5                       0x0002
 	#define	B16BITMAP16_SEL_BIT_POS5                       0x0002
 	#define	LSb32BITMAP16_SEL_BIT_POS5                          20
 	#define	LSb16BITMAP16_SEL_BIT_POS5                          4
 	#define	bBITMAP16_SEL_BIT_POS5                       4
 	#define	MSK32BITMAP16_SEL_BIT_POS5                          0x00F00000
 	#define	BA_BITMAP16_SEL_BIT_POS6                       0x0003
 	#define	B16BITMAP16_SEL_BIT_POS6                       0x0002
 	#define	LSb32BITMAP16_SEL_BIT_POS6                          24
 	#define	LSb16BITMAP16_SEL_BIT_POS6                          8
 	#define	bBITMAP16_SEL_BIT_POS6                       4
 	#define	MSK32BITMAP16_SEL_BIT_POS6                          0x0F000000
 	#define	BA_BITMAP16_SEL_BIT_POS7                       0x0003
 	#define	B16BITMAP16_SEL_BIT_POS7                       0x0002
 	#define	LSb32BITMAP16_SEL_BIT_POS7                          28
 	#define	LSb16BITMAP16_SEL_BIT_POS7                          12
 	#define	bBITMAP16_SEL_BIT_POS7                       4
 	#define	MSK32BITMAP16_SEL_BIT_POS7                          0xF0000000
 	#define	RA_BITMAP16_SEL1                               0x0004
 	#define	BA_BITMAP16_SEL_BIT_POS8                       0x0004
 	#define	B16BITMAP16_SEL_BIT_POS8                       0x0004
 	#define	LSb32BITMAP16_SEL_BIT_POS8                          0
 	#define	LSb16BITMAP16_SEL_BIT_POS8                          0
 	#define	bBITMAP16_SEL_BIT_POS8                       4
 	#define	MSK32BITMAP16_SEL_BIT_POS8                          0x0000000F
 	#define	BA_BITMAP16_SEL_BIT_POS9                       0x0004
 	#define	B16BITMAP16_SEL_BIT_POS9                       0x0004
 	#define	LSb32BITMAP16_SEL_BIT_POS9                          4
 	#define	LSb16BITMAP16_SEL_BIT_POS9                          4
 	#define	bBITMAP16_SEL_BIT_POS9                       4
 	#define	MSK32BITMAP16_SEL_BIT_POS9                          0x000000F0
 	#define	BA_BITMAP16_SEL_BIT_POS10                      0x0005
 	#define	B16BITMAP16_SEL_BIT_POS10                      0x0004
 	#define	LSb32BITMAP16_SEL_BIT_POS10                         8
 	#define	LSb16BITMAP16_SEL_BIT_POS10                         8
 	#define	bBITMAP16_SEL_BIT_POS10                      4
 	#define	MSK32BITMAP16_SEL_BIT_POS10                         0x00000F00
 	#define	BA_BITMAP16_SEL_BIT_POS11                      0x0005
 	#define	B16BITMAP16_SEL_BIT_POS11                      0x0004
 	#define	LSb32BITMAP16_SEL_BIT_POS11                         12
 	#define	LSb16BITMAP16_SEL_BIT_POS11                         12
 	#define	bBITMAP16_SEL_BIT_POS11                      4
 	#define	MSK32BITMAP16_SEL_BIT_POS11                         0x0000F000
 	#define	BA_BITMAP16_SEL_BIT_POS12                      0x0006
 	#define	B16BITMAP16_SEL_BIT_POS12                      0x0006
 	#define	LSb32BITMAP16_SEL_BIT_POS12                         16
 	#define	LSb16BITMAP16_SEL_BIT_POS12                         0
 	#define	bBITMAP16_SEL_BIT_POS12                      4
 	#define	MSK32BITMAP16_SEL_BIT_POS12                         0x000F0000
 	#define	BA_BITMAP16_SEL_BIT_POS13                      0x0006
 	#define	B16BITMAP16_SEL_BIT_POS13                      0x0006
 	#define	LSb32BITMAP16_SEL_BIT_POS13                         20
 	#define	LSb16BITMAP16_SEL_BIT_POS13                         4
 	#define	bBITMAP16_SEL_BIT_POS13                      4
 	#define	MSK32BITMAP16_SEL_BIT_POS13                         0x00F00000
 	#define	BA_BITMAP16_SEL_BIT_POS14                      0x0007
 	#define	B16BITMAP16_SEL_BIT_POS14                      0x0006
 	#define	LSb32BITMAP16_SEL_BIT_POS14                         24
 	#define	LSb16BITMAP16_SEL_BIT_POS14                         8
 	#define	bBITMAP16_SEL_BIT_POS14                      4
 	#define	MSK32BITMAP16_SEL_BIT_POS14                         0x0F000000
 	#define	BA_BITMAP16_SEL_BIT_POS15                      0x0007
 	#define	B16BITMAP16_SEL_BIT_POS15                      0x0006
 	#define	LSb32BITMAP16_SEL_BIT_POS15                         28
 	#define	LSb16BITMAP16_SEL_BIT_POS15                         12
 	#define	bBITMAP16_SEL_BIT_POS15                      4
 	#define	MSK32BITMAP16_SEL_BIT_POS15                         0xF0000000
 	#define	RA_ReadClient_Rd                               0x0000
 	#define	BA_ReadClient_Rd_start                         0x0000
 	#define	B16ReadClient_Rd_start                         0x0000
 	#define	LSb32ReadClient_Rd_start                            0
 	#define	LSb16ReadClient_Rd_start                            0
 	#define	bReadClient_Rd_start                         1
 	#define	MSK32ReadClient_Rd_start                            0x00000001
 	#define	BA_ReadClient_Rd_clear                         0x0000
 	#define	B16ReadClient_Rd_clear                         0x0000
 	#define	LSb32ReadClient_Rd_clear                            1
 	#define	LSb16ReadClient_Rd_clear                            1
 	#define	bReadClient_Rd_clear                         1
 	#define	MSK32ReadClient_Rd_clear                            0x00000002
 	#define	RA_ReadClient_Word                             0x0004
 	#define	BA_ReadClient_Word_tot                         0x0004
 	#define	B16ReadClient_Word_tot                         0x0004
 	#define	LSb32ReadClient_Word_tot                            0
 	#define	LSb16ReadClient_Word_tot                            0
 	#define	bReadClient_Word_tot                         32
 	#define	MSK32ReadClient_Word_tot                            0xFFFFFFFF
 	#define	RA_ReadClient_NonStdRes                        0x0008
 	#define	BA_ReadClient_NonStdRes_enable                 0x0008
 	#define	B16ReadClient_NonStdRes_enable                 0x0008
 	#define	LSb32ReadClient_NonStdRes_enable                    0
 	#define	LSb16ReadClient_NonStdRes_enable                    0
 	#define	bReadClient_NonStdRes_enable                 1
 	#define	MSK32ReadClient_NonStdRes_enable                    0x00000001
 	#define	BA_ReadClient_NonStdRes_pixlineTot             0x0008
 	#define	B16ReadClient_NonStdRes_pixlineTot             0x0008
 	#define	LSb32ReadClient_NonStdRes_pixlineTot                1
 	#define	LSb16ReadClient_NonStdRes_pixlineTot                1
 	#define	bReadClient_NonStdRes_pixlineTot             13
 	#define	MSK32ReadClient_NonStdRes_pixlineTot                0x00003FFE
 	#define	BA_ReadClient_NonStdRes_flushCnt               0x0009
 	#define	B16ReadClient_NonStdRes_flushCnt               0x0008
 	#define	LSb32ReadClient_NonStdRes_flushCnt                  14
 	#define	LSb16ReadClient_NonStdRes_flushCnt                  14
 	#define	bReadClient_NonStdRes_flushCnt               4
 	#define	MSK32ReadClient_NonStdRes_flushCnt                  0x0003C000
 	#define	RA_ReadClient_pack                             0x000C
 	#define	BA_ReadClient_pack_Sel                         0x000C
 	#define	B16ReadClient_pack_Sel                         0x000C
 	#define	LSb32ReadClient_pack_Sel                            0
 	#define	LSb16ReadClient_pack_Sel                            0
 	#define	bReadClient_pack_Sel                         4
 	#define	MSK32ReadClient_pack_Sel                            0x0000000F
 	#define	RA_WriteClient_Wr                              0x0000
 	#define	BA_WriteClient_Wr_start                        0x0000
 	#define	B16WriteClient_Wr_start                        0x0000
 	#define	LSb32WriteClient_Wr_start                           0
 	#define	LSb16WriteClient_Wr_start                           0
 	#define	bWriteClient_Wr_start                        1
 	#define	MSK32WriteClient_Wr_start                           0x00000001
 	#define	BA_WriteClient_Wr_clear                        0x0000
 	#define	B16WriteClient_Wr_clear                        0x0000
 	#define	LSb32WriteClient_Wr_clear                           1
 	#define	LSb16WriteClient_Wr_clear                           1
 	#define	bWriteClient_Wr_clear                        1
 	#define	MSK32WriteClient_Wr_clear                           0x00000002
 	#define	RA_WriteClient_pix                             0x0004
 	#define	BA_WriteClient_pix_tot                         0x0004
 	#define	B16WriteClient_pix_tot                         0x0004
 	#define	LSb32WriteClient_pix_tot                            0
 	#define	LSb16WriteClient_pix_tot                            0
 	#define	bWriteClient_pix_tot                         32
 	#define	MSK32WriteClient_pix_tot                            0xFFFFFFFF
 	#define	RA_WriteClient_NonStdRes                       0x0008
 	#define	BA_WriteClient_NonStdRes_enable                0x0008
 	#define	B16WriteClient_NonStdRes_enable                0x0008
 	#define	LSb32WriteClient_NonStdRes_enable                   0
 	#define	LSb16WriteClient_NonStdRes_enable                   0
 	#define	bWriteClient_NonStdRes_enable                1
 	#define	MSK32WriteClient_NonStdRes_enable                   0x00000001
 	#define	BA_WriteClient_NonStdRes_pixlineTot            0x0008
 	#define	B16WriteClient_NonStdRes_pixlineTot            0x0008
 	#define	LSb32WriteClient_NonStdRes_pixlineTot               1
 	#define	LSb16WriteClient_NonStdRes_pixlineTot               1
 	#define	bWriteClient_NonStdRes_pixlineTot            13
 	#define	MSK32WriteClient_NonStdRes_pixlineTot               0x00003FFE
 	#define	RA_WriteClient_pack                            0x000C
 	#define	BA_WriteClient_pack_Sel                        0x000C
 	#define	B16WriteClient_pack_Sel                        0x000C
 	#define	LSb32WriteClient_pack_Sel                           0
 	#define	LSb16WriteClient_pack_Sel                           0
 	#define	bWriteClient_pack_Sel                        4
 	#define	MSK32WriteClient_pack_Sel                           0x0000000F
 	#define	RA_ADPSCL_CFG0                                 0x0000
 	#define	BA_ADPSCL_CFG0_even                            0x0000
 	#define	B16ADPSCL_CFG0_even                            0x0000
 	#define	LSb32ADPSCL_CFG0_even                               0
 	#define	LSb16ADPSCL_CFG0_even                               0
 	#define	bADPSCL_CFG0_even                            8
 	#define	MSK32ADPSCL_CFG0_even                               0x000000FF
 	#define	BA_ADPSCL_CFG0_odd                             0x0001
 	#define	B16ADPSCL_CFG0_odd                             0x0000
 	#define	LSb32ADPSCL_CFG0_odd                                8
 	#define	LSb16ADPSCL_CFG0_odd                                8
 	#define	bADPSCL_CFG0_odd                             8
 	#define	MSK32ADPSCL_CFG0_odd                                0x0000FF00
 	#define	BA_ADPSCL_CFG0_hinitph                         0x0002
 	#define	B16ADPSCL_CFG0_hinitph                         0x0002
 	#define	LSb32ADPSCL_CFG0_hinitph                            16
 	#define	LSb16ADPSCL_CFG0_hinitph                            0
 	#define	bADPSCL_CFG0_hinitph                         8
 	#define	MSK32ADPSCL_CFG0_hinitph                            0x00FF0000
 	#define	BA_ADPSCL_CFG0_ctrl0                           0x0003
 	#define	B16ADPSCL_CFG0_ctrl0                           0x0002
 	#define	LSb32ADPSCL_CFG0_ctrl0                              24
 	#define	LSb16ADPSCL_CFG0_ctrl0                              8
 	#define	bADPSCL_CFG0_ctrl0                           8
 	#define	MSK32ADPSCL_CFG0_ctrl0                              0xFF000000
 	#define	RA_ADPSCL_CFG1                                 0x0004
 	#define	BA_ADPSCL_CFG1_ivres                           0x0004
 	#define	B16ADPSCL_CFG1_ivres                           0x0004
 	#define	LSb32ADPSCL_CFG1_ivres                              0
 	#define	LSb16ADPSCL_CFG1_ivres                              0
 	#define	bADPSCL_CFG1_ivres                           12
 	#define	MSK32ADPSCL_CFG1_ivres                              0x00000FFF
 	#define	BA_ADPSCL_CFG1_ovres                           0x0005
 	#define	B16ADPSCL_CFG1_ovres                           0x0004
 	#define	LSb32ADPSCL_CFG1_ovres                              12
 	#define	LSb16ADPSCL_CFG1_ovres                              12
 	#define	bADPSCL_CFG1_ovres                           12
 	#define	MSK32ADPSCL_CFG1_ovres                              0x00FFF000
 	#define	RA_ADPSCL_CFG2                                 0x0008
 	#define	BA_ADPSCL_CFG2_ihres                           0x0008
 	#define	B16ADPSCL_CFG2_ihres                           0x0008
 	#define	LSb32ADPSCL_CFG2_ihres                              0
 	#define	LSb16ADPSCL_CFG2_ihres                              0
 	#define	bADPSCL_CFG2_ihres                           13
 	#define	MSK32ADPSCL_CFG2_ihres                              0x00001FFF
 	#define	BA_ADPSCL_CFG2_ohres                           0x0009
 	#define	B16ADPSCL_CFG2_ohres                           0x0008
 	#define	LSb32ADPSCL_CFG2_ohres                              13
 	#define	LSb16ADPSCL_CFG2_ohres                              13
 	#define	bADPSCL_CFG2_ohres                           13
 	#define	MSK32ADPSCL_CFG2_ohres                              0x03FFE000
 	#define	RA_ADPSCL_CFG3                                 0x000C
 	#define	BA_ADPSCL_CFG3_vratio                          0x000C
 	#define	B16ADPSCL_CFG3_vratio                          0x000C
 	#define	LSb32ADPSCL_CFG3_vratio                             0
 	#define	LSb16ADPSCL_CFG3_vratio                             0
 	#define	bADPSCL_CFG3_vratio                          25
 	#define	MSK32ADPSCL_CFG3_vratio                             0x01FFFFFF
 	#define	RA_ADPSCL_CFG4                                 0x0010
 	#define	BA_ADPSCL_CFG4_hratio                          0x0010
 	#define	B16ADPSCL_CFG4_hratio                          0x0010
 	#define	LSb32ADPSCL_CFG4_hratio                             0
 	#define	LSb16ADPSCL_CFG4_hratio                             0
 	#define	bADPSCL_CFG4_hratio                          25
 	#define	MSK32ADPSCL_CFG4_hratio                             0x01FFFFFF
 	#define	RA_ADPSCL_CFG5                                 0x0014
 	#define	BA_ADPSCL_CFG5_memsize                         0x0014
 	#define	B16ADPSCL_CFG5_memsize                         0x0014
 	#define	LSb32ADPSCL_CFG5_memsize                            0
 	#define	LSb16ADPSCL_CFG5_memsize                            0
 	#define	bADPSCL_CFG5_memsize                         11
 	#define	MSK32ADPSCL_CFG5_memsize                            0x000007FF
 	#define	BA_ADPSCL_CFG5_vwrap                           0x0015
 	#define	B16ADPSCL_CFG5_vwrap                           0x0014
 	#define	LSb32ADPSCL_CFG5_vwrap                              11
 	#define	LSb16ADPSCL_CFG5_vwrap                              11
 	#define	bADPSCL_CFG5_vwrap                           16
 	#define	MSK32ADPSCL_CFG5_vwrap                              0x07FFF800
 	#define	RA_ADPSCL_CFG6                                 0x0018
 	#define	BA_ADPSCL_CFG6_ups_cswap                       0x0018
 	#define	B16ADPSCL_CFG6_ups_cswap                       0x0018
 	#define	LSb32ADPSCL_CFG6_ups_cswap                          0
 	#define	LSb16ADPSCL_CFG6_ups_cswap                          0
 	#define	bADPSCL_CFG6_ups_cswap                       1
 	#define	MSK32ADPSCL_CFG6_ups_cswap                          0x00000001
 	#define	BA_ADPSCL_CFG6_ups_cshift                      0x0018
 	#define	B16ADPSCL_CFG6_ups_cshift                      0x0018
 	#define	LSb32ADPSCL_CFG6_ups_cshift                         1
 	#define	LSb16ADPSCL_CFG6_ups_cshift                         1
 	#define	bADPSCL_CFG6_ups_cshift                      1
 	#define	MSK32ADPSCL_CFG6_ups_cshift                         0x00000002
 	#define	BA_ADPSCL_CFG6_ups_yshift                      0x0018
 	#define	B16ADPSCL_CFG6_ups_yshift                      0x0018
 	#define	LSb32ADPSCL_CFG6_ups_yshift                         2
 	#define	LSb16ADPSCL_CFG6_ups_yshift                         2
 	#define	bADPSCL_CFG6_ups_yshift                      1
 	#define	MSK32ADPSCL_CFG6_ups_yshift                         0x00000004
 	#define	BA_ADPSCL_CFG6_ups_yblank                      0x0018
 	#define	B16ADPSCL_CFG6_ups_yblank                      0x0018
 	#define	LSb32ADPSCL_CFG6_ups_yblank                         3
 	#define	LSb16ADPSCL_CFG6_ups_yblank                         3
 	#define	bADPSCL_CFG6_ups_yblank                      10
 	#define	MSK32ADPSCL_CFG6_ups_yblank                         0x00001FF8
 	#define	BA_ADPSCL_CFG6_fstall                          0x0019
 	#define	B16ADPSCL_CFG6_fstall                          0x0018
 	#define	LSb32ADPSCL_CFG6_fstall                             13
 	#define	LSb16ADPSCL_CFG6_fstall                             13
 	#define	bADPSCL_CFG6_fstall                          8
 	#define	MSK32ADPSCL_CFG6_fstall                             0x001FE000
 	#define	BA_ADPSCL_CFG6_bstall                          0x001A
 	#define	B16ADPSCL_CFG6_bstall                          0x001A
 	#define	LSb32ADPSCL_CFG6_bstall                             21
 	#define	LSb16ADPSCL_CFG6_bstall                             5
 	#define	bADPSCL_CFG6_bstall                          8
 	#define	MSK32ADPSCL_CFG6_bstall                             0x1FE00000
 	#define	RA_ADPSCL_CFG7                                 0x001C
 	#define	BA_ADPSCL_CFG7_ups_cblank                      0x001C
 	#define	B16ADPSCL_CFG7_ups_cblank                      0x001C
 	#define	LSb32ADPSCL_CFG7_ups_cblank                         0
 	#define	LSb16ADPSCL_CFG7_ups_cblank                         0
 	#define	bADPSCL_CFG7_ups_cblank                      10
 	#define	MSK32ADPSCL_CFG7_ups_cblank                         0x000003FF
 	#define	BA_ADPSCL_CFG7_htap_offset                     0x001D
 	#define	B16ADPSCL_CFG7_htap_offset                     0x001C
 	#define	LSb32ADPSCL_CFG7_htap_offset                        10
 	#define	LSb16ADPSCL_CFG7_htap_offset                        10
 	#define	bADPSCL_CFG7_htap_offset                     3
 	#define	MSK32ADPSCL_CFG7_htap_offset                        0x00001C00
 	#define	BA_ADPSCL_CFG7_vtap_offset                     0x001D
 	#define	B16ADPSCL_CFG7_vtap_offset                     0x001C
 	#define	LSb32ADPSCL_CFG7_vtap_offset                        13
 	#define	LSb16ADPSCL_CFG7_vtap_offset                        13
 	#define	bADPSCL_CFG7_vtap_offset                     8
 	#define	MSK32ADPSCL_CFG7_vtap_offset                        0x001FE000
 	#define	RA_ADPSCL_CFG8                                 0x0020
 	#define	BA_ADPSCL_CFG8_init_ratio                      0x0020
 	#define	B16ADPSCL_CFG8_init_ratio                      0x0020
 	#define	LSb32ADPSCL_CFG8_init_ratio                         0
 	#define	LSb16ADPSCL_CFG8_init_ratio                         0
 	#define	bADPSCL_CFG8_init_ratio                      25
 	#define	MSK32ADPSCL_CFG8_init_ratio                         0x01FFFFFF
 	#define	RA_ADPSCL_CFG9                                 0x0024
 	#define	BA_ADPSCL_CFG9_inc_ratio                       0x0024
 	#define	B16ADPSCL_CFG9_inc_ratio                       0x0024
 	#define	LSb32ADPSCL_CFG9_inc_ratio                          0
 	#define	LSb16ADPSCL_CFG9_inc_ratio                          0
 	#define	bADPSCL_CFG9_inc_ratio                       25
 	#define	MSK32ADPSCL_CFG9_inc_ratio                          0x01FFFFFF
 	#define	RA_ADPSCL_CFG10                                0x0028
 	#define	BA_ADPSCL_CFG10_nlcres                         0x0028
 	#define	B16ADPSCL_CFG10_nlcres                         0x0028
 	#define	LSb32ADPSCL_CFG10_nlcres                            0
 	#define	LSb16ADPSCL_CFG10_nlcres                            0
 	#define	bADPSCL_CFG10_nlcres                         13
 	#define	MSK32ADPSCL_CFG10_nlcres                            0x00001FFF
 	#define	RA_ADPSCL_CFG11                                0x002C
 	#define	BA_ADPSCL_CFG11_avg4_coeff0                    0x002C
 	#define	B16ADPSCL_CFG11_avg4_coeff0                    0x002C
 	#define	LSb32ADPSCL_CFG11_avg4_coeff0                       0
 	#define	LSb16ADPSCL_CFG11_avg4_coeff0                       0
 	#define	bADPSCL_CFG11_avg4_coeff0                    12
 	#define	MSK32ADPSCL_CFG11_avg4_coeff0                       0x00000FFF
 	#define	BA_ADPSCL_CFG11_avg4_coeff1                    0x002D
 	#define	B16ADPSCL_CFG11_avg4_coeff1                    0x002C
 	#define	LSb32ADPSCL_CFG11_avg4_coeff1                       12
 	#define	LSb16ADPSCL_CFG11_avg4_coeff1                       12
 	#define	bADPSCL_CFG11_avg4_coeff1                    12
 	#define	MSK32ADPSCL_CFG11_avg4_coeff1                       0x00FFF000
 	#define	BA_ADPSCL_CFG11_dign_dr1                       0x002F
 	#define	B16ADPSCL_CFG11_dign_dr1                       0x002E
 	#define	LSb32ADPSCL_CFG11_dign_dr1                          24
 	#define	LSb16ADPSCL_CFG11_dign_dr1                          8
 	#define	bADPSCL_CFG11_dign_dr1                       8
 	#define	MSK32ADPSCL_CFG11_dign_dr1                          0xFF000000
 	#define	RA_ADPSCL_CFG12                                0x0030
 	#define	BA_ADPSCL_CFG12_avg4_coeff2                    0x0030
 	#define	B16ADPSCL_CFG12_avg4_coeff2                    0x0030
 	#define	LSb32ADPSCL_CFG12_avg4_coeff2                       0
 	#define	LSb16ADPSCL_CFG12_avg4_coeff2                       0
 	#define	bADPSCL_CFG12_avg4_coeff2                    12
 	#define	MSK32ADPSCL_CFG12_avg4_coeff2                       0x00000FFF
 	#define	BA_ADPSCL_CFG12_avg4_coeff3                    0x0031
 	#define	B16ADPSCL_CFG12_avg4_coeff3                    0x0030
 	#define	LSb32ADPSCL_CFG12_avg4_coeff3                       12
 	#define	LSb16ADPSCL_CFG12_avg4_coeff3                       12
 	#define	bADPSCL_CFG12_avg4_coeff3                    12
 	#define	MSK32ADPSCL_CFG12_avg4_coeff3                       0x00FFF000
 	#define	BA_ADPSCL_CFG12_dign_dr2                       0x0033
 	#define	B16ADPSCL_CFG12_dign_dr2                       0x0032
 	#define	LSb32ADPSCL_CFG12_dign_dr2                          24
 	#define	LSb16ADPSCL_CFG12_dign_dr2                          8
 	#define	bADPSCL_CFG12_dign_dr2                       8
 	#define	MSK32ADPSCL_CFG12_dign_dr2                          0xFF000000
 	#define	RA_ADPSCL_CFG13                                0x0034
 	#define	BA_ADPSCL_CFG13_dign_ydiff                     0x0034
 	#define	B16ADPSCL_CFG13_dign_ydiff                     0x0034
 	#define	LSb32ADPSCL_CFG13_dign_ydiff                        0
 	#define	LSb16ADPSCL_CFG13_dign_ydiff                        0
 	#define	bADPSCL_CFG13_dign_ydiff                     12
 	#define	MSK32ADPSCL_CFG13_dign_ydiff                        0x00000FFF
 	#define	BA_ADPSCL_CFG13_dign_ddiff                     0x0035
 	#define	B16ADPSCL_CFG13_dign_ddiff                     0x0034
 	#define	LSb32ADPSCL_CFG13_dign_ddiff                        12
 	#define	LSb16ADPSCL_CFG13_dign_ddiff                        12
 	#define	bADPSCL_CFG13_dign_ddiff                     12
 	#define	MSK32ADPSCL_CFG13_dign_ddiff                        0x00FFF000
 	#define	BA_ADPSCL_CFG13_dign_dr3                       0x0037
 	#define	B16ADPSCL_CFG13_dign_dr3                       0x0036
 	#define	LSb32ADPSCL_CFG13_dign_dr3                          24
 	#define	LSb16ADPSCL_CFG13_dign_dr3                          8
 	#define	bADPSCL_CFG13_dign_dr3                       8
 	#define	MSK32ADPSCL_CFG13_dign_dr3                          0xFF000000
 	#define	RA_ADPSCL_CFG14                                0x0038
 	#define	BA_ADPSCL_CFG14_hp_offset                      0x0038
 	#define	B16ADPSCL_CFG14_hp_offset                      0x0038
 	#define	LSb32ADPSCL_CFG14_hp_offset                         0
 	#define	LSb16ADPSCL_CFG14_hp_offset                         0
 	#define	bADPSCL_CFG14_hp_offset                      12
 	#define	MSK32ADPSCL_CFG14_hp_offset                         0x00000FFF
 	#define	BA_ADPSCL_CFG14_hp_diff                        0x0039
 	#define	B16ADPSCL_CFG14_hp_diff                        0x0038
 	#define	LSb32ADPSCL_CFG14_hp_diff                           12
 	#define	LSb16ADPSCL_CFG14_hp_diff                           12
 	#define	bADPSCL_CFG14_hp_diff                        12
 	#define	MSK32ADPSCL_CFG14_hp_diff                           0x00FFF000
 	#define	BA_ADPSCL_CFG14_dign_nbr                       0x003B
 	#define	B16ADPSCL_CFG14_dign_nbr                       0x003A
 	#define	LSb32ADPSCL_CFG14_dign_nbr                          24
 	#define	LSb16ADPSCL_CFG14_dign_nbr                          8
 	#define	bADPSCL_CFG14_dign_nbr                       8
 	#define	MSK32ADPSCL_CFG14_dign_nbr                          0xFF000000
 	#define	RA_ADPSCL_CFG15                                0x003C
 	#define	BA_ADPSCL_CFG15_ctrl1                          0x003C
 	#define	B16ADPSCL_CFG15_ctrl1                          0x003C
 	#define	LSb32ADPSCL_CFG15_ctrl1                             0
 	#define	LSb16ADPSCL_CFG15_ctrl1                             0
 	#define	bADPSCL_CFG15_ctrl1                          8
 	#define	MSK32ADPSCL_CFG15_ctrl1                             0x000000FF
 	#define	BA_ADPSCL_CFG15_hctrl                          0x003D
 	#define	B16ADPSCL_CFG15_hctrl                          0x003C
 	#define	LSb32ADPSCL_CFG15_hctrl                             8
 	#define	LSb16ADPSCL_CFG15_hctrl                             8
 	#define	bADPSCL_CFG15_hctrl                          5
 	#define	MSK32ADPSCL_CFG15_hctrl                             0x00001F00
 	#define	BA_ADPSCL_CFG15_vctrl                          0x003D
 	#define	B16ADPSCL_CFG15_vctrl                          0x003C
 	#define	LSb32ADPSCL_CFG15_vctrl                             13
 	#define	LSb16ADPSCL_CFG15_vctrl                             13
 	#define	bADPSCL_CFG15_vctrl                          5
 	#define	MSK32ADPSCL_CFG15_vctrl                             0x0003E000
 	#define	BA_ADPSCL_CFG15_crop                           0x003E
 	#define	B16ADPSCL_CFG15_crop                           0x003E
 	#define	LSb32ADPSCL_CFG15_crop                              18
 	#define	LSb16ADPSCL_CFG15_crop                              2
 	#define	bADPSCL_CFG15_crop                           4
 	#define	MSK32ADPSCL_CFG15_crop                              0x003C0000
 	#define	BA_ADPSCL_CFG15_hscl11                         0x003E
 	#define	B16ADPSCL_CFG15_hscl11                         0x003E
 	#define	LSb32ADPSCL_CFG15_hscl11                            22
 	#define	LSb16ADPSCL_CFG15_hscl11                            6
 	#define	bADPSCL_CFG15_hscl11                         1
 	#define	MSK32ADPSCL_CFG15_hscl11                            0x00400000
 	#define	BA_ADPSCL_CFG15_vscl11                         0x003E
 	#define	B16ADPSCL_CFG15_vscl11                         0x003E
 	#define	LSb32ADPSCL_CFG15_vscl11                            23
 	#define	LSb16ADPSCL_CFG15_vscl11                            7
 	#define	bADPSCL_CFG15_vscl11                         1
 	#define	MSK32ADPSCL_CFG15_vscl11                            0x00800000
 	#define	BA_ADPSCL_CFG15_bypass                         0x003F
 	#define	B16ADPSCL_CFG15_bypass                         0x003E
 	#define	LSb32ADPSCL_CFG15_bypass                            24
 	#define	LSb16ADPSCL_CFG15_bypass                            8
 	#define	bADPSCL_CFG15_bypass                         1
 	#define	MSK32ADPSCL_CFG15_bypass                            0x01000000
 	#define	RA_ADPSCL_CFG16                                0x0040
 	#define	BA_ADPSCL_CFG16_en_n                           0x0040
 	#define	B16ADPSCL_CFG16_en_n                           0x0040
 	#define	LSb32ADPSCL_CFG16_en_n                              0
 	#define	LSb16ADPSCL_CFG16_en_n                              0
 	#define	bADPSCL_CFG16_en_n                           1
 	#define	MSK32ADPSCL_CFG16_en_n                              0x00000001
 	#define	BA_ADPSCL_CFG16_xbstall_en                     0x0040
 	#define	B16ADPSCL_CFG16_xbstall_en                     0x0040
 	#define	LSb32ADPSCL_CFG16_xbstall_en                        1
 	#define	LSb16ADPSCL_CFG16_xbstall_en                        1
 	#define	bADPSCL_CFG16_xbstall_en                     1
 	#define	MSK32ADPSCL_CFG16_xbstall_en                        0x00000002
 	#define	BA_ADPSCL_CFG16_xbstall_dly                    0x0040
 	#define	B16ADPSCL_CFG16_xbstall_dly                    0x0040
 	#define	LSb32ADPSCL_CFG16_xbstall_dly                       2
 	#define	LSb16ADPSCL_CFG16_xbstall_dly                       2
 	#define	bADPSCL_CFG16_xbstall_dly                    14
 	#define	MSK32ADPSCL_CFG16_xbstall_dly                       0x0000FFFC
 	#define	BA_ADPSCL_CFG16_ovf_margin                     0x0042
 	#define	B16ADPSCL_CFG16_ovf_margin                     0x0042
 	#define	LSb32ADPSCL_CFG16_ovf_margin                        16
 	#define	LSb16ADPSCL_CFG16_ovf_margin                        0
 	#define	bADPSCL_CFG16_ovf_margin                     8
 	#define	MSK32ADPSCL_CFG16_ovf_margin                        0x00FF0000
 	#define	BA_ADPSCL_CFG16_udf_margin                     0x0043
 	#define	B16ADPSCL_CFG16_udf_margin                     0x0042
 	#define	LSb32ADPSCL_CFG16_udf_margin                        24
 	#define	LSb16ADPSCL_CFG16_udf_margin                        8
 	#define	bADPSCL_CFG16_udf_margin                     8
 	#define	MSK32ADPSCL_CFG16_udf_margin                        0xFF000000
 	#define	RA_ADPSCL_CFG17                                0x0044
 	#define	BA_ADPSCL_CFG17_lsize                          0x0044
 	#define	B16ADPSCL_CFG17_lsize                          0x0044
 	#define	LSb32ADPSCL_CFG17_lsize                             0
 	#define	LSb16ADPSCL_CFG17_lsize                             0
 	#define	bADPSCL_CFG17_lsize                          10
 	#define	MSK32ADPSCL_CFG17_lsize                             0x000003FF
 	#define	BA_ADPSCL_CFG17_lsize_A                        0x0045
 	#define	B16ADPSCL_CFG17_lsize_A                        0x0044
 	#define	LSb32ADPSCL_CFG17_lsize_A                           10
 	#define	LSb16ADPSCL_CFG17_lsize_A                           10
 	#define	bADPSCL_CFG17_lsize_A                        10
 	#define	MSK32ADPSCL_CFG17_lsize_A                           0x000FFC00
 	#define	RA_ADPSCL_CFG18                                0x0048
 	#define	BA_ADPSCL_CFG18_fifo_mode                      0x0048
 	#define	B16ADPSCL_CFG18_fifo_mode                      0x0048
 	#define	LSb32ADPSCL_CFG18_fifo_mode                         0
 	#define	LSb16ADPSCL_CFG18_fifo_mode                         0
 	#define	bADPSCL_CFG18_fifo_mode                      1
 	#define	MSK32ADPSCL_CFG18_fifo_mode                         0x00000001
 	#define	BA_ADPSCL_CFG18_fifo_depth                     0x0048
 	#define	B16ADPSCL_CFG18_fifo_depth                     0x0048
 	#define	LSb32ADPSCL_CFG18_fifo_depth                        1
 	#define	LSb16ADPSCL_CFG18_fifo_depth                        1
 	#define	bADPSCL_CFG18_fifo_depth                     15
 	#define	MSK32ADPSCL_CFG18_fifo_depth                        0x0000FFFE
 	#define	BA_ADPSCL_CFG18_fifo_dfst                      0x004A
 	#define	B16ADPSCL_CFG18_fifo_dfst                      0x004A
 	#define	LSb32ADPSCL_CFG18_fifo_dfst                         16
 	#define	LSb16ADPSCL_CFG18_fifo_dfst                         0
 	#define	bADPSCL_CFG18_fifo_dfst                      15
 	#define	MSK32ADPSCL_CFG18_fifo_dfst                         0x7FFF0000
 	#define	BA_ADPSCL_CFG18_pftch                          0x004B
 	#define	B16ADPSCL_CFG18_pftch                          0x004A
 	#define	LSb32ADPSCL_CFG18_pftch                             31
 	#define	LSb16ADPSCL_CFG18_pftch                             15
 	#define	bADPSCL_CFG18_pftch                          1
 	#define	MSK32ADPSCL_CFG18_pftch                             0x80000000
 	#define	RA_ADPSCL_CFG19                                0x004C
 	#define	BA_ADPSCL_CFG19_scl_after_crop_h               0x004C
 	#define	B16ADPSCL_CFG19_scl_after_crop_h               0x004C
 	#define	LSb32ADPSCL_CFG19_scl_after_crop_h                  0
 	#define	LSb16ADPSCL_CFG19_scl_after_crop_h                  0
 	#define	bADPSCL_CFG19_scl_after_crop_h               8
 	#define	MSK32ADPSCL_CFG19_scl_after_crop_h                  0x000000FF
 	#define	BA_ADPSCL_CFG19_scl_after_crop_v               0x004D
 	#define	B16ADPSCL_CFG19_scl_after_crop_v               0x004C
 	#define	LSb32ADPSCL_CFG19_scl_after_crop_v                  8
 	#define	LSb16ADPSCL_CFG19_scl_after_crop_v                  8
 	#define	bADPSCL_CFG19_scl_after_crop_v               8
 	#define	MSK32ADPSCL_CFG19_scl_after_crop_v                  0x0000FF00
 	#define	RA_ADPSCL_CFG20                                0x0050
 	#define	BA_ADPSCL_CFG20_lb_pdwn_regs                   0x0050
 	#define	B16ADPSCL_CFG20_lb_pdwn_regs                   0x0050
 	#define	LSb32ADPSCL_CFG20_lb_pdwn_regs                      0
 	#define	LSb16ADPSCL_CFG20_lb_pdwn_regs                      0
 	#define	bADPSCL_CFG20_lb_pdwn_regs                   1
 	#define	MSK32ADPSCL_CFG20_lb_pdwn_regs                      0x00000001
 	#define	BA_ADPSCL_CFG20_lb_pdlvmc_regs                 0x0050
 	#define	B16ADPSCL_CFG20_lb_pdlvmc_regs                 0x0050
 	#define	LSb32ADPSCL_CFG20_lb_pdlvmc_regs                    1
 	#define	LSb16ADPSCL_CFG20_lb_pdlvmc_regs                    1
 	#define	bADPSCL_CFG20_lb_pdlvmc_regs                 1
 	#define	MSK32ADPSCL_CFG20_lb_pdlvmc_regs                    0x00000002
 	#define	BA_ADPSCL_CFG20_lb_pdfvssm_regs                0x0050
 	#define	B16ADPSCL_CFG20_lb_pdfvssm_regs                0x0050
 	#define	LSb32ADPSCL_CFG20_lb_pdfvssm_regs                   2
 	#define	LSb16ADPSCL_CFG20_lb_pdfvssm_regs                   2
 	#define	bADPSCL_CFG20_lb_pdfvssm_regs                1
 	#define	MSK32ADPSCL_CFG20_lb_pdfvssm_regs                   0x00000004
 	#define	BA_ADPSCL_CFG20_reserved0                      0x0050
 	#define	B16ADPSCL_CFG20_reserved0                      0x0050
 	#define	LSb32ADPSCL_CFG20_reserved0                         3
 	#define	LSb16ADPSCL_CFG20_reserved0                         3
 	#define	bADPSCL_CFG20_reserved0                      1
 	#define	MSK32ADPSCL_CFG20_reserved0                         0x00000008
 	#define	BA_ADPSCL_CFG20_lut_pdwn_regs                  0x0050
 	#define	B16ADPSCL_CFG20_lut_pdwn_regs                  0x0050
 	#define	LSb32ADPSCL_CFG20_lut_pdwn_regs                     4
 	#define	LSb16ADPSCL_CFG20_lut_pdwn_regs                     4
 	#define	bADPSCL_CFG20_lut_pdwn_regs                  1
 	#define	MSK32ADPSCL_CFG20_lut_pdwn_regs                     0x00000010
 	#define	BA_ADPSCL_CFG20_lut_pdlvmc_regs                0x0050
 	#define	B16ADPSCL_CFG20_lut_pdlvmc_regs                0x0050
 	#define	LSb32ADPSCL_CFG20_lut_pdlvmc_regs                   5
 	#define	LSb16ADPSCL_CFG20_lut_pdlvmc_regs                   5
 	#define	bADPSCL_CFG20_lut_pdlvmc_regs                1
 	#define	MSK32ADPSCL_CFG20_lut_pdlvmc_regs                   0x00000020
 	#define	BA_ADPSCL_CFG20_lut_pdfvssm_regs               0x0050
 	#define	B16ADPSCL_CFG20_lut_pdfvssm_regs               0x0050
 	#define	LSb32ADPSCL_CFG20_lut_pdfvssm_regs                  6
 	#define	LSb16ADPSCL_CFG20_lut_pdfvssm_regs                  6
 	#define	bADPSCL_CFG20_lut_pdfvssm_regs               1
 	#define	MSK32ADPSCL_CFG20_lut_pdfvssm_regs                  0x00000040
 	#define	BA_ADPSCL_CFG20_reserved1                      0x0050
 	#define	B16ADPSCL_CFG20_reserved1                      0x0050
 	#define	LSb32ADPSCL_CFG20_reserved1                         7
 	#define	LSb16ADPSCL_CFG20_reserved1                         7
 	#define	bADPSCL_CFG20_reserved1                      1
 	#define	MSK32ADPSCL_CFG20_reserved1                         0x00000080
 	#define	BA_ADPSCL_CFG20_dpwr_regs                      0x0051
 	#define	B16ADPSCL_CFG20_dpwr_regs                      0x0050
 	#define	LSb32ADPSCL_CFG20_dpwr_regs                         8
 	#define	LSb16ADPSCL_CFG20_dpwr_regs                         8
 	#define	bADPSCL_CFG20_dpwr_regs                      3
 	#define	MSK32ADPSCL_CFG20_dpwr_regs                         0x00000700
 	#define	BA_ADPSCL_CFG20_Reserved2                      0x0051
 	#define	B16ADPSCL_CFG20_Reserved2                      0x0050
 	#define	LSb32ADPSCL_CFG20_Reserved2                         11
 	#define	LSb16ADPSCL_CFG20_Reserved2                         11
 	#define	bADPSCL_CFG20_Reserved2                      1
 	#define	MSK32ADPSCL_CFG20_Reserved2                         0x00000800
 	#define	RA_ADPSCL_COEFF_CFG0                           0x0000
 	#define	BA_ADPSCL_COEFF_CFG0_htap                      0x0000
 	#define	B16ADPSCL_COEFF_CFG0_htap                      0x0000
 	#define	LSb32ADPSCL_COEFF_CFG0_htap                         0
 	#define	LSb16ADPSCL_COEFF_CFG0_htap                         0
 	#define	bADPSCL_COEFF_CFG0_htap                      4
 	#define	MSK32ADPSCL_COEFF_CFG0_htap                         0x0000000F
 	#define	BA_ADPSCL_COEFF_CFG0_vtap                      0x0000
 	#define	B16ADPSCL_COEFF_CFG0_vtap                      0x0000
 	#define	LSb32ADPSCL_COEFF_CFG0_vtap                         4
 	#define	LSb16ADPSCL_COEFF_CFG0_vtap                         4
 	#define	bADPSCL_COEFF_CFG0_vtap                      4
 	#define	MSK32ADPSCL_COEFF_CFG0_vtap                         0x000000F0
 	#define	BA_ADPSCL_COEFF_CFG0_coeff_index               0x0001
 	#define	B16ADPSCL_COEFF_CFG0_coeff_index               0x0000
 	#define	LSb32ADPSCL_COEFF_CFG0_coeff_index                  8
 	#define	LSb16ADPSCL_COEFF_CFG0_coeff_index                  8
 	#define	bADPSCL_COEFF_CFG0_coeff_index               5
 	#define	MSK32ADPSCL_COEFF_CFG0_coeff_index                  0x00001F00
 	#define	BA_ADPSCL_COEFF_CFG0_coeff_hvsel               0x0001
 	#define	B16ADPSCL_COEFF_CFG0_coeff_hvsel               0x0000
 	#define	LSb32ADPSCL_COEFF_CFG0_coeff_hvsel                  13
 	#define	LSb16ADPSCL_COEFF_CFG0_coeff_hvsel                  13
 	#define	bADPSCL_COEFF_CFG0_coeff_hvsel               1
 	#define	MSK32ADPSCL_COEFF_CFG0_coeff_hvsel                  0x00002000
 	#define	BA_ADPSCL_COEFF_CFG0_coeffload                 0x0001
 	#define	B16ADPSCL_COEFF_CFG0_coeffload                 0x0000
 	#define	LSb32ADPSCL_COEFF_CFG0_coeffload                    14
 	#define	LSb16ADPSCL_COEFF_CFG0_coeffload                    14
 	#define	bADPSCL_COEFF_CFG0_coeffload                 1
 	#define	MSK32ADPSCL_COEFF_CFG0_coeffload                    0x00004000
 	#define	BA_ADPSCL_COEFF_CFG0_coeffread                 0x0001
 	#define	B16ADPSCL_COEFF_CFG0_coeffread                 0x0000
 	#define	LSb32ADPSCL_COEFF_CFG0_coeffread                    15
 	#define	LSb16ADPSCL_COEFF_CFG0_coeffread                    15
 	#define	bADPSCL_COEFF_CFG0_coeffread                 1
 	#define	MSK32ADPSCL_COEFF_CFG0_coeffread                    0x00008000
 	#define	RA_ADPSCL_COEFF_CFG1                           0x0004
 	#define	BA_ADPSCL_COEFF_CFG1_coeff0                    0x0004
 	#define	B16ADPSCL_COEFF_CFG1_coeff0                    0x0004
 	#define	LSb32ADPSCL_COEFF_CFG1_coeff0                       0
 	#define	LSb16ADPSCL_COEFF_CFG1_coeff0                       0
 	#define	bADPSCL_COEFF_CFG1_coeff0                    12
 	#define	MSK32ADPSCL_COEFF_CFG1_coeff0                       0x00000FFF
 	#define	BA_ADPSCL_COEFF_CFG1_coeff1                    0x0005
 	#define	B16ADPSCL_COEFF_CFG1_coeff1                    0x0004
 	#define	LSb32ADPSCL_COEFF_CFG1_coeff1                       12
 	#define	LSb16ADPSCL_COEFF_CFG1_coeff1                       12
 	#define	bADPSCL_COEFF_CFG1_coeff1                    12
 	#define	MSK32ADPSCL_COEFF_CFG1_coeff1                       0x00FFF000
 	#define	RA_ADPSCL_COEFF_CFG2                           0x0008
 	#define	BA_ADPSCL_COEFF_CFG2_coeff2                    0x0008
 	#define	B16ADPSCL_COEFF_CFG2_coeff2                    0x0008
 	#define	LSb32ADPSCL_COEFF_CFG2_coeff2                       0
 	#define	LSb16ADPSCL_COEFF_CFG2_coeff2                       0
 	#define	bADPSCL_COEFF_CFG2_coeff2                    12
 	#define	MSK32ADPSCL_COEFF_CFG2_coeff2                       0x00000FFF
 	#define	BA_ADPSCL_COEFF_CFG2_coeff3                    0x0009
 	#define	B16ADPSCL_COEFF_CFG2_coeff3                    0x0008
 	#define	LSb32ADPSCL_COEFF_CFG2_coeff3                       12
 	#define	LSb16ADPSCL_COEFF_CFG2_coeff3                       12
 	#define	bADPSCL_COEFF_CFG2_coeff3                    12
 	#define	MSK32ADPSCL_COEFF_CFG2_coeff3                       0x00FFF000
 	#define	RA_ADPSCL_COEFF_CFG3                           0x000C
 	#define	BA_ADPSCL_COEFF_CFG3_coeff4                    0x000C
 	#define	B16ADPSCL_COEFF_CFG3_coeff4                    0x000C
 	#define	LSb32ADPSCL_COEFF_CFG3_coeff4                       0
 	#define	LSb16ADPSCL_COEFF_CFG3_coeff4                       0
 	#define	bADPSCL_COEFF_CFG3_coeff4                    12
 	#define	MSK32ADPSCL_COEFF_CFG3_coeff4                       0x00000FFF
 	#define	BA_ADPSCL_COEFF_CFG3_coeff5                    0x000D
 	#define	B16ADPSCL_COEFF_CFG3_coeff5                    0x000C
 	#define	LSb32ADPSCL_COEFF_CFG3_coeff5                       12
 	#define	LSb16ADPSCL_COEFF_CFG3_coeff5                       12
 	#define	bADPSCL_COEFF_CFG3_coeff5                    12
 	#define	MSK32ADPSCL_COEFF_CFG3_coeff5                       0x00FFF000
 	#define	RA_ADPSCL_COEFF_CFG4                           0x0010
 	#define	BA_ADPSCL_COEFF_CFG4_coeff6                    0x0010
 	#define	B16ADPSCL_COEFF_CFG4_coeff6                    0x0010
 	#define	LSb32ADPSCL_COEFF_CFG4_coeff6                       0
 	#define	LSb16ADPSCL_COEFF_CFG4_coeff6                       0
 	#define	bADPSCL_COEFF_CFG4_coeff6                    12
 	#define	MSK32ADPSCL_COEFF_CFG4_coeff6                       0x00000FFF
 	#define	BA_ADPSCL_COEFF_CFG4_coeff7                    0x0011
 	#define	B16ADPSCL_COEFF_CFG4_coeff7                    0x0010
 	#define	LSb32ADPSCL_COEFF_CFG4_coeff7                       12
 	#define	LSb16ADPSCL_COEFF_CFG4_coeff7                       12
 	#define	bADPSCL_COEFF_CFG4_coeff7                    12
 	#define	MSK32ADPSCL_COEFF_CFG4_coeff7                       0x00FFF000
 	#define	RA_ADPSCL_COEFF_CFG5                           0x0014
 	#define	BA_ADPSCL_COEFF_CFG5_coeff8                    0x0014
 	#define	B16ADPSCL_COEFF_CFG5_coeff8                    0x0014
 	#define	LSb32ADPSCL_COEFF_CFG5_coeff8                       0
 	#define	LSb16ADPSCL_COEFF_CFG5_coeff8                       0
 	#define	bADPSCL_COEFF_CFG5_coeff8                    12
 	#define	MSK32ADPSCL_COEFF_CFG5_coeff8                       0x00000FFF
 	#define	BA_ADPSCL_COEFF_CFG5_coeff9                    0x0015
 	#define	B16ADPSCL_COEFF_CFG5_coeff9                    0x0014
 	#define	LSb32ADPSCL_COEFF_CFG5_coeff9                       12
 	#define	LSb16ADPSCL_COEFF_CFG5_coeff9                       12
 	#define	bADPSCL_COEFF_CFG5_coeff9                    12
 	#define	MSK32ADPSCL_COEFF_CFG5_coeff9                       0x00FFF000
 	#define	RA_ADPSCL_COEFF_CFG6                           0x0018
 	#define	BA_ADPSCL_COEFF_CFG6_coeff10                   0x0018
 	#define	B16ADPSCL_COEFF_CFG6_coeff10                   0x0018
 	#define	LSb32ADPSCL_COEFF_CFG6_coeff10                      0
 	#define	LSb16ADPSCL_COEFF_CFG6_coeff10                      0
 	#define	bADPSCL_COEFF_CFG6_coeff10                   12
 	#define	MSK32ADPSCL_COEFF_CFG6_coeff10                      0x00000FFF
 	#define	BA_ADPSCL_COEFF_CFG6_coeff11                   0x0019
 	#define	B16ADPSCL_COEFF_CFG6_coeff11                   0x0018
 	#define	LSb32ADPSCL_COEFF_CFG6_coeff11                      12
 	#define	LSb16ADPSCL_COEFF_CFG6_coeff11                      12
 	#define	bADPSCL_COEFF_CFG6_coeff11                   12
 	#define	MSK32ADPSCL_COEFF_CFG6_coeff11                      0x00FFF000
 	#define	RA_ADPSCL_FRC_CFG0                             0x0000
 	#define	BA_ADPSCL_FRC_CFG0_sclclk_ctrl                 0x0000
 	#define	B16ADPSCL_FRC_CFG0_sclclk_ctrl                 0x0000
 	#define	LSb32ADPSCL_FRC_CFG0_sclclk_ctrl                    0
 	#define	LSb16ADPSCL_FRC_CFG0_sclclk_ctrl                    0
 	#define	bADPSCL_FRC_CFG0_sclclk_ctrl                 8
 	#define	MSK32ADPSCL_FRC_CFG0_sclclk_ctrl                    0x000000FF
 	#define	BA_ADPSCL_FRC_CFG0_sclclk_ctrl1                0x0001
 	#define	B16ADPSCL_FRC_CFG0_sclclk_ctrl1                0x0000
 	#define	LSb32ADPSCL_FRC_CFG0_sclclk_ctrl1                   8
 	#define	LSb16ADPSCL_FRC_CFG0_sclclk_ctrl1                   8
 	#define	bADPSCL_FRC_CFG0_sclclk_ctrl1                8
 	#define	MSK32ADPSCL_FRC_CFG0_sclclk_ctrl1                   0x0000FF00
 	#define	BA_ADPSCL_FRC_CFG0_ctrl0                       0x0002
 	#define	B16ADPSCL_FRC_CFG0_ctrl0                       0x0002
 	#define	LSb32ADPSCL_FRC_CFG0_ctrl0                          16
 	#define	LSb16ADPSCL_FRC_CFG0_ctrl0                          0
 	#define	bADPSCL_FRC_CFG0_ctrl0                       8
 	#define	MSK32ADPSCL_FRC_CFG0_ctrl0                          0x00FF0000
 	#define	BA_ADPSCL_FRC_CFG0_ctrl1                       0x0003
 	#define	B16ADPSCL_FRC_CFG0_ctrl1                       0x0002
 	#define	LSb32ADPSCL_FRC_CFG0_ctrl1                          24
 	#define	LSb16ADPSCL_FRC_CFG0_ctrl1                          8
 	#define	bADPSCL_FRC_CFG0_ctrl1                       8
 	#define	MSK32ADPSCL_FRC_CFG0_ctrl1                          0xFF000000
 	#define	RA_ADPSCL_FRC_CFG1                             0x0004
 	#define	BA_ADPSCL_FRC_CFG1_ctrl2                       0x0004
 	#define	B16ADPSCL_FRC_CFG1_ctrl2                       0x0004
 	#define	LSb32ADPSCL_FRC_CFG1_ctrl2                          0
 	#define	LSb16ADPSCL_FRC_CFG1_ctrl2                          0
 	#define	bADPSCL_FRC_CFG1_ctrl2                       8
 	#define	MSK32ADPSCL_FRC_CFG1_ctrl2                          0x000000FF
 	#define	BA_ADPSCL_FRC_CFG1_dly_frst_de                 0x0005
 	#define	B16ADPSCL_FRC_CFG1_dly_frst_de                 0x0004
 	#define	LSb32ADPSCL_FRC_CFG1_dly_frst_de                    8
 	#define	LSb16ADPSCL_FRC_CFG1_dly_frst_de                    8
 	#define	bADPSCL_FRC_CFG1_dly_frst_de                 8
 	#define	MSK32ADPSCL_FRC_CFG1_dly_frst_de                    0x0000FF00
 	#define	BA_ADPSCL_FRC_CFG1_dly_de_lrst                 0x0006
 	#define	B16ADPSCL_FRC_CFG1_dly_de_lrst                 0x0006
 	#define	LSb32ADPSCL_FRC_CFG1_dly_de_lrst                    16
 	#define	LSb16ADPSCL_FRC_CFG1_dly_de_lrst                    0
 	#define	bADPSCL_FRC_CFG1_dly_de_lrst                 10
 	#define	MSK32ADPSCL_FRC_CFG1_dly_de_lrst                    0x03FF0000
 	#define	RA_ADPSCL_FRC_CFG2                             0x0008
 	#define	BA_ADPSCL_FRC_CFG2_bevres                      0x0008
 	#define	B16ADPSCL_FRC_CFG2_bevres                      0x0008
 	#define	LSb32ADPSCL_FRC_CFG2_bevres                         0
 	#define	LSb16ADPSCL_FRC_CFG2_bevres                         0
 	#define	bADPSCL_FRC_CFG2_bevres                      12
 	#define	MSK32ADPSCL_FRC_CFG2_bevres                         0x00000FFF
 	#define	BA_ADPSCL_FRC_CFG2_fevres                      0x0009
 	#define	B16ADPSCL_FRC_CFG2_fevres                      0x0008
 	#define	LSb32ADPSCL_FRC_CFG2_fevres                         12
 	#define	LSb16ADPSCL_FRC_CFG2_fevres                         12
 	#define	bADPSCL_FRC_CFG2_fevres                      12
 	#define	MSK32ADPSCL_FRC_CFG2_fevres                         0x00FFF000
 	#define	BA_ADPSCL_FRC_CFG2_dly_lrst_de                 0x000B
 	#define	B16ADPSCL_FRC_CFG2_dly_lrst_de                 0x000A
 	#define	LSb32ADPSCL_FRC_CFG2_dly_lrst_de                    24
 	#define	LSb16ADPSCL_FRC_CFG2_dly_lrst_de                    8
 	#define	bADPSCL_FRC_CFG2_dly_lrst_de                 8
 	#define	MSK32ADPSCL_FRC_CFG2_dly_lrst_de                    0xFF000000
 	#define	RA_ADPSCL_FRC_CFG3                             0x000C
 	#define	BA_ADPSCL_FRC_CFG3_behres                      0x000C
 	#define	B16ADPSCL_FRC_CFG3_behres                      0x000C
 	#define	LSb32ADPSCL_FRC_CFG3_behres                         0
 	#define	LSb16ADPSCL_FRC_CFG3_behres                         0
 	#define	bADPSCL_FRC_CFG3_behres                      13
 	#define	MSK32ADPSCL_FRC_CFG3_behres                         0x00001FFF
 	#define	BA_ADPSCL_FRC_CFG3_clnt_ctrl                   0x000D
 	#define	B16ADPSCL_FRC_CFG3_clnt_ctrl                   0x000C
 	#define	LSb32ADPSCL_FRC_CFG3_clnt_ctrl                      13
 	#define	LSb16ADPSCL_FRC_CFG3_clnt_ctrl                      13
 	#define	bADPSCL_FRC_CFG3_clnt_ctrl                   2
 	#define	MSK32ADPSCL_FRC_CFG3_clnt_ctrl                      0x00006000
 	#define	BA_ADPSCL_FRC_CFG3_ctrl                        0x000D
 	#define	B16ADPSCL_FRC_CFG3_ctrl                        0x000C
 	#define	LSb32ADPSCL_FRC_CFG3_ctrl                           15
 	#define	LSb16ADPSCL_FRC_CFG3_ctrl                           15
 	#define	bADPSCL_FRC_CFG3_ctrl                        8
 	#define	MSK32ADPSCL_FRC_CFG3_ctrl                           0x007F8000
 	#define	BA_ADPSCL_FRC_CFG3_rff_ctrl                    0x000E
 	#define	B16ADPSCL_FRC_CFG3_rff_ctrl                    0x000E
 	#define	LSb32ADPSCL_FRC_CFG3_rff_ctrl                       23
 	#define	LSb16ADPSCL_FRC_CFG3_rff_ctrl                       7
 	#define	bADPSCL_FRC_CFG3_rff_ctrl                    8
 	#define	MSK32ADPSCL_FRC_CFG3_rff_ctrl                       0x7F800000
 	#define	RA_ADPSCL_FRC_CFG4                             0x0010
 	#define	BA_ADPSCL_FRC_CFG4_ols                         0x0010
 	#define	B16ADPSCL_FRC_CFG4_ols                         0x0010
 	#define	LSb32ADPSCL_FRC_CFG4_ols                            0
 	#define	LSb16ADPSCL_FRC_CFG4_ols                            0
 	#define	bADPSCL_FRC_CFG4_ols                         1
 	#define	MSK32ADPSCL_FRC_CFG4_ols                            0x00000001
 	#define	BA_ADPSCL_FRC_CFG4_wclient                     0x0010
 	#define	B16ADPSCL_FRC_CFG4_wclient                     0x0010
 	#define	LSb32ADPSCL_FRC_CFG4_wclient                        1
 	#define	LSb16ADPSCL_FRC_CFG4_wclient                        1
 	#define	bADPSCL_FRC_CFG4_wclient                     1
 	#define	MSK32ADPSCL_FRC_CFG4_wclient                        0x00000002
 	#define	BA_ADPSCL_FRC_CFG4_luma_key_en                 0x0010
 	#define	B16ADPSCL_FRC_CFG4_luma_key_en                 0x0010
 	#define	LSb32ADPSCL_FRC_CFG4_luma_key_en                    2
 	#define	LSb16ADPSCL_FRC_CFG4_luma_key_en                    2
 	#define	bADPSCL_FRC_CFG4_luma_key_en                 1
 	#define	MSK32ADPSCL_FRC_CFG4_luma_key_en                    0x00000004
 	#define	BA_ADPSCL_FRC_CFG4_luma_key_min                0x0010
 	#define	B16ADPSCL_FRC_CFG4_luma_key_min                0x0010
 	#define	LSb32ADPSCL_FRC_CFG4_luma_key_min                   3
 	#define	LSb16ADPSCL_FRC_CFG4_luma_key_min                   3
 	#define	bADPSCL_FRC_CFG4_luma_key_min                10
 	#define	MSK32ADPSCL_FRC_CFG4_luma_key_min                   0x00001FF8
 	#define	BA_ADPSCL_FRC_CFG4_luma_key_max                0x0011
 	#define	B16ADPSCL_FRC_CFG4_luma_key_max                0x0010
 	#define	LSb32ADPSCL_FRC_CFG4_luma_key_max                   13
 	#define	LSb16ADPSCL_FRC_CFG4_luma_key_max                   13
 	#define	bADPSCL_FRC_CFG4_luma_key_max                10
 	#define	MSK32ADPSCL_FRC_CFG4_luma_key_max                   0x007FE000
 	#define	RA_ADPSCL_FRC_CFG5                             0x0014
 	#define	BA_ADPSCL_FRC_CFG5_al_en_hit_al                0x0014
 	#define	B16ADPSCL_FRC_CFG5_al_en_hit_al                0x0014
 	#define	LSb32ADPSCL_FRC_CFG5_al_en_hit_al                   0
 	#define	LSb16ADPSCL_FRC_CFG5_al_en_hit_al                   0
 	#define	bADPSCL_FRC_CFG5_al_en_hit_al                10
 	#define	MSK32ADPSCL_FRC_CFG5_al_en_hit_al                   0x000003FF
 	#define	BA_ADPSCL_FRC_CFG5_al_en_non_hit_al            0x0015
 	#define	B16ADPSCL_FRC_CFG5_al_en_non_hit_al            0x0014
 	#define	LSb32ADPSCL_FRC_CFG5_al_en_non_hit_al               10
 	#define	LSb16ADPSCL_FRC_CFG5_al_en_non_hit_al               10
 	#define	bADPSCL_FRC_CFG5_al_en_non_hit_al            12
 	#define	MSK32ADPSCL_FRC_CFG5_al_en_non_hit_al               0x003FFC00
 	#define	RA_ADPSCL_FRC_CFG6                             0x0018
 	#define	BA_ADPSCL_FRC_CFG6_al_out_threshold            0x0018
 	#define	B16ADPSCL_FRC_CFG6_al_out_threshold            0x0018
 	#define	LSb32ADPSCL_FRC_CFG6_al_out_threshold               0
 	#define	LSb16ADPSCL_FRC_CFG6_al_out_threshold               0
 	#define	bADPSCL_FRC_CFG6_al_out_threshold            10
 	#define	MSK32ADPSCL_FRC_CFG6_al_out_threshold               0x000003FF
 	#define	BA_ADPSCL_FRC_CFG6_al_out_zeroluma             0x0019
 	#define	B16ADPSCL_FRC_CFG6_al_out_zeroluma             0x0018
 	#define	LSb32ADPSCL_FRC_CFG6_al_out_zeroluma                10
 	#define	LSb16ADPSCL_FRC_CFG6_al_out_zeroluma                10
 	#define	bADPSCL_FRC_CFG6_al_out_zeroluma             10
 	#define	MSK32ADPSCL_FRC_CFG6_al_out_zeroluma                0x000FFC00
 	#define	RA_ADPSCL_DNS_CFG0                             0x0000
 	#define	BA_ADPSCL_DNS_CFG0_c0                          0x0000
 	#define	B16ADPSCL_DNS_CFG0_c0                          0x0000
 	#define	LSb32ADPSCL_DNS_CFG0_c0                             0
 	#define	LSb16ADPSCL_DNS_CFG0_c0                             0
 	#define	bADPSCL_DNS_CFG0_c0                          13
 	#define	MSK32ADPSCL_DNS_CFG0_c0                             0x00001FFF
 	#define	BA_ADPSCL_DNS_CFG0_c1                          0x0001
 	#define	B16ADPSCL_DNS_CFG0_c1                          0x0000
 	#define	LSb32ADPSCL_DNS_CFG0_c1                             13
 	#define	LSb16ADPSCL_DNS_CFG0_c1                             13
 	#define	bADPSCL_DNS_CFG0_c1                          13
 	#define	MSK32ADPSCL_DNS_CFG0_c1                             0x03FFE000
 	#define	RA_ADPSCL_DNS_CFG1                             0x0004
 	#define	BA_ADPSCL_DNS_CFG1_c2                          0x0004
 	#define	B16ADPSCL_DNS_CFG1_c2                          0x0004
 	#define	LSb32ADPSCL_DNS_CFG1_c2                             0
 	#define	LSb16ADPSCL_DNS_CFG1_c2                             0
 	#define	bADPSCL_DNS_CFG1_c2                          13
 	#define	MSK32ADPSCL_DNS_CFG1_c2                             0x00001FFF
 	#define	BA_ADPSCL_DNS_CFG1_c3                          0x0005
 	#define	B16ADPSCL_DNS_CFG1_c3                          0x0004
 	#define	LSb32ADPSCL_DNS_CFG1_c3                             13
 	#define	LSb16ADPSCL_DNS_CFG1_c3                             13
 	#define	bADPSCL_DNS_CFG1_c3                          13
 	#define	MSK32ADPSCL_DNS_CFG1_c3                             0x03FFE000
 	#define	RA_ADPSCL_DNS_CFG2                             0x0008
 	#define	BA_ADPSCL_DNS_CFG2_c4                          0x0008
 	#define	B16ADPSCL_DNS_CFG2_c4                          0x0008
 	#define	LSb32ADPSCL_DNS_CFG2_c4                             0
 	#define	LSb16ADPSCL_DNS_CFG2_c4                             0
 	#define	bADPSCL_DNS_CFG2_c4                          13
 	#define	MSK32ADPSCL_DNS_CFG2_c4                             0x00001FFF
 	#define	BA_ADPSCL_DNS_CFG2_c5                          0x0009
 	#define	B16ADPSCL_DNS_CFG2_c5                          0x0008
 	#define	LSb32ADPSCL_DNS_CFG2_c5                             13
 	#define	LSb16ADPSCL_DNS_CFG2_c5                             13
 	#define	bADPSCL_DNS_CFG2_c5                          13
 	#define	MSK32ADPSCL_DNS_CFG2_c5                             0x03FFE000
 	#define	RA_ADPSCL_UPS_CFG0                             0x0000
 	#define	BA_ADPSCL_UPS_CFG0_c0                          0x0000
 	#define	B16ADPSCL_UPS_CFG0_c0                          0x0000
 	#define	LSb32ADPSCL_UPS_CFG0_c0                             0
 	#define	LSb16ADPSCL_UPS_CFG0_c0                             0
 	#define	bADPSCL_UPS_CFG0_c0                          13
 	#define	MSK32ADPSCL_UPS_CFG0_c0                             0x00001FFF
 	#define	BA_ADPSCL_UPS_CFG0_c1                          0x0001
 	#define	B16ADPSCL_UPS_CFG0_c1                          0x0000
 	#define	LSb32ADPSCL_UPS_CFG0_c1                             13
 	#define	LSb16ADPSCL_UPS_CFG0_c1                             13
 	#define	bADPSCL_UPS_CFG0_c1                          13
 	#define	MSK32ADPSCL_UPS_CFG0_c1                             0x03FFE000
 	#define	RA_ADPSCL_UPS_CFG1                             0x0004
 	#define	BA_ADPSCL_UPS_CFG1_c2                          0x0004
 	#define	B16ADPSCL_UPS_CFG1_c2                          0x0004
 	#define	LSb32ADPSCL_UPS_CFG1_c2                             0
 	#define	LSb16ADPSCL_UPS_CFG1_c2                             0
 	#define	bADPSCL_UPS_CFG1_c2                          13
 	#define	MSK32ADPSCL_UPS_CFG1_c2                             0x00001FFF
 	#define	BA_ADPSCL_UPS_CFG1_c3                          0x0005
 	#define	B16ADPSCL_UPS_CFG1_c3                          0x0004
 	#define	LSb32ADPSCL_UPS_CFG1_c3                             13
 	#define	LSb16ADPSCL_UPS_CFG1_c3                             13
 	#define	bADPSCL_UPS_CFG1_c3                          13
 	#define	MSK32ADPSCL_UPS_CFG1_c3                             0x03FFE000
 	#define	RA_ADPSCL_UPS_CFG2                             0x0008
 	#define	BA_ADPSCL_UPS_CFG2_c4                          0x0008
 	#define	B16ADPSCL_UPS_CFG2_c4                          0x0008
 	#define	LSb32ADPSCL_UPS_CFG2_c4                             0
 	#define	LSb16ADPSCL_UPS_CFG2_c4                             0
 	#define	bADPSCL_UPS_CFG2_c4                          13
 	#define	MSK32ADPSCL_UPS_CFG2_c4                             0x00001FFF
 	#define	BA_ADPSCL_UPS_CFG2_c5                          0x0009
 	#define	B16ADPSCL_UPS_CFG2_c5                          0x0008
 	#define	LSb32ADPSCL_UPS_CFG2_c5                             13
 	#define	LSb16ADPSCL_UPS_CFG2_c5                             13
 	#define	bADPSCL_UPS_CFG2_c5                          13
 	#define	MSK32ADPSCL_UPS_CFG2_c5                             0x03FFE000
 	#define	RA_ADPSCL_UPS_CFG3                             0x000C
 	#define	BA_ADPSCL_UPS_CFG3_c6                          0x000C
 	#define	B16ADPSCL_UPS_CFG3_c6                          0x000C
 	#define	LSb32ADPSCL_UPS_CFG3_c6                             0
 	#define	LSb16ADPSCL_UPS_CFG3_c6                             0
 	#define	bADPSCL_UPS_CFG3_c6                          13
 	#define	MSK32ADPSCL_UPS_CFG3_c6                             0x00001FFF
 	#define	RA_ADPSCL_CSC_CFG0                             0x0000
 	#define	BA_ADPSCL_CSC_CFG0_c0_sel                      0x0000
 	#define	B16ADPSCL_CSC_CFG0_c0_sel                      0x0000
 	#define	LSb32ADPSCL_CSC_CFG0_c0_sel                         0
 	#define	LSb16ADPSCL_CSC_CFG0_c0_sel                         0
 	#define	bADPSCL_CSC_CFG0_c0_sel                      14
 	#define	MSK32ADPSCL_CSC_CFG0_c0_sel                         0x00003FFF
 	#define	BA_ADPSCL_CSC_CFG0_c1_sel                      0x0001
 	#define	B16ADPSCL_CSC_CFG0_c1_sel                      0x0000
 	#define	LSb32ADPSCL_CSC_CFG0_c1_sel                         14
 	#define	LSb16ADPSCL_CSC_CFG0_c1_sel                         14
 	#define	bADPSCL_CSC_CFG0_c1_sel                      14
 	#define	MSK32ADPSCL_CSC_CFG0_c1_sel                         0x0FFFC000
 	#define	RA_ADPSCL_CSC_CFG1                             0x0004
 	#define	BA_ADPSCL_CSC_CFG1_c2_sel                      0x0004
 	#define	B16ADPSCL_CSC_CFG1_c2_sel                      0x0004
 	#define	LSb32ADPSCL_CSC_CFG1_c2_sel                         0
 	#define	LSb16ADPSCL_CSC_CFG1_c2_sel                         0
 	#define	bADPSCL_CSC_CFG1_c2_sel                      14
 	#define	MSK32ADPSCL_CSC_CFG1_c2_sel                         0x00003FFF
 	#define	BA_ADPSCL_CSC_CFG1_c3_sel                      0x0005
 	#define	B16ADPSCL_CSC_CFG1_c3_sel                      0x0004
 	#define	LSb32ADPSCL_CSC_CFG1_c3_sel                         14
 	#define	LSb16ADPSCL_CSC_CFG1_c3_sel                         14
 	#define	bADPSCL_CSC_CFG1_c3_sel                      14
 	#define	MSK32ADPSCL_CSC_CFG1_c3_sel                         0x0FFFC000
 	#define	RA_ADPSCL_CSC_CFG2                             0x0008
 	#define	BA_ADPSCL_CSC_CFG2_c4_sel                      0x0008
 	#define	B16ADPSCL_CSC_CFG2_c4_sel                      0x0008
 	#define	LSb32ADPSCL_CSC_CFG2_c4_sel                         0
 	#define	LSb16ADPSCL_CSC_CFG2_c4_sel                         0
 	#define	bADPSCL_CSC_CFG2_c4_sel                      14
 	#define	MSK32ADPSCL_CSC_CFG2_c4_sel                         0x00003FFF
 	#define	BA_ADPSCL_CSC_CFG2_c5_sel                      0x0009
 	#define	B16ADPSCL_CSC_CFG2_c5_sel                      0x0008
 	#define	LSb32ADPSCL_CSC_CFG2_c5_sel                         14
 	#define	LSb16ADPSCL_CSC_CFG2_c5_sel                         14
 	#define	bADPSCL_CSC_CFG2_c5_sel                      14
 	#define	MSK32ADPSCL_CSC_CFG2_c5_sel                         0x0FFFC000
 	#define	RA_ADPSCL_CSC_CFG3                             0x000C
 	#define	BA_ADPSCL_CSC_CFG3_c6_sel                      0x000C
 	#define	B16ADPSCL_CSC_CFG3_c6_sel                      0x000C
 	#define	LSb32ADPSCL_CSC_CFG3_c6_sel                         0
 	#define	LSb16ADPSCL_CSC_CFG3_c6_sel                         0
 	#define	bADPSCL_CSC_CFG3_c6_sel                      14
 	#define	MSK32ADPSCL_CSC_CFG3_c6_sel                         0x00003FFF
 	#define	BA_ADPSCL_CSC_CFG3_c7_sel                      0x000D
 	#define	B16ADPSCL_CSC_CFG3_c7_sel                      0x000C
 	#define	LSb32ADPSCL_CSC_CFG3_c7_sel                         14
 	#define	LSb16ADPSCL_CSC_CFG3_c7_sel                         14
 	#define	bADPSCL_CSC_CFG3_c7_sel                      14
 	#define	MSK32ADPSCL_CSC_CFG3_c7_sel                         0x0FFFC000
 	#define	RA_ADPSCL_CSC_CFG4                             0x0010
 	#define	BA_ADPSCL_CSC_CFG4_c8_sel                      0x0010
 	#define	B16ADPSCL_CSC_CFG4_c8_sel                      0x0010
 	#define	LSb32ADPSCL_CSC_CFG4_c8_sel                         0
 	#define	LSb16ADPSCL_CSC_CFG4_c8_sel                         0
 	#define	bADPSCL_CSC_CFG4_c8_sel                      14
 	#define	MSK32ADPSCL_CSC_CFG4_c8_sel                         0x00003FFF
 	#define	BA_ADPSCL_CSC_CFG4_off0_sel                    0x0011
 	#define	B16ADPSCL_CSC_CFG4_off0_sel                    0x0010
 	#define	LSb32ADPSCL_CSC_CFG4_off0_sel                       14
 	#define	LSb16ADPSCL_CSC_CFG4_off0_sel                       14
 	#define	bADPSCL_CSC_CFG4_off0_sel                    16
 	#define	MSK32ADPSCL_CSC_CFG4_off0_sel                       0x3FFFC000
 	#define	RA_ADPSCL_CSC_CFG5                             0x0014
 	#define	BA_ADPSCL_CSC_CFG5_off1_sel                    0x0014
 	#define	B16ADPSCL_CSC_CFG5_off1_sel                    0x0014
 	#define	LSb32ADPSCL_CSC_CFG5_off1_sel                       0
 	#define	LSb16ADPSCL_CSC_CFG5_off1_sel                       0
 	#define	bADPSCL_CSC_CFG5_off1_sel                    16
 	#define	MSK32ADPSCL_CSC_CFG5_off1_sel                       0x0000FFFF
 	#define	BA_ADPSCL_CSC_CFG5_off2_sel                    0x0016
 	#define	B16ADPSCL_CSC_CFG5_off2_sel                    0x0016
 	#define	LSb32ADPSCL_CSC_CFG5_off2_sel                       16
 	#define	LSb16ADPSCL_CSC_CFG5_off2_sel                       0
 	#define	bADPSCL_CSC_CFG5_off2_sel                    16
 	#define	MSK32ADPSCL_CSC_CFG5_off2_sel                       0xFFFF0000
 	#define	RA_DITHER_CFG0                                 0x0000
 	#define	BA_DITHER_CFG0_mode                            0x0000
 	#define	B16DITHER_CFG0_mode                            0x0000
 	#define	LSb32DITHER_CFG0_mode                               0
 	#define	LSb16DITHER_CFG0_mode                               0
 	#define	bDITHER_CFG0_mode                            2
 	#define	MSK32DITHER_CFG0_mode                               0x00000003
 	#define	BA_DITHER_CFG0_ctrl                            0x0000
 	#define	B16DITHER_CFG0_ctrl                            0x0000
 	#define	LSb32DITHER_CFG0_ctrl                               2
 	#define	LSb16DITHER_CFG0_ctrl                               2
 	#define	bDITHER_CFG0_ctrl                            2
 	#define	MSK32DITHER_CFG0_ctrl                               0x0000000C
 	#define	RA_DNS444_422_CFG0                             0x0000
 	#define	BA_DNS444_422_CFG0_c4_14_11tap_regs            0x0000
 	#define	B16DNS444_422_CFG0_c4_14_11tap_regs            0x0000
 	#define	LSb32DNS444_422_CFG0_c4_14_11tap_regs               0
 	#define	LSb16DNS444_422_CFG0_c4_14_11tap_regs               0
 	#define	bDNS444_422_CFG0_c4_14_11tap_regs            13
 	#define	MSK32DNS444_422_CFG0_c4_14_11tap_regs               0x00001FFF
 	#define	BA_DNS444_422_CFG0_c5_13_11tap_regs            0x0001
 	#define	B16DNS444_422_CFG0_c5_13_11tap_regs            0x0000
 	#define	LSb32DNS444_422_CFG0_c5_13_11tap_regs               13
 	#define	LSb16DNS444_422_CFG0_c5_13_11tap_regs               13
 	#define	bDNS444_422_CFG0_c5_13_11tap_regs            13
 	#define	MSK32DNS444_422_CFG0_c5_13_11tap_regs               0x03FFE000
 	#define	RA_DNS444_422_CFG1                             0x0004
 	#define	BA_DNS444_422_CFG1_c6_12_11tap_regs            0x0004
 	#define	B16DNS444_422_CFG1_c6_12_11tap_regs            0x0004
 	#define	LSb32DNS444_422_CFG1_c6_12_11tap_regs               0
 	#define	LSb16DNS444_422_CFG1_c6_12_11tap_regs               0
 	#define	bDNS444_422_CFG1_c6_12_11tap_regs            13
 	#define	MSK32DNS444_422_CFG1_c6_12_11tap_regs               0x00001FFF
 	#define	BA_DNS444_422_CFG1_c7_11_11tap_regs            0x0005
 	#define	B16DNS444_422_CFG1_c7_11_11tap_regs            0x0004
 	#define	LSb32DNS444_422_CFG1_c7_11_11tap_regs               13
 	#define	LSb16DNS444_422_CFG1_c7_11_11tap_regs               13
 	#define	bDNS444_422_CFG1_c7_11_11tap_regs            13
 	#define	MSK32DNS444_422_CFG1_c7_11_11tap_regs               0x03FFE000
 	#define	RA_DNS444_422_CFG2                             0x0008
 	#define	BA_DNS444_422_CFG2_c8_10_11tap_regs            0x0008
 	#define	B16DNS444_422_CFG2_c8_10_11tap_regs            0x0008
 	#define	LSb32DNS444_422_CFG2_c8_10_11tap_regs               0
 	#define	LSb16DNS444_422_CFG2_c8_10_11tap_regs               0
 	#define	bDNS444_422_CFG2_c8_10_11tap_regs            13
 	#define	MSK32DNS444_422_CFG2_c8_10_11tap_regs               0x00001FFF
 	#define	BA_DNS444_422_CFG2_c9_11tap_regs               0x0009
 	#define	B16DNS444_422_CFG2_c9_11tap_regs               0x0008
 	#define	LSb32DNS444_422_CFG2_c9_11tap_regs                  13
 	#define	LSb16DNS444_422_CFG2_c9_11tap_regs                  13
 	#define	bDNS444_422_CFG2_c9_11tap_regs               13
 	#define	MSK32DNS444_422_CFG2_c9_11tap_regs                  0x03FFE000
 	#define	RA_DNS444_422_CFG3                             0x000C
 	#define	BA_DNS444_422_CFG3_c6_12_7tap_regs             0x000C
 	#define	B16DNS444_422_CFG3_c6_12_7tap_regs             0x000C
 	#define	LSb32DNS444_422_CFG3_c6_12_7tap_regs                0
 	#define	LSb16DNS444_422_CFG3_c6_12_7tap_regs                0
 	#define	bDNS444_422_CFG3_c6_12_7tap_regs             13
 	#define	MSK32DNS444_422_CFG3_c6_12_7tap_regs                0x00001FFF
 	#define	BA_DNS444_422_CFG3_c7_11_7tap_regs             0x000D
 	#define	B16DNS444_422_CFG3_c7_11_7tap_regs             0x000C
 	#define	LSb32DNS444_422_CFG3_c7_11_7tap_regs                13
 	#define	LSb16DNS444_422_CFG3_c7_11_7tap_regs                13
 	#define	bDNS444_422_CFG3_c7_11_7tap_regs             13
 	#define	MSK32DNS444_422_CFG3_c7_11_7tap_regs                0x03FFE000
 	#define	RA_DNS444_422_CFG4                             0x0010
 	#define	BA_DNS444_422_CFG4_c8_10_7tap_regs             0x0010
 	#define	B16DNS444_422_CFG4_c8_10_7tap_regs             0x0010
 	#define	LSb32DNS444_422_CFG4_c8_10_7tap_regs                0
 	#define	LSb16DNS444_422_CFG4_c8_10_7tap_regs                0
 	#define	bDNS444_422_CFG4_c8_10_7tap_regs             13
 	#define	MSK32DNS444_422_CFG4_c8_10_7tap_regs                0x00001FFF
 	#define	BA_DNS444_422_CFG4_c9_7tap_regs                0x0011
 	#define	B16DNS444_422_CFG4_c9_7tap_regs                0x0010
 	#define	LSb32DNS444_422_CFG4_c9_7tap_regs                   13
 	#define	LSb16DNS444_422_CFG4_c9_7tap_regs                   13
 	#define	bDNS444_422_CFG4_c9_7tap_regs                13
 	#define	MSK32DNS444_422_CFG4_c9_7tap_regs                   0x03FFE000
 	#define	RA_DNS444_422_CFG5                             0x0014
 	#define	BA_DNS444_422_CFG5_edge_thresh_y               0x0014
 	#define	B16DNS444_422_CFG5_edge_thresh_y               0x0014
 	#define	LSb32DNS444_422_CFG5_edge_thresh_y                  0
 	#define	LSb16DNS444_422_CFG5_edge_thresh_y                  0
 	#define	bDNS444_422_CFG5_edge_thresh_y               8
 	#define	MSK32DNS444_422_CFG5_edge_thresh_y                  0x000000FF
 	#define	BA_DNS444_422_CFG5_edge_thresh_c               0x0015
 	#define	B16DNS444_422_CFG5_edge_thresh_c               0x0014
 	#define	LSb32DNS444_422_CFG5_edge_thresh_c                  8
 	#define	LSb16DNS444_422_CFG5_edge_thresh_c                  8
 	#define	bDNS444_422_CFG5_edge_thresh_c               8
 	#define	MSK32DNS444_422_CFG5_edge_thresh_c                  0x0000FF00
 	#define	BA_DNS444_422_CFG5_mode_regs                   0x0016
 	#define	B16DNS444_422_CFG5_mode_regs                   0x0016
 	#define	LSb32DNS444_422_CFG5_mode_regs                      16
 	#define	LSb16DNS444_422_CFG5_mode_regs                      0
 	#define	bDNS444_422_CFG5_mode_regs                   2
 	#define	MSK32DNS444_422_CFG5_mode_regs                      0x00030000
 	#define	RA_DNS444_422_CFG6                             0x0018
 	#define	BA_DNS444_422_CFG6_yblank                      0x0018
 	#define	B16DNS444_422_CFG6_yblank                      0x0018
 	#define	LSb32DNS444_422_CFG6_yblank                         0
 	#define	LSb16DNS444_422_CFG6_yblank                         0
 	#define	bDNS444_422_CFG6_yblank                      12
 	#define	MSK32DNS444_422_CFG6_yblank                         0x00000FFF
 	#define	BA_DNS444_422_CFG6_cblank                      0x0019
 	#define	B16DNS444_422_CFG6_cblank                      0x0018
 	#define	LSb32DNS444_422_CFG6_cblank                         12
 	#define	LSb16DNS444_422_CFG6_cblank                         12
 	#define	bDNS444_422_CFG6_cblank                      12
 	#define	MSK32DNS444_422_CFG6_cblank                         0x00FFF000
 	#define	BA_DNS444_422_CFG6_use_blank_regs              0x001B
 	#define	B16DNS444_422_CFG6_use_blank_regs              0x001A
 	#define	LSb32DNS444_422_CFG6_use_blank_regs                 24
 	#define	LSb16DNS444_422_CFG6_use_blank_regs                 8
 	#define	bDNS444_422_CFG6_use_blank_regs              1
 	#define	MSK32DNS444_422_CFG6_use_blank_regs                 0x01000000
 	#define	RA_CSC_C14O24_CFG0                             0x0000
 	#define	BA_CSC_C14O24_CFG0_C0                          0x0000
 	#define	B16CSC_C14O24_CFG0_C0                          0x0000
 	#define	LSb32CSC_C14O24_CFG0_C0                             0
 	#define	LSb16CSC_C14O24_CFG0_C0                             0
 	#define	bCSC_C14O24_CFG0_C0                          14
 	#define	MSK32CSC_C14O24_CFG0_C0                             0x00003FFF
 	#define	BA_CSC_C14O24_CFG0_C1                          0x0001
 	#define	B16CSC_C14O24_CFG0_C1                          0x0000
 	#define	LSb32CSC_C14O24_CFG0_C1                             14
 	#define	LSb16CSC_C14O24_CFG0_C1                             14
 	#define	bCSC_C14O24_CFG0_C1                          14
 	#define	MSK32CSC_C14O24_CFG0_C1                             0x0FFFC000
 	#define	RA_CSC_C14O24_CFG1                             0x0004
 	#define	BA_CSC_C14O24_CFG1_C2                          0x0004
 	#define	B16CSC_C14O24_CFG1_C2                          0x0004
 	#define	LSb32CSC_C14O24_CFG1_C2                             0
 	#define	LSb16CSC_C14O24_CFG1_C2                             0
 	#define	bCSC_C14O24_CFG1_C2                          14
 	#define	MSK32CSC_C14O24_CFG1_C2                             0x00003FFF
 	#define	BA_CSC_C14O24_CFG1_C3                          0x0005
 	#define	B16CSC_C14O24_CFG1_C3                          0x0004
 	#define	LSb32CSC_C14O24_CFG1_C3                             14
 	#define	LSb16CSC_C14O24_CFG1_C3                             14
 	#define	bCSC_C14O24_CFG1_C3                          14
 	#define	MSK32CSC_C14O24_CFG1_C3                             0x0FFFC000
 	#define	RA_CSC_C14O24_CFG2                             0x0008
 	#define	BA_CSC_C14O24_CFG2_C4                          0x0008
 	#define	B16CSC_C14O24_CFG2_C4                          0x0008
 	#define	LSb32CSC_C14O24_CFG2_C4                             0
 	#define	LSb16CSC_C14O24_CFG2_C4                             0
 	#define	bCSC_C14O24_CFG2_C4                          14
 	#define	MSK32CSC_C14O24_CFG2_C4                             0x00003FFF
 	#define	BA_CSC_C14O24_CFG2_C5                          0x0009
 	#define	B16CSC_C14O24_CFG2_C5                          0x0008
 	#define	LSb32CSC_C14O24_CFG2_C5                             14
 	#define	LSb16CSC_C14O24_CFG2_C5                             14
 	#define	bCSC_C14O24_CFG2_C5                          14
 	#define	MSK32CSC_C14O24_CFG2_C5                             0x0FFFC000
 	#define	RA_CSC_C14O24_CFG3                             0x000C
 	#define	BA_CSC_C14O24_CFG3_C6                          0x000C
 	#define	B16CSC_C14O24_CFG3_C6                          0x000C
 	#define	LSb32CSC_C14O24_CFG3_C6                             0
 	#define	LSb16CSC_C14O24_CFG3_C6                             0
 	#define	bCSC_C14O24_CFG3_C6                          14
 	#define	MSK32CSC_C14O24_CFG3_C6                             0x00003FFF
 	#define	BA_CSC_C14O24_CFG3_C7                          0x000D
 	#define	B16CSC_C14O24_CFG3_C7                          0x000C
 	#define	LSb32CSC_C14O24_CFG3_C7                             14
 	#define	LSb16CSC_C14O24_CFG3_C7                             14
 	#define	bCSC_C14O24_CFG3_C7                          14
 	#define	MSK32CSC_C14O24_CFG3_C7                             0x0FFFC000
 	#define	RA_CSC_C14O24_CFG4                             0x0010
 	#define	BA_CSC_C14O24_CFG4_C8                          0x0010
 	#define	B16CSC_C14O24_CFG4_C8                          0x0010
 	#define	LSb32CSC_C14O24_CFG4_C8                             0
 	#define	LSb16CSC_C14O24_CFG4_C8                             0
 	#define	bCSC_C14O24_CFG4_C8                          14
 	#define	MSK32CSC_C14O24_CFG4_C8                             0x00003FFF
 	#define	RA_CSC_C14O24_CFG5                             0x0014
 	#define	BA_CSC_C14O24_CFG5_OFF1                        0x0014
 	#define	B16CSC_C14O24_CFG5_OFF1                        0x0014
 	#define	LSb32CSC_C14O24_CFG5_OFF1                           0
 	#define	LSb16CSC_C14O24_CFG5_OFF1                           0
 	#define	bCSC_C14O24_CFG5_OFF1                        24
 	#define	MSK32CSC_C14O24_CFG5_OFF1                           0x00FFFFFF
 	#define	RA_CSC_C14O24_CFG6                             0x0018
 	#define	BA_CSC_C14O24_CFG6_OFF2                        0x0018
 	#define	B16CSC_C14O24_CFG6_OFF2                        0x0018
 	#define	LSb32CSC_C14O24_CFG6_OFF2                           0
 	#define	LSb16CSC_C14O24_CFG6_OFF2                           0
 	#define	bCSC_C14O24_CFG6_OFF2                        24
 	#define	MSK32CSC_C14O24_CFG6_OFF2                           0x00FFFFFF
 	#define	RA_CSC_C14O24_CFG7                             0x001C
 	#define	BA_CSC_C14O24_CFG7_OFF3                        0x001C
 	#define	B16CSC_C14O24_CFG7_OFF3                        0x001C
 	#define	LSb32CSC_C14O24_CFG7_OFF3                           0
 	#define	LSb16CSC_C14O24_CFG7_OFF3                           0
 	#define	bCSC_C14O24_CFG7_OFF3                        24
 	#define	MSK32CSC_C14O24_CFG7_OFF3                           0x00FFFFFF
 	#define	RA_UPS_420_422_HDMI_10b_CFG0                   0x0000
 	#define	BA_UPS_420_422_HDMI_10b_CFG0_enable            0x0000
 	#define	B16UPS_420_422_HDMI_10b_CFG0_enable            0x0000
 	#define	LSb32UPS_420_422_HDMI_10b_CFG0_enable               0
 	#define	LSb16UPS_420_422_HDMI_10b_CFG0_enable               0
 	#define	bUPS_420_422_HDMI_10b_CFG0_enable            1
 	#define	MSK32UPS_420_422_HDMI_10b_CFG0_enable               0x00000001
 	#define	BA_UPS_420_422_HDMI_10b_CFG0_msbswap           0x0000
 	#define	B16UPS_420_422_HDMI_10b_CFG0_msbswap           0x0000
 	#define	LSb32UPS_420_422_HDMI_10b_CFG0_msbswap              1
 	#define	LSb16UPS_420_422_HDMI_10b_CFG0_msbswap              1
 	#define	bUPS_420_422_HDMI_10b_CFG0_msbswap           1
 	#define	MSK32UPS_420_422_HDMI_10b_CFG0_msbswap              0x00000002
 	#define	BA_UPS_420_422_HDMI_10b_CFG0_cswap_regs        0x0000
 	#define	B16UPS_420_422_HDMI_10b_CFG0_cswap_regs        0x0000
 	#define	LSb32UPS_420_422_HDMI_10b_CFG0_cswap_regs           2
 	#define	LSb16UPS_420_422_HDMI_10b_CFG0_cswap_regs           2
 	#define	bUPS_420_422_HDMI_10b_CFG0_cswap_regs        1
 	#define	MSK32UPS_420_422_HDMI_10b_CFG0_cswap_regs           0x00000004
 	#define	BA_UPS_420_422_HDMI_10b_CFG0_yshift_regs       0x0000
 	#define	B16UPS_420_422_HDMI_10b_CFG0_yshift_regs       0x0000
 	#define	LSb32UPS_420_422_HDMI_10b_CFG0_yshift_regs          3
 	#define	LSb16UPS_420_422_HDMI_10b_CFG0_yshift_regs          3
 	#define	bUPS_420_422_HDMI_10b_CFG0_yshift_regs       1
 	#define	MSK32UPS_420_422_HDMI_10b_CFG0_yshift_regs          0x00000008
 	#define	BA_UPS_420_422_HDMI_10b_CFG0_cshift_regs       0x0000
 	#define	B16UPS_420_422_HDMI_10b_CFG0_cshift_regs       0x0000
 	#define	LSb32UPS_420_422_HDMI_10b_CFG0_cshift_regs          4
 	#define	LSb16UPS_420_422_HDMI_10b_CFG0_cshift_regs          4
 	#define	bUPS_420_422_HDMI_10b_CFG0_cshift_regs       1
 	#define	MSK32UPS_420_422_HDMI_10b_CFG0_cshift_regs          0x00000010
 	#define	BA_UPS_420_422_HDMI_10b_CFG0_reserved          0x0000
 	#define	B16UPS_420_422_HDMI_10b_CFG0_reserved          0x0000
 	#define	LSb32UPS_420_422_HDMI_10b_CFG0_reserved             5
 	#define	LSb16UPS_420_422_HDMI_10b_CFG0_reserved             5
 	#define	bUPS_420_422_HDMI_10b_CFG0_reserved          1
 	#define	MSK32UPS_420_422_HDMI_10b_CFG0_reserved             0x00000020
 	#define	BA_UPS_420_422_HDMI_10b_CFG0_dat8_en           0x0000
 	#define	B16UPS_420_422_HDMI_10b_CFG0_dat8_en           0x0000
 	#define	LSb32UPS_420_422_HDMI_10b_CFG0_dat8_en              6
 	#define	LSb16UPS_420_422_HDMI_10b_CFG0_dat8_en              6
 	#define	bUPS_420_422_HDMI_10b_CFG0_dat8_en           1
 	#define	MSK32UPS_420_422_HDMI_10b_CFG0_dat8_en              0x00000040
 	#define	BA_UPS_420_422_HDMI_10b_CFG0_sft_rst           0x0000
 	#define	B16UPS_420_422_HDMI_10b_CFG0_sft_rst           0x0000
 	#define	LSb32UPS_420_422_HDMI_10b_CFG0_sft_rst              7
 	#define	LSb16UPS_420_422_HDMI_10b_CFG0_sft_rst              7
 	#define	bUPS_420_422_HDMI_10b_CFG0_sft_rst           1
 	#define	MSK32UPS_420_422_HDMI_10b_CFG0_sft_rst              0x00000080
 	#define	BA_UPS_420_422_HDMI_10b_CFG0_use_blank         0x0001
 	#define	B16UPS_420_422_HDMI_10b_CFG0_use_blank         0x0000
 	#define	LSb32UPS_420_422_HDMI_10b_CFG0_use_blank            8
 	#define	LSb16UPS_420_422_HDMI_10b_CFG0_use_blank            8
 	#define	bUPS_420_422_HDMI_10b_CFG0_use_blank         1
 	#define	MSK32UPS_420_422_HDMI_10b_CFG0_use_blank            0x00000100
 	#define	BA_UPS_420_422_HDMI_10b_CFG0_yblank_regs       0x0001
 	#define	B16UPS_420_422_HDMI_10b_CFG0_yblank_regs       0x0000
 	#define	LSb32UPS_420_422_HDMI_10b_CFG0_yblank_regs          9
 	#define	LSb16UPS_420_422_HDMI_10b_CFG0_yblank_regs          9
 	#define	bUPS_420_422_HDMI_10b_CFG0_yblank_regs       10
 	#define	MSK32UPS_420_422_HDMI_10b_CFG0_yblank_regs          0x0007FE00
 	#define	BA_UPS_420_422_HDMI_10b_CFG0_cblank_regs       0x0002
 	#define	B16UPS_420_422_HDMI_10b_CFG0_cblank_regs       0x0002
 	#define	LSb32UPS_420_422_HDMI_10b_CFG0_cblank_regs          19
 	#define	LSb16UPS_420_422_HDMI_10b_CFG0_cblank_regs          3
 	#define	bUPS_420_422_HDMI_10b_CFG0_cblank_regs       10
 	#define	MSK32UPS_420_422_HDMI_10b_CFG0_cblank_regs          0x1FF80000
 	#define	BA_UPS_420_422_HDMI_10b_CFG0_hdmi_to_sp_en     0x0003
 	#define	B16UPS_420_422_HDMI_10b_CFG0_hdmi_to_sp_en     0x0002
 	#define	LSb32UPS_420_422_HDMI_10b_CFG0_hdmi_to_sp_en        29
 	#define	LSb16UPS_420_422_HDMI_10b_CFG0_hdmi_to_sp_en        13
 	#define	bUPS_420_422_HDMI_10b_CFG0_hdmi_to_sp_en     1
 	#define	MSK32UPS_420_422_HDMI_10b_CFG0_hdmi_to_sp_en        0x20000000
 	#define	RA_UPS_420_422_HDMI_10b_CFG1                   0x0004
 	#define	BA_UPS_420_422_HDMI_10b_CFG1_ups_c0            0x0004
 	#define	B16UPS_420_422_HDMI_10b_CFG1_ups_c0            0x0004
 	#define	LSb32UPS_420_422_HDMI_10b_CFG1_ups_c0               0
 	#define	LSb16UPS_420_422_HDMI_10b_CFG1_ups_c0               0
 	#define	bUPS_420_422_HDMI_10b_CFG1_ups_c0            13
 	#define	MSK32UPS_420_422_HDMI_10b_CFG1_ups_c0               0x00001FFF
 	#define	BA_UPS_420_422_HDMI_10b_CFG1_ups_c1            0x0005
 	#define	B16UPS_420_422_HDMI_10b_CFG1_ups_c1            0x0004
 	#define	LSb32UPS_420_422_HDMI_10b_CFG1_ups_c1               13
 	#define	LSb16UPS_420_422_HDMI_10b_CFG1_ups_c1               13
 	#define	bUPS_420_422_HDMI_10b_CFG1_ups_c1            13
 	#define	MSK32UPS_420_422_HDMI_10b_CFG1_ups_c1               0x03FFE000
 	#define	RA_UPS_420_422_HDMI_10b_CFG2                   0x0008
 	#define	BA_UPS_420_422_HDMI_10b_CFG2_ups_c2            0x0008
 	#define	B16UPS_420_422_HDMI_10b_CFG2_ups_c2            0x0008
 	#define	LSb32UPS_420_422_HDMI_10b_CFG2_ups_c2               0
 	#define	LSb16UPS_420_422_HDMI_10b_CFG2_ups_c2               0
 	#define	bUPS_420_422_HDMI_10b_CFG2_ups_c2            13
 	#define	MSK32UPS_420_422_HDMI_10b_CFG2_ups_c2               0x00001FFF
 	#define	BA_UPS_420_422_HDMI_10b_CFG2_ups_c3            0x0009
 	#define	B16UPS_420_422_HDMI_10b_CFG2_ups_c3            0x0008
 	#define	LSb32UPS_420_422_HDMI_10b_CFG2_ups_c3               13
 	#define	LSb16UPS_420_422_HDMI_10b_CFG2_ups_c3               13
 	#define	bUPS_420_422_HDMI_10b_CFG2_ups_c3            13
 	#define	MSK32UPS_420_422_HDMI_10b_CFG2_ups_c3               0x03FFE000
 	#define	RA_UPS_420_422_HDMI_10b_CFG3                   0x000C
 	#define	BA_UPS_420_422_HDMI_10b_CFG3_ups_c4            0x000C
 	#define	B16UPS_420_422_HDMI_10b_CFG3_ups_c4            0x000C
 	#define	LSb32UPS_420_422_HDMI_10b_CFG3_ups_c4               0
 	#define	LSb16UPS_420_422_HDMI_10b_CFG3_ups_c4               0
 	#define	bUPS_420_422_HDMI_10b_CFG3_ups_c4            13
 	#define	MSK32UPS_420_422_HDMI_10b_CFG3_ups_c4               0x00001FFF
 	#define	BA_UPS_420_422_HDMI_10b_CFG3_ups_c5            0x000D
 	#define	B16UPS_420_422_HDMI_10b_CFG3_ups_c5            0x000C
 	#define	LSb32UPS_420_422_HDMI_10b_CFG3_ups_c5               13
 	#define	LSb16UPS_420_422_HDMI_10b_CFG3_ups_c5               13
 	#define	bUPS_420_422_HDMI_10b_CFG3_ups_c5            13
 	#define	MSK32UPS_420_422_HDMI_10b_CFG3_ups_c5               0x03FFE000
 	#define	RA_UPS_420_422_HDMI_10b_CFG4                   0x0010
 	#define	BA_UPS_420_422_HDMI_10b_CFG4_ups_c6            0x0010
 	#define	B16UPS_420_422_HDMI_10b_CFG4_ups_c6            0x0010
 	#define	LSb32UPS_420_422_HDMI_10b_CFG4_ups_c6               0
 	#define	LSb16UPS_420_422_HDMI_10b_CFG4_ups_c6               0
 	#define	bUPS_420_422_HDMI_10b_CFG4_ups_c6            13
 	#define	MSK32UPS_420_422_HDMI_10b_CFG4_ups_c6               0x00001FFF
 	#define	RA_UPS_420_422_HDMI_10b_CFG5                   0x0014
 	#define	BA_UPS_420_422_HDMI_10b_CFG5_hres_regs         0x0014
 	#define	B16UPS_420_422_HDMI_10b_CFG5_hres_regs         0x0014
 	#define	LSb32UPS_420_422_HDMI_10b_CFG5_hres_regs            0
 	#define	LSb16UPS_420_422_HDMI_10b_CFG5_hres_regs            0
 	#define	bUPS_420_422_HDMI_10b_CFG5_hres_regs         13
 	#define	MSK32UPS_420_422_HDMI_10b_CFG5_hres_regs            0x00001FFF
 	#define	BA_UPS_420_422_HDMI_10b_CFG5_htot_regs         0x0015
 	#define	B16UPS_420_422_HDMI_10b_CFG5_htot_regs         0x0014
 	#define	LSb32UPS_420_422_HDMI_10b_CFG5_htot_regs            13
 	#define	LSb16UPS_420_422_HDMI_10b_CFG5_htot_regs            13
 	#define	bUPS_420_422_HDMI_10b_CFG5_htot_regs         13
 	#define	MSK32UPS_420_422_HDMI_10b_CFG5_htot_regs            0x03FFE000
 	#define	BA_UPS_420_422_HDMI_10b_CFG5_auto_pixcnt       0x0017
 	#define	B16UPS_420_422_HDMI_10b_CFG5_auto_pixcnt       0x0016
 	#define	LSb32UPS_420_422_HDMI_10b_CFG5_auto_pixcnt          26
 	#define	LSb16UPS_420_422_HDMI_10b_CFG5_auto_pixcnt          10
 	#define	bUPS_420_422_HDMI_10b_CFG5_auto_pixcnt       1
 	#define	MSK32UPS_420_422_HDMI_10b_CFG5_auto_pixcnt          0x04000000
 	#define	RA_UPS_420_422_HDMI_10b_CFG6                   0x0018
 	#define	BA_UPS_420_422_HDMI_10b_CFG6_top_crop          0x0018
 	#define	B16UPS_420_422_HDMI_10b_CFG6_top_crop          0x0018
 	#define	LSb32UPS_420_422_HDMI_10b_CFG6_top_crop             0
 	#define	LSb16UPS_420_422_HDMI_10b_CFG6_top_crop             0
 	#define	bUPS_420_422_HDMI_10b_CFG6_top_crop          6
 	#define	MSK32UPS_420_422_HDMI_10b_CFG6_top_crop             0x0000003F
 	#define	BA_UPS_420_422_HDMI_10b_CFG6_bot_crop          0x0018
 	#define	B16UPS_420_422_HDMI_10b_CFG6_bot_crop          0x0018
 	#define	LSb32UPS_420_422_HDMI_10b_CFG6_bot_crop             6
 	#define	LSb16UPS_420_422_HDMI_10b_CFG6_bot_crop             6
 	#define	bUPS_420_422_HDMI_10b_CFG6_bot_crop          6
 	#define	MSK32UPS_420_422_HDMI_10b_CFG6_bot_crop             0x00000FC0
 	#define	BA_UPS_420_422_HDMI_10b_CFG6_left_crop         0x0019
 	#define	B16UPS_420_422_HDMI_10b_CFG6_left_crop         0x0018
 	#define	LSb32UPS_420_422_HDMI_10b_CFG6_left_crop            12
 	#define	LSb16UPS_420_422_HDMI_10b_CFG6_left_crop            12
 	#define	bUPS_420_422_HDMI_10b_CFG6_left_crop         6
 	#define	MSK32UPS_420_422_HDMI_10b_CFG6_left_crop            0x0003F000
 	#define	BA_UPS_420_422_HDMI_10b_CFG6_right_crop        0x001A
 	#define	B16UPS_420_422_HDMI_10b_CFG6_right_crop        0x001A
 	#define	LSb32UPS_420_422_HDMI_10b_CFG6_right_crop           18
 	#define	LSb16UPS_420_422_HDMI_10b_CFG6_right_crop           2
 	#define	bUPS_420_422_HDMI_10b_CFG6_right_crop        6
 	#define	MSK32UPS_420_422_HDMI_10b_CFG6_right_crop           0x00FC0000
 	#define	RA_UPS_420_422_HDMI_10b_CFG7                   0x001C
 	#define	BA_UPS_420_422_HDMI_10b_CFG7_vres_regs         0x001C
 	#define	B16UPS_420_422_HDMI_10b_CFG7_vres_regs         0x001C
 	#define	LSb32UPS_420_422_HDMI_10b_CFG7_vres_regs            0
 	#define	LSb16UPS_420_422_HDMI_10b_CFG7_vres_regs            0
 	#define	bUPS_420_422_HDMI_10b_CFG7_vres_regs         13
 	#define	MSK32UPS_420_422_HDMI_10b_CFG7_vres_regs            0x00001FFF
 	#define	RA_UPS_420_422_HDMI_10b_CFG8                   0x0020
 	#define	BA_UPS_420_422_HDMI_10b_CFG8_pdwn_regs         0x0020
 	#define	B16UPS_420_422_HDMI_10b_CFG8_pdwn_regs         0x0020
 	#define	LSb32UPS_420_422_HDMI_10b_CFG8_pdwn_regs            0
 	#define	LSb16UPS_420_422_HDMI_10b_CFG8_pdwn_regs            0
 	#define	bUPS_420_422_HDMI_10b_CFG8_pdwn_regs         1
 	#define	MSK32UPS_420_422_HDMI_10b_CFG8_pdwn_regs            0x00000001
 	#define	BA_UPS_420_422_HDMI_10b_CFG8_pdlvmc_regs       0x0020
 	#define	B16UPS_420_422_HDMI_10b_CFG8_pdlvmc_regs       0x0020
 	#define	LSb32UPS_420_422_HDMI_10b_CFG8_pdlvmc_regs          1
 	#define	LSb16UPS_420_422_HDMI_10b_CFG8_pdlvmc_regs          1
 	#define	bUPS_420_422_HDMI_10b_CFG8_pdlvmc_regs       1
 	#define	MSK32UPS_420_422_HDMI_10b_CFG8_pdlvmc_regs          0x00000002
 	#define	BA_UPS_420_422_HDMI_10b_CFG8_pdfvssm_regs      0x0020
 	#define	B16UPS_420_422_HDMI_10b_CFG8_pdfvssm_regs      0x0020
 	#define	LSb32UPS_420_422_HDMI_10b_CFG8_pdfvssm_regs         2
 	#define	LSb16UPS_420_422_HDMI_10b_CFG8_pdfvssm_regs         2
 	#define	bUPS_420_422_HDMI_10b_CFG8_pdfvssm_regs      1
 	#define	MSK32UPS_420_422_HDMI_10b_CFG8_pdfvssm_regs         0x00000004
 	#define	BA_UPS_420_422_HDMI_10b_CFG8_dpwr_regs         0x0020
 	#define	B16UPS_420_422_HDMI_10b_CFG8_dpwr_regs         0x0020
 	#define	LSb32UPS_420_422_HDMI_10b_CFG8_dpwr_regs            3
 	#define	LSb16UPS_420_422_HDMI_10b_CFG8_dpwr_regs            3
 	#define	bUPS_420_422_HDMI_10b_CFG8_dpwr_regs         2
 	#define	MSK32UPS_420_422_HDMI_10b_CFG8_dpwr_regs            0x00000018
 	#define	RA_PATGEN_CFG0                                 0x0000
 	#define	BA_PATGEN_CFG0_ihcntl                          0x0000
 	#define	B16PATGEN_CFG0_ihcntl                          0x0000
 	#define	LSb32PATGEN_CFG0_ihcntl                             0
 	#define	LSb16PATGEN_CFG0_ihcntl                             0
 	#define	bPATGEN_CFG0_ihcntl                          2
 	#define	MSK32PATGEN_CFG0_ihcntl                             0x00000003
 	#define	BA_PATGEN_CFG0_ivcntl                          0x0000
 	#define	B16PATGEN_CFG0_ivcntl                          0x0000
 	#define	LSb32PATGEN_CFG0_ivcntl                             2
 	#define	LSb16PATGEN_CFG0_ivcntl                             2
 	#define	bPATGEN_CFG0_ivcntl                          2
 	#define	MSK32PATGEN_CFG0_ivcntl                             0x0000000C
 	#define	BA_PATGEN_CFG0_ihpitch                         0x0000
 	#define	B16PATGEN_CFG0_ihpitch                         0x0000
 	#define	LSb32PATGEN_CFG0_ihpitch                            4
 	#define	LSb16PATGEN_CFG0_ihpitch                            4
 	#define	bPATGEN_CFG0_ihpitch                         8
 	#define	MSK32PATGEN_CFG0_ihpitch                            0x00000FF0
 	#define	BA_PATGEN_CFG0_ivpitch                         0x0001
 	#define	B16PATGEN_CFG0_ivpitch                         0x0000
 	#define	LSb32PATGEN_CFG0_ivpitch                            12
 	#define	LSb16PATGEN_CFG0_ivpitch                            12
 	#define	bPATGEN_CFG0_ivpitch                         8
 	#define	MSK32PATGEN_CFG0_ivpitch                            0x000FF000
 	#define	RA_PATGEN_CFG1                                 0x0004
 	#define	BA_PATGEN_CFG1_ucolor_hp                       0x0004
 	#define	B16PATGEN_CFG1_ucolor_hp                       0x0004
 	#define	LSb32PATGEN_CFG1_ucolor_hp                          0
 	#define	LSb16PATGEN_CFG1_ucolor_hp                          0
 	#define	bPATGEN_CFG1_ucolor_hp                       24
 	#define	MSK32PATGEN_CFG1_ucolor_hp                          0x00FFFFFF
 	#define	RA_PATGEN_CFG2                                 0x0008
 	#define	BA_PATGEN_CFG2_ucolor_vp                       0x0008
 	#define	B16PATGEN_CFG2_ucolor_vp                       0x0008
 	#define	LSb32PATGEN_CFG2_ucolor_vp                          0
 	#define	LSb16PATGEN_CFG2_ucolor_vp                          0
 	#define	bPATGEN_CFG2_ucolor_vp                       24
 	#define	MSK32PATGEN_CFG2_ucolor_vp                          0x00FFFFFF
 	#define	RA_PATGEN_CFG3                                 0x000C
 	#define	BA_PATGEN_CFG3_ufseed                          0x000C
 	#define	B16PATGEN_CFG3_ufseed                          0x000C
 	#define	LSb32PATGEN_CFG3_ufseed                             0
 	#define	LSb16PATGEN_CFG3_ufseed                             0
 	#define	bPATGEN_CFG3_ufseed                          24
 	#define	MSK32PATGEN_CFG3_ufseed                             0x00FFFFFF
 	#define	RA_PATGEN_CFG4                                 0x0010
 	#define	BA_PATGEN_CFG4_ihres                           0x0010
 	#define	B16PATGEN_CFG4_ihres                           0x0010
 	#define	LSb32PATGEN_CFG4_ihres                              0
 	#define	LSb16PATGEN_CFG4_ihres                              0
 	#define	bPATGEN_CFG4_ihres                           16
 	#define	MSK32PATGEN_CFG4_ihres                              0x0000FFFF
 	#define	BA_PATGEN_CFG4_ivres                           0x0012
 	#define	B16PATGEN_CFG4_ivres                           0x0012
 	#define	LSb32PATGEN_CFG4_ivres                              16
 	#define	LSb16PATGEN_CFG4_ivres                              0
 	#define	bPATGEN_CFG4_ivres                           16
 	#define	MSK32PATGEN_CFG4_ivres                              0xFFFF0000
 	#define	RA_PATGEN_CFG5                                 0x0014
 	#define	BA_PATGEN_CFG5_ihtot                           0x0014
 	#define	B16PATGEN_CFG5_ihtot                           0x0014
 	#define	LSb32PATGEN_CFG5_ihtot                              0
 	#define	LSb16PATGEN_CFG5_ihtot                              0
 	#define	bPATGEN_CFG5_ihtot                           16
 	#define	MSK32PATGEN_CFG5_ihtot                              0x0000FFFF
 	#define	BA_PATGEN_CFG5_ivtot                           0x0016
 	#define	B16PATGEN_CFG5_ivtot                           0x0016
 	#define	LSb32PATGEN_CFG5_ivtot                              16
 	#define	LSb16PATGEN_CFG5_ivtot                              0
 	#define	bPATGEN_CFG5_ivtot                           16
 	#define	MSK32PATGEN_CFG5_ivtot                              0xFFFF0000
 	#define	RA_PATGEN_CFG6                                 0x0018
 	#define	BA_PATGEN_CFG6_ihsw                            0x0018
 	#define	B16PATGEN_CFG6_ihsw                            0x0018
 	#define	LSb32PATGEN_CFG6_ihsw                               0
 	#define	LSb16PATGEN_CFG6_ihsw                               0
 	#define	bPATGEN_CFG6_ihsw                            16
 	#define	MSK32PATGEN_CFG6_ihsw                               0x0000FFFF
 	#define	BA_PATGEN_CFG6_ivsw                            0x001A
 	#define	B16PATGEN_CFG6_ivsw                            0x001A
 	#define	LSb32PATGEN_CFG6_ivsw                               16
 	#define	LSb16PATGEN_CFG6_ivsw                               0
 	#define	bPATGEN_CFG6_ivsw                            16
 	#define	MSK32PATGEN_CFG6_ivsw                               0xFFFF0000
 	#define	RA_PATGEN_CFG7                                 0x001C
 	#define	BA_PATGEN_CFG7_ihst                            0x001C
 	#define	B16PATGEN_CFG7_ihst                            0x001C
 	#define	LSb32PATGEN_CFG7_ihst                               0
 	#define	LSb16PATGEN_CFG7_ihst                               0
 	#define	bPATGEN_CFG7_ihst                            16
 	#define	MSK32PATGEN_CFG7_ihst                               0x0000FFFF
 	#define	BA_PATGEN_CFG7_ivst                            0x001E
 	#define	B16PATGEN_CFG7_ivst                            0x001E
 	#define	LSb32PATGEN_CFG7_ivst                               16
 	#define	LSb16PATGEN_CFG7_ivst                               0
 	#define	bPATGEN_CFG7_ivst                            16
 	#define	MSK32PATGEN_CFG7_ivst                               0xFFFF0000
 	#define	RA_PATGEN_CFG8                                 0x0020
 	#define	BA_PATGEN_CFG8_lcolor_hp                       0x0020
 	#define	B16PATGEN_CFG8_lcolor_hp                       0x0020
 	#define	LSb32PATGEN_CFG8_lcolor_hp                          0
 	#define	LSb16PATGEN_CFG8_lcolor_hp                          0
 	#define	bPATGEN_CFG8_lcolor_hp                       6
 	#define	MSK32PATGEN_CFG8_lcolor_hp                          0x0000003F
 	#define	BA_PATGEN_CFG8_lcolor_vp                       0x0020
 	#define	B16PATGEN_CFG8_lcolor_vp                       0x0020
 	#define	LSb32PATGEN_CFG8_lcolor_vp                          6
 	#define	LSb16PATGEN_CFG8_lcolor_vp                          6
 	#define	bPATGEN_CFG8_lcolor_vp                       6
 	#define	MSK32PATGEN_CFG8_lcolor_vp                          0x00000FC0
 	#define	BA_PATGEN_CFG8_lfseed                          0x0021
 	#define	B16PATGEN_CFG8_lfseed                          0x0020
 	#define	LSb32PATGEN_CFG8_lfseed                             12
 	#define	LSb16PATGEN_CFG8_lfseed                             12
 	#define	bPATGEN_CFG8_lfseed                          6
 	#define	MSK32PATGEN_CFG8_lfseed                             0x0003F000
 	#define	BA_PATGEN_CFG8_cad_mode                        0x0022
 	#define	B16PATGEN_CFG8_cad_mode                        0x0022
 	#define	LSb32PATGEN_CFG8_cad_mode                           18
 	#define	LSb16PATGEN_CFG8_cad_mode                           2
 	#define	bPATGEN_CFG8_cad_mode                        2
 	#define	MSK32PATGEN_CFG8_cad_mode                           0x000C0000
 	#define	BA_PATGEN_CFG8_imode                           0x0022
 	#define	B16PATGEN_CFG8_imode                           0x0022
 	#define	LSb32PATGEN_CFG8_imode                              20
 	#define	LSb16PATGEN_CFG8_imode                              4
 	#define	bPATGEN_CFG8_imode                           1
 	#define	MSK32PATGEN_CFG8_imode                              0x00100000
 	#define	BA_PATGEN_CFG8_rff                             0x0022
 	#define	B16PATGEN_CFG8_rff                             0x0022
 	#define	LSb32PATGEN_CFG8_rff                                21
 	#define	LSb16PATGEN_CFG8_rff                                5
 	#define	bPATGEN_CFG8_rff                             5
 	#define	MSK32PATGEN_CFG8_rff                                0x03E00000
 	#define	RA_PATGEN_CFG9                                 0x0024
 	#define	BA_PATGEN_CFG9_ufseed1                         0x0024
 	#define	B16PATGEN_CFG9_ufseed1                         0x0024
 	#define	LSb32PATGEN_CFG9_ufseed1                            0
 	#define	LSb16PATGEN_CFG9_ufseed1                            0
 	#define	bPATGEN_CFG9_ufseed1                         24
 	#define	MSK32PATGEN_CFG9_ufseed1                            0x00FFFFFF
 	#define	BA_PATGEN_CFG9_lfseed1                         0x0027
 	#define	B16PATGEN_CFG9_lfseed1                         0x0026
 	#define	LSb32PATGEN_CFG9_lfseed1                            24
 	#define	LSb16PATGEN_CFG9_lfseed1                            8
 	#define	bPATGEN_CFG9_lfseed1                         6
 	#define	MSK32PATGEN_CFG9_lfseed1                            0x3F000000
 	#define	RA_VIPSTS_CFG0                                 0x0000
 	#define	BA_VIPSTS_CFG0_stcInitV0_0                     0x0000
 	#define	B16VIPSTS_CFG0_stcInitV0_0                     0x0000
 	#define	LSb32VIPSTS_CFG0_stcInitV0_0                        0
 	#define	LSb16VIPSTS_CFG0_stcInitV0_0                        0
 	#define	bVIPSTS_CFG0_stcInitV0_0                     8
 	#define	MSK32VIPSTS_CFG0_stcInitV0_0                        0x000000FF
 	#define	BA_VIPSTS_CFG0_stcInitV0_1                     0x0001
 	#define	B16VIPSTS_CFG0_stcInitV0_1                     0x0000
 	#define	LSb32VIPSTS_CFG0_stcInitV0_1                        8
 	#define	LSb16VIPSTS_CFG0_stcInitV0_1                        8
 	#define	bVIPSTS_CFG0_stcInitV0_1                     8
 	#define	MSK32VIPSTS_CFG0_stcInitV0_1                        0x0000FF00
 	#define	BA_VIPSTS_CFG0_stcInitV0_2                     0x0002
 	#define	B16VIPSTS_CFG0_stcInitV0_2                     0x0002
 	#define	LSb32VIPSTS_CFG0_stcInitV0_2                        16
 	#define	LSb16VIPSTS_CFG0_stcInitV0_2                        0
 	#define	bVIPSTS_CFG0_stcInitV0_2                     8
 	#define	MSK32VIPSTS_CFG0_stcInitV0_2                        0x00FF0000
 	#define	BA_VIPSTS_CFG0_stcInitV0_3                     0x0003
 	#define	B16VIPSTS_CFG0_stcInitV0_3                     0x0002
 	#define	LSb32VIPSTS_CFG0_stcInitV0_3                        24
 	#define	LSb16VIPSTS_CFG0_stcInitV0_3                        8
 	#define	bVIPSTS_CFG0_stcInitV0_3                     8
 	#define	MSK32VIPSTS_CFG0_stcInitV0_3                        0xFF000000
 	#define	RA_VIPSTS_CFG1                                 0x0004
 	#define	BA_VIPSTS_CFG1_stcInitV0_4                     0x0004
 	#define	B16VIPSTS_CFG1_stcInitV0_4                     0x0004
 	#define	LSb32VIPSTS_CFG1_stcInitV0_4                        0
 	#define	LSb16VIPSTS_CFG1_stcInitV0_4                        0
 	#define	bVIPSTS_CFG1_stcInitV0_4                     8
 	#define	MSK32VIPSTS_CFG1_stcInitV0_4                        0x000000FF
 	#define	BA_VIPSTS_CFG1_stcInitV0_5                     0x0005
 	#define	B16VIPSTS_CFG1_stcInitV0_5                     0x0004
 	#define	LSb32VIPSTS_CFG1_stcInitV0_5                        8
 	#define	LSb16VIPSTS_CFG1_stcInitV0_5                        8
 	#define	bVIPSTS_CFG1_stcInitV0_5                     8
 	#define	MSK32VIPSTS_CFG1_stcInitV0_5                        0x0000FF00
 	#define	BA_VIPSTS_CFG1_stcInitV0_6                     0x0006
 	#define	B16VIPSTS_CFG1_stcInitV0_6                     0x0006
 	#define	LSb32VIPSTS_CFG1_stcInitV0_6                        16
 	#define	LSb16VIPSTS_CFG1_stcInitV0_6                        0
 	#define	bVIPSTS_CFG1_stcInitV0_6                     8
 	#define	MSK32VIPSTS_CFG1_stcInitV0_6                        0x00FF0000
 	#define	BA_VIPSTS_CFG1_stcInitV0_7                     0x0007
 	#define	B16VIPSTS_CFG1_stcInitV0_7                     0x0006
 	#define	LSb32VIPSTS_CFG1_stcInitV0_7                        24
 	#define	LSb16VIPSTS_CFG1_stcInitV0_7                        8
 	#define	bVIPSTS_CFG1_stcInitV0_7                     8
 	#define	MSK32VIPSTS_CFG1_stcInitV0_7                        0xFF000000
 	#define	RA_VIPSTS_CFG2                                 0x0008
 	#define	BA_VIPSTS_CFG2_stcInitV1_0                     0x0008
 	#define	B16VIPSTS_CFG2_stcInitV1_0                     0x0008
 	#define	LSb32VIPSTS_CFG2_stcInitV1_0                        0
 	#define	LSb16VIPSTS_CFG2_stcInitV1_0                        0
 	#define	bVIPSTS_CFG2_stcInitV1_0                     8
 	#define	MSK32VIPSTS_CFG2_stcInitV1_0                        0x000000FF
 	#define	BA_VIPSTS_CFG2_stcInitV1_1                     0x0009
 	#define	B16VIPSTS_CFG2_stcInitV1_1                     0x0008
 	#define	LSb32VIPSTS_CFG2_stcInitV1_1                        8
 	#define	LSb16VIPSTS_CFG2_stcInitV1_1                        8
 	#define	bVIPSTS_CFG2_stcInitV1_1                     8
 	#define	MSK32VIPSTS_CFG2_stcInitV1_1                        0x0000FF00
 	#define	BA_VIPSTS_CFG2_stcInitV1_2                     0x000A
 	#define	B16VIPSTS_CFG2_stcInitV1_2                     0x000A
 	#define	LSb32VIPSTS_CFG2_stcInitV1_2                        16
 	#define	LSb16VIPSTS_CFG2_stcInitV1_2                        0
 	#define	bVIPSTS_CFG2_stcInitV1_2                     8
 	#define	MSK32VIPSTS_CFG2_stcInitV1_2                        0x00FF0000
 	#define	BA_VIPSTS_CFG2_stcInitV1_3                     0x000B
 	#define	B16VIPSTS_CFG2_stcInitV1_3                     0x000A
 	#define	LSb32VIPSTS_CFG2_stcInitV1_3                        24
 	#define	LSb16VIPSTS_CFG2_stcInitV1_3                        8
 	#define	bVIPSTS_CFG2_stcInitV1_3                     8
 	#define	MSK32VIPSTS_CFG2_stcInitV1_3                        0xFF000000
 	#define	RA_VIPSTS_CFG3                                 0x000C
 	#define	BA_VIPSTS_CFG3_stcInitV1_4                     0x000C
 	#define	B16VIPSTS_CFG3_stcInitV1_4                     0x000C
 	#define	LSb32VIPSTS_CFG3_stcInitV1_4                        0
 	#define	LSb16VIPSTS_CFG3_stcInitV1_4                        0
 	#define	bVIPSTS_CFG3_stcInitV1_4                     8
 	#define	MSK32VIPSTS_CFG3_stcInitV1_4                        0x000000FF
 	#define	BA_VIPSTS_CFG3_stcInitV1_5                     0x000D
 	#define	B16VIPSTS_CFG3_stcInitV1_5                     0x000C
 	#define	LSb32VIPSTS_CFG3_stcInitV1_5                        8
 	#define	LSb16VIPSTS_CFG3_stcInitV1_5                        8
 	#define	bVIPSTS_CFG3_stcInitV1_5                     8
 	#define	MSK32VIPSTS_CFG3_stcInitV1_5                        0x0000FF00
 	#define	BA_VIPSTS_CFG3_stcInitV1_6                     0x000E
 	#define	B16VIPSTS_CFG3_stcInitV1_6                     0x000E
 	#define	LSb32VIPSTS_CFG3_stcInitV1_6                        16
 	#define	LSb16VIPSTS_CFG3_stcInitV1_6                        0
 	#define	bVIPSTS_CFG3_stcInitV1_6                     8
 	#define	MSK32VIPSTS_CFG3_stcInitV1_6                        0x00FF0000
 	#define	BA_VIPSTS_CFG3_stcInitV1_7                     0x000F
 	#define	B16VIPSTS_CFG3_stcInitV1_7                     0x000E
 	#define	LSb32VIPSTS_CFG3_stcInitV1_7                        24
 	#define	LSb16VIPSTS_CFG3_stcInitV1_7                        8
 	#define	bVIPSTS_CFG3_stcInitV1_7                     8
 	#define	MSK32VIPSTS_CFG3_stcInitV1_7                        0xFF000000
 	#define	RA_VIPSTS_CFG4                                 0x0010
 	#define	BA_VIPSTS_CFG4_divValStc0_0                    0x0010
 	#define	B16VIPSTS_CFG4_divValStc0_0                    0x0010
 	#define	LSb32VIPSTS_CFG4_divValStc0_0                       0
 	#define	LSb16VIPSTS_CFG4_divValStc0_0                       0
 	#define	bVIPSTS_CFG4_divValStc0_0                    16
 	#define	MSK32VIPSTS_CFG4_divValStc0_0                       0x0000FFFF
 	#define	BA_VIPSTS_CFG4_divValStc0_1                    0x0012
 	#define	B16VIPSTS_CFG4_divValStc0_1                    0x0012
 	#define	LSb32VIPSTS_CFG4_divValStc0_1                       16
 	#define	LSb16VIPSTS_CFG4_divValStc0_1                       0
 	#define	bVIPSTS_CFG4_divValStc0_1                    16
 	#define	MSK32VIPSTS_CFG4_divValStc0_1                       0xFFFF0000
 	#define	RA_VIPSTS_CFG5                                 0x0014
 	#define	BA_VIPSTS_CFG5_divValStc1_0                    0x0014
 	#define	B16VIPSTS_CFG5_divValStc1_0                    0x0014
 	#define	LSb32VIPSTS_CFG5_divValStc1_0                       0
 	#define	LSb16VIPSTS_CFG5_divValStc1_0                       0
 	#define	bVIPSTS_CFG5_divValStc1_0                    16
 	#define	MSK32VIPSTS_CFG5_divValStc1_0                       0x0000FFFF
 	#define	BA_VIPSTS_CFG5_divValStc1_1                    0x0016
 	#define	B16VIPSTS_CFG5_divValStc1_1                    0x0016
 	#define	LSb32VIPSTS_CFG5_divValStc1_1                       16
 	#define	LSb16VIPSTS_CFG5_divValStc1_1                       0
 	#define	bVIPSTS_CFG5_divValStc1_1                    16
 	#define	MSK32VIPSTS_CFG5_divValStc1_1                       0xFFFF0000
 	#define	RA_VIPSTS_CFG6                                 0x0018
 	#define	BA_VIPSTS_CFG6_selSyncDviSts                   0x0018
 	#define	B16VIPSTS_CFG6_selSyncDviSts                   0x0018
 	#define	LSb32VIPSTS_CFG6_selSyncDviSts                      0
 	#define	LSb16VIPSTS_CFG6_selSyncDviSts                      0
 	#define	bVIPSTS_CFG6_selSyncDviSts                   8
 	#define	MSK32VIPSTS_CFG6_selSyncDviSts                      0x000000FF
 	#define	BA_VIPSTS_CFG6_selSyncHdmiRxSts                0x0019
 	#define	B16VIPSTS_CFG6_selSyncHdmiRxSts                0x0018
 	#define	LSb32VIPSTS_CFG6_selSyncHdmiRxSts                   8
 	#define	LSb16VIPSTS_CFG6_selSyncHdmiRxSts                   8
 	#define	bVIPSTS_CFG6_selSyncHdmiRxSts                8
 	#define	MSK32VIPSTS_CFG6_selSyncHdmiRxSts                   0x0000FF00
 	#define	BA_VIPSTS_CFG6_stsCtrl                         0x001A
 	#define	B16VIPSTS_CFG6_stsCtrl                         0x001A
 	#define	LSb32VIPSTS_CFG6_stsCtrl                            16
 	#define	LSb16VIPSTS_CFG6_stsCtrl                            0
 	#define	bVIPSTS_CFG6_stsCtrl                         8
 	#define	MSK32VIPSTS_CFG6_stsCtrl                            0x00FF0000
 	#define	RA_VIPSTS_STS0                                 0x001C
 	#define	BA_VIPSTS_STS0_dviSts0_0                       0x001C
 	#define	B16VIPSTS_STS0_dviSts0_0                       0x001C
 	#define	LSb32VIPSTS_STS0_dviSts0_0                          0
 	#define	LSb16VIPSTS_STS0_dviSts0_0                          0
 	#define	bVIPSTS_STS0_dviSts0_0                       8
 	#define	MSK32VIPSTS_STS0_dviSts0_0                          0x000000FF
 	#define	BA_VIPSTS_STS0_dviSts0_1                       0x001D
 	#define	B16VIPSTS_STS0_dviSts0_1                       0x001C
 	#define	LSb32VIPSTS_STS0_dviSts0_1                          8
 	#define	LSb16VIPSTS_STS0_dviSts0_1                          8
 	#define	bVIPSTS_STS0_dviSts0_1                       8
 	#define	MSK32VIPSTS_STS0_dviSts0_1                          0x0000FF00
 	#define	BA_VIPSTS_STS0_dviSts0_2                       0x001E
 	#define	B16VIPSTS_STS0_dviSts0_2                       0x001E
 	#define	LSb32VIPSTS_STS0_dviSts0_2                          16
 	#define	LSb16VIPSTS_STS0_dviSts0_2                          0
 	#define	bVIPSTS_STS0_dviSts0_2                       8
 	#define	MSK32VIPSTS_STS0_dviSts0_2                          0x00FF0000
 	#define	BA_VIPSTS_STS0_dviSts0_3                       0x001F
 	#define	B16VIPSTS_STS0_dviSts0_3                       0x001E
 	#define	LSb32VIPSTS_STS0_dviSts0_3                          24
 	#define	LSb16VIPSTS_STS0_dviSts0_3                          8
 	#define	bVIPSTS_STS0_dviSts0_3                       8
 	#define	MSK32VIPSTS_STS0_dviSts0_3                          0xFF000000
 	#define	RA_VIPSTS_STS1                                 0x0020
 	#define	BA_VIPSTS_STS1_dviSts0_4                       0x0020
 	#define	B16VIPSTS_STS1_dviSts0_4                       0x0020
 	#define	LSb32VIPSTS_STS1_dviSts0_4                          0
 	#define	LSb16VIPSTS_STS1_dviSts0_4                          0
 	#define	bVIPSTS_STS1_dviSts0_4                       8
 	#define	MSK32VIPSTS_STS1_dviSts0_4                          0x000000FF
 	#define	BA_VIPSTS_STS1_dviSts0_5                       0x0021
 	#define	B16VIPSTS_STS1_dviSts0_5                       0x0020
 	#define	LSb32VIPSTS_STS1_dviSts0_5                          8
 	#define	LSb16VIPSTS_STS1_dviSts0_5                          8
 	#define	bVIPSTS_STS1_dviSts0_5                       8
 	#define	MSK32VIPSTS_STS1_dviSts0_5                          0x0000FF00
 	#define	BA_VIPSTS_STS1_dviSts0_6                       0x0022
 	#define	B16VIPSTS_STS1_dviSts0_6                       0x0022
 	#define	LSb32VIPSTS_STS1_dviSts0_6                          16
 	#define	LSb16VIPSTS_STS1_dviSts0_6                          0
 	#define	bVIPSTS_STS1_dviSts0_6                       8
 	#define	MSK32VIPSTS_STS1_dviSts0_6                          0x00FF0000
 	#define	BA_VIPSTS_STS1_dviSts0_7                       0x0023
 	#define	B16VIPSTS_STS1_dviSts0_7                       0x0022
 	#define	LSb32VIPSTS_STS1_dviSts0_7                          24
 	#define	LSb16VIPSTS_STS1_dviSts0_7                          8
 	#define	bVIPSTS_STS1_dviSts0_7                       8
 	#define	MSK32VIPSTS_STS1_dviSts0_7                          0xFF000000
 	#define	RA_VIPSTS_STS2                                 0x0024
 	#define	BA_VIPSTS_STS2_dviSts1_0                       0x0024
 	#define	B16VIPSTS_STS2_dviSts1_0                       0x0024
 	#define	LSb32VIPSTS_STS2_dviSts1_0                          0
 	#define	LSb16VIPSTS_STS2_dviSts1_0                          0
 	#define	bVIPSTS_STS2_dviSts1_0                       8
 	#define	MSK32VIPSTS_STS2_dviSts1_0                          0x000000FF
 	#define	BA_VIPSTS_STS2_dviSts1_1                       0x0025
 	#define	B16VIPSTS_STS2_dviSts1_1                       0x0024
 	#define	LSb32VIPSTS_STS2_dviSts1_1                          8
 	#define	LSb16VIPSTS_STS2_dviSts1_1                          8
 	#define	bVIPSTS_STS2_dviSts1_1                       8
 	#define	MSK32VIPSTS_STS2_dviSts1_1                          0x0000FF00
 	#define	BA_VIPSTS_STS2_dviSts1_2                       0x0026
 	#define	B16VIPSTS_STS2_dviSts1_2                       0x0026
 	#define	LSb32VIPSTS_STS2_dviSts1_2                          16
 	#define	LSb16VIPSTS_STS2_dviSts1_2                          0
 	#define	bVIPSTS_STS2_dviSts1_2                       8
 	#define	MSK32VIPSTS_STS2_dviSts1_2                          0x00FF0000
 	#define	BA_VIPSTS_STS2_dviSts1_3                       0x0027
 	#define	B16VIPSTS_STS2_dviSts1_3                       0x0026
 	#define	LSb32VIPSTS_STS2_dviSts1_3                          24
 	#define	LSb16VIPSTS_STS2_dviSts1_3                          8
 	#define	bVIPSTS_STS2_dviSts1_3                       8
 	#define	MSK32VIPSTS_STS2_dviSts1_3                          0xFF000000
 	#define	RA_VIPSTS_STS3                                 0x0028
 	#define	BA_VIPSTS_STS3_dviSts1_4                       0x0028
 	#define	B16VIPSTS_STS3_dviSts1_4                       0x0028
 	#define	LSb32VIPSTS_STS3_dviSts1_4                          0
 	#define	LSb16VIPSTS_STS3_dviSts1_4                          0
 	#define	bVIPSTS_STS3_dviSts1_4                       8
 	#define	MSK32VIPSTS_STS3_dviSts1_4                          0x000000FF
 	#define	BA_VIPSTS_STS3_dviSts1_5                       0x0029
 	#define	B16VIPSTS_STS3_dviSts1_5                       0x0028
 	#define	LSb32VIPSTS_STS3_dviSts1_5                          8
 	#define	LSb16VIPSTS_STS3_dviSts1_5                          8
 	#define	bVIPSTS_STS3_dviSts1_5                       8
 	#define	MSK32VIPSTS_STS3_dviSts1_5                          0x0000FF00
 	#define	BA_VIPSTS_STS3_dviSts1_6                       0x002A
 	#define	B16VIPSTS_STS3_dviSts1_6                       0x002A
 	#define	LSb32VIPSTS_STS3_dviSts1_6                          16
 	#define	LSb16VIPSTS_STS3_dviSts1_6                          0
 	#define	bVIPSTS_STS3_dviSts1_6                       8
 	#define	MSK32VIPSTS_STS3_dviSts1_6                          0x00FF0000
 	#define	BA_VIPSTS_STS3_dviSts1_7                       0x002B
 	#define	B16VIPSTS_STS3_dviSts1_7                       0x002A
 	#define	LSb32VIPSTS_STS3_dviSts1_7                          24
 	#define	LSb16VIPSTS_STS3_dviSts1_7                          8
 	#define	bVIPSTS_STS3_dviSts1_7                       8
 	#define	MSK32VIPSTS_STS3_dviSts1_7                          0xFF000000
 	#define	RA_VIPSTS_STS4                                 0x002C
 	#define	BA_VIPSTS_STS4_hdmiRxSts0_0                    0x002C
 	#define	B16VIPSTS_STS4_hdmiRxSts0_0                    0x002C
 	#define	LSb32VIPSTS_STS4_hdmiRxSts0_0                       0
 	#define	LSb16VIPSTS_STS4_hdmiRxSts0_0                       0
 	#define	bVIPSTS_STS4_hdmiRxSts0_0                    8
 	#define	MSK32VIPSTS_STS4_hdmiRxSts0_0                       0x000000FF
 	#define	BA_VIPSTS_STS4_hdmiRxSts0_1                    0x002D
 	#define	B16VIPSTS_STS4_hdmiRxSts0_1                    0x002C
 	#define	LSb32VIPSTS_STS4_hdmiRxSts0_1                       8
 	#define	LSb16VIPSTS_STS4_hdmiRxSts0_1                       8
 	#define	bVIPSTS_STS4_hdmiRxSts0_1                    8
 	#define	MSK32VIPSTS_STS4_hdmiRxSts0_1                       0x0000FF00
 	#define	BA_VIPSTS_STS4_hdmiRxSts0_2                    0x002E
 	#define	B16VIPSTS_STS4_hdmiRxSts0_2                    0x002E
 	#define	LSb32VIPSTS_STS4_hdmiRxSts0_2                       16
 	#define	LSb16VIPSTS_STS4_hdmiRxSts0_2                       0
 	#define	bVIPSTS_STS4_hdmiRxSts0_2                    8
 	#define	MSK32VIPSTS_STS4_hdmiRxSts0_2                       0x00FF0000
 	#define	BA_VIPSTS_STS4_hdmiRxSts0_3                    0x002F
 	#define	B16VIPSTS_STS4_hdmiRxSts0_3                    0x002E
 	#define	LSb32VIPSTS_STS4_hdmiRxSts0_3                       24
 	#define	LSb16VIPSTS_STS4_hdmiRxSts0_3                       8
 	#define	bVIPSTS_STS4_hdmiRxSts0_3                    8
 	#define	MSK32VIPSTS_STS4_hdmiRxSts0_3                       0xFF000000
 	#define	RA_VIPSTS_STS5                                 0x0030
 	#define	BA_VIPSTS_STS5_hdmiRxSts0_4                    0x0030
 	#define	B16VIPSTS_STS5_hdmiRxSts0_4                    0x0030
 	#define	LSb32VIPSTS_STS5_hdmiRxSts0_4                       0
 	#define	LSb16VIPSTS_STS5_hdmiRxSts0_4                       0
 	#define	bVIPSTS_STS5_hdmiRxSts0_4                    8
 	#define	MSK32VIPSTS_STS5_hdmiRxSts0_4                       0x000000FF
 	#define	BA_VIPSTS_STS5_hdmiRxSts0_5                    0x0031
 	#define	B16VIPSTS_STS5_hdmiRxSts0_5                    0x0030
 	#define	LSb32VIPSTS_STS5_hdmiRxSts0_5                       8
 	#define	LSb16VIPSTS_STS5_hdmiRxSts0_5                       8
 	#define	bVIPSTS_STS5_hdmiRxSts0_5                    8
 	#define	MSK32VIPSTS_STS5_hdmiRxSts0_5                       0x0000FF00
 	#define	BA_VIPSTS_STS5_hdmiRxSts0_6                    0x0032
 	#define	B16VIPSTS_STS5_hdmiRxSts0_6                    0x0032
 	#define	LSb32VIPSTS_STS5_hdmiRxSts0_6                       16
 	#define	LSb16VIPSTS_STS5_hdmiRxSts0_6                       0
 	#define	bVIPSTS_STS5_hdmiRxSts0_6                    8
 	#define	MSK32VIPSTS_STS5_hdmiRxSts0_6                       0x00FF0000
 	#define	BA_VIPSTS_STS5_hdmiRxSts0_7                    0x0033
 	#define	B16VIPSTS_STS5_hdmiRxSts0_7                    0x0032
 	#define	LSb32VIPSTS_STS5_hdmiRxSts0_7                       24
 	#define	LSb16VIPSTS_STS5_hdmiRxSts0_7                       8
 	#define	bVIPSTS_STS5_hdmiRxSts0_7                    8
 	#define	MSK32VIPSTS_STS5_hdmiRxSts0_7                       0xFF000000
 	#define	RA_VIPSTS_STS6                                 0x0034
 	#define	BA_VIPSTS_STS6_hdmiRxSts1_0                    0x0034
 	#define	B16VIPSTS_STS6_hdmiRxSts1_0                    0x0034
 	#define	LSb32VIPSTS_STS6_hdmiRxSts1_0                       0
 	#define	LSb16VIPSTS_STS6_hdmiRxSts1_0                       0
 	#define	bVIPSTS_STS6_hdmiRxSts1_0                    8
 	#define	MSK32VIPSTS_STS6_hdmiRxSts1_0                       0x000000FF
 	#define	BA_VIPSTS_STS6_hdmiRxSts1_1                    0x0035
 	#define	B16VIPSTS_STS6_hdmiRxSts1_1                    0x0034
 	#define	LSb32VIPSTS_STS6_hdmiRxSts1_1                       8
 	#define	LSb16VIPSTS_STS6_hdmiRxSts1_1                       8
 	#define	bVIPSTS_STS6_hdmiRxSts1_1                    8
 	#define	MSK32VIPSTS_STS6_hdmiRxSts1_1                       0x0000FF00
 	#define	BA_VIPSTS_STS6_hdmiRxSts1_2                    0x0036
 	#define	B16VIPSTS_STS6_hdmiRxSts1_2                    0x0036
 	#define	LSb32VIPSTS_STS6_hdmiRxSts1_2                       16
 	#define	LSb16VIPSTS_STS6_hdmiRxSts1_2                       0
 	#define	bVIPSTS_STS6_hdmiRxSts1_2                    8
 	#define	MSK32VIPSTS_STS6_hdmiRxSts1_2                       0x00FF0000
 	#define	BA_VIPSTS_STS6_hdmiRxSts1_3                    0x0037
 	#define	B16VIPSTS_STS6_hdmiRxSts1_3                    0x0036
 	#define	LSb32VIPSTS_STS6_hdmiRxSts1_3                       24
 	#define	LSb16VIPSTS_STS6_hdmiRxSts1_3                       8
 	#define	bVIPSTS_STS6_hdmiRxSts1_3                    8
 	#define	MSK32VIPSTS_STS6_hdmiRxSts1_3                       0xFF000000
 	#define	RA_VIPSTS_STS7                                 0x0038
 	#define	BA_VIPSTS_STS7_hdmiRxSts1_4                    0x0038
 	#define	B16VIPSTS_STS7_hdmiRxSts1_4                    0x0038
 	#define	LSb32VIPSTS_STS7_hdmiRxSts1_4                       0
 	#define	LSb16VIPSTS_STS7_hdmiRxSts1_4                       0
 	#define	bVIPSTS_STS7_hdmiRxSts1_4                    8
 	#define	MSK32VIPSTS_STS7_hdmiRxSts1_4                       0x000000FF
 	#define	BA_VIPSTS_STS7_hdmiRxSts1_5                    0x0039
 	#define	B16VIPSTS_STS7_hdmiRxSts1_5                    0x0038
 	#define	LSb32VIPSTS_STS7_hdmiRxSts1_5                       8
 	#define	LSb16VIPSTS_STS7_hdmiRxSts1_5                       8
 	#define	bVIPSTS_STS7_hdmiRxSts1_5                    8
 	#define	MSK32VIPSTS_STS7_hdmiRxSts1_5                       0x0000FF00
 	#define	BA_VIPSTS_STS7_hdmiRxSts1_6                    0x003A
 	#define	B16VIPSTS_STS7_hdmiRxSts1_6                    0x003A
 	#define	LSb32VIPSTS_STS7_hdmiRxSts1_6                       16
 	#define	LSb16VIPSTS_STS7_hdmiRxSts1_6                       0
 	#define	bVIPSTS_STS7_hdmiRxSts1_6                    8
 	#define	MSK32VIPSTS_STS7_hdmiRxSts1_6                       0x00FF0000
 	#define	BA_VIPSTS_STS7_hdmiRxSts1_7                    0x003B
 	#define	B16VIPSTS_STS7_hdmiRxSts1_7                    0x003A
 	#define	LSb32VIPSTS_STS7_hdmiRxSts1_7                       24
 	#define	LSb16VIPSTS_STS7_hdmiRxSts1_7                       8
 	#define	bVIPSTS_STS7_hdmiRxSts1_7                    8
 	#define	MSK32VIPSTS_STS7_hdmiRxSts1_7                       0xFF000000
 	#define	RA_VIPSTS_STS8                                 0x003C
 	#define	BA_VIPSTS_STS8_dviSts0_rd_0                    0x003C
 	#define	B16VIPSTS_STS8_dviSts0_rd_0                    0x003C
 	#define	LSb32VIPSTS_STS8_dviSts0_rd_0                       0
 	#define	LSb16VIPSTS_STS8_dviSts0_rd_0                       0
 	#define	bVIPSTS_STS8_dviSts0_rd_0                    8
 	#define	MSK32VIPSTS_STS8_dviSts0_rd_0                       0x000000FF
 	#define	BA_VIPSTS_STS8_dviSts0_rd_1                    0x003D
 	#define	B16VIPSTS_STS8_dviSts0_rd_1                    0x003C
 	#define	LSb32VIPSTS_STS8_dviSts0_rd_1                       8
 	#define	LSb16VIPSTS_STS8_dviSts0_rd_1                       8
 	#define	bVIPSTS_STS8_dviSts0_rd_1                    8
 	#define	MSK32VIPSTS_STS8_dviSts0_rd_1                       0x0000FF00
 	#define	BA_VIPSTS_STS8_dviSts0_rd_2                    0x003E
 	#define	B16VIPSTS_STS8_dviSts0_rd_2                    0x003E
 	#define	LSb32VIPSTS_STS8_dviSts0_rd_2                       16
 	#define	LSb16VIPSTS_STS8_dviSts0_rd_2                       0
 	#define	bVIPSTS_STS8_dviSts0_rd_2                    8
 	#define	MSK32VIPSTS_STS8_dviSts0_rd_2                       0x00FF0000
 	#define	BA_VIPSTS_STS8_dviSts0_rd_3                    0x003F
 	#define	B16VIPSTS_STS8_dviSts0_rd_3                    0x003E
 	#define	LSb32VIPSTS_STS8_dviSts0_rd_3                       24
 	#define	LSb16VIPSTS_STS8_dviSts0_rd_3                       8
 	#define	bVIPSTS_STS8_dviSts0_rd_3                    8
 	#define	MSK32VIPSTS_STS8_dviSts0_rd_3                       0xFF000000
 	#define	RA_VIPSTS_STS9                                 0x0040
 	#define	BA_VIPSTS_STS9_dviSts0_rd_4                    0x0040
 	#define	B16VIPSTS_STS9_dviSts0_rd_4                    0x0040
 	#define	LSb32VIPSTS_STS9_dviSts0_rd_4                       0
 	#define	LSb16VIPSTS_STS9_dviSts0_rd_4                       0
 	#define	bVIPSTS_STS9_dviSts0_rd_4                    8
 	#define	MSK32VIPSTS_STS9_dviSts0_rd_4                       0x000000FF
 	#define	BA_VIPSTS_STS9_dviSts0_rd_5                    0x0041
 	#define	B16VIPSTS_STS9_dviSts0_rd_5                    0x0040
 	#define	LSb32VIPSTS_STS9_dviSts0_rd_5                       8
 	#define	LSb16VIPSTS_STS9_dviSts0_rd_5                       8
 	#define	bVIPSTS_STS9_dviSts0_rd_5                    8
 	#define	MSK32VIPSTS_STS9_dviSts0_rd_5                       0x0000FF00
 	#define	BA_VIPSTS_STS9_dviSts0_rd_6                    0x0042
 	#define	B16VIPSTS_STS9_dviSts0_rd_6                    0x0042
 	#define	LSb32VIPSTS_STS9_dviSts0_rd_6                       16
 	#define	LSb16VIPSTS_STS9_dviSts0_rd_6                       0
 	#define	bVIPSTS_STS9_dviSts0_rd_6                    8
 	#define	MSK32VIPSTS_STS9_dviSts0_rd_6                       0x00FF0000
 	#define	BA_VIPSTS_STS9_dviSts0_rd_7                    0x0043
 	#define	B16VIPSTS_STS9_dviSts0_rd_7                    0x0042
 	#define	LSb32VIPSTS_STS9_dviSts0_rd_7                       24
 	#define	LSb16VIPSTS_STS9_dviSts0_rd_7                       8
 	#define	bVIPSTS_STS9_dviSts0_rd_7                    8
 	#define	MSK32VIPSTS_STS9_dviSts0_rd_7                       0xFF000000
 	#define	RA_VIPSTS_STS10                                0x0044
 	#define	BA_VIPSTS_STS10_dviSts1_rd_0                   0x0044
 	#define	B16VIPSTS_STS10_dviSts1_rd_0                   0x0044
 	#define	LSb32VIPSTS_STS10_dviSts1_rd_0                      0
 	#define	LSb16VIPSTS_STS10_dviSts1_rd_0                      0
 	#define	bVIPSTS_STS10_dviSts1_rd_0                   8
 	#define	MSK32VIPSTS_STS10_dviSts1_rd_0                      0x000000FF
 	#define	BA_VIPSTS_STS10_dviSts1_rd_1                   0x0045
 	#define	B16VIPSTS_STS10_dviSts1_rd_1                   0x0044
 	#define	LSb32VIPSTS_STS10_dviSts1_rd_1                      8
 	#define	LSb16VIPSTS_STS10_dviSts1_rd_1                      8
 	#define	bVIPSTS_STS10_dviSts1_rd_1                   8
 	#define	MSK32VIPSTS_STS10_dviSts1_rd_1                      0x0000FF00
 	#define	BA_VIPSTS_STS10_dviSts1_rd_2                   0x0046
 	#define	B16VIPSTS_STS10_dviSts1_rd_2                   0x0046
 	#define	LSb32VIPSTS_STS10_dviSts1_rd_2                      16
 	#define	LSb16VIPSTS_STS10_dviSts1_rd_2                      0
 	#define	bVIPSTS_STS10_dviSts1_rd_2                   8
 	#define	MSK32VIPSTS_STS10_dviSts1_rd_2                      0x00FF0000
 	#define	BA_VIPSTS_STS10_dviSts1_rd_3                   0x0047
 	#define	B16VIPSTS_STS10_dviSts1_rd_3                   0x0046
 	#define	LSb32VIPSTS_STS10_dviSts1_rd_3                      24
 	#define	LSb16VIPSTS_STS10_dviSts1_rd_3                      8
 	#define	bVIPSTS_STS10_dviSts1_rd_3                   8
 	#define	MSK32VIPSTS_STS10_dviSts1_rd_3                      0xFF000000
 	#define	RA_VIPSTS_STS11                                0x0048
 	#define	BA_VIPSTS_STS11_dviSts1_rd_4                   0x0048
 	#define	B16VIPSTS_STS11_dviSts1_rd_4                   0x0048
 	#define	LSb32VIPSTS_STS11_dviSts1_rd_4                      0
 	#define	LSb16VIPSTS_STS11_dviSts1_rd_4                      0
 	#define	bVIPSTS_STS11_dviSts1_rd_4                   8
 	#define	MSK32VIPSTS_STS11_dviSts1_rd_4                      0x000000FF
 	#define	BA_VIPSTS_STS11_dviSts1_rd_5                   0x0049
 	#define	B16VIPSTS_STS11_dviSts1_rd_5                   0x0048
 	#define	LSb32VIPSTS_STS11_dviSts1_rd_5                      8
 	#define	LSb16VIPSTS_STS11_dviSts1_rd_5                      8
 	#define	bVIPSTS_STS11_dviSts1_rd_5                   8
 	#define	MSK32VIPSTS_STS11_dviSts1_rd_5                      0x0000FF00
 	#define	BA_VIPSTS_STS11_dviSts1_rd_6                   0x004A
 	#define	B16VIPSTS_STS11_dviSts1_rd_6                   0x004A
 	#define	LSb32VIPSTS_STS11_dviSts1_rd_6                      16
 	#define	LSb16VIPSTS_STS11_dviSts1_rd_6                      0
 	#define	bVIPSTS_STS11_dviSts1_rd_6                   8
 	#define	MSK32VIPSTS_STS11_dviSts1_rd_6                      0x00FF0000
 	#define	BA_VIPSTS_STS11_dviSts1_rd_7                   0x004B
 	#define	B16VIPSTS_STS11_dviSts1_rd_7                   0x004A
 	#define	LSb32VIPSTS_STS11_dviSts1_rd_7                      24
 	#define	LSb16VIPSTS_STS11_dviSts1_rd_7                      8
 	#define	bVIPSTS_STS11_dviSts1_rd_7                   8
 	#define	MSK32VIPSTS_STS11_dviSts1_rd_7                      0xFF000000
 	#define	RA_VIP_WriteClient_Wr                          0x0000
 	#define	BA_VIP_WriteClient_Wr_start                    0x0000
 	#define	B16VIP_WriteClient_Wr_start                    0x0000
 	#define	LSb32VIP_WriteClient_Wr_start                       0
 	#define	LSb16VIP_WriteClient_Wr_start                       0
 	#define	bVIP_WriteClient_Wr_start                    1
 	#define	MSK32VIP_WriteClient_Wr_start                       0x00000001
 	#define	BA_VIP_WriteClient_Wr_clear                    0x0000
 	#define	B16VIP_WriteClient_Wr_clear                    0x0000
 	#define	LSb32VIP_WriteClient_Wr_clear                       1
 	#define	LSb16VIP_WriteClient_Wr_clear                       1
 	#define	bVIP_WriteClient_Wr_clear                    1
 	#define	MSK32VIP_WriteClient_Wr_clear                       0x00000002
 	#define	RA_VIP_WriteClient_pix                         0x0004
 	#define	BA_VIP_WriteClient_pix_tot                     0x0004
 	#define	B16VIP_WriteClient_pix_tot                     0x0004
 	#define	LSb32VIP_WriteClient_pix_tot                        0
 	#define	LSb16VIP_WriteClient_pix_tot                        0
 	#define	bVIP_WriteClient_pix_tot                     32
 	#define	MSK32VIP_WriteClient_pix_tot                        0xFFFFFFFF
 	#define	RA_VIP_WriteClient_NonStdRes                   0x0008
 	#define	BA_VIP_WriteClient_NonStdRes_enable            0x0008
 	#define	B16VIP_WriteClient_NonStdRes_enable            0x0008
 	#define	LSb32VIP_WriteClient_NonStdRes_enable               0
 	#define	LSb16VIP_WriteClient_NonStdRes_enable               0
 	#define	bVIP_WriteClient_NonStdRes_enable            1
 	#define	MSK32VIP_WriteClient_NonStdRes_enable               0x00000001
 	#define	BA_VIP_WriteClient_NonStdRes_pixlineTot        0x0008
 	#define	B16VIP_WriteClient_NonStdRes_pixlineTot        0x0008
 	#define	LSb32VIP_WriteClient_NonStdRes_pixlineTot           1
 	#define	LSb16VIP_WriteClient_NonStdRes_pixlineTot           1
 	#define	bVIP_WriteClient_NonStdRes_pixlineTot        13
 	#define	MSK32VIP_WriteClient_NonStdRes_pixlineTot           0x00003FFE
 	#define	RA_VIP_WriteClient_pack                        0x000C
 	#define	BA_VIP_WriteClient_pack_Sel                    0x000C
 	#define	B16VIP_WriteClient_pack_Sel                    0x000C
 	#define	LSb32VIP_WriteClient_pack_Sel                       0
 	#define	LSb16VIP_WriteClient_pack_Sel                       0
 	#define	bVIP_WriteClient_pack_Sel                    4
 	#define	MSK32VIP_WriteClient_pack_Sel                       0x0000000F
 	#define	RA_HDMIRX_PIPE_CTRL                            0x0000
 	#define	BA_HDMIRX_PIPE_CTRL_SCL_CLKEN_CTRL             0x0000
 	#define	B16HDMIRX_PIPE_CTRL_SCL_CLKEN_CTRL             0x0000
 	#define	LSb32HDMIRX_PIPE_CTRL_SCL_CLKEN_CTRL                0
 	#define	LSb16HDMIRX_PIPE_CTRL_SCL_CLKEN_CTRL                0
 	#define	bHDMIRX_PIPE_CTRL_SCL_CLKEN_CTRL             1
 	#define	MSK32HDMIRX_PIPE_CTRL_SCL_CLKEN_CTRL                0x00000001
 	#define	BA_HDMIRX_PIPE_CTRL_fifo_sts_ctrl              0x0000
 	#define	B16HDMIRX_PIPE_CTRL_fifo_sts_ctrl              0x0000
 	#define	LSb32HDMIRX_PIPE_CTRL_fifo_sts_ctrl                 1
 	#define	LSb16HDMIRX_PIPE_CTRL_fifo_sts_ctrl                 1
 	#define	bHDMIRX_PIPE_CTRL_fifo_sts_ctrl              1
 	#define	MSK32HDMIRX_PIPE_CTRL_fifo_sts_ctrl                 0x00000002
 	#define	BA_HDMIRX_PIPE_CTRL_scl1d_in                   0x0000
 	#define	B16HDMIRX_PIPE_CTRL_scl1d_in                   0x0000
 	#define	LSb32HDMIRX_PIPE_CTRL_scl1d_in                      2
 	#define	LSb16HDMIRX_PIPE_CTRL_scl1d_in                      2
 	#define	bHDMIRX_PIPE_CTRL_scl1d_in                   1
 	#define	MSK32HDMIRX_PIPE_CTRL_scl1d_in                      0x00000004
 	#define	BA_HDMIRX_PIPE_CTRL_sb_clkg_en                 0x0000
 	#define	B16HDMIRX_PIPE_CTRL_sb_clkg_en                 0x0000
 	#define	LSb32HDMIRX_PIPE_CTRL_sb_clkg_en                    3
 	#define	LSb16HDMIRX_PIPE_CTRL_sb_clkg_en                    3
 	#define	bHDMIRX_PIPE_CTRL_sb_clkg_en                 1
 	#define	MSK32HDMIRX_PIPE_CTRL_sb_clkg_en                    0x00000008
 	#define	BA_HDMIRX_PIPE_CTRL_cfg_rst                    0x0000
 	#define	B16HDMIRX_PIPE_CTRL_cfg_rst                    0x0000
 	#define	LSb32HDMIRX_PIPE_CTRL_cfg_rst                       4
 	#define	LSb16HDMIRX_PIPE_CTRL_cfg_rst                       4
 	#define	bHDMIRX_PIPE_CTRL_cfg_rst                    1
 	#define	MSK32HDMIRX_PIPE_CTRL_cfg_rst                       0x00000010
 	#define	BA_HDMIRX_PIPE_CTRL_scl1d_sw_rst               0x0000
 	#define	B16HDMIRX_PIPE_CTRL_scl1d_sw_rst               0x0000
 	#define	LSb32HDMIRX_PIPE_CTRL_scl1d_sw_rst                  5
 	#define	LSb16HDMIRX_PIPE_CTRL_scl1d_sw_rst                  5
 	#define	bHDMIRX_PIPE_CTRL_scl1d_sw_rst               1
 	#define	MSK32HDMIRX_PIPE_CTRL_scl1d_sw_rst                  0x00000020
 	#define	BA_HDMIRX_PIPE_CTRL_scl_rst_en0                0x0000
 	#define	B16HDMIRX_PIPE_CTRL_scl_rst_en0                0x0000
 	#define	LSb32HDMIRX_PIPE_CTRL_scl_rst_en0                   6
 	#define	LSb16HDMIRX_PIPE_CTRL_scl_rst_en0                   6
 	#define	bHDMIRX_PIPE_CTRL_scl_rst_en0                1
 	#define	MSK32HDMIRX_PIPE_CTRL_scl_rst_en0                   0x00000040
 	#define	BA_HDMIRX_PIPE_CTRL_scl_rst_en1                0x0000
 	#define	B16HDMIRX_PIPE_CTRL_scl_rst_en1                0x0000
 	#define	LSb32HDMIRX_PIPE_CTRL_scl_rst_en1                   7
 	#define	LSb16HDMIRX_PIPE_CTRL_scl_rst_en1                   7
 	#define	bHDMIRX_PIPE_CTRL_scl_rst_en1                1
 	#define	MSK32HDMIRX_PIPE_CTRL_scl_rst_en1                   0x00000080
 	#define	BA_HDMIRX_PIPE_CTRL_read_sel                   0x0001
 	#define	B16HDMIRX_PIPE_CTRL_read_sel                   0x0000
 	#define	LSb32HDMIRX_PIPE_CTRL_read_sel                      8
 	#define	LSb16HDMIRX_PIPE_CTRL_read_sel                      8
 	#define	bHDMIRX_PIPE_CTRL_read_sel                   2
 	#define	MSK32HDMIRX_PIPE_CTRL_read_sel                      0x00000300
 	#define	BA_HDMIRX_PIPE_CTRL_clken_cnt                  0x0001
 	#define	B16HDMIRX_PIPE_CTRL_clken_cnt                  0x0000
 	#define	LSb32HDMIRX_PIPE_CTRL_clken_cnt                     10
 	#define	LSb16HDMIRX_PIPE_CTRL_clken_cnt                     10
 	#define	bHDMIRX_PIPE_CTRL_clken_cnt                  4
 	#define	MSK32HDMIRX_PIPE_CTRL_clken_cnt                     0x00003C00
 	#define	BA_HDMIRX_PIPE_CTRL_clken_ctrl                 0x0001
 	#define	B16HDMIRX_PIPE_CTRL_clken_ctrl                 0x0000
 	#define	LSb32HDMIRX_PIPE_CTRL_clken_ctrl                    14
 	#define	LSb16HDMIRX_PIPE_CTRL_clken_ctrl                    14
 	#define	bHDMIRX_PIPE_CTRL_clken_ctrl                 1
 	#define	MSK32HDMIRX_PIPE_CTRL_clken_ctrl                    0x00004000
 	#define	BA_HDMIRX_PIPE_CTRL_tgEof_en                   0x0001
 	#define	B16HDMIRX_PIPE_CTRL_tgEof_en                   0x0000
 	#define	LSb32HDMIRX_PIPE_CTRL_tgEof_en                      15
 	#define	LSb16HDMIRX_PIPE_CTRL_tgEof_en                      15
 	#define	bHDMIRX_PIPE_CTRL_tgEof_en                   1
 	#define	MSK32HDMIRX_PIPE_CTRL_tgEof_en                      0x00008000
 	#define	BA_HDMIRX_PIPE_CTRL_rdy_sts0_en                0x0002
 	#define	B16HDMIRX_PIPE_CTRL_rdy_sts0_en                0x0002
 	#define	LSb32HDMIRX_PIPE_CTRL_rdy_sts0_en                   16
 	#define	LSb16HDMIRX_PIPE_CTRL_rdy_sts0_en                   0
 	#define	bHDMIRX_PIPE_CTRL_rdy_sts0_en                1
 	#define	MSK32HDMIRX_PIPE_CTRL_rdy_sts0_en                   0x00010000
 	#define	BA_HDMIRX_PIPE_CTRL_rdy_sts1_en                0x0002
 	#define	B16HDMIRX_PIPE_CTRL_rdy_sts1_en                0x0002
 	#define	LSb32HDMIRX_PIPE_CTRL_rdy_sts1_en                   17
 	#define	LSb16HDMIRX_PIPE_CTRL_rdy_sts1_en                   1
 	#define	bHDMIRX_PIPE_CTRL_rdy_sts1_en                1
 	#define	MSK32HDMIRX_PIPE_CTRL_rdy_sts1_en                   0x00020000
 	#define	BA_HDMIRX_PIPE_CTRL_hdmi420sp_wrbk             0x0002
 	#define	B16HDMIRX_PIPE_CTRL_hdmi420sp_wrbk             0x0002
 	#define	LSb32HDMIRX_PIPE_CTRL_hdmi420sp_wrbk                18
 	#define	LSb16HDMIRX_PIPE_CTRL_hdmi420sp_wrbk                2
 	#define	bHDMIRX_PIPE_CTRL_hdmi420sp_wrbk             1
 	#define	MSK32HDMIRX_PIPE_CTRL_hdmi420sp_wrbk                0x00040000
 	#define	RA_HDMIRX_PIPE_BYPASS_CTRL                     0x0004
 	#define	BA_HDMIRX_PIPE_BYPASS_CTRL_scl1d_bypass        0x0004
 	#define	B16HDMIRX_PIPE_BYPASS_CTRL_scl1d_bypass        0x0004
 	#define	LSb32HDMIRX_PIPE_BYPASS_CTRL_scl1d_bypass           0
 	#define	LSb16HDMIRX_PIPE_BYPASS_CTRL_scl1d_bypass           0
 	#define	bHDMIRX_PIPE_BYPASS_CTRL_scl1d_bypass        1
 	#define	MSK32HDMIRX_PIPE_BYPASS_CTRL_scl1d_bypass           0x00000001
 	#define	BA_HDMIRX_PIPE_BYPASS_CTRL_ups420_bypass       0x0004
 	#define	B16HDMIRX_PIPE_BYPASS_CTRL_ups420_bypass       0x0004
 	#define	LSb32HDMIRX_PIPE_BYPASS_CTRL_ups420_bypass          1
 	#define	LSb16HDMIRX_PIPE_BYPASS_CTRL_ups420_bypass          1
 	#define	bHDMIRX_PIPE_BYPASS_CTRL_ups420_bypass       1
 	#define	MSK32HDMIRX_PIPE_BYPASS_CTRL_ups420_bypass          0x00000002
 	#define	BA_HDMIRX_PIPE_BYPASS_CTRL_csc_bypass          0x0004
 	#define	B16HDMIRX_PIPE_BYPASS_CTRL_csc_bypass          0x0004
 	#define	LSb32HDMIRX_PIPE_BYPASS_CTRL_csc_bypass             2
 	#define	LSb16HDMIRX_PIPE_BYPASS_CTRL_csc_bypass             2
 	#define	bHDMIRX_PIPE_BYPASS_CTRL_csc_bypass          1
 	#define	MSK32HDMIRX_PIPE_BYPASS_CTRL_csc_bypass             0x00000004
 	#define	BA_HDMIRX_PIPE_BYPASS_CTRL_dns444_422_bypass   0x0004
 	#define	B16HDMIRX_PIPE_BYPASS_CTRL_dns444_422_bypass   0x0004
 	#define	LSb32HDMIRX_PIPE_BYPASS_CTRL_dns444_422_bypass      3
 	#define	LSb16HDMIRX_PIPE_BYPASS_CTRL_dns444_422_bypass      3
 	#define	bHDMIRX_PIPE_BYPASS_CTRL_dns444_422_bypass   1
 	#define	MSK32HDMIRX_PIPE_BYPASS_CTRL_dns444_422_bypass      0x00000008
 	#define	BA_HDMIRX_PIPE_BYPASS_CTRL_dither_bypass       0x0004
 	#define	B16HDMIRX_PIPE_BYPASS_CTRL_dither_bypass       0x0004
 	#define	LSb32HDMIRX_PIPE_BYPASS_CTRL_dither_bypass          4
 	#define	LSb16HDMIRX_PIPE_BYPASS_CTRL_dither_bypass          4
 	#define	bHDMIRX_PIPE_BYPASS_CTRL_dither_bypass       1
 	#define	MSK32HDMIRX_PIPE_BYPASS_CTRL_dither_bypass          0x00000010
 	#define	RA_HDMIRX_PIPE_tg_ctrl                         0x0008
 	#define	BA_HDMIRX_PIPE_tg_ctrl_start                   0x0008
 	#define	B16HDMIRX_PIPE_tg_ctrl_start                   0x0008
 	#define	LSb32HDMIRX_PIPE_tg_ctrl_start                      0
 	#define	LSb16HDMIRX_PIPE_tg_ctrl_start                      0
 	#define	bHDMIRX_PIPE_tg_ctrl_start                   1
 	#define	MSK32HDMIRX_PIPE_tg_ctrl_start                      0x00000001
 	#define	BA_HDMIRX_PIPE_tg_ctrl_clear                   0x0008
 	#define	B16HDMIRX_PIPE_tg_ctrl_clear                   0x0008
 	#define	LSb32HDMIRX_PIPE_tg_ctrl_clear                      1
 	#define	LSb16HDMIRX_PIPE_tg_ctrl_clear                      1
 	#define	bHDMIRX_PIPE_tg_ctrl_clear                   1
 	#define	MSK32HDMIRX_PIPE_tg_ctrl_clear                      0x00000002
 	#define	RA_HDMIRX_PIPE_CFG0                            0x000C
 	#define	BA_HDMIRX_PIPE_CFG0_pat_vopFifo_ctrl           0x000C
 	#define	B16HDMIRX_PIPE_CFG0_pat_vopFifo_ctrl           0x000C
 	#define	LSb32HDMIRX_PIPE_CFG0_pat_vopFifo_ctrl              0
 	#define	LSb16HDMIRX_PIPE_CFG0_pat_vopFifo_ctrl              0
 	#define	bHDMIRX_PIPE_CFG0_pat_vopFifo_ctrl           1
 	#define	MSK32HDMIRX_PIPE_CFG0_pat_vopFifo_ctrl              0x00000001
 	#define	BA_HDMIRX_PIPE_CFG0_patvop_fifoCLR             0x000C
 	#define	B16HDMIRX_PIPE_CFG0_patvop_fifoCLR             0x000C
 	#define	LSb32HDMIRX_PIPE_CFG0_patvop_fifoCLR                1
 	#define	LSb16HDMIRX_PIPE_CFG0_patvop_fifoCLR                1
 	#define	bHDMIRX_PIPE_CFG0_patvop_fifoCLR             1
 	#define	MSK32HDMIRX_PIPE_CFG0_patvop_fifoCLR                0x00000002
 	#define	BA_HDMIRX_PIPE_CFG0_CfgSelAlgn                 0x000C
 	#define	B16HDMIRX_PIPE_CFG0_CfgSelAlgn                 0x000C
 	#define	LSb32HDMIRX_PIPE_CFG0_CfgSelAlgn                    2
 	#define	LSb16HDMIRX_PIPE_CFG0_CfgSelAlgn                    2
 	#define	bHDMIRX_PIPE_CFG0_CfgSelAlgn                 8
 	#define	MSK32HDMIRX_PIPE_CFG0_CfgSelAlgn                    0x000003FC
 	#define	BA_HDMIRX_PIPE_CFG0_CfgSel_12_10_8             0x000D
 	#define	B16HDMIRX_PIPE_CFG0_CfgSel_12_10_8             0x000C
 	#define	LSb32HDMIRX_PIPE_CFG0_CfgSel_12_10_8                10
 	#define	LSb16HDMIRX_PIPE_CFG0_CfgSel_12_10_8                10
 	#define	bHDMIRX_PIPE_CFG0_CfgSel_12_10_8             4
 	#define	MSK32HDMIRX_PIPE_CFG0_CfgSel_12_10_8                0x00003C00
 	#define	BA_HDMIRX_PIPE_CFG0_fifo_rd_sel                0x000D
 	#define	B16HDMIRX_PIPE_CFG0_fifo_rd_sel                0x000C
 	#define	LSb32HDMIRX_PIPE_CFG0_fifo_rd_sel                   14
 	#define	LSb16HDMIRX_PIPE_CFG0_fifo_rd_sel                   14
 	#define	bHDMIRX_PIPE_CFG0_fifo_rd_sel                1
 	#define	MSK32HDMIRX_PIPE_CFG0_fifo_rd_sel                   0x00004000
 	#define	BA_HDMIRX_PIPE_CFG0_rd_en_init                 0x000D
 	#define	B16HDMIRX_PIPE_CFG0_rd_en_init                 0x000C
 	#define	LSb32HDMIRX_PIPE_CFG0_rd_en_init                    15
 	#define	LSb16HDMIRX_PIPE_CFG0_rd_en_init                    15
 	#define	bHDMIRX_PIPE_CFG0_rd_en_init                 1
 	#define	MSK32HDMIRX_PIPE_CFG0_rd_en_init                    0x00008000
 	#define	BA_HDMIRX_PIPE_CFG0_hdmi_pk_8b_10b             0x000E
 	#define	B16HDMIRX_PIPE_CFG0_hdmi_pk_8b_10b             0x000E
 	#define	LSb32HDMIRX_PIPE_CFG0_hdmi_pk_8b_10b                16
 	#define	LSb16HDMIRX_PIPE_CFG0_hdmi_pk_8b_10b                0
 	#define	bHDMIRX_PIPE_CFG0_hdmi_pk_8b_10b             1
 	#define	MSK32HDMIRX_PIPE_CFG0_hdmi_pk_8b_10b                0x00010000
 	#define	BA_HDMIRX_PIPE_CFG0_rd_init0                   0x000E
 	#define	B16HDMIRX_PIPE_CFG0_rd_init0                   0x000E
 	#define	LSb32HDMIRX_PIPE_CFG0_rd_init0                      17
 	#define	LSb16HDMIRX_PIPE_CFG0_rd_init0                      1
 	#define	bHDMIRX_PIPE_CFG0_rd_init0                   1
 	#define	MSK32HDMIRX_PIPE_CFG0_rd_init0                      0x00020000
 	#define	BA_HDMIRX_PIPE_CFG0_rden_sft_rst               0x000E
 	#define	B16HDMIRX_PIPE_CFG0_rden_sft_rst               0x000E
 	#define	LSb32HDMIRX_PIPE_CFG0_rden_sft_rst                  18
 	#define	LSb16HDMIRX_PIPE_CFG0_rden_sft_rst                  2
 	#define	bHDMIRX_PIPE_CFG0_rden_sft_rst               1
 	#define	MSK32HDMIRX_PIPE_CFG0_rden_sft_rst                  0x00040000
 	#define	BA_HDMIRX_PIPE_CFG0_vsync_cnt_val              0x000E
 	#define	B16HDMIRX_PIPE_CFG0_vsync_cnt_val              0x000E
 	#define	LSb32HDMIRX_PIPE_CFG0_vsync_cnt_val                 19
 	#define	LSb16HDMIRX_PIPE_CFG0_vsync_cnt_val                 3
 	#define	bHDMIRX_PIPE_CFG0_vsync_cnt_val              5
 	#define	MSK32HDMIRX_PIPE_CFG0_vsync_cnt_val                 0x00F80000
 	#define	BA_HDMIRX_PIPE_CFG0_start_mask_reset           0x000F
 	#define	B16HDMIRX_PIPE_CFG0_start_mask_reset           0x000E
 	#define	LSb32HDMIRX_PIPE_CFG0_start_mask_reset              24
 	#define	LSb16HDMIRX_PIPE_CFG0_start_mask_reset              8
 	#define	bHDMIRX_PIPE_CFG0_start_mask_reset           1
 	#define	MSK32HDMIRX_PIPE_CFG0_start_mask_reset              0x01000000
 	#define	BA_HDMIRX_PIPE_CFG0_write_sel_8b               0x000F
 	#define	B16HDMIRX_PIPE_CFG0_write_sel_8b               0x000E
 	#define	LSb32HDMIRX_PIPE_CFG0_write_sel_8b                  25
 	#define	LSb16HDMIRX_PIPE_CFG0_write_sel_8b                  9
 	#define	bHDMIRX_PIPE_CFG0_write_sel_8b               1
 	#define	MSK32HDMIRX_PIPE_CFG0_write_sel_8b                  0x02000000
 	#define	BA_HDMIRX_PIPE_CFG0_hdmipk_420_sel             0x000F
 	#define	B16HDMIRX_PIPE_CFG0_hdmipk_420_sel             0x000E
 	#define	LSb32HDMIRX_PIPE_CFG0_hdmipk_420_sel                26
 	#define	LSb16HDMIRX_PIPE_CFG0_hdmipk_420_sel                10
 	#define	bHDMIRX_PIPE_CFG0_hdmipk_420_sel             1
 	#define	MSK32HDMIRX_PIPE_CFG0_hdmipk_420_sel                0x04000000
 	#define	BA_HDMIRX_PIPE_CFG0_clock_en_sel               0x000F
 	#define	B16HDMIRX_PIPE_CFG0_clock_en_sel               0x000E
 	#define	LSb32HDMIRX_PIPE_CFG0_clock_en_sel                  27
 	#define	LSb16HDMIRX_PIPE_CFG0_clock_en_sel                  11
 	#define	bHDMIRX_PIPE_CFG0_clock_en_sel               1
 	#define	MSK32HDMIRX_PIPE_CFG0_clock_en_sel                  0x08000000
 	#define	BA_HDMIRX_PIPE_CFG0_pol_ctrl                   0x000F
 	#define	B16HDMIRX_PIPE_CFG0_pol_ctrl                   0x000E
 	#define	LSb32HDMIRX_PIPE_CFG0_pol_ctrl                      28
 	#define	LSb16HDMIRX_PIPE_CFG0_pol_ctrl                      12
 	#define	bHDMIRX_PIPE_CFG0_pol_ctrl                   1
 	#define	MSK32HDMIRX_PIPE_CFG0_pol_ctrl                      0x10000000
 	#define	BA_HDMIRX_PIPE_CFG0_sp_wrbk_8b                 0x000F
 	#define	B16HDMIRX_PIPE_CFG0_sp_wrbk_8b                 0x000E
 	#define	LSb32HDMIRX_PIPE_CFG0_sp_wrbk_8b                    29
 	#define	LSb16HDMIRX_PIPE_CFG0_sp_wrbk_8b                    13
 	#define	bHDMIRX_PIPE_CFG0_sp_wrbk_8b                 1
 	#define	MSK32HDMIRX_PIPE_CFG0_sp_wrbk_8b                    0x20000000
 	#define	RA_HDMIRX_PIPE_CFG1                            0x0010
 	#define	BA_HDMIRX_PIPE_CFG1_vs_cnt                     0x0010
 	#define	B16HDMIRX_PIPE_CFG1_vs_cnt                     0x0010
 	#define	LSb32HDMIRX_PIPE_CFG1_vs_cnt                        0
 	#define	LSb16HDMIRX_PIPE_CFG1_vs_cnt                        0
 	#define	bHDMIRX_PIPE_CFG1_vs_cnt                     32
 	#define	MSK32HDMIRX_PIPE_CFG1_vs_cnt                        0xFFFFFFFF
 	#define	RA_HDMIRX_PIPE_CFG2                            0x0014
 	#define	BA_HDMIRX_PIPE_CFG2_hs_cnt                     0x0014
 	#define	B16HDMIRX_PIPE_CFG2_hs_cnt                     0x0014
 	#define	LSb32HDMIRX_PIPE_CFG2_hs_cnt                        0
 	#define	LSb16HDMIRX_PIPE_CFG2_hs_cnt                        0
 	#define	bHDMIRX_PIPE_CFG2_hs_cnt                     16
 	#define	MSK32HDMIRX_PIPE_CFG2_hs_cnt                        0x0000FFFF
 	#define	BA_HDMIRX_PIPE_CFG2_sync_pol_ctrl              0x0016
 	#define	B16HDMIRX_PIPE_CFG2_sync_pol_ctrl              0x0016
 	#define	LSb32HDMIRX_PIPE_CFG2_sync_pol_ctrl                 16
 	#define	LSb16HDMIRX_PIPE_CFG2_sync_pol_ctrl                 0
 	#define	bHDMIRX_PIPE_CFG2_sync_pol_ctrl              2
 	#define	MSK32HDMIRX_PIPE_CFG2_sync_pol_ctrl                 0x00030000
 	#define	BA_HDMIRX_PIPE_CFG2_sync_sts_en                0x0016
 	#define	B16HDMIRX_PIPE_CFG2_sync_sts_en                0x0016
 	#define	LSb32HDMIRX_PIPE_CFG2_sync_sts_en                   18
 	#define	LSb16HDMIRX_PIPE_CFG2_sync_sts_en                   2
 	#define	bHDMIRX_PIPE_CFG2_sync_sts_en                2
 	#define	MSK32HDMIRX_PIPE_CFG2_sync_sts_en                   0x000C0000
 	#define	BA_HDMIRX_PIPE_CFG2_sts_clr                    0x0016
 	#define	B16HDMIRX_PIPE_CFG2_sts_clr                    0x0016
 	#define	LSb32HDMIRX_PIPE_CFG2_sts_clr                       20
 	#define	LSb16HDMIRX_PIPE_CFG2_sts_clr                       4
 	#define	bHDMIRX_PIPE_CFG2_sts_clr                    1
 	#define	MSK32HDMIRX_PIPE_CFG2_sts_clr                       0x00100000
 	#define	BA_HDMIRX_PIPE_CFG2_stsflg_clr_en              0x0016
 	#define	B16HDMIRX_PIPE_CFG2_stsflg_clr_en              0x0016
 	#define	LSb32HDMIRX_PIPE_CFG2_stsflg_clr_en                 21
 	#define	LSb16HDMIRX_PIPE_CFG2_stsflg_clr_en                 5
 	#define	bHDMIRX_PIPE_CFG2_stsflg_clr_en              1
 	#define	MSK32HDMIRX_PIPE_CFG2_stsflg_clr_en                 0x00200000
 	#define	BA_HDMIRX_PIPE_CFG2_interlace_inp_en           0x0016
 	#define	B16HDMIRX_PIPE_CFG2_interlace_inp_en           0x0016
 	#define	LSb32HDMIRX_PIPE_CFG2_interlace_inp_en              22
 	#define	LSb16HDMIRX_PIPE_CFG2_interlace_inp_en              6
 	#define	bHDMIRX_PIPE_CFG2_interlace_inp_en           1
 	#define	MSK32HDMIRX_PIPE_CFG2_interlace_inp_en              0x00400000
 	#define	BA_HDMIRX_PIPE_CFG2_patgenFifo_stsClr          0x0016
 	#define	B16HDMIRX_PIPE_CFG2_patgenFifo_stsClr          0x0016
 	#define	LSb32HDMIRX_PIPE_CFG2_patgenFifo_stsClr             23
 	#define	LSb16HDMIRX_PIPE_CFG2_patgenFifo_stsClr             7
 	#define	bHDMIRX_PIPE_CFG2_patgenFifo_stsClr          1
 	#define	MSK32HDMIRX_PIPE_CFG2_patgenFifo_stsClr             0x00800000
 	#define	BA_HDMIRX_PIPE_CFG2_hdmiRxFifo_stsClr          0x0017
 	#define	B16HDMIRX_PIPE_CFG2_hdmiRxFifo_stsClr          0x0016
 	#define	LSb32HDMIRX_PIPE_CFG2_hdmiRxFifo_stsClr             24
 	#define	LSb16HDMIRX_PIPE_CFG2_hdmiRxFifo_stsClr             8
 	#define	bHDMIRX_PIPE_CFG2_hdmiRxFifo_stsClr          1
 	#define	MSK32HDMIRX_PIPE_CFG2_hdmiRxFifo_stsClr             0x01000000
 	#define	RA_HDMIRX_PIPE_CFG3                            0x0018
 	#define	BA_HDMIRX_PIPE_CFG3_fldsts_l                   0x0018
 	#define	B16HDMIRX_PIPE_CFG3_fldsts_l                   0x0018
 	#define	LSb32HDMIRX_PIPE_CFG3_fldsts_l                      0
 	#define	LSb16HDMIRX_PIPE_CFG3_fldsts_l                      0
 	#define	bHDMIRX_PIPE_CFG3_fldsts_l                   16
 	#define	MSK32HDMIRX_PIPE_CFG3_fldsts_l                      0x0000FFFF
 	#define	BA_HDMIRX_PIPE_CFG3_fldsts_h                   0x001A
 	#define	B16HDMIRX_PIPE_CFG3_fldsts_h                   0x001A
 	#define	LSb32HDMIRX_PIPE_CFG3_fldsts_h                      16
 	#define	LSb16HDMIRX_PIPE_CFG3_fldsts_h                      0
 	#define	bHDMIRX_PIPE_CFG3_fldsts_h                   16
 	#define	MSK32HDMIRX_PIPE_CFG3_fldsts_h                      0xFFFF0000
 	#define	RA_HDMIRX_PIPE_CFG4                            0x001C
 	#define	BA_HDMIRX_PIPE_CFG4_dvtest_offsclr_Fifoctrl    0x001C
 	#define	B16HDMIRX_PIPE_CFG4_dvtest_offsclr_Fifoctrl    0x001C
 	#define	LSb32HDMIRX_PIPE_CFG4_dvtest_offsclr_Fifoctrl       0
 	#define	LSb16HDMIRX_PIPE_CFG4_dvtest_offsclr_Fifoctrl       0
 	#define	bHDMIRX_PIPE_CFG4_dvtest_offsclr_Fifoctrl    1
 	#define	MSK32HDMIRX_PIPE_CFG4_dvtest_offsclr_Fifoctrl       0x00000001
 	#define	BA_HDMIRX_PIPE_CFG4_dvtest_ups420sp_datasel    0x001C
 	#define	B16HDMIRX_PIPE_CFG4_dvtest_ups420sp_datasel    0x001C
 	#define	LSb32HDMIRX_PIPE_CFG4_dvtest_ups420sp_datasel       1
 	#define	LSb16HDMIRX_PIPE_CFG4_dvtest_ups420sp_datasel       1
 	#define	bHDMIRX_PIPE_CFG4_dvtest_ups420sp_datasel    1
 	#define	MSK32HDMIRX_PIPE_CFG4_dvtest_ups420sp_datasel       0x00000002
 	#define	BA_HDMIRX_PIPE_CFG4_dlbyedr_datasel            0x001C
 	#define	B16HDMIRX_PIPE_CFG4_dlbyedr_datasel            0x001C
 	#define	LSb32HDMIRX_PIPE_CFG4_dlbyedr_datasel               2
 	#define	LSb16HDMIRX_PIPE_CFG4_dlbyedr_datasel               2
 	#define	bHDMIRX_PIPE_CFG4_dlbyedr_datasel            1
 	#define	MSK32HDMIRX_PIPE_CFG4_dlbyedr_datasel               0x00000004
 	#define	BA_HDMIRX_PIPE_CFG4_dvtest_fifoCLR             0x001C
 	#define	B16HDMIRX_PIPE_CFG4_dvtest_fifoCLR             0x001C
 	#define	LSb32HDMIRX_PIPE_CFG4_dvtest_fifoCLR                3
 	#define	LSb16HDMIRX_PIPE_CFG4_dvtest_fifoCLR                3
 	#define	bHDMIRX_PIPE_CFG4_dvtest_fifoCLR             1
 	#define	MSK32HDMIRX_PIPE_CFG4_dvtest_fifoCLR                0x00000008
 	#define	BA_HDMIRX_PIPE_CFG4_dlbyedr_fifoCLR            0x001C
 	#define	B16HDMIRX_PIPE_CFG4_dlbyedr_fifoCLR            0x001C
 	#define	LSb32HDMIRX_PIPE_CFG4_dlbyedr_fifoCLR               4
 	#define	LSb16HDMIRX_PIPE_CFG4_dlbyedr_fifoCLR               4
 	#define	bHDMIRX_PIPE_CFG4_dlbyedr_fifoCLR            1
 	#define	MSK32HDMIRX_PIPE_CFG4_dlbyedr_fifoCLR               0x00000010
 	#define	BA_HDMIRX_PIPE_CFG4_rdmain_initval0            0x001C
 	#define	B16HDMIRX_PIPE_CFG4_rdmain_initval0            0x001C
 	#define	LSb32HDMIRX_PIPE_CFG4_rdmain_initval0               5
 	#define	LSb16HDMIRX_PIPE_CFG4_rdmain_initval0               5
 	#define	bHDMIRX_PIPE_CFG4_rdmain_initval0            1
 	#define	MSK32HDMIRX_PIPE_CFG4_rdmain_initval0               0x00000020
 	#define	BA_HDMIRX_PIPE_CFG4_rdmain_initval1            0x001C
 	#define	B16HDMIRX_PIPE_CFG4_rdmain_initval1            0x001C
 	#define	LSb32HDMIRX_PIPE_CFG4_rdmain_initval1               6
 	#define	LSb16HDMIRX_PIPE_CFG4_rdmain_initval1               6
 	#define	bHDMIRX_PIPE_CFG4_rdmain_initval1            1
 	#define	MSK32HDMIRX_PIPE_CFG4_rdmain_initval1               0x00000040
 	#define	BA_HDMIRX_PIPE_CFG4_dvtest_dither_en           0x001C
 	#define	B16HDMIRX_PIPE_CFG4_dvtest_dither_en           0x001C
 	#define	LSb32HDMIRX_PIPE_CFG4_dvtest_dither_en              7
 	#define	LSb16HDMIRX_PIPE_CFG4_dvtest_dither_en              7
 	#define	bHDMIRX_PIPE_CFG4_dvtest_dither_en           1
 	#define	MSK32HDMIRX_PIPE_CFG4_dvtest_dither_en              0x00000080
 	#define	RA_HDMIRX_PIPE_tg_ctrl_420                     0x0020
 	#define	BA_HDMIRX_PIPE_tg_ctrl_420_rd_start            0x0020
 	#define	B16HDMIRX_PIPE_tg_ctrl_420_rd_start            0x0020
 	#define	LSb32HDMIRX_PIPE_tg_ctrl_420_rd_start               0
 	#define	LSb16HDMIRX_PIPE_tg_ctrl_420_rd_start               0
 	#define	bHDMIRX_PIPE_tg_ctrl_420_rd_start            1
 	#define	MSK32HDMIRX_PIPE_tg_ctrl_420_rd_start               0x00000001
 	#define	RA_HDMIRX_PIPE_scl1d_Inpix                     0x0024
 	#define	BA_HDMIRX_PIPE_scl1d_Inpix_tot                 0x0024
 	#define	B16HDMIRX_PIPE_scl1d_Inpix_tot                 0x0024
 	#define	LSb32HDMIRX_PIPE_scl1d_Inpix_tot                    0
 	#define	LSb16HDMIRX_PIPE_scl1d_Inpix_tot                    0
 	#define	bHDMIRX_PIPE_scl1d_Inpix_tot                 32
 	#define	MSK32HDMIRX_PIPE_scl1d_Inpix_tot                    0xFFFFFFFF
 	#define	RA_HDMIRX_PIPE_hdmirxpipe_Inpix                0x0028
 	#define	BA_HDMIRX_PIPE_hdmirxpipe_Inpix_tot            0x0028
 	#define	B16HDMIRX_PIPE_hdmirxpipe_Inpix_tot            0x0028
 	#define	LSb32HDMIRX_PIPE_hdmirxpipe_Inpix_tot               0
 	#define	LSb16HDMIRX_PIPE_hdmirxpipe_Inpix_tot               0
 	#define	bHDMIRX_PIPE_hdmirxpipe_Inpix_tot            32
 	#define	MSK32HDMIRX_PIPE_hdmirxpipe_Inpix_tot               0xFFFFFFFF
 	#define	RA_HDMIRX_PIPE_STATUS                          0x002C
 	#define	BA_HDMIRX_PIPE_STATUS_VIP_Tg                   0x002C
 	#define	B16HDMIRX_PIPE_STATUS_VIP_Tg                   0x002C
 	#define	LSb32HDMIRX_PIPE_STATUS_VIP_Tg                      0
 	#define	LSb16HDMIRX_PIPE_STATUS_VIP_Tg                      0
 	#define	bHDMIRX_PIPE_STATUS_VIP_Tg                   16
 	#define	MSK32HDMIRX_PIPE_STATUS_VIP_Tg                      0x0000FFFF
 	#define	BA_HDMIRX_PIPE_STATUS_SYNC                     0x002E
 	#define	B16HDMIRX_PIPE_STATUS_SYNC                     0x002E
 	#define	LSb32HDMIRX_PIPE_STATUS_SYNC                        16
 	#define	LSb16HDMIRX_PIPE_STATUS_SYNC                        0
 	#define	bHDMIRX_PIPE_STATUS_SYNC                     2
 	#define	MSK32HDMIRX_PIPE_STATUS_SYNC                        0x00030000
 	#define	BA_HDMIRX_PIPE_STATUS_FIELD                    0x002E
 	#define	B16HDMIRX_PIPE_STATUS_FIELD                    0x002E
 	#define	LSb32HDMIRX_PIPE_STATUS_FIELD                       18
 	#define	LSb16HDMIRX_PIPE_STATUS_FIELD                       2
 	#define	bHDMIRX_PIPE_STATUS_FIELD                    1
 	#define	MSK32HDMIRX_PIPE_STATUS_FIELD                       0x00040000
 	#define	BA_HDMIRX_PIPE_STATUS_patgenFifo_UF            0x002E
 	#define	B16HDMIRX_PIPE_STATUS_patgenFifo_UF            0x002E
 	#define	LSb32HDMIRX_PIPE_STATUS_patgenFifo_UF               19
 	#define	LSb16HDMIRX_PIPE_STATUS_patgenFifo_UF               3
 	#define	bHDMIRX_PIPE_STATUS_patgenFifo_UF            1
 	#define	MSK32HDMIRX_PIPE_STATUS_patgenFifo_UF               0x00080000
 	#define	BA_HDMIRX_PIPE_STATUS_patgenFifo_OF            0x002E
 	#define	B16HDMIRX_PIPE_STATUS_patgenFifo_OF            0x002E
 	#define	LSb32HDMIRX_PIPE_STATUS_patgenFifo_OF               20
 	#define	LSb16HDMIRX_PIPE_STATUS_patgenFifo_OF               4
 	#define	bHDMIRX_PIPE_STATUS_patgenFifo_OF            1
 	#define	MSK32HDMIRX_PIPE_STATUS_patgenFifo_OF               0x00100000
 	#define	BA_HDMIRX_PIPE_STATUS_hdrxFifo_UF              0x002E
 	#define	B16HDMIRX_PIPE_STATUS_hdrxFifo_UF              0x002E
 	#define	LSb32HDMIRX_PIPE_STATUS_hdrxFifo_UF                 21
 	#define	LSb16HDMIRX_PIPE_STATUS_hdrxFifo_UF                 5
 	#define	bHDMIRX_PIPE_STATUS_hdrxFifo_UF              1
 	#define	MSK32HDMIRX_PIPE_STATUS_hdrxFifo_UF                 0x00200000
 	#define	BA_HDMIRX_PIPE_STATUS_hdrxFifo_OF              0x002E
 	#define	B16HDMIRX_PIPE_STATUS_hdrxFifo_OF              0x002E
 	#define	LSb32HDMIRX_PIPE_STATUS_hdrxFifo_OF                 22
 	#define	LSb16HDMIRX_PIPE_STATUS_hdrxFifo_OF                 6
 	#define	bHDMIRX_PIPE_STATUS_hdrxFifo_OF              1
 	#define	MSK32HDMIRX_PIPE_STATUS_hdrxFifo_OF                 0x00400000
 	#define	BA_HDMIRX_PIPE_STATUS_PATGEN_FLD               0x002E
 	#define	B16HDMIRX_PIPE_STATUS_PATGEN_FLD               0x002E
 	#define	LSb32HDMIRX_PIPE_STATUS_PATGEN_FLD                  23
 	#define	LSb16HDMIRX_PIPE_STATUS_PATGEN_FLD                  7
 	#define	bHDMIRX_PIPE_STATUS_PATGEN_FLD               1
 	#define	MSK32HDMIRX_PIPE_STATUS_PATGEN_FLD                  0x00800000
 	#define	RA_HDMIRX_PIPE_INTR_EN                         0x0030
 	#define	BA_HDMIRX_PIPE_INTR_EN_EOF                     0x0030
 	#define	B16HDMIRX_PIPE_INTR_EN_EOF                     0x0030
 	#define	LSb32HDMIRX_PIPE_INTR_EN_EOF                        0
 	#define	LSb16HDMIRX_PIPE_INTR_EN_EOF                        0
 	#define	bHDMIRX_PIPE_INTR_EN_EOF                     1
 	#define	MSK32HDMIRX_PIPE_INTR_EN_EOF                        0x00000001
 	#define	BA_HDMIRX_PIPE_INTR_EN_HDMIRX                  0x0030
 	#define	B16HDMIRX_PIPE_INTR_EN_HDMIRX                  0x0030
 	#define	LSb32HDMIRX_PIPE_INTR_EN_HDMIRX                     1
 	#define	LSb16HDMIRX_PIPE_INTR_EN_HDMIRX                     1
 	#define	bHDMIRX_PIPE_INTR_EN_HDMIRX                  1
 	#define	MSK32HDMIRX_PIPE_INTR_EN_HDMIRX                     0x00000002
 	#define	BA_HDMIRX_PIPE_INTR_EN_SPDIFRX                 0x0030
 	#define	B16HDMIRX_PIPE_INTR_EN_SPDIFRX                 0x0030
 	#define	LSb32HDMIRX_PIPE_INTR_EN_SPDIFRX                    2
 	#define	LSb16HDMIRX_PIPE_INTR_EN_SPDIFRX                    2
 	#define	bHDMIRX_PIPE_INTR_EN_SPDIFRX                 2
 	#define	MSK32HDMIRX_PIPE_INTR_EN_SPDIFRX                    0x0000000C
 	#define	RA_HDMIRX_PIPE_VIP_WR                          0x0034
 	#define	RA_HDMIRX_PIPE_VIP_CRCH_WR                     0x0044
 	#define	RA_HDMIRX_PIPE_VIP_TG                          0x0054
 	#define	RA_HDMIRX_PIPE_SCL1D                           0x0094
 	#define	RA_HDMIRX_PIPE_VIP_1DSCL_COEFF                 0x00E8
 	#define	RA_HDMIRX_PIPE_VIP_1DSCL_FRC                   0x0104
 	#define	RA_HDMIRX_PIPE_VIP_1DSCL_DNS                   0x0120
 	#define	RA_HDMIRX_PIPE_VIP_1DSCL_UPS                   0x012C
 	#define	RA_HDMIRX_PIPE_VIP_1DSCL_CSC                   0x013C
 	#define	RA_HDMIRX_PIPE_VIP_CSC                         0x0154
 	#define	RA_HDMIRX_PIPE_VIP_DITHER                      0x0174
 	#define	RA_HDMIRX_PIPE_VIP_DNS444_422                  0x0178
 	#define	RA_HDMIRX_PIPE_VIP_UPS420_HDMI                 0x0194
 	#define	RA_HDMIRX_PIPE_VIP_PATGEN                      0x01B8
 	#define	RA_HDMIRX_PIPE_VIPSTS                          0x01E0

     #define     w32HDMIRX_PIPE_BYPASS_CTRL                     {\
             UNSG32 uBYPASS_CTRL_scl1d_bypass                   :  1;\
             UNSG32 uBYPASS_CTRL_ups420_bypass                  :  1;\
             UNSG32 uBYPASS_CTRL_csc_bypass                     :  1;\
             UNSG32 uBYPASS_CTRL_dns444_422_bypass              :  1;\
             UNSG32 uBYPASS_CTRL_dither_bypass                  :  1;\
             UNSG32 RSVDx4_b5                                   : 27;\
           }

     #define     w32HDMIRX_PIPE_CTRL                            {\
             UNSG32 uCTRL_SCL_CLKEN_CTRL                        :  1;\
             UNSG32 uCTRL_fifo_sts_ctrl                         :  1;\
             UNSG32 uCTRL_scl1d_in                              :  1;\
             UNSG32 uCTRL_sb_clkg_en                            :  1;\
             UNSG32 uCTRL_cfg_rst                               :  1;\
             UNSG32 uCTRL_scl1d_sw_rst                          :  1;\
             UNSG32 uCTRL_scl_rst_en0                           :  1;\
             UNSG32 uCTRL_scl_rst_en1                           :  1;\
             UNSG32 uCTRL_read_sel                              :  2;\
             UNSG32 uCTRL_clken_cnt                             :  4;\
             UNSG32 uCTRL_clken_ctrl                            :  1;\
             UNSG32 uCTRL_tgEof_en                              :  1;\
             UNSG32 uCTRL_rdy_sts0_en                           :  1;\
             UNSG32 uCTRL_rdy_sts1_en                           :  1;\
             UNSG32 uCTRL_hdmi420sp_wrbk                        :  1;\
             UNSG32 RSVDx0_b19                                  : 13;\
           }

     #define     w32HDMIRX_PIPE_CFG2                            {\
             UNSG32 uCFG2_hs_cnt                                : 16;\
             UNSG32 uCFG2_sync_pol_ctrl                         :  2;\
             UNSG32 uCFG2_sync_sts_en                           :  2;\
             UNSG32 uCFG2_sts_clr                               :  1;\
             UNSG32 uCFG2_stsflg_clr_en                         :  1;\
             UNSG32 uCFG2_interlace_inp_en                      :  1;\
             UNSG32 uCFG2_patgenFifo_stsClr                     :  1;\
             UNSG32 uCFG2_hdmiRxFifo_stsClr                     :  1;\
             UNSG32 RSVDx14_b25                                 :  7;\
           }

     typedef union  T32HDMIRX_PIPE_BYPASS_CTRL
           { UNSG32 u32;
             struct w32HDMIRX_PIPE_BYPASS_CTRL;
                  } T32HDMIRX_PIPE_BYPASS_CTRL;

     typedef union  T32HDMIRX_PIPE_CTRL
           { UNSG32 u32;
             struct w32HDMIRX_PIPE_CTRL;
                  } T32HDMIRX_PIPE_CTRL;

     typedef union  T32HDMIRX_PIPE_CFG2
           { UNSG32 u32;
             struct w32HDMIRX_PIPE_CFG2;
                  } T32HDMIRX_PIPE_CFG2;
 #endif