| /* |
| * Copyright Marvell Semiconductor, Inc. 2006. All rights reserved. |
| * |
| * Register address mapping configure file for rom testing code. |
| */ |
| |
| #ifndef __hdrx_H__ |
| #define __hdrx_H__ |
| |
| #define RA_HDRX_REV_ID 0x0000 |
| #define BA_HDRX_REV_ID_rev_id 0x0000 |
| #define B16HDRX_REV_ID_rev_id 0x0000 |
| #define LSb32HDRX_REV_ID_rev_id 0 |
| #define LSb16HDRX_REV_ID_rev_id 0 |
| #define bHDRX_REV_ID_rev_id 8 |
| #define MSK32HDRX_REV_ID_rev_id 0x000000FF |
| #define RA_HDRX_MHL_CTRL 0x0004 |
| #define BA_HDRX_MHL_CTRL_mhl_en 0x0004 |
| #define B16HDRX_MHL_CTRL_mhl_en 0x0004 |
| #define LSb32HDRX_MHL_CTRL_mhl_en 0 |
| #define LSb16HDRX_MHL_CTRL_mhl_en 0 |
| #define bHDRX_MHL_CTRL_mhl_en 1 |
| #define MSK32HDRX_MHL_CTRL_mhl_en 0x00000001 |
| #define BA_HDRX_MHL_CTRL_char_assrt 0x0004 |
| #define B16HDRX_MHL_CTRL_char_assrt 0x0004 |
| #define LSb32HDRX_MHL_CTRL_char_assrt 1 |
| #define LSb16HDRX_MHL_CTRL_char_assrt 1 |
| #define bHDRX_MHL_CTRL_char_assrt 8 |
| #define MSK32HDRX_MHL_CTRL_char_assrt 0x000001FE |
| #define BA_HDRX_MHL_CTRL_chnl_swap 0x0005 |
| #define B16HDRX_MHL_CTRL_chnl_swap 0x0004 |
| #define LSb32HDRX_MHL_CTRL_chnl_swap 9 |
| #define LSb16HDRX_MHL_CTRL_chnl_swap 9 |
| #define bHDRX_MHL_CTRL_chnl_swap 1 |
| #define MSK32HDRX_MHL_CTRL_chnl_swap 0x00000200 |
| #define BA_HDRX_MHL_CTRL_fifo_sft_rst 0x0005 |
| #define B16HDRX_MHL_CTRL_fifo_sft_rst 0x0004 |
| #define LSb32HDRX_MHL_CTRL_fifo_sft_rst 10 |
| #define LSb16HDRX_MHL_CTRL_fifo_sft_rst 10 |
| #define bHDRX_MHL_CTRL_fifo_sft_rst 1 |
| #define MSK32HDRX_MHL_CTRL_fifo_sft_rst 0x00000400 |
| #define BA_HDRX_MHL_CTRL_fifo_wr_ptr 0x0005 |
| #define B16HDRX_MHL_CTRL_fifo_wr_ptr 0x0004 |
| #define LSb32HDRX_MHL_CTRL_fifo_wr_ptr 11 |
| #define LSb16HDRX_MHL_CTRL_fifo_wr_ptr 11 |
| #define bHDRX_MHL_CTRL_fifo_wr_ptr 3 |
| #define MSK32HDRX_MHL_CTRL_fifo_wr_ptr 0x00003800 |
| #define BA_HDRX_MHL_CTRL_fifo_rd_ptr 0x0005 |
| #define B16HDRX_MHL_CTRL_fifo_rd_ptr 0x0004 |
| #define LSb32HDRX_MHL_CTRL_fifo_rd_ptr 14 |
| #define LSb16HDRX_MHL_CTRL_fifo_rd_ptr 14 |
| #define bHDRX_MHL_CTRL_fifo_rd_ptr 3 |
| #define MSK32HDRX_MHL_CTRL_fifo_rd_ptr 0x0001C000 |
| #define RA_HDRX_TMDS_CTRL 0x0008 |
| #define BA_HDRX_TMDS_CTRL_char_bound_sh 0x0008 |
| #define B16HDRX_TMDS_CTRL_char_bound_sh 0x0008 |
| #define LSb32HDRX_TMDS_CTRL_char_bound_sh 0 |
| #define LSb16HDRX_TMDS_CTRL_char_bound_sh 0 |
| #define bHDRX_TMDS_CTRL_char_bound_sh 8 |
| #define MSK32HDRX_TMDS_CTRL_char_bound_sh 0x000000FF |
| #define BA_HDRX_TMDS_CTRL_mode_ctrl 0x0009 |
| #define B16HDRX_TMDS_CTRL_mode_ctrl 0x0008 |
| #define LSb32HDRX_TMDS_CTRL_mode_ctrl 8 |
| #define LSb16HDRX_TMDS_CTRL_mode_ctrl 8 |
| #define bHDRX_TMDS_CTRL_mode_ctrl 2 |
| #define MSK32HDRX_TMDS_CTRL_mode_ctrl 0x00000300 |
| #define BA_HDRX_TMDS_CTRL_mode_clear 0x0009 |
| #define B16HDRX_TMDS_CTRL_mode_clear 0x0008 |
| #define LSb32HDRX_TMDS_CTRL_mode_clear 10 |
| #define LSb16HDRX_TMDS_CTRL_mode_clear 10 |
| #define bHDRX_TMDS_CTRL_mode_clear 1 |
| #define MSK32HDRX_TMDS_CTRL_mode_clear 0x00000400 |
| #define BA_HDRX_TMDS_CTRL_mode_reset 0x0009 |
| #define B16HDRX_TMDS_CTRL_mode_reset 0x0008 |
| #define LSb32HDRX_TMDS_CTRL_mode_reset 11 |
| #define LSb16HDRX_TMDS_CTRL_mode_reset 11 |
| #define bHDRX_TMDS_CTRL_mode_reset 1 |
| #define MSK32HDRX_TMDS_CTRL_mode_reset 0x00000800 |
| #define BA_HDRX_TMDS_CTRL_tmds_gb_sel_ctrl_regs 0x0009 |
| #define B16HDRX_TMDS_CTRL_tmds_gb_sel_ctrl_regs 0x0008 |
| #define LSb32HDRX_TMDS_CTRL_tmds_gb_sel_ctrl_regs 12 |
| #define LSb16HDRX_TMDS_CTRL_tmds_gb_sel_ctrl_regs 12 |
| #define bHDRX_TMDS_CTRL_tmds_gb_sel_ctrl_regs 1 |
| #define MSK32HDRX_TMDS_CTRL_tmds_gb_sel_ctrl_regs 0x00001000 |
| #define BA_HDRX_TMDS_CTRL_frm_cnt 0x0009 |
| #define B16HDRX_TMDS_CTRL_frm_cnt 0x0008 |
| #define LSb32HDRX_TMDS_CTRL_frm_cnt 13 |
| #define LSb16HDRX_TMDS_CTRL_frm_cnt 13 |
| #define bHDRX_TMDS_CTRL_frm_cnt 8 |
| #define MSK32HDRX_TMDS_CTRL_frm_cnt 0x001FE000 |
| #define BA_HDRX_TMDS_CTRL_bit_swap 0x000A |
| #define B16HDRX_TMDS_CTRL_bit_swap 0x000A |
| #define LSb32HDRX_TMDS_CTRL_bit_swap 21 |
| #define LSb16HDRX_TMDS_CTRL_bit_swap 5 |
| #define bHDRX_TMDS_CTRL_bit_swap 1 |
| #define MSK32HDRX_TMDS_CTRL_bit_swap 0x00200000 |
| #define BA_HDRX_TMDS_CTRL_chnl_swap 0x000A |
| #define B16HDRX_TMDS_CTRL_chnl_swap 0x000A |
| #define LSb32HDRX_TMDS_CTRL_chnl_swap 22 |
| #define LSb16HDRX_TMDS_CTRL_chnl_swap 6 |
| #define bHDRX_TMDS_CTRL_chnl_swap 1 |
| #define MSK32HDRX_TMDS_CTRL_chnl_swap 0x00400000 |
| #define BA_HDRX_TMDS_CTRL_scr_en 0x000A |
| #define B16HDRX_TMDS_CTRL_scr_en 0x000A |
| #define LSb32HDRX_TMDS_CTRL_scr_en 23 |
| #define LSb16HDRX_TMDS_CTRL_scr_en 7 |
| #define bHDRX_TMDS_CTRL_scr_en 1 |
| #define MSK32HDRX_TMDS_CTRL_scr_en 0x00800000 |
| #define BA_HDRX_TMDS_CTRL_scr_en_sel 0x000B |
| #define B16HDRX_TMDS_CTRL_scr_en_sel 0x000A |
| #define LSb32HDRX_TMDS_CTRL_scr_en_sel 24 |
| #define LSb16HDRX_TMDS_CTRL_scr_en_sel 8 |
| #define bHDRX_TMDS_CTRL_scr_en_sel 1 |
| #define MSK32HDRX_TMDS_CTRL_scr_en_sel 0x01000000 |
| #define BA_HDRX_TMDS_CTRL_vs_cnt_regs 0x000B |
| #define B16HDRX_TMDS_CTRL_vs_cnt_regs 0x000A |
| #define LSb32HDRX_TMDS_CTRL_vs_cnt_regs 25 |
| #define LSb16HDRX_TMDS_CTRL_vs_cnt_regs 9 |
| #define bHDRX_TMDS_CTRL_vs_cnt_regs 2 |
| #define MSK32HDRX_TMDS_CTRL_vs_cnt_regs 0x06000000 |
| #define BA_HDRX_TMDS_CTRL_tmds_bit_clk_ratio_sw 0x000B |
| #define B16HDRX_TMDS_CTRL_tmds_bit_clk_ratio_sw 0x000A |
| #define LSb32HDRX_TMDS_CTRL_tmds_bit_clk_ratio_sw 27 |
| #define LSb16HDRX_TMDS_CTRL_tmds_bit_clk_ratio_sw 11 |
| #define bHDRX_TMDS_CTRL_tmds_bit_clk_ratio_sw 1 |
| #define MSK32HDRX_TMDS_CTRL_tmds_bit_clk_ratio_sw 0x08000000 |
| #define BA_HDRX_TMDS_CTRL_tmds_bit_clk_ratio_sel 0x000B |
| #define B16HDRX_TMDS_CTRL_tmds_bit_clk_ratio_sel 0x000A |
| #define LSb32HDRX_TMDS_CTRL_tmds_bit_clk_ratio_sel 28 |
| #define LSb16HDRX_TMDS_CTRL_tmds_bit_clk_ratio_sel 12 |
| #define bHDRX_TMDS_CTRL_tmds_bit_clk_ratio_sel 1 |
| #define MSK32HDRX_TMDS_CTRL_tmds_bit_clk_ratio_sel 0x10000000 |
| #define RA_HDRX_TMDS_CTRL_1 0x000C |
| #define BA_HDRX_TMDS_CTRL_1_sscp_per 0x000C |
| #define B16HDRX_TMDS_CTRL_1_sscp_per 0x000C |
| #define LSb32HDRX_TMDS_CTRL_1_sscp_per 0 |
| #define LSb16HDRX_TMDS_CTRL_1_sscp_per 0 |
| #define bHDRX_TMDS_CTRL_1_sscp_per 4 |
| #define MSK32HDRX_TMDS_CTRL_1_sscp_per 0x0000000F |
| #define BA_HDRX_TMDS_CTRL_1_tmds_mode_lat_en 0x000C |
| #define B16HDRX_TMDS_CTRL_1_tmds_mode_lat_en 0x000C |
| #define LSb32HDRX_TMDS_CTRL_1_tmds_mode_lat_en 4 |
| #define LSb16HDRX_TMDS_CTRL_1_tmds_mode_lat_en 4 |
| #define bHDRX_TMDS_CTRL_1_tmds_mode_lat_en 1 |
| #define MSK32HDRX_TMDS_CTRL_1_tmds_mode_lat_en 0x00000010 |
| #define RA_HDRX_TMDS_ERR_INS 0x0010 |
| #define BA_HDRX_TMDS_ERR_INS_bit_err0 0x0010 |
| #define B16HDRX_TMDS_ERR_INS_bit_err0 0x0010 |
| #define LSb32HDRX_TMDS_ERR_INS_bit_err0 0 |
| #define LSb16HDRX_TMDS_ERR_INS_bit_err0 0 |
| #define bHDRX_TMDS_ERR_INS_bit_err0 1 |
| #define MSK32HDRX_TMDS_ERR_INS_bit_err0 0x00000001 |
| #define BA_HDRX_TMDS_ERR_INS_skew_err0 0x0010 |
| #define B16HDRX_TMDS_ERR_INS_skew_err0 0x0010 |
| #define LSb32HDRX_TMDS_ERR_INS_skew_err0 1 |
| #define LSb16HDRX_TMDS_ERR_INS_skew_err0 1 |
| #define bHDRX_TMDS_ERR_INS_skew_err0 3 |
| #define MSK32HDRX_TMDS_ERR_INS_skew_err0 0x0000000E |
| #define BA_HDRX_TMDS_ERR_INS_bit_err1 0x0010 |
| #define B16HDRX_TMDS_ERR_INS_bit_err1 0x0010 |
| #define LSb32HDRX_TMDS_ERR_INS_bit_err1 4 |
| #define LSb16HDRX_TMDS_ERR_INS_bit_err1 4 |
| #define bHDRX_TMDS_ERR_INS_bit_err1 1 |
| #define MSK32HDRX_TMDS_ERR_INS_bit_err1 0x00000010 |
| #define BA_HDRX_TMDS_ERR_INS_skew_err1 0x0010 |
| #define B16HDRX_TMDS_ERR_INS_skew_err1 0x0010 |
| #define LSb32HDRX_TMDS_ERR_INS_skew_err1 5 |
| #define LSb16HDRX_TMDS_ERR_INS_skew_err1 5 |
| #define bHDRX_TMDS_ERR_INS_skew_err1 3 |
| #define MSK32HDRX_TMDS_ERR_INS_skew_err1 0x000000E0 |
| #define BA_HDRX_TMDS_ERR_INS_bit_err2 0x0011 |
| #define B16HDRX_TMDS_ERR_INS_bit_err2 0x0010 |
| #define LSb32HDRX_TMDS_ERR_INS_bit_err2 8 |
| #define LSb16HDRX_TMDS_ERR_INS_bit_err2 8 |
| #define bHDRX_TMDS_ERR_INS_bit_err2 1 |
| #define MSK32HDRX_TMDS_ERR_INS_bit_err2 0x00000100 |
| #define BA_HDRX_TMDS_ERR_INS_skew_err2 0x0011 |
| #define B16HDRX_TMDS_ERR_INS_skew_err2 0x0010 |
| #define LSb32HDRX_TMDS_ERR_INS_skew_err2 9 |
| #define LSb16HDRX_TMDS_ERR_INS_skew_err2 9 |
| #define bHDRX_TMDS_ERR_INS_skew_err2 3 |
| #define MSK32HDRX_TMDS_ERR_INS_skew_err2 0x00000E00 |
| #define RA_HDRX_TMDS_STAT 0x0014 |
| #define BA_HDRX_TMDS_STAT_chn0_skew 0x0014 |
| #define B16HDRX_TMDS_STAT_chn0_skew 0x0014 |
| #define LSb32HDRX_TMDS_STAT_chn0_skew 0 |
| #define LSb16HDRX_TMDS_STAT_chn0_skew 0 |
| #define bHDRX_TMDS_STAT_chn0_skew 4 |
| #define MSK32HDRX_TMDS_STAT_chn0_skew 0x0000000F |
| #define BA_HDRX_TMDS_STAT_chn1_skew 0x0014 |
| #define B16HDRX_TMDS_STAT_chn1_skew 0x0014 |
| #define LSb32HDRX_TMDS_STAT_chn1_skew 4 |
| #define LSb16HDRX_TMDS_STAT_chn1_skew 4 |
| #define bHDRX_TMDS_STAT_chn1_skew 4 |
| #define MSK32HDRX_TMDS_STAT_chn1_skew 0x000000F0 |
| #define BA_HDRX_TMDS_STAT_chn2_skew 0x0015 |
| #define B16HDRX_TMDS_STAT_chn2_skew 0x0014 |
| #define LSb32HDRX_TMDS_STAT_chn2_skew 8 |
| #define LSb16HDRX_TMDS_STAT_chn2_skew 8 |
| #define bHDRX_TMDS_STAT_chn2_skew 4 |
| #define MSK32HDRX_TMDS_STAT_chn2_skew 0x00000F00 |
| #define BA_HDRX_TMDS_STAT_bound_sel_chn0 0x0015 |
| #define B16HDRX_TMDS_STAT_bound_sel_chn0 0x0014 |
| #define LSb32HDRX_TMDS_STAT_bound_sel_chn0 12 |
| #define LSb16HDRX_TMDS_STAT_bound_sel_chn0 12 |
| #define bHDRX_TMDS_STAT_bound_sel_chn0 4 |
| #define MSK32HDRX_TMDS_STAT_bound_sel_chn0 0x0000F000 |
| #define BA_HDRX_TMDS_STAT_bound_sel_chn1 0x0016 |
| #define B16HDRX_TMDS_STAT_bound_sel_chn1 0x0016 |
| #define LSb32HDRX_TMDS_STAT_bound_sel_chn1 16 |
| #define LSb16HDRX_TMDS_STAT_bound_sel_chn1 0 |
| #define bHDRX_TMDS_STAT_bound_sel_chn1 4 |
| #define MSK32HDRX_TMDS_STAT_bound_sel_chn1 0x000F0000 |
| #define BA_HDRX_TMDS_STAT_bound_sel_chn2 0x0016 |
| #define B16HDRX_TMDS_STAT_bound_sel_chn2 0x0016 |
| #define LSb32HDRX_TMDS_STAT_bound_sel_chn2 20 |
| #define LSb16HDRX_TMDS_STAT_bound_sel_chn2 4 |
| #define bHDRX_TMDS_STAT_bound_sel_chn2 4 |
| #define MSK32HDRX_TMDS_STAT_bound_sel_chn2 0x00F00000 |
| #define RA_HDRX_TMDS_FIFO_CTRL 0x0018 |
| #define BA_HDRX_TMDS_FIFO_CTRL_fifo0_wr_ptr 0x0018 |
| #define B16HDRX_TMDS_FIFO_CTRL_fifo0_wr_ptr 0x0018 |
| #define LSb32HDRX_TMDS_FIFO_CTRL_fifo0_wr_ptr 0 |
| #define LSb16HDRX_TMDS_FIFO_CTRL_fifo0_wr_ptr 0 |
| #define bHDRX_TMDS_FIFO_CTRL_fifo0_wr_ptr 3 |
| #define MSK32HDRX_TMDS_FIFO_CTRL_fifo0_wr_ptr 0x00000007 |
| #define BA_HDRX_TMDS_FIFO_CTRL_fifo0_rd_ptr 0x0018 |
| #define B16HDRX_TMDS_FIFO_CTRL_fifo0_rd_ptr 0x0018 |
| #define LSb32HDRX_TMDS_FIFO_CTRL_fifo0_rd_ptr 3 |
| #define LSb16HDRX_TMDS_FIFO_CTRL_fifo0_rd_ptr 3 |
| #define bHDRX_TMDS_FIFO_CTRL_fifo0_rd_ptr 3 |
| #define MSK32HDRX_TMDS_FIFO_CTRL_fifo0_rd_ptr 0x00000038 |
| #define BA_HDRX_TMDS_FIFO_CTRL_fifo1_wr_ptr 0x0018 |
| #define B16HDRX_TMDS_FIFO_CTRL_fifo1_wr_ptr 0x0018 |
| #define LSb32HDRX_TMDS_FIFO_CTRL_fifo1_wr_ptr 6 |
| #define LSb16HDRX_TMDS_FIFO_CTRL_fifo1_wr_ptr 6 |
| #define bHDRX_TMDS_FIFO_CTRL_fifo1_wr_ptr 3 |
| #define MSK32HDRX_TMDS_FIFO_CTRL_fifo1_wr_ptr 0x000001C0 |
| #define BA_HDRX_TMDS_FIFO_CTRL_fifo1_rd_ptr 0x0019 |
| #define B16HDRX_TMDS_FIFO_CTRL_fifo1_rd_ptr 0x0018 |
| #define LSb32HDRX_TMDS_FIFO_CTRL_fifo1_rd_ptr 9 |
| #define LSb16HDRX_TMDS_FIFO_CTRL_fifo1_rd_ptr 9 |
| #define bHDRX_TMDS_FIFO_CTRL_fifo1_rd_ptr 3 |
| #define MSK32HDRX_TMDS_FIFO_CTRL_fifo1_rd_ptr 0x00000E00 |
| #define BA_HDRX_TMDS_FIFO_CTRL_fifo2_wr_ptr 0x0019 |
| #define B16HDRX_TMDS_FIFO_CTRL_fifo2_wr_ptr 0x0018 |
| #define LSb32HDRX_TMDS_FIFO_CTRL_fifo2_wr_ptr 12 |
| #define LSb16HDRX_TMDS_FIFO_CTRL_fifo2_wr_ptr 12 |
| #define bHDRX_TMDS_FIFO_CTRL_fifo2_wr_ptr 3 |
| #define MSK32HDRX_TMDS_FIFO_CTRL_fifo2_wr_ptr 0x00007000 |
| #define BA_HDRX_TMDS_FIFO_CTRL_fifo2_rd_ptr 0x0019 |
| #define B16HDRX_TMDS_FIFO_CTRL_fifo2_rd_ptr 0x0018 |
| #define LSb32HDRX_TMDS_FIFO_CTRL_fifo2_rd_ptr 15 |
| #define LSb16HDRX_TMDS_FIFO_CTRL_fifo2_rd_ptr 15 |
| #define bHDRX_TMDS_FIFO_CTRL_fifo2_rd_ptr 3 |
| #define MSK32HDRX_TMDS_FIFO_CTRL_fifo2_rd_ptr 0x00038000 |
| #define BA_HDRX_TMDS_FIFO_CTRL_fifo_sft_rst 0x001A |
| #define B16HDRX_TMDS_FIFO_CTRL_fifo_sft_rst 0x001A |
| #define LSb32HDRX_TMDS_FIFO_CTRL_fifo_sft_rst 18 |
| #define LSb16HDRX_TMDS_FIFO_CTRL_fifo_sft_rst 2 |
| #define bHDRX_TMDS_FIFO_CTRL_fifo_sft_rst 1 |
| #define MSK32HDRX_TMDS_FIFO_CTRL_fifo_sft_rst 0x00040000 |
| #define RA_HDRX_VBE_FIX_CLR 0x001C |
| #define BA_HDRX_VBE_FIX_CLR_chnl0 0x001C |
| #define B16HDRX_VBE_FIX_CLR_chnl0 0x001C |
| #define LSb32HDRX_VBE_FIX_CLR_chnl0 0 |
| #define LSb16HDRX_VBE_FIX_CLR_chnl0 0 |
| #define bHDRX_VBE_FIX_CLR_chnl0 12 |
| #define MSK32HDRX_VBE_FIX_CLR_chnl0 0x00000FFF |
| #define BA_HDRX_VBE_FIX_CLR_chnl1 0x001D |
| #define B16HDRX_VBE_FIX_CLR_chnl1 0x001C |
| #define LSb32HDRX_VBE_FIX_CLR_chnl1 12 |
| #define LSb16HDRX_VBE_FIX_CLR_chnl1 12 |
| #define bHDRX_VBE_FIX_CLR_chnl1 12 |
| #define MSK32HDRX_VBE_FIX_CLR_chnl1 0x00FFF000 |
| #define RA_HDRX_VBE_FIX_CLR1 0x0020 |
| #define BA_HDRX_VBE_FIX_CLR_chnl2 0x0020 |
| #define B16HDRX_VBE_FIX_CLR_chnl2 0x0020 |
| #define LSb32HDRX_VBE_FIX_CLR_chnl2 0 |
| #define LSb16HDRX_VBE_FIX_CLR_chnl2 0 |
| #define bHDRX_VBE_FIX_CLR_chnl2 12 |
| #define MSK32HDRX_VBE_FIX_CLR_chnl2 0x00000FFF |
| #define RA_HDRX_FIX_CLR 0x0024 |
| #define BA_HDRX_FIX_CLR_chnl0 0x0024 |
| #define B16HDRX_FIX_CLR_chnl0 0x0024 |
| #define LSb32HDRX_FIX_CLR_chnl0 0 |
| #define LSb16HDRX_FIX_CLR_chnl0 0 |
| #define bHDRX_FIX_CLR_chnl0 12 |
| #define MSK32HDRX_FIX_CLR_chnl0 0x00000FFF |
| #define BA_HDRX_FIX_CLR_chnl1 0x0025 |
| #define B16HDRX_FIX_CLR_chnl1 0x0024 |
| #define LSb32HDRX_FIX_CLR_chnl1 12 |
| #define LSb16HDRX_FIX_CLR_chnl1 12 |
| #define bHDRX_FIX_CLR_chnl1 12 |
| #define MSK32HDRX_FIX_CLR_chnl1 0x00FFF000 |
| #define RA_HDRX_FIX_CLR1 0x0028 |
| #define BA_HDRX_FIX_CLR_chnl2 0x0028 |
| #define B16HDRX_FIX_CLR_chnl2 0x0028 |
| #define LSb32HDRX_FIX_CLR_chnl2 0 |
| #define LSb16HDRX_FIX_CLR_chnl2 0 |
| #define bHDRX_FIX_CLR_chnl2 12 |
| #define MSK32HDRX_FIX_CLR_chnl2 0x00000FFF |
| #define BA_HDRX_FIX_CLR_fix_clr_sel 0x0029 |
| #define B16HDRX_FIX_CLR_fix_clr_sel 0x0028 |
| #define LSb32HDRX_FIX_CLR_fix_clr_sel 12 |
| #define LSb16HDRX_FIX_CLR_fix_clr_sel 12 |
| #define bHDRX_FIX_CLR_fix_clr_sel 2 |
| #define MSK32HDRX_FIX_CLR_fix_clr_sel 0x00003000 |
| #define RA_HDRX_TESTMODE 0x002C |
| #define BA_HDRX_TESTMODE_testmode 0x002C |
| #define B16HDRX_TESTMODE_testmode 0x002C |
| #define LSb32HDRX_TESTMODE_testmode 0 |
| #define LSb16HDRX_TESTMODE_testmode 0 |
| #define bHDRX_TESTMODE_testmode 4 |
| #define MSK32HDRX_TESTMODE_testmode 0x0000000F |
| #define RA_HDRX_DI_GCP_CTRL 0x0030 |
| #define BA_HDRX_DI_GCP_CTRL_color_depth 0x0030 |
| #define B16HDRX_DI_GCP_CTRL_color_depth 0x0030 |
| #define LSb32HDRX_DI_GCP_CTRL_color_depth 0 |
| #define LSb16HDRX_DI_GCP_CTRL_color_depth 0 |
| #define bHDRX_DI_GCP_CTRL_color_depth 4 |
| #define MSK32HDRX_DI_GCP_CTRL_color_depth 0x0000000F |
| #define BA_HDRX_DI_GCP_CTRL_color_depth_sel 0x0030 |
| #define B16HDRX_DI_GCP_CTRL_color_depth_sel 0x0030 |
| #define LSb32HDRX_DI_GCP_CTRL_color_depth_sel 4 |
| #define LSb16HDRX_DI_GCP_CTRL_color_depth_sel 4 |
| #define bHDRX_DI_GCP_CTRL_color_depth_sel 1 |
| #define MSK32HDRX_DI_GCP_CTRL_color_depth_sel 0x00000010 |
| #define BA_HDRX_DI_GCP_CTRL_default_phase 0x0030 |
| #define B16HDRX_DI_GCP_CTRL_default_phase 0x0030 |
| #define LSb32HDRX_DI_GCP_CTRL_default_phase 5 |
| #define LSb16HDRX_DI_GCP_CTRL_default_phase 5 |
| #define bHDRX_DI_GCP_CTRL_default_phase 1 |
| #define MSK32HDRX_DI_GCP_CTRL_default_phase 0x00000020 |
| #define BA_HDRX_DI_GCP_CTRL_default_phase_sel 0x0030 |
| #define B16HDRX_DI_GCP_CTRL_default_phase_sel 0x0030 |
| #define LSb32HDRX_DI_GCP_CTRL_default_phase_sel 6 |
| #define LSb16HDRX_DI_GCP_CTRL_default_phase_sel 6 |
| #define bHDRX_DI_GCP_CTRL_default_phase_sel 1 |
| #define MSK32HDRX_DI_GCP_CTRL_default_phase_sel 0x00000040 |
| #define BA_HDRX_DI_GCP_CTRL_pp_phase 0x0030 |
| #define B16HDRX_DI_GCP_CTRL_pp_phase 0x0030 |
| #define LSb32HDRX_DI_GCP_CTRL_pp_phase 7 |
| #define LSb16HDRX_DI_GCP_CTRL_pp_phase 7 |
| #define bHDRX_DI_GCP_CTRL_pp_phase 4 |
| #define MSK32HDRX_DI_GCP_CTRL_pp_phase 0x00000780 |
| #define BA_HDRX_DI_GCP_CTRL_pp_align_mode 0x0031 |
| #define B16HDRX_DI_GCP_CTRL_pp_align_mode 0x0030 |
| #define LSb32HDRX_DI_GCP_CTRL_pp_align_mode 11 |
| #define LSb16HDRX_DI_GCP_CTRL_pp_align_mode 11 |
| #define bHDRX_DI_GCP_CTRL_pp_align_mode 1 |
| #define MSK32HDRX_DI_GCP_CTRL_pp_align_mode 0x00000800 |
| #define BA_HDRX_DI_GCP_CTRL_pp_phase_sel 0x0031 |
| #define B16HDRX_DI_GCP_CTRL_pp_phase_sel 0x0030 |
| #define LSb32HDRX_DI_GCP_CTRL_pp_phase_sel 12 |
| #define LSb16HDRX_DI_GCP_CTRL_pp_phase_sel 12 |
| #define bHDRX_DI_GCP_CTRL_pp_phase_sel 1 |
| #define MSK32HDRX_DI_GCP_CTRL_pp_phase_sel 0x00001000 |
| #define BA_HDRX_DI_GCP_CTRL_gcp_rx_sel 0x0031 |
| #define B16HDRX_DI_GCP_CTRL_gcp_rx_sel 0x0030 |
| #define LSb32HDRX_DI_GCP_CTRL_gcp_rx_sel 13 |
| #define LSb16HDRX_DI_GCP_CTRL_gcp_rx_sel 13 |
| #define bHDRX_DI_GCP_CTRL_gcp_rx_sel 1 |
| #define MSK32HDRX_DI_GCP_CTRL_gcp_rx_sel 0x00002000 |
| #define BA_HDRX_DI_GCP_CTRL_sw_avmute 0x0031 |
| #define B16HDRX_DI_GCP_CTRL_sw_avmute 0x0030 |
| #define LSb32HDRX_DI_GCP_CTRL_sw_avmute 14 |
| #define LSb16HDRX_DI_GCP_CTRL_sw_avmute 14 |
| #define bHDRX_DI_GCP_CTRL_sw_avmute 1 |
| #define MSK32HDRX_DI_GCP_CTRL_sw_avmute 0x00004000 |
| #define BA_HDRX_DI_GCP_CTRL_sw_avmute_en 0x0031 |
| #define B16HDRX_DI_GCP_CTRL_sw_avmute_en 0x0030 |
| #define LSb32HDRX_DI_GCP_CTRL_sw_avmute_en 15 |
| #define LSb16HDRX_DI_GCP_CTRL_sw_avmute_en 15 |
| #define bHDRX_DI_GCP_CTRL_sw_avmute_en 1 |
| #define MSK32HDRX_DI_GCP_CTRL_sw_avmute_en 0x00008000 |
| #define RA_HDRX_PIXEL_REPT_VAL 0x0034 |
| #define BA_HDRX_PIXEL_REPT_VAL_pixel_repeat_value 0x0034 |
| #define B16HDRX_PIXEL_REPT_VAL_pixel_repeat_value 0x0034 |
| #define LSb32HDRX_PIXEL_REPT_VAL_pixel_repeat_value 0 |
| #define LSb16HDRX_PIXEL_REPT_VAL_pixel_repeat_value 0 |
| #define bHDRX_PIXEL_REPT_VAL_pixel_repeat_value 4 |
| #define MSK32HDRX_PIXEL_REPT_VAL_pixel_repeat_value 0x0000000F |
| #define RA_HDRX_DC_FIFO_CTRL 0x0038 |
| #define BA_HDRX_DC_FIFO_CTRL_fifo_sft_rst 0x0038 |
| #define B16HDRX_DC_FIFO_CTRL_fifo_sft_rst 0x0038 |
| #define LSb32HDRX_DC_FIFO_CTRL_fifo_sft_rst 0 |
| #define LSb16HDRX_DC_FIFO_CTRL_fifo_sft_rst 0 |
| #define bHDRX_DC_FIFO_CTRL_fifo_sft_rst 1 |
| #define MSK32HDRX_DC_FIFO_CTRL_fifo_sft_rst 0x00000001 |
| #define BA_HDRX_DC_FIFO_CTRL_fifo_wr_ptr 0x0038 |
| #define B16HDRX_DC_FIFO_CTRL_fifo_wr_ptr 0x0038 |
| #define LSb32HDRX_DC_FIFO_CTRL_fifo_wr_ptr 1 |
| #define LSb16HDRX_DC_FIFO_CTRL_fifo_wr_ptr 1 |
| #define bHDRX_DC_FIFO_CTRL_fifo_wr_ptr 6 |
| #define MSK32HDRX_DC_FIFO_CTRL_fifo_wr_ptr 0x0000007E |
| #define BA_HDRX_DC_FIFO_CTRL_fifo_rd_ptr 0x0038 |
| #define B16HDRX_DC_FIFO_CTRL_fifo_rd_ptr 0x0038 |
| #define LSb32HDRX_DC_FIFO_CTRL_fifo_rd_ptr 7 |
| #define LSb16HDRX_DC_FIFO_CTRL_fifo_rd_ptr 7 |
| #define bHDRX_DC_FIFO_CTRL_fifo_rd_ptr 6 |
| #define MSK32HDRX_DC_FIFO_CTRL_fifo_rd_ptr 0x00001F80 |
| #define RA_HDRX_OP_CTRL 0x003C |
| #define BA_HDRX_OP_CTRL_out_chn_swap 0x003C |
| #define B16HDRX_OP_CTRL_out_chn_swap 0x003C |
| #define LSb32HDRX_OP_CTRL_out_chn_swap 0 |
| #define LSb16HDRX_OP_CTRL_out_chn_swap 0 |
| #define bHDRX_OP_CTRL_out_chn_swap 1 |
| #define MSK32HDRX_OP_CTRL_out_chn_swap 0x00000001 |
| #define BA_HDRX_OP_CTRL_video_format_select 0x003C |
| #define B16HDRX_OP_CTRL_video_format_select 0x003C |
| #define LSb32HDRX_OP_CTRL_video_format_select 1 |
| #define LSb16HDRX_OP_CTRL_video_format_select 1 |
| #define bHDRX_OP_CTRL_video_format_select 2 |
| #define MSK32HDRX_OP_CTRL_video_format_select 0x00000006 |
| #define BA_HDRX_OP_CTRL_pclk_2x 0x003C |
| #define B16HDRX_OP_CTRL_pclk_2x 0x003C |
| #define LSb32HDRX_OP_CTRL_pclk_2x 3 |
| #define LSb16HDRX_OP_CTRL_pclk_2x 3 |
| #define bHDRX_OP_CTRL_pclk_2x 1 |
| #define MSK32HDRX_OP_CTRL_pclk_2x 0x00000008 |
| #define BA_HDRX_OP_CTRL_dc_clk_2x 0x003C |
| #define B16HDRX_OP_CTRL_dc_clk_2x 0x003C |
| #define LSb32HDRX_OP_CTRL_dc_clk_2x 4 |
| #define LSb16HDRX_OP_CTRL_dc_clk_2x 4 |
| #define bHDRX_OP_CTRL_dc_clk_2x 1 |
| #define MSK32HDRX_OP_CTRL_dc_clk_2x 0x00000010 |
| #define RA_HDRX_DI_ACR_N 0x0040 |
| #define BA_HDRX_DI_ACR_N_n 0x0040 |
| #define B16HDRX_DI_ACR_N_n 0x0040 |
| #define LSb32HDRX_DI_ACR_N_n 0 |
| #define LSb16HDRX_DI_ACR_N_n 0 |
| #define bHDRX_DI_ACR_N_n 20 |
| #define MSK32HDRX_DI_ACR_N_n 0x000FFFFF |
| #define RA_HDRX_DI_ACR_CTS 0x0044 |
| #define BA_HDRX_DI_ACR_CTS_cts 0x0044 |
| #define B16HDRX_DI_ACR_CTS_cts 0x0044 |
| #define LSb32HDRX_DI_ACR_CTS_cts 0 |
| #define LSb16HDRX_DI_ACR_CTS_cts 0 |
| #define bHDRX_DI_ACR_CTS_cts 20 |
| #define MSK32HDRX_DI_ACR_CTS_cts 0x000FFFFF |
| #define RA_HDRX_DI_GCP 0x0048 |
| #define BA_HDRX_DI_GCP_set_avmute 0x0048 |
| #define B16HDRX_DI_GCP_set_avmute 0x0048 |
| #define LSb32HDRX_DI_GCP_set_avmute 0 |
| #define LSb16HDRX_DI_GCP_set_avmute 0 |
| #define bHDRX_DI_GCP_set_avmute 1 |
| #define MSK32HDRX_DI_GCP_set_avmute 0x00000001 |
| #define BA_HDRX_DI_GCP_clear_avmute 0x0048 |
| #define B16HDRX_DI_GCP_clear_avmute 0x0048 |
| #define LSb32HDRX_DI_GCP_clear_avmute 1 |
| #define LSb16HDRX_DI_GCP_clear_avmute 1 |
| #define bHDRX_DI_GCP_clear_avmute 1 |
| #define MSK32HDRX_DI_GCP_clear_avmute 0x00000002 |
| #define BA_HDRX_DI_GCP_cd 0x0048 |
| #define B16HDRX_DI_GCP_cd 0x0048 |
| #define LSb32HDRX_DI_GCP_cd 2 |
| #define LSb16HDRX_DI_GCP_cd 2 |
| #define bHDRX_DI_GCP_cd 4 |
| #define MSK32HDRX_DI_GCP_cd 0x0000003C |
| #define BA_HDRX_DI_GCP_pp 0x0048 |
| #define B16HDRX_DI_GCP_pp 0x0048 |
| #define LSb32HDRX_DI_GCP_pp 6 |
| #define LSb16HDRX_DI_GCP_pp 6 |
| #define bHDRX_DI_GCP_pp 4 |
| #define MSK32HDRX_DI_GCP_pp 0x000003C0 |
| #define BA_HDRX_DI_GCP_dp 0x0049 |
| #define B16HDRX_DI_GCP_dp 0x0048 |
| #define LSb32HDRX_DI_GCP_dp 10 |
| #define LSb16HDRX_DI_GCP_dp 10 |
| #define bHDRX_DI_GCP_dp 1 |
| #define MSK32HDRX_DI_GCP_dp 0x00000400 |
| #define RA_HDRX_DI_AVI_INFOFRAME 0x004C |
| #define BA_HDRX_DI_AVI_INFOFRAME_version 0x004C |
| #define B16HDRX_DI_AVI_INFOFRAME_version 0x004C |
| #define LSb32HDRX_DI_AVI_INFOFRAME_version 0 |
| #define LSb16HDRX_DI_AVI_INFOFRAME_version 0 |
| #define bHDRX_DI_AVI_INFOFRAME_version 8 |
| #define MSK32HDRX_DI_AVI_INFOFRAME_version 0x000000FF |
| #define BA_HDRX_DI_AVI_INFOFRAME_length 0x004D |
| #define B16HDRX_DI_AVI_INFOFRAME_length 0x004C |
| #define LSb32HDRX_DI_AVI_INFOFRAME_length 8 |
| #define LSb16HDRX_DI_AVI_INFOFRAME_length 8 |
| #define bHDRX_DI_AVI_INFOFRAME_length 8 |
| #define MSK32HDRX_DI_AVI_INFOFRAME_length 0x0000FF00 |
| #define BA_HDRX_DI_AVI_INFOFRAME_checksum 0x004E |
| #define B16HDRX_DI_AVI_INFOFRAME_checksum 0x004E |
| #define LSb32HDRX_DI_AVI_INFOFRAME_checksum 16 |
| #define LSb16HDRX_DI_AVI_INFOFRAME_checksum 0 |
| #define bHDRX_DI_AVI_INFOFRAME_checksum 8 |
| #define MSK32HDRX_DI_AVI_INFOFRAME_checksum 0x00FF0000 |
| #define RA_HDRX_DI_AVI_INFOFRAME1 0x0050 |
| #define BA_HDRX_DI_AVI_INFOFRAME_db_1_to_4 0x0050 |
| #define B16HDRX_DI_AVI_INFOFRAME_db_1_to_4 0x0050 |
| #define LSb32HDRX_DI_AVI_INFOFRAME_db_1_to_4 0 |
| #define LSb16HDRX_DI_AVI_INFOFRAME_db_1_to_4 0 |
| #define bHDRX_DI_AVI_INFOFRAME_db_1_to_4 32 |
| #define MSK32HDRX_DI_AVI_INFOFRAME_db_1_to_4 0xFFFFFFFF |
| #define RA_HDRX_DI_AVI_INFOFRAME2 0x0054 |
| #define BA_HDRX_DI_AVI_INFOFRAME_db_5_to_8 0x0054 |
| #define B16HDRX_DI_AVI_INFOFRAME_db_5_to_8 0x0054 |
| #define LSb32HDRX_DI_AVI_INFOFRAME_db_5_to_8 0 |
| #define LSb16HDRX_DI_AVI_INFOFRAME_db_5_to_8 0 |
| #define bHDRX_DI_AVI_INFOFRAME_db_5_to_8 32 |
| #define MSK32HDRX_DI_AVI_INFOFRAME_db_5_to_8 0xFFFFFFFF |
| #define RA_HDRX_DI_AVI_INFOFRAME3 0x0058 |
| #define BA_HDRX_DI_AVI_INFOFRAME_db_9_to_12 0x0058 |
| #define B16HDRX_DI_AVI_INFOFRAME_db_9_to_12 0x0058 |
| #define LSb32HDRX_DI_AVI_INFOFRAME_db_9_to_12 0 |
| #define LSb16HDRX_DI_AVI_INFOFRAME_db_9_to_12 0 |
| #define bHDRX_DI_AVI_INFOFRAME_db_9_to_12 32 |
| #define MSK32HDRX_DI_AVI_INFOFRAME_db_9_to_12 0xFFFFFFFF |
| #define RA_HDRX_DI_AVI_INFOFRAME4 0x005C |
| #define BA_HDRX_DI_AVI_INFOFRAME_db_13 0x005C |
| #define B16HDRX_DI_AVI_INFOFRAME_db_13 0x005C |
| #define LSb32HDRX_DI_AVI_INFOFRAME_db_13 0 |
| #define LSb16HDRX_DI_AVI_INFOFRAME_db_13 0 |
| #define bHDRX_DI_AVI_INFOFRAME_db_13 8 |
| #define MSK32HDRX_DI_AVI_INFOFRAME_db_13 0x000000FF |
| #define RA_HDRX_DI_SPD_INFOFRAME 0x0060 |
| #define BA_HDRX_DI_SPD_INFOFRAME_version 0x0060 |
| #define B16HDRX_DI_SPD_INFOFRAME_version 0x0060 |
| #define LSb32HDRX_DI_SPD_INFOFRAME_version 0 |
| #define LSb16HDRX_DI_SPD_INFOFRAME_version 0 |
| #define bHDRX_DI_SPD_INFOFRAME_version 8 |
| #define MSK32HDRX_DI_SPD_INFOFRAME_version 0x000000FF |
| #define BA_HDRX_DI_SPD_INFOFRAME_length 0x0061 |
| #define B16HDRX_DI_SPD_INFOFRAME_length 0x0060 |
| #define LSb32HDRX_DI_SPD_INFOFRAME_length 8 |
| #define LSb16HDRX_DI_SPD_INFOFRAME_length 8 |
| #define bHDRX_DI_SPD_INFOFRAME_length 8 |
| #define MSK32HDRX_DI_SPD_INFOFRAME_length 0x0000FF00 |
| #define BA_HDRX_DI_SPD_INFOFRAME_checksum 0x0062 |
| #define B16HDRX_DI_SPD_INFOFRAME_checksum 0x0062 |
| #define LSb32HDRX_DI_SPD_INFOFRAME_checksum 16 |
| #define LSb16HDRX_DI_SPD_INFOFRAME_checksum 0 |
| #define bHDRX_DI_SPD_INFOFRAME_checksum 8 |
| #define MSK32HDRX_DI_SPD_INFOFRAME_checksum 0x00FF0000 |
| #define RA_HDRX_DI_SPD_INFOFRAME1 0x0064 |
| #define BA_HDRX_DI_SPD_INFOFRAME_db_1_to_4 0x0064 |
| #define B16HDRX_DI_SPD_INFOFRAME_db_1_to_4 0x0064 |
| #define LSb32HDRX_DI_SPD_INFOFRAME_db_1_to_4 0 |
| #define LSb16HDRX_DI_SPD_INFOFRAME_db_1_to_4 0 |
| #define bHDRX_DI_SPD_INFOFRAME_db_1_to_4 32 |
| #define MSK32HDRX_DI_SPD_INFOFRAME_db_1_to_4 0xFFFFFFFF |
| #define RA_HDRX_DI_SPD_INFOFRAME2 0x0068 |
| #define BA_HDRX_DI_SPD_INFOFRAME_db_5_to_8 0x0068 |
| #define B16HDRX_DI_SPD_INFOFRAME_db_5_to_8 0x0068 |
| #define LSb32HDRX_DI_SPD_INFOFRAME_db_5_to_8 0 |
| #define LSb16HDRX_DI_SPD_INFOFRAME_db_5_to_8 0 |
| #define bHDRX_DI_SPD_INFOFRAME_db_5_to_8 32 |
| #define MSK32HDRX_DI_SPD_INFOFRAME_db_5_to_8 0xFFFFFFFF |
| #define RA_HDRX_DI_SPD_INFOFRAME3 0x006C |
| #define BA_HDRX_DI_SPD_INFOFRAME_db_9_to_12 0x006C |
| #define B16HDRX_DI_SPD_INFOFRAME_db_9_to_12 0x006C |
| #define LSb32HDRX_DI_SPD_INFOFRAME_db_9_to_12 0 |
| #define LSb16HDRX_DI_SPD_INFOFRAME_db_9_to_12 0 |
| #define bHDRX_DI_SPD_INFOFRAME_db_9_to_12 32 |
| #define MSK32HDRX_DI_SPD_INFOFRAME_db_9_to_12 0xFFFFFFFF |
| #define RA_HDRX_DI_SPD_INFOFRAME4 0x0070 |
| #define BA_HDRX_DI_SPD_INFOFRAME_db_13_to_16 0x0070 |
| #define B16HDRX_DI_SPD_INFOFRAME_db_13_to_16 0x0070 |
| #define LSb32HDRX_DI_SPD_INFOFRAME_db_13_to_16 0 |
| #define LSb16HDRX_DI_SPD_INFOFRAME_db_13_to_16 0 |
| #define bHDRX_DI_SPD_INFOFRAME_db_13_to_16 32 |
| #define MSK32HDRX_DI_SPD_INFOFRAME_db_13_to_16 0xFFFFFFFF |
| #define RA_HDRX_DI_SPD_INFOFRAME5 0x0074 |
| #define BA_HDRX_DI_SPD_INFOFRAME_db_17_to_20 0x0074 |
| #define B16HDRX_DI_SPD_INFOFRAME_db_17_to_20 0x0074 |
| #define LSb32HDRX_DI_SPD_INFOFRAME_db_17_to_20 0 |
| #define LSb16HDRX_DI_SPD_INFOFRAME_db_17_to_20 0 |
| #define bHDRX_DI_SPD_INFOFRAME_db_17_to_20 32 |
| #define MSK32HDRX_DI_SPD_INFOFRAME_db_17_to_20 0xFFFFFFFF |
| #define RA_HDRX_DI_SPD_INFOFRAME6 0x0078 |
| #define BA_HDRX_DI_SPD_INFOFRAME_db_21_to_24 0x0078 |
| #define B16HDRX_DI_SPD_INFOFRAME_db_21_to_24 0x0078 |
| #define LSb32HDRX_DI_SPD_INFOFRAME_db_21_to_24 0 |
| #define LSb16HDRX_DI_SPD_INFOFRAME_db_21_to_24 0 |
| #define bHDRX_DI_SPD_INFOFRAME_db_21_to_24 32 |
| #define MSK32HDRX_DI_SPD_INFOFRAME_db_21_to_24 0xFFFFFFFF |
| #define RA_HDRX_DI_SPD_INFOFRAME7 0x007C |
| #define BA_HDRX_DI_SPD_INFOFRAME_db_25 0x007C |
| #define B16HDRX_DI_SPD_INFOFRAME_db_25 0x007C |
| #define LSb32HDRX_DI_SPD_INFOFRAME_db_25 0 |
| #define LSb16HDRX_DI_SPD_INFOFRAME_db_25 0 |
| #define bHDRX_DI_SPD_INFOFRAME_db_25 8 |
| #define MSK32HDRX_DI_SPD_INFOFRAME_db_25 0x000000FF |
| #define RA_HDRX_DI_AUDIO_INFOFRAME 0x0080 |
| #define BA_HDRX_DI_AUDIO_INFOFRAME_version 0x0080 |
| #define B16HDRX_DI_AUDIO_INFOFRAME_version 0x0080 |
| #define LSb32HDRX_DI_AUDIO_INFOFRAME_version 0 |
| #define LSb16HDRX_DI_AUDIO_INFOFRAME_version 0 |
| #define bHDRX_DI_AUDIO_INFOFRAME_version 8 |
| #define MSK32HDRX_DI_AUDIO_INFOFRAME_version 0x000000FF |
| #define BA_HDRX_DI_AUDIO_INFOFRAME_length 0x0081 |
| #define B16HDRX_DI_AUDIO_INFOFRAME_length 0x0080 |
| #define LSb32HDRX_DI_AUDIO_INFOFRAME_length 8 |
| #define LSb16HDRX_DI_AUDIO_INFOFRAME_length 8 |
| #define bHDRX_DI_AUDIO_INFOFRAME_length 8 |
| #define MSK32HDRX_DI_AUDIO_INFOFRAME_length 0x0000FF00 |
| #define BA_HDRX_DI_AUDIO_INFOFRAME_checksum 0x0082 |
| #define B16HDRX_DI_AUDIO_INFOFRAME_checksum 0x0082 |
| #define LSb32HDRX_DI_AUDIO_INFOFRAME_checksum 16 |
| #define LSb16HDRX_DI_AUDIO_INFOFRAME_checksum 0 |
| #define bHDRX_DI_AUDIO_INFOFRAME_checksum 8 |
| #define MSK32HDRX_DI_AUDIO_INFOFRAME_checksum 0x00FF0000 |
| #define BA_HDRX_DI_AUDIO_INFOFRAME_db1 0x0083 |
| #define B16HDRX_DI_AUDIO_INFOFRAME_db1 0x0082 |
| #define LSb32HDRX_DI_AUDIO_INFOFRAME_db1 24 |
| #define LSb16HDRX_DI_AUDIO_INFOFRAME_db1 8 |
| #define bHDRX_DI_AUDIO_INFOFRAME_db1 8 |
| #define MSK32HDRX_DI_AUDIO_INFOFRAME_db1 0xFF000000 |
| #define RA_HDRX_DI_AUDIO_INFOFRAME1 0x0084 |
| #define BA_HDRX_DI_AUDIO_INFOFRAME_db2 0x0084 |
| #define B16HDRX_DI_AUDIO_INFOFRAME_db2 0x0084 |
| #define LSb32HDRX_DI_AUDIO_INFOFRAME_db2 0 |
| #define LSb16HDRX_DI_AUDIO_INFOFRAME_db2 0 |
| #define bHDRX_DI_AUDIO_INFOFRAME_db2 8 |
| #define MSK32HDRX_DI_AUDIO_INFOFRAME_db2 0x000000FF |
| #define BA_HDRX_DI_AUDIO_INFOFRAME_db3 0x0085 |
| #define B16HDRX_DI_AUDIO_INFOFRAME_db3 0x0084 |
| #define LSb32HDRX_DI_AUDIO_INFOFRAME_db3 8 |
| #define LSb16HDRX_DI_AUDIO_INFOFRAME_db3 8 |
| #define bHDRX_DI_AUDIO_INFOFRAME_db3 8 |
| #define MSK32HDRX_DI_AUDIO_INFOFRAME_db3 0x0000FF00 |
| #define BA_HDRX_DI_AUDIO_INFOFRAME_db4 0x0086 |
| #define B16HDRX_DI_AUDIO_INFOFRAME_db4 0x0086 |
| #define LSb32HDRX_DI_AUDIO_INFOFRAME_db4 16 |
| #define LSb16HDRX_DI_AUDIO_INFOFRAME_db4 0 |
| #define bHDRX_DI_AUDIO_INFOFRAME_db4 8 |
| #define MSK32HDRX_DI_AUDIO_INFOFRAME_db4 0x00FF0000 |
| #define BA_HDRX_DI_AUDIO_INFOFRAME_db5 0x0087 |
| #define B16HDRX_DI_AUDIO_INFOFRAME_db5 0x0086 |
| #define LSb32HDRX_DI_AUDIO_INFOFRAME_db5 24 |
| #define LSb16HDRX_DI_AUDIO_INFOFRAME_db5 8 |
| #define bHDRX_DI_AUDIO_INFOFRAME_db5 8 |
| #define MSK32HDRX_DI_AUDIO_INFOFRAME_db5 0xFF000000 |
| #define RA_HDRX_DI_MPEG_INFOFRAME 0x0088 |
| #define BA_HDRX_DI_MPEG_INFOFRAME_version 0x0088 |
| #define B16HDRX_DI_MPEG_INFOFRAME_version 0x0088 |
| #define LSb32HDRX_DI_MPEG_INFOFRAME_version 0 |
| #define LSb16HDRX_DI_MPEG_INFOFRAME_version 0 |
| #define bHDRX_DI_MPEG_INFOFRAME_version 8 |
| #define MSK32HDRX_DI_MPEG_INFOFRAME_version 0x000000FF |
| #define BA_HDRX_DI_MPEG_INFOFRAME_length 0x0089 |
| #define B16HDRX_DI_MPEG_INFOFRAME_length 0x0088 |
| #define LSb32HDRX_DI_MPEG_INFOFRAME_length 8 |
| #define LSb16HDRX_DI_MPEG_INFOFRAME_length 8 |
| #define bHDRX_DI_MPEG_INFOFRAME_length 8 |
| #define MSK32HDRX_DI_MPEG_INFOFRAME_length 0x0000FF00 |
| #define BA_HDRX_DI_MPEG_INFOFRAME_checksum 0x008A |
| #define B16HDRX_DI_MPEG_INFOFRAME_checksum 0x008A |
| #define LSb32HDRX_DI_MPEG_INFOFRAME_checksum 16 |
| #define LSb16HDRX_DI_MPEG_INFOFRAME_checksum 0 |
| #define bHDRX_DI_MPEG_INFOFRAME_checksum 8 |
| #define MSK32HDRX_DI_MPEG_INFOFRAME_checksum 0x00FF0000 |
| #define RA_HDRX_DI_MPEG_INFOFRAME1 0x008C |
| #define BA_HDRX_DI_MPEG_INFOFRAME_db_1_to_4 0x008C |
| #define B16HDRX_DI_MPEG_INFOFRAME_db_1_to_4 0x008C |
| #define LSb32HDRX_DI_MPEG_INFOFRAME_db_1_to_4 0 |
| #define LSb16HDRX_DI_MPEG_INFOFRAME_db_1_to_4 0 |
| #define bHDRX_DI_MPEG_INFOFRAME_db_1_to_4 32 |
| #define MSK32HDRX_DI_MPEG_INFOFRAME_db_1_to_4 0xFFFFFFFF |
| #define RA_HDRX_DI_MPEG_INFOFRAME2 0x0090 |
| #define BA_HDRX_DI_MPEG_INFOFRAME_db_5 0x0090 |
| #define B16HDRX_DI_MPEG_INFOFRAME_db_5 0x0090 |
| #define LSb32HDRX_DI_MPEG_INFOFRAME_db_5 0 |
| #define LSb16HDRX_DI_MPEG_INFOFRAME_db_5 0 |
| #define bHDRX_DI_MPEG_INFOFRAME_db_5 8 |
| #define MSK32HDRX_DI_MPEG_INFOFRAME_db_5 0x000000FF |
| #define RA_HDRX_DI_VEN_INFOFRAME 0x0094 |
| #define BA_HDRX_DI_VEN_INFOFRAME_version 0x0094 |
| #define B16HDRX_DI_VEN_INFOFRAME_version 0x0094 |
| #define LSb32HDRX_DI_VEN_INFOFRAME_version 0 |
| #define LSb16HDRX_DI_VEN_INFOFRAME_version 0 |
| #define bHDRX_DI_VEN_INFOFRAME_version 8 |
| #define MSK32HDRX_DI_VEN_INFOFRAME_version 0x000000FF |
| #define BA_HDRX_DI_VEN_INFOFRAME_length 0x0095 |
| #define B16HDRX_DI_VEN_INFOFRAME_length 0x0094 |
| #define LSb32HDRX_DI_VEN_INFOFRAME_length 8 |
| #define LSb16HDRX_DI_VEN_INFOFRAME_length 8 |
| #define bHDRX_DI_VEN_INFOFRAME_length 8 |
| #define MSK32HDRX_DI_VEN_INFOFRAME_length 0x0000FF00 |
| #define BA_HDRX_DI_VEN_INFOFRAME_checksum 0x0096 |
| #define B16HDRX_DI_VEN_INFOFRAME_checksum 0x0096 |
| #define LSb32HDRX_DI_VEN_INFOFRAME_checksum 16 |
| #define LSb16HDRX_DI_VEN_INFOFRAME_checksum 0 |
| #define bHDRX_DI_VEN_INFOFRAME_checksum 8 |
| #define MSK32HDRX_DI_VEN_INFOFRAME_checksum 0x00FF0000 |
| #define RA_HDRX_DI_VEN_INFOFRAME1 0x0098 |
| #define BA_HDRX_DI_VEN_INFOFRAME_db_1_to_4 0x0098 |
| #define B16HDRX_DI_VEN_INFOFRAME_db_1_to_4 0x0098 |
| #define LSb32HDRX_DI_VEN_INFOFRAME_db_1_to_4 0 |
| #define LSb16HDRX_DI_VEN_INFOFRAME_db_1_to_4 0 |
| #define bHDRX_DI_VEN_INFOFRAME_db_1_to_4 32 |
| #define MSK32HDRX_DI_VEN_INFOFRAME_db_1_to_4 0xFFFFFFFF |
| #define RA_HDRX_DI_VEN_INFOFRAME2 0x009C |
| #define BA_HDRX_DI_VEN_INFOFRAME_db_5_to_8 0x009C |
| #define B16HDRX_DI_VEN_INFOFRAME_db_5_to_8 0x009C |
| #define LSb32HDRX_DI_VEN_INFOFRAME_db_5_to_8 0 |
| #define LSb16HDRX_DI_VEN_INFOFRAME_db_5_to_8 0 |
| #define bHDRX_DI_VEN_INFOFRAME_db_5_to_8 32 |
| #define MSK32HDRX_DI_VEN_INFOFRAME_db_5_to_8 0xFFFFFFFF |
| #define RA_HDRX_DI_VEN_INFOFRAME3 0x00A0 |
| #define BA_HDRX_DI_VEN_INFOFRAME_db_9_to_12 0x00A0 |
| #define B16HDRX_DI_VEN_INFOFRAME_db_9_to_12 0x00A0 |
| #define LSb32HDRX_DI_VEN_INFOFRAME_db_9_to_12 0 |
| #define LSb16HDRX_DI_VEN_INFOFRAME_db_9_to_12 0 |
| #define bHDRX_DI_VEN_INFOFRAME_db_9_to_12 32 |
| #define MSK32HDRX_DI_VEN_INFOFRAME_db_9_to_12 0xFFFFFFFF |
| #define RA_HDRX_DI_VEN_INFOFRAME4 0x00A4 |
| #define BA_HDRX_DI_VEN_INFOFRAME_db_13_to_16 0x00A4 |
| #define B16HDRX_DI_VEN_INFOFRAME_db_13_to_16 0x00A4 |
| #define LSb32HDRX_DI_VEN_INFOFRAME_db_13_to_16 0 |
| #define LSb16HDRX_DI_VEN_INFOFRAME_db_13_to_16 0 |
| #define bHDRX_DI_VEN_INFOFRAME_db_13_to_16 32 |
| #define MSK32HDRX_DI_VEN_INFOFRAME_db_13_to_16 0xFFFFFFFF |
| #define RA_HDRX_DI_VEN_INFOFRAME5 0x00A8 |
| #define BA_HDRX_DI_VEN_INFOFRAME_db_17_to_20 0x00A8 |
| #define B16HDRX_DI_VEN_INFOFRAME_db_17_to_20 0x00A8 |
| #define LSb32HDRX_DI_VEN_INFOFRAME_db_17_to_20 0 |
| #define LSb16HDRX_DI_VEN_INFOFRAME_db_17_to_20 0 |
| #define bHDRX_DI_VEN_INFOFRAME_db_17_to_20 32 |
| #define MSK32HDRX_DI_VEN_INFOFRAME_db_17_to_20 0xFFFFFFFF |
| #define RA_HDRX_DI_VEN_INFOFRAME6 0x00AC |
| #define BA_HDRX_DI_VEN_INFOFRAME_db_21_to_24 0x00AC |
| #define B16HDRX_DI_VEN_INFOFRAME_db_21_to_24 0x00AC |
| #define LSb32HDRX_DI_VEN_INFOFRAME_db_21_to_24 0 |
| #define LSb16HDRX_DI_VEN_INFOFRAME_db_21_to_24 0 |
| #define bHDRX_DI_VEN_INFOFRAME_db_21_to_24 32 |
| #define MSK32HDRX_DI_VEN_INFOFRAME_db_21_to_24 0xFFFFFFFF |
| #define RA_HDRX_DI_VEN_INFOFRAME7 0x00B0 |
| #define BA_HDRX_DI_VEN_INFOFRAME_db_25_to_27 0x00B0 |
| #define B16HDRX_DI_VEN_INFOFRAME_db_25_to_27 0x00B0 |
| #define LSb32HDRX_DI_VEN_INFOFRAME_db_25_to_27 0 |
| #define LSb16HDRX_DI_VEN_INFOFRAME_db_25_to_27 0 |
| #define bHDRX_DI_VEN_INFOFRAME_db_25_to_27 24 |
| #define MSK32HDRX_DI_VEN_INFOFRAME_db_25_to_27 0x00FFFFFF |
| #define RA_HDRX_DI_DRM_INFO 0x00B4 |
| #define BA_HDRX_DI_DRM_INFO_version 0x00B4 |
| #define B16HDRX_DI_DRM_INFO_version 0x00B4 |
| #define LSb32HDRX_DI_DRM_INFO_version 0 |
| #define LSb16HDRX_DI_DRM_INFO_version 0 |
| #define bHDRX_DI_DRM_INFO_version 8 |
| #define MSK32HDRX_DI_DRM_INFO_version 0x000000FF |
| #define BA_HDRX_DI_DRM_INFO_length 0x00B5 |
| #define B16HDRX_DI_DRM_INFO_length 0x00B4 |
| #define LSb32HDRX_DI_DRM_INFO_length 8 |
| #define LSb16HDRX_DI_DRM_INFO_length 8 |
| #define bHDRX_DI_DRM_INFO_length 8 |
| #define MSK32HDRX_DI_DRM_INFO_length 0x0000FF00 |
| #define BA_HDRX_DI_DRM_INFO_checksum 0x00B6 |
| #define B16HDRX_DI_DRM_INFO_checksum 0x00B6 |
| #define LSb32HDRX_DI_DRM_INFO_checksum 16 |
| #define LSb16HDRX_DI_DRM_INFO_checksum 0 |
| #define bHDRX_DI_DRM_INFO_checksum 8 |
| #define MSK32HDRX_DI_DRM_INFO_checksum 0x00FF0000 |
| #define RA_HDRX_DI_DRM_INFO1 0x00B8 |
| #define BA_HDRX_DI_DRM_INFO_db_1_to_4 0x00B8 |
| #define B16HDRX_DI_DRM_INFO_db_1_to_4 0x00B8 |
| #define LSb32HDRX_DI_DRM_INFO_db_1_to_4 0 |
| #define LSb16HDRX_DI_DRM_INFO_db_1_to_4 0 |
| #define bHDRX_DI_DRM_INFO_db_1_to_4 32 |
| #define MSK32HDRX_DI_DRM_INFO_db_1_to_4 0xFFFFFFFF |
| #define RA_HDRX_DI_DRM_INFO2 0x00BC |
| #define BA_HDRX_DI_DRM_INFO_db_5_to_8 0x00BC |
| #define B16HDRX_DI_DRM_INFO_db_5_to_8 0x00BC |
| #define LSb32HDRX_DI_DRM_INFO_db_5_to_8 0 |
| #define LSb16HDRX_DI_DRM_INFO_db_5_to_8 0 |
| #define bHDRX_DI_DRM_INFO_db_5_to_8 32 |
| #define MSK32HDRX_DI_DRM_INFO_db_5_to_8 0xFFFFFFFF |
| #define RA_HDRX_DI_DRM_INFO3 0x00C0 |
| #define BA_HDRX_DI_DRM_INFO_db_9_to_12 0x00C0 |
| #define B16HDRX_DI_DRM_INFO_db_9_to_12 0x00C0 |
| #define LSb32HDRX_DI_DRM_INFO_db_9_to_12 0 |
| #define LSb16HDRX_DI_DRM_INFO_db_9_to_12 0 |
| #define bHDRX_DI_DRM_INFO_db_9_to_12 32 |
| #define MSK32HDRX_DI_DRM_INFO_db_9_to_12 0xFFFFFFFF |
| #define RA_HDRX_DI_DRM_INFO4 0x00C4 |
| #define BA_HDRX_DI_DRM_INFO_db_13_to_16 0x00C4 |
| #define B16HDRX_DI_DRM_INFO_db_13_to_16 0x00C4 |
| #define LSb32HDRX_DI_DRM_INFO_db_13_to_16 0 |
| #define LSb16HDRX_DI_DRM_INFO_db_13_to_16 0 |
| #define bHDRX_DI_DRM_INFO_db_13_to_16 32 |
| #define MSK32HDRX_DI_DRM_INFO_db_13_to_16 0xFFFFFFFF |
| #define RA_HDRX_DI_DRM_INFO5 0x00C8 |
| #define BA_HDRX_DI_DRM_INFO_db_17_to_20 0x00C8 |
| #define B16HDRX_DI_DRM_INFO_db_17_to_20 0x00C8 |
| #define LSb32HDRX_DI_DRM_INFO_db_17_to_20 0 |
| #define LSb16HDRX_DI_DRM_INFO_db_17_to_20 0 |
| #define bHDRX_DI_DRM_INFO_db_17_to_20 32 |
| #define MSK32HDRX_DI_DRM_INFO_db_17_to_20 0xFFFFFFFF |
| #define RA_HDRX_DI_DRM_INFO6 0x00CC |
| #define BA_HDRX_DI_DRM_INFO_db_21_to_24 0x00CC |
| #define B16HDRX_DI_DRM_INFO_db_21_to_24 0x00CC |
| #define LSb32HDRX_DI_DRM_INFO_db_21_to_24 0 |
| #define LSb16HDRX_DI_DRM_INFO_db_21_to_24 0 |
| #define bHDRX_DI_DRM_INFO_db_21_to_24 32 |
| #define MSK32HDRX_DI_DRM_INFO_db_21_to_24 0xFFFFFFFF |
| #define RA_HDRX_DI_DRM_INFO7 0x00D0 |
| #define BA_HDRX_DI_DRM_INFO_db_25_to_27 0x00D0 |
| #define B16HDRX_DI_DRM_INFO_db_25_to_27 0x00D0 |
| #define LSb32HDRX_DI_DRM_INFO_db_25_to_27 0 |
| #define LSb16HDRX_DI_DRM_INFO_db_25_to_27 0 |
| #define bHDRX_DI_DRM_INFO_db_25_to_27 24 |
| #define MSK32HDRX_DI_DRM_INFO_db_25_to_27 0x00FFFFFF |
| #define RA_HDRX_DI_GMD_PKT 0x00D4 |
| #define BA_HDRX_DI_GMD_PKT_hb_1_to_2 0x00D4 |
| #define B16HDRX_DI_GMD_PKT_hb_1_to_2 0x00D4 |
| #define LSb32HDRX_DI_GMD_PKT_hb_1_to_2 0 |
| #define LSb16HDRX_DI_GMD_PKT_hb_1_to_2 0 |
| #define bHDRX_DI_GMD_PKT_hb_1_to_2 16 |
| #define MSK32HDRX_DI_GMD_PKT_hb_1_to_2 0x0000FFFF |
| #define RA_HDRX_DI_GMD_PKT1 0x00D8 |
| #define BA_HDRX_DI_GMD_PKT_pb_0_to_3 0x00D8 |
| #define B16HDRX_DI_GMD_PKT_pb_0_to_3 0x00D8 |
| #define LSb32HDRX_DI_GMD_PKT_pb_0_to_3 0 |
| #define LSb16HDRX_DI_GMD_PKT_pb_0_to_3 0 |
| #define bHDRX_DI_GMD_PKT_pb_0_to_3 32 |
| #define MSK32HDRX_DI_GMD_PKT_pb_0_to_3 0xFFFFFFFF |
| #define RA_HDRX_DI_GMD_PKT2 0x00DC |
| #define BA_HDRX_DI_GMD_PKT_pb_4_to_7 0x00DC |
| #define B16HDRX_DI_GMD_PKT_pb_4_to_7 0x00DC |
| #define LSb32HDRX_DI_GMD_PKT_pb_4_to_7 0 |
| #define LSb16HDRX_DI_GMD_PKT_pb_4_to_7 0 |
| #define bHDRX_DI_GMD_PKT_pb_4_to_7 32 |
| #define MSK32HDRX_DI_GMD_PKT_pb_4_to_7 0xFFFFFFFF |
| #define RA_HDRX_DI_GMD_PKT3 0x00E0 |
| #define BA_HDRX_DI_GMD_PKT_pb_8_to_11 0x00E0 |
| #define B16HDRX_DI_GMD_PKT_pb_8_to_11 0x00E0 |
| #define LSb32HDRX_DI_GMD_PKT_pb_8_to_11 0 |
| #define LSb16HDRX_DI_GMD_PKT_pb_8_to_11 0 |
| #define bHDRX_DI_GMD_PKT_pb_8_to_11 32 |
| #define MSK32HDRX_DI_GMD_PKT_pb_8_to_11 0xFFFFFFFF |
| #define RA_HDRX_DI_GMD_PKT4 0x00E4 |
| #define BA_HDRX_DI_GMD_PKT_pb_12_to_15 0x00E4 |
| #define B16HDRX_DI_GMD_PKT_pb_12_to_15 0x00E4 |
| #define LSb32HDRX_DI_GMD_PKT_pb_12_to_15 0 |
| #define LSb16HDRX_DI_GMD_PKT_pb_12_to_15 0 |
| #define bHDRX_DI_GMD_PKT_pb_12_to_15 32 |
| #define MSK32HDRX_DI_GMD_PKT_pb_12_to_15 0xFFFFFFFF |
| #define RA_HDRX_DI_GMD_PKT5 0x00E8 |
| #define BA_HDRX_DI_GMD_PKT_pb_16_to_19 0x00E8 |
| #define B16HDRX_DI_GMD_PKT_pb_16_to_19 0x00E8 |
| #define LSb32HDRX_DI_GMD_PKT_pb_16_to_19 0 |
| #define LSb16HDRX_DI_GMD_PKT_pb_16_to_19 0 |
| #define bHDRX_DI_GMD_PKT_pb_16_to_19 32 |
| #define MSK32HDRX_DI_GMD_PKT_pb_16_to_19 0xFFFFFFFF |
| #define RA_HDRX_DI_GMD_PKT6 0x00EC |
| #define BA_HDRX_DI_GMD_PKT_pb_20_to_23 0x00EC |
| #define B16HDRX_DI_GMD_PKT_pb_20_to_23 0x00EC |
| #define LSb32HDRX_DI_GMD_PKT_pb_20_to_23 0 |
| #define LSb16HDRX_DI_GMD_PKT_pb_20_to_23 0 |
| #define bHDRX_DI_GMD_PKT_pb_20_to_23 32 |
| #define MSK32HDRX_DI_GMD_PKT_pb_20_to_23 0xFFFFFFFF |
| #define RA_HDRX_DI_GMD_PKT7 0x00F0 |
| #define BA_HDRX_DI_GMD_PKT_pb_24_to_27 0x00F0 |
| #define B16HDRX_DI_GMD_PKT_pb_24_to_27 0x00F0 |
| #define LSb32HDRX_DI_GMD_PKT_pb_24_to_27 0 |
| #define LSb16HDRX_DI_GMD_PKT_pb_24_to_27 0 |
| #define bHDRX_DI_GMD_PKT_pb_24_to_27 32 |
| #define MSK32HDRX_DI_GMD_PKT_pb_24_to_27 0xFFFFFFFF |
| #define RA_HDRX_DI_GMD_PKT8 0x00F4 |
| #define BA_HDRX_DI_GMD_PKT_pb_28 0x00F4 |
| #define B16HDRX_DI_GMD_PKT_pb_28 0x00F4 |
| #define LSb32HDRX_DI_GMD_PKT_pb_28 0 |
| #define LSb16HDRX_DI_GMD_PKT_pb_28 0 |
| #define bHDRX_DI_GMD_PKT_pb_28 8 |
| #define MSK32HDRX_DI_GMD_PKT_pb_28 0x000000FF |
| #define RA_HDRX_DI_AMD_PKT 0x00F8 |
| #define BA_HDRX_DI_AMD_PKT_hb_0_to_2 0x00F8 |
| #define B16HDRX_DI_AMD_PKT_hb_0_to_2 0x00F8 |
| #define LSb32HDRX_DI_AMD_PKT_hb_0_to_2 0 |
| #define LSb16HDRX_DI_AMD_PKT_hb_0_to_2 0 |
| #define bHDRX_DI_AMD_PKT_hb_0_to_2 24 |
| #define MSK32HDRX_DI_AMD_PKT_hb_0_to_2 0x00FFFFFF |
| #define RA_HDRX_DI_AMD_PKT1 0x00FC |
| #define BA_HDRX_DI_AMD_PKT_pb_0_to_3 0x00FC |
| #define B16HDRX_DI_AMD_PKT_pb_0_to_3 0x00FC |
| #define LSb32HDRX_DI_AMD_PKT_pb_0_to_3 0 |
| #define LSb16HDRX_DI_AMD_PKT_pb_0_to_3 0 |
| #define bHDRX_DI_AMD_PKT_pb_0_to_3 32 |
| #define MSK32HDRX_DI_AMD_PKT_pb_0_to_3 0xFFFFFFFF |
| #define RA_HDRX_DI_AMD_PKT2 0x0100 |
| #define BA_HDRX_DI_AMD_PKT_pb_4_to_7 0x0100 |
| #define B16HDRX_DI_AMD_PKT_pb_4_to_7 0x0100 |
| #define LSb32HDRX_DI_AMD_PKT_pb_4_to_7 0 |
| #define LSb16HDRX_DI_AMD_PKT_pb_4_to_7 0 |
| #define bHDRX_DI_AMD_PKT_pb_4_to_7 32 |
| #define MSK32HDRX_DI_AMD_PKT_pb_4_to_7 0xFFFFFFFF |
| #define RA_HDRX_DI_AMD_PKT3 0x0104 |
| #define BA_HDRX_DI_AMD_PKT_pb_8_to_11 0x0104 |
| #define B16HDRX_DI_AMD_PKT_pb_8_to_11 0x0104 |
| #define LSb32HDRX_DI_AMD_PKT_pb_8_to_11 0 |
| #define LSb16HDRX_DI_AMD_PKT_pb_8_to_11 0 |
| #define bHDRX_DI_AMD_PKT_pb_8_to_11 32 |
| #define MSK32HDRX_DI_AMD_PKT_pb_8_to_11 0xFFFFFFFF |
| #define RA_HDRX_DI_AMD_PKT4 0x0108 |
| #define BA_HDRX_DI_AMD_PKT_pb_12_to_15 0x0108 |
| #define B16HDRX_DI_AMD_PKT_pb_12_to_15 0x0108 |
| #define LSb32HDRX_DI_AMD_PKT_pb_12_to_15 0 |
| #define LSb16HDRX_DI_AMD_PKT_pb_12_to_15 0 |
| #define bHDRX_DI_AMD_PKT_pb_12_to_15 32 |
| #define MSK32HDRX_DI_AMD_PKT_pb_12_to_15 0xFFFFFFFF |
| #define RA_HDRX_DI_AMD_PKT5 0x010C |
| #define BA_HDRX_DI_AMD_PKT_pb_16_to_19 0x010C |
| #define B16HDRX_DI_AMD_PKT_pb_16_to_19 0x010C |
| #define LSb32HDRX_DI_AMD_PKT_pb_16_to_19 0 |
| #define LSb16HDRX_DI_AMD_PKT_pb_16_to_19 0 |
| #define bHDRX_DI_AMD_PKT_pb_16_to_19 32 |
| #define MSK32HDRX_DI_AMD_PKT_pb_16_to_19 0xFFFFFFFF |
| #define RA_HDRX_DI_ACP 0x0110 |
| #define BA_HDRX_DI_ACP_hb_1_to_2 0x0110 |
| #define B16HDRX_DI_ACP_hb_1_to_2 0x0110 |
| #define LSb32HDRX_DI_ACP_hb_1_to_2 0 |
| #define LSb16HDRX_DI_ACP_hb_1_to_2 0 |
| #define bHDRX_DI_ACP_hb_1_to_2 16 |
| #define MSK32HDRX_DI_ACP_hb_1_to_2 0x0000FFFF |
| #define RA_HDRX_DI_ACP1 0x0114 |
| #define BA_HDRX_DI_ACP_pb_0_to_3 0x0114 |
| #define B16HDRX_DI_ACP_pb_0_to_3 0x0114 |
| #define LSb32HDRX_DI_ACP_pb_0_to_3 0 |
| #define LSb16HDRX_DI_ACP_pb_0_to_3 0 |
| #define bHDRX_DI_ACP_pb_0_to_3 32 |
| #define MSK32HDRX_DI_ACP_pb_0_to_3 0xFFFFFFFF |
| #define RA_HDRX_DI_ACP2 0x0118 |
| #define BA_HDRX_DI_ACP_pb_4_to_7 0x0118 |
| #define B16HDRX_DI_ACP_pb_4_to_7 0x0118 |
| #define LSb32HDRX_DI_ACP_pb_4_to_7 0 |
| #define LSb16HDRX_DI_ACP_pb_4_to_7 0 |
| #define bHDRX_DI_ACP_pb_4_to_7 32 |
| #define MSK32HDRX_DI_ACP_pb_4_to_7 0xFFFFFFFF |
| #define RA_HDRX_DI_ACP3 0x011C |
| #define BA_HDRX_DI_ACP_pb_8_to_11 0x011C |
| #define B16HDRX_DI_ACP_pb_8_to_11 0x011C |
| #define LSb32HDRX_DI_ACP_pb_8_to_11 0 |
| #define LSb16HDRX_DI_ACP_pb_8_to_11 0 |
| #define bHDRX_DI_ACP_pb_8_to_11 32 |
| #define MSK32HDRX_DI_ACP_pb_8_to_11 0xFFFFFFFF |
| #define RA_HDRX_DI_ACP4 0x0120 |
| #define BA_HDRX_DI_ACP_pb_12_to_15 0x0120 |
| #define B16HDRX_DI_ACP_pb_12_to_15 0x0120 |
| #define LSb32HDRX_DI_ACP_pb_12_to_15 0 |
| #define LSb16HDRX_DI_ACP_pb_12_to_15 0 |
| #define bHDRX_DI_ACP_pb_12_to_15 32 |
| #define MSK32HDRX_DI_ACP_pb_12_to_15 0xFFFFFFFF |
| #define RA_HDRX_DI_ACP5 0x0124 |
| #define BA_HDRX_DI_ACP_pb_16_to_19 0x0124 |
| #define B16HDRX_DI_ACP_pb_16_to_19 0x0124 |
| #define LSb32HDRX_DI_ACP_pb_16_to_19 0 |
| #define LSb16HDRX_DI_ACP_pb_16_to_19 0 |
| #define bHDRX_DI_ACP_pb_16_to_19 32 |
| #define MSK32HDRX_DI_ACP_pb_16_to_19 0xFFFFFFFF |
| #define RA_HDRX_DI_ACP6 0x0128 |
| #define BA_HDRX_DI_ACP_pb_20_to_23 0x0128 |
| #define B16HDRX_DI_ACP_pb_20_to_23 0x0128 |
| #define LSb32HDRX_DI_ACP_pb_20_to_23 0 |
| #define LSb16HDRX_DI_ACP_pb_20_to_23 0 |
| #define bHDRX_DI_ACP_pb_20_to_23 32 |
| #define MSK32HDRX_DI_ACP_pb_20_to_23 0xFFFFFFFF |
| #define RA_HDRX_DI_ACP7 0x012C |
| #define BA_HDRX_DI_ACP_pb_24_to_27 0x012C |
| #define B16HDRX_DI_ACP_pb_24_to_27 0x012C |
| #define LSb32HDRX_DI_ACP_pb_24_to_27 0 |
| #define LSb16HDRX_DI_ACP_pb_24_to_27 0 |
| #define bHDRX_DI_ACP_pb_24_to_27 32 |
| #define MSK32HDRX_DI_ACP_pb_24_to_27 0xFFFFFFFF |
| #define RA_HDRX_DI_ISRC1 0x0130 |
| #define BA_HDRX_DI_ISRC1_hb_1_to_2 0x0130 |
| #define B16HDRX_DI_ISRC1_hb_1_to_2 0x0130 |
| #define LSb32HDRX_DI_ISRC1_hb_1_to_2 0 |
| #define LSb16HDRX_DI_ISRC1_hb_1_to_2 0 |
| #define bHDRX_DI_ISRC1_hb_1_to_2 16 |
| #define MSK32HDRX_DI_ISRC1_hb_1_to_2 0x0000FFFF |
| #define RA_HDRX_DI_ISRC11 0x0134 |
| #define BA_HDRX_DI_ISRC1_pb_0_to_3 0x0134 |
| #define B16HDRX_DI_ISRC1_pb_0_to_3 0x0134 |
| #define LSb32HDRX_DI_ISRC1_pb_0_to_3 0 |
| #define LSb16HDRX_DI_ISRC1_pb_0_to_3 0 |
| #define bHDRX_DI_ISRC1_pb_0_to_3 32 |
| #define MSK32HDRX_DI_ISRC1_pb_0_to_3 0xFFFFFFFF |
| #define RA_HDRX_DI_ISRC12 0x0138 |
| #define BA_HDRX_DI_ISRC1_pb_4_to_7 0x0138 |
| #define B16HDRX_DI_ISRC1_pb_4_to_7 0x0138 |
| #define LSb32HDRX_DI_ISRC1_pb_4_to_7 0 |
| #define LSb16HDRX_DI_ISRC1_pb_4_to_7 0 |
| #define bHDRX_DI_ISRC1_pb_4_to_7 32 |
| #define MSK32HDRX_DI_ISRC1_pb_4_to_7 0xFFFFFFFF |
| #define RA_HDRX_DI_ISRC13 0x013C |
| #define BA_HDRX_DI_ISRC1_pb_8_to_11 0x013C |
| #define B16HDRX_DI_ISRC1_pb_8_to_11 0x013C |
| #define LSb32HDRX_DI_ISRC1_pb_8_to_11 0 |
| #define LSb16HDRX_DI_ISRC1_pb_8_to_11 0 |
| #define bHDRX_DI_ISRC1_pb_8_to_11 32 |
| #define MSK32HDRX_DI_ISRC1_pb_8_to_11 0xFFFFFFFF |
| #define RA_HDRX_DI_ISRC14 0x0140 |
| #define BA_HDRX_DI_ISRC1_pb_12_to_15 0x0140 |
| #define B16HDRX_DI_ISRC1_pb_12_to_15 0x0140 |
| #define LSb32HDRX_DI_ISRC1_pb_12_to_15 0 |
| #define LSb16HDRX_DI_ISRC1_pb_12_to_15 0 |
| #define bHDRX_DI_ISRC1_pb_12_to_15 32 |
| #define MSK32HDRX_DI_ISRC1_pb_12_to_15 0xFFFFFFFF |
| #define RA_HDRX_DI_ISRC2 0x0144 |
| #define BA_HDRX_DI_ISRC2_pb_0_to_3 0x0144 |
| #define B16HDRX_DI_ISRC2_pb_0_to_3 0x0144 |
| #define LSb32HDRX_DI_ISRC2_pb_0_to_3 0 |
| #define LSb16HDRX_DI_ISRC2_pb_0_to_3 0 |
| #define bHDRX_DI_ISRC2_pb_0_to_3 32 |
| #define MSK32HDRX_DI_ISRC2_pb_0_to_3 0xFFFFFFFF |
| #define RA_HDRX_DI_ISRC21 0x0148 |
| #define BA_HDRX_DI_ISRC2_pb_4_to_7 0x0148 |
| #define B16HDRX_DI_ISRC2_pb_4_to_7 0x0148 |
| #define LSb32HDRX_DI_ISRC2_pb_4_to_7 0 |
| #define LSb16HDRX_DI_ISRC2_pb_4_to_7 0 |
| #define bHDRX_DI_ISRC2_pb_4_to_7 32 |
| #define MSK32HDRX_DI_ISRC2_pb_4_to_7 0xFFFFFFFF |
| #define RA_HDRX_DI_ISRC22 0x014C |
| #define BA_HDRX_DI_ISRC2_pb_8_to_11 0x014C |
| #define B16HDRX_DI_ISRC2_pb_8_to_11 0x014C |
| #define LSb32HDRX_DI_ISRC2_pb_8_to_11 0 |
| #define LSb16HDRX_DI_ISRC2_pb_8_to_11 0 |
| #define bHDRX_DI_ISRC2_pb_8_to_11 32 |
| #define MSK32HDRX_DI_ISRC2_pb_8_to_11 0xFFFFFFFF |
| #define RA_HDRX_DI_ISRC23 0x0150 |
| #define BA_HDRX_DI_ISRC2_pb_12_to_15 0x0150 |
| #define B16HDRX_DI_ISRC2_pb_12_to_15 0x0150 |
| #define LSb32HDRX_DI_ISRC2_pb_12_to_15 0 |
| #define LSb16HDRX_DI_ISRC2_pb_12_to_15 0 |
| #define bHDRX_DI_ISRC2_pb_12_to_15 32 |
| #define MSK32HDRX_DI_ISRC2_pb_12_to_15 0xFFFFFFFF |
| #define RA_HDRX_DI_NULL_CNT 0x0154 |
| #define BA_HDRX_DI_NULL_CNT_null_cnt 0x0154 |
| #define B16HDRX_DI_NULL_CNT_null_cnt 0x0154 |
| #define LSb32HDRX_DI_NULL_CNT_null_cnt 0 |
| #define LSb16HDRX_DI_NULL_CNT_null_cnt 0 |
| #define bHDRX_DI_NULL_CNT_null_cnt 16 |
| #define MSK32HDRX_DI_NULL_CNT_null_cnt 0x0000FFFF |
| #define RA_HDRX_DI_ACR_CNT 0x0158 |
| #define BA_HDRX_DI_ACR_CNT_acr_cnt 0x0158 |
| #define B16HDRX_DI_ACR_CNT_acr_cnt 0x0158 |
| #define LSb32HDRX_DI_ACR_CNT_acr_cnt 0 |
| #define LSb16HDRX_DI_ACR_CNT_acr_cnt 0 |
| #define bHDRX_DI_ACR_CNT_acr_cnt 16 |
| #define MSK32HDRX_DI_ACR_CNT_acr_cnt 0x0000FFFF |
| #define RA_HDRX_DI_GCP_CNT 0x015C |
| #define BA_HDRX_DI_GCP_CNT_gcp_cnt 0x015C |
| #define B16HDRX_DI_GCP_CNT_gcp_cnt 0x015C |
| #define LSb32HDRX_DI_GCP_CNT_gcp_cnt 0 |
| #define LSb16HDRX_DI_GCP_CNT_gcp_cnt 0 |
| #define bHDRX_DI_GCP_CNT_gcp_cnt 16 |
| #define MSK32HDRX_DI_GCP_CNT_gcp_cnt 0x0000FFFF |
| #define RA_HDRX_DI_ACP_CNT 0x0160 |
| #define BA_HDRX_DI_ACP_CNT_acp_cnt 0x0160 |
| #define B16HDRX_DI_ACP_CNT_acp_cnt 0x0160 |
| #define LSb32HDRX_DI_ACP_CNT_acp_cnt 0 |
| #define LSb16HDRX_DI_ACP_CNT_acp_cnt 0 |
| #define bHDRX_DI_ACP_CNT_acp_cnt 16 |
| #define MSK32HDRX_DI_ACP_CNT_acp_cnt 0x0000FFFF |
| #define RA_HDRX_DI_ISRC1_CNT 0x0164 |
| #define BA_HDRX_DI_ISRC1_CNT_isrc1_cnt 0x0164 |
| #define B16HDRX_DI_ISRC1_CNT_isrc1_cnt 0x0164 |
| #define LSb32HDRX_DI_ISRC1_CNT_isrc1_cnt 0 |
| #define LSb16HDRX_DI_ISRC1_CNT_isrc1_cnt 0 |
| #define bHDRX_DI_ISRC1_CNT_isrc1_cnt 16 |
| #define MSK32HDRX_DI_ISRC1_CNT_isrc1_cnt 0x0000FFFF |
| #define RA_HDRX_DI_ISRC2_CNT 0x0168 |
| #define BA_HDRX_DI_ISRC2_CNT_isrc2_cnt 0x0168 |
| #define B16HDRX_DI_ISRC2_CNT_isrc2_cnt 0x0168 |
| #define LSb32HDRX_DI_ISRC2_CNT_isrc2_cnt 0 |
| #define LSb16HDRX_DI_ISRC2_CNT_isrc2_cnt 0 |
| #define bHDRX_DI_ISRC2_CNT_isrc2_cnt 16 |
| #define MSK32HDRX_DI_ISRC2_CNT_isrc2_cnt 0x0000FFFF |
| #define RA_HDRX_DI_VEN_INFO_CNT 0x016C |
| #define BA_HDRX_DI_VEN_INFO_CNT_ven_info_cnt 0x016C |
| #define B16HDRX_DI_VEN_INFO_CNT_ven_info_cnt 0x016C |
| #define LSb32HDRX_DI_VEN_INFO_CNT_ven_info_cnt 0 |
| #define LSb16HDRX_DI_VEN_INFO_CNT_ven_info_cnt 0 |
| #define bHDRX_DI_VEN_INFO_CNT_ven_info_cnt 16 |
| #define MSK32HDRX_DI_VEN_INFO_CNT_ven_info_cnt 0x0000FFFF |
| #define RA_HDRX_DI_AVI_PKT_CNT 0x0170 |
| #define BA_HDRX_DI_AVI_PKT_CNT_avi_pkt_cnt 0x0170 |
| #define B16HDRX_DI_AVI_PKT_CNT_avi_pkt_cnt 0x0170 |
| #define LSb32HDRX_DI_AVI_PKT_CNT_avi_pkt_cnt 0 |
| #define LSb16HDRX_DI_AVI_PKT_CNT_avi_pkt_cnt 0 |
| #define bHDRX_DI_AVI_PKT_CNT_avi_pkt_cnt 16 |
| #define MSK32HDRX_DI_AVI_PKT_CNT_avi_pkt_cnt 0x0000FFFF |
| #define RA_HDRX_DI_SPD_PKT_CNT 0x0174 |
| #define BA_HDRX_DI_SPD_PKT_CNT_spd_pkt_cnt 0x0174 |
| #define B16HDRX_DI_SPD_PKT_CNT_spd_pkt_cnt 0x0174 |
| #define LSb32HDRX_DI_SPD_PKT_CNT_spd_pkt_cnt 0 |
| #define LSb16HDRX_DI_SPD_PKT_CNT_spd_pkt_cnt 0 |
| #define bHDRX_DI_SPD_PKT_CNT_spd_pkt_cnt 16 |
| #define MSK32HDRX_DI_SPD_PKT_CNT_spd_pkt_cnt 0x0000FFFF |
| #define RA_HDRX_DI_AUD_INFO_PKT_CNT 0x0178 |
| #define BA_HDRX_DI_AUD_INFO_PKT_CNT_aud_info_pkt_cnt 0x0178 |
| #define B16HDRX_DI_AUD_INFO_PKT_CNT_aud_info_pkt_cnt 0x0178 |
| #define LSb32HDRX_DI_AUD_INFO_PKT_CNT_aud_info_pkt_cnt 0 |
| #define LSb16HDRX_DI_AUD_INFO_PKT_CNT_aud_info_pkt_cnt 0 |
| #define bHDRX_DI_AUD_INFO_PKT_CNT_aud_info_pkt_cnt 16 |
| #define MSK32HDRX_DI_AUD_INFO_PKT_CNT_aud_info_pkt_cnt 0x0000FFFF |
| #define RA_HDRX_DI_MPEG_INFO_PKT_CNT 0x017C |
| #define BA_HDRX_DI_MPEG_INFO_PKT_CNT_mpeg_pkt_cnt 0x017C |
| #define B16HDRX_DI_MPEG_INFO_PKT_CNT_mpeg_pkt_cnt 0x017C |
| #define LSb32HDRX_DI_MPEG_INFO_PKT_CNT_mpeg_pkt_cnt 0 |
| #define LSb16HDRX_DI_MPEG_INFO_PKT_CNT_mpeg_pkt_cnt 0 |
| #define bHDRX_DI_MPEG_INFO_PKT_CNT_mpeg_pkt_cnt 16 |
| #define MSK32HDRX_DI_MPEG_INFO_PKT_CNT_mpeg_pkt_cnt 0x0000FFFF |
| #define RA_HDRX_DI_GMD_PKT_CNT 0x0180 |
| #define BA_HDRX_DI_GMD_PKT_CNT_gmd_pkt_cnt 0x0180 |
| #define B16HDRX_DI_GMD_PKT_CNT_gmd_pkt_cnt 0x0180 |
| #define LSb32HDRX_DI_GMD_PKT_CNT_gmd_pkt_cnt 0 |
| #define LSb16HDRX_DI_GMD_PKT_CNT_gmd_pkt_cnt 0 |
| #define bHDRX_DI_GMD_PKT_CNT_gmd_pkt_cnt 16 |
| #define MSK32HDRX_DI_GMD_PKT_CNT_gmd_pkt_cnt 0x0000FFFF |
| #define RA_HDRX_DI_AMD_PKT_CNT 0x0184 |
| #define BA_HDRX_DI_AMD_PKT_CNT_amd_pkt_cnt 0x0184 |
| #define B16HDRX_DI_AMD_PKT_CNT_amd_pkt_cnt 0x0184 |
| #define LSb32HDRX_DI_AMD_PKT_CNT_amd_pkt_cnt 0 |
| #define LSb16HDRX_DI_AMD_PKT_CNT_amd_pkt_cnt 0 |
| #define bHDRX_DI_AMD_PKT_CNT_amd_pkt_cnt 16 |
| #define MSK32HDRX_DI_AMD_PKT_CNT_amd_pkt_cnt 0x0000FFFF |
| #define RA_HDRX_DI_DRM_INFO_CNT 0x0188 |
| #define BA_HDRX_DI_DRM_INFO_CNT_cnt 0x0188 |
| #define B16HDRX_DI_DRM_INFO_CNT_cnt 0x0188 |
| #define LSb32HDRX_DI_DRM_INFO_CNT_cnt 0 |
| #define LSb16HDRX_DI_DRM_INFO_CNT_cnt 0 |
| #define bHDRX_DI_DRM_INFO_CNT_cnt 16 |
| #define MSK32HDRX_DI_DRM_INFO_CNT_cnt 0x0000FFFF |
| #define RA_HDRX_DI_ECC_SGL_ERR_CNT 0x018C |
| #define BA_HDRX_DI_ECC_SGL_ERR_CNT_sgl_err_pkt_cnt 0x018C |
| #define B16HDRX_DI_ECC_SGL_ERR_CNT_sgl_err_pkt_cnt 0x018C |
| #define LSb32HDRX_DI_ECC_SGL_ERR_CNT_sgl_err_pkt_cnt 0 |
| #define LSb16HDRX_DI_ECC_SGL_ERR_CNT_sgl_err_pkt_cnt 0 |
| #define bHDRX_DI_ECC_SGL_ERR_CNT_sgl_err_pkt_cnt 16 |
| #define MSK32HDRX_DI_ECC_SGL_ERR_CNT_sgl_err_pkt_cnt 0x0000FFFF |
| #define RA_HDRX_DI_ECC_MUL_ERR_CNT 0x0190 |
| #define BA_HDRX_DI_ECC_MUL_ERR_CNT_mul_err_pkt_cnt 0x0190 |
| #define B16HDRX_DI_ECC_MUL_ERR_CNT_mul_err_pkt_cnt 0x0190 |
| #define LSb32HDRX_DI_ECC_MUL_ERR_CNT_mul_err_pkt_cnt 0 |
| #define LSb16HDRX_DI_ECC_MUL_ERR_CNT_mul_err_pkt_cnt 0 |
| #define bHDRX_DI_ECC_MUL_ERR_CNT_mul_err_pkt_cnt 16 |
| #define MSK32HDRX_DI_ECC_MUL_ERR_CNT_mul_err_pkt_cnt 0x0000FFFF |
| #define RA_HDRX_PKT_CLR 0x0194 |
| #define BA_HDRX_PKT_CLR_ven_spec_clr 0x0194 |
| #define B16HDRX_PKT_CLR_ven_spec_clr 0x0194 |
| #define LSb32HDRX_PKT_CLR_ven_spec_clr 0 |
| #define LSb16HDRX_PKT_CLR_ven_spec_clr 0 |
| #define bHDRX_PKT_CLR_ven_spec_clr 1 |
| #define MSK32HDRX_PKT_CLR_ven_spec_clr 0x00000001 |
| #define BA_HDRX_PKT_CLR_avi_clr 0x0194 |
| #define B16HDRX_PKT_CLR_avi_clr 0x0194 |
| #define LSb32HDRX_PKT_CLR_avi_clr 1 |
| #define LSb16HDRX_PKT_CLR_avi_clr 1 |
| #define bHDRX_PKT_CLR_avi_clr 1 |
| #define MSK32HDRX_PKT_CLR_avi_clr 0x00000002 |
| #define BA_HDRX_PKT_CLR_spd_clr 0x0194 |
| #define B16HDRX_PKT_CLR_spd_clr 0x0194 |
| #define LSb32HDRX_PKT_CLR_spd_clr 2 |
| #define LSb16HDRX_PKT_CLR_spd_clr 2 |
| #define bHDRX_PKT_CLR_spd_clr 1 |
| #define MSK32HDRX_PKT_CLR_spd_clr 0x00000004 |
| #define BA_HDRX_PKT_CLR_aud_clr 0x0194 |
| #define B16HDRX_PKT_CLR_aud_clr 0x0194 |
| #define LSb32HDRX_PKT_CLR_aud_clr 3 |
| #define LSb16HDRX_PKT_CLR_aud_clr 3 |
| #define bHDRX_PKT_CLR_aud_clr 1 |
| #define MSK32HDRX_PKT_CLR_aud_clr 0x00000008 |
| #define BA_HDRX_PKT_CLR_mpeg_clr 0x0194 |
| #define B16HDRX_PKT_CLR_mpeg_clr 0x0194 |
| #define LSb32HDRX_PKT_CLR_mpeg_clr 4 |
| #define LSb16HDRX_PKT_CLR_mpeg_clr 4 |
| #define bHDRX_PKT_CLR_mpeg_clr 1 |
| #define MSK32HDRX_PKT_CLR_mpeg_clr 0x00000010 |
| #define BA_HDRX_PKT_CLR_gmd_spec_clr 0x0194 |
| #define B16HDRX_PKT_CLR_gmd_spec_clr 0x0194 |
| #define LSb32HDRX_PKT_CLR_gmd_spec_clr 5 |
| #define LSb16HDRX_PKT_CLR_gmd_spec_clr 5 |
| #define bHDRX_PKT_CLR_gmd_spec_clr 1 |
| #define MSK32HDRX_PKT_CLR_gmd_spec_clr 0x00000020 |
| #define BA_HDRX_PKT_CLR_amd_clr 0x0194 |
| #define B16HDRX_PKT_CLR_amd_clr 0x0194 |
| #define LSb32HDRX_PKT_CLR_amd_clr 6 |
| #define LSb16HDRX_PKT_CLR_amd_clr 6 |
| #define bHDRX_PKT_CLR_amd_clr 1 |
| #define MSK32HDRX_PKT_CLR_amd_clr 0x00000040 |
| #define BA_HDRX_PKT_CLR_isrc1_clr 0x0194 |
| #define B16HDRX_PKT_CLR_isrc1_clr 0x0194 |
| #define LSb32HDRX_PKT_CLR_isrc1_clr 7 |
| #define LSb16HDRX_PKT_CLR_isrc1_clr 7 |
| #define bHDRX_PKT_CLR_isrc1_clr 1 |
| #define MSK32HDRX_PKT_CLR_isrc1_clr 0x00000080 |
| #define BA_HDRX_PKT_CLR_isrc2_clr 0x0195 |
| #define B16HDRX_PKT_CLR_isrc2_clr 0x0194 |
| #define LSb32HDRX_PKT_CLR_isrc2_clr 8 |
| #define LSb16HDRX_PKT_CLR_isrc2_clr 8 |
| #define bHDRX_PKT_CLR_isrc2_clr 1 |
| #define MSK32HDRX_PKT_CLR_isrc2_clr 0x00000100 |
| #define BA_HDRX_PKT_CLR_avmute_clr 0x0195 |
| #define B16HDRX_PKT_CLR_avmute_clr 0x0194 |
| #define LSb32HDRX_PKT_CLR_avmute_clr 9 |
| #define LSb16HDRX_PKT_CLR_avmute_clr 9 |
| #define bHDRX_PKT_CLR_avmute_clr 1 |
| #define MSK32HDRX_PKT_CLR_avmute_clr 0x00000200 |
| #define BA_HDRX_PKT_CLR_cd_clr 0x0195 |
| #define B16HDRX_PKT_CLR_cd_clr 0x0194 |
| #define LSb32HDRX_PKT_CLR_cd_clr 10 |
| #define LSb16HDRX_PKT_CLR_cd_clr 10 |
| #define bHDRX_PKT_CLR_cd_clr 1 |
| #define MSK32HDRX_PKT_CLR_cd_clr 0x00000400 |
| #define BA_HDRX_PKT_CLR_acr_clr 0x0195 |
| #define B16HDRX_PKT_CLR_acr_clr 0x0194 |
| #define LSb32HDRX_PKT_CLR_acr_clr 11 |
| #define LSb16HDRX_PKT_CLR_acr_clr 11 |
| #define bHDRX_PKT_CLR_acr_clr 1 |
| #define MSK32HDRX_PKT_CLR_acr_clr 0x00000800 |
| #define BA_HDRX_PKT_CLR_acp_clr 0x0195 |
| #define B16HDRX_PKT_CLR_acp_clr 0x0194 |
| #define LSb32HDRX_PKT_CLR_acp_clr 12 |
| #define LSb16HDRX_PKT_CLR_acp_clr 12 |
| #define bHDRX_PKT_CLR_acp_clr 1 |
| #define MSK32HDRX_PKT_CLR_acp_clr 0x00001000 |
| #define BA_HDRX_PKT_CLR_chsts_clr 0x0195 |
| #define B16HDRX_PKT_CLR_chsts_clr 0x0194 |
| #define LSb32HDRX_PKT_CLR_chsts_clr 13 |
| #define LSb16HDRX_PKT_CLR_chsts_clr 13 |
| #define bHDRX_PKT_CLR_chsts_clr 1 |
| #define MSK32HDRX_PKT_CLR_chsts_clr 0x00002000 |
| #define BA_HDRX_PKT_CLR_ubits_clr 0x0195 |
| #define B16HDRX_PKT_CLR_ubits_clr 0x0194 |
| #define LSb32HDRX_PKT_CLR_ubits_clr 14 |
| #define LSb16HDRX_PKT_CLR_ubits_clr 14 |
| #define bHDRX_PKT_CLR_ubits_clr 1 |
| #define MSK32HDRX_PKT_CLR_ubits_clr 0x00004000 |
| #define BA_HDRX_PKT_CLR_drm_info_clr 0x0195 |
| #define B16HDRX_PKT_CLR_drm_info_clr 0x0194 |
| #define LSb32HDRX_PKT_CLR_drm_info_clr 15 |
| #define LSb16HDRX_PKT_CLR_drm_info_clr 15 |
| #define bHDRX_PKT_CLR_drm_info_clr 1 |
| #define MSK32HDRX_PKT_CLR_drm_info_clr 0x00008000 |
| #define RA_HDRX_PKT_CNT_CLR 0x0198 |
| #define BA_HDRX_PKT_CNT_CLR_mul_ecc_err_cnt_clr 0x0198 |
| #define B16HDRX_PKT_CNT_CLR_mul_ecc_err_cnt_clr 0x0198 |
| #define LSb32HDRX_PKT_CNT_CLR_mul_ecc_err_cnt_clr 0 |
| #define LSb16HDRX_PKT_CNT_CLR_mul_ecc_err_cnt_clr 0 |
| #define bHDRX_PKT_CNT_CLR_mul_ecc_err_cnt_clr 1 |
| #define MSK32HDRX_PKT_CNT_CLR_mul_ecc_err_cnt_clr 0x00000001 |
| #define BA_HDRX_PKT_CNT_CLR_ecc_err_cnt_sw_clr 0x0198 |
| #define B16HDRX_PKT_CNT_CLR_ecc_err_cnt_sw_clr 0x0198 |
| #define LSb32HDRX_PKT_CNT_CLR_ecc_err_cnt_sw_clr 1 |
| #define LSb16HDRX_PKT_CNT_CLR_ecc_err_cnt_sw_clr 1 |
| #define bHDRX_PKT_CNT_CLR_ecc_err_cnt_sw_clr 1 |
| #define MSK32HDRX_PKT_CNT_CLR_ecc_err_cnt_sw_clr 0x00000002 |
| #define BA_HDRX_PKT_CNT_CLR_sgl_ecc_err_cnt_clr 0x0198 |
| #define B16HDRX_PKT_CNT_CLR_sgl_ecc_err_cnt_clr 0x0198 |
| #define LSb32HDRX_PKT_CNT_CLR_sgl_ecc_err_cnt_clr 2 |
| #define LSb16HDRX_PKT_CNT_CLR_sgl_ecc_err_cnt_clr 2 |
| #define bHDRX_PKT_CNT_CLR_sgl_ecc_err_cnt_clr 1 |
| #define MSK32HDRX_PKT_CNT_CLR_sgl_ecc_err_cnt_clr 0x00000004 |
| #define BA_HDRX_PKT_CNT_CLR_null_cnt_clr 0x0198 |
| #define B16HDRX_PKT_CNT_CLR_null_cnt_clr 0x0198 |
| #define LSb32HDRX_PKT_CNT_CLR_null_cnt_clr 3 |
| #define LSb16HDRX_PKT_CNT_CLR_null_cnt_clr 3 |
| #define bHDRX_PKT_CNT_CLR_null_cnt_clr 1 |
| #define MSK32HDRX_PKT_CNT_CLR_null_cnt_clr 0x00000008 |
| #define BA_HDRX_PKT_CNT_CLR_ven_info_cnt_clr 0x0198 |
| #define B16HDRX_PKT_CNT_CLR_ven_info_cnt_clr 0x0198 |
| #define LSb32HDRX_PKT_CNT_CLR_ven_info_cnt_clr 4 |
| #define LSb16HDRX_PKT_CNT_CLR_ven_info_cnt_clr 4 |
| #define bHDRX_PKT_CNT_CLR_ven_info_cnt_clr 1 |
| #define MSK32HDRX_PKT_CNT_CLR_ven_info_cnt_clr 0x00000010 |
| #define BA_HDRX_PKT_CNT_CLR_avi_pkt_cnt_clr 0x0198 |
| #define B16HDRX_PKT_CNT_CLR_avi_pkt_cnt_clr 0x0198 |
| #define LSb32HDRX_PKT_CNT_CLR_avi_pkt_cnt_clr 5 |
| #define LSb16HDRX_PKT_CNT_CLR_avi_pkt_cnt_clr 5 |
| #define bHDRX_PKT_CNT_CLR_avi_pkt_cnt_clr 1 |
| #define MSK32HDRX_PKT_CNT_CLR_avi_pkt_cnt_clr 0x00000020 |
| #define BA_HDRX_PKT_CNT_CLR_spd_pkt_cnt_clr 0x0198 |
| #define B16HDRX_PKT_CNT_CLR_spd_pkt_cnt_clr 0x0198 |
| #define LSb32HDRX_PKT_CNT_CLR_spd_pkt_cnt_clr 6 |
| #define LSb16HDRX_PKT_CNT_CLR_spd_pkt_cnt_clr 6 |
| #define bHDRX_PKT_CNT_CLR_spd_pkt_cnt_clr 1 |
| #define MSK32HDRX_PKT_CNT_CLR_spd_pkt_cnt_clr 0x00000040 |
| #define BA_HDRX_PKT_CNT_CLR_aud_info_pkt_cnt_clr 0x0198 |
| #define B16HDRX_PKT_CNT_CLR_aud_info_pkt_cnt_clr 0x0198 |
| #define LSb32HDRX_PKT_CNT_CLR_aud_info_pkt_cnt_clr 7 |
| #define LSb16HDRX_PKT_CNT_CLR_aud_info_pkt_cnt_clr 7 |
| #define bHDRX_PKT_CNT_CLR_aud_info_pkt_cnt_clr 1 |
| #define MSK32HDRX_PKT_CNT_CLR_aud_info_pkt_cnt_clr 0x00000080 |
| #define BA_HDRX_PKT_CNT_CLR_mpeg_info_pkt_cnt_clr 0x0199 |
| #define B16HDRX_PKT_CNT_CLR_mpeg_info_pkt_cnt_clr 0x0198 |
| #define LSb32HDRX_PKT_CNT_CLR_mpeg_info_pkt_cnt_clr 8 |
| #define LSb16HDRX_PKT_CNT_CLR_mpeg_info_pkt_cnt_clr 8 |
| #define bHDRX_PKT_CNT_CLR_mpeg_info_pkt_cnt_clr 1 |
| #define MSK32HDRX_PKT_CNT_CLR_mpeg_info_pkt_cnt_clr 0x00000100 |
| #define BA_HDRX_PKT_CNT_CLR_amd_cnt_clr 0x0199 |
| #define B16HDRX_PKT_CNT_CLR_amd_cnt_clr 0x0198 |
| #define LSb32HDRX_PKT_CNT_CLR_amd_cnt_clr 9 |
| #define LSb16HDRX_PKT_CNT_CLR_amd_cnt_clr 9 |
| #define bHDRX_PKT_CNT_CLR_amd_cnt_clr 1 |
| #define MSK32HDRX_PKT_CNT_CLR_amd_cnt_clr 0x00000200 |
| #define BA_HDRX_PKT_CNT_CLR_gmd_cnt_clr 0x0199 |
| #define B16HDRX_PKT_CNT_CLR_gmd_cnt_clr 0x0198 |
| #define LSb32HDRX_PKT_CNT_CLR_gmd_cnt_clr 10 |
| #define LSb16HDRX_PKT_CNT_CLR_gmd_cnt_clr 10 |
| #define bHDRX_PKT_CNT_CLR_gmd_cnt_clr 1 |
| #define MSK32HDRX_PKT_CNT_CLR_gmd_cnt_clr 0x00000400 |
| #define BA_HDRX_PKT_CNT_CLR_isrc1_cnt_clr 0x0199 |
| #define B16HDRX_PKT_CNT_CLR_isrc1_cnt_clr 0x0198 |
| #define LSb32HDRX_PKT_CNT_CLR_isrc1_cnt_clr 11 |
| #define LSb16HDRX_PKT_CNT_CLR_isrc1_cnt_clr 11 |
| #define bHDRX_PKT_CNT_CLR_isrc1_cnt_clr 1 |
| #define MSK32HDRX_PKT_CNT_CLR_isrc1_cnt_clr 0x00000800 |
| #define BA_HDRX_PKT_CNT_CLR_isrc2_cnt_clr 0x0199 |
| #define B16HDRX_PKT_CNT_CLR_isrc2_cnt_clr 0x0198 |
| #define LSb32HDRX_PKT_CNT_CLR_isrc2_cnt_clr 12 |
| #define LSb16HDRX_PKT_CNT_CLR_isrc2_cnt_clr 12 |
| #define bHDRX_PKT_CNT_CLR_isrc2_cnt_clr 1 |
| #define MSK32HDRX_PKT_CNT_CLR_isrc2_cnt_clr 0x00001000 |
| #define BA_HDRX_PKT_CNT_CLR_acp_cnt_clr 0x0199 |
| #define B16HDRX_PKT_CNT_CLR_acp_cnt_clr 0x0198 |
| #define LSb32HDRX_PKT_CNT_CLR_acp_cnt_clr 13 |
| #define LSb16HDRX_PKT_CNT_CLR_acp_cnt_clr 13 |
| #define bHDRX_PKT_CNT_CLR_acp_cnt_clr 1 |
| #define MSK32HDRX_PKT_CNT_CLR_acp_cnt_clr 0x00002000 |
| #define BA_HDRX_PKT_CNT_CLR_acr_cnt_clr 0x0199 |
| #define B16HDRX_PKT_CNT_CLR_acr_cnt_clr 0x0198 |
| #define LSb32HDRX_PKT_CNT_CLR_acr_cnt_clr 14 |
| #define LSb16HDRX_PKT_CNT_CLR_acr_cnt_clr 14 |
| #define bHDRX_PKT_CNT_CLR_acr_cnt_clr 1 |
| #define MSK32HDRX_PKT_CNT_CLR_acr_cnt_clr 0x00004000 |
| #define BA_HDRX_PKT_CNT_CLR_gcp_cnt_clr 0x0199 |
| #define B16HDRX_PKT_CNT_CLR_gcp_cnt_clr 0x0198 |
| #define LSb32HDRX_PKT_CNT_CLR_gcp_cnt_clr 15 |
| #define LSb16HDRX_PKT_CNT_CLR_gcp_cnt_clr 15 |
| #define bHDRX_PKT_CNT_CLR_gcp_cnt_clr 1 |
| #define MSK32HDRX_PKT_CNT_CLR_gcp_cnt_clr 0x00008000 |
| #define BA_HDRX_PKT_CNT_CLR_drm_info_cnt_clr 0x019A |
| #define B16HDRX_PKT_CNT_CLR_drm_info_cnt_clr 0x019A |
| #define LSb32HDRX_PKT_CNT_CLR_drm_info_cnt_clr 16 |
| #define LSb16HDRX_PKT_CNT_CLR_drm_info_cnt_clr 0 |
| #define bHDRX_PKT_CNT_CLR_drm_info_cnt_clr 1 |
| #define MSK32HDRX_PKT_CNT_CLR_drm_info_cnt_clr 0x00010000 |
| #define RA_HDRX_DI_INTR_CTRL 0x019C |
| #define BA_HDRX_DI_INTR_CTRL_en_checksum 0x019C |
| #define B16HDRX_DI_INTR_CTRL_en_checksum 0x019C |
| #define LSb32HDRX_DI_INTR_CTRL_en_checksum 0 |
| #define LSb16HDRX_DI_INTR_CTRL_en_checksum 0 |
| #define bHDRX_DI_INTR_CTRL_en_checksum 1 |
| #define MSK32HDRX_DI_INTR_CTRL_en_checksum 0x00000001 |
| #define RA_HDRX_INTR_EN 0x01A0 |
| #define BA_HDRX_INTR_EN_acr_n_intr_en 0x01A0 |
| #define B16HDRX_INTR_EN_acr_n_intr_en 0x01A0 |
| #define LSb32HDRX_INTR_EN_acr_n_intr_en 0 |
| #define LSb16HDRX_INTR_EN_acr_n_intr_en 0 |
| #define bHDRX_INTR_EN_acr_n_intr_en 1 |
| #define MSK32HDRX_INTR_EN_acr_n_intr_en 0x00000001 |
| #define BA_HDRX_INTR_EN_acr_cts_intr_en 0x01A0 |
| #define B16HDRX_INTR_EN_acr_cts_intr_en 0x01A0 |
| #define LSb32HDRX_INTR_EN_acr_cts_intr_en 1 |
| #define LSb16HDRX_INTR_EN_acr_cts_intr_en 1 |
| #define bHDRX_INTR_EN_acr_cts_intr_en 1 |
| #define MSK32HDRX_INTR_EN_acr_cts_intr_en 0x00000002 |
| #define BA_HDRX_INTR_EN_gcp_avmute_intr_en 0x01A0 |
| #define B16HDRX_INTR_EN_gcp_avmute_intr_en 0x01A0 |
| #define LSb32HDRX_INTR_EN_gcp_avmute_intr_en 2 |
| #define LSb16HDRX_INTR_EN_gcp_avmute_intr_en 2 |
| #define bHDRX_INTR_EN_gcp_avmute_intr_en 1 |
| #define MSK32HDRX_INTR_EN_gcp_avmute_intr_en 0x00000004 |
| #define BA_HDRX_INTR_EN_gcp_cd_intr_en 0x01A0 |
| #define B16HDRX_INTR_EN_gcp_cd_intr_en 0x01A0 |
| #define LSb32HDRX_INTR_EN_gcp_cd_intr_en 3 |
| #define LSb16HDRX_INTR_EN_gcp_cd_intr_en 3 |
| #define bHDRX_INTR_EN_gcp_cd_intr_en 1 |
| #define MSK32HDRX_INTR_EN_gcp_cd_intr_en 0x00000008 |
| #define BA_HDRX_INTR_EN_gcp_dp_intr_en 0x01A0 |
| #define B16HDRX_INTR_EN_gcp_dp_intr_en 0x01A0 |
| #define LSb32HDRX_INTR_EN_gcp_dp_intr_en 4 |
| #define LSb16HDRX_INTR_EN_gcp_dp_intr_en 4 |
| #define bHDRX_INTR_EN_gcp_dp_intr_en 1 |
| #define MSK32HDRX_INTR_EN_gcp_dp_intr_en 0x00000010 |
| #define BA_HDRX_INTR_EN_acp_pkt_intr_en 0x01A0 |
| #define B16HDRX_INTR_EN_acp_pkt_intr_en 0x01A0 |
| #define LSb32HDRX_INTR_EN_acp_pkt_intr_en 5 |
| #define LSb16HDRX_INTR_EN_acp_pkt_intr_en 5 |
| #define bHDRX_INTR_EN_acp_pkt_intr_en 1 |
| #define MSK32HDRX_INTR_EN_acp_pkt_intr_en 0x00000020 |
| #define BA_HDRX_INTR_EN_isrc1_pkt_intr_en 0x01A0 |
| #define B16HDRX_INTR_EN_isrc1_pkt_intr_en 0x01A0 |
| #define LSb32HDRX_INTR_EN_isrc1_pkt_intr_en 6 |
| #define LSb16HDRX_INTR_EN_isrc1_pkt_intr_en 6 |
| #define bHDRX_INTR_EN_isrc1_pkt_intr_en 1 |
| #define MSK32HDRX_INTR_EN_isrc1_pkt_intr_en 0x00000040 |
| #define BA_HDRX_INTR_EN_isrc2_pkt_intr_en 0x01A0 |
| #define B16HDRX_INTR_EN_isrc2_pkt_intr_en 0x01A0 |
| #define LSb32HDRX_INTR_EN_isrc2_pkt_intr_en 7 |
| #define LSb16HDRX_INTR_EN_isrc2_pkt_intr_en 7 |
| #define bHDRX_INTR_EN_isrc2_pkt_intr_en 1 |
| #define MSK32HDRX_INTR_EN_isrc2_pkt_intr_en 0x00000080 |
| #define BA_HDRX_INTR_EN_gmd_pkt_intr_en 0x01A1 |
| #define B16HDRX_INTR_EN_gmd_pkt_intr_en 0x01A0 |
| #define LSb32HDRX_INTR_EN_gmd_pkt_intr_en 8 |
| #define LSb16HDRX_INTR_EN_gmd_pkt_intr_en 8 |
| #define bHDRX_INTR_EN_gmd_pkt_intr_en 1 |
| #define MSK32HDRX_INTR_EN_gmd_pkt_intr_en 0x00000100 |
| #define BA_HDRX_INTR_EN_amd_pkt_intr_en 0x01A1 |
| #define B16HDRX_INTR_EN_amd_pkt_intr_en 0x01A0 |
| #define LSb32HDRX_INTR_EN_amd_pkt_intr_en 9 |
| #define LSb16HDRX_INTR_EN_amd_pkt_intr_en 9 |
| #define bHDRX_INTR_EN_amd_pkt_intr_en 1 |
| #define MSK32HDRX_INTR_EN_amd_pkt_intr_en 0x00000200 |
| #define BA_HDRX_INTR_EN_ven_spec_pkt_intr_en 0x01A1 |
| #define B16HDRX_INTR_EN_ven_spec_pkt_intr_en 0x01A0 |
| #define LSb32HDRX_INTR_EN_ven_spec_pkt_intr_en 10 |
| #define LSb16HDRX_INTR_EN_ven_spec_pkt_intr_en 10 |
| #define bHDRX_INTR_EN_ven_spec_pkt_intr_en 1 |
| #define MSK32HDRX_INTR_EN_ven_spec_pkt_intr_en 0x00000400 |
| #define BA_HDRX_INTR_EN_avi_info_pkt_intr_en 0x01A1 |
| #define B16HDRX_INTR_EN_avi_info_pkt_intr_en 0x01A0 |
| #define LSb32HDRX_INTR_EN_avi_info_pkt_intr_en 11 |
| #define LSb16HDRX_INTR_EN_avi_info_pkt_intr_en 11 |
| #define bHDRX_INTR_EN_avi_info_pkt_intr_en 1 |
| #define MSK32HDRX_INTR_EN_avi_info_pkt_intr_en 0x00000800 |
| #define BA_HDRX_INTR_EN_spd_pkt_intr_en 0x01A1 |
| #define B16HDRX_INTR_EN_spd_pkt_intr_en 0x01A0 |
| #define LSb32HDRX_INTR_EN_spd_pkt_intr_en 12 |
| #define LSb16HDRX_INTR_EN_spd_pkt_intr_en 12 |
| #define bHDRX_INTR_EN_spd_pkt_intr_en 1 |
| #define MSK32HDRX_INTR_EN_spd_pkt_intr_en 0x00001000 |
| #define BA_HDRX_INTR_EN_aud_info_pkt_intr_en 0x01A1 |
| #define B16HDRX_INTR_EN_aud_info_pkt_intr_en 0x01A0 |
| #define LSb32HDRX_INTR_EN_aud_info_pkt_intr_en 13 |
| #define LSb16HDRX_INTR_EN_aud_info_pkt_intr_en 13 |
| #define bHDRX_INTR_EN_aud_info_pkt_intr_en 1 |
| #define MSK32HDRX_INTR_EN_aud_info_pkt_intr_en 0x00002000 |
| #define BA_HDRX_INTR_EN_mpeg_info_pkt_intr_en 0x01A1 |
| #define B16HDRX_INTR_EN_mpeg_info_pkt_intr_en 0x01A0 |
| #define LSb32HDRX_INTR_EN_mpeg_info_pkt_intr_en 14 |
| #define LSb16HDRX_INTR_EN_mpeg_info_pkt_intr_en 14 |
| #define bHDRX_INTR_EN_mpeg_info_pkt_intr_en 1 |
| #define MSK32HDRX_INTR_EN_mpeg_info_pkt_intr_en 0x00004000 |
| #define BA_HDRX_INTR_EN_chsts_intr_en 0x01A1 |
| #define B16HDRX_INTR_EN_chsts_intr_en 0x01A0 |
| #define LSb32HDRX_INTR_EN_chsts_intr_en 15 |
| #define LSb16HDRX_INTR_EN_chsts_intr_en 15 |
| #define bHDRX_INTR_EN_chsts_intr_en 1 |
| #define MSK32HDRX_INTR_EN_chsts_intr_en 0x00008000 |
| #define BA_HDRX_INTR_EN_tmds_mode_intr_en 0x01A2 |
| #define B16HDRX_INTR_EN_tmds_mode_intr_en 0x01A2 |
| #define LSb32HDRX_INTR_EN_tmds_mode_intr_en 16 |
| #define LSb16HDRX_INTR_EN_tmds_mode_intr_en 0 |
| #define bHDRX_INTR_EN_tmds_mode_intr_en 1 |
| #define MSK32HDRX_INTR_EN_tmds_mode_intr_en 0x00010000 |
| #define BA_HDRX_INTR_EN_auth_start_intr_en 0x01A2 |
| #define B16HDRX_INTR_EN_auth_start_intr_en 0x01A2 |
| #define LSb32HDRX_INTR_EN_auth_start_intr_en 17 |
| #define LSb16HDRX_INTR_EN_auth_start_intr_en 1 |
| #define bHDRX_INTR_EN_auth_start_intr_en 1 |
| #define MSK32HDRX_INTR_EN_auth_start_intr_en 0x00020000 |
| #define BA_HDRX_INTR_EN_auth_cmplt_intr_en 0x01A2 |
| #define B16HDRX_INTR_EN_auth_cmplt_intr_en 0x01A2 |
| #define LSb32HDRX_INTR_EN_auth_cmplt_intr_en 18 |
| #define LSb16HDRX_INTR_EN_auth_cmplt_intr_en 2 |
| #define bHDRX_INTR_EN_auth_cmplt_intr_en 1 |
| #define MSK32HDRX_INTR_EN_auth_cmplt_intr_en 0x00040000 |
| #define BA_HDRX_INTR_EN_vsync_intr_en 0x01A2 |
| #define B16HDRX_INTR_EN_vsync_intr_en 0x01A2 |
| #define LSb32HDRX_INTR_EN_vsync_intr_en 19 |
| #define LSb16HDRX_INTR_EN_vsync_intr_en 3 |
| #define bHDRX_INTR_EN_vsync_intr_en 1 |
| #define MSK32HDRX_INTR_EN_vsync_intr_en 0x00080000 |
| #define BA_HDRX_INTR_EN_ubits_intr_en 0x01A2 |
| #define B16HDRX_INTR_EN_ubits_intr_en 0x01A2 |
| #define LSb32HDRX_INTR_EN_ubits_intr_en 20 |
| #define LSb16HDRX_INTR_EN_ubits_intr_en 4 |
| #define bHDRX_INTR_EN_ubits_intr_en 1 |
| #define MSK32HDRX_INTR_EN_ubits_intr_en 0x00100000 |
| #define BA_HDRX_INTR_EN_vsi_stop_intr_en 0x01A2 |
| #define B16HDRX_INTR_EN_vsi_stop_intr_en 0x01A2 |
| #define LSb32HDRX_INTR_EN_vsi_stop_intr_en 21 |
| #define LSb16HDRX_INTR_EN_vsi_stop_intr_en 5 |
| #define bHDRX_INTR_EN_vsi_stop_intr_en 1 |
| #define MSK32HDRX_INTR_EN_vsi_stop_intr_en 0x00200000 |
| #define BA_HDRX_INTR_EN_sync_det_intr_en 0x01A2 |
| #define B16HDRX_INTR_EN_sync_det_intr_en 0x01A2 |
| #define LSb32HDRX_INTR_EN_sync_det_intr_en 22 |
| #define LSb16HDRX_INTR_EN_sync_det_intr_en 6 |
| #define bHDRX_INTR_EN_sync_det_intr_en 1 |
| #define MSK32HDRX_INTR_EN_sync_det_intr_en 0x00400000 |
| #define BA_HDRX_INTR_EN_vres_chg_intr_en 0x01A2 |
| #define B16HDRX_INTR_EN_vres_chg_intr_en 0x01A2 |
| #define LSb32HDRX_INTR_EN_vres_chg_intr_en 23 |
| #define LSb16HDRX_INTR_EN_vres_chg_intr_en 7 |
| #define bHDRX_INTR_EN_vres_chg_intr_en 1 |
| #define MSK32HDRX_INTR_EN_vres_chg_intr_en 0x00800000 |
| #define BA_HDRX_INTR_EN_hres_chg_intr_en 0x01A3 |
| #define B16HDRX_INTR_EN_hres_chg_intr_en 0x01A2 |
| #define LSb32HDRX_INTR_EN_hres_chg_intr_en 24 |
| #define LSb16HDRX_INTR_EN_hres_chg_intr_en 8 |
| #define bHDRX_INTR_EN_hres_chg_intr_en 1 |
| #define MSK32HDRX_INTR_EN_hres_chg_intr_en 0x01000000 |
| #define BA_HDRX_INTR_EN_ced_cnt_update_intr_en 0x01A3 |
| #define B16HDRX_INTR_EN_ced_cnt_update_intr_en 0x01A2 |
| #define LSb32HDRX_INTR_EN_ced_cnt_update_intr_en 25 |
| #define LSb16HDRX_INTR_EN_ced_cnt_update_intr_en 9 |
| #define bHDRX_INTR_EN_ced_cnt_update_intr_en 1 |
| #define MSK32HDRX_INTR_EN_ced_cnt_update_intr_en 0x02000000 |
| #define BA_HDRX_INTR_EN_unplug_intr_en 0x01A3 |
| #define B16HDRX_INTR_EN_unplug_intr_en 0x01A2 |
| #define LSb32HDRX_INTR_EN_unplug_intr_en 26 |
| #define LSb16HDRX_INTR_EN_unplug_intr_en 10 |
| #define bHDRX_INTR_EN_unplug_intr_en 1 |
| #define MSK32HDRX_INTR_EN_unplug_intr_en 0x04000000 |
| #define BA_HDRX_INTR_EN_clk_det_intr_en 0x01A3 |
| #define B16HDRX_INTR_EN_clk_det_intr_en 0x01A2 |
| #define LSb32HDRX_INTR_EN_clk_det_intr_en 27 |
| #define LSb16HDRX_INTR_EN_clk_det_intr_en 11 |
| #define bHDRX_INTR_EN_clk_det_intr_en 1 |
| #define MSK32HDRX_INTR_EN_clk_det_intr_en 0x08000000 |
| #define BA_HDRX_INTR_EN_edid_intr_en 0x01A3 |
| #define B16HDRX_INTR_EN_edid_intr_en 0x01A2 |
| #define LSb32HDRX_INTR_EN_edid_intr_en 28 |
| #define LSb16HDRX_INTR_EN_edid_intr_en 12 |
| #define bHDRX_INTR_EN_edid_intr_en 1 |
| #define MSK32HDRX_INTR_EN_edid_intr_en 0x10000000 |
| #define BA_HDRX_INTR_EN_tmds_bit_clk_ratio_intr_en 0x01A3 |
| #define B16HDRX_INTR_EN_tmds_bit_clk_ratio_intr_en 0x01A2 |
| #define LSb32HDRX_INTR_EN_tmds_bit_clk_ratio_intr_en 29 |
| #define LSb16HDRX_INTR_EN_tmds_bit_clk_ratio_intr_en 13 |
| #define bHDRX_INTR_EN_tmds_bit_clk_ratio_intr_en 1 |
| #define MSK32HDRX_INTR_EN_tmds_bit_clk_ratio_intr_en 0x20000000 |
| #define BA_HDRX_INTR_EN_scrambler_en_intr_en 0x01A3 |
| #define B16HDRX_INTR_EN_scrambler_en_intr_en 0x01A2 |
| #define LSb32HDRX_INTR_EN_scrambler_en_intr_en 30 |
| #define LSb16HDRX_INTR_EN_scrambler_en_intr_en 14 |
| #define bHDRX_INTR_EN_scrambler_en_intr_en 1 |
| #define MSK32HDRX_INTR_EN_scrambler_en_intr_en 0x40000000 |
| #define BA_HDRX_INTR_EN_rr_enable_intr_en 0x01A3 |
| #define B16HDRX_INTR_EN_rr_enable_intr_en 0x01A2 |
| #define LSb32HDRX_INTR_EN_rr_enable_intr_en 31 |
| #define LSb16HDRX_INTR_EN_rr_enable_intr_en 15 |
| #define bHDRX_INTR_EN_rr_enable_intr_en 1 |
| #define MSK32HDRX_INTR_EN_rr_enable_intr_en 0x80000000 |
| #define RA_HDRX_INTR_EN1 0x01A4 |
| #define BA_HDRX_INTR_EN_wr_mssg_started_intr_en 0x01A4 |
| #define B16HDRX_INTR_EN_wr_mssg_started_intr_en 0x01A4 |
| #define LSb32HDRX_INTR_EN_wr_mssg_started_intr_en 0 |
| #define LSb16HDRX_INTR_EN_wr_mssg_started_intr_en 0 |
| #define bHDRX_INTR_EN_wr_mssg_started_intr_en 1 |
| #define MSK32HDRX_INTR_EN_wr_mssg_started_intr_en 0x00000001 |
| #define BA_HDRX_INTR_EN_wr_mssg_done_intr_en 0x01A4 |
| #define B16HDRX_INTR_EN_wr_mssg_done_intr_en 0x01A4 |
| #define LSb32HDRX_INTR_EN_wr_mssg_done_intr_en 1 |
| #define LSb16HDRX_INTR_EN_wr_mssg_done_intr_en 1 |
| #define bHDRX_INTR_EN_wr_mssg_done_intr_en 1 |
| #define MSK32HDRX_INTR_EN_wr_mssg_done_intr_en 0x00000002 |
| #define BA_HDRX_INTR_EN_read_message_done_intr_en 0x01A4 |
| #define B16HDRX_INTR_EN_read_message_done_intr_en 0x01A4 |
| #define LSb32HDRX_INTR_EN_read_message_done_intr_en 2 |
| #define LSb16HDRX_INTR_EN_read_message_done_intr_en 2 |
| #define bHDRX_INTR_EN_read_message_done_intr_en 1 |
| #define MSK32HDRX_INTR_EN_read_message_done_intr_en 0x00000004 |
| #define BA_HDRX_INTR_EN_read_message_fail_intr_en 0x01A4 |
| #define B16HDRX_INTR_EN_read_message_fail_intr_en 0x01A4 |
| #define LSb32HDRX_INTR_EN_read_message_fail_intr_en 3 |
| #define LSb16HDRX_INTR_EN_read_message_fail_intr_en 3 |
| #define bHDRX_INTR_EN_read_message_fail_intr_en 1 |
| #define MSK32HDRX_INTR_EN_read_message_fail_intr_en 0x00000008 |
| #define BA_HDRX_INTR_EN_hmac_sm_rdy_en 0x01A4 |
| #define B16HDRX_INTR_EN_hmac_sm_rdy_en 0x01A4 |
| #define LSb32HDRX_INTR_EN_hmac_sm_rdy_en 4 |
| #define LSb16HDRX_INTR_EN_hmac_sm_rdy_en 4 |
| #define bHDRX_INTR_EN_hmac_sm_rdy_en 1 |
| #define MSK32HDRX_INTR_EN_hmac_sm_rdy_en 0x00000010 |
| #define BA_HDRX_INTR_EN_hmac_hash_done_en 0x01A4 |
| #define B16HDRX_INTR_EN_hmac_hash_done_en 0x01A4 |
| #define LSb32HDRX_INTR_EN_hmac_hash_done_en 5 |
| #define LSb16HDRX_INTR_EN_hmac_hash_done_en 5 |
| #define bHDRX_INTR_EN_hmac_hash_done_en 1 |
| #define MSK32HDRX_INTR_EN_hmac_hash_done_en 0x00000020 |
| #define BA_HDRX_INTR_EN_phy_prt_en_intr_en 0x01A4 |
| #define B16HDRX_INTR_EN_phy_prt_en_intr_en 0x01A4 |
| #define LSb32HDRX_INTR_EN_phy_prt_en_intr_en 6 |
| #define LSb16HDRX_INTR_EN_phy_prt_en_intr_en 6 |
| #define bHDRX_INTR_EN_phy_prt_en_intr_en 1 |
| #define MSK32HDRX_INTR_EN_phy_prt_en_intr_en 0x00000040 |
| #define BA_HDRX_INTR_EN_drm_info_intr_en 0x01A4 |
| #define B16HDRX_INTR_EN_drm_info_intr_en 0x01A4 |
| #define LSb32HDRX_INTR_EN_drm_info_intr_en 7 |
| #define LSb16HDRX_INTR_EN_drm_info_intr_en 7 |
| #define bHDRX_INTR_EN_drm_info_intr_en 1 |
| #define MSK32HDRX_INTR_EN_drm_info_intr_en 0x00000080 |
| #define BA_HDRX_INTR_EN_aud_fifo_over_flow_intr_en 0x01A5 |
| #define B16HDRX_INTR_EN_aud_fifo_over_flow_intr_en 0x01A4 |
| #define LSb32HDRX_INTR_EN_aud_fifo_over_flow_intr_en 8 |
| #define LSb16HDRX_INTR_EN_aud_fifo_over_flow_intr_en 8 |
| #define bHDRX_INTR_EN_aud_fifo_over_flow_intr_en 1 |
| #define MSK32HDRX_INTR_EN_aud_fifo_over_flow_intr_en 0x00000100 |
| #define BA_HDRX_INTR_EN_aud_fifo_under_flow_intr_en 0x01A5 |
| #define B16HDRX_INTR_EN_aud_fifo_under_flow_intr_en 0x01A4 |
| #define LSb32HDRX_INTR_EN_aud_fifo_under_flow_intr_en 9 |
| #define LSb16HDRX_INTR_EN_aud_fifo_under_flow_intr_en 9 |
| #define bHDRX_INTR_EN_aud_fifo_under_flow_intr_en 1 |
| #define MSK32HDRX_INTR_EN_aud_fifo_under_flow_intr_en 0x00000200 |
| #define BA_HDRX_INTR_EN_phy_pll_lock_intr_en 0x01A5 |
| #define B16HDRX_INTR_EN_phy_pll_lock_intr_en 0x01A4 |
| #define LSb32HDRX_INTR_EN_phy_pll_lock_intr_en 10 |
| #define LSb16HDRX_INTR_EN_phy_pll_lock_intr_en 10 |
| #define bHDRX_INTR_EN_phy_pll_lock_intr_en 1 |
| #define MSK32HDRX_INTR_EN_phy_pll_lock_intr_en 0x00000400 |
| #define RA_HDRX_INTR_STATUS 0x01A8 |
| #define BA_HDRX_INTR_STATUS_acr_n_intr_st 0x01A8 |
| #define B16HDRX_INTR_STATUS_acr_n_intr_st 0x01A8 |
| #define LSb32HDRX_INTR_STATUS_acr_n_intr_st 0 |
| #define LSb16HDRX_INTR_STATUS_acr_n_intr_st 0 |
| #define bHDRX_INTR_STATUS_acr_n_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_acr_n_intr_st 0x00000001 |
| #define BA_HDRX_INTR_STATUS_acr_cts_intr_st 0x01A8 |
| #define B16HDRX_INTR_STATUS_acr_cts_intr_st 0x01A8 |
| #define LSb32HDRX_INTR_STATUS_acr_cts_intr_st 1 |
| #define LSb16HDRX_INTR_STATUS_acr_cts_intr_st 1 |
| #define bHDRX_INTR_STATUS_acr_cts_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_acr_cts_intr_st 0x00000002 |
| #define BA_HDRX_INTR_STATUS_gcp_avmute_intr_st 0x01A8 |
| #define B16HDRX_INTR_STATUS_gcp_avmute_intr_st 0x01A8 |
| #define LSb32HDRX_INTR_STATUS_gcp_avmute_intr_st 2 |
| #define LSb16HDRX_INTR_STATUS_gcp_avmute_intr_st 2 |
| #define bHDRX_INTR_STATUS_gcp_avmute_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_gcp_avmute_intr_st 0x00000004 |
| #define BA_HDRX_INTR_STATUS_gcp_cd_intr_st 0x01A8 |
| #define B16HDRX_INTR_STATUS_gcp_cd_intr_st 0x01A8 |
| #define LSb32HDRX_INTR_STATUS_gcp_cd_intr_st 3 |
| #define LSb16HDRX_INTR_STATUS_gcp_cd_intr_st 3 |
| #define bHDRX_INTR_STATUS_gcp_cd_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_gcp_cd_intr_st 0x00000008 |
| #define BA_HDRX_INTR_STATUS_gcp_dp_intr_st 0x01A8 |
| #define B16HDRX_INTR_STATUS_gcp_dp_intr_st 0x01A8 |
| #define LSb32HDRX_INTR_STATUS_gcp_dp_intr_st 4 |
| #define LSb16HDRX_INTR_STATUS_gcp_dp_intr_st 4 |
| #define bHDRX_INTR_STATUS_gcp_dp_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_gcp_dp_intr_st 0x00000010 |
| #define BA_HDRX_INTR_STATUS_acp_pkt_intr_st 0x01A8 |
| #define B16HDRX_INTR_STATUS_acp_pkt_intr_st 0x01A8 |
| #define LSb32HDRX_INTR_STATUS_acp_pkt_intr_st 5 |
| #define LSb16HDRX_INTR_STATUS_acp_pkt_intr_st 5 |
| #define bHDRX_INTR_STATUS_acp_pkt_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_acp_pkt_intr_st 0x00000020 |
| #define BA_HDRX_INTR_STATUS_isrc1_pkt_intr_st 0x01A8 |
| #define B16HDRX_INTR_STATUS_isrc1_pkt_intr_st 0x01A8 |
| #define LSb32HDRX_INTR_STATUS_isrc1_pkt_intr_st 6 |
| #define LSb16HDRX_INTR_STATUS_isrc1_pkt_intr_st 6 |
| #define bHDRX_INTR_STATUS_isrc1_pkt_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_isrc1_pkt_intr_st 0x00000040 |
| #define BA_HDRX_INTR_STATUS_isrc2_pkt_intr_st 0x01A8 |
| #define B16HDRX_INTR_STATUS_isrc2_pkt_intr_st 0x01A8 |
| #define LSb32HDRX_INTR_STATUS_isrc2_pkt_intr_st 7 |
| #define LSb16HDRX_INTR_STATUS_isrc2_pkt_intr_st 7 |
| #define bHDRX_INTR_STATUS_isrc2_pkt_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_isrc2_pkt_intr_st 0x00000080 |
| #define BA_HDRX_INTR_STATUS_gmd_pkt_intr_st 0x01A9 |
| #define B16HDRX_INTR_STATUS_gmd_pkt_intr_st 0x01A8 |
| #define LSb32HDRX_INTR_STATUS_gmd_pkt_intr_st 8 |
| #define LSb16HDRX_INTR_STATUS_gmd_pkt_intr_st 8 |
| #define bHDRX_INTR_STATUS_gmd_pkt_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_gmd_pkt_intr_st 0x00000100 |
| #define BA_HDRX_INTR_STATUS_amd_pkt_intr_st 0x01A9 |
| #define B16HDRX_INTR_STATUS_amd_pkt_intr_st 0x01A8 |
| #define LSb32HDRX_INTR_STATUS_amd_pkt_intr_st 9 |
| #define LSb16HDRX_INTR_STATUS_amd_pkt_intr_st 9 |
| #define bHDRX_INTR_STATUS_amd_pkt_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_amd_pkt_intr_st 0x00000200 |
| #define BA_HDRX_INTR_STATUS_ven_spec_pkt_intr_st 0x01A9 |
| #define B16HDRX_INTR_STATUS_ven_spec_pkt_intr_st 0x01A8 |
| #define LSb32HDRX_INTR_STATUS_ven_spec_pkt_intr_st 10 |
| #define LSb16HDRX_INTR_STATUS_ven_spec_pkt_intr_st 10 |
| #define bHDRX_INTR_STATUS_ven_spec_pkt_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_ven_spec_pkt_intr_st 0x00000400 |
| #define BA_HDRX_INTR_STATUS_avi_info_pkt_intr_st 0x01A9 |
| #define B16HDRX_INTR_STATUS_avi_info_pkt_intr_st 0x01A8 |
| #define LSb32HDRX_INTR_STATUS_avi_info_pkt_intr_st 11 |
| #define LSb16HDRX_INTR_STATUS_avi_info_pkt_intr_st 11 |
| #define bHDRX_INTR_STATUS_avi_info_pkt_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_avi_info_pkt_intr_st 0x00000800 |
| #define BA_HDRX_INTR_STATUS_spd_pkt_intr_st 0x01A9 |
| #define B16HDRX_INTR_STATUS_spd_pkt_intr_st 0x01A8 |
| #define LSb32HDRX_INTR_STATUS_spd_pkt_intr_st 12 |
| #define LSb16HDRX_INTR_STATUS_spd_pkt_intr_st 12 |
| #define bHDRX_INTR_STATUS_spd_pkt_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_spd_pkt_intr_st 0x00001000 |
| #define BA_HDRX_INTR_STATUS_aud_info_pkt_intr_st 0x01A9 |
| #define B16HDRX_INTR_STATUS_aud_info_pkt_intr_st 0x01A8 |
| #define LSb32HDRX_INTR_STATUS_aud_info_pkt_intr_st 13 |
| #define LSb16HDRX_INTR_STATUS_aud_info_pkt_intr_st 13 |
| #define bHDRX_INTR_STATUS_aud_info_pkt_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_aud_info_pkt_intr_st 0x00002000 |
| #define BA_HDRX_INTR_STATUS_mpeg_info_pkt_intr_st 0x01A9 |
| #define B16HDRX_INTR_STATUS_mpeg_info_pkt_intr_st 0x01A8 |
| #define LSb32HDRX_INTR_STATUS_mpeg_info_pkt_intr_st 14 |
| #define LSb16HDRX_INTR_STATUS_mpeg_info_pkt_intr_st 14 |
| #define bHDRX_INTR_STATUS_mpeg_info_pkt_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_mpeg_info_pkt_intr_st 0x00004000 |
| #define BA_HDRX_INTR_STATUS_chsts_intr_st 0x01A9 |
| #define B16HDRX_INTR_STATUS_chsts_intr_st 0x01A8 |
| #define LSb32HDRX_INTR_STATUS_chsts_intr_st 15 |
| #define LSb16HDRX_INTR_STATUS_chsts_intr_st 15 |
| #define bHDRX_INTR_STATUS_chsts_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_chsts_intr_st 0x00008000 |
| #define BA_HDRX_INTR_STATUS_tmds_mode_intr_st 0x01AA |
| #define B16HDRX_INTR_STATUS_tmds_mode_intr_st 0x01AA |
| #define LSb32HDRX_INTR_STATUS_tmds_mode_intr_st 16 |
| #define LSb16HDRX_INTR_STATUS_tmds_mode_intr_st 0 |
| #define bHDRX_INTR_STATUS_tmds_mode_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_tmds_mode_intr_st 0x00010000 |
| #define BA_HDRX_INTR_STATUS_auth_start_intr_st 0x01AA |
| #define B16HDRX_INTR_STATUS_auth_start_intr_st 0x01AA |
| #define LSb32HDRX_INTR_STATUS_auth_start_intr_st 17 |
| #define LSb16HDRX_INTR_STATUS_auth_start_intr_st 1 |
| #define bHDRX_INTR_STATUS_auth_start_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_auth_start_intr_st 0x00020000 |
| #define BA_HDRX_INTR_STATUS_auth_cmplt_intr_st 0x01AA |
| #define B16HDRX_INTR_STATUS_auth_cmplt_intr_st 0x01AA |
| #define LSb32HDRX_INTR_STATUS_auth_cmplt_intr_st 18 |
| #define LSb16HDRX_INTR_STATUS_auth_cmplt_intr_st 2 |
| #define bHDRX_INTR_STATUS_auth_cmplt_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_auth_cmplt_intr_st 0x00040000 |
| #define BA_HDRX_INTR_STATUS_vsync_intr_st 0x01AA |
| #define B16HDRX_INTR_STATUS_vsync_intr_st 0x01AA |
| #define LSb32HDRX_INTR_STATUS_vsync_intr_st 19 |
| #define LSb16HDRX_INTR_STATUS_vsync_intr_st 3 |
| #define bHDRX_INTR_STATUS_vsync_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_vsync_intr_st 0x00080000 |
| #define BA_HDRX_INTR_STATUS_ubits_intr_st 0x01AA |
| #define B16HDRX_INTR_STATUS_ubits_intr_st 0x01AA |
| #define LSb32HDRX_INTR_STATUS_ubits_intr_st 20 |
| #define LSb16HDRX_INTR_STATUS_ubits_intr_st 4 |
| #define bHDRX_INTR_STATUS_ubits_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_ubits_intr_st 0x00100000 |
| #define BA_HDRX_INTR_STATUS_vsi_stop_intr_st 0x01AA |
| #define B16HDRX_INTR_STATUS_vsi_stop_intr_st 0x01AA |
| #define LSb32HDRX_INTR_STATUS_vsi_stop_intr_st 21 |
| #define LSb16HDRX_INTR_STATUS_vsi_stop_intr_st 5 |
| #define bHDRX_INTR_STATUS_vsi_stop_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_vsi_stop_intr_st 0x00200000 |
| #define BA_HDRX_INTR_STATUS_sync_det_intr_st 0x01AA |
| #define B16HDRX_INTR_STATUS_sync_det_intr_st 0x01AA |
| #define LSb32HDRX_INTR_STATUS_sync_det_intr_st 22 |
| #define LSb16HDRX_INTR_STATUS_sync_det_intr_st 6 |
| #define bHDRX_INTR_STATUS_sync_det_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_sync_det_intr_st 0x00400000 |
| #define BA_HDRX_INTR_STATUS_vres_chg_intr_st 0x01AA |
| #define B16HDRX_INTR_STATUS_vres_chg_intr_st 0x01AA |
| #define LSb32HDRX_INTR_STATUS_vres_chg_intr_st 23 |
| #define LSb16HDRX_INTR_STATUS_vres_chg_intr_st 7 |
| #define bHDRX_INTR_STATUS_vres_chg_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_vres_chg_intr_st 0x00800000 |
| #define BA_HDRX_INTR_STATUS_hres_chg_intr_st 0x01AB |
| #define B16HDRX_INTR_STATUS_hres_chg_intr_st 0x01AA |
| #define LSb32HDRX_INTR_STATUS_hres_chg_intr_st 24 |
| #define LSb16HDRX_INTR_STATUS_hres_chg_intr_st 8 |
| #define bHDRX_INTR_STATUS_hres_chg_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_hres_chg_intr_st 0x01000000 |
| #define BA_HDRX_INTR_STATUS_ced_cnt_update_intr_st 0x01AB |
| #define B16HDRX_INTR_STATUS_ced_cnt_update_intr_st 0x01AA |
| #define LSb32HDRX_INTR_STATUS_ced_cnt_update_intr_st 25 |
| #define LSb16HDRX_INTR_STATUS_ced_cnt_update_intr_st 9 |
| #define bHDRX_INTR_STATUS_ced_cnt_update_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_ced_cnt_update_intr_st 0x02000000 |
| #define BA_HDRX_INTR_STATUS_unplug_intr_st 0x01AB |
| #define B16HDRX_INTR_STATUS_unplug_intr_st 0x01AA |
| #define LSb32HDRX_INTR_STATUS_unplug_intr_st 26 |
| #define LSb16HDRX_INTR_STATUS_unplug_intr_st 10 |
| #define bHDRX_INTR_STATUS_unplug_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_unplug_intr_st 0x04000000 |
| #define BA_HDRX_INTR_STATUS_clk_det_intr_en 0x01AB |
| #define B16HDRX_INTR_STATUS_clk_det_intr_en 0x01AA |
| #define LSb32HDRX_INTR_STATUS_clk_det_intr_en 27 |
| #define LSb16HDRX_INTR_STATUS_clk_det_intr_en 11 |
| #define bHDRX_INTR_STATUS_clk_det_intr_en 1 |
| #define MSK32HDRX_INTR_STATUS_clk_det_intr_en 0x08000000 |
| #define BA_HDRX_INTR_STATUS_edid_intr_en 0x01AB |
| #define B16HDRX_INTR_STATUS_edid_intr_en 0x01AA |
| #define LSb32HDRX_INTR_STATUS_edid_intr_en 28 |
| #define LSb16HDRX_INTR_STATUS_edid_intr_en 12 |
| #define bHDRX_INTR_STATUS_edid_intr_en 1 |
| #define MSK32HDRX_INTR_STATUS_edid_intr_en 0x10000000 |
| #define BA_HDRX_INTR_STATUS_tmds_bit_clk_ratio_intr_st 0x01AB |
| #define B16HDRX_INTR_STATUS_tmds_bit_clk_ratio_intr_st 0x01AA |
| #define LSb32HDRX_INTR_STATUS_tmds_bit_clk_ratio_intr_st 29 |
| #define LSb16HDRX_INTR_STATUS_tmds_bit_clk_ratio_intr_st 13 |
| #define bHDRX_INTR_STATUS_tmds_bit_clk_ratio_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_tmds_bit_clk_ratio_intr_st 0x20000000 |
| #define BA_HDRX_INTR_STATUS_scrambler_en_intr_st 0x01AB |
| #define B16HDRX_INTR_STATUS_scrambler_en_intr_st 0x01AA |
| #define LSb32HDRX_INTR_STATUS_scrambler_en_intr_st 30 |
| #define LSb16HDRX_INTR_STATUS_scrambler_en_intr_st 14 |
| #define bHDRX_INTR_STATUS_scrambler_en_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_scrambler_en_intr_st 0x40000000 |
| #define BA_HDRX_INTR_STATUS_rr_enable_intr_st 0x01AB |
| #define B16HDRX_INTR_STATUS_rr_enable_intr_st 0x01AA |
| #define LSb32HDRX_INTR_STATUS_rr_enable_intr_st 31 |
| #define LSb16HDRX_INTR_STATUS_rr_enable_intr_st 15 |
| #define bHDRX_INTR_STATUS_rr_enable_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_rr_enable_intr_st 0x80000000 |
| #define RA_HDRX_INTR_STATUS1 0x01AC |
| #define BA_HDRX_INTR_STATUS_wr_mssg_started_intr_st 0x01AC |
| #define B16HDRX_INTR_STATUS_wr_mssg_started_intr_st 0x01AC |
| #define LSb32HDRX_INTR_STATUS_wr_mssg_started_intr_st 0 |
| #define LSb16HDRX_INTR_STATUS_wr_mssg_started_intr_st 0 |
| #define bHDRX_INTR_STATUS_wr_mssg_started_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_wr_mssg_started_intr_st 0x00000001 |
| #define BA_HDRX_INTR_STATUS_wr_mssg_done_intr_st 0x01AC |
| #define B16HDRX_INTR_STATUS_wr_mssg_done_intr_st 0x01AC |
| #define LSb32HDRX_INTR_STATUS_wr_mssg_done_intr_st 1 |
| #define LSb16HDRX_INTR_STATUS_wr_mssg_done_intr_st 1 |
| #define bHDRX_INTR_STATUS_wr_mssg_done_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_wr_mssg_done_intr_st 0x00000002 |
| #define BA_HDRX_INTR_STATUS_read_message_done_intr_st 0x01AC |
| #define B16HDRX_INTR_STATUS_read_message_done_intr_st 0x01AC |
| #define LSb32HDRX_INTR_STATUS_read_message_done_intr_st 2 |
| #define LSb16HDRX_INTR_STATUS_read_message_done_intr_st 2 |
| #define bHDRX_INTR_STATUS_read_message_done_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_read_message_done_intr_st 0x00000004 |
| #define BA_HDRX_INTR_STATUS_read_message_fail_intr_st 0x01AC |
| #define B16HDRX_INTR_STATUS_read_message_fail_intr_st 0x01AC |
| #define LSb32HDRX_INTR_STATUS_read_message_fail_intr_st 3 |
| #define LSb16HDRX_INTR_STATUS_read_message_fail_intr_st 3 |
| #define bHDRX_INTR_STATUS_read_message_fail_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_read_message_fail_intr_st 0x00000008 |
| #define BA_HDRX_INTR_STATUS_hmac_sm_rdy_intr_st 0x01AC |
| #define B16HDRX_INTR_STATUS_hmac_sm_rdy_intr_st 0x01AC |
| #define LSb32HDRX_INTR_STATUS_hmac_sm_rdy_intr_st 4 |
| #define LSb16HDRX_INTR_STATUS_hmac_sm_rdy_intr_st 4 |
| #define bHDRX_INTR_STATUS_hmac_sm_rdy_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_hmac_sm_rdy_intr_st 0x00000010 |
| #define BA_HDRX_INTR_STATUS_hmac_hash_done_intr_st 0x01AC |
| #define B16HDRX_INTR_STATUS_hmac_hash_done_intr_st 0x01AC |
| #define LSb32HDRX_INTR_STATUS_hmac_hash_done_intr_st 5 |
| #define LSb16HDRX_INTR_STATUS_hmac_hash_done_intr_st 5 |
| #define bHDRX_INTR_STATUS_hmac_hash_done_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_hmac_hash_done_intr_st 0x00000020 |
| #define BA_HDRX_INTR_STATUS_phy_prt_en_intr_st 0x01AC |
| #define B16HDRX_INTR_STATUS_phy_prt_en_intr_st 0x01AC |
| #define LSb32HDRX_INTR_STATUS_phy_prt_en_intr_st 6 |
| #define LSb16HDRX_INTR_STATUS_phy_prt_en_intr_st 6 |
| #define bHDRX_INTR_STATUS_phy_prt_en_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_phy_prt_en_intr_st 0x00000040 |
| #define BA_HDRX_INTR_STATUS_drm_info_intr_st 0x01AC |
| #define B16HDRX_INTR_STATUS_drm_info_intr_st 0x01AC |
| #define LSb32HDRX_INTR_STATUS_drm_info_intr_st 7 |
| #define LSb16HDRX_INTR_STATUS_drm_info_intr_st 7 |
| #define bHDRX_INTR_STATUS_drm_info_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_drm_info_intr_st 0x00000080 |
| #define BA_HDRX_INTR_STATUS_aud_fifo_over_flow_intr_st 0x01AD |
| #define B16HDRX_INTR_STATUS_aud_fifo_over_flow_intr_st 0x01AC |
| #define LSb32HDRX_INTR_STATUS_aud_fifo_over_flow_intr_st 8 |
| #define LSb16HDRX_INTR_STATUS_aud_fifo_over_flow_intr_st 8 |
| #define bHDRX_INTR_STATUS_aud_fifo_over_flow_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_aud_fifo_over_flow_intr_st 0x00000100 |
| #define BA_HDRX_INTR_STATUS_aud_fifo_under_flow_intr_st 0x01AD |
| #define B16HDRX_INTR_STATUS_aud_fifo_under_flow_intr_st 0x01AC |
| #define LSb32HDRX_INTR_STATUS_aud_fifo_under_flow_intr_st 9 |
| #define LSb16HDRX_INTR_STATUS_aud_fifo_under_flow_intr_st 9 |
| #define bHDRX_INTR_STATUS_aud_fifo_under_flow_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_aud_fifo_under_flow_intr_st 0x00000200 |
| #define BA_HDRX_INTR_STATUS_phy_pll_lock_intr_st 0x01AD |
| #define B16HDRX_INTR_STATUS_phy_pll_lock_intr_st 0x01AC |
| #define LSb32HDRX_INTR_STATUS_phy_pll_lock_intr_st 10 |
| #define LSb16HDRX_INTR_STATUS_phy_pll_lock_intr_st 10 |
| #define bHDRX_INTR_STATUS_phy_pll_lock_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_phy_pll_lock_intr_st 0x00000400 |
| #define RA_HDRX_INTR_STATUS_RAW 0x01B0 |
| #define BA_HDRX_INTR_STATUS_RAW_acr_n_intr_st 0x01B0 |
| #define B16HDRX_INTR_STATUS_RAW_acr_n_intr_st 0x01B0 |
| #define LSb32HDRX_INTR_STATUS_RAW_acr_n_intr_st 0 |
| #define LSb16HDRX_INTR_STATUS_RAW_acr_n_intr_st 0 |
| #define bHDRX_INTR_STATUS_RAW_acr_n_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_acr_n_intr_st 0x00000001 |
| #define BA_HDRX_INTR_STATUS_RAW_acr_cts_intr_st 0x01B0 |
| #define B16HDRX_INTR_STATUS_RAW_acr_cts_intr_st 0x01B0 |
| #define LSb32HDRX_INTR_STATUS_RAW_acr_cts_intr_st 1 |
| #define LSb16HDRX_INTR_STATUS_RAW_acr_cts_intr_st 1 |
| #define bHDRX_INTR_STATUS_RAW_acr_cts_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_acr_cts_intr_st 0x00000002 |
| #define BA_HDRX_INTR_STATUS_RAW_gcp_avmute_intr_st 0x01B0 |
| #define B16HDRX_INTR_STATUS_RAW_gcp_avmute_intr_st 0x01B0 |
| #define LSb32HDRX_INTR_STATUS_RAW_gcp_avmute_intr_st 2 |
| #define LSb16HDRX_INTR_STATUS_RAW_gcp_avmute_intr_st 2 |
| #define bHDRX_INTR_STATUS_RAW_gcp_avmute_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_gcp_avmute_intr_st 0x00000004 |
| #define BA_HDRX_INTR_STATUS_RAW_gcp_cd_intr_st 0x01B0 |
| #define B16HDRX_INTR_STATUS_RAW_gcp_cd_intr_st 0x01B0 |
| #define LSb32HDRX_INTR_STATUS_RAW_gcp_cd_intr_st 3 |
| #define LSb16HDRX_INTR_STATUS_RAW_gcp_cd_intr_st 3 |
| #define bHDRX_INTR_STATUS_RAW_gcp_cd_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_gcp_cd_intr_st 0x00000008 |
| #define BA_HDRX_INTR_STATUS_RAW_gcp_dp_intr_st 0x01B0 |
| #define B16HDRX_INTR_STATUS_RAW_gcp_dp_intr_st 0x01B0 |
| #define LSb32HDRX_INTR_STATUS_RAW_gcp_dp_intr_st 4 |
| #define LSb16HDRX_INTR_STATUS_RAW_gcp_dp_intr_st 4 |
| #define bHDRX_INTR_STATUS_RAW_gcp_dp_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_gcp_dp_intr_st 0x00000010 |
| #define BA_HDRX_INTR_STATUS_RAW_acp_pkt_intr_st 0x01B0 |
| #define B16HDRX_INTR_STATUS_RAW_acp_pkt_intr_st 0x01B0 |
| #define LSb32HDRX_INTR_STATUS_RAW_acp_pkt_intr_st 5 |
| #define LSb16HDRX_INTR_STATUS_RAW_acp_pkt_intr_st 5 |
| #define bHDRX_INTR_STATUS_RAW_acp_pkt_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_acp_pkt_intr_st 0x00000020 |
| #define BA_HDRX_INTR_STATUS_RAW_isrc1_pkt_intr_st 0x01B0 |
| #define B16HDRX_INTR_STATUS_RAW_isrc1_pkt_intr_st 0x01B0 |
| #define LSb32HDRX_INTR_STATUS_RAW_isrc1_pkt_intr_st 6 |
| #define LSb16HDRX_INTR_STATUS_RAW_isrc1_pkt_intr_st 6 |
| #define bHDRX_INTR_STATUS_RAW_isrc1_pkt_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_isrc1_pkt_intr_st 0x00000040 |
| #define BA_HDRX_INTR_STATUS_RAW_isrc2_pkt_intr_st 0x01B0 |
| #define B16HDRX_INTR_STATUS_RAW_isrc2_pkt_intr_st 0x01B0 |
| #define LSb32HDRX_INTR_STATUS_RAW_isrc2_pkt_intr_st 7 |
| #define LSb16HDRX_INTR_STATUS_RAW_isrc2_pkt_intr_st 7 |
| #define bHDRX_INTR_STATUS_RAW_isrc2_pkt_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_isrc2_pkt_intr_st 0x00000080 |
| #define BA_HDRX_INTR_STATUS_RAW_gmd_pkt_intr_st 0x01B1 |
| #define B16HDRX_INTR_STATUS_RAW_gmd_pkt_intr_st 0x01B0 |
| #define LSb32HDRX_INTR_STATUS_RAW_gmd_pkt_intr_st 8 |
| #define LSb16HDRX_INTR_STATUS_RAW_gmd_pkt_intr_st 8 |
| #define bHDRX_INTR_STATUS_RAW_gmd_pkt_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_gmd_pkt_intr_st 0x00000100 |
| #define BA_HDRX_INTR_STATUS_RAW_amd_pkt_intr_st 0x01B1 |
| #define B16HDRX_INTR_STATUS_RAW_amd_pkt_intr_st 0x01B0 |
| #define LSb32HDRX_INTR_STATUS_RAW_amd_pkt_intr_st 9 |
| #define LSb16HDRX_INTR_STATUS_RAW_amd_pkt_intr_st 9 |
| #define bHDRX_INTR_STATUS_RAW_amd_pkt_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_amd_pkt_intr_st 0x00000200 |
| #define BA_HDRX_INTR_STATUS_RAW_ven_spec_pkt_intr_st 0x01B1 |
| #define B16HDRX_INTR_STATUS_RAW_ven_spec_pkt_intr_st 0x01B0 |
| #define LSb32HDRX_INTR_STATUS_RAW_ven_spec_pkt_intr_st 10 |
| #define LSb16HDRX_INTR_STATUS_RAW_ven_spec_pkt_intr_st 10 |
| #define bHDRX_INTR_STATUS_RAW_ven_spec_pkt_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_ven_spec_pkt_intr_st 0x00000400 |
| #define BA_HDRX_INTR_STATUS_RAW_avi_info_pkt_intr_st 0x01B1 |
| #define B16HDRX_INTR_STATUS_RAW_avi_info_pkt_intr_st 0x01B0 |
| #define LSb32HDRX_INTR_STATUS_RAW_avi_info_pkt_intr_st 11 |
| #define LSb16HDRX_INTR_STATUS_RAW_avi_info_pkt_intr_st 11 |
| #define bHDRX_INTR_STATUS_RAW_avi_info_pkt_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_avi_info_pkt_intr_st 0x00000800 |
| #define BA_HDRX_INTR_STATUS_RAW_spd_pkt_intr_st 0x01B1 |
| #define B16HDRX_INTR_STATUS_RAW_spd_pkt_intr_st 0x01B0 |
| #define LSb32HDRX_INTR_STATUS_RAW_spd_pkt_intr_st 12 |
| #define LSb16HDRX_INTR_STATUS_RAW_spd_pkt_intr_st 12 |
| #define bHDRX_INTR_STATUS_RAW_spd_pkt_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_spd_pkt_intr_st 0x00001000 |
| #define BA_HDRX_INTR_STATUS_RAW_aud_info_pkt_intr_st 0x01B1 |
| #define B16HDRX_INTR_STATUS_RAW_aud_info_pkt_intr_st 0x01B0 |
| #define LSb32HDRX_INTR_STATUS_RAW_aud_info_pkt_intr_st 13 |
| #define LSb16HDRX_INTR_STATUS_RAW_aud_info_pkt_intr_st 13 |
| #define bHDRX_INTR_STATUS_RAW_aud_info_pkt_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_aud_info_pkt_intr_st 0x00002000 |
| #define BA_HDRX_INTR_STATUS_RAW_mpeg_info_pkt_intr_st 0x01B1 |
| #define B16HDRX_INTR_STATUS_RAW_mpeg_info_pkt_intr_st 0x01B0 |
| #define LSb32HDRX_INTR_STATUS_RAW_mpeg_info_pkt_intr_st 14 |
| #define LSb16HDRX_INTR_STATUS_RAW_mpeg_info_pkt_intr_st 14 |
| #define bHDRX_INTR_STATUS_RAW_mpeg_info_pkt_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_mpeg_info_pkt_intr_st 0x00004000 |
| #define BA_HDRX_INTR_STATUS_RAW_chsts_intr_st 0x01B1 |
| #define B16HDRX_INTR_STATUS_RAW_chsts_intr_st 0x01B0 |
| #define LSb32HDRX_INTR_STATUS_RAW_chsts_intr_st 15 |
| #define LSb16HDRX_INTR_STATUS_RAW_chsts_intr_st 15 |
| #define bHDRX_INTR_STATUS_RAW_chsts_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_chsts_intr_st 0x00008000 |
| #define BA_HDRX_INTR_STATUS_RAW_tmds_mode_intr_st 0x01B2 |
| #define B16HDRX_INTR_STATUS_RAW_tmds_mode_intr_st 0x01B2 |
| #define LSb32HDRX_INTR_STATUS_RAW_tmds_mode_intr_st 16 |
| #define LSb16HDRX_INTR_STATUS_RAW_tmds_mode_intr_st 0 |
| #define bHDRX_INTR_STATUS_RAW_tmds_mode_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_tmds_mode_intr_st 0x00010000 |
| #define BA_HDRX_INTR_STATUS_RAW_auth_start_intr_st 0x01B2 |
| #define B16HDRX_INTR_STATUS_RAW_auth_start_intr_st 0x01B2 |
| #define LSb32HDRX_INTR_STATUS_RAW_auth_start_intr_st 17 |
| #define LSb16HDRX_INTR_STATUS_RAW_auth_start_intr_st 1 |
| #define bHDRX_INTR_STATUS_RAW_auth_start_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_auth_start_intr_st 0x00020000 |
| #define BA_HDRX_INTR_STATUS_RAW_auth_cmplt_intr_st 0x01B2 |
| #define B16HDRX_INTR_STATUS_RAW_auth_cmplt_intr_st 0x01B2 |
| #define LSb32HDRX_INTR_STATUS_RAW_auth_cmplt_intr_st 18 |
| #define LSb16HDRX_INTR_STATUS_RAW_auth_cmplt_intr_st 2 |
| #define bHDRX_INTR_STATUS_RAW_auth_cmplt_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_auth_cmplt_intr_st 0x00040000 |
| #define BA_HDRX_INTR_STATUS_RAW_vsync_intr_st 0x01B2 |
| #define B16HDRX_INTR_STATUS_RAW_vsync_intr_st 0x01B2 |
| #define LSb32HDRX_INTR_STATUS_RAW_vsync_intr_st 19 |
| #define LSb16HDRX_INTR_STATUS_RAW_vsync_intr_st 3 |
| #define bHDRX_INTR_STATUS_RAW_vsync_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_vsync_intr_st 0x00080000 |
| #define BA_HDRX_INTR_STATUS_RAW_ubits_intr_st 0x01B2 |
| #define B16HDRX_INTR_STATUS_RAW_ubits_intr_st 0x01B2 |
| #define LSb32HDRX_INTR_STATUS_RAW_ubits_intr_st 20 |
| #define LSb16HDRX_INTR_STATUS_RAW_ubits_intr_st 4 |
| #define bHDRX_INTR_STATUS_RAW_ubits_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_ubits_intr_st 0x00100000 |
| #define BA_HDRX_INTR_STATUS_RAW_vsi_stop_intr_st 0x01B2 |
| #define B16HDRX_INTR_STATUS_RAW_vsi_stop_intr_st 0x01B2 |
| #define LSb32HDRX_INTR_STATUS_RAW_vsi_stop_intr_st 21 |
| #define LSb16HDRX_INTR_STATUS_RAW_vsi_stop_intr_st 5 |
| #define bHDRX_INTR_STATUS_RAW_vsi_stop_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_vsi_stop_intr_st 0x00200000 |
| #define BA_HDRX_INTR_STATUS_RAW_sync_det_intr_st 0x01B2 |
| #define B16HDRX_INTR_STATUS_RAW_sync_det_intr_st 0x01B2 |
| #define LSb32HDRX_INTR_STATUS_RAW_sync_det_intr_st 22 |
| #define LSb16HDRX_INTR_STATUS_RAW_sync_det_intr_st 6 |
| #define bHDRX_INTR_STATUS_RAW_sync_det_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_sync_det_intr_st 0x00400000 |
| #define BA_HDRX_INTR_STATUS_RAW_vres_chg_intr_st 0x01B2 |
| #define B16HDRX_INTR_STATUS_RAW_vres_chg_intr_st 0x01B2 |
| #define LSb32HDRX_INTR_STATUS_RAW_vres_chg_intr_st 23 |
| #define LSb16HDRX_INTR_STATUS_RAW_vres_chg_intr_st 7 |
| #define bHDRX_INTR_STATUS_RAW_vres_chg_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_vres_chg_intr_st 0x00800000 |
| #define BA_HDRX_INTR_STATUS_RAW_hres_chg_intr_st 0x01B3 |
| #define B16HDRX_INTR_STATUS_RAW_hres_chg_intr_st 0x01B2 |
| #define LSb32HDRX_INTR_STATUS_RAW_hres_chg_intr_st 24 |
| #define LSb16HDRX_INTR_STATUS_RAW_hres_chg_intr_st 8 |
| #define bHDRX_INTR_STATUS_RAW_hres_chg_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_hres_chg_intr_st 0x01000000 |
| #define BA_HDRX_INTR_STATUS_RAW_ced_cnt_update_intr_st 0x01B3 |
| #define B16HDRX_INTR_STATUS_RAW_ced_cnt_update_intr_st 0x01B2 |
| #define LSb32HDRX_INTR_STATUS_RAW_ced_cnt_update_intr_st 25 |
| #define LSb16HDRX_INTR_STATUS_RAW_ced_cnt_update_intr_st 9 |
| #define bHDRX_INTR_STATUS_RAW_ced_cnt_update_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_ced_cnt_update_intr_st 0x02000000 |
| #define BA_HDRX_INTR_STATUS_RAW_unplug_intr_st 0x01B3 |
| #define B16HDRX_INTR_STATUS_RAW_unplug_intr_st 0x01B2 |
| #define LSb32HDRX_INTR_STATUS_RAW_unplug_intr_st 26 |
| #define LSb16HDRX_INTR_STATUS_RAW_unplug_intr_st 10 |
| #define bHDRX_INTR_STATUS_RAW_unplug_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_unplug_intr_st 0x04000000 |
| #define BA_HDRX_INTR_STATUS_RAW_clk_det_intr_en 0x01B3 |
| #define B16HDRX_INTR_STATUS_RAW_clk_det_intr_en 0x01B2 |
| #define LSb32HDRX_INTR_STATUS_RAW_clk_det_intr_en 27 |
| #define LSb16HDRX_INTR_STATUS_RAW_clk_det_intr_en 11 |
| #define bHDRX_INTR_STATUS_RAW_clk_det_intr_en 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_clk_det_intr_en 0x08000000 |
| #define BA_HDRX_INTR_STATUS_RAW_edid_intr_en 0x01B3 |
| #define B16HDRX_INTR_STATUS_RAW_edid_intr_en 0x01B2 |
| #define LSb32HDRX_INTR_STATUS_RAW_edid_intr_en 28 |
| #define LSb16HDRX_INTR_STATUS_RAW_edid_intr_en 12 |
| #define bHDRX_INTR_STATUS_RAW_edid_intr_en 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_edid_intr_en 0x10000000 |
| #define BA_HDRX_INTR_STATUS_RAW_tmds_bit_clk_ratio_intr_st 0x01B3 |
| #define B16HDRX_INTR_STATUS_RAW_tmds_bit_clk_ratio_intr_st 0x01B2 |
| #define LSb32HDRX_INTR_STATUS_RAW_tmds_bit_clk_ratio_intr_st 29 |
| #define LSb16HDRX_INTR_STATUS_RAW_tmds_bit_clk_ratio_intr_st 13 |
| #define bHDRX_INTR_STATUS_RAW_tmds_bit_clk_ratio_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_tmds_bit_clk_ratio_intr_st 0x20000000 |
| #define BA_HDRX_INTR_STATUS_RAW_scrambler_en_intr_st 0x01B3 |
| #define B16HDRX_INTR_STATUS_RAW_scrambler_en_intr_st 0x01B2 |
| #define LSb32HDRX_INTR_STATUS_RAW_scrambler_en_intr_st 30 |
| #define LSb16HDRX_INTR_STATUS_RAW_scrambler_en_intr_st 14 |
| #define bHDRX_INTR_STATUS_RAW_scrambler_en_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_scrambler_en_intr_st 0x40000000 |
| #define BA_HDRX_INTR_STATUS_RAW_rr_enable_intr_st 0x01B3 |
| #define B16HDRX_INTR_STATUS_RAW_rr_enable_intr_st 0x01B2 |
| #define LSb32HDRX_INTR_STATUS_RAW_rr_enable_intr_st 31 |
| #define LSb16HDRX_INTR_STATUS_RAW_rr_enable_intr_st 15 |
| #define bHDRX_INTR_STATUS_RAW_rr_enable_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_rr_enable_intr_st 0x80000000 |
| #define RA_HDRX_INTR_STATUS_RAW1 0x01B4 |
| #define BA_HDRX_INTR_STATUS_RAW_wr_mssg_started_intr_st 0x01B4 |
| #define B16HDRX_INTR_STATUS_RAW_wr_mssg_started_intr_st 0x01B4 |
| #define LSb32HDRX_INTR_STATUS_RAW_wr_mssg_started_intr_st 0 |
| #define LSb16HDRX_INTR_STATUS_RAW_wr_mssg_started_intr_st 0 |
| #define bHDRX_INTR_STATUS_RAW_wr_mssg_started_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_wr_mssg_started_intr_st 0x00000001 |
| #define BA_HDRX_INTR_STATUS_RAW_wr_mssg_done_intr_st 0x01B4 |
| #define B16HDRX_INTR_STATUS_RAW_wr_mssg_done_intr_st 0x01B4 |
| #define LSb32HDRX_INTR_STATUS_RAW_wr_mssg_done_intr_st 1 |
| #define LSb16HDRX_INTR_STATUS_RAW_wr_mssg_done_intr_st 1 |
| #define bHDRX_INTR_STATUS_RAW_wr_mssg_done_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_wr_mssg_done_intr_st 0x00000002 |
| #define BA_HDRX_INTR_STATUS_RAW_read_message_done_intr_st 0x01B4 |
| #define B16HDRX_INTR_STATUS_RAW_read_message_done_intr_st 0x01B4 |
| #define LSb32HDRX_INTR_STATUS_RAW_read_message_done_intr_st 2 |
| #define LSb16HDRX_INTR_STATUS_RAW_read_message_done_intr_st 2 |
| #define bHDRX_INTR_STATUS_RAW_read_message_done_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_read_message_done_intr_st 0x00000004 |
| #define BA_HDRX_INTR_STATUS_RAW_read_message_fail_intr_st 0x01B4 |
| #define B16HDRX_INTR_STATUS_RAW_read_message_fail_intr_st 0x01B4 |
| #define LSb32HDRX_INTR_STATUS_RAW_read_message_fail_intr_st 3 |
| #define LSb16HDRX_INTR_STATUS_RAW_read_message_fail_intr_st 3 |
| #define bHDRX_INTR_STATUS_RAW_read_message_fail_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_read_message_fail_intr_st 0x00000008 |
| #define BA_HDRX_INTR_STATUS_RAW_hmac_sm_rdy_intr_st 0x01B4 |
| #define B16HDRX_INTR_STATUS_RAW_hmac_sm_rdy_intr_st 0x01B4 |
| #define LSb32HDRX_INTR_STATUS_RAW_hmac_sm_rdy_intr_st 4 |
| #define LSb16HDRX_INTR_STATUS_RAW_hmac_sm_rdy_intr_st 4 |
| #define bHDRX_INTR_STATUS_RAW_hmac_sm_rdy_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_hmac_sm_rdy_intr_st 0x00000010 |
| #define BA_HDRX_INTR_STATUS_RAW_hmac_hash_done_intr_st 0x01B4 |
| #define B16HDRX_INTR_STATUS_RAW_hmac_hash_done_intr_st 0x01B4 |
| #define LSb32HDRX_INTR_STATUS_RAW_hmac_hash_done_intr_st 5 |
| #define LSb16HDRX_INTR_STATUS_RAW_hmac_hash_done_intr_st 5 |
| #define bHDRX_INTR_STATUS_RAW_hmac_hash_done_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_hmac_hash_done_intr_st 0x00000020 |
| #define BA_HDRX_INTR_STATUS_RAW_phy_prt_en_intr_st 0x01B4 |
| #define B16HDRX_INTR_STATUS_RAW_phy_prt_en_intr_st 0x01B4 |
| #define LSb32HDRX_INTR_STATUS_RAW_phy_prt_en_intr_st 6 |
| #define LSb16HDRX_INTR_STATUS_RAW_phy_prt_en_intr_st 6 |
| #define bHDRX_INTR_STATUS_RAW_phy_prt_en_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_phy_prt_en_intr_st 0x00000040 |
| #define BA_HDRX_INTR_STATUS_RAW_drm_info_intr_st 0x01B4 |
| #define B16HDRX_INTR_STATUS_RAW_drm_info_intr_st 0x01B4 |
| #define LSb32HDRX_INTR_STATUS_RAW_drm_info_intr_st 7 |
| #define LSb16HDRX_INTR_STATUS_RAW_drm_info_intr_st 7 |
| #define bHDRX_INTR_STATUS_RAW_drm_info_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_drm_info_intr_st 0x00000080 |
| #define BA_HDRX_INTR_STATUS_RAW_aud_fifo_over_flow_intr_st 0x01B5 |
| #define B16HDRX_INTR_STATUS_RAW_aud_fifo_over_flow_intr_st 0x01B4 |
| #define LSb32HDRX_INTR_STATUS_RAW_aud_fifo_over_flow_intr_st 8 |
| #define LSb16HDRX_INTR_STATUS_RAW_aud_fifo_over_flow_intr_st 8 |
| #define bHDRX_INTR_STATUS_RAW_aud_fifo_over_flow_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_aud_fifo_over_flow_intr_st 0x00000100 |
| #define BA_HDRX_INTR_STATUS_RAW_aud_fifo_under_flow_intr_st 0x01B5 |
| #define B16HDRX_INTR_STATUS_RAW_aud_fifo_under_flow_intr_st 0x01B4 |
| #define LSb32HDRX_INTR_STATUS_RAW_aud_fifo_under_flow_intr_st 9 |
| #define LSb16HDRX_INTR_STATUS_RAW_aud_fifo_under_flow_intr_st 9 |
| #define bHDRX_INTR_STATUS_RAW_aud_fifo_under_flow_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_aud_fifo_under_flow_intr_st 0x00000200 |
| #define BA_HDRX_INTR_STATUS_RAW_phy_pll_lock_intr_st 0x01B5 |
| #define B16HDRX_INTR_STATUS_RAW_phy_pll_lock_intr_st 0x01B4 |
| #define LSb32HDRX_INTR_STATUS_RAW_phy_pll_lock_intr_st 10 |
| #define LSb16HDRX_INTR_STATUS_RAW_phy_pll_lock_intr_st 10 |
| #define bHDRX_INTR_STATUS_RAW_phy_pll_lock_intr_st 1 |
| #define MSK32HDRX_INTR_STATUS_RAW_phy_pll_lock_intr_st 0x00000400 |
| #define RA_HDRX_INTR_CLR 0x01B8 |
| #define BA_HDRX_INTR_CLR_acr_n_intr_clr 0x01B8 |
| #define B16HDRX_INTR_CLR_acr_n_intr_clr 0x01B8 |
| #define LSb32HDRX_INTR_CLR_acr_n_intr_clr 0 |
| #define LSb16HDRX_INTR_CLR_acr_n_intr_clr 0 |
| #define bHDRX_INTR_CLR_acr_n_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_acr_n_intr_clr 0x00000001 |
| #define BA_HDRX_INTR_CLR_acr_cts_intr_clr 0x01B8 |
| #define B16HDRX_INTR_CLR_acr_cts_intr_clr 0x01B8 |
| #define LSb32HDRX_INTR_CLR_acr_cts_intr_clr 1 |
| #define LSb16HDRX_INTR_CLR_acr_cts_intr_clr 1 |
| #define bHDRX_INTR_CLR_acr_cts_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_acr_cts_intr_clr 0x00000002 |
| #define BA_HDRX_INTR_CLR_gcp_avmute_intr_clr 0x01B8 |
| #define B16HDRX_INTR_CLR_gcp_avmute_intr_clr 0x01B8 |
| #define LSb32HDRX_INTR_CLR_gcp_avmute_intr_clr 2 |
| #define LSb16HDRX_INTR_CLR_gcp_avmute_intr_clr 2 |
| #define bHDRX_INTR_CLR_gcp_avmute_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_gcp_avmute_intr_clr 0x00000004 |
| #define BA_HDRX_INTR_CLR_gcp_cd_intr_clr 0x01B8 |
| #define B16HDRX_INTR_CLR_gcp_cd_intr_clr 0x01B8 |
| #define LSb32HDRX_INTR_CLR_gcp_cd_intr_clr 3 |
| #define LSb16HDRX_INTR_CLR_gcp_cd_intr_clr 3 |
| #define bHDRX_INTR_CLR_gcp_cd_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_gcp_cd_intr_clr 0x00000008 |
| #define BA_HDRX_INTR_CLR_gcp_dp_intr_clr 0x01B8 |
| #define B16HDRX_INTR_CLR_gcp_dp_intr_clr 0x01B8 |
| #define LSb32HDRX_INTR_CLR_gcp_dp_intr_clr 4 |
| #define LSb16HDRX_INTR_CLR_gcp_dp_intr_clr 4 |
| #define bHDRX_INTR_CLR_gcp_dp_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_gcp_dp_intr_clr 0x00000010 |
| #define BA_HDRX_INTR_CLR_acp_pkt_intr_clr 0x01B8 |
| #define B16HDRX_INTR_CLR_acp_pkt_intr_clr 0x01B8 |
| #define LSb32HDRX_INTR_CLR_acp_pkt_intr_clr 5 |
| #define LSb16HDRX_INTR_CLR_acp_pkt_intr_clr 5 |
| #define bHDRX_INTR_CLR_acp_pkt_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_acp_pkt_intr_clr 0x00000020 |
| #define BA_HDRX_INTR_CLR_isrc1_pkt_intr_clr 0x01B8 |
| #define B16HDRX_INTR_CLR_isrc1_pkt_intr_clr 0x01B8 |
| #define LSb32HDRX_INTR_CLR_isrc1_pkt_intr_clr 6 |
| #define LSb16HDRX_INTR_CLR_isrc1_pkt_intr_clr 6 |
| #define bHDRX_INTR_CLR_isrc1_pkt_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_isrc1_pkt_intr_clr 0x00000040 |
| #define BA_HDRX_INTR_CLR_isrc2_pkt_intr_clr 0x01B8 |
| #define B16HDRX_INTR_CLR_isrc2_pkt_intr_clr 0x01B8 |
| #define LSb32HDRX_INTR_CLR_isrc2_pkt_intr_clr 7 |
| #define LSb16HDRX_INTR_CLR_isrc2_pkt_intr_clr 7 |
| #define bHDRX_INTR_CLR_isrc2_pkt_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_isrc2_pkt_intr_clr 0x00000080 |
| #define BA_HDRX_INTR_CLR_gmd_pkt_intr_clr 0x01B9 |
| #define B16HDRX_INTR_CLR_gmd_pkt_intr_clr 0x01B8 |
| #define LSb32HDRX_INTR_CLR_gmd_pkt_intr_clr 8 |
| #define LSb16HDRX_INTR_CLR_gmd_pkt_intr_clr 8 |
| #define bHDRX_INTR_CLR_gmd_pkt_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_gmd_pkt_intr_clr 0x00000100 |
| #define BA_HDRX_INTR_CLR_amd_pkt_intr_clr 0x01B9 |
| #define B16HDRX_INTR_CLR_amd_pkt_intr_clr 0x01B8 |
| #define LSb32HDRX_INTR_CLR_amd_pkt_intr_clr 9 |
| #define LSb16HDRX_INTR_CLR_amd_pkt_intr_clr 9 |
| #define bHDRX_INTR_CLR_amd_pkt_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_amd_pkt_intr_clr 0x00000200 |
| #define BA_HDRX_INTR_CLR_ven_spec_pkt_intr_clr 0x01B9 |
| #define B16HDRX_INTR_CLR_ven_spec_pkt_intr_clr 0x01B8 |
| #define LSb32HDRX_INTR_CLR_ven_spec_pkt_intr_clr 10 |
| #define LSb16HDRX_INTR_CLR_ven_spec_pkt_intr_clr 10 |
| #define bHDRX_INTR_CLR_ven_spec_pkt_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_ven_spec_pkt_intr_clr 0x00000400 |
| #define BA_HDRX_INTR_CLR_avi_info_pkt_intr_clr 0x01B9 |
| #define B16HDRX_INTR_CLR_avi_info_pkt_intr_clr 0x01B8 |
| #define LSb32HDRX_INTR_CLR_avi_info_pkt_intr_clr 11 |
| #define LSb16HDRX_INTR_CLR_avi_info_pkt_intr_clr 11 |
| #define bHDRX_INTR_CLR_avi_info_pkt_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_avi_info_pkt_intr_clr 0x00000800 |
| #define BA_HDRX_INTR_CLR_spd_pkt_intr_clr 0x01B9 |
| #define B16HDRX_INTR_CLR_spd_pkt_intr_clr 0x01B8 |
| #define LSb32HDRX_INTR_CLR_spd_pkt_intr_clr 12 |
| #define LSb16HDRX_INTR_CLR_spd_pkt_intr_clr 12 |
| #define bHDRX_INTR_CLR_spd_pkt_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_spd_pkt_intr_clr 0x00001000 |
| #define BA_HDRX_INTR_CLR_aud_info_pkt_intr_clr 0x01B9 |
| #define B16HDRX_INTR_CLR_aud_info_pkt_intr_clr 0x01B8 |
| #define LSb32HDRX_INTR_CLR_aud_info_pkt_intr_clr 13 |
| #define LSb16HDRX_INTR_CLR_aud_info_pkt_intr_clr 13 |
| #define bHDRX_INTR_CLR_aud_info_pkt_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_aud_info_pkt_intr_clr 0x00002000 |
| #define BA_HDRX_INTR_CLR_mpeg_info_pkt_intr_clr 0x01B9 |
| #define B16HDRX_INTR_CLR_mpeg_info_pkt_intr_clr 0x01B8 |
| #define LSb32HDRX_INTR_CLR_mpeg_info_pkt_intr_clr 14 |
| #define LSb16HDRX_INTR_CLR_mpeg_info_pkt_intr_clr 14 |
| #define bHDRX_INTR_CLR_mpeg_info_pkt_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_mpeg_info_pkt_intr_clr 0x00004000 |
| #define BA_HDRX_INTR_CLR_chsts_intr_clr 0x01B9 |
| #define B16HDRX_INTR_CLR_chsts_intr_clr 0x01B8 |
| #define LSb32HDRX_INTR_CLR_chsts_intr_clr 15 |
| #define LSb16HDRX_INTR_CLR_chsts_intr_clr 15 |
| #define bHDRX_INTR_CLR_chsts_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_chsts_intr_clr 0x00008000 |
| #define BA_HDRX_INTR_CLR_tmds_mode_intr_clr 0x01BA |
| #define B16HDRX_INTR_CLR_tmds_mode_intr_clr 0x01BA |
| #define LSb32HDRX_INTR_CLR_tmds_mode_intr_clr 16 |
| #define LSb16HDRX_INTR_CLR_tmds_mode_intr_clr 0 |
| #define bHDRX_INTR_CLR_tmds_mode_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_tmds_mode_intr_clr 0x00010000 |
| #define BA_HDRX_INTR_CLR_auth_start_intr_clr 0x01BA |
| #define B16HDRX_INTR_CLR_auth_start_intr_clr 0x01BA |
| #define LSb32HDRX_INTR_CLR_auth_start_intr_clr 17 |
| #define LSb16HDRX_INTR_CLR_auth_start_intr_clr 1 |
| #define bHDRX_INTR_CLR_auth_start_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_auth_start_intr_clr 0x00020000 |
| #define BA_HDRX_INTR_CLR_auth_cmplt_intr_clr 0x01BA |
| #define B16HDRX_INTR_CLR_auth_cmplt_intr_clr 0x01BA |
| #define LSb32HDRX_INTR_CLR_auth_cmplt_intr_clr 18 |
| #define LSb16HDRX_INTR_CLR_auth_cmplt_intr_clr 2 |
| #define bHDRX_INTR_CLR_auth_cmplt_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_auth_cmplt_intr_clr 0x00040000 |
| #define BA_HDRX_INTR_CLR_vsync_intr_clr 0x01BA |
| #define B16HDRX_INTR_CLR_vsync_intr_clr 0x01BA |
| #define LSb32HDRX_INTR_CLR_vsync_intr_clr 19 |
| #define LSb16HDRX_INTR_CLR_vsync_intr_clr 3 |
| #define bHDRX_INTR_CLR_vsync_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_vsync_intr_clr 0x00080000 |
| #define BA_HDRX_INTR_CLR_ubits_intr_clr 0x01BA |
| #define B16HDRX_INTR_CLR_ubits_intr_clr 0x01BA |
| #define LSb32HDRX_INTR_CLR_ubits_intr_clr 20 |
| #define LSb16HDRX_INTR_CLR_ubits_intr_clr 4 |
| #define bHDRX_INTR_CLR_ubits_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_ubits_intr_clr 0x00100000 |
| #define BA_HDRX_INTR_CLR_vsi_stop_intr_clr 0x01BA |
| #define B16HDRX_INTR_CLR_vsi_stop_intr_clr 0x01BA |
| #define LSb32HDRX_INTR_CLR_vsi_stop_intr_clr 21 |
| #define LSb16HDRX_INTR_CLR_vsi_stop_intr_clr 5 |
| #define bHDRX_INTR_CLR_vsi_stop_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_vsi_stop_intr_clr 0x00200000 |
| #define BA_HDRX_INTR_CLR_sync_det_intr_clr 0x01BA |
| #define B16HDRX_INTR_CLR_sync_det_intr_clr 0x01BA |
| #define LSb32HDRX_INTR_CLR_sync_det_intr_clr 22 |
| #define LSb16HDRX_INTR_CLR_sync_det_intr_clr 6 |
| #define bHDRX_INTR_CLR_sync_det_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_sync_det_intr_clr 0x00400000 |
| #define BA_HDRX_INTR_CLR_vres_chg_intr_clr 0x01BA |
| #define B16HDRX_INTR_CLR_vres_chg_intr_clr 0x01BA |
| #define LSb32HDRX_INTR_CLR_vres_chg_intr_clr 23 |
| #define LSb16HDRX_INTR_CLR_vres_chg_intr_clr 7 |
| #define bHDRX_INTR_CLR_vres_chg_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_vres_chg_intr_clr 0x00800000 |
| #define BA_HDRX_INTR_CLR_hres_chg_intr_clr 0x01BB |
| #define B16HDRX_INTR_CLR_hres_chg_intr_clr 0x01BA |
| #define LSb32HDRX_INTR_CLR_hres_chg_intr_clr 24 |
| #define LSb16HDRX_INTR_CLR_hres_chg_intr_clr 8 |
| #define bHDRX_INTR_CLR_hres_chg_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_hres_chg_intr_clr 0x01000000 |
| #define BA_HDRX_INTR_CLR_ced_cnt_update_intr_clr 0x01BB |
| #define B16HDRX_INTR_CLR_ced_cnt_update_intr_clr 0x01BA |
| #define LSb32HDRX_INTR_CLR_ced_cnt_update_intr_clr 25 |
| #define LSb16HDRX_INTR_CLR_ced_cnt_update_intr_clr 9 |
| #define bHDRX_INTR_CLR_ced_cnt_update_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_ced_cnt_update_intr_clr 0x02000000 |
| #define BA_HDRX_INTR_CLR_unplug_intr_clr 0x01BB |
| #define B16HDRX_INTR_CLR_unplug_intr_clr 0x01BA |
| #define LSb32HDRX_INTR_CLR_unplug_intr_clr 26 |
| #define LSb16HDRX_INTR_CLR_unplug_intr_clr 10 |
| #define bHDRX_INTR_CLR_unplug_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_unplug_intr_clr 0x04000000 |
| #define BA_HDRX_INTR_CLR_clk_det_intr_clr 0x01BB |
| #define B16HDRX_INTR_CLR_clk_det_intr_clr 0x01BA |
| #define LSb32HDRX_INTR_CLR_clk_det_intr_clr 27 |
| #define LSb16HDRX_INTR_CLR_clk_det_intr_clr 11 |
| #define bHDRX_INTR_CLR_clk_det_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_clk_det_intr_clr 0x08000000 |
| #define BA_HDRX_INTR_CLR_edid_intr_clr 0x01BB |
| #define B16HDRX_INTR_CLR_edid_intr_clr 0x01BA |
| #define LSb32HDRX_INTR_CLR_edid_intr_clr 28 |
| #define LSb16HDRX_INTR_CLR_edid_intr_clr 12 |
| #define bHDRX_INTR_CLR_edid_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_edid_intr_clr 0x10000000 |
| #define BA_HDRX_INTR_CLR_tmds_bit_clk_ratio_intr_clr 0x01BB |
| #define B16HDRX_INTR_CLR_tmds_bit_clk_ratio_intr_clr 0x01BA |
| #define LSb32HDRX_INTR_CLR_tmds_bit_clk_ratio_intr_clr 29 |
| #define LSb16HDRX_INTR_CLR_tmds_bit_clk_ratio_intr_clr 13 |
| #define bHDRX_INTR_CLR_tmds_bit_clk_ratio_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_tmds_bit_clk_ratio_intr_clr 0x20000000 |
| #define BA_HDRX_INTR_CLR_scrambler_en_intr_clr 0x01BB |
| #define B16HDRX_INTR_CLR_scrambler_en_intr_clr 0x01BA |
| #define LSb32HDRX_INTR_CLR_scrambler_en_intr_clr 30 |
| #define LSb16HDRX_INTR_CLR_scrambler_en_intr_clr 14 |
| #define bHDRX_INTR_CLR_scrambler_en_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_scrambler_en_intr_clr 0x40000000 |
| #define BA_HDRX_INTR_CLR_rr_enable_intr_clr 0x01BB |
| #define B16HDRX_INTR_CLR_rr_enable_intr_clr 0x01BA |
| #define LSb32HDRX_INTR_CLR_rr_enable_intr_clr 31 |
| #define LSb16HDRX_INTR_CLR_rr_enable_intr_clr 15 |
| #define bHDRX_INTR_CLR_rr_enable_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_rr_enable_intr_clr 0x80000000 |
| #define RA_HDRX_INTR_CLR1 0x01BC |
| #define BA_HDRX_INTR_CLR_wr_mssg_started_intr_clr 0x01BC |
| #define B16HDRX_INTR_CLR_wr_mssg_started_intr_clr 0x01BC |
| #define LSb32HDRX_INTR_CLR_wr_mssg_started_intr_clr 0 |
| #define LSb16HDRX_INTR_CLR_wr_mssg_started_intr_clr 0 |
| #define bHDRX_INTR_CLR_wr_mssg_started_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_wr_mssg_started_intr_clr 0x00000001 |
| #define BA_HDRX_INTR_CLR_wr_mssg_done_intr_clr 0x01BC |
| #define B16HDRX_INTR_CLR_wr_mssg_done_intr_clr 0x01BC |
| #define LSb32HDRX_INTR_CLR_wr_mssg_done_intr_clr 1 |
| #define LSb16HDRX_INTR_CLR_wr_mssg_done_intr_clr 1 |
| #define bHDRX_INTR_CLR_wr_mssg_done_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_wr_mssg_done_intr_clr 0x00000002 |
| #define BA_HDRX_INTR_CLR_read_message_done_intr_clr 0x01BC |
| #define B16HDRX_INTR_CLR_read_message_done_intr_clr 0x01BC |
| #define LSb32HDRX_INTR_CLR_read_message_done_intr_clr 2 |
| #define LSb16HDRX_INTR_CLR_read_message_done_intr_clr 2 |
| #define bHDRX_INTR_CLR_read_message_done_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_read_message_done_intr_clr 0x00000004 |
| #define BA_HDRX_INTR_CLR_read_message_fail_intr_clr 0x01BC |
| #define B16HDRX_INTR_CLR_read_message_fail_intr_clr 0x01BC |
| #define LSb32HDRX_INTR_CLR_read_message_fail_intr_clr 3 |
| #define LSb16HDRX_INTR_CLR_read_message_fail_intr_clr 3 |
| #define bHDRX_INTR_CLR_read_message_fail_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_read_message_fail_intr_clr 0x00000008 |
| #define BA_HDRX_INTR_CLR_hmac_sm_rdy_intr_clr 0x01BC |
| #define B16HDRX_INTR_CLR_hmac_sm_rdy_intr_clr 0x01BC |
| #define LSb32HDRX_INTR_CLR_hmac_sm_rdy_intr_clr 4 |
| #define LSb16HDRX_INTR_CLR_hmac_sm_rdy_intr_clr 4 |
| #define bHDRX_INTR_CLR_hmac_sm_rdy_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_hmac_sm_rdy_intr_clr 0x00000010 |
| #define BA_HDRX_INTR_CLR_hmac_hash_done_intr_clr 0x01BC |
| #define B16HDRX_INTR_CLR_hmac_hash_done_intr_clr 0x01BC |
| #define LSb32HDRX_INTR_CLR_hmac_hash_done_intr_clr 5 |
| #define LSb16HDRX_INTR_CLR_hmac_hash_done_intr_clr 5 |
| #define bHDRX_INTR_CLR_hmac_hash_done_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_hmac_hash_done_intr_clr 0x00000020 |
| #define BA_HDRX_INTR_CLR_phy_prt_en_intr_clr 0x01BC |
| #define B16HDRX_INTR_CLR_phy_prt_en_intr_clr 0x01BC |
| #define LSb32HDRX_INTR_CLR_phy_prt_en_intr_clr 6 |
| #define LSb16HDRX_INTR_CLR_phy_prt_en_intr_clr 6 |
| #define bHDRX_INTR_CLR_phy_prt_en_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_phy_prt_en_intr_clr 0x00000040 |
| #define BA_HDRX_INTR_CLR_drm_info_intr_clr 0x01BC |
| #define B16HDRX_INTR_CLR_drm_info_intr_clr 0x01BC |
| #define LSb32HDRX_INTR_CLR_drm_info_intr_clr 7 |
| #define LSb16HDRX_INTR_CLR_drm_info_intr_clr 7 |
| #define bHDRX_INTR_CLR_drm_info_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_drm_info_intr_clr 0x00000080 |
| #define BA_HDRX_INTR_CLR_aud_fifo_over_flow_intr_clr 0x01BD |
| #define B16HDRX_INTR_CLR_aud_fifo_over_flow_intr_clr 0x01BC |
| #define LSb32HDRX_INTR_CLR_aud_fifo_over_flow_intr_clr 8 |
| #define LSb16HDRX_INTR_CLR_aud_fifo_over_flow_intr_clr 8 |
| #define bHDRX_INTR_CLR_aud_fifo_over_flow_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_aud_fifo_over_flow_intr_clr 0x00000100 |
| #define BA_HDRX_INTR_CLR_aud_fifo_under_flow_intr_clr 0x01BD |
| #define B16HDRX_INTR_CLR_aud_fifo_under_flow_intr_clr 0x01BC |
| #define LSb32HDRX_INTR_CLR_aud_fifo_under_flow_intr_clr 9 |
| #define LSb16HDRX_INTR_CLR_aud_fifo_under_flow_intr_clr 9 |
| #define bHDRX_INTR_CLR_aud_fifo_under_flow_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_aud_fifo_under_flow_intr_clr 0x00000200 |
| #define BA_HDRX_INTR_CLR_phy_pll_lock_intr_clr 0x01BD |
| #define B16HDRX_INTR_CLR_phy_pll_lock_intr_clr 0x01BC |
| #define LSb32HDRX_INTR_CLR_phy_pll_lock_intr_clr 10 |
| #define LSb16HDRX_INTR_CLR_phy_pll_lock_intr_clr 10 |
| #define bHDRX_INTR_CLR_phy_pll_lock_intr_clr 1 |
| #define MSK32HDRX_INTR_CLR_phy_pll_lock_intr_clr 0x00000400 |
| #define RA_HDRX_DI_ERR_STS 0x01C0 |
| #define BA_HDRX_DI_ERR_STS_error_avmute 0x01C0 |
| #define B16HDRX_DI_ERR_STS_error_avmute 0x01C0 |
| #define LSb32HDRX_DI_ERR_STS_error_avmute 0 |
| #define LSb16HDRX_DI_ERR_STS_error_avmute 0 |
| #define bHDRX_DI_ERR_STS_error_avmute 1 |
| #define MSK32HDRX_DI_ERR_STS_error_avmute 0x00000001 |
| #define BA_HDRX_DI_ERR_STS_error_gcp_arr 0x01C0 |
| #define B16HDRX_DI_ERR_STS_error_gcp_arr 0x01C0 |
| #define LSb32HDRX_DI_ERR_STS_error_gcp_arr 1 |
| #define LSb16HDRX_DI_ERR_STS_error_gcp_arr 1 |
| #define bHDRX_DI_ERR_STS_error_gcp_arr 1 |
| #define MSK32HDRX_DI_ERR_STS_error_gcp_arr 0x00000002 |
| #define RA_HDRX_AUD_TST_CTRL 0x01C4 |
| #define BA_HDRX_AUD_TST_CTRL_tst_rst 0x01C4 |
| #define B16HDRX_AUD_TST_CTRL_tst_rst 0x01C4 |
| #define LSb32HDRX_AUD_TST_CTRL_tst_rst 0 |
| #define LSb16HDRX_AUD_TST_CTRL_tst_rst 0 |
| #define bHDRX_AUD_TST_CTRL_tst_rst 1 |
| #define MSK32HDRX_AUD_TST_CTRL_tst_rst 0x00000001 |
| #define BA_HDRX_AUD_TST_CTRL_tst_sub 0x01C4 |
| #define B16HDRX_AUD_TST_CTRL_tst_sub 0x01C4 |
| #define LSb32HDRX_AUD_TST_CTRL_tst_sub 1 |
| #define LSb16HDRX_AUD_TST_CTRL_tst_sub 1 |
| #define bHDRX_AUD_TST_CTRL_tst_sub 4 |
| #define MSK32HDRX_AUD_TST_CTRL_tst_sub 0x0000001E |
| #define RA_HDRX_AUD_TST_STATUS 0x01C8 |
| #define BA_HDRX_AUD_TST_STATUS_max_cnt 0x01C8 |
| #define B16HDRX_AUD_TST_STATUS_max_cnt 0x01C8 |
| #define LSb32HDRX_AUD_TST_STATUS_max_cnt 0 |
| #define LSb16HDRX_AUD_TST_STATUS_max_cnt 0 |
| #define bHDRX_AUD_TST_STATUS_max_cnt 16 |
| #define MSK32HDRX_AUD_TST_STATUS_max_cnt 0x0000FFFF |
| #define BA_HDRX_AUD_TST_STATUS_min_cnt 0x01CA |
| #define B16HDRX_AUD_TST_STATUS_min_cnt 0x01CA |
| #define LSb32HDRX_AUD_TST_STATUS_min_cnt 16 |
| #define LSb16HDRX_AUD_TST_STATUS_min_cnt 0 |
| #define bHDRX_AUD_TST_STATUS_min_cnt 16 |
| #define MSK32HDRX_AUD_TST_STATUS_min_cnt 0xFFFF0000 |
| #define RA_HDRX_AUD_TST_STATUS1 0x01CC |
| #define BA_HDRX_AUD_TST_STATUS_cnt 0x01CC |
| #define B16HDRX_AUD_TST_STATUS_cnt 0x01CC |
| #define LSb32HDRX_AUD_TST_STATUS_cnt 0 |
| #define LSb16HDRX_AUD_TST_STATUS_cnt 0 |
| #define bHDRX_AUD_TST_STATUS_cnt 16 |
| #define MSK32HDRX_AUD_TST_STATUS_cnt 0x0000FFFF |
| #define RA_HDRX_ACR_CTRL 0x01D0 |
| #define BA_HDRX_ACR_CTRL_cts_thresh 0x01D0 |
| #define B16HDRX_ACR_CTRL_cts_thresh 0x01D0 |
| #define LSb32HDRX_ACR_CTRL_cts_thresh 0 |
| #define LSb16HDRX_ACR_CTRL_cts_thresh 0 |
| #define bHDRX_ACR_CTRL_cts_thresh 4 |
| #define MSK32HDRX_ACR_CTRL_cts_thresh 0x0000000F |
| #define BA_HDRX_ACR_CTRL_sw_n 0x01D0 |
| #define B16HDRX_ACR_CTRL_sw_n 0x01D0 |
| #define LSb32HDRX_ACR_CTRL_sw_n 4 |
| #define LSb16HDRX_ACR_CTRL_sw_n 4 |
| #define bHDRX_ACR_CTRL_sw_n 1 |
| #define MSK32HDRX_ACR_CTRL_sw_n 0x00000010 |
| #define BA_HDRX_ACR_CTRL_sw_cts 0x01D0 |
| #define B16HDRX_ACR_CTRL_sw_cts 0x01D0 |
| #define LSb32HDRX_ACR_CTRL_sw_cts 5 |
| #define LSb16HDRX_ACR_CTRL_sw_cts 5 |
| #define bHDRX_ACR_CTRL_sw_cts 1 |
| #define MSK32HDRX_ACR_CTRL_sw_cts 0x00000020 |
| #define RA_HDRX_AUD_CTRL 0x01D4 |
| #define BA_HDRX_AUD_CTRL_memsize 0x01D4 |
| #define B16HDRX_AUD_CTRL_memsize 0x01D4 |
| #define LSb32HDRX_AUD_CTRL_memsize 0 |
| #define LSb16HDRX_AUD_CTRL_memsize 0 |
| #define bHDRX_AUD_CTRL_memsize 9 |
| #define MSK32HDRX_AUD_CTRL_memsize 0x000001FF |
| #define BA_HDRX_AUD_CTRL_rd_wr_dist 0x01D5 |
| #define B16HDRX_AUD_CTRL_rd_wr_dist 0x01D4 |
| #define LSb32HDRX_AUD_CTRL_rd_wr_dist 9 |
| #define LSb16HDRX_AUD_CTRL_rd_wr_dist 9 |
| #define bHDRX_AUD_CTRL_rd_wr_dist 8 |
| #define MSK32HDRX_AUD_CTRL_rd_wr_dist 0x0001FE00 |
| #define BA_HDRX_AUD_CTRL_clos_det_dist 0x01D6 |
| #define B16HDRX_AUD_CTRL_clos_det_dist 0x01D6 |
| #define LSb32HDRX_AUD_CTRL_clos_det_dist 17 |
| #define LSb16HDRX_AUD_CTRL_clos_det_dist 1 |
| #define bHDRX_AUD_CTRL_clos_det_dist 8 |
| #define MSK32HDRX_AUD_CTRL_clos_det_dist 0x01FE0000 |
| #define BA_HDRX_AUD_CTRL_fifo_rst 0x01D7 |
| #define B16HDRX_AUD_CTRL_fifo_rst 0x01D6 |
| #define LSb32HDRX_AUD_CTRL_fifo_rst 25 |
| #define LSb16HDRX_AUD_CTRL_fifo_rst 9 |
| #define bHDRX_AUD_CTRL_fifo_rst 1 |
| #define MSK32HDRX_AUD_CTRL_fifo_rst 0x02000000 |
| #define BA_HDRX_AUD_CTRL_irst_mask0 0x01D7 |
| #define B16HDRX_AUD_CTRL_irst_mask0 0x01D6 |
| #define LSb32HDRX_AUD_CTRL_irst_mask0 26 |
| #define LSb16HDRX_AUD_CTRL_irst_mask0 10 |
| #define bHDRX_AUD_CTRL_irst_mask0 1 |
| #define MSK32HDRX_AUD_CTRL_irst_mask0 0x04000000 |
| #define BA_HDRX_AUD_CTRL_irst_mask1 0x01D7 |
| #define B16HDRX_AUD_CTRL_irst_mask1 0x01D6 |
| #define LSb32HDRX_AUD_CTRL_irst_mask1 27 |
| #define LSb16HDRX_AUD_CTRL_irst_mask1 11 |
| #define bHDRX_AUD_CTRL_irst_mask1 1 |
| #define MSK32HDRX_AUD_CTRL_irst_mask1 0x08000000 |
| #define BA_HDRX_AUD_CTRL_aud_fpll_ref_clk_sel 0x01D7 |
| #define B16HDRX_AUD_CTRL_aud_fpll_ref_clk_sel 0x01D6 |
| #define LSb32HDRX_AUD_CTRL_aud_fpll_ref_clk_sel 28 |
| #define LSb16HDRX_AUD_CTRL_aud_fpll_ref_clk_sel 12 |
| #define bHDRX_AUD_CTRL_aud_fpll_ref_clk_sel 2 |
| #define MSK32HDRX_AUD_CTRL_aud_fpll_ref_clk_sel 0x30000000 |
| #define BA_HDRX_AUD_CTRL_n_mul_factor 0x01D7 |
| #define B16HDRX_AUD_CTRL_n_mul_factor 0x01D6 |
| #define LSb32HDRX_AUD_CTRL_n_mul_factor 30 |
| #define LSb16HDRX_AUD_CTRL_n_mul_factor 14 |
| #define bHDRX_AUD_CTRL_n_mul_factor 2 |
| #define MSK32HDRX_AUD_CTRL_n_mul_factor 0xC0000000 |
| #define RA_HDRX_AUD_CTRL1 0x01D8 |
| #define BA_HDRX_AUD_CTRL_hbr_pkt_en 0x01D8 |
| #define B16HDRX_AUD_CTRL_hbr_pkt_en 0x01D8 |
| #define LSb32HDRX_AUD_CTRL_hbr_pkt_en 0 |
| #define LSb16HDRX_AUD_CTRL_hbr_pkt_en 0 |
| #define bHDRX_AUD_CTRL_hbr_pkt_en 1 |
| #define MSK32HDRX_AUD_CTRL_hbr_pkt_en 0x00000001 |
| #define BA_HDRX_AUD_CTRL_hbr_audio_out 0x01D8 |
| #define B16HDRX_AUD_CTRL_hbr_audio_out 0x01D8 |
| #define LSb32HDRX_AUD_CTRL_hbr_audio_out 1 |
| #define LSb16HDRX_AUD_CTRL_hbr_audio_out 1 |
| #define bHDRX_AUD_CTRL_hbr_audio_out 1 |
| #define MSK32HDRX_AUD_CTRL_hbr_audio_out 0x00000002 |
| #define BA_HDRX_AUD_CTRL_aud3d_en 0x01D8 |
| #define B16HDRX_AUD_CTRL_aud3d_en 0x01D8 |
| #define LSb32HDRX_AUD_CTRL_aud3d_en 2 |
| #define LSb16HDRX_AUD_CTRL_aud3d_en 2 |
| #define bHDRX_AUD_CTRL_aud3d_en 1 |
| #define MSK32HDRX_AUD_CTRL_aud3d_en 0x00000004 |
| #define BA_HDRX_AUD_CTRL_max_noc 0x01D8 |
| #define B16HDRX_AUD_CTRL_max_noc 0x01D8 |
| #define LSb32HDRX_AUD_CTRL_max_noc 3 |
| #define LSb16HDRX_AUD_CTRL_max_noc 3 |
| #define bHDRX_AUD_CTRL_max_noc 2 |
| #define MSK32HDRX_AUD_CTRL_max_noc 0x00000018 |
| #define RA_HDRX_ACR_SW_N 0x01DC |
| #define BA_HDRX_ACR_SW_N_val 0x01DC |
| #define B16HDRX_ACR_SW_N_val 0x01DC |
| #define LSb32HDRX_ACR_SW_N_val 0 |
| #define LSb16HDRX_ACR_SW_N_val 0 |
| #define bHDRX_ACR_SW_N_val 20 |
| #define MSK32HDRX_ACR_SW_N_val 0x000FFFFF |
| #define RA_HDRX_ACR_SW_CTS 0x01E0 |
| #define BA_HDRX_ACR_SW_CTS_val 0x01E0 |
| #define B16HDRX_ACR_SW_CTS_val 0x01E0 |
| #define LSb32HDRX_ACR_SW_CTS_val 0 |
| #define LSb16HDRX_ACR_SW_CTS_val 0 |
| #define bHDRX_ACR_SW_CTS_val 20 |
| #define MSK32HDRX_ACR_SW_CTS_val 0x000FFFFF |
| #define RA_HDRX_I2S_CTRL 0x01E4 |
| #define BA_HDRX_I2S_CTRL_i2s_ctrl 0x01E4 |
| #define B16HDRX_I2S_CTRL_i2s_ctrl 0x01E4 |
| #define LSb32HDRX_I2S_CTRL_i2s_ctrl 0 |
| #define LSb16HDRX_I2S_CTRL_i2s_ctrl 0 |
| #define bHDRX_I2S_CTRL_i2s_ctrl 4 |
| #define MSK32HDRX_I2S_CTRL_i2s_ctrl 0x0000000F |
| #define BA_HDRX_I2S_CTRL_i2s_clk_pol 0x01E4 |
| #define B16HDRX_I2S_CTRL_i2s_clk_pol 0x01E4 |
| #define LSb32HDRX_I2S_CTRL_i2s_clk_pol 4 |
| #define LSb16HDRX_I2S_CTRL_i2s_clk_pol 4 |
| #define bHDRX_I2S_CTRL_i2s_clk_pol 1 |
| #define MSK32HDRX_I2S_CTRL_i2s_clk_pol 0x00000010 |
| #define BA_HDRX_I2S_CTRL_pream_ctrl 0x01E4 |
| #define B16HDRX_I2S_CTRL_pream_ctrl 0x01E4 |
| #define LSb32HDRX_I2S_CTRL_pream_ctrl 5 |
| #define LSb16HDRX_I2S_CTRL_pream_ctrl 5 |
| #define bHDRX_I2S_CTRL_pream_ctrl 1 |
| #define MSK32HDRX_I2S_CTRL_pream_ctrl 0x00000020 |
| #define BA_HDRX_I2S_CTRL_data_wid 0x01E4 |
| #define B16HDRX_I2S_CTRL_data_wid 0x01E4 |
| #define LSb32HDRX_I2S_CTRL_data_wid 6 |
| #define LSb16HDRX_I2S_CTRL_data_wid 6 |
| #define bHDRX_I2S_CTRL_data_wid 5 |
| #define MSK32HDRX_I2S_CTRL_data_wid 0x000007C0 |
| #define RA_HDRX_ECC_CTRL 0x01E8 |
| #define BA_HDRX_ECC_CTRL_ecc_det_en 0x01E8 |
| #define B16HDRX_ECC_CTRL_ecc_det_en 0x01E8 |
| #define LSb32HDRX_ECC_CTRL_ecc_det_en 0 |
| #define LSb16HDRX_ECC_CTRL_ecc_det_en 0 |
| #define bHDRX_ECC_CTRL_ecc_det_en 1 |
| #define MSK32HDRX_ECC_CTRL_ecc_det_en 0x00000001 |
| #define BA_HDRX_ECC_CTRL_ecc_byp 0x01E8 |
| #define B16HDRX_ECC_CTRL_ecc_byp 0x01E8 |
| #define LSb32HDRX_ECC_CTRL_ecc_byp 1 |
| #define LSb16HDRX_ECC_CTRL_ecc_byp 1 |
| #define bHDRX_ECC_CTRL_ecc_byp 1 |
| #define MSK32HDRX_ECC_CTRL_ecc_byp 0x00000002 |
| #define BA_HDRX_ECC_CTRL_ecc_par_dir 0x01E8 |
| #define B16HDRX_ECC_CTRL_ecc_par_dir 0x01E8 |
| #define LSb32HDRX_ECC_CTRL_ecc_par_dir 2 |
| #define LSb16HDRX_ECC_CTRL_ecc_par_dir 2 |
| #define bHDRX_ECC_CTRL_ecc_par_dir 1 |
| #define MSK32HDRX_ECC_CTRL_ecc_par_dir 0x00000004 |
| #define BA_HDRX_ECC_CTRL_ecc_clr_sel 0x01E8 |
| #define B16HDRX_ECC_CTRL_ecc_clr_sel 0x01E8 |
| #define LSb32HDRX_ECC_CTRL_ecc_clr_sel 3 |
| #define LSb16HDRX_ECC_CTRL_ecc_clr_sel 3 |
| #define bHDRX_ECC_CTRL_ecc_clr_sel 1 |
| #define MSK32HDRX_ECC_CTRL_ecc_clr_sel 0x00000008 |
| #define BA_HDRX_ECC_CTRL_ecc_ctrl0 0x01E8 |
| #define B16HDRX_ECC_CTRL_ecc_ctrl0 0x01E8 |
| #define LSb32HDRX_ECC_CTRL_ecc_ctrl0 4 |
| #define LSb16HDRX_ECC_CTRL_ecc_ctrl0 4 |
| #define bHDRX_ECC_CTRL_ecc_ctrl0 1 |
| #define MSK32HDRX_ECC_CTRL_ecc_ctrl0 0x00000010 |
| #define BA_HDRX_ECC_CTRL_ecc_ctrl1 0x01E8 |
| #define B16HDRX_ECC_CTRL_ecc_ctrl1 0x01E8 |
| #define LSb32HDRX_ECC_CTRL_ecc_ctrl1 5 |
| #define LSb16HDRX_ECC_CTRL_ecc_ctrl1 5 |
| #define bHDRX_ECC_CTRL_ecc_ctrl1 3 |
| #define MSK32HDRX_ECC_CTRL_ecc_ctrl1 0x000000E0 |
| #define BA_HDRX_ECC_CTRL_ecc_ctrl2 0x01E9 |
| #define B16HDRX_ECC_CTRL_ecc_ctrl2 0x01E8 |
| #define LSb32HDRX_ECC_CTRL_ecc_ctrl2 8 |
| #define LSb16HDRX_ECC_CTRL_ecc_ctrl2 8 |
| #define bHDRX_ECC_CTRL_ecc_ctrl2 6 |
| #define MSK32HDRX_ECC_CTRL_ecc_ctrl2 0x00003F00 |
| #define BA_HDRX_ECC_CTRL_link_check_ecc_thresh 0x01E9 |
| #define B16HDRX_ECC_CTRL_link_check_ecc_thresh 0x01E8 |
| #define LSb32HDRX_ECC_CTRL_link_check_ecc_thresh 14 |
| #define LSb16HDRX_ECC_CTRL_link_check_ecc_thresh 14 |
| #define bHDRX_ECC_CTRL_link_check_ecc_thresh 8 |
| #define MSK32HDRX_ECC_CTRL_link_check_ecc_thresh 0x003FC000 |
| #define RA_HDRX_DI_ASP_CHSTS 0x01EC |
| #define BA_HDRX_DI_ASP_CHSTS_chsts_0 0x01EC |
| #define B16HDRX_DI_ASP_CHSTS_chsts_0 0x01EC |
| #define LSb32HDRX_DI_ASP_CHSTS_chsts_0 0 |
| #define LSb16HDRX_DI_ASP_CHSTS_chsts_0 0 |
| #define bHDRX_DI_ASP_CHSTS_chsts_0 8 |
| #define MSK32HDRX_DI_ASP_CHSTS_chsts_0 0x000000FF |
| #define BA_HDRX_DI_ASP_CHSTS_chsts_1 0x01ED |
| #define B16HDRX_DI_ASP_CHSTS_chsts_1 0x01EC |
| #define LSb32HDRX_DI_ASP_CHSTS_chsts_1 8 |
| #define LSb16HDRX_DI_ASP_CHSTS_chsts_1 8 |
| #define bHDRX_DI_ASP_CHSTS_chsts_1 8 |
| #define MSK32HDRX_DI_ASP_CHSTS_chsts_1 0x0000FF00 |
| #define BA_HDRX_DI_ASP_CHSTS_chsts_2 0x01EE |
| #define B16HDRX_DI_ASP_CHSTS_chsts_2 0x01EE |
| #define LSb32HDRX_DI_ASP_CHSTS_chsts_2 16 |
| #define LSb16HDRX_DI_ASP_CHSTS_chsts_2 0 |
| #define bHDRX_DI_ASP_CHSTS_chsts_2 8 |
| #define MSK32HDRX_DI_ASP_CHSTS_chsts_2 0x00FF0000 |
| #define BA_HDRX_DI_ASP_CHSTS_chsts_3 0x01EF |
| #define B16HDRX_DI_ASP_CHSTS_chsts_3 0x01EE |
| #define LSb32HDRX_DI_ASP_CHSTS_chsts_3 24 |
| #define LSb16HDRX_DI_ASP_CHSTS_chsts_3 8 |
| #define bHDRX_DI_ASP_CHSTS_chsts_3 8 |
| #define MSK32HDRX_DI_ASP_CHSTS_chsts_3 0xFF000000 |
| #define RA_HDRX_DI_ASP_CHSTS1 0x01F0 |
| #define BA_HDRX_DI_ASP_CHSTS_chsts_4 0x01F0 |
| #define B16HDRX_DI_ASP_CHSTS_chsts_4 0x01F0 |
| #define LSb32HDRX_DI_ASP_CHSTS_chsts_4 0 |
| #define LSb16HDRX_DI_ASP_CHSTS_chsts_4 0 |
| #define bHDRX_DI_ASP_CHSTS_chsts_4 8 |
| #define MSK32HDRX_DI_ASP_CHSTS_chsts_4 0x000000FF |
| #define BA_HDRX_DI_ASP_CHSTS_chsts_5 0x01F1 |
| #define B16HDRX_DI_ASP_CHSTS_chsts_5 0x01F0 |
| #define LSb32HDRX_DI_ASP_CHSTS_chsts_5 8 |
| #define LSb16HDRX_DI_ASP_CHSTS_chsts_5 8 |
| #define bHDRX_DI_ASP_CHSTS_chsts_5 8 |
| #define MSK32HDRX_DI_ASP_CHSTS_chsts_5 0x0000FF00 |
| #define RA_HDRX_DI_ASP_UBITS 0x01F4 |
| #define BA_HDRX_DI_ASP_UBITS_ubits_0_to_31 0x01F4 |
| #define B16HDRX_DI_ASP_UBITS_ubits_0_to_31 0x01F4 |
| #define LSb32HDRX_DI_ASP_UBITS_ubits_0_to_31 0 |
| #define LSb16HDRX_DI_ASP_UBITS_ubits_0_to_31 0 |
| #define bHDRX_DI_ASP_UBITS_ubits_0_to_31 32 |
| #define MSK32HDRX_DI_ASP_UBITS_ubits_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_DI_ASP_UBITS1 0x01F8 |
| #define BA_HDRX_DI_ASP_UBITS_ubits_32_to_63 0x01F8 |
| #define B16HDRX_DI_ASP_UBITS_ubits_32_to_63 0x01F8 |
| #define LSb32HDRX_DI_ASP_UBITS_ubits_32_to_63 0 |
| #define LSb16HDRX_DI_ASP_UBITS_ubits_32_to_63 0 |
| #define bHDRX_DI_ASP_UBITS_ubits_32_to_63 32 |
| #define MSK32HDRX_DI_ASP_UBITS_ubits_32_to_63 0xFFFFFFFF |
| #define RA_HDRX_DI_ASP_UBITS2 0x01FC |
| #define BA_HDRX_DI_ASP_UBITS_ubits_64_to_95 0x01FC |
| #define B16HDRX_DI_ASP_UBITS_ubits_64_to_95 0x01FC |
| #define LSb32HDRX_DI_ASP_UBITS_ubits_64_to_95 0 |
| #define LSb16HDRX_DI_ASP_UBITS_ubits_64_to_95 0 |
| #define bHDRX_DI_ASP_UBITS_ubits_64_to_95 32 |
| #define MSK32HDRX_DI_ASP_UBITS_ubits_64_to_95 0xFFFFFFFF |
| #define RA_HDRX_DI_ASP_UBITS3 0x0200 |
| #define BA_HDRX_DI_ASP_UBITS_ubits_96_to_111 0x0200 |
| #define B16HDRX_DI_ASP_UBITS_ubits_96_to_111 0x0200 |
| #define LSb32HDRX_DI_ASP_UBITS_ubits_96_to_111 0 |
| #define LSb16HDRX_DI_ASP_UBITS_ubits_96_to_111 0 |
| #define bHDRX_DI_ASP_UBITS_ubits_96_to_111 16 |
| #define MSK32HDRX_DI_ASP_UBITS_ubits_96_to_111 0x0000FFFF |
| #define RA_HDRX_DI_ASP_HDR 0x0204 |
| #define BA_HDRX_DI_ASP_HDR_layout 0x0204 |
| #define B16HDRX_DI_ASP_HDR_layout 0x0204 |
| #define LSb32HDRX_DI_ASP_HDR_layout 0 |
| #define LSb16HDRX_DI_ASP_HDR_layout 0 |
| #define bHDRX_DI_ASP_HDR_layout 1 |
| #define MSK32HDRX_DI_ASP_HDR_layout 0x00000001 |
| #define BA_HDRX_DI_ASP_HDR_sp 0x0204 |
| #define B16HDRX_DI_ASP_HDR_sp 0x0204 |
| #define LSb32HDRX_DI_ASP_HDR_sp 1 |
| #define LSb16HDRX_DI_ASP_HDR_sp 1 |
| #define bHDRX_DI_ASP_HDR_sp 4 |
| #define MSK32HDRX_DI_ASP_HDR_sp 0x0000001E |
| #define RA_HDRX_CMON_DIV 0x0208 |
| #define BA_HDRX_CMON_DIV_cmon_div 0x0208 |
| #define B16HDRX_CMON_DIV_cmon_div 0x0208 |
| #define LSb32HDRX_CMON_DIV_cmon_div 0 |
| #define LSb16HDRX_CMON_DIV_cmon_div 0 |
| #define bHDRX_CMON_DIV_cmon_div 16 |
| #define MSK32HDRX_CMON_DIV_cmon_div 0x0000FFFF |
| #define RA_HDRX_CMON_CTRL 0x020C |
| #define BA_HDRX_CMON_CTRL_trig 0x020C |
| #define B16HDRX_CMON_CTRL_trig 0x020C |
| #define LSb32HDRX_CMON_CTRL_trig 0 |
| #define LSb16HDRX_CMON_CTRL_trig 0 |
| #define bHDRX_CMON_CTRL_trig 1 |
| #define MSK32HDRX_CMON_CTRL_trig 0x00000001 |
| #define BA_HDRX_CMON_CTRL_mode 0x020C |
| #define B16HDRX_CMON_CTRL_mode 0x020C |
| #define LSb32HDRX_CMON_CTRL_mode 1 |
| #define LSb16HDRX_CMON_CTRL_mode 1 |
| #define bHDRX_CMON_CTRL_mode 1 |
| #define MSK32HDRX_CMON_CTRL_mode 0x00000002 |
| #define BA_HDRX_CMON_CTRL_async_clr 0x020C |
| #define B16HDRX_CMON_CTRL_async_clr 0x020C |
| #define LSb32HDRX_CMON_CTRL_async_clr 2 |
| #define LSb16HDRX_CMON_CTRL_async_clr 2 |
| #define bHDRX_CMON_CTRL_async_clr 1 |
| #define MSK32HDRX_CMON_CTRL_async_clr 0x00000004 |
| #define BA_HDRX_CMON_CTRL_clock_sel 0x020C |
| #define B16HDRX_CMON_CTRL_clock_sel 0x020C |
| #define LSb32HDRX_CMON_CTRL_clock_sel 3 |
| #define LSb16HDRX_CMON_CTRL_clock_sel 3 |
| #define bHDRX_CMON_CTRL_clock_sel 2 |
| #define MSK32HDRX_CMON_CTRL_clock_sel 0x00000018 |
| #define BA_HDRX_CMON_CTRL_cmon_tol 0x020C |
| #define B16HDRX_CMON_CTRL_cmon_tol 0x020C |
| #define LSb32HDRX_CMON_CTRL_cmon_tol 5 |
| #define LSb16HDRX_CMON_CTRL_cmon_tol 5 |
| #define bHDRX_CMON_CTRL_cmon_tol 4 |
| #define MSK32HDRX_CMON_CTRL_cmon_tol 0x000001E0 |
| #define BA_HDRX_CMON_CTRL_cmon_tmo 0x020D |
| #define B16HDRX_CMON_CTRL_cmon_tmo 0x020C |
| #define LSb32HDRX_CMON_CTRL_cmon_tmo 9 |
| #define LSb16HDRX_CMON_CTRL_cmon_tmo 9 |
| #define bHDRX_CMON_CTRL_cmon_tmo 8 |
| #define MSK32HDRX_CMON_CTRL_cmon_tmo 0x0001FE00 |
| #define BA_HDRX_CMON_CTRL_cmon_mat 0x020E |
| #define B16HDRX_CMON_CTRL_cmon_mat 0x020E |
| #define LSb32HDRX_CMON_CTRL_cmon_mat 17 |
| #define LSb16HDRX_CMON_CTRL_cmon_mat 1 |
| #define bHDRX_CMON_CTRL_cmon_mat 12 |
| #define MSK32HDRX_CMON_CTRL_cmon_mat 0x1FFE0000 |
| #define BA_HDRX_CMON_CTRL_RSVD 0x020F |
| #define B16HDRX_CMON_CTRL_RSVD 0x020E |
| #define LSb32HDRX_CMON_CTRL_RSVD 29 |
| #define LSb16HDRX_CMON_CTRL_RSVD 13 |
| #define bHDRX_CMON_CTRL_RSVD 3 |
| #define MSK32HDRX_CMON_CTRL_RSVD 0xE0000000 |
| #define RA_HDRX_CMON_CTRL1 0x0210 |
| #define BA_HDRX_CMON_CTRL_cmon_mismat 0x0210 |
| #define B16HDRX_CMON_CTRL_cmon_mismat 0x0210 |
| #define LSb32HDRX_CMON_CTRL_cmon_mismat 0 |
| #define LSb16HDRX_CMON_CTRL_cmon_mismat 0 |
| #define bHDRX_CMON_CTRL_cmon_mismat 8 |
| #define MSK32HDRX_CMON_CTRL_cmon_mismat 0x000000FF |
| #define RA_HDRX_SMON_CTRL 0x0214 |
| #define BA_HDRX_SMON_CTRL_trig 0x0214 |
| #define B16HDRX_SMON_CTRL_trig 0x0214 |
| #define LSb32HDRX_SMON_CTRL_trig 0 |
| #define LSb16HDRX_SMON_CTRL_trig 0 |
| #define bHDRX_SMON_CTRL_trig 1 |
| #define MSK32HDRX_SMON_CTRL_trig 0x00000001 |
| #define BA_HDRX_SMON_CTRL_mode 0x0214 |
| #define B16HDRX_SMON_CTRL_mode 0x0214 |
| #define LSb32HDRX_SMON_CTRL_mode 1 |
| #define LSb16HDRX_SMON_CTRL_mode 1 |
| #define bHDRX_SMON_CTRL_mode 1 |
| #define MSK32HDRX_SMON_CTRL_mode 0x00000002 |
| #define BA_HDRX_SMON_CTRL_detect 0x0214 |
| #define B16HDRX_SMON_CTRL_detect 0x0214 |
| #define LSb32HDRX_SMON_CTRL_detect 2 |
| #define LSb16HDRX_SMON_CTRL_detect 2 |
| #define bHDRX_SMON_CTRL_detect 1 |
| #define MSK32HDRX_SMON_CTRL_detect 0x00000004 |
| #define BA_HDRX_SMON_CTRL_async_clr 0x0214 |
| #define B16HDRX_SMON_CTRL_async_clr 0x0214 |
| #define LSb32HDRX_SMON_CTRL_async_clr 3 |
| #define LSb16HDRX_SMON_CTRL_async_clr 3 |
| #define bHDRX_SMON_CTRL_async_clr 1 |
| #define MSK32HDRX_SMON_CTRL_async_clr 0x00000008 |
| #define BA_HDRX_SMON_CTRL_smon_tol 0x0214 |
| #define B16HDRX_SMON_CTRL_smon_tol 0x0214 |
| #define LSb32HDRX_SMON_CTRL_smon_tol 4 |
| #define LSb16HDRX_SMON_CTRL_smon_tol 4 |
| #define bHDRX_SMON_CTRL_smon_tol 8 |
| #define MSK32HDRX_SMON_CTRL_smon_tol 0x00000FF0 |
| #define BA_HDRX_SMON_CTRL_smon_htmo 0x0215 |
| #define B16HDRX_SMON_CTRL_smon_htmo 0x0214 |
| #define LSb32HDRX_SMON_CTRL_smon_htmo 12 |
| #define LSb16HDRX_SMON_CTRL_smon_htmo 12 |
| #define bHDRX_SMON_CTRL_smon_htmo 8 |
| #define MSK32HDRX_SMON_CTRL_smon_htmo 0x000FF000 |
| #define BA_HDRX_SMON_CTRL_smon_hmat 0x0216 |
| #define B16HDRX_SMON_CTRL_smon_hmat 0x0216 |
| #define LSb32HDRX_SMON_CTRL_smon_hmat 20 |
| #define LSb16HDRX_SMON_CTRL_smon_hmat 4 |
| #define bHDRX_SMON_CTRL_smon_hmat 12 |
| #define MSK32HDRX_SMON_CTRL_smon_hmat 0xFFF00000 |
| #define RA_HDRX_SMON_CTRL1 0x0218 |
| #define BA_HDRX_SMON_CTRL_smon_hmismat 0x0218 |
| #define B16HDRX_SMON_CTRL_smon_hmismat 0x0218 |
| #define LSb32HDRX_SMON_CTRL_smon_hmismat 0 |
| #define LSb16HDRX_SMON_CTRL_smon_hmismat 0 |
| #define bHDRX_SMON_CTRL_smon_hmismat 8 |
| #define MSK32HDRX_SMON_CTRL_smon_hmismat 0x000000FF |
| #define BA_HDRX_SMON_CTRL_smon_vsmp 0x0219 |
| #define B16HDRX_SMON_CTRL_smon_vsmp 0x0218 |
| #define LSb32HDRX_SMON_CTRL_smon_vsmp 8 |
| #define LSb16HDRX_SMON_CTRL_smon_vsmp 8 |
| #define bHDRX_SMON_CTRL_smon_vsmp 8 |
| #define MSK32HDRX_SMON_CTRL_smon_vsmp 0x0000FF00 |
| #define BA_HDRX_SMON_CTRL_smon_vtmo 0x021A |
| #define B16HDRX_SMON_CTRL_smon_vtmo 0x021A |
| #define LSb32HDRX_SMON_CTRL_smon_vtmo 16 |
| #define LSb16HDRX_SMON_CTRL_smon_vtmo 0 |
| #define bHDRX_SMON_CTRL_smon_vtmo 8 |
| #define MSK32HDRX_SMON_CTRL_smon_vtmo 0x00FF0000 |
| #define BA_HDRX_SMON_CTRL_smon_vmismat 0x021B |
| #define B16HDRX_SMON_CTRL_smon_vmismat 0x021A |
| #define LSb32HDRX_SMON_CTRL_smon_vmismat 24 |
| #define LSb16HDRX_SMON_CTRL_smon_vmismat 8 |
| #define bHDRX_SMON_CTRL_smon_vmismat 8 |
| #define MSK32HDRX_SMON_CTRL_smon_vmismat 0xFF000000 |
| #define RA_HDRX_SMON_CTRL2 0x021C |
| #define BA_HDRX_SMON_CTRL_smon_vmat 0x021C |
| #define B16HDRX_SMON_CTRL_smon_vmat 0x021C |
| #define LSb32HDRX_SMON_CTRL_smon_vmat 0 |
| #define LSb16HDRX_SMON_CTRL_smon_vmat 0 |
| #define bHDRX_SMON_CTRL_smon_vmat 12 |
| #define MSK32HDRX_SMON_CTRL_smon_vmat 0x00000FFF |
| #define RA_HDRX_CMON_STAT 0x0220 |
| #define BA_HDRX_CMON_STAT_status 0x0220 |
| #define B16HDRX_CMON_STAT_status 0x0220 |
| #define LSb32HDRX_CMON_STAT_status 0 |
| #define LSb16HDRX_CMON_STAT_status 0 |
| #define bHDRX_CMON_STAT_status 4 |
| #define MSK32HDRX_CMON_STAT_status 0x0000000F |
| #define BA_HDRX_CMON_STAT_total 0x0220 |
| #define B16HDRX_CMON_STAT_total 0x0220 |
| #define LSb32HDRX_CMON_STAT_total 4 |
| #define LSb16HDRX_CMON_STAT_total 4 |
| #define bHDRX_CMON_STAT_total 16 |
| #define MSK32HDRX_CMON_STAT_total 0x000FFFF0 |
| #define RA_HDRX_CMON_STAT1 0x0224 |
| #define BA_HDRX_CMON_STAT_width 0x0224 |
| #define B16HDRX_CMON_STAT_width 0x0224 |
| #define LSb32HDRX_CMON_STAT_width 0 |
| #define LSb16HDRX_CMON_STAT_width 0 |
| #define bHDRX_CMON_STAT_width 16 |
| #define MSK32HDRX_CMON_STAT_width 0x0000FFFF |
| #define RA_HDRX_SMON_STAT 0x0228 |
| #define BA_HDRX_SMON_STAT_htotal 0x0228 |
| #define B16HDRX_SMON_STAT_htotal 0x0228 |
| #define LSb32HDRX_SMON_STAT_htotal 0 |
| #define LSb16HDRX_SMON_STAT_htotal 0 |
| #define bHDRX_SMON_STAT_htotal 16 |
| #define MSK32HDRX_SMON_STAT_htotal 0x0000FFFF |
| #define BA_HDRX_SMON_STAT_hwidth 0x022A |
| #define B16HDRX_SMON_STAT_hwidth 0x022A |
| #define LSb32HDRX_SMON_STAT_hwidth 16 |
| #define LSb16HDRX_SMON_STAT_hwidth 0 |
| #define bHDRX_SMON_STAT_hwidth 16 |
| #define MSK32HDRX_SMON_STAT_hwidth 0xFFFF0000 |
| #define RA_HDRX_SMON_STAT1 0x022C |
| #define BA_HDRX_SMON_STAT_vtotal 0x022C |
| #define B16HDRX_SMON_STAT_vtotal 0x022C |
| #define LSb32HDRX_SMON_STAT_vtotal 0 |
| #define LSb16HDRX_SMON_STAT_vtotal 0 |
| #define bHDRX_SMON_STAT_vtotal 16 |
| #define MSK32HDRX_SMON_STAT_vtotal 0x0000FFFF |
| #define BA_HDRX_SMON_STAT_vwidth 0x022E |
| #define B16HDRX_SMON_STAT_vwidth 0x022E |
| #define LSb32HDRX_SMON_STAT_vwidth 16 |
| #define LSb16HDRX_SMON_STAT_vwidth 0 |
| #define bHDRX_SMON_STAT_vwidth 16 |
| #define MSK32HDRX_SMON_STAT_vwidth 0xFFFF0000 |
| #define RA_HDRX_SMON_STAT2 0x0230 |
| #define BA_HDRX_SMON_STAT_status 0x0230 |
| #define B16HDRX_SMON_STAT_status 0x0230 |
| #define LSb32HDRX_SMON_STAT_status 0 |
| #define LSb16HDRX_SMON_STAT_status 0 |
| #define bHDRX_SMON_STAT_status 8 |
| #define MSK32HDRX_SMON_STAT_status 0x000000FF |
| #define RA_HDRX_PWR5V_STATUS 0x0234 |
| #define BA_HDRX_PWR5V_STATUS_status 0x0234 |
| #define B16HDRX_PWR5V_STATUS_status 0x0234 |
| #define LSb32HDRX_PWR5V_STATUS_status 0 |
| #define LSb16HDRX_PWR5V_STATUS_status 0 |
| #define bHDRX_PWR5V_STATUS_status 1 |
| #define MSK32HDRX_PWR5V_STATUS_status 0x00000001 |
| #define RA_HDRX_PWR5V_SW 0x0238 |
| #define BA_HDRX_PWR5V_SW_pwr5v_sw 0x0238 |
| #define B16HDRX_PWR5V_SW_pwr5v_sw 0x0238 |
| #define LSb32HDRX_PWR5V_SW_pwr5v_sw 0 |
| #define LSb16HDRX_PWR5V_SW_pwr5v_sw 0 |
| #define bHDRX_PWR5V_SW_pwr5v_sw 1 |
| #define MSK32HDRX_PWR5V_SW_pwr5v_sw 0x00000001 |
| #define BA_HDRX_PWR5V_SW_pwr5v_sel 0x0238 |
| #define B16HDRX_PWR5V_SW_pwr5v_sel 0x0238 |
| #define LSb32HDRX_PWR5V_SW_pwr5v_sel 1 |
| #define LSb16HDRX_PWR5V_SW_pwr5v_sel 1 |
| #define bHDRX_PWR5V_SW_pwr5v_sel 1 |
| #define MSK32HDRX_PWR5V_SW_pwr5v_sel 0x00000002 |
| #define RA_HDRX_GF_CTRL 0x023C |
| #define BA_HDRX_GF_CTRL_gf_ctrl 0x023C |
| #define B16HDRX_GF_CTRL_gf_ctrl 0x023C |
| #define LSb32HDRX_GF_CTRL_gf_ctrl 0 |
| #define LSb16HDRX_GF_CTRL_gf_ctrl 0 |
| #define bHDRX_GF_CTRL_gf_ctrl 24 |
| #define MSK32HDRX_GF_CTRL_gf_ctrl 0x00FFFFFF |
| #define RA_HDRX_HDCP_CTRL 0x0240 |
| #define BA_HDRX_HDCP_CTRL_enc_en 0x0240 |
| #define B16HDRX_HDCP_CTRL_enc_en 0x0240 |
| #define LSb32HDRX_HDCP_CTRL_enc_en 0 |
| #define LSb16HDRX_HDCP_CTRL_enc_en 0 |
| #define bHDRX_HDCP_CTRL_enc_en 1 |
| #define MSK32HDRX_HDCP_CTRL_enc_en 0x00000001 |
| #define BA_HDRX_HDCP_CTRL_hdcp_version 0x0240 |
| #define B16HDRX_HDCP_CTRL_hdcp_version 0x0240 |
| #define LSb32HDRX_HDCP_CTRL_hdcp_version 1 |
| #define LSb16HDRX_HDCP_CTRL_hdcp_version 1 |
| #define bHDRX_HDCP_CTRL_hdcp_version 1 |
| #define MSK32HDRX_HDCP_CTRL_hdcp_version 0x00000002 |
| #define BA_HDRX_HDCP_CTRL_ainfo_ctrl 0x0240 |
| #define B16HDRX_HDCP_CTRL_ainfo_ctrl 0x0240 |
| #define LSb32HDRX_HDCP_CTRL_ainfo_ctrl 2 |
| #define LSb16HDRX_HDCP_CTRL_ainfo_ctrl 2 |
| #define bHDRX_HDCP_CTRL_ainfo_ctrl 1 |
| #define MSK32HDRX_HDCP_CTRL_ainfo_ctrl 0x00000004 |
| #define BA_HDRX_HDCP_CTRL_eess_win 0x0240 |
| #define B16HDRX_HDCP_CTRL_eess_win 0x0240 |
| #define LSb32HDRX_HDCP_CTRL_eess_win 3 |
| #define LSb16HDRX_HDCP_CTRL_eess_win 3 |
| #define bHDRX_HDCP_CTRL_eess_win 4 |
| #define MSK32HDRX_HDCP_CTRL_eess_win 0x00000078 |
| #define BA_HDRX_HDCP_CTRL_km_sel 0x0240 |
| #define B16HDRX_HDCP_CTRL_km_sel 0x0240 |
| #define LSb32HDRX_HDCP_CTRL_km_sel 7 |
| #define LSb16HDRX_HDCP_CTRL_km_sel 7 |
| #define bHDRX_HDCP_CTRL_km_sel 1 |
| #define MSK32HDRX_HDCP_CTRL_km_sel 0x00000080 |
| #define BA_HDRX_HDCP_CTRL_sw_ri 0x0241 |
| #define B16HDRX_HDCP_CTRL_sw_ri 0x0240 |
| #define LSb32HDRX_HDCP_CTRL_sw_ri 8 |
| #define LSb16HDRX_HDCP_CTRL_sw_ri 8 |
| #define bHDRX_HDCP_CTRL_sw_ri 1 |
| #define MSK32HDRX_HDCP_CTRL_sw_ri 0x00000100 |
| #define BA_HDRX_HDCP_CTRL_sw_pj 0x0241 |
| #define B16HDRX_HDCP_CTRL_sw_pj 0x0240 |
| #define LSb32HDRX_HDCP_CTRL_sw_pj 9 |
| #define LSb16HDRX_HDCP_CTRL_sw_pj 9 |
| #define bHDRX_HDCP_CTRL_sw_pj 1 |
| #define MSK32HDRX_HDCP_CTRL_sw_pj 0x00000200 |
| #define BA_HDRX_HDCP_CTRL_sw_i2c_sl_ack 0x0241 |
| #define B16HDRX_HDCP_CTRL_sw_i2c_sl_ack 0x0240 |
| #define LSb32HDRX_HDCP_CTRL_sw_i2c_sl_ack 10 |
| #define LSb16HDRX_HDCP_CTRL_sw_i2c_sl_ack 10 |
| #define bHDRX_HDCP_CTRL_sw_i2c_sl_ack 1 |
| #define MSK32HDRX_HDCP_CTRL_sw_i2c_sl_ack 0x00000400 |
| #define BA_HDRX_HDCP_CTRL_i2c_en 0x0241 |
| #define B16HDRX_HDCP_CTRL_i2c_en 0x0240 |
| #define LSb32HDRX_HDCP_CTRL_i2c_en 11 |
| #define LSb16HDRX_HDCP_CTRL_i2c_en 11 |
| #define bHDRX_HDCP_CTRL_i2c_en 1 |
| #define MSK32HDRX_HDCP_CTRL_i2c_en 0x00000800 |
| #define BA_HDRX_HDCP_CTRL_decrypt_en 0x0241 |
| #define B16HDRX_HDCP_CTRL_decrypt_en 0x0240 |
| #define LSb32HDRX_HDCP_CTRL_decrypt_en 12 |
| #define LSb16HDRX_HDCP_CTRL_decrypt_en 12 |
| #define bHDRX_HDCP_CTRL_decrypt_en 1 |
| #define MSK32HDRX_HDCP_CTRL_decrypt_en 0x00001000 |
| #define BA_HDRX_HDCP_CTRL_l_prime_rdy_sel 0x0241 |
| #define B16HDRX_HDCP_CTRL_l_prime_rdy_sel 0x0240 |
| #define LSb32HDRX_HDCP_CTRL_l_prime_rdy_sel 13 |
| #define LSb16HDRX_HDCP_CTRL_l_prime_rdy_sel 13 |
| #define bHDRX_HDCP_CTRL_l_prime_rdy_sel 1 |
| #define MSK32HDRX_HDCP_CTRL_l_prime_rdy_sel 0x00002000 |
| #define BA_HDRX_HDCP_CTRL_l_prime_rdy_sw 0x0241 |
| #define B16HDRX_HDCP_CTRL_l_prime_rdy_sw 0x0240 |
| #define LSb32HDRX_HDCP_CTRL_l_prime_rdy_sw 14 |
| #define LSb16HDRX_HDCP_CTRL_l_prime_rdy_sw 14 |
| #define bHDRX_HDCP_CTRL_l_prime_rdy_sw 1 |
| #define MSK32HDRX_HDCP_CTRL_l_prime_rdy_sw 0x00004000 |
| #define BA_HDRX_HDCP_CTRL_eess_sel 0x0241 |
| #define B16HDRX_HDCP_CTRL_eess_sel 0x0240 |
| #define LSb32HDRX_HDCP_CTRL_eess_sel 15 |
| #define LSb16HDRX_HDCP_CTRL_eess_sel 15 |
| #define bHDRX_HDCP_CTRL_eess_sel 1 |
| #define MSK32HDRX_HDCP_CTRL_eess_sel 0x00008000 |
| #define RA_HDRX_HDCP_BCAPS 0x0244 |
| #define BA_HDRX_HDCP_BCAPS_bcaps 0x0244 |
| #define B16HDRX_HDCP_BCAPS_bcaps 0x0244 |
| #define LSb32HDRX_HDCP_BCAPS_bcaps 0 |
| #define LSb16HDRX_HDCP_BCAPS_bcaps 0 |
| #define bHDRX_HDCP_BCAPS_bcaps 8 |
| #define MSK32HDRX_HDCP_BCAPS_bcaps 0x000000FF |
| #define RA_HDRX_HDCP_KM 0x0248 |
| #define BA_HDRX_HDCP_KM_bytes_0_to_3 0x0248 |
| #define B16HDRX_HDCP_KM_bytes_0_to_3 0x0248 |
| #define LSb32HDRX_HDCP_KM_bytes_0_to_3 0 |
| #define LSb16HDRX_HDCP_KM_bytes_0_to_3 0 |
| #define bHDRX_HDCP_KM_bytes_0_to_3 32 |
| #define MSK32HDRX_HDCP_KM_bytes_0_to_3 0xFFFFFFFF |
| #define RA_HDRX_HDCP_KM1 0x024C |
| #define BA_HDRX_HDCP_KM_bytes_4_to_6 0x024C |
| #define B16HDRX_HDCP_KM_bytes_4_to_6 0x024C |
| #define LSb32HDRX_HDCP_KM_bytes_4_to_6 0 |
| #define LSb16HDRX_HDCP_KM_bytes_4_to_6 0 |
| #define bHDRX_HDCP_KM_bytes_4_to_6 24 |
| #define MSK32HDRX_HDCP_KM_bytes_4_to_6 0x00FFFFFF |
| #define RA_HDRX_HDCP_AINFO 0x0250 |
| #define BA_HDRX_HDCP_AINFO_ainfo 0x0250 |
| #define B16HDRX_HDCP_AINFO_ainfo 0x0250 |
| #define LSb32HDRX_HDCP_AINFO_ainfo 0 |
| #define LSb16HDRX_HDCP_AINFO_ainfo 0 |
| #define bHDRX_HDCP_AINFO_ainfo 8 |
| #define MSK32HDRX_HDCP_AINFO_ainfo 0x000000FF |
| #define RA_HDRX_HDCP_STATUS 0x0254 |
| #define BA_HDRX_HDCP_STATUS_status 0x0254 |
| #define B16HDRX_HDCP_STATUS_status 0x0254 |
| #define LSb32HDRX_HDCP_STATUS_status 0 |
| #define LSb16HDRX_HDCP_STATUS_status 0 |
| #define bHDRX_HDCP_STATUS_status 5 |
| #define MSK32HDRX_HDCP_STATUS_status 0x0000001F |
| #define RA_HDRX_HDCP_BKSV 0x0258 |
| #define BA_HDRX_HDCP_BKSV_bytes_0_to_3 0x0258 |
| #define B16HDRX_HDCP_BKSV_bytes_0_to_3 0x0258 |
| #define LSb32HDRX_HDCP_BKSV_bytes_0_to_3 0 |
| #define LSb16HDRX_HDCP_BKSV_bytes_0_to_3 0 |
| #define bHDRX_HDCP_BKSV_bytes_0_to_3 32 |
| #define MSK32HDRX_HDCP_BKSV_bytes_0_to_3 0xFFFFFFFF |
| #define RA_HDRX_HDCP_BKSV1 0x025C |
| #define BA_HDRX_HDCP_BKSV_byte_4 0x025C |
| #define B16HDRX_HDCP_BKSV_byte_4 0x025C |
| #define LSb32HDRX_HDCP_BKSV_byte_4 0 |
| #define LSb16HDRX_HDCP_BKSV_byte_4 0 |
| #define bHDRX_HDCP_BKSV_byte_4 8 |
| #define MSK32HDRX_HDCP_BKSV_byte_4 0x000000FF |
| #define RA_HDRX_HDCP_AKSV 0x0260 |
| #define BA_HDRX_HDCP_AKSV_bytes_0_to_3 0x0260 |
| #define B16HDRX_HDCP_AKSV_bytes_0_to_3 0x0260 |
| #define LSb32HDRX_HDCP_AKSV_bytes_0_to_3 0 |
| #define LSb16HDRX_HDCP_AKSV_bytes_0_to_3 0 |
| #define bHDRX_HDCP_AKSV_bytes_0_to_3 32 |
| #define MSK32HDRX_HDCP_AKSV_bytes_0_to_3 0xFFFFFFFF |
| #define RA_HDRX_HDCP_AKSV1 0x0264 |
| #define BA_HDRX_HDCP_AKSV_byte_4 0x0264 |
| #define B16HDRX_HDCP_AKSV_byte_4 0x0264 |
| #define LSb32HDRX_HDCP_AKSV_byte_4 0 |
| #define LSb16HDRX_HDCP_AKSV_byte_4 0 |
| #define bHDRX_HDCP_AKSV_byte_4 8 |
| #define MSK32HDRX_HDCP_AKSV_byte_4 0x000000FF |
| #define RA_HDRX_HDCP_AN 0x0268 |
| #define BA_HDRX_HDCP_AN_bytes_0_to_3 0x0268 |
| #define B16HDRX_HDCP_AN_bytes_0_to_3 0x0268 |
| #define LSb32HDRX_HDCP_AN_bytes_0_to_3 0 |
| #define LSb16HDRX_HDCP_AN_bytes_0_to_3 0 |
| #define bHDRX_HDCP_AN_bytes_0_to_3 32 |
| #define MSK32HDRX_HDCP_AN_bytes_0_to_3 0xFFFFFFFF |
| #define RA_HDRX_HDCP_AN1 0x026C |
| #define BA_HDRX_HDCP_AN_bytes_4_to_7 0x026C |
| #define B16HDRX_HDCP_AN_bytes_4_to_7 0x026C |
| #define LSb32HDRX_HDCP_AN_bytes_4_to_7 0 |
| #define LSb16HDRX_HDCP_AN_bytes_4_to_7 0 |
| #define bHDRX_HDCP_AN_bytes_4_to_7 32 |
| #define MSK32HDRX_HDCP_AN_bytes_4_to_7 0xFFFFFFFF |
| #define RA_HDRX_HDCP_M0 0x0270 |
| #define BA_HDRX_HDCP_M0_bytes_0_to_3 0x0270 |
| #define B16HDRX_HDCP_M0_bytes_0_to_3 0x0270 |
| #define LSb32HDRX_HDCP_M0_bytes_0_to_3 0 |
| #define LSb16HDRX_HDCP_M0_bytes_0_to_3 0 |
| #define bHDRX_HDCP_M0_bytes_0_to_3 32 |
| #define MSK32HDRX_HDCP_M0_bytes_0_to_3 0xFFFFFFFF |
| #define RA_HDRX_HDCP_M01 0x0274 |
| #define BA_HDRX_HDCP_M0_bytes_4_to_7 0x0274 |
| #define B16HDRX_HDCP_M0_bytes_4_to_7 0x0274 |
| #define LSb32HDRX_HDCP_M0_bytes_4_to_7 0 |
| #define LSb16HDRX_HDCP_M0_bytes_4_to_7 0 |
| #define bHDRX_HDCP_M0_bytes_4_to_7 32 |
| #define MSK32HDRX_HDCP_M0_bytes_4_to_7 0xFFFFFFFF |
| #define RA_HDRX_HDCP_BSTATUS 0x0278 |
| #define BA_HDRX_HDCP_BSTATUS_bstatus 0x0278 |
| #define B16HDRX_HDCP_BSTATUS_bstatus 0x0278 |
| #define LSb32HDRX_HDCP_BSTATUS_bstatus 0 |
| #define LSb16HDRX_HDCP_BSTATUS_bstatus 0 |
| #define bHDRX_HDCP_BSTATUS_bstatus 16 |
| #define MSK32HDRX_HDCP_BSTATUS_bstatus 0x0000FFFF |
| #define RA_HDRX_HDCP_BSTATUS_HW 0x027C |
| #define BA_HDRX_HDCP_BSTATUS_HW_mode 0x027C |
| #define B16HDRX_HDCP_BSTATUS_HW_mode 0x027C |
| #define LSb32HDRX_HDCP_BSTATUS_HW_mode 0 |
| #define LSb16HDRX_HDCP_BSTATUS_HW_mode 0 |
| #define bHDRX_HDCP_BSTATUS_HW_mode 1 |
| #define MSK32HDRX_HDCP_BSTATUS_HW_mode 0x00000001 |
| #define RA_HDRX_HDCP_PJ 0x0280 |
| #define BA_HDRX_HDCP_PJ_pj 0x0280 |
| #define B16HDRX_HDCP_PJ_pj 0x0280 |
| #define LSb32HDRX_HDCP_PJ_pj 0 |
| #define LSb16HDRX_HDCP_PJ_pj 0 |
| #define bHDRX_HDCP_PJ_pj 8 |
| #define MSK32HDRX_HDCP_PJ_pj 0x000000FF |
| #define RA_HDRX_HDCP_RI 0x0284 |
| #define BA_HDRX_HDCP_RI_ri 0x0284 |
| #define B16HDRX_HDCP_RI_ri 0x0284 |
| #define LSb32HDRX_HDCP_RI_ri 0 |
| #define LSb16HDRX_HDCP_RI_ri 0 |
| #define bHDRX_HDCP_RI_ri 16 |
| #define MSK32HDRX_HDCP_RI_ri 0x0000FFFF |
| #define RA_HDRX_HDCP_DBG 0x0288 |
| #define BA_HDRX_HDCP_DBG_ri_val 0x0288 |
| #define B16HDRX_HDCP_DBG_ri_val 0x0288 |
| #define LSb32HDRX_HDCP_DBG_ri_val 0 |
| #define LSb16HDRX_HDCP_DBG_ri_val 0 |
| #define bHDRX_HDCP_DBG_ri_val 16 |
| #define MSK32HDRX_HDCP_DBG_ri_val 0x0000FFFF |
| #define BA_HDRX_HDCP_DBG_pj_val 0x028A |
| #define B16HDRX_HDCP_DBG_pj_val 0x028A |
| #define LSb32HDRX_HDCP_DBG_pj_val 16 |
| #define LSb16HDRX_HDCP_DBG_pj_val 0 |
| #define bHDRX_HDCP_DBG_pj_val 8 |
| #define MSK32HDRX_HDCP_DBG_pj_val 0x00FF0000 |
| #define BA_HDRX_HDCP_DBG_frm_cnt 0x028B |
| #define B16HDRX_HDCP_DBG_frm_cnt 0x028A |
| #define LSb32HDRX_HDCP_DBG_frm_cnt 24 |
| #define LSb16HDRX_HDCP_DBG_frm_cnt 8 |
| #define bHDRX_HDCP_DBG_frm_cnt 8 |
| #define MSK32HDRX_HDCP_DBG_frm_cnt 0xFF000000 |
| #define RA_HDRX_HDCP_DBG1 0x028C |
| #define BA_HDRX_HDCP_DBG_first_state 0x028C |
| #define B16HDRX_HDCP_DBG_first_state 0x028C |
| #define LSb32HDRX_HDCP_DBG_first_state 0 |
| #define LSb16HDRX_HDCP_DBG_first_state 0 |
| #define bHDRX_HDCP_DBG_first_state 2 |
| #define MSK32HDRX_HDCP_DBG_first_state 0x00000003 |
| #define BA_HDRX_HDCP_DBG_enc_en 0x028C |
| #define B16HDRX_HDCP_DBG_enc_en 0x028C |
| #define LSb32HDRX_HDCP_DBG_enc_en 2 |
| #define LSb16HDRX_HDCP_DBG_enc_en 2 |
| #define bHDRX_HDCP_DBG_enc_en 1 |
| #define MSK32HDRX_HDCP_DBG_enc_en 0x00000004 |
| #define BA_HDRX_HDCP_DBG_enc_dis 0x028C |
| #define B16HDRX_HDCP_DBG_enc_dis 0x028C |
| #define LSb32HDRX_HDCP_DBG_enc_dis 3 |
| #define LSb16HDRX_HDCP_DBG_enc_dis 3 |
| #define bHDRX_HDCP_DBG_enc_dis 1 |
| #define MSK32HDRX_HDCP_DBG_enc_dis 0x00000008 |
| #define BA_HDRX_HDCP_DBG_second_state 0x028C |
| #define B16HDRX_HDCP_DBG_second_state 0x028C |
| #define LSb32HDRX_HDCP_DBG_second_state 4 |
| #define LSb16HDRX_HDCP_DBG_second_state 4 |
| #define bHDRX_HDCP_DBG_second_state 4 |
| #define MSK32HDRX_HDCP_DBG_second_state 0x000000F0 |
| #define RA_HDRX_HDCP_VH 0x0290 |
| #define BA_HDRX_HDCP_VH_vh0 0x0290 |
| #define B16HDRX_HDCP_VH_vh0 0x0290 |
| #define LSb32HDRX_HDCP_VH_vh0 0 |
| #define LSb16HDRX_HDCP_VH_vh0 0 |
| #define bHDRX_HDCP_VH_vh0 32 |
| #define MSK32HDRX_HDCP_VH_vh0 0xFFFFFFFF |
| #define RA_HDRX_HDCP_VH1 0x0294 |
| #define BA_HDRX_HDCP_VH_vh1 0x0294 |
| #define B16HDRX_HDCP_VH_vh1 0x0294 |
| #define LSb32HDRX_HDCP_VH_vh1 0 |
| #define LSb16HDRX_HDCP_VH_vh1 0 |
| #define bHDRX_HDCP_VH_vh1 32 |
| #define MSK32HDRX_HDCP_VH_vh1 0xFFFFFFFF |
| #define RA_HDRX_HDCP_VH2 0x0298 |
| #define BA_HDRX_HDCP_VH_vh2 0x0298 |
| #define B16HDRX_HDCP_VH_vh2 0x0298 |
| #define LSb32HDRX_HDCP_VH_vh2 0 |
| #define LSb16HDRX_HDCP_VH_vh2 0 |
| #define bHDRX_HDCP_VH_vh2 32 |
| #define MSK32HDRX_HDCP_VH_vh2 0xFFFFFFFF |
| #define RA_HDRX_HDCP_VH3 0x029C |
| #define BA_HDRX_HDCP_VH_vh3 0x029C |
| #define B16HDRX_HDCP_VH_vh3 0x029C |
| #define LSb32HDRX_HDCP_VH_vh3 0 |
| #define LSb16HDRX_HDCP_VH_vh3 0 |
| #define bHDRX_HDCP_VH_vh3 32 |
| #define MSK32HDRX_HDCP_VH_vh3 0xFFFFFFFF |
| #define RA_HDRX_HDCP_VH4 0x02A0 |
| #define BA_HDRX_HDCP_VH_vh4 0x02A0 |
| #define B16HDRX_HDCP_VH_vh4 0x02A0 |
| #define LSb32HDRX_HDCP_VH_vh4 0 |
| #define LSb16HDRX_HDCP_VH_vh4 0 |
| #define bHDRX_HDCP_VH_vh4 32 |
| #define MSK32HDRX_HDCP_VH_vh4 0xFFFFFFFF |
| #define RA_HDRX_HDCP_KSV_FIFO 0x02A4 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte0 0x02A4 |
| #define B16HDRX_HDCP_KSV_FIFO_byte0 0x02A4 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte0 0 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte0 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte0 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte0 0x000000FF |
| #define BA_HDRX_HDCP_KSV_FIFO_byte1 0x02A5 |
| #define B16HDRX_HDCP_KSV_FIFO_byte1 0x02A4 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte1 8 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte1 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte1 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte1 0x0000FF00 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte2 0x02A6 |
| #define B16HDRX_HDCP_KSV_FIFO_byte2 0x02A6 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte2 16 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte2 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte2 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte2 0x00FF0000 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte3 0x02A7 |
| #define B16HDRX_HDCP_KSV_FIFO_byte3 0x02A6 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte3 24 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte3 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte3 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte3 0xFF000000 |
| #define RA_HDRX_HDCP_KSV_FIFO1 0x02A8 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte4 0x02A8 |
| #define B16HDRX_HDCP_KSV_FIFO_byte4 0x02A8 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte4 0 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte4 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte4 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte4 0x000000FF |
| #define BA_HDRX_HDCP_KSV_FIFO_byte5 0x02A9 |
| #define B16HDRX_HDCP_KSV_FIFO_byte5 0x02A8 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte5 8 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte5 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte5 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte5 0x0000FF00 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte6 0x02AA |
| #define B16HDRX_HDCP_KSV_FIFO_byte6 0x02AA |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte6 16 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte6 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte6 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte6 0x00FF0000 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte7 0x02AB |
| #define B16HDRX_HDCP_KSV_FIFO_byte7 0x02AA |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte7 24 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte7 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte7 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte7 0xFF000000 |
| #define RA_HDRX_HDCP_KSV_FIFO2 0x02AC |
| #define BA_HDRX_HDCP_KSV_FIFO_byte8 0x02AC |
| #define B16HDRX_HDCP_KSV_FIFO_byte8 0x02AC |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte8 0 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte8 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte8 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte8 0x000000FF |
| #define BA_HDRX_HDCP_KSV_FIFO_byte9 0x02AD |
| #define B16HDRX_HDCP_KSV_FIFO_byte9 0x02AC |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte9 8 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte9 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte9 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte9 0x0000FF00 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte10 0x02AE |
| #define B16HDRX_HDCP_KSV_FIFO_byte10 0x02AE |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte10 16 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte10 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte10 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte10 0x00FF0000 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte11 0x02AF |
| #define B16HDRX_HDCP_KSV_FIFO_byte11 0x02AE |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte11 24 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte11 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte11 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte11 0xFF000000 |
| #define RA_HDRX_HDCP_KSV_FIFO3 0x02B0 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte12 0x02B0 |
| #define B16HDRX_HDCP_KSV_FIFO_byte12 0x02B0 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte12 0 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte12 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte12 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte12 0x000000FF |
| #define BA_HDRX_HDCP_KSV_FIFO_byte13 0x02B1 |
| #define B16HDRX_HDCP_KSV_FIFO_byte13 0x02B0 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte13 8 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte13 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte13 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte13 0x0000FF00 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte14 0x02B2 |
| #define B16HDRX_HDCP_KSV_FIFO_byte14 0x02B2 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte14 16 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte14 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte14 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte14 0x00FF0000 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte15 0x02B3 |
| #define B16HDRX_HDCP_KSV_FIFO_byte15 0x02B2 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte15 24 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte15 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte15 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte15 0xFF000000 |
| #define RA_HDRX_HDCP_KSV_FIFO4 0x02B4 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte16 0x02B4 |
| #define B16HDRX_HDCP_KSV_FIFO_byte16 0x02B4 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte16 0 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte16 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte16 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte16 0x000000FF |
| #define BA_HDRX_HDCP_KSV_FIFO_byte17 0x02B5 |
| #define B16HDRX_HDCP_KSV_FIFO_byte17 0x02B4 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte17 8 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte17 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte17 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte17 0x0000FF00 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte18 0x02B6 |
| #define B16HDRX_HDCP_KSV_FIFO_byte18 0x02B6 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte18 16 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte18 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte18 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte18 0x00FF0000 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte19 0x02B7 |
| #define B16HDRX_HDCP_KSV_FIFO_byte19 0x02B6 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte19 24 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte19 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte19 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte19 0xFF000000 |
| #define RA_HDRX_HDCP_KSV_FIFO5 0x02B8 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte20 0x02B8 |
| #define B16HDRX_HDCP_KSV_FIFO_byte20 0x02B8 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte20 0 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte20 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte20 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte20 0x000000FF |
| #define BA_HDRX_HDCP_KSV_FIFO_byte21 0x02B9 |
| #define B16HDRX_HDCP_KSV_FIFO_byte21 0x02B8 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte21 8 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte21 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte21 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte21 0x0000FF00 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte22 0x02BA |
| #define B16HDRX_HDCP_KSV_FIFO_byte22 0x02BA |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte22 16 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte22 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte22 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte22 0x00FF0000 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte23 0x02BB |
| #define B16HDRX_HDCP_KSV_FIFO_byte23 0x02BA |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte23 24 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte23 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte23 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte23 0xFF000000 |
| #define RA_HDRX_HDCP_KSV_FIFO6 0x02BC |
| #define BA_HDRX_HDCP_KSV_FIFO_byte24 0x02BC |
| #define B16HDRX_HDCP_KSV_FIFO_byte24 0x02BC |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte24 0 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte24 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte24 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte24 0x000000FF |
| #define BA_HDRX_HDCP_KSV_FIFO_byte25 0x02BD |
| #define B16HDRX_HDCP_KSV_FIFO_byte25 0x02BC |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte25 8 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte25 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte25 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte25 0x0000FF00 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte26 0x02BE |
| #define B16HDRX_HDCP_KSV_FIFO_byte26 0x02BE |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte26 16 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte26 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte26 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte26 0x00FF0000 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte27 0x02BF |
| #define B16HDRX_HDCP_KSV_FIFO_byte27 0x02BE |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte27 24 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte27 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte27 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte27 0xFF000000 |
| #define RA_HDRX_HDCP_KSV_FIFO7 0x02C0 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte28 0x02C0 |
| #define B16HDRX_HDCP_KSV_FIFO_byte28 0x02C0 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte28 0 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte28 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte28 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte28 0x000000FF |
| #define BA_HDRX_HDCP_KSV_FIFO_byte29 0x02C1 |
| #define B16HDRX_HDCP_KSV_FIFO_byte29 0x02C0 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte29 8 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte29 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte29 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte29 0x0000FF00 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte30 0x02C2 |
| #define B16HDRX_HDCP_KSV_FIFO_byte30 0x02C2 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte30 16 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte30 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte30 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte30 0x00FF0000 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte31 0x02C3 |
| #define B16HDRX_HDCP_KSV_FIFO_byte31 0x02C2 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte31 24 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte31 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte31 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte31 0xFF000000 |
| #define RA_HDRX_HDCP_KSV_FIFO8 0x02C4 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte32 0x02C4 |
| #define B16HDRX_HDCP_KSV_FIFO_byte32 0x02C4 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte32 0 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte32 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte32 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte32 0x000000FF |
| #define BA_HDRX_HDCP_KSV_FIFO_byte33 0x02C5 |
| #define B16HDRX_HDCP_KSV_FIFO_byte33 0x02C4 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte33 8 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte33 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte33 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte33 0x0000FF00 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte34 0x02C6 |
| #define B16HDRX_HDCP_KSV_FIFO_byte34 0x02C6 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte34 16 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte34 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte34 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte34 0x00FF0000 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte35 0x02C7 |
| #define B16HDRX_HDCP_KSV_FIFO_byte35 0x02C6 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte35 24 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte35 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte35 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte35 0xFF000000 |
| #define RA_HDRX_HDCP_KSV_FIFO9 0x02C8 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte36 0x02C8 |
| #define B16HDRX_HDCP_KSV_FIFO_byte36 0x02C8 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte36 0 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte36 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte36 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte36 0x000000FF |
| #define BA_HDRX_HDCP_KSV_FIFO_byte37 0x02C9 |
| #define B16HDRX_HDCP_KSV_FIFO_byte37 0x02C8 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte37 8 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte37 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte37 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte37 0x0000FF00 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte38 0x02CA |
| #define B16HDRX_HDCP_KSV_FIFO_byte38 0x02CA |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte38 16 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte38 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte38 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte38 0x00FF0000 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte39 0x02CB |
| #define B16HDRX_HDCP_KSV_FIFO_byte39 0x02CA |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte39 24 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte39 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte39 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte39 0xFF000000 |
| #define RA_HDRX_HDCP_KSV_FIFO10 0x02CC |
| #define BA_HDRX_HDCP_KSV_FIFO_byte40 0x02CC |
| #define B16HDRX_HDCP_KSV_FIFO_byte40 0x02CC |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte40 0 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte40 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte40 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte40 0x000000FF |
| #define BA_HDRX_HDCP_KSV_FIFO_byte41 0x02CD |
| #define B16HDRX_HDCP_KSV_FIFO_byte41 0x02CC |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte41 8 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte41 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte41 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte41 0x0000FF00 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte42 0x02CE |
| #define B16HDRX_HDCP_KSV_FIFO_byte42 0x02CE |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte42 16 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte42 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte42 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte42 0x00FF0000 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte43 0x02CF |
| #define B16HDRX_HDCP_KSV_FIFO_byte43 0x02CE |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte43 24 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte43 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte43 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte43 0xFF000000 |
| #define RA_HDRX_HDCP_KSV_FIFO11 0x02D0 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte44 0x02D0 |
| #define B16HDRX_HDCP_KSV_FIFO_byte44 0x02D0 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte44 0 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte44 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte44 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte44 0x000000FF |
| #define BA_HDRX_HDCP_KSV_FIFO_byte45 0x02D1 |
| #define B16HDRX_HDCP_KSV_FIFO_byte45 0x02D0 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte45 8 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte45 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte45 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte45 0x0000FF00 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte46 0x02D2 |
| #define B16HDRX_HDCP_KSV_FIFO_byte46 0x02D2 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte46 16 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte46 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte46 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte46 0x00FF0000 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte47 0x02D3 |
| #define B16HDRX_HDCP_KSV_FIFO_byte47 0x02D2 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte47 24 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte47 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte47 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte47 0xFF000000 |
| #define RA_HDRX_HDCP_KSV_FIFO12 0x02D4 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte48 0x02D4 |
| #define B16HDRX_HDCP_KSV_FIFO_byte48 0x02D4 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte48 0 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte48 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte48 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte48 0x000000FF |
| #define BA_HDRX_HDCP_KSV_FIFO_byte49 0x02D5 |
| #define B16HDRX_HDCP_KSV_FIFO_byte49 0x02D4 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte49 8 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte49 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte49 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte49 0x0000FF00 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte50 0x02D6 |
| #define B16HDRX_HDCP_KSV_FIFO_byte50 0x02D6 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte50 16 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte50 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte50 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte50 0x00FF0000 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte51 0x02D7 |
| #define B16HDRX_HDCP_KSV_FIFO_byte51 0x02D6 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte51 24 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte51 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte51 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte51 0xFF000000 |
| #define RA_HDRX_HDCP_KSV_FIFO13 0x02D8 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte52 0x02D8 |
| #define B16HDRX_HDCP_KSV_FIFO_byte52 0x02D8 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte52 0 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte52 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte52 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte52 0x000000FF |
| #define BA_HDRX_HDCP_KSV_FIFO_byte53 0x02D9 |
| #define B16HDRX_HDCP_KSV_FIFO_byte53 0x02D8 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte53 8 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte53 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte53 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte53 0x0000FF00 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte54 0x02DA |
| #define B16HDRX_HDCP_KSV_FIFO_byte54 0x02DA |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte54 16 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte54 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte54 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte54 0x00FF0000 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte55 0x02DB |
| #define B16HDRX_HDCP_KSV_FIFO_byte55 0x02DA |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte55 24 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte55 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte55 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte55 0xFF000000 |
| #define RA_HDRX_HDCP_KSV_FIFO14 0x02DC |
| #define BA_HDRX_HDCP_KSV_FIFO_byte56 0x02DC |
| #define B16HDRX_HDCP_KSV_FIFO_byte56 0x02DC |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte56 0 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte56 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte56 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte56 0x000000FF |
| #define BA_HDRX_HDCP_KSV_FIFO_byte57 0x02DD |
| #define B16HDRX_HDCP_KSV_FIFO_byte57 0x02DC |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte57 8 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte57 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte57 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte57 0x0000FF00 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte58 0x02DE |
| #define B16HDRX_HDCP_KSV_FIFO_byte58 0x02DE |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte58 16 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte58 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte58 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte58 0x00FF0000 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte59 0x02DF |
| #define B16HDRX_HDCP_KSV_FIFO_byte59 0x02DE |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte59 24 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte59 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte59 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte59 0xFF000000 |
| #define RA_HDRX_HDCP_KSV_FIFO15 0x02E0 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte60 0x02E0 |
| #define B16HDRX_HDCP_KSV_FIFO_byte60 0x02E0 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte60 0 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte60 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte60 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte60 0x000000FF |
| #define BA_HDRX_HDCP_KSV_FIFO_byte61 0x02E1 |
| #define B16HDRX_HDCP_KSV_FIFO_byte61 0x02E0 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte61 8 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte61 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte61 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte61 0x0000FF00 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte62 0x02E2 |
| #define B16HDRX_HDCP_KSV_FIFO_byte62 0x02E2 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte62 16 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte62 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte62 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte62 0x00FF0000 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte63 0x02E3 |
| #define B16HDRX_HDCP_KSV_FIFO_byte63 0x02E2 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte63 24 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte63 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte63 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte63 0xFF000000 |
| #define RA_HDRX_HDCP_KSV_FIFO16 0x02E4 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte64 0x02E4 |
| #define B16HDRX_HDCP_KSV_FIFO_byte64 0x02E4 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte64 0 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte64 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte64 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte64 0x000000FF |
| #define BA_HDRX_HDCP_KSV_FIFO_byte65 0x02E5 |
| #define B16HDRX_HDCP_KSV_FIFO_byte65 0x02E4 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte65 8 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte65 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte65 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte65 0x0000FF00 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte66 0x02E6 |
| #define B16HDRX_HDCP_KSV_FIFO_byte66 0x02E6 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte66 16 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte66 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte66 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte66 0x00FF0000 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte67 0x02E7 |
| #define B16HDRX_HDCP_KSV_FIFO_byte67 0x02E6 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte67 24 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte67 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte67 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte67 0xFF000000 |
| #define RA_HDRX_HDCP_KSV_FIFO17 0x02E8 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte68 0x02E8 |
| #define B16HDRX_HDCP_KSV_FIFO_byte68 0x02E8 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte68 0 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte68 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte68 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte68 0x000000FF |
| #define BA_HDRX_HDCP_KSV_FIFO_byte69 0x02E9 |
| #define B16HDRX_HDCP_KSV_FIFO_byte69 0x02E8 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte69 8 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte69 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte69 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte69 0x0000FF00 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte70 0x02EA |
| #define B16HDRX_HDCP_KSV_FIFO_byte70 0x02EA |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte70 16 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte70 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte70 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte70 0x00FF0000 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte71 0x02EB |
| #define B16HDRX_HDCP_KSV_FIFO_byte71 0x02EA |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte71 24 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte71 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte71 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte71 0xFF000000 |
| #define RA_HDRX_HDCP_KSV_FIFO18 0x02EC |
| #define BA_HDRX_HDCP_KSV_FIFO_byte72 0x02EC |
| #define B16HDRX_HDCP_KSV_FIFO_byte72 0x02EC |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte72 0 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte72 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte72 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte72 0x000000FF |
| #define BA_HDRX_HDCP_KSV_FIFO_byte73 0x02ED |
| #define B16HDRX_HDCP_KSV_FIFO_byte73 0x02EC |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte73 8 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte73 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte73 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte73 0x0000FF00 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte74 0x02EE |
| #define B16HDRX_HDCP_KSV_FIFO_byte74 0x02EE |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte74 16 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte74 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte74 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte74 0x00FF0000 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte75 0x02EF |
| #define B16HDRX_HDCP_KSV_FIFO_byte75 0x02EE |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte75 24 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte75 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte75 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte75 0xFF000000 |
| #define RA_HDRX_HDCP_KSV_FIFO19 0x02F0 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte76 0x02F0 |
| #define B16HDRX_HDCP_KSV_FIFO_byte76 0x02F0 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte76 0 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte76 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte76 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte76 0x000000FF |
| #define BA_HDRX_HDCP_KSV_FIFO_byte77 0x02F1 |
| #define B16HDRX_HDCP_KSV_FIFO_byte77 0x02F0 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte77 8 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte77 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte77 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte77 0x0000FF00 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte78 0x02F2 |
| #define B16HDRX_HDCP_KSV_FIFO_byte78 0x02F2 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte78 16 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte78 0 |
| #define bHDRX_HDCP_KSV_FIFO_byte78 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte78 0x00FF0000 |
| #define BA_HDRX_HDCP_KSV_FIFO_byte79 0x02F3 |
| #define B16HDRX_HDCP_KSV_FIFO_byte79 0x02F2 |
| #define LSb32HDRX_HDCP_KSV_FIFO_byte79 24 |
| #define LSb16HDRX_HDCP_KSV_FIFO_byte79 8 |
| #define bHDRX_HDCP_KSV_FIFO_byte79 8 |
| #define MSK32HDRX_HDCP_KSV_FIFO_byte79 0xFF000000 |
| #define RA_HDRX_BKEYS 0x02F4 |
| #define BA_HDRX_BKEYS_key0_0_to_31 0x02F4 |
| #define B16HDRX_BKEYS_key0_0_to_31 0x02F4 |
| #define LSb32HDRX_BKEYS_key0_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key0_0_to_31 0 |
| #define bHDRX_BKEYS_key0_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key0_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS1 0x02F8 |
| #define BA_HDRX_BKEYS_key0_32_to_55 0x02F8 |
| #define B16HDRX_BKEYS_key0_32_to_55 0x02F8 |
| #define LSb32HDRX_BKEYS_key0_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key0_32_to_55 0 |
| #define bHDRX_BKEYS_key0_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key0_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS2 0x02FC |
| #define BA_HDRX_BKEYS_key1_0_to_31 0x02FC |
| #define B16HDRX_BKEYS_key1_0_to_31 0x02FC |
| #define LSb32HDRX_BKEYS_key1_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key1_0_to_31 0 |
| #define bHDRX_BKEYS_key1_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key1_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS3 0x0300 |
| #define BA_HDRX_BKEYS_key1_32_to_55 0x0300 |
| #define B16HDRX_BKEYS_key1_32_to_55 0x0300 |
| #define LSb32HDRX_BKEYS_key1_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key1_32_to_55 0 |
| #define bHDRX_BKEYS_key1_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key1_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS4 0x0304 |
| #define BA_HDRX_BKEYS_key2_0_to_31 0x0304 |
| #define B16HDRX_BKEYS_key2_0_to_31 0x0304 |
| #define LSb32HDRX_BKEYS_key2_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key2_0_to_31 0 |
| #define bHDRX_BKEYS_key2_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key2_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS5 0x0308 |
| #define BA_HDRX_BKEYS_key2_32_to_55 0x0308 |
| #define B16HDRX_BKEYS_key2_32_to_55 0x0308 |
| #define LSb32HDRX_BKEYS_key2_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key2_32_to_55 0 |
| #define bHDRX_BKEYS_key2_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key2_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS6 0x030C |
| #define BA_HDRX_BKEYS_key3_0_to_31 0x030C |
| #define B16HDRX_BKEYS_key3_0_to_31 0x030C |
| #define LSb32HDRX_BKEYS_key3_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key3_0_to_31 0 |
| #define bHDRX_BKEYS_key3_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key3_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS7 0x0310 |
| #define BA_HDRX_BKEYS_key3_32_to_55 0x0310 |
| #define B16HDRX_BKEYS_key3_32_to_55 0x0310 |
| #define LSb32HDRX_BKEYS_key3_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key3_32_to_55 0 |
| #define bHDRX_BKEYS_key3_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key3_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS8 0x0314 |
| #define BA_HDRX_BKEYS_key4_0_to_31 0x0314 |
| #define B16HDRX_BKEYS_key4_0_to_31 0x0314 |
| #define LSb32HDRX_BKEYS_key4_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key4_0_to_31 0 |
| #define bHDRX_BKEYS_key4_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key4_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS9 0x0318 |
| #define BA_HDRX_BKEYS_key4_32_to_55 0x0318 |
| #define B16HDRX_BKEYS_key4_32_to_55 0x0318 |
| #define LSb32HDRX_BKEYS_key4_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key4_32_to_55 0 |
| #define bHDRX_BKEYS_key4_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key4_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS10 0x031C |
| #define BA_HDRX_BKEYS_key5_0_to_31 0x031C |
| #define B16HDRX_BKEYS_key5_0_to_31 0x031C |
| #define LSb32HDRX_BKEYS_key5_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key5_0_to_31 0 |
| #define bHDRX_BKEYS_key5_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key5_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS11 0x0320 |
| #define BA_HDRX_BKEYS_key5_32_to_55 0x0320 |
| #define B16HDRX_BKEYS_key5_32_to_55 0x0320 |
| #define LSb32HDRX_BKEYS_key5_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key5_32_to_55 0 |
| #define bHDRX_BKEYS_key5_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key5_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS12 0x0324 |
| #define BA_HDRX_BKEYS_key6_0_to_31 0x0324 |
| #define B16HDRX_BKEYS_key6_0_to_31 0x0324 |
| #define LSb32HDRX_BKEYS_key6_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key6_0_to_31 0 |
| #define bHDRX_BKEYS_key6_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key6_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS13 0x0328 |
| #define BA_HDRX_BKEYS_key6_32_to_55 0x0328 |
| #define B16HDRX_BKEYS_key6_32_to_55 0x0328 |
| #define LSb32HDRX_BKEYS_key6_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key6_32_to_55 0 |
| #define bHDRX_BKEYS_key6_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key6_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS14 0x032C |
| #define BA_HDRX_BKEYS_key7_0_to_31 0x032C |
| #define B16HDRX_BKEYS_key7_0_to_31 0x032C |
| #define LSb32HDRX_BKEYS_key7_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key7_0_to_31 0 |
| #define bHDRX_BKEYS_key7_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key7_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS15 0x0330 |
| #define BA_HDRX_BKEYS_key7_32_to_55 0x0330 |
| #define B16HDRX_BKEYS_key7_32_to_55 0x0330 |
| #define LSb32HDRX_BKEYS_key7_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key7_32_to_55 0 |
| #define bHDRX_BKEYS_key7_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key7_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS16 0x0334 |
| #define BA_HDRX_BKEYS_key8_0_to_31 0x0334 |
| #define B16HDRX_BKEYS_key8_0_to_31 0x0334 |
| #define LSb32HDRX_BKEYS_key8_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key8_0_to_31 0 |
| #define bHDRX_BKEYS_key8_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key8_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS17 0x0338 |
| #define BA_HDRX_BKEYS_key8_32_to_55 0x0338 |
| #define B16HDRX_BKEYS_key8_32_to_55 0x0338 |
| #define LSb32HDRX_BKEYS_key8_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key8_32_to_55 0 |
| #define bHDRX_BKEYS_key8_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key8_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS18 0x033C |
| #define BA_HDRX_BKEYS_key9_0_to_31 0x033C |
| #define B16HDRX_BKEYS_key9_0_to_31 0x033C |
| #define LSb32HDRX_BKEYS_key9_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key9_0_to_31 0 |
| #define bHDRX_BKEYS_key9_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key9_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS19 0x0340 |
| #define BA_HDRX_BKEYS_key9_32_to_55 0x0340 |
| #define B16HDRX_BKEYS_key9_32_to_55 0x0340 |
| #define LSb32HDRX_BKEYS_key9_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key9_32_to_55 0 |
| #define bHDRX_BKEYS_key9_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key9_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS20 0x0344 |
| #define BA_HDRX_BKEYS_key10_0_to_31 0x0344 |
| #define B16HDRX_BKEYS_key10_0_to_31 0x0344 |
| #define LSb32HDRX_BKEYS_key10_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key10_0_to_31 0 |
| #define bHDRX_BKEYS_key10_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key10_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS21 0x0348 |
| #define BA_HDRX_BKEYS_key10_32_to_55 0x0348 |
| #define B16HDRX_BKEYS_key10_32_to_55 0x0348 |
| #define LSb32HDRX_BKEYS_key10_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key10_32_to_55 0 |
| #define bHDRX_BKEYS_key10_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key10_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS22 0x034C |
| #define BA_HDRX_BKEYS_key11_0_to_31 0x034C |
| #define B16HDRX_BKEYS_key11_0_to_31 0x034C |
| #define LSb32HDRX_BKEYS_key11_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key11_0_to_31 0 |
| #define bHDRX_BKEYS_key11_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key11_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS23 0x0350 |
| #define BA_HDRX_BKEYS_key11_32_to_55 0x0350 |
| #define B16HDRX_BKEYS_key11_32_to_55 0x0350 |
| #define LSb32HDRX_BKEYS_key11_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key11_32_to_55 0 |
| #define bHDRX_BKEYS_key11_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key11_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS24 0x0354 |
| #define BA_HDRX_BKEYS_key12_0_to_31 0x0354 |
| #define B16HDRX_BKEYS_key12_0_to_31 0x0354 |
| #define LSb32HDRX_BKEYS_key12_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key12_0_to_31 0 |
| #define bHDRX_BKEYS_key12_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key12_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS25 0x0358 |
| #define BA_HDRX_BKEYS_key12_32_to_55 0x0358 |
| #define B16HDRX_BKEYS_key12_32_to_55 0x0358 |
| #define LSb32HDRX_BKEYS_key12_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key12_32_to_55 0 |
| #define bHDRX_BKEYS_key12_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key12_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS26 0x035C |
| #define BA_HDRX_BKEYS_key13_0_to_31 0x035C |
| #define B16HDRX_BKEYS_key13_0_to_31 0x035C |
| #define LSb32HDRX_BKEYS_key13_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key13_0_to_31 0 |
| #define bHDRX_BKEYS_key13_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key13_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS27 0x0360 |
| #define BA_HDRX_BKEYS_key13_32_to_55 0x0360 |
| #define B16HDRX_BKEYS_key13_32_to_55 0x0360 |
| #define LSb32HDRX_BKEYS_key13_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key13_32_to_55 0 |
| #define bHDRX_BKEYS_key13_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key13_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS28 0x0364 |
| #define BA_HDRX_BKEYS_key14_0_to_31 0x0364 |
| #define B16HDRX_BKEYS_key14_0_to_31 0x0364 |
| #define LSb32HDRX_BKEYS_key14_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key14_0_to_31 0 |
| #define bHDRX_BKEYS_key14_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key14_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS29 0x0368 |
| #define BA_HDRX_BKEYS_key14_32_to_55 0x0368 |
| #define B16HDRX_BKEYS_key14_32_to_55 0x0368 |
| #define LSb32HDRX_BKEYS_key14_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key14_32_to_55 0 |
| #define bHDRX_BKEYS_key14_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key14_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS30 0x036C |
| #define BA_HDRX_BKEYS_key15_0_to_31 0x036C |
| #define B16HDRX_BKEYS_key15_0_to_31 0x036C |
| #define LSb32HDRX_BKEYS_key15_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key15_0_to_31 0 |
| #define bHDRX_BKEYS_key15_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key15_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS31 0x0370 |
| #define BA_HDRX_BKEYS_key15_32_to_55 0x0370 |
| #define B16HDRX_BKEYS_key15_32_to_55 0x0370 |
| #define LSb32HDRX_BKEYS_key15_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key15_32_to_55 0 |
| #define bHDRX_BKEYS_key15_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key15_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS32 0x0374 |
| #define BA_HDRX_BKEYS_key16_0_to_31 0x0374 |
| #define B16HDRX_BKEYS_key16_0_to_31 0x0374 |
| #define LSb32HDRX_BKEYS_key16_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key16_0_to_31 0 |
| #define bHDRX_BKEYS_key16_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key16_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS33 0x0378 |
| #define BA_HDRX_BKEYS_key16_32_to_55 0x0378 |
| #define B16HDRX_BKEYS_key16_32_to_55 0x0378 |
| #define LSb32HDRX_BKEYS_key16_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key16_32_to_55 0 |
| #define bHDRX_BKEYS_key16_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key16_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS34 0x037C |
| #define BA_HDRX_BKEYS_key17_0_to_31 0x037C |
| #define B16HDRX_BKEYS_key17_0_to_31 0x037C |
| #define LSb32HDRX_BKEYS_key17_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key17_0_to_31 0 |
| #define bHDRX_BKEYS_key17_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key17_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS35 0x0380 |
| #define BA_HDRX_BKEYS_key17_32_to_55 0x0380 |
| #define B16HDRX_BKEYS_key17_32_to_55 0x0380 |
| #define LSb32HDRX_BKEYS_key17_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key17_32_to_55 0 |
| #define bHDRX_BKEYS_key17_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key17_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS36 0x0384 |
| #define BA_HDRX_BKEYS_key18_0_to_31 0x0384 |
| #define B16HDRX_BKEYS_key18_0_to_31 0x0384 |
| #define LSb32HDRX_BKEYS_key18_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key18_0_to_31 0 |
| #define bHDRX_BKEYS_key18_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key18_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS37 0x0388 |
| #define BA_HDRX_BKEYS_key18_32_to_55 0x0388 |
| #define B16HDRX_BKEYS_key18_32_to_55 0x0388 |
| #define LSb32HDRX_BKEYS_key18_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key18_32_to_55 0 |
| #define bHDRX_BKEYS_key18_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key18_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS38 0x038C |
| #define BA_HDRX_BKEYS_key19_0_to_31 0x038C |
| #define B16HDRX_BKEYS_key19_0_to_31 0x038C |
| #define LSb32HDRX_BKEYS_key19_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key19_0_to_31 0 |
| #define bHDRX_BKEYS_key19_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key19_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS39 0x0390 |
| #define BA_HDRX_BKEYS_key19_32_to_55 0x0390 |
| #define B16HDRX_BKEYS_key19_32_to_55 0x0390 |
| #define LSb32HDRX_BKEYS_key19_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key19_32_to_55 0 |
| #define bHDRX_BKEYS_key19_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key19_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS40 0x0394 |
| #define BA_HDRX_BKEYS_key20_0_to_31 0x0394 |
| #define B16HDRX_BKEYS_key20_0_to_31 0x0394 |
| #define LSb32HDRX_BKEYS_key20_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key20_0_to_31 0 |
| #define bHDRX_BKEYS_key20_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key20_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS41 0x0398 |
| #define BA_HDRX_BKEYS_key20_32_to_55 0x0398 |
| #define B16HDRX_BKEYS_key20_32_to_55 0x0398 |
| #define LSb32HDRX_BKEYS_key20_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key20_32_to_55 0 |
| #define bHDRX_BKEYS_key20_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key20_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS42 0x039C |
| #define BA_HDRX_BKEYS_key21_0_to_31 0x039C |
| #define B16HDRX_BKEYS_key21_0_to_31 0x039C |
| #define LSb32HDRX_BKEYS_key21_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key21_0_to_31 0 |
| #define bHDRX_BKEYS_key21_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key21_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS43 0x03A0 |
| #define BA_HDRX_BKEYS_key21_32_to_55 0x03A0 |
| #define B16HDRX_BKEYS_key21_32_to_55 0x03A0 |
| #define LSb32HDRX_BKEYS_key21_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key21_32_to_55 0 |
| #define bHDRX_BKEYS_key21_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key21_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS44 0x03A4 |
| #define BA_HDRX_BKEYS_key22_0_to_31 0x03A4 |
| #define B16HDRX_BKEYS_key22_0_to_31 0x03A4 |
| #define LSb32HDRX_BKEYS_key22_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key22_0_to_31 0 |
| #define bHDRX_BKEYS_key22_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key22_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS45 0x03A8 |
| #define BA_HDRX_BKEYS_key22_32_to_55 0x03A8 |
| #define B16HDRX_BKEYS_key22_32_to_55 0x03A8 |
| #define LSb32HDRX_BKEYS_key22_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key22_32_to_55 0 |
| #define bHDRX_BKEYS_key22_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key22_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS46 0x03AC |
| #define BA_HDRX_BKEYS_key23_0_to_31 0x03AC |
| #define B16HDRX_BKEYS_key23_0_to_31 0x03AC |
| #define LSb32HDRX_BKEYS_key23_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key23_0_to_31 0 |
| #define bHDRX_BKEYS_key23_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key23_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS47 0x03B0 |
| #define BA_HDRX_BKEYS_key23_32_to_55 0x03B0 |
| #define B16HDRX_BKEYS_key23_32_to_55 0x03B0 |
| #define LSb32HDRX_BKEYS_key23_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key23_32_to_55 0 |
| #define bHDRX_BKEYS_key23_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key23_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS48 0x03B4 |
| #define BA_HDRX_BKEYS_key24_0_to_31 0x03B4 |
| #define B16HDRX_BKEYS_key24_0_to_31 0x03B4 |
| #define LSb32HDRX_BKEYS_key24_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key24_0_to_31 0 |
| #define bHDRX_BKEYS_key24_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key24_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS49 0x03B8 |
| #define BA_HDRX_BKEYS_key24_32_to_55 0x03B8 |
| #define B16HDRX_BKEYS_key24_32_to_55 0x03B8 |
| #define LSb32HDRX_BKEYS_key24_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key24_32_to_55 0 |
| #define bHDRX_BKEYS_key24_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key24_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS50 0x03BC |
| #define BA_HDRX_BKEYS_key25_0_to_31 0x03BC |
| #define B16HDRX_BKEYS_key25_0_to_31 0x03BC |
| #define LSb32HDRX_BKEYS_key25_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key25_0_to_31 0 |
| #define bHDRX_BKEYS_key25_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key25_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS51 0x03C0 |
| #define BA_HDRX_BKEYS_key25_32_to_55 0x03C0 |
| #define B16HDRX_BKEYS_key25_32_to_55 0x03C0 |
| #define LSb32HDRX_BKEYS_key25_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key25_32_to_55 0 |
| #define bHDRX_BKEYS_key25_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key25_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS52 0x03C4 |
| #define BA_HDRX_BKEYS_key26_0_to_31 0x03C4 |
| #define B16HDRX_BKEYS_key26_0_to_31 0x03C4 |
| #define LSb32HDRX_BKEYS_key26_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key26_0_to_31 0 |
| #define bHDRX_BKEYS_key26_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key26_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS53 0x03C8 |
| #define BA_HDRX_BKEYS_key26_32_to_55 0x03C8 |
| #define B16HDRX_BKEYS_key26_32_to_55 0x03C8 |
| #define LSb32HDRX_BKEYS_key26_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key26_32_to_55 0 |
| #define bHDRX_BKEYS_key26_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key26_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS54 0x03CC |
| #define BA_HDRX_BKEYS_key27_0_to_31 0x03CC |
| #define B16HDRX_BKEYS_key27_0_to_31 0x03CC |
| #define LSb32HDRX_BKEYS_key27_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key27_0_to_31 0 |
| #define bHDRX_BKEYS_key27_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key27_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS55 0x03D0 |
| #define BA_HDRX_BKEYS_key27_32_to_55 0x03D0 |
| #define B16HDRX_BKEYS_key27_32_to_55 0x03D0 |
| #define LSb32HDRX_BKEYS_key27_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key27_32_to_55 0 |
| #define bHDRX_BKEYS_key27_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key27_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS56 0x03D4 |
| #define BA_HDRX_BKEYS_key28_0_to_31 0x03D4 |
| #define B16HDRX_BKEYS_key28_0_to_31 0x03D4 |
| #define LSb32HDRX_BKEYS_key28_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key28_0_to_31 0 |
| #define bHDRX_BKEYS_key28_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key28_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS57 0x03D8 |
| #define BA_HDRX_BKEYS_key28_32_to_55 0x03D8 |
| #define B16HDRX_BKEYS_key28_32_to_55 0x03D8 |
| #define LSb32HDRX_BKEYS_key28_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key28_32_to_55 0 |
| #define bHDRX_BKEYS_key28_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key28_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS58 0x03DC |
| #define BA_HDRX_BKEYS_key29_0_to_31 0x03DC |
| #define B16HDRX_BKEYS_key29_0_to_31 0x03DC |
| #define LSb32HDRX_BKEYS_key29_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key29_0_to_31 0 |
| #define bHDRX_BKEYS_key29_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key29_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS59 0x03E0 |
| #define BA_HDRX_BKEYS_key29_32_to_55 0x03E0 |
| #define B16HDRX_BKEYS_key29_32_to_55 0x03E0 |
| #define LSb32HDRX_BKEYS_key29_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key29_32_to_55 0 |
| #define bHDRX_BKEYS_key29_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key29_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS60 0x03E4 |
| #define BA_HDRX_BKEYS_key30_0_to_31 0x03E4 |
| #define B16HDRX_BKEYS_key30_0_to_31 0x03E4 |
| #define LSb32HDRX_BKEYS_key30_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key30_0_to_31 0 |
| #define bHDRX_BKEYS_key30_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key30_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS61 0x03E8 |
| #define BA_HDRX_BKEYS_key30_32_to_55 0x03E8 |
| #define B16HDRX_BKEYS_key30_32_to_55 0x03E8 |
| #define LSb32HDRX_BKEYS_key30_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key30_32_to_55 0 |
| #define bHDRX_BKEYS_key30_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key30_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS62 0x03EC |
| #define BA_HDRX_BKEYS_key31_0_to_31 0x03EC |
| #define B16HDRX_BKEYS_key31_0_to_31 0x03EC |
| #define LSb32HDRX_BKEYS_key31_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key31_0_to_31 0 |
| #define bHDRX_BKEYS_key31_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key31_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS63 0x03F0 |
| #define BA_HDRX_BKEYS_key31_32_to_55 0x03F0 |
| #define B16HDRX_BKEYS_key31_32_to_55 0x03F0 |
| #define LSb32HDRX_BKEYS_key31_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key31_32_to_55 0 |
| #define bHDRX_BKEYS_key31_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key31_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS64 0x03F4 |
| #define BA_HDRX_BKEYS_key32_0_to_31 0x03F4 |
| #define B16HDRX_BKEYS_key32_0_to_31 0x03F4 |
| #define LSb32HDRX_BKEYS_key32_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key32_0_to_31 0 |
| #define bHDRX_BKEYS_key32_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key32_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS65 0x03F8 |
| #define BA_HDRX_BKEYS_key32_32_to_55 0x03F8 |
| #define B16HDRX_BKEYS_key32_32_to_55 0x03F8 |
| #define LSb32HDRX_BKEYS_key32_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key32_32_to_55 0 |
| #define bHDRX_BKEYS_key32_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key32_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS66 0x03FC |
| #define BA_HDRX_BKEYS_key33_0_to_31 0x03FC |
| #define B16HDRX_BKEYS_key33_0_to_31 0x03FC |
| #define LSb32HDRX_BKEYS_key33_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key33_0_to_31 0 |
| #define bHDRX_BKEYS_key33_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key33_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS67 0x0400 |
| #define BA_HDRX_BKEYS_key33_32_to_55 0x0400 |
| #define B16HDRX_BKEYS_key33_32_to_55 0x0400 |
| #define LSb32HDRX_BKEYS_key33_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key33_32_to_55 0 |
| #define bHDRX_BKEYS_key33_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key33_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS68 0x0404 |
| #define BA_HDRX_BKEYS_key34_0_to_31 0x0404 |
| #define B16HDRX_BKEYS_key34_0_to_31 0x0404 |
| #define LSb32HDRX_BKEYS_key34_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key34_0_to_31 0 |
| #define bHDRX_BKEYS_key34_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key34_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS69 0x0408 |
| #define BA_HDRX_BKEYS_key34_32_to_55 0x0408 |
| #define B16HDRX_BKEYS_key34_32_to_55 0x0408 |
| #define LSb32HDRX_BKEYS_key34_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key34_32_to_55 0 |
| #define bHDRX_BKEYS_key34_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key34_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS70 0x040C |
| #define BA_HDRX_BKEYS_key35_0_to_31 0x040C |
| #define B16HDRX_BKEYS_key35_0_to_31 0x040C |
| #define LSb32HDRX_BKEYS_key35_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key35_0_to_31 0 |
| #define bHDRX_BKEYS_key35_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key35_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS71 0x0410 |
| #define BA_HDRX_BKEYS_key35_32_to_55 0x0410 |
| #define B16HDRX_BKEYS_key35_32_to_55 0x0410 |
| #define LSb32HDRX_BKEYS_key35_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key35_32_to_55 0 |
| #define bHDRX_BKEYS_key35_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key35_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS72 0x0414 |
| #define BA_HDRX_BKEYS_key36_0_to_31 0x0414 |
| #define B16HDRX_BKEYS_key36_0_to_31 0x0414 |
| #define LSb32HDRX_BKEYS_key36_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key36_0_to_31 0 |
| #define bHDRX_BKEYS_key36_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key36_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS73 0x0418 |
| #define BA_HDRX_BKEYS_key36_32_to_55 0x0418 |
| #define B16HDRX_BKEYS_key36_32_to_55 0x0418 |
| #define LSb32HDRX_BKEYS_key36_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key36_32_to_55 0 |
| #define bHDRX_BKEYS_key36_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key36_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS74 0x041C |
| #define BA_HDRX_BKEYS_key37_0_to_31 0x041C |
| #define B16HDRX_BKEYS_key37_0_to_31 0x041C |
| #define LSb32HDRX_BKEYS_key37_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key37_0_to_31 0 |
| #define bHDRX_BKEYS_key37_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key37_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS75 0x0420 |
| #define BA_HDRX_BKEYS_key37_32_to_55 0x0420 |
| #define B16HDRX_BKEYS_key37_32_to_55 0x0420 |
| #define LSb32HDRX_BKEYS_key37_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key37_32_to_55 0 |
| #define bHDRX_BKEYS_key37_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key37_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS76 0x0424 |
| #define BA_HDRX_BKEYS_key38_0_to_31 0x0424 |
| #define B16HDRX_BKEYS_key38_0_to_31 0x0424 |
| #define LSb32HDRX_BKEYS_key38_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key38_0_to_31 0 |
| #define bHDRX_BKEYS_key38_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key38_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS77 0x0428 |
| #define BA_HDRX_BKEYS_key38_32_to_55 0x0428 |
| #define B16HDRX_BKEYS_key38_32_to_55 0x0428 |
| #define LSb32HDRX_BKEYS_key38_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key38_32_to_55 0 |
| #define bHDRX_BKEYS_key38_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key38_32_to_55 0x00FFFFFF |
| #define RA_HDRX_BKEYS78 0x042C |
| #define BA_HDRX_BKEYS_key39_0_to_31 0x042C |
| #define B16HDRX_BKEYS_key39_0_to_31 0x042C |
| #define LSb32HDRX_BKEYS_key39_0_to_31 0 |
| #define LSb16HDRX_BKEYS_key39_0_to_31 0 |
| #define bHDRX_BKEYS_key39_0_to_31 32 |
| #define MSK32HDRX_BKEYS_key39_0_to_31 0xFFFFFFFF |
| #define RA_HDRX_BKEYS79 0x0430 |
| #define BA_HDRX_BKEYS_key39_32_to_55 0x0430 |
| #define B16HDRX_BKEYS_key39_32_to_55 0x0430 |
| #define LSb32HDRX_BKEYS_key39_32_to_55 0 |
| #define LSb16HDRX_BKEYS_key39_32_to_55 0 |
| #define bHDRX_BKEYS_key39_32_to_55 24 |
| #define MSK32HDRX_BKEYS_key39_32_to_55 0x00FFFFFF |
| #define RA_HDRX_ERR_CNT_TMDS 0x0434 |
| #define BA_HDRX_ERR_CNT_TMDS_chn0_err_cnt 0x0434 |
| #define B16HDRX_ERR_CNT_TMDS_chn0_err_cnt 0x0434 |
| #define LSb32HDRX_ERR_CNT_TMDS_chn0_err_cnt 0 |
| #define LSb16HDRX_ERR_CNT_TMDS_chn0_err_cnt 0 |
| #define bHDRX_ERR_CNT_TMDS_chn0_err_cnt 16 |
| #define MSK32HDRX_ERR_CNT_TMDS_chn0_err_cnt 0x0000FFFF |
| #define BA_HDRX_ERR_CNT_TMDS_chn1_err_cnt 0x0436 |
| #define B16HDRX_ERR_CNT_TMDS_chn1_err_cnt 0x0436 |
| #define LSb32HDRX_ERR_CNT_TMDS_chn1_err_cnt 16 |
| #define LSb16HDRX_ERR_CNT_TMDS_chn1_err_cnt 0 |
| #define bHDRX_ERR_CNT_TMDS_chn1_err_cnt 16 |
| #define MSK32HDRX_ERR_CNT_TMDS_chn1_err_cnt 0xFFFF0000 |
| #define RA_HDRX_ERR_CNT_TMDS1 0x0438 |
| #define BA_HDRX_ERR_CNT_TMDS_chn2_err_cnt 0x0438 |
| #define B16HDRX_ERR_CNT_TMDS_chn2_err_cnt 0x0438 |
| #define LSb32HDRX_ERR_CNT_TMDS_chn2_err_cnt 0 |
| #define LSb16HDRX_ERR_CNT_TMDS_chn2_err_cnt 0 |
| #define bHDRX_ERR_CNT_TMDS_chn2_err_cnt 16 |
| #define MSK32HDRX_ERR_CNT_TMDS_chn2_err_cnt 0x0000FFFF |
| #define BA_HDRX_ERR_CNT_TMDS_err_cnt_checksum 0x043A |
| #define B16HDRX_ERR_CNT_TMDS_err_cnt_checksum 0x043A |
| #define LSb32HDRX_ERR_CNT_TMDS_err_cnt_checksum 16 |
| #define LSb16HDRX_ERR_CNT_TMDS_err_cnt_checksum 0 |
| #define bHDRX_ERR_CNT_TMDS_err_cnt_checksum 8 |
| #define MSK32HDRX_ERR_CNT_TMDS_err_cnt_checksum 0x00FF0000 |
| #define RA_HDRX_TMDS_CHN_LOCK 0x043C |
| #define BA_HDRX_TMDS_CHN_LOCK_tmds_err_lck_sts_reg 0x043C |
| #define B16HDRX_TMDS_CHN_LOCK_tmds_err_lck_sts_reg 0x043C |
| #define LSb32HDRX_TMDS_CHN_LOCK_tmds_err_lck_sts_reg 0 |
| #define LSb16HDRX_TMDS_CHN_LOCK_tmds_err_lck_sts_reg 0 |
| #define bHDRX_TMDS_CHN_LOCK_tmds_err_lck_sts_reg 12 |
| #define MSK32HDRX_TMDS_CHN_LOCK_tmds_err_lck_sts_reg 0x00000FFF |
| #define BA_HDRX_TMDS_CHN_LOCK_lk_sts_ovrwen 0x043D |
| #define B16HDRX_TMDS_CHN_LOCK_lk_sts_ovrwen 0x043C |
| #define LSb32HDRX_TMDS_CHN_LOCK_lk_sts_ovrwen 12 |
| #define LSb16HDRX_TMDS_CHN_LOCK_lk_sts_ovrwen 12 |
| #define bHDRX_TMDS_CHN_LOCK_lk_sts_ovrwen 1 |
| #define MSK32HDRX_TMDS_CHN_LOCK_lk_sts_ovrwen 0x00001000 |
| #define RA_HDRX_REF_CLK_PROG 0x0440 |
| #define BA_HDRX_REF_CLK_PROG_ref_clk_freq 0x0440 |
| #define B16HDRX_REF_CLK_PROG_ref_clk_freq 0x0440 |
| #define LSb32HDRX_REF_CLK_PROG_ref_clk_freq 0 |
| #define LSb16HDRX_REF_CLK_PROG_ref_clk_freq 0 |
| #define bHDRX_REF_CLK_PROG_ref_clk_freq 8 |
| #define MSK32HDRX_REF_CLK_PROG_ref_clk_freq 0x000000FF |
| #define RA_HDRX_SCDC_SLAVE 0x0444 |
| #define BA_HDRX_SCDC_SLAVE_slave_addr 0x0444 |
| #define B16HDRX_SCDC_SLAVE_slave_addr 0x0444 |
| #define LSb32HDRX_SCDC_SLAVE_slave_addr 0 |
| #define LSb16HDRX_SCDC_SLAVE_slave_addr 0 |
| #define bHDRX_SCDC_SLAVE_slave_addr 7 |
| #define MSK32HDRX_SCDC_SLAVE_slave_addr 0x0000007F |
| #define RA_HDRX_SW_HPD 0x0448 |
| #define BA_HDRX_SW_HPD_sw_hpd 0x0448 |
| #define B16HDRX_SW_HPD_sw_hpd 0x0448 |
| #define LSb32HDRX_SW_HPD_sw_hpd 0 |
| #define LSb16HDRX_SW_HPD_sw_hpd 0 |
| #define bHDRX_SW_HPD_sw_hpd 1 |
| #define MSK32HDRX_SW_HPD_sw_hpd 0x00000001 |
| #define RA_HDRX_SINK_VER 0x044C |
| #define BA_HDRX_SINK_VER_sink_ver 0x044C |
| #define B16HDRX_SINK_VER_sink_ver 0x044C |
| #define LSb32HDRX_SINK_VER_sink_ver 0 |
| #define LSb16HDRX_SINK_VER_sink_ver 0 |
| #define bHDRX_SINK_VER_sink_ver 8 |
| #define MSK32HDRX_SINK_VER_sink_ver 0x000000FF |
| #define RA_HDRX_SRC_VER 0x0450 |
| #define BA_HDRX_SRC_VER_src_ver 0x0450 |
| #define B16HDRX_SRC_VER_src_ver 0x0450 |
| #define LSb32HDRX_SRC_VER_src_ver 0 |
| #define LSb16HDRX_SRC_VER_src_ver 0 |
| #define bHDRX_SRC_VER_src_ver 8 |
| #define MSK32HDRX_SRC_VER_src_ver 0x000000FF |
| #define RA_HDRX_UPDATE_FLAG_EN 0x0454 |
| #define BA_HDRX_UPDATE_FLAG_EN_status_flag_en 0x0454 |
| #define B16HDRX_UPDATE_FLAG_EN_status_flag_en 0x0454 |
| #define LSb32HDRX_UPDATE_FLAG_EN_status_flag_en 0 |
| #define LSb16HDRX_UPDATE_FLAG_EN_status_flag_en 0 |
| #define bHDRX_UPDATE_FLAG_EN_status_flag_en 1 |
| #define MSK32HDRX_UPDATE_FLAG_EN_status_flag_en 0x00000001 |
| #define BA_HDRX_UPDATE_FLAG_EN_ced_update_en 0x0454 |
| #define B16HDRX_UPDATE_FLAG_EN_ced_update_en 0x0454 |
| #define LSb32HDRX_UPDATE_FLAG_EN_ced_update_en 1 |
| #define LSb16HDRX_UPDATE_FLAG_EN_ced_update_en 1 |
| #define bHDRX_UPDATE_FLAG_EN_ced_update_en 1 |
| #define MSK32HDRX_UPDATE_FLAG_EN_ced_update_en 0x00000002 |
| #define BA_HDRX_UPDATE_FLAG_EN_rr_test_en 0x0454 |
| #define B16HDRX_UPDATE_FLAG_EN_rr_test_en 0x0454 |
| #define LSb32HDRX_UPDATE_FLAG_EN_rr_test_en 2 |
| #define LSb16HDRX_UPDATE_FLAG_EN_rr_test_en 2 |
| #define bHDRX_UPDATE_FLAG_EN_rr_test_en 1 |
| #define MSK32HDRX_UPDATE_FLAG_EN_rr_test_en 0x00000004 |
| #define RA_HDRX_SCDC_FLAGS 0x0458 |
| #define BA_HDRX_SCDC_FLAGS_status_update 0x0458 |
| #define B16HDRX_SCDC_FLAGS_status_update 0x0458 |
| #define LSb32HDRX_SCDC_FLAGS_status_update 0 |
| #define LSb16HDRX_SCDC_FLAGS_status_update 0 |
| #define bHDRX_SCDC_FLAGS_status_update 1 |
| #define MSK32HDRX_SCDC_FLAGS_status_update 0x00000001 |
| #define BA_HDRX_SCDC_FLAGS_ced_update 0x0458 |
| #define B16HDRX_SCDC_FLAGS_ced_update 0x0458 |
| #define LSb32HDRX_SCDC_FLAGS_ced_update 1 |
| #define LSb16HDRX_SCDC_FLAGS_ced_update 1 |
| #define bHDRX_SCDC_FLAGS_ced_update 1 |
| #define MSK32HDRX_SCDC_FLAGS_ced_update 0x00000002 |
| #define BA_HDRX_SCDC_FLAGS_rr_test 0x0458 |
| #define B16HDRX_SCDC_FLAGS_rr_test 0x0458 |
| #define LSb32HDRX_SCDC_FLAGS_rr_test 2 |
| #define LSb16HDRX_SCDC_FLAGS_rr_test 2 |
| #define bHDRX_SCDC_FLAGS_rr_test 1 |
| #define MSK32HDRX_SCDC_FLAGS_rr_test 0x00000004 |
| #define BA_HDRX_SCDC_FLAGS_scrambling_en 0x0458 |
| #define B16HDRX_SCDC_FLAGS_scrambling_en 0x0458 |
| #define LSb32HDRX_SCDC_FLAGS_scrambling_en 3 |
| #define LSb16HDRX_SCDC_FLAGS_scrambling_en 3 |
| #define bHDRX_SCDC_FLAGS_scrambling_en 1 |
| #define MSK32HDRX_SCDC_FLAGS_scrambling_en 0x00000008 |
| #define BA_HDRX_SCDC_FLAGS_tmds_bit_clk_ratio 0x0458 |
| #define B16HDRX_SCDC_FLAGS_tmds_bit_clk_ratio 0x0458 |
| #define LSb32HDRX_SCDC_FLAGS_tmds_bit_clk_ratio 4 |
| #define LSb16HDRX_SCDC_FLAGS_tmds_bit_clk_ratio 4 |
| #define bHDRX_SCDC_FLAGS_tmds_bit_clk_ratio 1 |
| #define MSK32HDRX_SCDC_FLAGS_tmds_bit_clk_ratio 0x00000010 |
| #define BA_HDRX_SCDC_FLAGS_scrambler_status 0x0458 |
| #define B16HDRX_SCDC_FLAGS_scrambler_status 0x0458 |
| #define LSb32HDRX_SCDC_FLAGS_scrambler_status 5 |
| #define LSb16HDRX_SCDC_FLAGS_scrambler_status 5 |
| #define bHDRX_SCDC_FLAGS_scrambler_status 1 |
| #define MSK32HDRX_SCDC_FLAGS_scrambler_status 0x00000020 |
| #define BA_HDRX_SCDC_FLAGS_rr_enable 0x0458 |
| #define B16HDRX_SCDC_FLAGS_rr_enable 0x0458 |
| #define LSb32HDRX_SCDC_FLAGS_rr_enable 6 |
| #define LSb16HDRX_SCDC_FLAGS_rr_enable 6 |
| #define bHDRX_SCDC_FLAGS_rr_enable 1 |
| #define MSK32HDRX_SCDC_FLAGS_rr_enable 0x00000040 |
| #define BA_HDRX_SCDC_FLAGS_ch0_locked 0x0458 |
| #define B16HDRX_SCDC_FLAGS_ch0_locked 0x0458 |
| #define LSb32HDRX_SCDC_FLAGS_ch0_locked 7 |
| #define LSb16HDRX_SCDC_FLAGS_ch0_locked 7 |
| #define bHDRX_SCDC_FLAGS_ch0_locked 1 |
| #define MSK32HDRX_SCDC_FLAGS_ch0_locked 0x00000080 |
| #define BA_HDRX_SCDC_FLAGS_ch1_locked 0x0459 |
| #define B16HDRX_SCDC_FLAGS_ch1_locked 0x0458 |
| #define LSb32HDRX_SCDC_FLAGS_ch1_locked 8 |
| #define LSb16HDRX_SCDC_FLAGS_ch1_locked 8 |
| #define bHDRX_SCDC_FLAGS_ch1_locked 1 |
| #define MSK32HDRX_SCDC_FLAGS_ch1_locked 0x00000100 |
| #define BA_HDRX_SCDC_FLAGS_ch2_locked 0x0459 |
| #define B16HDRX_SCDC_FLAGS_ch2_locked 0x0458 |
| #define LSb32HDRX_SCDC_FLAGS_ch2_locked 9 |
| #define LSb16HDRX_SCDC_FLAGS_ch2_locked 9 |
| #define bHDRX_SCDC_FLAGS_ch2_locked 1 |
| #define MSK32HDRX_SCDC_FLAGS_ch2_locked 0x00000200 |
| #define BA_HDRX_SCDC_FLAGS_test_read_request_delay 0x0459 |
| #define B16HDRX_SCDC_FLAGS_test_read_request_delay 0x0458 |
| #define LSb32HDRX_SCDC_FLAGS_test_read_request_delay 10 |
| #define LSb16HDRX_SCDC_FLAGS_test_read_request_delay 10 |
| #define bHDRX_SCDC_FLAGS_test_read_request_delay 7 |
| #define MSK32HDRX_SCDC_FLAGS_test_read_request_delay 0x0001FC00 |
| #define BA_HDRX_SCDC_FLAGS_test_read_request 0x045A |
| #define B16HDRX_SCDC_FLAGS_test_read_request 0x045A |
| #define LSb32HDRX_SCDC_FLAGS_test_read_request 17 |
| #define LSb16HDRX_SCDC_FLAGS_test_read_request 1 |
| #define bHDRX_SCDC_FLAGS_test_read_request 1 |
| #define MSK32HDRX_SCDC_FLAGS_test_read_request 0x00020000 |
| #define RA_HDRX_MAN_IEEE_OUI 0x045C |
| #define BA_HDRX_MAN_IEEE_OUI_third_octet 0x045C |
| #define B16HDRX_MAN_IEEE_OUI_third_octet 0x045C |
| #define LSb32HDRX_MAN_IEEE_OUI_third_octet 0 |
| #define LSb16HDRX_MAN_IEEE_OUI_third_octet 0 |
| #define bHDRX_MAN_IEEE_OUI_third_octet 8 |
| #define MSK32HDRX_MAN_IEEE_OUI_third_octet 0x000000FF |
| #define BA_HDRX_MAN_IEEE_OUI_second_octet 0x045D |
| #define B16HDRX_MAN_IEEE_OUI_second_octet 0x045C |
| #define LSb32HDRX_MAN_IEEE_OUI_second_octet 8 |
| #define LSb16HDRX_MAN_IEEE_OUI_second_octet 8 |
| #define bHDRX_MAN_IEEE_OUI_second_octet 8 |
| #define MSK32HDRX_MAN_IEEE_OUI_second_octet 0x0000FF00 |
| #define BA_HDRX_MAN_IEEE_OUI_first_octet 0x045E |
| #define B16HDRX_MAN_IEEE_OUI_first_octet 0x045E |
| #define LSb32HDRX_MAN_IEEE_OUI_first_octet 16 |
| #define LSb16HDRX_MAN_IEEE_OUI_first_octet 0 |
| #define bHDRX_MAN_IEEE_OUI_first_octet 8 |
| #define MSK32HDRX_MAN_IEEE_OUI_first_octet 0x00FF0000 |
| #define RA_HDRX_DEVICE_ID 0x0460 |
| #define BA_HDRX_DEVICE_ID_string0 0x0460 |
| #define B16HDRX_DEVICE_ID_string0 0x0460 |
| #define LSb32HDRX_DEVICE_ID_string0 0 |
| #define LSb16HDRX_DEVICE_ID_string0 0 |
| #define bHDRX_DEVICE_ID_string0 32 |
| #define MSK32HDRX_DEVICE_ID_string0 0xFFFFFFFF |
| #define RA_HDRX_DEVICE_ID1 0x0464 |
| #define BA_HDRX_DEVICE_ID_string1 0x0464 |
| #define B16HDRX_DEVICE_ID_string1 0x0464 |
| #define LSb32HDRX_DEVICE_ID_string1 0 |
| #define LSb16HDRX_DEVICE_ID_string1 0 |
| #define bHDRX_DEVICE_ID_string1 32 |
| #define MSK32HDRX_DEVICE_ID_string1 0xFFFFFFFF |
| #define RA_HDRX_DEVICE_ID2 0x0468 |
| #define BA_HDRX_DEVICE_ID_hw_revision 0x0468 |
| #define B16HDRX_DEVICE_ID_hw_revision 0x0468 |
| #define LSb32HDRX_DEVICE_ID_hw_revision 0 |
| #define LSb16HDRX_DEVICE_ID_hw_revision 0 |
| #define bHDRX_DEVICE_ID_hw_revision 8 |
| #define MSK32HDRX_DEVICE_ID_hw_revision 0x000000FF |
| #define BA_HDRX_DEVICE_ID_sw_major_rev 0x0469 |
| #define B16HDRX_DEVICE_ID_sw_major_rev 0x0468 |
| #define LSb32HDRX_DEVICE_ID_sw_major_rev 8 |
| #define LSb16HDRX_DEVICE_ID_sw_major_rev 8 |
| #define bHDRX_DEVICE_ID_sw_major_rev 8 |
| #define MSK32HDRX_DEVICE_ID_sw_major_rev 0x0000FF00 |
| #define BA_HDRX_DEVICE_ID_sw_minor_rev 0x046A |
| #define B16HDRX_DEVICE_ID_sw_minor_rev 0x046A |
| #define LSb32HDRX_DEVICE_ID_sw_minor_rev 16 |
| #define LSb16HDRX_DEVICE_ID_sw_minor_rev 0 |
| #define bHDRX_DEVICE_ID_sw_minor_rev 8 |
| #define MSK32HDRX_DEVICE_ID_sw_minor_rev 0x00FF0000 |
| #define RA_HDRX_MAN_SPECIFIC 0x046C |
| #define BA_HDRX_MAN_SPECIFIC_regs_0_3 0x046C |
| #define B16HDRX_MAN_SPECIFIC_regs_0_3 0x046C |
| #define LSb32HDRX_MAN_SPECIFIC_regs_0_3 0 |
| #define LSb16HDRX_MAN_SPECIFIC_regs_0_3 0 |
| #define bHDRX_MAN_SPECIFIC_regs_0_3 32 |
| #define MSK32HDRX_MAN_SPECIFIC_regs_0_3 0xFFFFFFFF |
| #define RA_HDRX_MAN_SPECIFIC1 0x0470 |
| #define BA_HDRX_MAN_SPECIFIC_regs_4_7 0x0470 |
| #define B16HDRX_MAN_SPECIFIC_regs_4_7 0x0470 |
| #define LSb32HDRX_MAN_SPECIFIC_regs_4_7 0 |
| #define LSb16HDRX_MAN_SPECIFIC_regs_4_7 0 |
| #define bHDRX_MAN_SPECIFIC_regs_4_7 32 |
| #define MSK32HDRX_MAN_SPECIFIC_regs_4_7 0xFFFFFFFF |
| #define RA_HDRX_MAN_SPECIFIC2 0x0474 |
| #define BA_HDRX_MAN_SPECIFIC_regs_8_11 0x0474 |
| #define B16HDRX_MAN_SPECIFIC_regs_8_11 0x0474 |
| #define LSb32HDRX_MAN_SPECIFIC_regs_8_11 0 |
| #define LSb16HDRX_MAN_SPECIFIC_regs_8_11 0 |
| #define bHDRX_MAN_SPECIFIC_regs_8_11 32 |
| #define MSK32HDRX_MAN_SPECIFIC_regs_8_11 0xFFFFFFFF |
| #define RA_HDRX_MAN_SPECIFIC3 0x0478 |
| #define BA_HDRX_MAN_SPECIFIC_regs_12_15 0x0478 |
| #define B16HDRX_MAN_SPECIFIC_regs_12_15 0x0478 |
| #define LSb32HDRX_MAN_SPECIFIC_regs_12_15 0 |
| #define LSb16HDRX_MAN_SPECIFIC_regs_12_15 0 |
| #define bHDRX_MAN_SPECIFIC_regs_12_15 32 |
| #define MSK32HDRX_MAN_SPECIFIC_regs_12_15 0xFFFFFFFF |
| #define RA_HDRX_MAN_SPECIFIC4 0x047C |
| #define BA_HDRX_MAN_SPECIFIC_regs_16_19 0x047C |
| #define B16HDRX_MAN_SPECIFIC_regs_16_19 0x047C |
| #define LSb32HDRX_MAN_SPECIFIC_regs_16_19 0 |
| #define LSb16HDRX_MAN_SPECIFIC_regs_16_19 0 |
| #define bHDRX_MAN_SPECIFIC_regs_16_19 32 |
| #define MSK32HDRX_MAN_SPECIFIC_regs_16_19 0xFFFFFFFF |
| #define RA_HDRX_MAN_SPECIFIC5 0x0480 |
| #define BA_HDRX_MAN_SPECIFIC_regs_20_23 0x0480 |
| #define B16HDRX_MAN_SPECIFIC_regs_20_23 0x0480 |
| #define LSb32HDRX_MAN_SPECIFIC_regs_20_23 0 |
| #define LSb16HDRX_MAN_SPECIFIC_regs_20_23 0 |
| #define bHDRX_MAN_SPECIFIC_regs_20_23 32 |
| #define MSK32HDRX_MAN_SPECIFIC_regs_20_23 0xFFFFFFFF |
| #define RA_HDRX_MAN_SPECIFIC6 0x0484 |
| #define BA_HDRX_MAN_SPECIFIC_regs_24_27 0x0484 |
| #define B16HDRX_MAN_SPECIFIC_regs_24_27 0x0484 |
| #define LSb32HDRX_MAN_SPECIFIC_regs_24_27 0 |
| #define LSb16HDRX_MAN_SPECIFIC_regs_24_27 0 |
| #define bHDRX_MAN_SPECIFIC_regs_24_27 32 |
| #define MSK32HDRX_MAN_SPECIFIC_regs_24_27 0xFFFFFFFF |
| #define RA_HDRX_MAN_SPECIFIC7 0x0488 |
| #define BA_HDRX_MAN_SPECIFIC_regs_28_31 0x0488 |
| #define B16HDRX_MAN_SPECIFIC_regs_28_31 0x0488 |
| #define LSb32HDRX_MAN_SPECIFIC_regs_28_31 0 |
| #define LSb16HDRX_MAN_SPECIFIC_regs_28_31 0 |
| #define bHDRX_MAN_SPECIFIC_regs_28_31 32 |
| #define MSK32HDRX_MAN_SPECIFIC_regs_28_31 0xFFFFFFFF |
| #define RA_HDRX_MAN_SPECIFIC8 0x048C |
| #define BA_HDRX_MAN_SPECIFIC_regs_32_33 0x048C |
| #define B16HDRX_MAN_SPECIFIC_regs_32_33 0x048C |
| #define LSb32HDRX_MAN_SPECIFIC_regs_32_33 0 |
| #define LSb16HDRX_MAN_SPECIFIC_regs_32_33 0 |
| #define bHDRX_MAN_SPECIFIC_regs_32_33 16 |
| #define MSK32HDRX_MAN_SPECIFIC_regs_32_33 0x0000FFFF |
| #define RA_HDRX_SCDC_RW_MISC 0x0490 |
| #define BA_HDRX_SCDC_RW_MISC_clock_detected_sw 0x0490 |
| #define B16HDRX_SCDC_RW_MISC_clock_detected_sw 0x0490 |
| #define LSb32HDRX_SCDC_RW_MISC_clock_detected_sw 0 |
| #define LSb16HDRX_SCDC_RW_MISC_clock_detected_sw 0 |
| #define bHDRX_SCDC_RW_MISC_clock_detected_sw 1 |
| #define MSK32HDRX_SCDC_RW_MISC_clock_detected_sw 0x00000001 |
| #define BA_HDRX_SCDC_RW_MISC_clock_detected_sel 0x0490 |
| #define B16HDRX_SCDC_RW_MISC_clock_detected_sel 0x0490 |
| #define LSb32HDRX_SCDC_RW_MISC_clock_detected_sel 1 |
| #define LSb16HDRX_SCDC_RW_MISC_clock_detected_sel 1 |
| #define bHDRX_SCDC_RW_MISC_clock_detected_sel 1 |
| #define MSK32HDRX_SCDC_RW_MISC_clock_detected_sel 0x00000002 |
| #define BA_HDRX_SCDC_RW_MISC_rr_enable_sw 0x0490 |
| #define B16HDRX_SCDC_RW_MISC_rr_enable_sw 0x0490 |
| #define LSb32HDRX_SCDC_RW_MISC_rr_enable_sw 2 |
| #define LSb16HDRX_SCDC_RW_MISC_rr_enable_sw 2 |
| #define bHDRX_SCDC_RW_MISC_rr_enable_sw 1 |
| #define MSK32HDRX_SCDC_RW_MISC_rr_enable_sw 0x00000004 |
| #define BA_HDRX_SCDC_RW_MISC_rr_enable_sel 0x0490 |
| #define B16HDRX_SCDC_RW_MISC_rr_enable_sel 0x0490 |
| #define LSb32HDRX_SCDC_RW_MISC_rr_enable_sel 3 |
| #define LSb16HDRX_SCDC_RW_MISC_rr_enable_sel 3 |
| #define bHDRX_SCDC_RW_MISC_rr_enable_sel 1 |
| #define MSK32HDRX_SCDC_RW_MISC_rr_enable_sel 0x00000008 |
| #define BA_HDRX_SCDC_RW_MISC_ced_update_set_sel 0x0490 |
| #define B16HDRX_SCDC_RW_MISC_ced_update_set_sel 0x0490 |
| #define LSb32HDRX_SCDC_RW_MISC_ced_update_set_sel 4 |
| #define LSb16HDRX_SCDC_RW_MISC_ced_update_set_sel 4 |
| #define bHDRX_SCDC_RW_MISC_ced_update_set_sel 1 |
| #define MSK32HDRX_SCDC_RW_MISC_ced_update_set_sel 0x00000010 |
| #define BA_HDRX_SCDC_RW_MISC_sw_i2c_sl_ack 0x0490 |
| #define B16HDRX_SCDC_RW_MISC_sw_i2c_sl_ack 0x0490 |
| #define LSb32HDRX_SCDC_RW_MISC_sw_i2c_sl_ack 5 |
| #define LSb16HDRX_SCDC_RW_MISC_sw_i2c_sl_ack 5 |
| #define bHDRX_SCDC_RW_MISC_sw_i2c_sl_ack 1 |
| #define MSK32HDRX_SCDC_RW_MISC_sw_i2c_sl_ack 0x00000020 |
| #define BA_HDRX_SCDC_RW_MISC_i2c_en 0x0490 |
| #define B16HDRX_SCDC_RW_MISC_i2c_en 0x0490 |
| #define LSb32HDRX_SCDC_RW_MISC_i2c_en 6 |
| #define LSb16HDRX_SCDC_RW_MISC_i2c_en 6 |
| #define bHDRX_SCDC_RW_MISC_i2c_en 1 |
| #define MSK32HDRX_SCDC_RW_MISC_i2c_en 0x00000040 |
| #define RA_HDRX_ERR_CNT_UPDATE 0x0494 |
| #define BA_HDRX_ERR_CNT_UPDATE_err_cnt_update_sw 0x0494 |
| #define B16HDRX_ERR_CNT_UPDATE_err_cnt_update_sw 0x0494 |
| #define LSb32HDRX_ERR_CNT_UPDATE_err_cnt_update_sw 0 |
| #define LSb16HDRX_ERR_CNT_UPDATE_err_cnt_update_sw 0 |
| #define bHDRX_ERR_CNT_UPDATE_err_cnt_update_sw 1 |
| #define MSK32HDRX_ERR_CNT_UPDATE_err_cnt_update_sw 0x00000001 |
| #define RA_HDRX_PHY_COMM_CTRL 0x0498 |
| #define BA_HDRX_PHY_COMM_CTRL_ipp_ctl 0x0498 |
| #define B16HDRX_PHY_COMM_CTRL_ipp_ctl 0x0498 |
| #define LSb32HDRX_PHY_COMM_CTRL_ipp_ctl 0 |
| #define LSb16HDRX_PHY_COMM_CTRL_ipp_ctl 0 |
| #define bHDRX_PHY_COMM_CTRL_ipp_ctl 3 |
| #define MSK32HDRX_PHY_COMM_CTRL_ipp_ctl 0x00000007 |
| #define BA_HDRX_PHY_COMM_CTRL_sw_dc_sel 0x0498 |
| #define B16HDRX_PHY_COMM_CTRL_sw_dc_sel 0x0498 |
| #define LSb32HDRX_PHY_COMM_CTRL_sw_dc_sel 3 |
| #define LSb16HDRX_PHY_COMM_CTRL_sw_dc_sel 3 |
| #define bHDRX_PHY_COMM_CTRL_sw_dc_sel 1 |
| #define MSK32HDRX_PHY_COMM_CTRL_sw_dc_sel 0x00000008 |
| #define RA_HDRX_PHY_PLL_CTRL 0x049C |
| #define BA_HDRX_PHY_PLL_CTRL_sel_diva_fb 0x049C |
| #define B16HDRX_PHY_PLL_CTRL_sel_diva_fb 0x049C |
| #define LSb32HDRX_PHY_PLL_CTRL_sel_diva_fb 0 |
| #define LSb16HDRX_PHY_PLL_CTRL_sel_diva_fb 0 |
| #define bHDRX_PHY_PLL_CTRL_sel_diva_fb 3 |
| #define MSK32HDRX_PHY_PLL_CTRL_sel_diva_fb 0x00000007 |
| #define BA_HDRX_PHY_PLL_CTRL_sel_divx 0x049C |
| #define B16HDRX_PHY_PLL_CTRL_sel_divx 0x049C |
| #define LSb32HDRX_PHY_PLL_CTRL_sel_divx 3 |
| #define LSb16HDRX_PHY_PLL_CTRL_sel_divx 3 |
| #define bHDRX_PHY_PLL_CTRL_sel_divx 3 |
| #define MSK32HDRX_PHY_PLL_CTRL_sel_divx 0x00000038 |
| #define BA_HDRX_PHY_PLL_CTRL_sicp 0x049C |
| #define B16HDRX_PHY_PLL_CTRL_sicp 0x049C |
| #define LSb32HDRX_PHY_PLL_CTRL_sicp 6 |
| #define LSb16HDRX_PHY_PLL_CTRL_sicp 6 |
| #define bHDRX_PHY_PLL_CTRL_sicp 5 |
| #define MSK32HDRX_PHY_PLL_CTRL_sicp 0x000007C0 |
| #define BA_HDRX_PHY_PLL_CTRL_sikvco 0x049D |
| #define B16HDRX_PHY_PLL_CTRL_sikvco 0x049C |
| #define LSb32HDRX_PHY_PLL_CTRL_sikvco 11 |
| #define LSb16HDRX_PHY_PLL_CTRL_sikvco 11 |
| #define bHDRX_PHY_PLL_CTRL_sikvco 5 |
| #define MSK32HDRX_PHY_PLL_CTRL_sikvco 0x0000F800 |
| #define BA_HDRX_PHY_PLL_CTRL_sel_dc 0x049E |
| #define B16HDRX_PHY_PLL_CTRL_sel_dc 0x049E |
| #define LSb32HDRX_PHY_PLL_CTRL_sel_dc 16 |
| #define LSb16HDRX_PHY_PLL_CTRL_sel_dc 0 |
| #define bHDRX_PHY_PLL_CTRL_sel_dc 2 |
| #define MSK32HDRX_PHY_PLL_CTRL_sel_dc 0x00030000 |
| #define BA_HDRX_PHY_PLL_CTRL_sel_420 0x049E |
| #define B16HDRX_PHY_PLL_CTRL_sel_420 0x049E |
| #define LSb32HDRX_PHY_PLL_CTRL_sel_420 18 |
| #define LSb16HDRX_PHY_PLL_CTRL_sel_420 2 |
| #define bHDRX_PHY_PLL_CTRL_sel_420 1 |
| #define MSK32HDRX_PHY_PLL_CTRL_sel_420 0x00040000 |
| #define BA_HDRX_PHY_PLL_CTRL_vref_filt_byp 0x049E |
| #define B16HDRX_PHY_PLL_CTRL_vref_filt_byp 0x049E |
| #define LSb32HDRX_PHY_PLL_CTRL_vref_filt_byp 19 |
| #define LSb16HDRX_PHY_PLL_CTRL_vref_filt_byp 3 |
| #define bHDRX_PHY_PLL_CTRL_vref_filt_byp 1 |
| #define MSK32HDRX_PHY_PLL_CTRL_vref_filt_byp 0x00080000 |
| #define BA_HDRX_PHY_PLL_CTRL_svpll 0x049E |
| #define B16HDRX_PHY_PLL_CTRL_svpll 0x049E |
| #define LSb32HDRX_PHY_PLL_CTRL_svpll 20 |
| #define LSb16HDRX_PHY_PLL_CTRL_svpll 4 |
| #define bHDRX_PHY_PLL_CTRL_svpll 2 |
| #define MSK32HDRX_PHY_PLL_CTRL_svpll 0x00300000 |
| #define BA_HDRX_PHY_PLL_CTRL_svpllh 0x049E |
| #define B16HDRX_PHY_PLL_CTRL_svpllh 0x049E |
| #define LSb32HDRX_PHY_PLL_CTRL_svpllh 22 |
| #define LSb16HDRX_PHY_PLL_CTRL_svpllh 6 |
| #define bHDRX_PHY_PLL_CTRL_svpllh 2 |
| #define MSK32HDRX_PHY_PLL_CTRL_svpllh 0x00C00000 |
| #define BA_HDRX_PHY_PLL_CTRL_svcal 0x049F |
| #define B16HDRX_PHY_PLL_CTRL_svcal 0x049E |
| #define LSb32HDRX_PHY_PLL_CTRL_svcal 24 |
| #define LSb16HDRX_PHY_PLL_CTRL_svcal 8 |
| #define bHDRX_PHY_PLL_CTRL_svcal 2 |
| #define MSK32HDRX_PHY_PLL_CTRL_svcal 0x03000000 |
| #define BA_HDRX_PHY_PLL_CTRL_lock_th 0x049F |
| #define B16HDRX_PHY_PLL_CTRL_lock_th 0x049E |
| #define LSb32HDRX_PHY_PLL_CTRL_lock_th 26 |
| #define LSb16HDRX_PHY_PLL_CTRL_lock_th 10 |
| #define bHDRX_PHY_PLL_CTRL_lock_th 4 |
| #define MSK32HDRX_PHY_PLL_CTRL_lock_th 0x3C000000 |
| #define BA_HDRX_PHY_PLL_CTRL_v2i_filt_r_adj 0x049F |
| #define B16HDRX_PHY_PLL_CTRL_v2i_filt_r_adj 0x049E |
| #define LSb32HDRX_PHY_PLL_CTRL_v2i_filt_r_adj 30 |
| #define LSb16HDRX_PHY_PLL_CTRL_v2i_filt_r_adj 14 |
| #define bHDRX_PHY_PLL_CTRL_v2i_filt_r_adj 2 |
| #define MSK32HDRX_PHY_PLL_CTRL_v2i_filt_r_adj 0xC0000000 |
| #define RA_HDRX_PHY_PLL_CTRL1 0x04A0 |
| #define BA_HDRX_PHY_PLL_CTRL_rosc_ini 0x04A0 |
| #define B16HDRX_PHY_PLL_CTRL_rosc_ini 0x04A0 |
| #define LSb32HDRX_PHY_PLL_CTRL_rosc_ini 0 |
| #define LSb16HDRX_PHY_PLL_CTRL_rosc_ini 0 |
| #define bHDRX_PHY_PLL_CTRL_rosc_ini 1 |
| #define MSK32HDRX_PHY_PLL_CTRL_rosc_ini 0x00000001 |
| #define BA_HDRX_PHY_PLL_CTRL_sel_diva_ref 0x04A0 |
| #define B16HDRX_PHY_PLL_CTRL_sel_diva_ref 0x04A0 |
| #define LSb32HDRX_PHY_PLL_CTRL_sel_diva_ref 1 |
| #define LSb16HDRX_PHY_PLL_CTRL_sel_diva_ref 1 |
| #define bHDRX_PHY_PLL_CTRL_sel_diva_ref 3 |
| #define MSK32HDRX_PHY_PLL_CTRL_sel_diva_ref 0x0000000E |
| #define BA_HDRX_PHY_PLL_CTRL_iconstctl 0x04A0 |
| #define B16HDRX_PHY_PLL_CTRL_iconstctl 0x04A0 |
| #define LSb32HDRX_PHY_PLL_CTRL_iconstctl 4 |
| #define LSb16HDRX_PHY_PLL_CTRL_iconstctl 4 |
| #define bHDRX_PHY_PLL_CTRL_iconstctl 4 |
| #define MSK32HDRX_PHY_PLL_CTRL_iconstctl 0x000000F0 |
| #define BA_HDRX_PHY_PLL_CTRL_svpllck 0x04A1 |
| #define B16HDRX_PHY_PLL_CTRL_svpllck 0x04A0 |
| #define LSb32HDRX_PHY_PLL_CTRL_svpllck 8 |
| #define LSb16HDRX_PHY_PLL_CTRL_svpllck 8 |
| #define bHDRX_PHY_PLL_CTRL_svpllck 2 |
| #define MSK32HDRX_PHY_PLL_CTRL_svpllck 0x00000300 |
| #define RA_HDRX_PHY_CLK_CTRL 0x04A4 |
| #define BA_HDRX_PHY_CLK_CTRL_rt_en_c 0x04A4 |
| #define B16HDRX_PHY_CLK_CTRL_rt_en_c 0x04A4 |
| #define LSb32HDRX_PHY_CLK_CTRL_rt_en_c 0 |
| #define LSb16HDRX_PHY_CLK_CTRL_rt_en_c 0 |
| #define bHDRX_PHY_CLK_CTRL_rt_en_c 1 |
| #define MSK32HDRX_PHY_CLK_CTRL_rt_en_c 0x00000001 |
| #define BA_HDRX_PHY_CLK_CTRL_polswap_rx_c 0x04A4 |
| #define B16HDRX_PHY_CLK_CTRL_polswap_rx_c 0x04A4 |
| #define LSb32HDRX_PHY_CLK_CTRL_polswap_rx_c 1 |
| #define LSb16HDRX_PHY_CLK_CTRL_polswap_rx_c 1 |
| #define bHDRX_PHY_CLK_CTRL_polswap_rx_c 1 |
| #define MSK32HDRX_PHY_CLK_CTRL_polswap_rx_c 0x00000002 |
| #define BA_HDRX_PHY_CLK_CTRL_chn0_clkg_enb 0x04A4 |
| #define B16HDRX_PHY_CLK_CTRL_chn0_clkg_enb 0x04A4 |
| #define LSb32HDRX_PHY_CLK_CTRL_chn0_clkg_enb 2 |
| #define LSb16HDRX_PHY_CLK_CTRL_chn0_clkg_enb 2 |
| #define bHDRX_PHY_CLK_CTRL_chn0_clkg_enb 1 |
| #define MSK32HDRX_PHY_CLK_CTRL_chn0_clkg_enb 0x00000004 |
| #define BA_HDRX_PHY_CLK_CTRL_testck_sel 0x04A4 |
| #define B16HDRX_PHY_CLK_CTRL_testck_sel 0x04A4 |
| #define LSb32HDRX_PHY_CLK_CTRL_testck_sel 3 |
| #define LSb16HDRX_PHY_CLK_CTRL_testck_sel 3 |
| #define bHDRX_PHY_CLK_CTRL_testck_sel 2 |
| #define MSK32HDRX_PHY_CLK_CTRL_testck_sel 0x00000018 |
| #define RA_HDRX_PHY_DATA_CTRL 0x04A8 |
| #define BA_HDRX_PHY_DATA_CTRL_rt_en_d 0x04A8 |
| #define B16HDRX_PHY_DATA_CTRL_rt_en_d 0x04A8 |
| #define LSb32HDRX_PHY_DATA_CTRL_rt_en_d 0 |
| #define LSb16HDRX_PHY_DATA_CTRL_rt_en_d 0 |
| #define bHDRX_PHY_DATA_CTRL_rt_en_d 1 |
| #define MSK32HDRX_PHY_DATA_CTRL_rt_en_d 0x00000001 |
| #define BA_HDRX_PHY_DATA_CTRL_eq_ctrl_ovrw_d2 0x04A8 |
| #define B16HDRX_PHY_DATA_CTRL_eq_ctrl_ovrw_d2 0x04A8 |
| #define LSb32HDRX_PHY_DATA_CTRL_eq_ctrl_ovrw_d2 1 |
| #define LSb16HDRX_PHY_DATA_CTRL_eq_ctrl_ovrw_d2 1 |
| #define bHDRX_PHY_DATA_CTRL_eq_ctrl_ovrw_d2 8 |
| #define MSK32HDRX_PHY_DATA_CTRL_eq_ctrl_ovrw_d2 0x000001FE |
| #define BA_HDRX_PHY_DATA_CTRL_eq_ctrl_ovrw_d1 0x04A9 |
| #define B16HDRX_PHY_DATA_CTRL_eq_ctrl_ovrw_d1 0x04A8 |
| #define LSb32HDRX_PHY_DATA_CTRL_eq_ctrl_ovrw_d1 9 |
| #define LSb16HDRX_PHY_DATA_CTRL_eq_ctrl_ovrw_d1 9 |
| #define bHDRX_PHY_DATA_CTRL_eq_ctrl_ovrw_d1 8 |
| #define MSK32HDRX_PHY_DATA_CTRL_eq_ctrl_ovrw_d1 0x0001FE00 |
| #define BA_HDRX_PHY_DATA_CTRL_eq_ctrl_ovrw_d0 0x04AA |
| #define B16HDRX_PHY_DATA_CTRL_eq_ctrl_ovrw_d0 0x04AA |
| #define LSb32HDRX_PHY_DATA_CTRL_eq_ctrl_ovrw_d0 17 |
| #define LSb16HDRX_PHY_DATA_CTRL_eq_ctrl_ovrw_d0 1 |
| #define bHDRX_PHY_DATA_CTRL_eq_ctrl_ovrw_d0 8 |
| #define MSK32HDRX_PHY_DATA_CTRL_eq_ctrl_ovrw_d0 0x01FE0000 |
| #define BA_HDRX_PHY_DATA_CTRL_eq_bias_d2 0x04AB |
| #define B16HDRX_PHY_DATA_CTRL_eq_bias_d2 0x04AA |
| #define LSb32HDRX_PHY_DATA_CTRL_eq_bias_d2 25 |
| #define LSb16HDRX_PHY_DATA_CTRL_eq_bias_d2 9 |
| #define bHDRX_PHY_DATA_CTRL_eq_bias_d2 2 |
| #define MSK32HDRX_PHY_DATA_CTRL_eq_bias_d2 0x06000000 |
| #define BA_HDRX_PHY_DATA_CTRL_eq_bias_d1 0x04AB |
| #define B16HDRX_PHY_DATA_CTRL_eq_bias_d1 0x04AA |
| #define LSb32HDRX_PHY_DATA_CTRL_eq_bias_d1 27 |
| #define LSb16HDRX_PHY_DATA_CTRL_eq_bias_d1 11 |
| #define bHDRX_PHY_DATA_CTRL_eq_bias_d1 2 |
| #define MSK32HDRX_PHY_DATA_CTRL_eq_bias_d1 0x18000000 |
| #define BA_HDRX_PHY_DATA_CTRL_eq_bias_d0 0x04AB |
| #define B16HDRX_PHY_DATA_CTRL_eq_bias_d0 0x04AA |
| #define LSb32HDRX_PHY_DATA_CTRL_eq_bias_d0 29 |
| #define LSb16HDRX_PHY_DATA_CTRL_eq_bias_d0 13 |
| #define bHDRX_PHY_DATA_CTRL_eq_bias_d0 2 |
| #define MSK32HDRX_PHY_DATA_CTRL_eq_bias_d0 0x60000000 |
| #define RA_HDRX_PHY_DATA_CTRL1 0x04AC |
| #define BA_HDRX_PHY_DATA_CTRL_rt_adj_c 0x04AC |
| #define B16HDRX_PHY_DATA_CTRL_rt_adj_c 0x04AC |
| #define LSb32HDRX_PHY_DATA_CTRL_rt_adj_c 0 |
| #define LSb16HDRX_PHY_DATA_CTRL_rt_adj_c 0 |
| #define bHDRX_PHY_DATA_CTRL_rt_adj_c 4 |
| #define MSK32HDRX_PHY_DATA_CTRL_rt_adj_c 0x0000000F |
| #define BA_HDRX_PHY_DATA_CTRL_rt_adj_d2 0x04AC |
| #define B16HDRX_PHY_DATA_CTRL_rt_adj_d2 0x04AC |
| #define LSb32HDRX_PHY_DATA_CTRL_rt_adj_d2 4 |
| #define LSb16HDRX_PHY_DATA_CTRL_rt_adj_d2 4 |
| #define bHDRX_PHY_DATA_CTRL_rt_adj_d2 4 |
| #define MSK32HDRX_PHY_DATA_CTRL_rt_adj_d2 0x000000F0 |
| #define BA_HDRX_PHY_DATA_CTRL_rt_adj_d1 0x04AD |
| #define B16HDRX_PHY_DATA_CTRL_rt_adj_d1 0x04AC |
| #define LSb32HDRX_PHY_DATA_CTRL_rt_adj_d1 8 |
| #define LSb16HDRX_PHY_DATA_CTRL_rt_adj_d1 8 |
| #define bHDRX_PHY_DATA_CTRL_rt_adj_d1 4 |
| #define MSK32HDRX_PHY_DATA_CTRL_rt_adj_d1 0x00000F00 |
| #define BA_HDRX_PHY_DATA_CTRL_rt_adj_d0 0x04AD |
| #define B16HDRX_PHY_DATA_CTRL_rt_adj_d0 0x04AC |
| #define LSb32HDRX_PHY_DATA_CTRL_rt_adj_d0 12 |
| #define LSb16HDRX_PHY_DATA_CTRL_rt_adj_d0 12 |
| #define bHDRX_PHY_DATA_CTRL_rt_adj_d0 4 |
| #define MSK32HDRX_PHY_DATA_CTRL_rt_adj_d0 0x0000F000 |
| #define RA_HDRX_PHY_EQ_CTRL 0x04B0 |
| #define BA_HDRX_PHY_EQ_CTRL_en 0x04B0 |
| #define B16HDRX_PHY_EQ_CTRL_en 0x04B0 |
| #define LSb32HDRX_PHY_EQ_CTRL_en 0 |
| #define LSb16HDRX_PHY_EQ_CTRL_en 0 |
| #define bHDRX_PHY_EQ_CTRL_en 1 |
| #define MSK32HDRX_PHY_EQ_CTRL_en 0x00000001 |
| #define BA_HDRX_PHY_EQ_CTRL_ovrwen 0x04B0 |
| #define B16HDRX_PHY_EQ_CTRL_ovrwen 0x04B0 |
| #define LSb32HDRX_PHY_EQ_CTRL_ovrwen 1 |
| #define LSb16HDRX_PHY_EQ_CTRL_ovrwen 1 |
| #define bHDRX_PHY_EQ_CTRL_ovrwen 1 |
| #define MSK32HDRX_PHY_EQ_CTRL_ovrwen 0x00000002 |
| #define BA_HDRX_PHY_EQ_CTRL_eq_flt_sel 0x04B0 |
| #define B16HDRX_PHY_EQ_CTRL_eq_flt_sel 0x04B0 |
| #define LSb32HDRX_PHY_EQ_CTRL_eq_flt_sel 2 |
| #define LSb16HDRX_PHY_EQ_CTRL_eq_flt_sel 2 |
| #define bHDRX_PHY_EQ_CTRL_eq_flt_sel 3 |
| #define MSK32HDRX_PHY_EQ_CTRL_eq_flt_sel 0x0000001C |
| #define BA_HDRX_PHY_EQ_CTRL_eq_ud_sw 0x04B0 |
| #define B16HDRX_PHY_EQ_CTRL_eq_ud_sw 0x04B0 |
| #define LSb32HDRX_PHY_EQ_CTRL_eq_ud_sw 5 |
| #define LSb16HDRX_PHY_EQ_CTRL_eq_ud_sw 5 |
| #define bHDRX_PHY_EQ_CTRL_eq_ud_sw 6 |
| #define MSK32HDRX_PHY_EQ_CTRL_eq_ud_sw 0x000007E0 |
| #define BA_HDRX_PHY_EQ_CTRL_eq_ctrl_param 0x04B1 |
| #define B16HDRX_PHY_EQ_CTRL_eq_ctrl_param 0x04B0 |
| #define LSb32HDRX_PHY_EQ_CTRL_eq_ctrl_param 11 |
| #define LSb16HDRX_PHY_EQ_CTRL_eq_ctrl_param 11 |
| #define bHDRX_PHY_EQ_CTRL_eq_ctrl_param 8 |
| #define MSK32HDRX_PHY_EQ_CTRL_eq_ctrl_param 0x0007F800 |
| #define BA_HDRX_PHY_EQ_CTRL_err_tol_03 0x04B2 |
| #define B16HDRX_PHY_EQ_CTRL_err_tol_03 0x04B2 |
| #define LSb32HDRX_PHY_EQ_CTRL_err_tol_03 19 |
| #define LSb16HDRX_PHY_EQ_CTRL_err_tol_03 3 |
| #define bHDRX_PHY_EQ_CTRL_err_tol_03 3 |
| #define MSK32HDRX_PHY_EQ_CTRL_err_tol_03 0x00380000 |
| #define BA_HDRX_PHY_EQ_CTRL_err_tol_45 0x04B2 |
| #define B16HDRX_PHY_EQ_CTRL_err_tol_45 0x04B2 |
| #define LSb32HDRX_PHY_EQ_CTRL_err_tol_45 22 |
| #define LSb16HDRX_PHY_EQ_CTRL_err_tol_45 6 |
| #define bHDRX_PHY_EQ_CTRL_err_tol_45 3 |
| #define MSK32HDRX_PHY_EQ_CTRL_err_tol_45 0x01C00000 |
| #define RA_HDRX_PHY_RGL_CTRL 0x04B4 |
| #define BA_HDRX_PHY_RGL_CTRL_svfrt 0x04B4 |
| #define B16HDRX_PHY_RGL_CTRL_svfrt 0x04B4 |
| #define LSb32HDRX_PHY_RGL_CTRL_svfrt 0 |
| #define LSb16HDRX_PHY_RGL_CTRL_svfrt 0 |
| #define bHDRX_PHY_RGL_CTRL_svfrt 2 |
| #define MSK32HDRX_PHY_RGL_CTRL_svfrt 0x00000003 |
| #define BA_HDRX_PHY_RGL_CTRL_svcdr 0x04B4 |
| #define B16HDRX_PHY_RGL_CTRL_svcdr 0x04B4 |
| #define LSb32HDRX_PHY_RGL_CTRL_svcdr 2 |
| #define LSb16HDRX_PHY_RGL_CTRL_svcdr 2 |
| #define bHDRX_PHY_RGL_CTRL_svcdr 3 |
| #define MSK32HDRX_PHY_RGL_CTRL_svcdr 0x0000001C |
| #define BA_HDRX_PHY_RGL_CTRL_eq_iref_d2 0x04B4 |
| #define B16HDRX_PHY_RGL_CTRL_eq_iref_d2 0x04B4 |
| #define LSb32HDRX_PHY_RGL_CTRL_eq_iref_d2 5 |
| #define LSb16HDRX_PHY_RGL_CTRL_eq_iref_d2 5 |
| #define bHDRX_PHY_RGL_CTRL_eq_iref_d2 2 |
| #define MSK32HDRX_PHY_RGL_CTRL_eq_iref_d2 0x00000060 |
| #define BA_HDRX_PHY_RGL_CTRL_eq_iref_d1 0x04B4 |
| #define B16HDRX_PHY_RGL_CTRL_eq_iref_d1 0x04B4 |
| #define LSb32HDRX_PHY_RGL_CTRL_eq_iref_d1 7 |
| #define LSb16HDRX_PHY_RGL_CTRL_eq_iref_d1 7 |
| #define bHDRX_PHY_RGL_CTRL_eq_iref_d1 2 |
| #define MSK32HDRX_PHY_RGL_CTRL_eq_iref_d1 0x00000180 |
| #define BA_HDRX_PHY_RGL_CTRL_eq_iref_d0 0x04B5 |
| #define B16HDRX_PHY_RGL_CTRL_eq_iref_d0 0x04B4 |
| #define LSb32HDRX_PHY_RGL_CTRL_eq_iref_d0 9 |
| #define LSb16HDRX_PHY_RGL_CTRL_eq_iref_d0 9 |
| #define bHDRX_PHY_RGL_CTRL_eq_iref_d0 2 |
| #define MSK32HDRX_PHY_RGL_CTRL_eq_iref_d0 0x00000600 |
| #define RA_HDRX_PHY_CDR_CTRL 0x04B8 |
| #define BA_HDRX_PHY_CDR_CTRL_polswap_rx_d 0x04B8 |
| #define B16HDRX_PHY_CDR_CTRL_polswap_rx_d 0x04B8 |
| #define LSb32HDRX_PHY_CDR_CTRL_polswap_rx_d 0 |
| #define LSb16HDRX_PHY_CDR_CTRL_polswap_rx_d 0 |
| #define bHDRX_PHY_CDR_CTRL_polswap_rx_d 3 |
| #define MSK32HDRX_PHY_CDR_CTRL_polswap_rx_d 0x00000007 |
| #define BA_HDRX_PHY_CDR_CTRL_lpf 0x04B8 |
| #define B16HDRX_PHY_CDR_CTRL_lpf 0x04B8 |
| #define LSb32HDRX_PHY_CDR_CTRL_lpf 3 |
| #define LSb16HDRX_PHY_CDR_CTRL_lpf 3 |
| #define bHDRX_PHY_CDR_CTRL_lpf 3 |
| #define MSK32HDRX_PHY_CDR_CTRL_lpf 0x00000038 |
| #define BA_HDRX_PHY_CDR_CTRL_dtl_ckdiv 0x04B8 |
| #define B16HDRX_PHY_CDR_CTRL_dtl_ckdiv 0x04B8 |
| #define LSb32HDRX_PHY_CDR_CTRL_dtl_ckdiv 6 |
| #define LSb16HDRX_PHY_CDR_CTRL_dtl_ckdiv 6 |
| #define bHDRX_PHY_CDR_CTRL_dtl_ckdiv 3 |
| #define MSK32HDRX_PHY_CDR_CTRL_dtl_ckdiv 0x000001C0 |
| #define BA_HDRX_PHY_CDR_CTRL_pi_stop 0x04B9 |
| #define B16HDRX_PHY_CDR_CTRL_pi_stop 0x04B8 |
| #define LSb32HDRX_PHY_CDR_CTRL_pi_stop 9 |
| #define LSb16HDRX_PHY_CDR_CTRL_pi_stop 9 |
| #define bHDRX_PHY_CDR_CTRL_pi_stop 1 |
| #define MSK32HDRX_PHY_CDR_CTRL_pi_stop 0x00000200 |
| #define BA_HDRX_PHY_CDR_CTRL_dpherin 0x04B9 |
| #define B16HDRX_PHY_CDR_CTRL_dpherin 0x04B8 |
| #define LSb32HDRX_PHY_CDR_CTRL_dpherin 10 |
| #define LSb16HDRX_PHY_CDR_CTRL_dpherin 10 |
| #define bHDRX_PHY_CDR_CTRL_dpherin 7 |
| #define MSK32HDRX_PHY_CDR_CTRL_dpherin 0x0001FC00 |
| #define BA_HDRX_PHY_CDR_CTRL_pi_toggle_ck 0x04BA |
| #define B16HDRX_PHY_CDR_CTRL_pi_toggle_ck 0x04BA |
| #define LSb32HDRX_PHY_CDR_CTRL_pi_toggle_ck 17 |
| #define LSb16HDRX_PHY_CDR_CTRL_pi_toggle_ck 1 |
| #define bHDRX_PHY_CDR_CTRL_pi_toggle_ck 1 |
| #define MSK32HDRX_PHY_CDR_CTRL_pi_toggle_ck 0x00020000 |
| #define BA_HDRX_PHY_CDR_CTRL_pi_ctrl 0x04BA |
| #define B16HDRX_PHY_CDR_CTRL_pi_ctrl 0x04BA |
| #define LSb32HDRX_PHY_CDR_CTRL_pi_ctrl 18 |
| #define LSb16HDRX_PHY_CDR_CTRL_pi_ctrl 2 |
| #define bHDRX_PHY_CDR_CTRL_pi_ctrl 8 |
| #define MSK32HDRX_PHY_CDR_CTRL_pi_ctrl 0x03FC0000 |
| #define BA_HDRX_PHY_CDR_CTRL_pi_low_bias 0x04BB |
| #define B16HDRX_PHY_CDR_CTRL_pi_low_bias 0x04BA |
| #define LSb32HDRX_PHY_CDR_CTRL_pi_low_bias 26 |
| #define LSb16HDRX_PHY_CDR_CTRL_pi_low_bias 10 |
| #define bHDRX_PHY_CDR_CTRL_pi_low_bias 1 |
| #define MSK32HDRX_PHY_CDR_CTRL_pi_low_bias 0x04000000 |
| #define BA_HDRX_PHY_CDR_CTRL_cdr_selckmon 0x04BB |
| #define B16HDRX_PHY_CDR_CTRL_cdr_selckmon 0x04BA |
| #define LSb32HDRX_PHY_CDR_CTRL_cdr_selckmon 27 |
| #define LSb16HDRX_PHY_CDR_CTRL_cdr_selckmon 11 |
| #define bHDRX_PHY_CDR_CTRL_cdr_selckmon 3 |
| #define MSK32HDRX_PHY_CDR_CTRL_cdr_selckmon 0x38000000 |
| #define RA_HDRX_PHY_TP_CTRL 0x04BC |
| #define BA_HDRX_PHY_TP_CTRL_tp_en_mode 0x04BC |
| #define B16HDRX_PHY_TP_CTRL_tp_en_mode 0x04BC |
| #define LSb32HDRX_PHY_TP_CTRL_tp_en_mode 0 |
| #define LSb16HDRX_PHY_TP_CTRL_tp_en_mode 0 |
| #define bHDRX_PHY_TP_CTRL_tp_en_mode 1 |
| #define MSK32HDRX_PHY_TP_CTRL_tp_en_mode 0x00000001 |
| #define BA_HDRX_PHY_TP_CTRL_tp_en 0x04BC |
| #define B16HDRX_PHY_TP_CTRL_tp_en 0x04BC |
| #define LSb32HDRX_PHY_TP_CTRL_tp_en 1 |
| #define LSb16HDRX_PHY_TP_CTRL_tp_en 1 |
| #define bHDRX_PHY_TP_CTRL_tp_en 5 |
| #define MSK32HDRX_PHY_TP_CTRL_tp_en 0x0000003E |
| #define BA_HDRX_PHY_TP_CTRL_tpc 0x04BC |
| #define B16HDRX_PHY_TP_CTRL_tpc 0x04BC |
| #define LSb32HDRX_PHY_TP_CTRL_tpc 6 |
| #define LSb16HDRX_PHY_TP_CTRL_tpc 6 |
| #define bHDRX_PHY_TP_CTRL_tpc 5 |
| #define MSK32HDRX_PHY_TP_CTRL_tpc 0x000007C0 |
| #define RA_HDRX_PHY_AUX_CTRL 0x04C0 |
| #define BA_HDRX_PHY_AUX_CTRL_aux_d2 0x04C0 |
| #define B16HDRX_PHY_AUX_CTRL_aux_d2 0x04C0 |
| #define LSb32HDRX_PHY_AUX_CTRL_aux_d2 0 |
| #define LSb16HDRX_PHY_AUX_CTRL_aux_d2 0 |
| #define bHDRX_PHY_AUX_CTRL_aux_d2 4 |
| #define MSK32HDRX_PHY_AUX_CTRL_aux_d2 0x0000000F |
| #define BA_HDRX_PHY_AUX_CTRL_aux_d1 0x04C0 |
| #define B16HDRX_PHY_AUX_CTRL_aux_d1 0x04C0 |
| #define LSb32HDRX_PHY_AUX_CTRL_aux_d1 4 |
| #define LSb16HDRX_PHY_AUX_CTRL_aux_d1 4 |
| #define bHDRX_PHY_AUX_CTRL_aux_d1 4 |
| #define MSK32HDRX_PHY_AUX_CTRL_aux_d1 0x000000F0 |
| #define BA_HDRX_PHY_AUX_CTRL_aux_d0 0x04C1 |
| #define B16HDRX_PHY_AUX_CTRL_aux_d0 0x04C0 |
| #define LSb32HDRX_PHY_AUX_CTRL_aux_d0 8 |
| #define LSb16HDRX_PHY_AUX_CTRL_aux_d0 8 |
| #define bHDRX_PHY_AUX_CTRL_aux_d0 4 |
| #define MSK32HDRX_PHY_AUX_CTRL_aux_d0 0x00000F00 |
| #define BA_HDRX_PHY_AUX_CTRL_aux_ck 0x04C1 |
| #define B16HDRX_PHY_AUX_CTRL_aux_ck 0x04C0 |
| #define LSb32HDRX_PHY_AUX_CTRL_aux_ck 12 |
| #define LSb16HDRX_PHY_AUX_CTRL_aux_ck 12 |
| #define bHDRX_PHY_AUX_CTRL_aux_ck 4 |
| #define MSK32HDRX_PHY_AUX_CTRL_aux_ck 0x0000F000 |
| #define BA_HDRX_PHY_AUX_CTRL_aux_comm 0x04C2 |
| #define B16HDRX_PHY_AUX_CTRL_aux_comm 0x04C2 |
| #define LSb32HDRX_PHY_AUX_CTRL_aux_comm 16 |
| #define LSb16HDRX_PHY_AUX_CTRL_aux_comm 0 |
| #define bHDRX_PHY_AUX_CTRL_aux_comm 8 |
| #define MSK32HDRX_PHY_AUX_CTRL_aux_comm 0x00FF0000 |
| #define BA_HDRX_PHY_AUX_CTRL_aux_ctrl_0 0x04C3 |
| #define B16HDRX_PHY_AUX_CTRL_aux_ctrl_0 0x04C2 |
| #define LSb32HDRX_PHY_AUX_CTRL_aux_ctrl_0 24 |
| #define LSb16HDRX_PHY_AUX_CTRL_aux_ctrl_0 8 |
| #define bHDRX_PHY_AUX_CTRL_aux_ctrl_0 8 |
| #define MSK32HDRX_PHY_AUX_CTRL_aux_ctrl_0 0xFF000000 |
| #define RA_HDRX_PHY_AUX_CTRL1 0x04C4 |
| #define BA_HDRX_PHY_AUX_CTRL_aux_ctrl_1 0x04C4 |
| #define B16HDRX_PHY_AUX_CTRL_aux_ctrl_1 0x04C4 |
| #define LSb32HDRX_PHY_AUX_CTRL_aux_ctrl_1 0 |
| #define LSb16HDRX_PHY_AUX_CTRL_aux_ctrl_1 0 |
| #define bHDRX_PHY_AUX_CTRL_aux_ctrl_1 8 |
| #define MSK32HDRX_PHY_AUX_CTRL_aux_ctrl_1 0x000000FF |
| #define RA_HDRX_PHY_PKT_CTRL 0x04C8 |
| #define BA_HDRX_PHY_PKT_CTRL_prt_disable 0x04C8 |
| #define B16HDRX_PHY_PKT_CTRL_prt_disable 0x04C8 |
| #define LSb32HDRX_PHY_PKT_CTRL_prt_disable 0 |
| #define LSb16HDRX_PHY_PKT_CTRL_prt_disable 0 |
| #define bHDRX_PHY_PKT_CTRL_prt_disable 1 |
| #define MSK32HDRX_PHY_PKT_CTRL_prt_disable 0x00000001 |
| #define BA_HDRX_PHY_PKT_CTRL_prt_lvl 0x04C8 |
| #define B16HDRX_PHY_PKT_CTRL_prt_lvl 0x04C8 |
| #define LSb32HDRX_PHY_PKT_CTRL_prt_lvl 1 |
| #define LSb16HDRX_PHY_PKT_CTRL_prt_lvl 1 |
| #define bHDRX_PHY_PKT_CTRL_prt_lvl 2 |
| #define MSK32HDRX_PHY_PKT_CTRL_prt_lvl 0x00000006 |
| #define RA_HDRX_PHY_VCOCAL 0x04CC |
| #define BA_HDRX_PHY_VCOCAL_vcon_adj 0x04CC |
| #define B16HDRX_PHY_VCOCAL_vcon_adj 0x04CC |
| #define LSb32HDRX_PHY_VCOCAL_vcon_adj 0 |
| #define LSb16HDRX_PHY_VCOCAL_vcon_adj 0 |
| #define bHDRX_PHY_VCOCAL_vcon_adj 2 |
| #define MSK32HDRX_PHY_VCOCAL_vcon_adj 0x00000003 |
| #define BA_HDRX_PHY_VCOCAL_div_ctrl 0x04CC |
| #define B16HDRX_PHY_VCOCAL_div_ctrl 0x04CC |
| #define LSb32HDRX_PHY_VCOCAL_div_ctrl 2 |
| #define LSb16HDRX_PHY_VCOCAL_div_ctrl 2 |
| #define bHDRX_PHY_VCOCAL_div_ctrl 2 |
| #define MSK32HDRX_PHY_VCOCAL_div_ctrl 0x0000000C |
| #define BA_HDRX_PHY_VCOCAL_timer_ctrl 0x04CC |
| #define B16HDRX_PHY_VCOCAL_timer_ctrl 0x04CC |
| #define LSb32HDRX_PHY_VCOCAL_timer_ctrl 4 |
| #define LSb16HDRX_PHY_VCOCAL_timer_ctrl 4 |
| #define bHDRX_PHY_VCOCAL_timer_ctrl 2 |
| #define MSK32HDRX_PHY_VCOCAL_timer_ctrl 0x00000030 |
| #define BA_HDRX_PHY_VCOCAL_ovrwen 0x04CC |
| #define B16HDRX_PHY_VCOCAL_ovrwen 0x04CC |
| #define LSb32HDRX_PHY_VCOCAL_ovrwen 6 |
| #define LSb16HDRX_PHY_VCOCAL_ovrwen 6 |
| #define bHDRX_PHY_VCOCAL_ovrwen 1 |
| #define MSK32HDRX_PHY_VCOCAL_ovrwen 0x00000040 |
| #define BA_HDRX_PHY_VCOCAL_v2i_filt_byp_ovrwen 0x04CC |
| #define B16HDRX_PHY_VCOCAL_v2i_filt_byp_ovrwen 0x04CC |
| #define LSb32HDRX_PHY_VCOCAL_v2i_filt_byp_ovrwen 7 |
| #define LSb16HDRX_PHY_VCOCAL_v2i_filt_byp_ovrwen 7 |
| #define bHDRX_PHY_VCOCAL_v2i_filt_byp_ovrwen 1 |
| #define MSK32HDRX_PHY_VCOCAL_v2i_filt_byp_ovrwen 0x00000080 |
| #define BA_HDRX_PHY_VCOCAL_icp_scale_ovrwen 0x04CD |
| #define B16HDRX_PHY_VCOCAL_icp_scale_ovrwen 0x04CC |
| #define LSb32HDRX_PHY_VCOCAL_icp_scale_ovrwen 8 |
| #define LSb16HDRX_PHY_VCOCAL_icp_scale_ovrwen 8 |
| #define bHDRX_PHY_VCOCAL_icp_scale_ovrwen 1 |
| #define MSK32HDRX_PHY_VCOCAL_icp_scale_ovrwen 0x00000100 |
| #define BA_HDRX_PHY_VCOCAL_ovrw 0x04CD |
| #define B16HDRX_PHY_VCOCAL_ovrw 0x04CC |
| #define LSb32HDRX_PHY_VCOCAL_ovrw 9 |
| #define LSb16HDRX_PHY_VCOCAL_ovrw 9 |
| #define bHDRX_PHY_VCOCAL_ovrw 4 |
| #define MSK32HDRX_PHY_VCOCAL_ovrw 0x00001E00 |
| #define BA_HDRX_PHY_VCOCAL_V2i_filt_byp_ovrw 0x04CD |
| #define B16HDRX_PHY_VCOCAL_V2i_filt_byp_ovrw 0x04CC |
| #define LSb32HDRX_PHY_VCOCAL_V2i_filt_byp_ovrw 13 |
| #define LSb16HDRX_PHY_VCOCAL_V2i_filt_byp_ovrw 13 |
| #define bHDRX_PHY_VCOCAL_V2i_filt_byp_ovrw 1 |
| #define MSK32HDRX_PHY_VCOCAL_V2i_filt_byp_ovrw 0x00002000 |
| #define BA_HDRX_PHY_VCOCAL_icp_scale_ovrw 0x04CD |
| #define B16HDRX_PHY_VCOCAL_icp_scale_ovrw 0x04CC |
| #define LSb32HDRX_PHY_VCOCAL_icp_scale_ovrw 14 |
| #define LSb16HDRX_PHY_VCOCAL_icp_scale_ovrw 14 |
| #define bHDRX_PHY_VCOCAL_icp_scale_ovrw 4 |
| #define MSK32HDRX_PHY_VCOCAL_icp_scale_ovrw 0x0003C000 |
| #define BA_HDRX_PHY_VCOCAL_vcocal_en 0x04CE |
| #define B16HDRX_PHY_VCOCAL_vcocal_en 0x04CE |
| #define LSb32HDRX_PHY_VCOCAL_vcocal_en 18 |
| #define LSb16HDRX_PHY_VCOCAL_vcocal_en 2 |
| #define bHDRX_PHY_VCOCAL_vcocal_en 1 |
| #define MSK32HDRX_PHY_VCOCAL_vcocal_en 0x00040000 |
| #define RA_HDRX_PHY_HSDAC_CTRL0 0x04D0 |
| #define BA_HDRX_PHY_HSDAC_CTRL0_nv_pher_ck 0x04D0 |
| #define B16HDRX_PHY_HSDAC_CTRL0_nv_pher_ck 0x04D0 |
| #define LSb32HDRX_PHY_HSDAC_CTRL0_nv_pher_ck 0 |
| #define LSb16HDRX_PHY_HSDAC_CTRL0_nv_pher_ck 0 |
| #define bHDRX_PHY_HSDAC_CTRL0_nv_pher_ck 1 |
| #define MSK32HDRX_PHY_HSDAC_CTRL0_nv_pher_ck 0x00000001 |
| #define RA_HDRX_PHY_PM 0x04D4 |
| #define BA_HDRX_PHY_PM_pd_rxck 0x04D4 |
| #define B16HDRX_PHY_PM_pd_rxck 0x04D4 |
| #define LSb32HDRX_PHY_PM_pd_rxck 0 |
| #define LSb16HDRX_PHY_PM_pd_rxck 0 |
| #define bHDRX_PHY_PM_pd_rxck 1 |
| #define MSK32HDRX_PHY_PM_pd_rxck 0x00000001 |
| #define BA_HDRX_PHY_PM_syn_ck2rx 0x04D4 |
| #define B16HDRX_PHY_PM_syn_ck2rx 0x04D4 |
| #define LSb32HDRX_PHY_PM_syn_ck2rx 1 |
| #define LSb16HDRX_PHY_PM_syn_ck2rx 1 |
| #define bHDRX_PHY_PM_syn_ck2rx 1 |
| #define MSK32HDRX_PHY_PM_syn_ck2rx 0x00000002 |
| #define BA_HDRX_PHY_PM_pd_comm 0x04D4 |
| #define B16HDRX_PHY_PM_pd_comm 0x04D4 |
| #define LSb32HDRX_PHY_PM_pd_comm 2 |
| #define LSb16HDRX_PHY_PM_pd_comm 2 |
| #define bHDRX_PHY_PM_pd_comm 1 |
| #define MSK32HDRX_PHY_PM_pd_comm 0x00000004 |
| #define BA_HDRX_PHY_PM_pd_pll 0x04D4 |
| #define B16HDRX_PHY_PM_pd_pll 0x04D4 |
| #define LSb32HDRX_PHY_PM_pd_pll 3 |
| #define LSb16HDRX_PHY_PM_pd_pll 3 |
| #define bHDRX_PHY_PM_pd_pll 1 |
| #define MSK32HDRX_PHY_PM_pd_pll 0x00000008 |
| #define BA_HDRX_PHY_PM_pd_cdr 0x04D4 |
| #define B16HDRX_PHY_PM_pd_cdr 0x04D4 |
| #define LSb32HDRX_PHY_PM_pd_cdr 4 |
| #define LSb16HDRX_PHY_PM_pd_cdr 4 |
| #define bHDRX_PHY_PM_pd_cdr 1 |
| #define MSK32HDRX_PHY_PM_pd_cdr 0x00000010 |
| #define BA_HDRX_PHY_PM_pd_frt_c 0x04D4 |
| #define B16HDRX_PHY_PM_pd_frt_c 0x04D4 |
| #define LSb32HDRX_PHY_PM_pd_frt_c 5 |
| #define LSb16HDRX_PHY_PM_pd_frt_c 5 |
| #define bHDRX_PHY_PM_pd_frt_c 1 |
| #define MSK32HDRX_PHY_PM_pd_frt_c 0x00000020 |
| #define BA_HDRX_PHY_PM_pd_frt_d 0x04D4 |
| #define B16HDRX_PHY_PM_pd_frt_d 0x04D4 |
| #define LSb32HDRX_PHY_PM_pd_frt_d 6 |
| #define LSb16HDRX_PHY_PM_pd_frt_d 6 |
| #define bHDRX_PHY_PM_pd_frt_d 1 |
| #define MSK32HDRX_PHY_PM_pd_frt_d 0x00000040 |
| #define BA_HDRX_PHY_PM_reset_rx 0x04D4 |
| #define B16HDRX_PHY_PM_reset_rx 0x04D4 |
| #define LSb32HDRX_PHY_PM_reset_rx 7 |
| #define LSb16HDRX_PHY_PM_reset_rx 7 |
| #define bHDRX_PHY_PM_reset_rx 1 |
| #define MSK32HDRX_PHY_PM_reset_rx 0x00000080 |
| #define BA_HDRX_PHY_PM_reset_pll 0x04D5 |
| #define B16HDRX_PHY_PM_reset_pll 0x04D4 |
| #define LSb32HDRX_PHY_PM_reset_pll 8 |
| #define LSb16HDRX_PHY_PM_reset_pll 8 |
| #define bHDRX_PHY_PM_reset_pll 1 |
| #define MSK32HDRX_PHY_PM_reset_pll 0x00000100 |
| #define RA_HDRX_ARC_TX_CTRL 0x04D8 |
| #define BA_HDRX_ARC_TX_CTRL_en 0x04D8 |
| #define B16HDRX_ARC_TX_CTRL_en 0x04D8 |
| #define LSb32HDRX_ARC_TX_CTRL_en 0 |
| #define LSb16HDRX_ARC_TX_CTRL_en 0 |
| #define bHDRX_ARC_TX_CTRL_en 1 |
| #define MSK32HDRX_ARC_TX_CTRL_en 0x00000001 |
| #define BA_HDRX_ARC_TX_CTRL_pd 0x04D8 |
| #define B16HDRX_ARC_TX_CTRL_pd 0x04D8 |
| #define LSb32HDRX_ARC_TX_CTRL_pd 1 |
| #define LSb16HDRX_ARC_TX_CTRL_pd 1 |
| #define bHDRX_ARC_TX_CTRL_pd 1 |
| #define MSK32HDRX_ARC_TX_CTRL_pd 0x00000002 |
| #define BA_HDRX_ARC_TX_CTRL_amp 0x04D8 |
| #define B16HDRX_ARC_TX_CTRL_amp 0x04D8 |
| #define LSb32HDRX_ARC_TX_CTRL_amp 2 |
| #define LSb16HDRX_ARC_TX_CTRL_amp 2 |
| #define bHDRX_ARC_TX_CTRL_amp 2 |
| #define MSK32HDRX_ARC_TX_CTRL_amp 0x0000000C |
| #define BA_HDRX_ARC_TX_CTRL_pull_ud 0x04D8 |
| #define B16HDRX_ARC_TX_CTRL_pull_ud 0x04D8 |
| #define LSb32HDRX_ARC_TX_CTRL_pull_ud 4 |
| #define LSb16HDRX_ARC_TX_CTRL_pull_ud 4 |
| #define bHDRX_ARC_TX_CTRL_pull_ud 2 |
| #define MSK32HDRX_ARC_TX_CTRL_pull_ud 0x00000030 |
| #define BA_HDRX_ARC_TX_CTRL_trf 0x04D8 |
| #define B16HDRX_ARC_TX_CTRL_trf 0x04D8 |
| #define LSb32HDRX_ARC_TX_CTRL_trf 6 |
| #define LSb16HDRX_ARC_TX_CTRL_trf 6 |
| #define bHDRX_ARC_TX_CTRL_trf 2 |
| #define MSK32HDRX_ARC_TX_CTRL_trf 0x000000C0 |
| #define RA_HDRX_PHY_IF_CTRL 0x04DC |
| #define BA_HDRX_PHY_IF_CTRL_clk_pol 0x04DC |
| #define B16HDRX_PHY_IF_CTRL_clk_pol 0x04DC |
| #define LSb32HDRX_PHY_IF_CTRL_clk_pol 0 |
| #define LSb16HDRX_PHY_IF_CTRL_clk_pol 0 |
| #define bHDRX_PHY_IF_CTRL_clk_pol 3 |
| #define MSK32HDRX_PHY_IF_CTRL_clk_pol 0x00000007 |
| #define RA_HDRX_PHY_PRBS_CTRL 0x04E0 |
| #define BA_HDRX_PHY_PRBS_CTRL_en_0 0x04E0 |
| #define B16HDRX_PHY_PRBS_CTRL_en_0 0x04E0 |
| #define LSb32HDRX_PHY_PRBS_CTRL_en_0 0 |
| #define LSb16HDRX_PHY_PRBS_CTRL_en_0 0 |
| #define bHDRX_PHY_PRBS_CTRL_en_0 1 |
| #define MSK32HDRX_PHY_PRBS_CTRL_en_0 0x00000001 |
| #define BA_HDRX_PHY_PRBS_CTRL_clear_0 0x04E0 |
| #define B16HDRX_PHY_PRBS_CTRL_clear_0 0x04E0 |
| #define LSb32HDRX_PHY_PRBS_CTRL_clear_0 1 |
| #define LSb16HDRX_PHY_PRBS_CTRL_clear_0 1 |
| #define bHDRX_PHY_PRBS_CTRL_clear_0 1 |
| #define MSK32HDRX_PHY_PRBS_CTRL_clear_0 0x00000002 |
| #define BA_HDRX_PHY_PRBS_CTRL_type_0 0x04E0 |
| #define B16HDRX_PHY_PRBS_CTRL_type_0 0x04E0 |
| #define LSb32HDRX_PHY_PRBS_CTRL_type_0 2 |
| #define LSb16HDRX_PHY_PRBS_CTRL_type_0 2 |
| #define bHDRX_PHY_PRBS_CTRL_type_0 2 |
| #define MSK32HDRX_PHY_PRBS_CTRL_type_0 0x0000000C |
| #define BA_HDRX_PHY_PRBS_CTRL_misc_0 0x04E0 |
| #define B16HDRX_PHY_PRBS_CTRL_misc_0 0x04E0 |
| #define LSb32HDRX_PHY_PRBS_CTRL_misc_0 4 |
| #define LSb16HDRX_PHY_PRBS_CTRL_misc_0 4 |
| #define bHDRX_PHY_PRBS_CTRL_misc_0 1 |
| #define MSK32HDRX_PHY_PRBS_CTRL_misc_0 0x00000010 |
| #define BA_HDRX_PHY_PRBS_CTRL_en_1 0x04E0 |
| #define B16HDRX_PHY_PRBS_CTRL_en_1 0x04E0 |
| #define LSb32HDRX_PHY_PRBS_CTRL_en_1 5 |
| #define LSb16HDRX_PHY_PRBS_CTRL_en_1 5 |
| #define bHDRX_PHY_PRBS_CTRL_en_1 1 |
| #define MSK32HDRX_PHY_PRBS_CTRL_en_1 0x00000020 |
| #define BA_HDRX_PHY_PRBS_CTRL_clear_1 0x04E0 |
| #define B16HDRX_PHY_PRBS_CTRL_clear_1 0x04E0 |
| #define LSb32HDRX_PHY_PRBS_CTRL_clear_1 6 |
| #define LSb16HDRX_PHY_PRBS_CTRL_clear_1 6 |
| #define bHDRX_PHY_PRBS_CTRL_clear_1 1 |
| #define MSK32HDRX_PHY_PRBS_CTRL_clear_1 0x00000040 |
| #define BA_HDRX_PHY_PRBS_CTRL_type_1 0x04E0 |
| #define B16HDRX_PHY_PRBS_CTRL_type_1 0x04E0 |
| #define LSb32HDRX_PHY_PRBS_CTRL_type_1 7 |
| #define LSb16HDRX_PHY_PRBS_CTRL_type_1 7 |
| #define bHDRX_PHY_PRBS_CTRL_type_1 2 |
| #define MSK32HDRX_PHY_PRBS_CTRL_type_1 0x00000180 |
| #define BA_HDRX_PHY_PRBS_CTRL_misc_1 0x04E1 |
| #define B16HDRX_PHY_PRBS_CTRL_misc_1 0x04E0 |
| #define LSb32HDRX_PHY_PRBS_CTRL_misc_1 9 |
| #define LSb16HDRX_PHY_PRBS_CTRL_misc_1 9 |
| #define bHDRX_PHY_PRBS_CTRL_misc_1 1 |
| #define MSK32HDRX_PHY_PRBS_CTRL_misc_1 0x00000200 |
| #define BA_HDRX_PHY_PRBS_CTRL_en_2 0x04E1 |
| #define B16HDRX_PHY_PRBS_CTRL_en_2 0x04E0 |
| #define LSb32HDRX_PHY_PRBS_CTRL_en_2 10 |
| #define LSb16HDRX_PHY_PRBS_CTRL_en_2 10 |
| #define bHDRX_PHY_PRBS_CTRL_en_2 1 |
| #define MSK32HDRX_PHY_PRBS_CTRL_en_2 0x00000400 |
| #define BA_HDRX_PHY_PRBS_CTRL_clear_2 0x04E1 |
| #define B16HDRX_PHY_PRBS_CTRL_clear_2 0x04E0 |
| #define LSb32HDRX_PHY_PRBS_CTRL_clear_2 11 |
| #define LSb16HDRX_PHY_PRBS_CTRL_clear_2 11 |
| #define bHDRX_PHY_PRBS_CTRL_clear_2 1 |
| #define MSK32HDRX_PHY_PRBS_CTRL_clear_2 0x00000800 |
| #define BA_HDRX_PHY_PRBS_CTRL_type_2 0x04E1 |
| #define B16HDRX_PHY_PRBS_CTRL_type_2 0x04E0 |
| #define LSb32HDRX_PHY_PRBS_CTRL_type_2 12 |
| #define LSb16HDRX_PHY_PRBS_CTRL_type_2 12 |
| #define bHDRX_PHY_PRBS_CTRL_type_2 2 |
| #define MSK32HDRX_PHY_PRBS_CTRL_type_2 0x00003000 |
| #define BA_HDRX_PHY_PRBS_CTRL_misc_2 0x04E1 |
| #define B16HDRX_PHY_PRBS_CTRL_misc_2 0x04E0 |
| #define LSb32HDRX_PHY_PRBS_CTRL_misc_2 14 |
| #define LSb16HDRX_PHY_PRBS_CTRL_misc_2 14 |
| #define bHDRX_PHY_PRBS_CTRL_misc_2 1 |
| #define MSK32HDRX_PHY_PRBS_CTRL_misc_2 0x00004000 |
| #define BA_HDRX_PHY_PRBS_CTRL_match_cnt 0x04E1 |
| #define B16HDRX_PHY_PRBS_CTRL_match_cnt 0x04E0 |
| #define LSb32HDRX_PHY_PRBS_CTRL_match_cnt 15 |
| #define LSb16HDRX_PHY_PRBS_CTRL_match_cnt 15 |
| #define bHDRX_PHY_PRBS_CTRL_match_cnt 16 |
| #define MSK32HDRX_PHY_PRBS_CTRL_match_cnt 0x7FFF8000 |
| #define RA_HDRX_PHY_STAT 0x04E4 |
| #define BA_HDRX_PHY_STAT_pll_lock 0x04E4 |
| #define B16HDRX_PHY_STAT_pll_lock 0x04E4 |
| #define LSb32HDRX_PHY_STAT_pll_lock 0 |
| #define LSb16HDRX_PHY_STAT_pll_lock 0 |
| #define bHDRX_PHY_STAT_pll_lock 1 |
| #define MSK32HDRX_PHY_STAT_pll_lock 0x00000001 |
| #define BA_HDRX_PHY_STAT_prt_enabled 0x04E4 |
| #define B16HDRX_PHY_STAT_prt_enabled 0x04E4 |
| #define LSb32HDRX_PHY_STAT_prt_enabled 1 |
| #define LSb16HDRX_PHY_STAT_prt_enabled 1 |
| #define bHDRX_PHY_STAT_prt_enabled 1 |
| #define MSK32HDRX_PHY_STAT_prt_enabled 0x00000002 |
| #define BA_HDRX_PHY_STAT_auxo_d2 0x04E4 |
| #define B16HDRX_PHY_STAT_auxo_d2 0x04E4 |
| #define LSb32HDRX_PHY_STAT_auxo_d2 2 |
| #define LSb16HDRX_PHY_STAT_auxo_d2 2 |
| #define bHDRX_PHY_STAT_auxo_d2 4 |
| #define MSK32HDRX_PHY_STAT_auxo_d2 0x0000003C |
| #define BA_HDRX_PHY_STAT_auxo_d1 0x04E4 |
| #define B16HDRX_PHY_STAT_auxo_d1 0x04E4 |
| #define LSb32HDRX_PHY_STAT_auxo_d1 6 |
| #define LSb16HDRX_PHY_STAT_auxo_d1 6 |
| #define bHDRX_PHY_STAT_auxo_d1 4 |
| #define MSK32HDRX_PHY_STAT_auxo_d1 0x000003C0 |
| #define BA_HDRX_PHY_STAT_auxo_d0 0x04E5 |
| #define B16HDRX_PHY_STAT_auxo_d0 0x04E4 |
| #define LSb32HDRX_PHY_STAT_auxo_d0 10 |
| #define LSb16HDRX_PHY_STAT_auxo_d0 10 |
| #define bHDRX_PHY_STAT_auxo_d0 4 |
| #define MSK32HDRX_PHY_STAT_auxo_d0 0x00003C00 |
| #define BA_HDRX_PHY_STAT_auxo_ck 0x04E5 |
| #define B16HDRX_PHY_STAT_auxo_ck 0x04E4 |
| #define LSb32HDRX_PHY_STAT_auxo_ck 14 |
| #define LSb16HDRX_PHY_STAT_auxo_ck 14 |
| #define bHDRX_PHY_STAT_auxo_ck 4 |
| #define MSK32HDRX_PHY_STAT_auxo_ck 0x0003C000 |
| #define BA_HDRX_PHY_STAT_RSVD 0x04E6 |
| #define B16HDRX_PHY_STAT_RSVD 0x04E6 |
| #define LSb32HDRX_PHY_STAT_RSVD 18 |
| #define LSb16HDRX_PHY_STAT_RSVD 2 |
| #define bHDRX_PHY_STAT_RSVD 11 |
| #define MSK32HDRX_PHY_STAT_RSVD 0x1FFC0000 |
| #define BA_HDRX_PHY_STAT_eq_h_dn 0x04E7 |
| #define B16HDRX_PHY_STAT_eq_h_dn 0x04E6 |
| #define LSb32HDRX_PHY_STAT_eq_h_dn 29 |
| #define LSb16HDRX_PHY_STAT_eq_h_dn 13 |
| #define bHDRX_PHY_STAT_eq_h_dn 3 |
| #define MSK32HDRX_PHY_STAT_eq_h_dn 0xE0000000 |
| #define RA_HDRX_PHY_STAT1 0x04E8 |
| #define BA_HDRX_PHY_STAT_eqh_h_up 0x04E8 |
| #define B16HDRX_PHY_STAT_eqh_h_up 0x04E8 |
| #define LSb32HDRX_PHY_STAT_eqh_h_up 0 |
| #define LSb16HDRX_PHY_STAT_eqh_h_up 0 |
| #define bHDRX_PHY_STAT_eqh_h_up 3 |
| #define MSK32HDRX_PHY_STAT_eqh_h_up 0x00000007 |
| #define BA_HDRX_PHY_STAT_eq_l_dn 0x04E8 |
| #define B16HDRX_PHY_STAT_eq_l_dn 0x04E8 |
| #define LSb32HDRX_PHY_STAT_eq_l_dn 3 |
| #define LSb16HDRX_PHY_STAT_eq_l_dn 3 |
| #define bHDRX_PHY_STAT_eq_l_dn 3 |
| #define MSK32HDRX_PHY_STAT_eq_l_dn 0x00000038 |
| #define BA_HDRX_PHY_STAT_eq_l_up 0x04E8 |
| #define B16HDRX_PHY_STAT_eq_l_up 0x04E8 |
| #define LSb32HDRX_PHY_STAT_eq_l_up 6 |
| #define LSb16HDRX_PHY_STAT_eq_l_up 6 |
| #define bHDRX_PHY_STAT_eq_l_up 3 |
| #define MSK32HDRX_PHY_STAT_eq_l_up 0x000001C0 |
| #define BA_HDRX_PHY_STAT_vcocal_busy 0x04E9 |
| #define B16HDRX_PHY_STAT_vcocal_busy 0x04E8 |
| #define LSb32HDRX_PHY_STAT_vcocal_busy 9 |
| #define LSb16HDRX_PHY_STAT_vcocal_busy 9 |
| #define bHDRX_PHY_STAT_vcocal_busy 1 |
| #define MSK32HDRX_PHY_STAT_vcocal_busy 0x00000200 |
| #define BA_HDRX_PHY_STAT_vcocal_val 0x04E9 |
| #define B16HDRX_PHY_STAT_vcocal_val 0x04E8 |
| #define LSb32HDRX_PHY_STAT_vcocal_val 10 |
| #define LSb16HDRX_PHY_STAT_vcocal_val 10 |
| #define bHDRX_PHY_STAT_vcocal_val 4 |
| #define MSK32HDRX_PHY_STAT_vcocal_val 0x00003C00 |
| #define BA_HDRX_PHY_STAT_vcocal_fail 0x04E9 |
| #define B16HDRX_PHY_STAT_vcocal_fail 0x04E8 |
| #define LSb32HDRX_PHY_STAT_vcocal_fail 14 |
| #define LSb16HDRX_PHY_STAT_vcocal_fail 14 |
| #define bHDRX_PHY_STAT_vcocal_fail 1 |
| #define MSK32HDRX_PHY_STAT_vcocal_fail 0x00004000 |
| #define BA_HDRX_PHY_STAT_vcocal_comp 0x04E9 |
| #define B16HDRX_PHY_STAT_vcocal_comp 0x04E8 |
| #define LSb32HDRX_PHY_STAT_vcocal_comp 15 |
| #define LSb16HDRX_PHY_STAT_vcocal_comp 15 |
| #define bHDRX_PHY_STAT_vcocal_comp 1 |
| #define MSK32HDRX_PHY_STAT_vcocal_comp 0x00008000 |
| #define BA_HDRX_PHY_STAT_auxo_pll 0x04EA |
| #define B16HDRX_PHY_STAT_auxo_pll 0x04EA |
| #define LSb32HDRX_PHY_STAT_auxo_pll 16 |
| #define LSb16HDRX_PHY_STAT_auxo_pll 0 |
| #define bHDRX_PHY_STAT_auxo_pll 4 |
| #define MSK32HDRX_PHY_STAT_auxo_pll 0x000F0000 |
| #define BA_HDRX_PHY_STAT_eq_fsm_d2 0x04EA |
| #define B16HDRX_PHY_STAT_eq_fsm_d2 0x04EA |
| #define LSb32HDRX_PHY_STAT_eq_fsm_d2 20 |
| #define LSb16HDRX_PHY_STAT_eq_fsm_d2 4 |
| #define bHDRX_PHY_STAT_eq_fsm_d2 4 |
| #define MSK32HDRX_PHY_STAT_eq_fsm_d2 0x00F00000 |
| #define BA_HDRX_PHY_STAT_eq_fsm_d1 0x04EB |
| #define B16HDRX_PHY_STAT_eq_fsm_d1 0x04EA |
| #define LSb32HDRX_PHY_STAT_eq_fsm_d1 24 |
| #define LSb16HDRX_PHY_STAT_eq_fsm_d1 8 |
| #define bHDRX_PHY_STAT_eq_fsm_d1 4 |
| #define MSK32HDRX_PHY_STAT_eq_fsm_d1 0x0F000000 |
| #define BA_HDRX_PHY_STAT_eq_fsm_d0 0x04EB |
| #define B16HDRX_PHY_STAT_eq_fsm_d0 0x04EA |
| #define LSb32HDRX_PHY_STAT_eq_fsm_d0 28 |
| #define LSb16HDRX_PHY_STAT_eq_fsm_d0 12 |
| #define bHDRX_PHY_STAT_eq_fsm_d0 4 |
| #define MSK32HDRX_PHY_STAT_eq_fsm_d0 0xF0000000 |
| #define RA_HDRX_PHY_STAT2 0x04EC |
| #define BA_HDRX_PHY_STAT_eq_ctrl_d2 0x04EC |
| #define B16HDRX_PHY_STAT_eq_ctrl_d2 0x04EC |
| #define LSb32HDRX_PHY_STAT_eq_ctrl_d2 0 |
| #define LSb16HDRX_PHY_STAT_eq_ctrl_d2 0 |
| #define bHDRX_PHY_STAT_eq_ctrl_d2 8 |
| #define MSK32HDRX_PHY_STAT_eq_ctrl_d2 0x000000FF |
| #define BA_HDRX_PHY_STAT_eq_ctrl_d1 0x04ED |
| #define B16HDRX_PHY_STAT_eq_ctrl_d1 0x04EC |
| #define LSb32HDRX_PHY_STAT_eq_ctrl_d1 8 |
| #define LSb16HDRX_PHY_STAT_eq_ctrl_d1 8 |
| #define bHDRX_PHY_STAT_eq_ctrl_d1 8 |
| #define MSK32HDRX_PHY_STAT_eq_ctrl_d1 0x0000FF00 |
| #define BA_HDRX_PHY_STAT_eq_ctrl_d0 0x04EE |
| #define B16HDRX_PHY_STAT_eq_ctrl_d0 0x04EE |
| #define LSb32HDRX_PHY_STAT_eq_ctrl_d0 16 |
| #define LSb16HDRX_PHY_STAT_eq_ctrl_d0 0 |
| #define bHDRX_PHY_STAT_eq_ctrl_d0 8 |
| #define MSK32HDRX_PHY_STAT_eq_ctrl_d0 0x00FF0000 |
| #define RA_HDRX_PHY_PRBS_LOCK_STAT 0x04F0 |
| #define BA_HDRX_PHY_PRBS_LOCK_STAT_ch0 0x04F0 |
| #define B16HDRX_PHY_PRBS_LOCK_STAT_ch0 0x04F0 |
| #define LSb32HDRX_PHY_PRBS_LOCK_STAT_ch0 0 |
| #define LSb16HDRX_PHY_PRBS_LOCK_STAT_ch0 0 |
| #define bHDRX_PHY_PRBS_LOCK_STAT_ch0 1 |
| #define MSK32HDRX_PHY_PRBS_LOCK_STAT_ch0 0x00000001 |
| #define BA_HDRX_PHY_PRBS_LOCK_STAT_ch1 0x04F0 |
| #define B16HDRX_PHY_PRBS_LOCK_STAT_ch1 0x04F0 |
| #define LSb32HDRX_PHY_PRBS_LOCK_STAT_ch1 1 |
| #define LSb16HDRX_PHY_PRBS_LOCK_STAT_ch1 1 |
| #define bHDRX_PHY_PRBS_LOCK_STAT_ch1 1 |
| #define MSK32HDRX_PHY_PRBS_LOCK_STAT_ch1 0x00000002 |
| #define BA_HDRX_PHY_PRBS_LOCK_STAT_ch2 0x04F0 |
| #define B16HDRX_PHY_PRBS_LOCK_STAT_ch2 0x04F0 |
| #define LSb32HDRX_PHY_PRBS_LOCK_STAT_ch2 2 |
| #define LSb16HDRX_PHY_PRBS_LOCK_STAT_ch2 2 |
| #define bHDRX_PHY_PRBS_LOCK_STAT_ch2 1 |
| #define MSK32HDRX_PHY_PRBS_LOCK_STAT_ch2 0x00000004 |
| #define RA_HDRX_PHY_PRBS_CH0_ERR 0x04F4 |
| #define BA_HDRX_PHY_PRBS_CH0_ERR_cnt 0x04F4 |
| #define B16HDRX_PHY_PRBS_CH0_ERR_cnt 0x04F4 |
| #define LSb32HDRX_PHY_PRBS_CH0_ERR_cnt 0 |
| #define LSb16HDRX_PHY_PRBS_CH0_ERR_cnt 0 |
| #define bHDRX_PHY_PRBS_CH0_ERR_cnt 32 |
| #define MSK32HDRX_PHY_PRBS_CH0_ERR_cnt 0xFFFFFFFF |
| #define RA_HDRX_PHY_PRBS_CH1_ERR 0x04F8 |
| #define BA_HDRX_PHY_PRBS_CH1_ERR_cnt 0x04F8 |
| #define B16HDRX_PHY_PRBS_CH1_ERR_cnt 0x04F8 |
| #define LSb32HDRX_PHY_PRBS_CH1_ERR_cnt 0 |
| #define LSb16HDRX_PHY_PRBS_CH1_ERR_cnt 0 |
| #define bHDRX_PHY_PRBS_CH1_ERR_cnt 32 |
| #define MSK32HDRX_PHY_PRBS_CH1_ERR_cnt 0xFFFFFFFF |
| #define RA_HDRX_PHY_PRBS_CH2_ERR 0x04FC |
| #define BA_HDRX_PHY_PRBS_CH2_ERR_cnt 0x04FC |
| #define B16HDRX_PHY_PRBS_CH2_ERR_cnt 0x04FC |
| #define LSb32HDRX_PHY_PRBS_CH2_ERR_cnt 0 |
| #define LSb16HDRX_PHY_PRBS_CH2_ERR_cnt 0 |
| #define bHDRX_PHY_PRBS_CH2_ERR_cnt 32 |
| #define MSK32HDRX_PHY_PRBS_CH2_ERR_cnt 0xFFFFFFFF |
| #define RA_HDRX_PHY_LB_CTRL 0x0500 |
| #define BA_HDRX_PHY_LB_CTRL_ctrl 0x0500 |
| #define B16HDRX_PHY_LB_CTRL_ctrl 0x0500 |
| #define LSb32HDRX_PHY_LB_CTRL_ctrl 0 |
| #define LSb16HDRX_PHY_LB_CTRL_ctrl 0 |
| #define bHDRX_PHY_LB_CTRL_ctrl 8 |
| #define MSK32HDRX_PHY_LB_CTRL_ctrl 0x000000FF |
| #define BA_HDRX_PHY_LB_CTRL_en 0x0501 |
| #define B16HDRX_PHY_LB_CTRL_en 0x0500 |
| #define LSb32HDRX_PHY_LB_CTRL_en 8 |
| #define LSb16HDRX_PHY_LB_CTRL_en 8 |
| #define bHDRX_PHY_LB_CTRL_en 1 |
| #define MSK32HDRX_PHY_LB_CTRL_en 0x00000100 |
| #define BA_HDRX_PHY_LB_CTRL_prbs_type 0x0501 |
| #define B16HDRX_PHY_LB_CTRL_prbs_type 0x0500 |
| #define LSb32HDRX_PHY_LB_CTRL_prbs_type 9 |
| #define LSb16HDRX_PHY_LB_CTRL_prbs_type 9 |
| #define bHDRX_PHY_LB_CTRL_prbs_type 2 |
| #define MSK32HDRX_PHY_LB_CTRL_prbs_type 0x00000600 |
| #define BA_HDRX_PHY_LB_CTRL_prbs_en 0x0501 |
| #define B16HDRX_PHY_LB_CTRL_prbs_en 0x0500 |
| #define LSb32HDRX_PHY_LB_CTRL_prbs_en 11 |
| #define LSb16HDRX_PHY_LB_CTRL_prbs_en 11 |
| #define bHDRX_PHY_LB_CTRL_prbs_en 1 |
| #define MSK32HDRX_PHY_LB_CTRL_prbs_en 0x00000800 |
| #define RA_HDRX_HDCP_ENC_DEC_CTRL 0x0504 |
| #define BA_HDRX_HDCP_ENC_DEC_CTRL_cipher_gen_ctrl 0x0504 |
| #define B16HDRX_HDCP_ENC_DEC_CTRL_cipher_gen_ctrl 0x0504 |
| #define LSb32HDRX_HDCP_ENC_DEC_CTRL_cipher_gen_ctrl 0 |
| #define LSb16HDRX_HDCP_ENC_DEC_CTRL_cipher_gen_ctrl 0 |
| #define bHDRX_HDCP_ENC_DEC_CTRL_cipher_gen_ctrl 2 |
| #define MSK32HDRX_HDCP_ENC_DEC_CTRL_cipher_gen_ctrl 0x00000003 |
| #define BA_HDRX_HDCP_ENC_DEC_CTRL_avmute_enc_dec_win 0x0504 |
| #define B16HDRX_HDCP_ENC_DEC_CTRL_avmute_enc_dec_win 0x0504 |
| #define LSb32HDRX_HDCP_ENC_DEC_CTRL_avmute_enc_dec_win 2 |
| #define LSb16HDRX_HDCP_ENC_DEC_CTRL_avmute_enc_dec_win 2 |
| #define bHDRX_HDCP_ENC_DEC_CTRL_avmute_enc_dec_win 1 |
| #define MSK32HDRX_HDCP_ENC_DEC_CTRL_avmute_enc_dec_win 0x00000004 |
| #define RA_HDRX_HDCP_KS 0x0508 |
| #define BA_HDRX_HDCP_KS_bytes_0_to_3 0x0508 |
| #define B16HDRX_HDCP_KS_bytes_0_to_3 0x0508 |
| #define LSb32HDRX_HDCP_KS_bytes_0_to_3 0 |
| #define LSb16HDRX_HDCP_KS_bytes_0_to_3 0 |
| #define bHDRX_HDCP_KS_bytes_0_to_3 32 |
| #define MSK32HDRX_HDCP_KS_bytes_0_to_3 0xFFFFFFFF |
| #define RA_HDRX_HDCP_KS1 0x050C |
| #define BA_HDRX_HDCP_KS_bytes_4_to_7 0x050C |
| #define B16HDRX_HDCP_KS_bytes_4_to_7 0x050C |
| #define LSb32HDRX_HDCP_KS_bytes_4_to_7 0 |
| #define LSb16HDRX_HDCP_KS_bytes_4_to_7 0 |
| #define bHDRX_HDCP_KS_bytes_4_to_7 32 |
| #define MSK32HDRX_HDCP_KS_bytes_4_to_7 0xFFFFFFFF |
| #define RA_HDRX_HDCP_KS2 0x0510 |
| #define BA_HDRX_HDCP_KS_bytes_8_to_11 0x0510 |
| #define B16HDRX_HDCP_KS_bytes_8_to_11 0x0510 |
| #define LSb32HDRX_HDCP_KS_bytes_8_to_11 0 |
| #define LSb16HDRX_HDCP_KS_bytes_8_to_11 0 |
| #define bHDRX_HDCP_KS_bytes_8_to_11 32 |
| #define MSK32HDRX_HDCP_KS_bytes_8_to_11 0xFFFFFFFF |
| #define RA_HDRX_HDCP_KS3 0x0514 |
| #define BA_HDRX_HDCP_KS_bytes_12_to_15 0x0514 |
| #define B16HDRX_HDCP_KS_bytes_12_to_15 0x0514 |
| #define LSb32HDRX_HDCP_KS_bytes_12_to_15 0 |
| #define LSb16HDRX_HDCP_KS_bytes_12_to_15 0 |
| #define bHDRX_HDCP_KS_bytes_12_to_15 32 |
| #define MSK32HDRX_HDCP_KS_bytes_12_to_15 0xFFFFFFFF |
| #define RA_HDRX_HDCP_LC 0x0518 |
| #define BA_HDRX_HDCP_LC_bytes_0_to_3 0x0518 |
| #define B16HDRX_HDCP_LC_bytes_0_to_3 0x0518 |
| #define LSb32HDRX_HDCP_LC_bytes_0_to_3 0 |
| #define LSb16HDRX_HDCP_LC_bytes_0_to_3 0 |
| #define bHDRX_HDCP_LC_bytes_0_to_3 32 |
| #define MSK32HDRX_HDCP_LC_bytes_0_to_3 0xFFFFFFFF |
| #define RA_HDRX_HDCP_LC1 0x051C |
| #define BA_HDRX_HDCP_LC_bytes_4_to_7 0x051C |
| #define B16HDRX_HDCP_LC_bytes_4_to_7 0x051C |
| #define LSb32HDRX_HDCP_LC_bytes_4_to_7 0 |
| #define LSb16HDRX_HDCP_LC_bytes_4_to_7 0 |
| #define bHDRX_HDCP_LC_bytes_4_to_7 32 |
| #define MSK32HDRX_HDCP_LC_bytes_4_to_7 0xFFFFFFFF |
| #define RA_HDRX_HDCP_LC2 0x0520 |
| #define BA_HDRX_HDCP_LC_bytes_8_to_11 0x0520 |
| #define B16HDRX_HDCP_LC_bytes_8_to_11 0x0520 |
| #define LSb32HDRX_HDCP_LC_bytes_8_to_11 0 |
| #define LSb16HDRX_HDCP_LC_bytes_8_to_11 0 |
| #define bHDRX_HDCP_LC_bytes_8_to_11 32 |
| #define MSK32HDRX_HDCP_LC_bytes_8_to_11 0xFFFFFFFF |
| #define RA_HDRX_HDCP_LC3 0x0524 |
| #define BA_HDRX_HDCP_LC_bytes_12_to_15 0x0524 |
| #define B16HDRX_HDCP_LC_bytes_12_to_15 0x0524 |
| #define LSb32HDRX_HDCP_LC_bytes_12_to_15 0 |
| #define LSb16HDRX_HDCP_LC_bytes_12_to_15 0 |
| #define bHDRX_HDCP_LC_bytes_12_to_15 32 |
| #define MSK32HDRX_HDCP_LC_bytes_12_to_15 0xFFFFFFFF |
| #define RA_HDRX_HDCP_RIV 0x0528 |
| #define BA_HDRX_HDCP_RIV_bytes_0_to_3 0x0528 |
| #define B16HDRX_HDCP_RIV_bytes_0_to_3 0x0528 |
| #define LSb32HDRX_HDCP_RIV_bytes_0_to_3 0 |
| #define LSb16HDRX_HDCP_RIV_bytes_0_to_3 0 |
| #define bHDRX_HDCP_RIV_bytes_0_to_3 32 |
| #define MSK32HDRX_HDCP_RIV_bytes_0_to_3 0xFFFFFFFF |
| #define RA_HDRX_HDCP_RIV1 0x052C |
| #define BA_HDRX_HDCP_RIV_bytes_4_to_7 0x052C |
| #define B16HDRX_HDCP_RIV_bytes_4_to_7 0x052C |
| #define LSb32HDRX_HDCP_RIV_bytes_4_to_7 0 |
| #define LSb16HDRX_HDCP_RIV_bytes_4_to_7 0 |
| #define bHDRX_HDCP_RIV_bytes_4_to_7 32 |
| #define MSK32HDRX_HDCP_RIV_bytes_4_to_7 0xFFFFFFFF |
| #define RA_HDRX_KS_READY 0x0530 |
| #define BA_HDRX_KS_READY_ks_ready 0x0530 |
| #define B16HDRX_KS_READY_ks_ready 0x0530 |
| #define LSb32HDRX_KS_READY_ks_ready 0 |
| #define LSb16HDRX_KS_READY_ks_ready 0 |
| #define bHDRX_KS_READY_ks_ready 1 |
| #define MSK32HDRX_KS_READY_ks_ready 0x00000001 |
| #define RA_HDRX_RX_STATUS 0x0534 |
| #define BA_HDRX_RX_STATUS_message_size 0x0534 |
| #define B16HDRX_RX_STATUS_message_size 0x0534 |
| #define LSb32HDRX_RX_STATUS_message_size 0 |
| #define LSb16HDRX_RX_STATUS_message_size 0 |
| #define bHDRX_RX_STATUS_message_size 10 |
| #define MSK32HDRX_RX_STATUS_message_size 0x000003FF |
| #define BA_HDRX_RX_STATUS_ready 0x0535 |
| #define B16HDRX_RX_STATUS_ready 0x0534 |
| #define LSb32HDRX_RX_STATUS_ready 10 |
| #define LSb16HDRX_RX_STATUS_ready 10 |
| #define bHDRX_RX_STATUS_ready 1 |
| #define MSK32HDRX_RX_STATUS_ready 0x00000400 |
| #define BA_HDRX_RX_STATUS_reauth_req_set 0x0535 |
| #define B16HDRX_RX_STATUS_reauth_req_set 0x0534 |
| #define LSb32HDRX_RX_STATUS_reauth_req_set 11 |
| #define LSb16HDRX_RX_STATUS_reauth_req_set 11 |
| #define bHDRX_RX_STATUS_reauth_req_set 1 |
| #define MSK32HDRX_RX_STATUS_reauth_req_set 0x00000800 |
| #define BA_HDRX_RX_STATUS_reauth_req_clr 0x0535 |
| #define B16HDRX_RX_STATUS_reauth_req_clr 0x0534 |
| #define LSb32HDRX_RX_STATUS_reauth_req_clr 12 |
| #define LSb16HDRX_RX_STATUS_reauth_req_clr 12 |
| #define bHDRX_RX_STATUS_reauth_req_clr 1 |
| #define MSK32HDRX_RX_STATUS_reauth_req_clr 0x00001000 |
| #define RA_HDRX_RX_STATUS_DBG 0x0538 |
| #define BA_HDRX_RX_STATUS_DBG_message_size 0x0538 |
| #define B16HDRX_RX_STATUS_DBG_message_size 0x0538 |
| #define LSb32HDRX_RX_STATUS_DBG_message_size 0 |
| #define LSb16HDRX_RX_STATUS_DBG_message_size 0 |
| #define bHDRX_RX_STATUS_DBG_message_size 10 |
| #define MSK32HDRX_RX_STATUS_DBG_message_size 0x000003FF |
| #define BA_HDRX_RX_STATUS_DBG_ready 0x0539 |
| #define B16HDRX_RX_STATUS_DBG_ready 0x0538 |
| #define LSb32HDRX_RX_STATUS_DBG_ready 10 |
| #define LSb16HDRX_RX_STATUS_DBG_ready 10 |
| #define bHDRX_RX_STATUS_DBG_ready 1 |
| #define MSK32HDRX_RX_STATUS_DBG_ready 0x00000400 |
| #define BA_HDRX_RX_STATUS_DBG_reauth_req 0x0539 |
| #define B16HDRX_RX_STATUS_DBG_reauth_req 0x0538 |
| #define LSb32HDRX_RX_STATUS_DBG_reauth_req 11 |
| #define LSb16HDRX_RX_STATUS_DBG_reauth_req 11 |
| #define bHDRX_RX_STATUS_DBG_reauth_req 1 |
| #define MSK32HDRX_RX_STATUS_DBG_reauth_req 0x00000800 |
| #define RA_HDRX_HDCP_MISC_RO 0x053C |
| #define BA_HDRX_HDCP_MISC_RO_data_wr_cnt 0x053C |
| #define B16HDRX_HDCP_MISC_RO_data_wr_cnt 0x053C |
| #define LSb32HDRX_HDCP_MISC_RO_data_wr_cnt 0 |
| #define LSb16HDRX_HDCP_MISC_RO_data_wr_cnt 0 |
| #define bHDRX_HDCP_MISC_RO_data_wr_cnt 8 |
| #define MSK32HDRX_HDCP_MISC_RO_data_wr_cnt 0x000000FF |
| #define RA_HDRX_HDCP_WR_FIFO 0x0540 |
| #define BA_HDRX_HDCP_WR_FIFO_byte0 0x0540 |
| #define B16HDRX_HDCP_WR_FIFO_byte0 0x0540 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte0 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte0 0 |
| #define bHDRX_HDCP_WR_FIFO_byte0 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte0 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte1 0x0541 |
| #define B16HDRX_HDCP_WR_FIFO_byte1 0x0540 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte1 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte1 8 |
| #define bHDRX_HDCP_WR_FIFO_byte1 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte1 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte2 0x0542 |
| #define B16HDRX_HDCP_WR_FIFO_byte2 0x0542 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte2 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte2 0 |
| #define bHDRX_HDCP_WR_FIFO_byte2 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte2 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte3 0x0543 |
| #define B16HDRX_HDCP_WR_FIFO_byte3 0x0542 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte3 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte3 8 |
| #define bHDRX_HDCP_WR_FIFO_byte3 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte3 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO1 0x0544 |
| #define BA_HDRX_HDCP_WR_FIFO_byte4 0x0544 |
| #define B16HDRX_HDCP_WR_FIFO_byte4 0x0544 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte4 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte4 0 |
| #define bHDRX_HDCP_WR_FIFO_byte4 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte4 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte5 0x0545 |
| #define B16HDRX_HDCP_WR_FIFO_byte5 0x0544 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte5 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte5 8 |
| #define bHDRX_HDCP_WR_FIFO_byte5 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte5 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte6 0x0546 |
| #define B16HDRX_HDCP_WR_FIFO_byte6 0x0546 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte6 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte6 0 |
| #define bHDRX_HDCP_WR_FIFO_byte6 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte6 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte7 0x0547 |
| #define B16HDRX_HDCP_WR_FIFO_byte7 0x0546 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte7 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte7 8 |
| #define bHDRX_HDCP_WR_FIFO_byte7 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte7 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO2 0x0548 |
| #define BA_HDRX_HDCP_WR_FIFO_byte8 0x0548 |
| #define B16HDRX_HDCP_WR_FIFO_byte8 0x0548 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte8 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte8 0 |
| #define bHDRX_HDCP_WR_FIFO_byte8 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte8 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte9 0x0549 |
| #define B16HDRX_HDCP_WR_FIFO_byte9 0x0548 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte9 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte9 8 |
| #define bHDRX_HDCP_WR_FIFO_byte9 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte9 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte10 0x054A |
| #define B16HDRX_HDCP_WR_FIFO_byte10 0x054A |
| #define LSb32HDRX_HDCP_WR_FIFO_byte10 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte10 0 |
| #define bHDRX_HDCP_WR_FIFO_byte10 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte10 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte11 0x054B |
| #define B16HDRX_HDCP_WR_FIFO_byte11 0x054A |
| #define LSb32HDRX_HDCP_WR_FIFO_byte11 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte11 8 |
| #define bHDRX_HDCP_WR_FIFO_byte11 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte11 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO3 0x054C |
| #define BA_HDRX_HDCP_WR_FIFO_byte12 0x054C |
| #define B16HDRX_HDCP_WR_FIFO_byte12 0x054C |
| #define LSb32HDRX_HDCP_WR_FIFO_byte12 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte12 0 |
| #define bHDRX_HDCP_WR_FIFO_byte12 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte12 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte13 0x054D |
| #define B16HDRX_HDCP_WR_FIFO_byte13 0x054C |
| #define LSb32HDRX_HDCP_WR_FIFO_byte13 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte13 8 |
| #define bHDRX_HDCP_WR_FIFO_byte13 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte13 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte14 0x054E |
| #define B16HDRX_HDCP_WR_FIFO_byte14 0x054E |
| #define LSb32HDRX_HDCP_WR_FIFO_byte14 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte14 0 |
| #define bHDRX_HDCP_WR_FIFO_byte14 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte14 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte15 0x054F |
| #define B16HDRX_HDCP_WR_FIFO_byte15 0x054E |
| #define LSb32HDRX_HDCP_WR_FIFO_byte15 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte15 8 |
| #define bHDRX_HDCP_WR_FIFO_byte15 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte15 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO4 0x0550 |
| #define BA_HDRX_HDCP_WR_FIFO_byte16 0x0550 |
| #define B16HDRX_HDCP_WR_FIFO_byte16 0x0550 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte16 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte16 0 |
| #define bHDRX_HDCP_WR_FIFO_byte16 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte16 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte17 0x0551 |
| #define B16HDRX_HDCP_WR_FIFO_byte17 0x0550 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte17 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte17 8 |
| #define bHDRX_HDCP_WR_FIFO_byte17 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte17 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte18 0x0552 |
| #define B16HDRX_HDCP_WR_FIFO_byte18 0x0552 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte18 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte18 0 |
| #define bHDRX_HDCP_WR_FIFO_byte18 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte18 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte19 0x0553 |
| #define B16HDRX_HDCP_WR_FIFO_byte19 0x0552 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte19 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte19 8 |
| #define bHDRX_HDCP_WR_FIFO_byte19 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte19 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO5 0x0554 |
| #define BA_HDRX_HDCP_WR_FIFO_byte20 0x0554 |
| #define B16HDRX_HDCP_WR_FIFO_byte20 0x0554 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte20 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte20 0 |
| #define bHDRX_HDCP_WR_FIFO_byte20 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte20 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte21 0x0555 |
| #define B16HDRX_HDCP_WR_FIFO_byte21 0x0554 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte21 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte21 8 |
| #define bHDRX_HDCP_WR_FIFO_byte21 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte21 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte22 0x0556 |
| #define B16HDRX_HDCP_WR_FIFO_byte22 0x0556 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte22 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte22 0 |
| #define bHDRX_HDCP_WR_FIFO_byte22 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte22 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte23 0x0557 |
| #define B16HDRX_HDCP_WR_FIFO_byte23 0x0556 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte23 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte23 8 |
| #define bHDRX_HDCP_WR_FIFO_byte23 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte23 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO6 0x0558 |
| #define BA_HDRX_HDCP_WR_FIFO_byte24 0x0558 |
| #define B16HDRX_HDCP_WR_FIFO_byte24 0x0558 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte24 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte24 0 |
| #define bHDRX_HDCP_WR_FIFO_byte24 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte24 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte25 0x0559 |
| #define B16HDRX_HDCP_WR_FIFO_byte25 0x0558 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte25 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte25 8 |
| #define bHDRX_HDCP_WR_FIFO_byte25 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte25 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte26 0x055A |
| #define B16HDRX_HDCP_WR_FIFO_byte26 0x055A |
| #define LSb32HDRX_HDCP_WR_FIFO_byte26 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte26 0 |
| #define bHDRX_HDCP_WR_FIFO_byte26 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte26 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte27 0x055B |
| #define B16HDRX_HDCP_WR_FIFO_byte27 0x055A |
| #define LSb32HDRX_HDCP_WR_FIFO_byte27 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte27 8 |
| #define bHDRX_HDCP_WR_FIFO_byte27 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte27 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO7 0x055C |
| #define BA_HDRX_HDCP_WR_FIFO_byte28 0x055C |
| #define B16HDRX_HDCP_WR_FIFO_byte28 0x055C |
| #define LSb32HDRX_HDCP_WR_FIFO_byte28 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte28 0 |
| #define bHDRX_HDCP_WR_FIFO_byte28 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte28 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte29 0x055D |
| #define B16HDRX_HDCP_WR_FIFO_byte29 0x055C |
| #define LSb32HDRX_HDCP_WR_FIFO_byte29 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte29 8 |
| #define bHDRX_HDCP_WR_FIFO_byte29 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte29 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte30 0x055E |
| #define B16HDRX_HDCP_WR_FIFO_byte30 0x055E |
| #define LSb32HDRX_HDCP_WR_FIFO_byte30 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte30 0 |
| #define bHDRX_HDCP_WR_FIFO_byte30 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte30 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte31 0x055F |
| #define B16HDRX_HDCP_WR_FIFO_byte31 0x055E |
| #define LSb32HDRX_HDCP_WR_FIFO_byte31 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte31 8 |
| #define bHDRX_HDCP_WR_FIFO_byte31 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte31 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO8 0x0560 |
| #define BA_HDRX_HDCP_WR_FIFO_byte32 0x0560 |
| #define B16HDRX_HDCP_WR_FIFO_byte32 0x0560 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte32 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte32 0 |
| #define bHDRX_HDCP_WR_FIFO_byte32 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte32 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte33 0x0561 |
| #define B16HDRX_HDCP_WR_FIFO_byte33 0x0560 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte33 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte33 8 |
| #define bHDRX_HDCP_WR_FIFO_byte33 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte33 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte34 0x0562 |
| #define B16HDRX_HDCP_WR_FIFO_byte34 0x0562 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte34 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte34 0 |
| #define bHDRX_HDCP_WR_FIFO_byte34 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte34 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte35 0x0563 |
| #define B16HDRX_HDCP_WR_FIFO_byte35 0x0562 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte35 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte35 8 |
| #define bHDRX_HDCP_WR_FIFO_byte35 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte35 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO9 0x0564 |
| #define BA_HDRX_HDCP_WR_FIFO_byte36 0x0564 |
| #define B16HDRX_HDCP_WR_FIFO_byte36 0x0564 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte36 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte36 0 |
| #define bHDRX_HDCP_WR_FIFO_byte36 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte36 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte37 0x0565 |
| #define B16HDRX_HDCP_WR_FIFO_byte37 0x0564 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte37 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte37 8 |
| #define bHDRX_HDCP_WR_FIFO_byte37 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte37 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte38 0x0566 |
| #define B16HDRX_HDCP_WR_FIFO_byte38 0x0566 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte38 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte38 0 |
| #define bHDRX_HDCP_WR_FIFO_byte38 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte38 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte39 0x0567 |
| #define B16HDRX_HDCP_WR_FIFO_byte39 0x0566 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte39 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte39 8 |
| #define bHDRX_HDCP_WR_FIFO_byte39 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte39 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO10 0x0568 |
| #define BA_HDRX_HDCP_WR_FIFO_byte40 0x0568 |
| #define B16HDRX_HDCP_WR_FIFO_byte40 0x0568 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte40 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte40 0 |
| #define bHDRX_HDCP_WR_FIFO_byte40 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte40 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte41 0x0569 |
| #define B16HDRX_HDCP_WR_FIFO_byte41 0x0568 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte41 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte41 8 |
| #define bHDRX_HDCP_WR_FIFO_byte41 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte41 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte42 0x056A |
| #define B16HDRX_HDCP_WR_FIFO_byte42 0x056A |
| #define LSb32HDRX_HDCP_WR_FIFO_byte42 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte42 0 |
| #define bHDRX_HDCP_WR_FIFO_byte42 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte42 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte43 0x056B |
| #define B16HDRX_HDCP_WR_FIFO_byte43 0x056A |
| #define LSb32HDRX_HDCP_WR_FIFO_byte43 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte43 8 |
| #define bHDRX_HDCP_WR_FIFO_byte43 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte43 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO11 0x056C |
| #define BA_HDRX_HDCP_WR_FIFO_byte44 0x056C |
| #define B16HDRX_HDCP_WR_FIFO_byte44 0x056C |
| #define LSb32HDRX_HDCP_WR_FIFO_byte44 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte44 0 |
| #define bHDRX_HDCP_WR_FIFO_byte44 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte44 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte45 0x056D |
| #define B16HDRX_HDCP_WR_FIFO_byte45 0x056C |
| #define LSb32HDRX_HDCP_WR_FIFO_byte45 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte45 8 |
| #define bHDRX_HDCP_WR_FIFO_byte45 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte45 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte46 0x056E |
| #define B16HDRX_HDCP_WR_FIFO_byte46 0x056E |
| #define LSb32HDRX_HDCP_WR_FIFO_byte46 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte46 0 |
| #define bHDRX_HDCP_WR_FIFO_byte46 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte46 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte47 0x056F |
| #define B16HDRX_HDCP_WR_FIFO_byte47 0x056E |
| #define LSb32HDRX_HDCP_WR_FIFO_byte47 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte47 8 |
| #define bHDRX_HDCP_WR_FIFO_byte47 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte47 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO12 0x0570 |
| #define BA_HDRX_HDCP_WR_FIFO_byte48 0x0570 |
| #define B16HDRX_HDCP_WR_FIFO_byte48 0x0570 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte48 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte48 0 |
| #define bHDRX_HDCP_WR_FIFO_byte48 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte48 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte49 0x0571 |
| #define B16HDRX_HDCP_WR_FIFO_byte49 0x0570 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte49 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte49 8 |
| #define bHDRX_HDCP_WR_FIFO_byte49 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte49 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte50 0x0572 |
| #define B16HDRX_HDCP_WR_FIFO_byte50 0x0572 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte50 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte50 0 |
| #define bHDRX_HDCP_WR_FIFO_byte50 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte50 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte51 0x0573 |
| #define B16HDRX_HDCP_WR_FIFO_byte51 0x0572 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte51 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte51 8 |
| #define bHDRX_HDCP_WR_FIFO_byte51 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte51 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO13 0x0574 |
| #define BA_HDRX_HDCP_WR_FIFO_byte52 0x0574 |
| #define B16HDRX_HDCP_WR_FIFO_byte52 0x0574 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte52 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte52 0 |
| #define bHDRX_HDCP_WR_FIFO_byte52 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte52 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte53 0x0575 |
| #define B16HDRX_HDCP_WR_FIFO_byte53 0x0574 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte53 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte53 8 |
| #define bHDRX_HDCP_WR_FIFO_byte53 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte53 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte54 0x0576 |
| #define B16HDRX_HDCP_WR_FIFO_byte54 0x0576 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte54 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte54 0 |
| #define bHDRX_HDCP_WR_FIFO_byte54 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte54 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte55 0x0577 |
| #define B16HDRX_HDCP_WR_FIFO_byte55 0x0576 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte55 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte55 8 |
| #define bHDRX_HDCP_WR_FIFO_byte55 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte55 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO14 0x0578 |
| #define BA_HDRX_HDCP_WR_FIFO_byte56 0x0578 |
| #define B16HDRX_HDCP_WR_FIFO_byte56 0x0578 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte56 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte56 0 |
| #define bHDRX_HDCP_WR_FIFO_byte56 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte56 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte57 0x0579 |
| #define B16HDRX_HDCP_WR_FIFO_byte57 0x0578 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte57 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte57 8 |
| #define bHDRX_HDCP_WR_FIFO_byte57 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte57 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte58 0x057A |
| #define B16HDRX_HDCP_WR_FIFO_byte58 0x057A |
| #define LSb32HDRX_HDCP_WR_FIFO_byte58 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte58 0 |
| #define bHDRX_HDCP_WR_FIFO_byte58 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte58 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte59 0x057B |
| #define B16HDRX_HDCP_WR_FIFO_byte59 0x057A |
| #define LSb32HDRX_HDCP_WR_FIFO_byte59 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte59 8 |
| #define bHDRX_HDCP_WR_FIFO_byte59 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte59 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO15 0x057C |
| #define BA_HDRX_HDCP_WR_FIFO_byte60 0x057C |
| #define B16HDRX_HDCP_WR_FIFO_byte60 0x057C |
| #define LSb32HDRX_HDCP_WR_FIFO_byte60 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte60 0 |
| #define bHDRX_HDCP_WR_FIFO_byte60 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte60 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte61 0x057D |
| #define B16HDRX_HDCP_WR_FIFO_byte61 0x057C |
| #define LSb32HDRX_HDCP_WR_FIFO_byte61 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte61 8 |
| #define bHDRX_HDCP_WR_FIFO_byte61 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte61 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte62 0x057E |
| #define B16HDRX_HDCP_WR_FIFO_byte62 0x057E |
| #define LSb32HDRX_HDCP_WR_FIFO_byte62 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte62 0 |
| #define bHDRX_HDCP_WR_FIFO_byte62 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte62 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte63 0x057F |
| #define B16HDRX_HDCP_WR_FIFO_byte63 0x057E |
| #define LSb32HDRX_HDCP_WR_FIFO_byte63 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte63 8 |
| #define bHDRX_HDCP_WR_FIFO_byte63 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte63 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO16 0x0580 |
| #define BA_HDRX_HDCP_WR_FIFO_byte64 0x0580 |
| #define B16HDRX_HDCP_WR_FIFO_byte64 0x0580 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte64 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte64 0 |
| #define bHDRX_HDCP_WR_FIFO_byte64 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte64 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte65 0x0581 |
| #define B16HDRX_HDCP_WR_FIFO_byte65 0x0580 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte65 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte65 8 |
| #define bHDRX_HDCP_WR_FIFO_byte65 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte65 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte66 0x0582 |
| #define B16HDRX_HDCP_WR_FIFO_byte66 0x0582 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte66 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte66 0 |
| #define bHDRX_HDCP_WR_FIFO_byte66 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte66 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte67 0x0583 |
| #define B16HDRX_HDCP_WR_FIFO_byte67 0x0582 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte67 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte67 8 |
| #define bHDRX_HDCP_WR_FIFO_byte67 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte67 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO17 0x0584 |
| #define BA_HDRX_HDCP_WR_FIFO_byte68 0x0584 |
| #define B16HDRX_HDCP_WR_FIFO_byte68 0x0584 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte68 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte68 0 |
| #define bHDRX_HDCP_WR_FIFO_byte68 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte68 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte69 0x0585 |
| #define B16HDRX_HDCP_WR_FIFO_byte69 0x0584 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte69 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte69 8 |
| #define bHDRX_HDCP_WR_FIFO_byte69 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte69 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte70 0x0586 |
| #define B16HDRX_HDCP_WR_FIFO_byte70 0x0586 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte70 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte70 0 |
| #define bHDRX_HDCP_WR_FIFO_byte70 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte70 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte71 0x0587 |
| #define B16HDRX_HDCP_WR_FIFO_byte71 0x0586 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte71 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte71 8 |
| #define bHDRX_HDCP_WR_FIFO_byte71 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte71 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO18 0x0588 |
| #define BA_HDRX_HDCP_WR_FIFO_byte72 0x0588 |
| #define B16HDRX_HDCP_WR_FIFO_byte72 0x0588 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte72 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte72 0 |
| #define bHDRX_HDCP_WR_FIFO_byte72 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte72 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte73 0x0589 |
| #define B16HDRX_HDCP_WR_FIFO_byte73 0x0588 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte73 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte73 8 |
| #define bHDRX_HDCP_WR_FIFO_byte73 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte73 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte74 0x058A |
| #define B16HDRX_HDCP_WR_FIFO_byte74 0x058A |
| #define LSb32HDRX_HDCP_WR_FIFO_byte74 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte74 0 |
| #define bHDRX_HDCP_WR_FIFO_byte74 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte74 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte75 0x058B |
| #define B16HDRX_HDCP_WR_FIFO_byte75 0x058A |
| #define LSb32HDRX_HDCP_WR_FIFO_byte75 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte75 8 |
| #define bHDRX_HDCP_WR_FIFO_byte75 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte75 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO19 0x058C |
| #define BA_HDRX_HDCP_WR_FIFO_byte76 0x058C |
| #define B16HDRX_HDCP_WR_FIFO_byte76 0x058C |
| #define LSb32HDRX_HDCP_WR_FIFO_byte76 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte76 0 |
| #define bHDRX_HDCP_WR_FIFO_byte76 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte76 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte77 0x058D |
| #define B16HDRX_HDCP_WR_FIFO_byte77 0x058C |
| #define LSb32HDRX_HDCP_WR_FIFO_byte77 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte77 8 |
| #define bHDRX_HDCP_WR_FIFO_byte77 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte77 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte78 0x058E |
| #define B16HDRX_HDCP_WR_FIFO_byte78 0x058E |
| #define LSb32HDRX_HDCP_WR_FIFO_byte78 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte78 0 |
| #define bHDRX_HDCP_WR_FIFO_byte78 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte78 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte79 0x058F |
| #define B16HDRX_HDCP_WR_FIFO_byte79 0x058E |
| #define LSb32HDRX_HDCP_WR_FIFO_byte79 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte79 8 |
| #define bHDRX_HDCP_WR_FIFO_byte79 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte79 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO20 0x0590 |
| #define BA_HDRX_HDCP_WR_FIFO_byte80 0x0590 |
| #define B16HDRX_HDCP_WR_FIFO_byte80 0x0590 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte80 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte80 0 |
| #define bHDRX_HDCP_WR_FIFO_byte80 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte80 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte81 0x0591 |
| #define B16HDRX_HDCP_WR_FIFO_byte81 0x0590 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte81 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte81 8 |
| #define bHDRX_HDCP_WR_FIFO_byte81 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte81 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte82 0x0592 |
| #define B16HDRX_HDCP_WR_FIFO_byte82 0x0592 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte82 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte82 0 |
| #define bHDRX_HDCP_WR_FIFO_byte82 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte82 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte83 0x0593 |
| #define B16HDRX_HDCP_WR_FIFO_byte83 0x0592 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte83 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte83 8 |
| #define bHDRX_HDCP_WR_FIFO_byte83 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte83 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO21 0x0594 |
| #define BA_HDRX_HDCP_WR_FIFO_byte84 0x0594 |
| #define B16HDRX_HDCP_WR_FIFO_byte84 0x0594 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte84 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte84 0 |
| #define bHDRX_HDCP_WR_FIFO_byte84 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte84 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte85 0x0595 |
| #define B16HDRX_HDCP_WR_FIFO_byte85 0x0594 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte85 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte85 8 |
| #define bHDRX_HDCP_WR_FIFO_byte85 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte85 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte86 0x0596 |
| #define B16HDRX_HDCP_WR_FIFO_byte86 0x0596 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte86 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte86 0 |
| #define bHDRX_HDCP_WR_FIFO_byte86 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte86 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte87 0x0597 |
| #define B16HDRX_HDCP_WR_FIFO_byte87 0x0596 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte87 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte87 8 |
| #define bHDRX_HDCP_WR_FIFO_byte87 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte87 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO22 0x0598 |
| #define BA_HDRX_HDCP_WR_FIFO_byte88 0x0598 |
| #define B16HDRX_HDCP_WR_FIFO_byte88 0x0598 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte88 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte88 0 |
| #define bHDRX_HDCP_WR_FIFO_byte88 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte88 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte89 0x0599 |
| #define B16HDRX_HDCP_WR_FIFO_byte89 0x0598 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte89 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte89 8 |
| #define bHDRX_HDCP_WR_FIFO_byte89 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte89 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte90 0x059A |
| #define B16HDRX_HDCP_WR_FIFO_byte90 0x059A |
| #define LSb32HDRX_HDCP_WR_FIFO_byte90 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte90 0 |
| #define bHDRX_HDCP_WR_FIFO_byte90 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte90 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte91 0x059B |
| #define B16HDRX_HDCP_WR_FIFO_byte91 0x059A |
| #define LSb32HDRX_HDCP_WR_FIFO_byte91 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte91 8 |
| #define bHDRX_HDCP_WR_FIFO_byte91 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte91 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO23 0x059C |
| #define BA_HDRX_HDCP_WR_FIFO_byte92 0x059C |
| #define B16HDRX_HDCP_WR_FIFO_byte92 0x059C |
| #define LSb32HDRX_HDCP_WR_FIFO_byte92 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte92 0 |
| #define bHDRX_HDCP_WR_FIFO_byte92 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte92 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte93 0x059D |
| #define B16HDRX_HDCP_WR_FIFO_byte93 0x059C |
| #define LSb32HDRX_HDCP_WR_FIFO_byte93 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte93 8 |
| #define bHDRX_HDCP_WR_FIFO_byte93 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte93 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte94 0x059E |
| #define B16HDRX_HDCP_WR_FIFO_byte94 0x059E |
| #define LSb32HDRX_HDCP_WR_FIFO_byte94 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte94 0 |
| #define bHDRX_HDCP_WR_FIFO_byte94 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte94 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte95 0x059F |
| #define B16HDRX_HDCP_WR_FIFO_byte95 0x059E |
| #define LSb32HDRX_HDCP_WR_FIFO_byte95 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte95 8 |
| #define bHDRX_HDCP_WR_FIFO_byte95 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte95 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO24 0x05A0 |
| #define BA_HDRX_HDCP_WR_FIFO_byte96 0x05A0 |
| #define B16HDRX_HDCP_WR_FIFO_byte96 0x05A0 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte96 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte96 0 |
| #define bHDRX_HDCP_WR_FIFO_byte96 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte96 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte97 0x05A1 |
| #define B16HDRX_HDCP_WR_FIFO_byte97 0x05A0 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte97 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte97 8 |
| #define bHDRX_HDCP_WR_FIFO_byte97 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte97 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte98 0x05A2 |
| #define B16HDRX_HDCP_WR_FIFO_byte98 0x05A2 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte98 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte98 0 |
| #define bHDRX_HDCP_WR_FIFO_byte98 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte98 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte99 0x05A3 |
| #define B16HDRX_HDCP_WR_FIFO_byte99 0x05A2 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte99 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte99 8 |
| #define bHDRX_HDCP_WR_FIFO_byte99 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte99 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO25 0x05A4 |
| #define BA_HDRX_HDCP_WR_FIFO_byte100 0x05A4 |
| #define B16HDRX_HDCP_WR_FIFO_byte100 0x05A4 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte100 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte100 0 |
| #define bHDRX_HDCP_WR_FIFO_byte100 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte100 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte101 0x05A5 |
| #define B16HDRX_HDCP_WR_FIFO_byte101 0x05A4 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte101 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte101 8 |
| #define bHDRX_HDCP_WR_FIFO_byte101 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte101 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte102 0x05A6 |
| #define B16HDRX_HDCP_WR_FIFO_byte102 0x05A6 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte102 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte102 0 |
| #define bHDRX_HDCP_WR_FIFO_byte102 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte102 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte103 0x05A7 |
| #define B16HDRX_HDCP_WR_FIFO_byte103 0x05A6 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte103 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte103 8 |
| #define bHDRX_HDCP_WR_FIFO_byte103 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte103 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO26 0x05A8 |
| #define BA_HDRX_HDCP_WR_FIFO_byte104 0x05A8 |
| #define B16HDRX_HDCP_WR_FIFO_byte104 0x05A8 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte104 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte104 0 |
| #define bHDRX_HDCP_WR_FIFO_byte104 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte104 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte105 0x05A9 |
| #define B16HDRX_HDCP_WR_FIFO_byte105 0x05A8 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte105 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte105 8 |
| #define bHDRX_HDCP_WR_FIFO_byte105 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte105 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte106 0x05AA |
| #define B16HDRX_HDCP_WR_FIFO_byte106 0x05AA |
| #define LSb32HDRX_HDCP_WR_FIFO_byte106 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte106 0 |
| #define bHDRX_HDCP_WR_FIFO_byte106 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte106 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte107 0x05AB |
| #define B16HDRX_HDCP_WR_FIFO_byte107 0x05AA |
| #define LSb32HDRX_HDCP_WR_FIFO_byte107 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte107 8 |
| #define bHDRX_HDCP_WR_FIFO_byte107 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte107 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO27 0x05AC |
| #define BA_HDRX_HDCP_WR_FIFO_byte108 0x05AC |
| #define B16HDRX_HDCP_WR_FIFO_byte108 0x05AC |
| #define LSb32HDRX_HDCP_WR_FIFO_byte108 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte108 0 |
| #define bHDRX_HDCP_WR_FIFO_byte108 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte108 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte109 0x05AD |
| #define B16HDRX_HDCP_WR_FIFO_byte109 0x05AC |
| #define LSb32HDRX_HDCP_WR_FIFO_byte109 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte109 8 |
| #define bHDRX_HDCP_WR_FIFO_byte109 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte109 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte110 0x05AE |
| #define B16HDRX_HDCP_WR_FIFO_byte110 0x05AE |
| #define LSb32HDRX_HDCP_WR_FIFO_byte110 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte110 0 |
| #define bHDRX_HDCP_WR_FIFO_byte110 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte110 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte111 0x05AF |
| #define B16HDRX_HDCP_WR_FIFO_byte111 0x05AE |
| #define LSb32HDRX_HDCP_WR_FIFO_byte111 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte111 8 |
| #define bHDRX_HDCP_WR_FIFO_byte111 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte111 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO28 0x05B0 |
| #define BA_HDRX_HDCP_WR_FIFO_byte112 0x05B0 |
| #define B16HDRX_HDCP_WR_FIFO_byte112 0x05B0 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte112 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte112 0 |
| #define bHDRX_HDCP_WR_FIFO_byte112 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte112 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte113 0x05B1 |
| #define B16HDRX_HDCP_WR_FIFO_byte113 0x05B0 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte113 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte113 8 |
| #define bHDRX_HDCP_WR_FIFO_byte113 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte113 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte114 0x05B2 |
| #define B16HDRX_HDCP_WR_FIFO_byte114 0x05B2 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte114 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte114 0 |
| #define bHDRX_HDCP_WR_FIFO_byte114 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte114 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte115 0x05B3 |
| #define B16HDRX_HDCP_WR_FIFO_byte115 0x05B2 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte115 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte115 8 |
| #define bHDRX_HDCP_WR_FIFO_byte115 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte115 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO29 0x05B4 |
| #define BA_HDRX_HDCP_WR_FIFO_byte116 0x05B4 |
| #define B16HDRX_HDCP_WR_FIFO_byte116 0x05B4 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte116 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte116 0 |
| #define bHDRX_HDCP_WR_FIFO_byte116 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte116 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte117 0x05B5 |
| #define B16HDRX_HDCP_WR_FIFO_byte117 0x05B4 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte117 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte117 8 |
| #define bHDRX_HDCP_WR_FIFO_byte117 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte117 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte118 0x05B6 |
| #define B16HDRX_HDCP_WR_FIFO_byte118 0x05B6 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte118 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte118 0 |
| #define bHDRX_HDCP_WR_FIFO_byte118 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte118 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte119 0x05B7 |
| #define B16HDRX_HDCP_WR_FIFO_byte119 0x05B6 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte119 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte119 8 |
| #define bHDRX_HDCP_WR_FIFO_byte119 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte119 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO30 0x05B8 |
| #define BA_HDRX_HDCP_WR_FIFO_byte120 0x05B8 |
| #define B16HDRX_HDCP_WR_FIFO_byte120 0x05B8 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte120 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte120 0 |
| #define bHDRX_HDCP_WR_FIFO_byte120 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte120 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte121 0x05B9 |
| #define B16HDRX_HDCP_WR_FIFO_byte121 0x05B8 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte121 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte121 8 |
| #define bHDRX_HDCP_WR_FIFO_byte121 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte121 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte122 0x05BA |
| #define B16HDRX_HDCP_WR_FIFO_byte122 0x05BA |
| #define LSb32HDRX_HDCP_WR_FIFO_byte122 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte122 0 |
| #define bHDRX_HDCP_WR_FIFO_byte122 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte122 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte123 0x05BB |
| #define B16HDRX_HDCP_WR_FIFO_byte123 0x05BA |
| #define LSb32HDRX_HDCP_WR_FIFO_byte123 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte123 8 |
| #define bHDRX_HDCP_WR_FIFO_byte123 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte123 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO31 0x05BC |
| #define BA_HDRX_HDCP_WR_FIFO_byte124 0x05BC |
| #define B16HDRX_HDCP_WR_FIFO_byte124 0x05BC |
| #define LSb32HDRX_HDCP_WR_FIFO_byte124 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte124 0 |
| #define bHDRX_HDCP_WR_FIFO_byte124 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte124 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte125 0x05BD |
| #define B16HDRX_HDCP_WR_FIFO_byte125 0x05BC |
| #define LSb32HDRX_HDCP_WR_FIFO_byte125 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte125 8 |
| #define bHDRX_HDCP_WR_FIFO_byte125 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte125 0x0000FF00 |
| #define BA_HDRX_HDCP_WR_FIFO_byte126 0x05BE |
| #define B16HDRX_HDCP_WR_FIFO_byte126 0x05BE |
| #define LSb32HDRX_HDCP_WR_FIFO_byte126 16 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte126 0 |
| #define bHDRX_HDCP_WR_FIFO_byte126 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte126 0x00FF0000 |
| #define BA_HDRX_HDCP_WR_FIFO_byte127 0x05BF |
| #define B16HDRX_HDCP_WR_FIFO_byte127 0x05BE |
| #define LSb32HDRX_HDCP_WR_FIFO_byte127 24 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte127 8 |
| #define bHDRX_HDCP_WR_FIFO_byte127 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte127 0xFF000000 |
| #define RA_HDRX_HDCP_WR_FIFO32 0x05C0 |
| #define BA_HDRX_HDCP_WR_FIFO_byte128 0x05C0 |
| #define B16HDRX_HDCP_WR_FIFO_byte128 0x05C0 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte128 0 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte128 0 |
| #define bHDRX_HDCP_WR_FIFO_byte128 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte128 0x000000FF |
| #define BA_HDRX_HDCP_WR_FIFO_byte129 0x05C1 |
| #define B16HDRX_HDCP_WR_FIFO_byte129 0x05C0 |
| #define LSb32HDRX_HDCP_WR_FIFO_byte129 8 |
| #define LSb16HDRX_HDCP_WR_FIFO_byte129 8 |
| #define bHDRX_HDCP_WR_FIFO_byte129 8 |
| #define MSK32HDRX_HDCP_WR_FIFO_byte129 0x0000FF00 |
| #define RA_HDRX_HDCP_RD_FIFO 0x05C4 |
| #define BA_HDRX_HDCP_RD_FIFO_byte0 0x05C4 |
| #define B16HDRX_HDCP_RD_FIFO_byte0 0x05C4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte0 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte0 0 |
| #define bHDRX_HDCP_RD_FIFO_byte0 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte0 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte1 0x05C5 |
| #define B16HDRX_HDCP_RD_FIFO_byte1 0x05C4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte1 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte1 8 |
| #define bHDRX_HDCP_RD_FIFO_byte1 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte1 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte2 0x05C6 |
| #define B16HDRX_HDCP_RD_FIFO_byte2 0x05C6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte2 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte2 0 |
| #define bHDRX_HDCP_RD_FIFO_byte2 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte2 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte3 0x05C7 |
| #define B16HDRX_HDCP_RD_FIFO_byte3 0x05C6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte3 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte3 8 |
| #define bHDRX_HDCP_RD_FIFO_byte3 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte3 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO1 0x05C8 |
| #define BA_HDRX_HDCP_RD_FIFO_byte4 0x05C8 |
| #define B16HDRX_HDCP_RD_FIFO_byte4 0x05C8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte4 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte4 0 |
| #define bHDRX_HDCP_RD_FIFO_byte4 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte4 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte5 0x05C9 |
| #define B16HDRX_HDCP_RD_FIFO_byte5 0x05C8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte5 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte5 8 |
| #define bHDRX_HDCP_RD_FIFO_byte5 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte5 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte6 0x05CA |
| #define B16HDRX_HDCP_RD_FIFO_byte6 0x05CA |
| #define LSb32HDRX_HDCP_RD_FIFO_byte6 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte6 0 |
| #define bHDRX_HDCP_RD_FIFO_byte6 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte6 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte7 0x05CB |
| #define B16HDRX_HDCP_RD_FIFO_byte7 0x05CA |
| #define LSb32HDRX_HDCP_RD_FIFO_byte7 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte7 8 |
| #define bHDRX_HDCP_RD_FIFO_byte7 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte7 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO2 0x05CC |
| #define BA_HDRX_HDCP_RD_FIFO_byte8 0x05CC |
| #define B16HDRX_HDCP_RD_FIFO_byte8 0x05CC |
| #define LSb32HDRX_HDCP_RD_FIFO_byte8 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte8 0 |
| #define bHDRX_HDCP_RD_FIFO_byte8 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte8 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte9 0x05CD |
| #define B16HDRX_HDCP_RD_FIFO_byte9 0x05CC |
| #define LSb32HDRX_HDCP_RD_FIFO_byte9 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte9 8 |
| #define bHDRX_HDCP_RD_FIFO_byte9 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte9 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte10 0x05CE |
| #define B16HDRX_HDCP_RD_FIFO_byte10 0x05CE |
| #define LSb32HDRX_HDCP_RD_FIFO_byte10 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte10 0 |
| #define bHDRX_HDCP_RD_FIFO_byte10 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte10 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte11 0x05CF |
| #define B16HDRX_HDCP_RD_FIFO_byte11 0x05CE |
| #define LSb32HDRX_HDCP_RD_FIFO_byte11 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte11 8 |
| #define bHDRX_HDCP_RD_FIFO_byte11 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte11 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO3 0x05D0 |
| #define BA_HDRX_HDCP_RD_FIFO_byte12 0x05D0 |
| #define B16HDRX_HDCP_RD_FIFO_byte12 0x05D0 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte12 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte12 0 |
| #define bHDRX_HDCP_RD_FIFO_byte12 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte12 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte13 0x05D1 |
| #define B16HDRX_HDCP_RD_FIFO_byte13 0x05D0 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte13 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte13 8 |
| #define bHDRX_HDCP_RD_FIFO_byte13 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte13 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte14 0x05D2 |
| #define B16HDRX_HDCP_RD_FIFO_byte14 0x05D2 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte14 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte14 0 |
| #define bHDRX_HDCP_RD_FIFO_byte14 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte14 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte15 0x05D3 |
| #define B16HDRX_HDCP_RD_FIFO_byte15 0x05D2 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte15 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte15 8 |
| #define bHDRX_HDCP_RD_FIFO_byte15 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte15 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO4 0x05D4 |
| #define BA_HDRX_HDCP_RD_FIFO_byte16 0x05D4 |
| #define B16HDRX_HDCP_RD_FIFO_byte16 0x05D4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte16 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte16 0 |
| #define bHDRX_HDCP_RD_FIFO_byte16 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte16 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte17 0x05D5 |
| #define B16HDRX_HDCP_RD_FIFO_byte17 0x05D4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte17 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte17 8 |
| #define bHDRX_HDCP_RD_FIFO_byte17 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte17 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte18 0x05D6 |
| #define B16HDRX_HDCP_RD_FIFO_byte18 0x05D6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte18 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte18 0 |
| #define bHDRX_HDCP_RD_FIFO_byte18 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte18 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte19 0x05D7 |
| #define B16HDRX_HDCP_RD_FIFO_byte19 0x05D6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte19 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte19 8 |
| #define bHDRX_HDCP_RD_FIFO_byte19 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte19 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO5 0x05D8 |
| #define BA_HDRX_HDCP_RD_FIFO_byte20 0x05D8 |
| #define B16HDRX_HDCP_RD_FIFO_byte20 0x05D8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte20 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte20 0 |
| #define bHDRX_HDCP_RD_FIFO_byte20 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte20 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte21 0x05D9 |
| #define B16HDRX_HDCP_RD_FIFO_byte21 0x05D8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte21 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte21 8 |
| #define bHDRX_HDCP_RD_FIFO_byte21 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte21 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte22 0x05DA |
| #define B16HDRX_HDCP_RD_FIFO_byte22 0x05DA |
| #define LSb32HDRX_HDCP_RD_FIFO_byte22 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte22 0 |
| #define bHDRX_HDCP_RD_FIFO_byte22 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte22 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte23 0x05DB |
| #define B16HDRX_HDCP_RD_FIFO_byte23 0x05DA |
| #define LSb32HDRX_HDCP_RD_FIFO_byte23 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte23 8 |
| #define bHDRX_HDCP_RD_FIFO_byte23 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte23 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO6 0x05DC |
| #define BA_HDRX_HDCP_RD_FIFO_byte24 0x05DC |
| #define B16HDRX_HDCP_RD_FIFO_byte24 0x05DC |
| #define LSb32HDRX_HDCP_RD_FIFO_byte24 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte24 0 |
| #define bHDRX_HDCP_RD_FIFO_byte24 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte24 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte25 0x05DD |
| #define B16HDRX_HDCP_RD_FIFO_byte25 0x05DC |
| #define LSb32HDRX_HDCP_RD_FIFO_byte25 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte25 8 |
| #define bHDRX_HDCP_RD_FIFO_byte25 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte25 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte26 0x05DE |
| #define B16HDRX_HDCP_RD_FIFO_byte26 0x05DE |
| #define LSb32HDRX_HDCP_RD_FIFO_byte26 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte26 0 |
| #define bHDRX_HDCP_RD_FIFO_byte26 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte26 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte27 0x05DF |
| #define B16HDRX_HDCP_RD_FIFO_byte27 0x05DE |
| #define LSb32HDRX_HDCP_RD_FIFO_byte27 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte27 8 |
| #define bHDRX_HDCP_RD_FIFO_byte27 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte27 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO7 0x05E0 |
| #define BA_HDRX_HDCP_RD_FIFO_byte28 0x05E0 |
| #define B16HDRX_HDCP_RD_FIFO_byte28 0x05E0 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte28 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte28 0 |
| #define bHDRX_HDCP_RD_FIFO_byte28 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte28 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte29 0x05E1 |
| #define B16HDRX_HDCP_RD_FIFO_byte29 0x05E0 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte29 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte29 8 |
| #define bHDRX_HDCP_RD_FIFO_byte29 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte29 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte30 0x05E2 |
| #define B16HDRX_HDCP_RD_FIFO_byte30 0x05E2 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte30 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte30 0 |
| #define bHDRX_HDCP_RD_FIFO_byte30 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte30 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte31 0x05E3 |
| #define B16HDRX_HDCP_RD_FIFO_byte31 0x05E2 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte31 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte31 8 |
| #define bHDRX_HDCP_RD_FIFO_byte31 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte31 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO8 0x05E4 |
| #define BA_HDRX_HDCP_RD_FIFO_byte32 0x05E4 |
| #define B16HDRX_HDCP_RD_FIFO_byte32 0x05E4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte32 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte32 0 |
| #define bHDRX_HDCP_RD_FIFO_byte32 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte32 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte33 0x05E5 |
| #define B16HDRX_HDCP_RD_FIFO_byte33 0x05E4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte33 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte33 8 |
| #define bHDRX_HDCP_RD_FIFO_byte33 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte33 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte34 0x05E6 |
| #define B16HDRX_HDCP_RD_FIFO_byte34 0x05E6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte34 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte34 0 |
| #define bHDRX_HDCP_RD_FIFO_byte34 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte34 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte35 0x05E7 |
| #define B16HDRX_HDCP_RD_FIFO_byte35 0x05E6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte35 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte35 8 |
| #define bHDRX_HDCP_RD_FIFO_byte35 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte35 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO9 0x05E8 |
| #define BA_HDRX_HDCP_RD_FIFO_byte36 0x05E8 |
| #define B16HDRX_HDCP_RD_FIFO_byte36 0x05E8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte36 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte36 0 |
| #define bHDRX_HDCP_RD_FIFO_byte36 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte36 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte37 0x05E9 |
| #define B16HDRX_HDCP_RD_FIFO_byte37 0x05E8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte37 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte37 8 |
| #define bHDRX_HDCP_RD_FIFO_byte37 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte37 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte38 0x05EA |
| #define B16HDRX_HDCP_RD_FIFO_byte38 0x05EA |
| #define LSb32HDRX_HDCP_RD_FIFO_byte38 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte38 0 |
| #define bHDRX_HDCP_RD_FIFO_byte38 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte38 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte39 0x05EB |
| #define B16HDRX_HDCP_RD_FIFO_byte39 0x05EA |
| #define LSb32HDRX_HDCP_RD_FIFO_byte39 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte39 8 |
| #define bHDRX_HDCP_RD_FIFO_byte39 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte39 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO10 0x05EC |
| #define BA_HDRX_HDCP_RD_FIFO_byte40 0x05EC |
| #define B16HDRX_HDCP_RD_FIFO_byte40 0x05EC |
| #define LSb32HDRX_HDCP_RD_FIFO_byte40 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte40 0 |
| #define bHDRX_HDCP_RD_FIFO_byte40 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte40 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte41 0x05ED |
| #define B16HDRX_HDCP_RD_FIFO_byte41 0x05EC |
| #define LSb32HDRX_HDCP_RD_FIFO_byte41 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte41 8 |
| #define bHDRX_HDCP_RD_FIFO_byte41 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte41 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte42 0x05EE |
| #define B16HDRX_HDCP_RD_FIFO_byte42 0x05EE |
| #define LSb32HDRX_HDCP_RD_FIFO_byte42 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte42 0 |
| #define bHDRX_HDCP_RD_FIFO_byte42 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte42 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte43 0x05EF |
| #define B16HDRX_HDCP_RD_FIFO_byte43 0x05EE |
| #define LSb32HDRX_HDCP_RD_FIFO_byte43 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte43 8 |
| #define bHDRX_HDCP_RD_FIFO_byte43 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte43 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO11 0x05F0 |
| #define BA_HDRX_HDCP_RD_FIFO_byte44 0x05F0 |
| #define B16HDRX_HDCP_RD_FIFO_byte44 0x05F0 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte44 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte44 0 |
| #define bHDRX_HDCP_RD_FIFO_byte44 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte44 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte45 0x05F1 |
| #define B16HDRX_HDCP_RD_FIFO_byte45 0x05F0 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte45 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte45 8 |
| #define bHDRX_HDCP_RD_FIFO_byte45 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte45 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte46 0x05F2 |
| #define B16HDRX_HDCP_RD_FIFO_byte46 0x05F2 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte46 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte46 0 |
| #define bHDRX_HDCP_RD_FIFO_byte46 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte46 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte47 0x05F3 |
| #define B16HDRX_HDCP_RD_FIFO_byte47 0x05F2 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte47 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte47 8 |
| #define bHDRX_HDCP_RD_FIFO_byte47 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte47 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO12 0x05F4 |
| #define BA_HDRX_HDCP_RD_FIFO_byte48 0x05F4 |
| #define B16HDRX_HDCP_RD_FIFO_byte48 0x05F4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte48 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte48 0 |
| #define bHDRX_HDCP_RD_FIFO_byte48 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte48 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte49 0x05F5 |
| #define B16HDRX_HDCP_RD_FIFO_byte49 0x05F4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte49 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte49 8 |
| #define bHDRX_HDCP_RD_FIFO_byte49 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte49 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte50 0x05F6 |
| #define B16HDRX_HDCP_RD_FIFO_byte50 0x05F6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte50 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte50 0 |
| #define bHDRX_HDCP_RD_FIFO_byte50 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte50 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte51 0x05F7 |
| #define B16HDRX_HDCP_RD_FIFO_byte51 0x05F6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte51 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte51 8 |
| #define bHDRX_HDCP_RD_FIFO_byte51 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte51 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO13 0x05F8 |
| #define BA_HDRX_HDCP_RD_FIFO_byte52 0x05F8 |
| #define B16HDRX_HDCP_RD_FIFO_byte52 0x05F8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte52 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte52 0 |
| #define bHDRX_HDCP_RD_FIFO_byte52 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte52 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte53 0x05F9 |
| #define B16HDRX_HDCP_RD_FIFO_byte53 0x05F8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte53 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte53 8 |
| #define bHDRX_HDCP_RD_FIFO_byte53 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte53 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte54 0x05FA |
| #define B16HDRX_HDCP_RD_FIFO_byte54 0x05FA |
| #define LSb32HDRX_HDCP_RD_FIFO_byte54 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte54 0 |
| #define bHDRX_HDCP_RD_FIFO_byte54 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte54 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte55 0x05FB |
| #define B16HDRX_HDCP_RD_FIFO_byte55 0x05FA |
| #define LSb32HDRX_HDCP_RD_FIFO_byte55 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte55 8 |
| #define bHDRX_HDCP_RD_FIFO_byte55 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte55 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO14 0x05FC |
| #define BA_HDRX_HDCP_RD_FIFO_byte56 0x05FC |
| #define B16HDRX_HDCP_RD_FIFO_byte56 0x05FC |
| #define LSb32HDRX_HDCP_RD_FIFO_byte56 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte56 0 |
| #define bHDRX_HDCP_RD_FIFO_byte56 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte56 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte57 0x05FD |
| #define B16HDRX_HDCP_RD_FIFO_byte57 0x05FC |
| #define LSb32HDRX_HDCP_RD_FIFO_byte57 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte57 8 |
| #define bHDRX_HDCP_RD_FIFO_byte57 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte57 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte58 0x05FE |
| #define B16HDRX_HDCP_RD_FIFO_byte58 0x05FE |
| #define LSb32HDRX_HDCP_RD_FIFO_byte58 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte58 0 |
| #define bHDRX_HDCP_RD_FIFO_byte58 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte58 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte59 0x05FF |
| #define B16HDRX_HDCP_RD_FIFO_byte59 0x05FE |
| #define LSb32HDRX_HDCP_RD_FIFO_byte59 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte59 8 |
| #define bHDRX_HDCP_RD_FIFO_byte59 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte59 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO15 0x0600 |
| #define BA_HDRX_HDCP_RD_FIFO_byte60 0x0600 |
| #define B16HDRX_HDCP_RD_FIFO_byte60 0x0600 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte60 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte60 0 |
| #define bHDRX_HDCP_RD_FIFO_byte60 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte60 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte61 0x0601 |
| #define B16HDRX_HDCP_RD_FIFO_byte61 0x0600 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte61 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte61 8 |
| #define bHDRX_HDCP_RD_FIFO_byte61 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte61 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte62 0x0602 |
| #define B16HDRX_HDCP_RD_FIFO_byte62 0x0602 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte62 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte62 0 |
| #define bHDRX_HDCP_RD_FIFO_byte62 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte62 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte63 0x0603 |
| #define B16HDRX_HDCP_RD_FIFO_byte63 0x0602 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte63 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte63 8 |
| #define bHDRX_HDCP_RD_FIFO_byte63 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte63 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO16 0x0604 |
| #define BA_HDRX_HDCP_RD_FIFO_byte64 0x0604 |
| #define B16HDRX_HDCP_RD_FIFO_byte64 0x0604 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte64 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte64 0 |
| #define bHDRX_HDCP_RD_FIFO_byte64 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte64 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte65 0x0605 |
| #define B16HDRX_HDCP_RD_FIFO_byte65 0x0604 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte65 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte65 8 |
| #define bHDRX_HDCP_RD_FIFO_byte65 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte65 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte66 0x0606 |
| #define B16HDRX_HDCP_RD_FIFO_byte66 0x0606 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte66 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte66 0 |
| #define bHDRX_HDCP_RD_FIFO_byte66 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte66 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte67 0x0607 |
| #define B16HDRX_HDCP_RD_FIFO_byte67 0x0606 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte67 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte67 8 |
| #define bHDRX_HDCP_RD_FIFO_byte67 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte67 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO17 0x0608 |
| #define BA_HDRX_HDCP_RD_FIFO_byte68 0x0608 |
| #define B16HDRX_HDCP_RD_FIFO_byte68 0x0608 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte68 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte68 0 |
| #define bHDRX_HDCP_RD_FIFO_byte68 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte68 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte69 0x0609 |
| #define B16HDRX_HDCP_RD_FIFO_byte69 0x0608 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte69 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte69 8 |
| #define bHDRX_HDCP_RD_FIFO_byte69 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte69 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte70 0x060A |
| #define B16HDRX_HDCP_RD_FIFO_byte70 0x060A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte70 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte70 0 |
| #define bHDRX_HDCP_RD_FIFO_byte70 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte70 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte71 0x060B |
| #define B16HDRX_HDCP_RD_FIFO_byte71 0x060A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte71 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte71 8 |
| #define bHDRX_HDCP_RD_FIFO_byte71 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte71 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO18 0x060C |
| #define BA_HDRX_HDCP_RD_FIFO_byte72 0x060C |
| #define B16HDRX_HDCP_RD_FIFO_byte72 0x060C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte72 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte72 0 |
| #define bHDRX_HDCP_RD_FIFO_byte72 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte72 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte73 0x060D |
| #define B16HDRX_HDCP_RD_FIFO_byte73 0x060C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte73 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte73 8 |
| #define bHDRX_HDCP_RD_FIFO_byte73 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte73 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte74 0x060E |
| #define B16HDRX_HDCP_RD_FIFO_byte74 0x060E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte74 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte74 0 |
| #define bHDRX_HDCP_RD_FIFO_byte74 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte74 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte75 0x060F |
| #define B16HDRX_HDCP_RD_FIFO_byte75 0x060E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte75 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte75 8 |
| #define bHDRX_HDCP_RD_FIFO_byte75 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte75 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO19 0x0610 |
| #define BA_HDRX_HDCP_RD_FIFO_byte76 0x0610 |
| #define B16HDRX_HDCP_RD_FIFO_byte76 0x0610 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte76 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte76 0 |
| #define bHDRX_HDCP_RD_FIFO_byte76 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte76 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte77 0x0611 |
| #define B16HDRX_HDCP_RD_FIFO_byte77 0x0610 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte77 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte77 8 |
| #define bHDRX_HDCP_RD_FIFO_byte77 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte77 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte78 0x0612 |
| #define B16HDRX_HDCP_RD_FIFO_byte78 0x0612 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte78 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte78 0 |
| #define bHDRX_HDCP_RD_FIFO_byte78 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte78 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte79 0x0613 |
| #define B16HDRX_HDCP_RD_FIFO_byte79 0x0612 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte79 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte79 8 |
| #define bHDRX_HDCP_RD_FIFO_byte79 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte79 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO20 0x0614 |
| #define BA_HDRX_HDCP_RD_FIFO_byte80 0x0614 |
| #define B16HDRX_HDCP_RD_FIFO_byte80 0x0614 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte80 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte80 0 |
| #define bHDRX_HDCP_RD_FIFO_byte80 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte80 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte81 0x0615 |
| #define B16HDRX_HDCP_RD_FIFO_byte81 0x0614 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte81 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte81 8 |
| #define bHDRX_HDCP_RD_FIFO_byte81 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte81 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte82 0x0616 |
| #define B16HDRX_HDCP_RD_FIFO_byte82 0x0616 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte82 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte82 0 |
| #define bHDRX_HDCP_RD_FIFO_byte82 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte82 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte83 0x0617 |
| #define B16HDRX_HDCP_RD_FIFO_byte83 0x0616 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte83 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte83 8 |
| #define bHDRX_HDCP_RD_FIFO_byte83 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte83 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO21 0x0618 |
| #define BA_HDRX_HDCP_RD_FIFO_byte84 0x0618 |
| #define B16HDRX_HDCP_RD_FIFO_byte84 0x0618 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte84 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte84 0 |
| #define bHDRX_HDCP_RD_FIFO_byte84 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte84 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte85 0x0619 |
| #define B16HDRX_HDCP_RD_FIFO_byte85 0x0618 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte85 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte85 8 |
| #define bHDRX_HDCP_RD_FIFO_byte85 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte85 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte86 0x061A |
| #define B16HDRX_HDCP_RD_FIFO_byte86 0x061A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte86 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte86 0 |
| #define bHDRX_HDCP_RD_FIFO_byte86 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte86 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte87 0x061B |
| #define B16HDRX_HDCP_RD_FIFO_byte87 0x061A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte87 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte87 8 |
| #define bHDRX_HDCP_RD_FIFO_byte87 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte87 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO22 0x061C |
| #define BA_HDRX_HDCP_RD_FIFO_byte88 0x061C |
| #define B16HDRX_HDCP_RD_FIFO_byte88 0x061C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte88 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte88 0 |
| #define bHDRX_HDCP_RD_FIFO_byte88 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte88 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte89 0x061D |
| #define B16HDRX_HDCP_RD_FIFO_byte89 0x061C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte89 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte89 8 |
| #define bHDRX_HDCP_RD_FIFO_byte89 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte89 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte90 0x061E |
| #define B16HDRX_HDCP_RD_FIFO_byte90 0x061E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte90 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte90 0 |
| #define bHDRX_HDCP_RD_FIFO_byte90 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte90 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte91 0x061F |
| #define B16HDRX_HDCP_RD_FIFO_byte91 0x061E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte91 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte91 8 |
| #define bHDRX_HDCP_RD_FIFO_byte91 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte91 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO23 0x0620 |
| #define BA_HDRX_HDCP_RD_FIFO_byte92 0x0620 |
| #define B16HDRX_HDCP_RD_FIFO_byte92 0x0620 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte92 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte92 0 |
| #define bHDRX_HDCP_RD_FIFO_byte92 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte92 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte93 0x0621 |
| #define B16HDRX_HDCP_RD_FIFO_byte93 0x0620 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte93 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte93 8 |
| #define bHDRX_HDCP_RD_FIFO_byte93 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte93 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte94 0x0622 |
| #define B16HDRX_HDCP_RD_FIFO_byte94 0x0622 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte94 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte94 0 |
| #define bHDRX_HDCP_RD_FIFO_byte94 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte94 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte95 0x0623 |
| #define B16HDRX_HDCP_RD_FIFO_byte95 0x0622 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte95 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte95 8 |
| #define bHDRX_HDCP_RD_FIFO_byte95 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte95 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO24 0x0624 |
| #define BA_HDRX_HDCP_RD_FIFO_byte96 0x0624 |
| #define B16HDRX_HDCP_RD_FIFO_byte96 0x0624 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte96 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte96 0 |
| #define bHDRX_HDCP_RD_FIFO_byte96 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte96 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte97 0x0625 |
| #define B16HDRX_HDCP_RD_FIFO_byte97 0x0624 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte97 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte97 8 |
| #define bHDRX_HDCP_RD_FIFO_byte97 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte97 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte98 0x0626 |
| #define B16HDRX_HDCP_RD_FIFO_byte98 0x0626 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte98 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte98 0 |
| #define bHDRX_HDCP_RD_FIFO_byte98 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte98 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte99 0x0627 |
| #define B16HDRX_HDCP_RD_FIFO_byte99 0x0626 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte99 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte99 8 |
| #define bHDRX_HDCP_RD_FIFO_byte99 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte99 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO25 0x0628 |
| #define BA_HDRX_HDCP_RD_FIFO_byte100 0x0628 |
| #define B16HDRX_HDCP_RD_FIFO_byte100 0x0628 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte100 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte100 0 |
| #define bHDRX_HDCP_RD_FIFO_byte100 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte100 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte101 0x0629 |
| #define B16HDRX_HDCP_RD_FIFO_byte101 0x0628 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte101 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte101 8 |
| #define bHDRX_HDCP_RD_FIFO_byte101 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte101 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte102 0x062A |
| #define B16HDRX_HDCP_RD_FIFO_byte102 0x062A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte102 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte102 0 |
| #define bHDRX_HDCP_RD_FIFO_byte102 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte102 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte103 0x062B |
| #define B16HDRX_HDCP_RD_FIFO_byte103 0x062A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte103 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte103 8 |
| #define bHDRX_HDCP_RD_FIFO_byte103 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte103 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO26 0x062C |
| #define BA_HDRX_HDCP_RD_FIFO_byte104 0x062C |
| #define B16HDRX_HDCP_RD_FIFO_byte104 0x062C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte104 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte104 0 |
| #define bHDRX_HDCP_RD_FIFO_byte104 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte104 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte105 0x062D |
| #define B16HDRX_HDCP_RD_FIFO_byte105 0x062C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte105 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte105 8 |
| #define bHDRX_HDCP_RD_FIFO_byte105 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte105 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte106 0x062E |
| #define B16HDRX_HDCP_RD_FIFO_byte106 0x062E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte106 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte106 0 |
| #define bHDRX_HDCP_RD_FIFO_byte106 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte106 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte107 0x062F |
| #define B16HDRX_HDCP_RD_FIFO_byte107 0x062E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte107 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte107 8 |
| #define bHDRX_HDCP_RD_FIFO_byte107 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte107 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO27 0x0630 |
| #define BA_HDRX_HDCP_RD_FIFO_byte108 0x0630 |
| #define B16HDRX_HDCP_RD_FIFO_byte108 0x0630 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte108 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte108 0 |
| #define bHDRX_HDCP_RD_FIFO_byte108 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte108 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte109 0x0631 |
| #define B16HDRX_HDCP_RD_FIFO_byte109 0x0630 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte109 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte109 8 |
| #define bHDRX_HDCP_RD_FIFO_byte109 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte109 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte110 0x0632 |
| #define B16HDRX_HDCP_RD_FIFO_byte110 0x0632 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte110 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte110 0 |
| #define bHDRX_HDCP_RD_FIFO_byte110 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte110 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte111 0x0633 |
| #define B16HDRX_HDCP_RD_FIFO_byte111 0x0632 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte111 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte111 8 |
| #define bHDRX_HDCP_RD_FIFO_byte111 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte111 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO28 0x0634 |
| #define BA_HDRX_HDCP_RD_FIFO_byte112 0x0634 |
| #define B16HDRX_HDCP_RD_FIFO_byte112 0x0634 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte112 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte112 0 |
| #define bHDRX_HDCP_RD_FIFO_byte112 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte112 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte113 0x0635 |
| #define B16HDRX_HDCP_RD_FIFO_byte113 0x0634 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte113 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte113 8 |
| #define bHDRX_HDCP_RD_FIFO_byte113 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte113 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte114 0x0636 |
| #define B16HDRX_HDCP_RD_FIFO_byte114 0x0636 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte114 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte114 0 |
| #define bHDRX_HDCP_RD_FIFO_byte114 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte114 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte115 0x0637 |
| #define B16HDRX_HDCP_RD_FIFO_byte115 0x0636 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte115 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte115 8 |
| #define bHDRX_HDCP_RD_FIFO_byte115 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte115 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO29 0x0638 |
| #define BA_HDRX_HDCP_RD_FIFO_byte116 0x0638 |
| #define B16HDRX_HDCP_RD_FIFO_byte116 0x0638 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte116 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte116 0 |
| #define bHDRX_HDCP_RD_FIFO_byte116 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte116 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte117 0x0639 |
| #define B16HDRX_HDCP_RD_FIFO_byte117 0x0638 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte117 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte117 8 |
| #define bHDRX_HDCP_RD_FIFO_byte117 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte117 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte118 0x063A |
| #define B16HDRX_HDCP_RD_FIFO_byte118 0x063A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte118 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte118 0 |
| #define bHDRX_HDCP_RD_FIFO_byte118 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte118 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte119 0x063B |
| #define B16HDRX_HDCP_RD_FIFO_byte119 0x063A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte119 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte119 8 |
| #define bHDRX_HDCP_RD_FIFO_byte119 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte119 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO30 0x063C |
| #define BA_HDRX_HDCP_RD_FIFO_byte120 0x063C |
| #define B16HDRX_HDCP_RD_FIFO_byte120 0x063C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte120 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte120 0 |
| #define bHDRX_HDCP_RD_FIFO_byte120 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte120 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte121 0x063D |
| #define B16HDRX_HDCP_RD_FIFO_byte121 0x063C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte121 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte121 8 |
| #define bHDRX_HDCP_RD_FIFO_byte121 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte121 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte122 0x063E |
| #define B16HDRX_HDCP_RD_FIFO_byte122 0x063E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte122 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte122 0 |
| #define bHDRX_HDCP_RD_FIFO_byte122 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte122 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte123 0x063F |
| #define B16HDRX_HDCP_RD_FIFO_byte123 0x063E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte123 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte123 8 |
| #define bHDRX_HDCP_RD_FIFO_byte123 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte123 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO31 0x0640 |
| #define BA_HDRX_HDCP_RD_FIFO_byte124 0x0640 |
| #define B16HDRX_HDCP_RD_FIFO_byte124 0x0640 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte124 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte124 0 |
| #define bHDRX_HDCP_RD_FIFO_byte124 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte124 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte125 0x0641 |
| #define B16HDRX_HDCP_RD_FIFO_byte125 0x0640 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte125 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte125 8 |
| #define bHDRX_HDCP_RD_FIFO_byte125 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte125 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte126 0x0642 |
| #define B16HDRX_HDCP_RD_FIFO_byte126 0x0642 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte126 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte126 0 |
| #define bHDRX_HDCP_RD_FIFO_byte126 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte126 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte127 0x0643 |
| #define B16HDRX_HDCP_RD_FIFO_byte127 0x0642 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte127 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte127 8 |
| #define bHDRX_HDCP_RD_FIFO_byte127 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte127 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO32 0x0644 |
| #define BA_HDRX_HDCP_RD_FIFO_byte128 0x0644 |
| #define B16HDRX_HDCP_RD_FIFO_byte128 0x0644 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte128 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte128 0 |
| #define bHDRX_HDCP_RD_FIFO_byte128 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte128 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte129 0x0645 |
| #define B16HDRX_HDCP_RD_FIFO_byte129 0x0644 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte129 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte129 8 |
| #define bHDRX_HDCP_RD_FIFO_byte129 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte129 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte130 0x0646 |
| #define B16HDRX_HDCP_RD_FIFO_byte130 0x0646 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte130 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte130 0 |
| #define bHDRX_HDCP_RD_FIFO_byte130 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte130 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte131 0x0647 |
| #define B16HDRX_HDCP_RD_FIFO_byte131 0x0646 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte131 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte131 8 |
| #define bHDRX_HDCP_RD_FIFO_byte131 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte131 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO33 0x0648 |
| #define BA_HDRX_HDCP_RD_FIFO_byte132 0x0648 |
| #define B16HDRX_HDCP_RD_FIFO_byte132 0x0648 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte132 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte132 0 |
| #define bHDRX_HDCP_RD_FIFO_byte132 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte132 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte133 0x0649 |
| #define B16HDRX_HDCP_RD_FIFO_byte133 0x0648 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte133 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte133 8 |
| #define bHDRX_HDCP_RD_FIFO_byte133 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte133 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte134 0x064A |
| #define B16HDRX_HDCP_RD_FIFO_byte134 0x064A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte134 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte134 0 |
| #define bHDRX_HDCP_RD_FIFO_byte134 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte134 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte135 0x064B |
| #define B16HDRX_HDCP_RD_FIFO_byte135 0x064A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte135 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte135 8 |
| #define bHDRX_HDCP_RD_FIFO_byte135 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte135 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO34 0x064C |
| #define BA_HDRX_HDCP_RD_FIFO_byte136 0x064C |
| #define B16HDRX_HDCP_RD_FIFO_byte136 0x064C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte136 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte136 0 |
| #define bHDRX_HDCP_RD_FIFO_byte136 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte136 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte137 0x064D |
| #define B16HDRX_HDCP_RD_FIFO_byte137 0x064C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte137 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte137 8 |
| #define bHDRX_HDCP_RD_FIFO_byte137 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte137 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte138 0x064E |
| #define B16HDRX_HDCP_RD_FIFO_byte138 0x064E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte138 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte138 0 |
| #define bHDRX_HDCP_RD_FIFO_byte138 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte138 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte139 0x064F |
| #define B16HDRX_HDCP_RD_FIFO_byte139 0x064E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte139 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte139 8 |
| #define bHDRX_HDCP_RD_FIFO_byte139 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte139 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO35 0x0650 |
| #define BA_HDRX_HDCP_RD_FIFO_byte140 0x0650 |
| #define B16HDRX_HDCP_RD_FIFO_byte140 0x0650 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte140 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte140 0 |
| #define bHDRX_HDCP_RD_FIFO_byte140 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte140 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte141 0x0651 |
| #define B16HDRX_HDCP_RD_FIFO_byte141 0x0650 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte141 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte141 8 |
| #define bHDRX_HDCP_RD_FIFO_byte141 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte141 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte142 0x0652 |
| #define B16HDRX_HDCP_RD_FIFO_byte142 0x0652 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte142 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte142 0 |
| #define bHDRX_HDCP_RD_FIFO_byte142 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte142 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte143 0x0653 |
| #define B16HDRX_HDCP_RD_FIFO_byte143 0x0652 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte143 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte143 8 |
| #define bHDRX_HDCP_RD_FIFO_byte143 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte143 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO36 0x0654 |
| #define BA_HDRX_HDCP_RD_FIFO_byte144 0x0654 |
| #define B16HDRX_HDCP_RD_FIFO_byte144 0x0654 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte144 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte144 0 |
| #define bHDRX_HDCP_RD_FIFO_byte144 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte144 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte145 0x0655 |
| #define B16HDRX_HDCP_RD_FIFO_byte145 0x0654 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte145 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte145 8 |
| #define bHDRX_HDCP_RD_FIFO_byte145 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte145 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte146 0x0656 |
| #define B16HDRX_HDCP_RD_FIFO_byte146 0x0656 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte146 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte146 0 |
| #define bHDRX_HDCP_RD_FIFO_byte146 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte146 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte147 0x0657 |
| #define B16HDRX_HDCP_RD_FIFO_byte147 0x0656 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte147 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte147 8 |
| #define bHDRX_HDCP_RD_FIFO_byte147 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte147 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO37 0x0658 |
| #define BA_HDRX_HDCP_RD_FIFO_byte148 0x0658 |
| #define B16HDRX_HDCP_RD_FIFO_byte148 0x0658 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte148 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte148 0 |
| #define bHDRX_HDCP_RD_FIFO_byte148 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte148 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte149 0x0659 |
| #define B16HDRX_HDCP_RD_FIFO_byte149 0x0658 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte149 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte149 8 |
| #define bHDRX_HDCP_RD_FIFO_byte149 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte149 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte150 0x065A |
| #define B16HDRX_HDCP_RD_FIFO_byte150 0x065A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte150 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte150 0 |
| #define bHDRX_HDCP_RD_FIFO_byte150 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte150 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte151 0x065B |
| #define B16HDRX_HDCP_RD_FIFO_byte151 0x065A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte151 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte151 8 |
| #define bHDRX_HDCP_RD_FIFO_byte151 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte151 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO38 0x065C |
| #define BA_HDRX_HDCP_RD_FIFO_byte152 0x065C |
| #define B16HDRX_HDCP_RD_FIFO_byte152 0x065C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte152 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte152 0 |
| #define bHDRX_HDCP_RD_FIFO_byte152 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte152 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte153 0x065D |
| #define B16HDRX_HDCP_RD_FIFO_byte153 0x065C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte153 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte153 8 |
| #define bHDRX_HDCP_RD_FIFO_byte153 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte153 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte154 0x065E |
| #define B16HDRX_HDCP_RD_FIFO_byte154 0x065E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte154 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte154 0 |
| #define bHDRX_HDCP_RD_FIFO_byte154 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte154 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte155 0x065F |
| #define B16HDRX_HDCP_RD_FIFO_byte155 0x065E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte155 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte155 8 |
| #define bHDRX_HDCP_RD_FIFO_byte155 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte155 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO39 0x0660 |
| #define BA_HDRX_HDCP_RD_FIFO_byte156 0x0660 |
| #define B16HDRX_HDCP_RD_FIFO_byte156 0x0660 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte156 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte156 0 |
| #define bHDRX_HDCP_RD_FIFO_byte156 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte156 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte157 0x0661 |
| #define B16HDRX_HDCP_RD_FIFO_byte157 0x0660 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte157 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte157 8 |
| #define bHDRX_HDCP_RD_FIFO_byte157 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte157 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte158 0x0662 |
| #define B16HDRX_HDCP_RD_FIFO_byte158 0x0662 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte158 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte158 0 |
| #define bHDRX_HDCP_RD_FIFO_byte158 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte158 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte159 0x0663 |
| #define B16HDRX_HDCP_RD_FIFO_byte159 0x0662 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte159 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte159 8 |
| #define bHDRX_HDCP_RD_FIFO_byte159 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte159 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO40 0x0664 |
| #define BA_HDRX_HDCP_RD_FIFO_byte160 0x0664 |
| #define B16HDRX_HDCP_RD_FIFO_byte160 0x0664 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte160 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte160 0 |
| #define bHDRX_HDCP_RD_FIFO_byte160 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte160 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte161 0x0665 |
| #define B16HDRX_HDCP_RD_FIFO_byte161 0x0664 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte161 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte161 8 |
| #define bHDRX_HDCP_RD_FIFO_byte161 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte161 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte162 0x0666 |
| #define B16HDRX_HDCP_RD_FIFO_byte162 0x0666 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte162 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte162 0 |
| #define bHDRX_HDCP_RD_FIFO_byte162 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte162 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte163 0x0667 |
| #define B16HDRX_HDCP_RD_FIFO_byte163 0x0666 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte163 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte163 8 |
| #define bHDRX_HDCP_RD_FIFO_byte163 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte163 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO41 0x0668 |
| #define BA_HDRX_HDCP_RD_FIFO_byte164 0x0668 |
| #define B16HDRX_HDCP_RD_FIFO_byte164 0x0668 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte164 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte164 0 |
| #define bHDRX_HDCP_RD_FIFO_byte164 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte164 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte165 0x0669 |
| #define B16HDRX_HDCP_RD_FIFO_byte165 0x0668 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte165 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte165 8 |
| #define bHDRX_HDCP_RD_FIFO_byte165 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte165 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte166 0x066A |
| #define B16HDRX_HDCP_RD_FIFO_byte166 0x066A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte166 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte166 0 |
| #define bHDRX_HDCP_RD_FIFO_byte166 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte166 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte167 0x066B |
| #define B16HDRX_HDCP_RD_FIFO_byte167 0x066A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte167 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte167 8 |
| #define bHDRX_HDCP_RD_FIFO_byte167 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte167 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO42 0x066C |
| #define BA_HDRX_HDCP_RD_FIFO_byte168 0x066C |
| #define B16HDRX_HDCP_RD_FIFO_byte168 0x066C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte168 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte168 0 |
| #define bHDRX_HDCP_RD_FIFO_byte168 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte168 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte169 0x066D |
| #define B16HDRX_HDCP_RD_FIFO_byte169 0x066C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte169 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte169 8 |
| #define bHDRX_HDCP_RD_FIFO_byte169 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte169 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte170 0x066E |
| #define B16HDRX_HDCP_RD_FIFO_byte170 0x066E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte170 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte170 0 |
| #define bHDRX_HDCP_RD_FIFO_byte170 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte170 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte171 0x066F |
| #define B16HDRX_HDCP_RD_FIFO_byte171 0x066E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte171 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte171 8 |
| #define bHDRX_HDCP_RD_FIFO_byte171 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte171 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO43 0x0670 |
| #define BA_HDRX_HDCP_RD_FIFO_byte172 0x0670 |
| #define B16HDRX_HDCP_RD_FIFO_byte172 0x0670 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte172 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte172 0 |
| #define bHDRX_HDCP_RD_FIFO_byte172 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte172 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte173 0x0671 |
| #define B16HDRX_HDCP_RD_FIFO_byte173 0x0670 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte173 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte173 8 |
| #define bHDRX_HDCP_RD_FIFO_byte173 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte173 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte174 0x0672 |
| #define B16HDRX_HDCP_RD_FIFO_byte174 0x0672 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte174 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte174 0 |
| #define bHDRX_HDCP_RD_FIFO_byte174 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte174 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte175 0x0673 |
| #define B16HDRX_HDCP_RD_FIFO_byte175 0x0672 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte175 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte175 8 |
| #define bHDRX_HDCP_RD_FIFO_byte175 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte175 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO44 0x0674 |
| #define BA_HDRX_HDCP_RD_FIFO_byte176 0x0674 |
| #define B16HDRX_HDCP_RD_FIFO_byte176 0x0674 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte176 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte176 0 |
| #define bHDRX_HDCP_RD_FIFO_byte176 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte176 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte177 0x0675 |
| #define B16HDRX_HDCP_RD_FIFO_byte177 0x0674 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte177 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte177 8 |
| #define bHDRX_HDCP_RD_FIFO_byte177 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte177 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte178 0x0676 |
| #define B16HDRX_HDCP_RD_FIFO_byte178 0x0676 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte178 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte178 0 |
| #define bHDRX_HDCP_RD_FIFO_byte178 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte178 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte179 0x0677 |
| #define B16HDRX_HDCP_RD_FIFO_byte179 0x0676 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte179 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte179 8 |
| #define bHDRX_HDCP_RD_FIFO_byte179 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte179 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO45 0x0678 |
| #define BA_HDRX_HDCP_RD_FIFO_byte180 0x0678 |
| #define B16HDRX_HDCP_RD_FIFO_byte180 0x0678 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte180 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte180 0 |
| #define bHDRX_HDCP_RD_FIFO_byte180 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte180 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte181 0x0679 |
| #define B16HDRX_HDCP_RD_FIFO_byte181 0x0678 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte181 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte181 8 |
| #define bHDRX_HDCP_RD_FIFO_byte181 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte181 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte182 0x067A |
| #define B16HDRX_HDCP_RD_FIFO_byte182 0x067A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte182 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte182 0 |
| #define bHDRX_HDCP_RD_FIFO_byte182 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte182 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte183 0x067B |
| #define B16HDRX_HDCP_RD_FIFO_byte183 0x067A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte183 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte183 8 |
| #define bHDRX_HDCP_RD_FIFO_byte183 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte183 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO46 0x067C |
| #define BA_HDRX_HDCP_RD_FIFO_byte184 0x067C |
| #define B16HDRX_HDCP_RD_FIFO_byte184 0x067C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte184 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte184 0 |
| #define bHDRX_HDCP_RD_FIFO_byte184 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte184 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte185 0x067D |
| #define B16HDRX_HDCP_RD_FIFO_byte185 0x067C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte185 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte185 8 |
| #define bHDRX_HDCP_RD_FIFO_byte185 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte185 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte186 0x067E |
| #define B16HDRX_HDCP_RD_FIFO_byte186 0x067E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte186 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte186 0 |
| #define bHDRX_HDCP_RD_FIFO_byte186 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte186 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte187 0x067F |
| #define B16HDRX_HDCP_RD_FIFO_byte187 0x067E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte187 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte187 8 |
| #define bHDRX_HDCP_RD_FIFO_byte187 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte187 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO47 0x0680 |
| #define BA_HDRX_HDCP_RD_FIFO_byte188 0x0680 |
| #define B16HDRX_HDCP_RD_FIFO_byte188 0x0680 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte188 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte188 0 |
| #define bHDRX_HDCP_RD_FIFO_byte188 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte188 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte189 0x0681 |
| #define B16HDRX_HDCP_RD_FIFO_byte189 0x0680 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte189 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte189 8 |
| #define bHDRX_HDCP_RD_FIFO_byte189 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte189 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte190 0x0682 |
| #define B16HDRX_HDCP_RD_FIFO_byte190 0x0682 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte190 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte190 0 |
| #define bHDRX_HDCP_RD_FIFO_byte190 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte190 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte191 0x0683 |
| #define B16HDRX_HDCP_RD_FIFO_byte191 0x0682 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte191 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte191 8 |
| #define bHDRX_HDCP_RD_FIFO_byte191 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte191 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO48 0x0684 |
| #define BA_HDRX_HDCP_RD_FIFO_byte192 0x0684 |
| #define B16HDRX_HDCP_RD_FIFO_byte192 0x0684 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte192 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte192 0 |
| #define bHDRX_HDCP_RD_FIFO_byte192 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte192 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte193 0x0685 |
| #define B16HDRX_HDCP_RD_FIFO_byte193 0x0684 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte193 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte193 8 |
| #define bHDRX_HDCP_RD_FIFO_byte193 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte193 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte194 0x0686 |
| #define B16HDRX_HDCP_RD_FIFO_byte194 0x0686 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte194 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte194 0 |
| #define bHDRX_HDCP_RD_FIFO_byte194 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte194 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte195 0x0687 |
| #define B16HDRX_HDCP_RD_FIFO_byte195 0x0686 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte195 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte195 8 |
| #define bHDRX_HDCP_RD_FIFO_byte195 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte195 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO49 0x0688 |
| #define BA_HDRX_HDCP_RD_FIFO_byte196 0x0688 |
| #define B16HDRX_HDCP_RD_FIFO_byte196 0x0688 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte196 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte196 0 |
| #define bHDRX_HDCP_RD_FIFO_byte196 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte196 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte197 0x0689 |
| #define B16HDRX_HDCP_RD_FIFO_byte197 0x0688 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte197 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte197 8 |
| #define bHDRX_HDCP_RD_FIFO_byte197 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte197 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte198 0x068A |
| #define B16HDRX_HDCP_RD_FIFO_byte198 0x068A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte198 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte198 0 |
| #define bHDRX_HDCP_RD_FIFO_byte198 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte198 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte199 0x068B |
| #define B16HDRX_HDCP_RD_FIFO_byte199 0x068A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte199 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte199 8 |
| #define bHDRX_HDCP_RD_FIFO_byte199 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte199 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO50 0x068C |
| #define BA_HDRX_HDCP_RD_FIFO_byte200 0x068C |
| #define B16HDRX_HDCP_RD_FIFO_byte200 0x068C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte200 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte200 0 |
| #define bHDRX_HDCP_RD_FIFO_byte200 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte200 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte201 0x068D |
| #define B16HDRX_HDCP_RD_FIFO_byte201 0x068C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte201 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte201 8 |
| #define bHDRX_HDCP_RD_FIFO_byte201 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte201 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte202 0x068E |
| #define B16HDRX_HDCP_RD_FIFO_byte202 0x068E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte202 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte202 0 |
| #define bHDRX_HDCP_RD_FIFO_byte202 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte202 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte203 0x068F |
| #define B16HDRX_HDCP_RD_FIFO_byte203 0x068E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte203 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte203 8 |
| #define bHDRX_HDCP_RD_FIFO_byte203 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte203 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO51 0x0690 |
| #define BA_HDRX_HDCP_RD_FIFO_byte204 0x0690 |
| #define B16HDRX_HDCP_RD_FIFO_byte204 0x0690 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte204 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte204 0 |
| #define bHDRX_HDCP_RD_FIFO_byte204 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte204 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte205 0x0691 |
| #define B16HDRX_HDCP_RD_FIFO_byte205 0x0690 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte205 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte205 8 |
| #define bHDRX_HDCP_RD_FIFO_byte205 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte205 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte206 0x0692 |
| #define B16HDRX_HDCP_RD_FIFO_byte206 0x0692 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte206 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte206 0 |
| #define bHDRX_HDCP_RD_FIFO_byte206 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte206 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte207 0x0693 |
| #define B16HDRX_HDCP_RD_FIFO_byte207 0x0692 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte207 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte207 8 |
| #define bHDRX_HDCP_RD_FIFO_byte207 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte207 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO52 0x0694 |
| #define BA_HDRX_HDCP_RD_FIFO_byte208 0x0694 |
| #define B16HDRX_HDCP_RD_FIFO_byte208 0x0694 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte208 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte208 0 |
| #define bHDRX_HDCP_RD_FIFO_byte208 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte208 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte209 0x0695 |
| #define B16HDRX_HDCP_RD_FIFO_byte209 0x0694 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte209 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte209 8 |
| #define bHDRX_HDCP_RD_FIFO_byte209 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte209 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte210 0x0696 |
| #define B16HDRX_HDCP_RD_FIFO_byte210 0x0696 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte210 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte210 0 |
| #define bHDRX_HDCP_RD_FIFO_byte210 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte210 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte211 0x0697 |
| #define B16HDRX_HDCP_RD_FIFO_byte211 0x0696 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte211 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte211 8 |
| #define bHDRX_HDCP_RD_FIFO_byte211 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte211 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO53 0x0698 |
| #define BA_HDRX_HDCP_RD_FIFO_byte212 0x0698 |
| #define B16HDRX_HDCP_RD_FIFO_byte212 0x0698 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte212 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte212 0 |
| #define bHDRX_HDCP_RD_FIFO_byte212 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte212 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte213 0x0699 |
| #define B16HDRX_HDCP_RD_FIFO_byte213 0x0698 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte213 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte213 8 |
| #define bHDRX_HDCP_RD_FIFO_byte213 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte213 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte214 0x069A |
| #define B16HDRX_HDCP_RD_FIFO_byte214 0x069A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte214 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte214 0 |
| #define bHDRX_HDCP_RD_FIFO_byte214 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte214 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte215 0x069B |
| #define B16HDRX_HDCP_RD_FIFO_byte215 0x069A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte215 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte215 8 |
| #define bHDRX_HDCP_RD_FIFO_byte215 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte215 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO54 0x069C |
| #define BA_HDRX_HDCP_RD_FIFO_byte216 0x069C |
| #define B16HDRX_HDCP_RD_FIFO_byte216 0x069C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte216 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte216 0 |
| #define bHDRX_HDCP_RD_FIFO_byte216 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte216 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte217 0x069D |
| #define B16HDRX_HDCP_RD_FIFO_byte217 0x069C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte217 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte217 8 |
| #define bHDRX_HDCP_RD_FIFO_byte217 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte217 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte218 0x069E |
| #define B16HDRX_HDCP_RD_FIFO_byte218 0x069E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte218 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte218 0 |
| #define bHDRX_HDCP_RD_FIFO_byte218 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte218 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte219 0x069F |
| #define B16HDRX_HDCP_RD_FIFO_byte219 0x069E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte219 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte219 8 |
| #define bHDRX_HDCP_RD_FIFO_byte219 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte219 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO55 0x06A0 |
| #define BA_HDRX_HDCP_RD_FIFO_byte220 0x06A0 |
| #define B16HDRX_HDCP_RD_FIFO_byte220 0x06A0 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte220 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte220 0 |
| #define bHDRX_HDCP_RD_FIFO_byte220 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte220 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte221 0x06A1 |
| #define B16HDRX_HDCP_RD_FIFO_byte221 0x06A0 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte221 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte221 8 |
| #define bHDRX_HDCP_RD_FIFO_byte221 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte221 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte222 0x06A2 |
| #define B16HDRX_HDCP_RD_FIFO_byte222 0x06A2 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte222 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte222 0 |
| #define bHDRX_HDCP_RD_FIFO_byte222 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte222 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte223 0x06A3 |
| #define B16HDRX_HDCP_RD_FIFO_byte223 0x06A2 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte223 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte223 8 |
| #define bHDRX_HDCP_RD_FIFO_byte223 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte223 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO56 0x06A4 |
| #define BA_HDRX_HDCP_RD_FIFO_byte224 0x06A4 |
| #define B16HDRX_HDCP_RD_FIFO_byte224 0x06A4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte224 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte224 0 |
| #define bHDRX_HDCP_RD_FIFO_byte224 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte224 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte225 0x06A5 |
| #define B16HDRX_HDCP_RD_FIFO_byte225 0x06A4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte225 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte225 8 |
| #define bHDRX_HDCP_RD_FIFO_byte225 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte225 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte226 0x06A6 |
| #define B16HDRX_HDCP_RD_FIFO_byte226 0x06A6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte226 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte226 0 |
| #define bHDRX_HDCP_RD_FIFO_byte226 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte226 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte227 0x06A7 |
| #define B16HDRX_HDCP_RD_FIFO_byte227 0x06A6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte227 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte227 8 |
| #define bHDRX_HDCP_RD_FIFO_byte227 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte227 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO57 0x06A8 |
| #define BA_HDRX_HDCP_RD_FIFO_byte228 0x06A8 |
| #define B16HDRX_HDCP_RD_FIFO_byte228 0x06A8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte228 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte228 0 |
| #define bHDRX_HDCP_RD_FIFO_byte228 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte228 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte229 0x06A9 |
| #define B16HDRX_HDCP_RD_FIFO_byte229 0x06A8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte229 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte229 8 |
| #define bHDRX_HDCP_RD_FIFO_byte229 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte229 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte230 0x06AA |
| #define B16HDRX_HDCP_RD_FIFO_byte230 0x06AA |
| #define LSb32HDRX_HDCP_RD_FIFO_byte230 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte230 0 |
| #define bHDRX_HDCP_RD_FIFO_byte230 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte230 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte231 0x06AB |
| #define B16HDRX_HDCP_RD_FIFO_byte231 0x06AA |
| #define LSb32HDRX_HDCP_RD_FIFO_byte231 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte231 8 |
| #define bHDRX_HDCP_RD_FIFO_byte231 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte231 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO58 0x06AC |
| #define BA_HDRX_HDCP_RD_FIFO_byte232 0x06AC |
| #define B16HDRX_HDCP_RD_FIFO_byte232 0x06AC |
| #define LSb32HDRX_HDCP_RD_FIFO_byte232 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte232 0 |
| #define bHDRX_HDCP_RD_FIFO_byte232 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte232 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte233 0x06AD |
| #define B16HDRX_HDCP_RD_FIFO_byte233 0x06AC |
| #define LSb32HDRX_HDCP_RD_FIFO_byte233 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte233 8 |
| #define bHDRX_HDCP_RD_FIFO_byte233 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte233 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte234 0x06AE |
| #define B16HDRX_HDCP_RD_FIFO_byte234 0x06AE |
| #define LSb32HDRX_HDCP_RD_FIFO_byte234 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte234 0 |
| #define bHDRX_HDCP_RD_FIFO_byte234 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte234 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte235 0x06AF |
| #define B16HDRX_HDCP_RD_FIFO_byte235 0x06AE |
| #define LSb32HDRX_HDCP_RD_FIFO_byte235 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte235 8 |
| #define bHDRX_HDCP_RD_FIFO_byte235 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte235 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO59 0x06B0 |
| #define BA_HDRX_HDCP_RD_FIFO_byte236 0x06B0 |
| #define B16HDRX_HDCP_RD_FIFO_byte236 0x06B0 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte236 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte236 0 |
| #define bHDRX_HDCP_RD_FIFO_byte236 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte236 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte237 0x06B1 |
| #define B16HDRX_HDCP_RD_FIFO_byte237 0x06B0 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte237 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte237 8 |
| #define bHDRX_HDCP_RD_FIFO_byte237 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte237 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte238 0x06B2 |
| #define B16HDRX_HDCP_RD_FIFO_byte238 0x06B2 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte238 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte238 0 |
| #define bHDRX_HDCP_RD_FIFO_byte238 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte238 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte239 0x06B3 |
| #define B16HDRX_HDCP_RD_FIFO_byte239 0x06B2 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte239 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte239 8 |
| #define bHDRX_HDCP_RD_FIFO_byte239 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte239 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO60 0x06B4 |
| #define BA_HDRX_HDCP_RD_FIFO_byte240 0x06B4 |
| #define B16HDRX_HDCP_RD_FIFO_byte240 0x06B4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte240 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte240 0 |
| #define bHDRX_HDCP_RD_FIFO_byte240 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte240 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte241 0x06B5 |
| #define B16HDRX_HDCP_RD_FIFO_byte241 0x06B4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte241 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte241 8 |
| #define bHDRX_HDCP_RD_FIFO_byte241 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte241 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte242 0x06B6 |
| #define B16HDRX_HDCP_RD_FIFO_byte242 0x06B6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte242 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte242 0 |
| #define bHDRX_HDCP_RD_FIFO_byte242 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte242 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte243 0x06B7 |
| #define B16HDRX_HDCP_RD_FIFO_byte243 0x06B6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte243 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte243 8 |
| #define bHDRX_HDCP_RD_FIFO_byte243 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte243 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO61 0x06B8 |
| #define BA_HDRX_HDCP_RD_FIFO_byte244 0x06B8 |
| #define B16HDRX_HDCP_RD_FIFO_byte244 0x06B8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte244 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte244 0 |
| #define bHDRX_HDCP_RD_FIFO_byte244 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte244 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte245 0x06B9 |
| #define B16HDRX_HDCP_RD_FIFO_byte245 0x06B8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte245 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte245 8 |
| #define bHDRX_HDCP_RD_FIFO_byte245 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte245 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte246 0x06BA |
| #define B16HDRX_HDCP_RD_FIFO_byte246 0x06BA |
| #define LSb32HDRX_HDCP_RD_FIFO_byte246 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte246 0 |
| #define bHDRX_HDCP_RD_FIFO_byte246 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte246 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte247 0x06BB |
| #define B16HDRX_HDCP_RD_FIFO_byte247 0x06BA |
| #define LSb32HDRX_HDCP_RD_FIFO_byte247 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte247 8 |
| #define bHDRX_HDCP_RD_FIFO_byte247 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte247 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO62 0x06BC |
| #define BA_HDRX_HDCP_RD_FIFO_byte248 0x06BC |
| #define B16HDRX_HDCP_RD_FIFO_byte248 0x06BC |
| #define LSb32HDRX_HDCP_RD_FIFO_byte248 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte248 0 |
| #define bHDRX_HDCP_RD_FIFO_byte248 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte248 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte249 0x06BD |
| #define B16HDRX_HDCP_RD_FIFO_byte249 0x06BC |
| #define LSb32HDRX_HDCP_RD_FIFO_byte249 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte249 8 |
| #define bHDRX_HDCP_RD_FIFO_byte249 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte249 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte250 0x06BE |
| #define B16HDRX_HDCP_RD_FIFO_byte250 0x06BE |
| #define LSb32HDRX_HDCP_RD_FIFO_byte250 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte250 0 |
| #define bHDRX_HDCP_RD_FIFO_byte250 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte250 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte251 0x06BF |
| #define B16HDRX_HDCP_RD_FIFO_byte251 0x06BE |
| #define LSb32HDRX_HDCP_RD_FIFO_byte251 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte251 8 |
| #define bHDRX_HDCP_RD_FIFO_byte251 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte251 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO63 0x06C0 |
| #define BA_HDRX_HDCP_RD_FIFO_byte252 0x06C0 |
| #define B16HDRX_HDCP_RD_FIFO_byte252 0x06C0 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte252 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte252 0 |
| #define bHDRX_HDCP_RD_FIFO_byte252 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte252 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte253 0x06C1 |
| #define B16HDRX_HDCP_RD_FIFO_byte253 0x06C0 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte253 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte253 8 |
| #define bHDRX_HDCP_RD_FIFO_byte253 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte253 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte254 0x06C2 |
| #define B16HDRX_HDCP_RD_FIFO_byte254 0x06C2 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte254 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte254 0 |
| #define bHDRX_HDCP_RD_FIFO_byte254 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte254 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte255 0x06C3 |
| #define B16HDRX_HDCP_RD_FIFO_byte255 0x06C2 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte255 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte255 8 |
| #define bHDRX_HDCP_RD_FIFO_byte255 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte255 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO64 0x06C4 |
| #define BA_HDRX_HDCP_RD_FIFO_byte256 0x06C4 |
| #define B16HDRX_HDCP_RD_FIFO_byte256 0x06C4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte256 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte256 0 |
| #define bHDRX_HDCP_RD_FIFO_byte256 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte256 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte257 0x06C5 |
| #define B16HDRX_HDCP_RD_FIFO_byte257 0x06C4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte257 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte257 8 |
| #define bHDRX_HDCP_RD_FIFO_byte257 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte257 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte258 0x06C6 |
| #define B16HDRX_HDCP_RD_FIFO_byte258 0x06C6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte258 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte258 0 |
| #define bHDRX_HDCP_RD_FIFO_byte258 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte258 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte259 0x06C7 |
| #define B16HDRX_HDCP_RD_FIFO_byte259 0x06C6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte259 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte259 8 |
| #define bHDRX_HDCP_RD_FIFO_byte259 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte259 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO65 0x06C8 |
| #define BA_HDRX_HDCP_RD_FIFO_byte260 0x06C8 |
| #define B16HDRX_HDCP_RD_FIFO_byte260 0x06C8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte260 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte260 0 |
| #define bHDRX_HDCP_RD_FIFO_byte260 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte260 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte261 0x06C9 |
| #define B16HDRX_HDCP_RD_FIFO_byte261 0x06C8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte261 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte261 8 |
| #define bHDRX_HDCP_RD_FIFO_byte261 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte261 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte262 0x06CA |
| #define B16HDRX_HDCP_RD_FIFO_byte262 0x06CA |
| #define LSb32HDRX_HDCP_RD_FIFO_byte262 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte262 0 |
| #define bHDRX_HDCP_RD_FIFO_byte262 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte262 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte263 0x06CB |
| #define B16HDRX_HDCP_RD_FIFO_byte263 0x06CA |
| #define LSb32HDRX_HDCP_RD_FIFO_byte263 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte263 8 |
| #define bHDRX_HDCP_RD_FIFO_byte263 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte263 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO66 0x06CC |
| #define BA_HDRX_HDCP_RD_FIFO_byte264 0x06CC |
| #define B16HDRX_HDCP_RD_FIFO_byte264 0x06CC |
| #define LSb32HDRX_HDCP_RD_FIFO_byte264 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte264 0 |
| #define bHDRX_HDCP_RD_FIFO_byte264 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte264 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte265 0x06CD |
| #define B16HDRX_HDCP_RD_FIFO_byte265 0x06CC |
| #define LSb32HDRX_HDCP_RD_FIFO_byte265 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte265 8 |
| #define bHDRX_HDCP_RD_FIFO_byte265 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte265 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte266 0x06CE |
| #define B16HDRX_HDCP_RD_FIFO_byte266 0x06CE |
| #define LSb32HDRX_HDCP_RD_FIFO_byte266 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte266 0 |
| #define bHDRX_HDCP_RD_FIFO_byte266 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte266 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte267 0x06CF |
| #define B16HDRX_HDCP_RD_FIFO_byte267 0x06CE |
| #define LSb32HDRX_HDCP_RD_FIFO_byte267 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte267 8 |
| #define bHDRX_HDCP_RD_FIFO_byte267 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte267 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO67 0x06D0 |
| #define BA_HDRX_HDCP_RD_FIFO_byte268 0x06D0 |
| #define B16HDRX_HDCP_RD_FIFO_byte268 0x06D0 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte268 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte268 0 |
| #define bHDRX_HDCP_RD_FIFO_byte268 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte268 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte269 0x06D1 |
| #define B16HDRX_HDCP_RD_FIFO_byte269 0x06D0 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte269 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte269 8 |
| #define bHDRX_HDCP_RD_FIFO_byte269 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte269 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte270 0x06D2 |
| #define B16HDRX_HDCP_RD_FIFO_byte270 0x06D2 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte270 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte270 0 |
| #define bHDRX_HDCP_RD_FIFO_byte270 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte270 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte271 0x06D3 |
| #define B16HDRX_HDCP_RD_FIFO_byte271 0x06D2 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte271 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte271 8 |
| #define bHDRX_HDCP_RD_FIFO_byte271 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte271 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO68 0x06D4 |
| #define BA_HDRX_HDCP_RD_FIFO_byte272 0x06D4 |
| #define B16HDRX_HDCP_RD_FIFO_byte272 0x06D4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte272 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte272 0 |
| #define bHDRX_HDCP_RD_FIFO_byte272 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte272 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte273 0x06D5 |
| #define B16HDRX_HDCP_RD_FIFO_byte273 0x06D4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte273 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte273 8 |
| #define bHDRX_HDCP_RD_FIFO_byte273 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte273 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte274 0x06D6 |
| #define B16HDRX_HDCP_RD_FIFO_byte274 0x06D6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte274 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte274 0 |
| #define bHDRX_HDCP_RD_FIFO_byte274 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte274 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte275 0x06D7 |
| #define B16HDRX_HDCP_RD_FIFO_byte275 0x06D6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte275 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte275 8 |
| #define bHDRX_HDCP_RD_FIFO_byte275 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte275 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO69 0x06D8 |
| #define BA_HDRX_HDCP_RD_FIFO_byte276 0x06D8 |
| #define B16HDRX_HDCP_RD_FIFO_byte276 0x06D8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte276 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte276 0 |
| #define bHDRX_HDCP_RD_FIFO_byte276 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte276 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte277 0x06D9 |
| #define B16HDRX_HDCP_RD_FIFO_byte277 0x06D8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte277 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte277 8 |
| #define bHDRX_HDCP_RD_FIFO_byte277 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte277 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte278 0x06DA |
| #define B16HDRX_HDCP_RD_FIFO_byte278 0x06DA |
| #define LSb32HDRX_HDCP_RD_FIFO_byte278 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte278 0 |
| #define bHDRX_HDCP_RD_FIFO_byte278 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte278 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte279 0x06DB |
| #define B16HDRX_HDCP_RD_FIFO_byte279 0x06DA |
| #define LSb32HDRX_HDCP_RD_FIFO_byte279 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte279 8 |
| #define bHDRX_HDCP_RD_FIFO_byte279 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte279 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO70 0x06DC |
| #define BA_HDRX_HDCP_RD_FIFO_byte280 0x06DC |
| #define B16HDRX_HDCP_RD_FIFO_byte280 0x06DC |
| #define LSb32HDRX_HDCP_RD_FIFO_byte280 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte280 0 |
| #define bHDRX_HDCP_RD_FIFO_byte280 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte280 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte281 0x06DD |
| #define B16HDRX_HDCP_RD_FIFO_byte281 0x06DC |
| #define LSb32HDRX_HDCP_RD_FIFO_byte281 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte281 8 |
| #define bHDRX_HDCP_RD_FIFO_byte281 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte281 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte282 0x06DE |
| #define B16HDRX_HDCP_RD_FIFO_byte282 0x06DE |
| #define LSb32HDRX_HDCP_RD_FIFO_byte282 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte282 0 |
| #define bHDRX_HDCP_RD_FIFO_byte282 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte282 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte283 0x06DF |
| #define B16HDRX_HDCP_RD_FIFO_byte283 0x06DE |
| #define LSb32HDRX_HDCP_RD_FIFO_byte283 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte283 8 |
| #define bHDRX_HDCP_RD_FIFO_byte283 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte283 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO71 0x06E0 |
| #define BA_HDRX_HDCP_RD_FIFO_byte284 0x06E0 |
| #define B16HDRX_HDCP_RD_FIFO_byte284 0x06E0 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte284 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte284 0 |
| #define bHDRX_HDCP_RD_FIFO_byte284 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte284 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte285 0x06E1 |
| #define B16HDRX_HDCP_RD_FIFO_byte285 0x06E0 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte285 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte285 8 |
| #define bHDRX_HDCP_RD_FIFO_byte285 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte285 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte286 0x06E2 |
| #define B16HDRX_HDCP_RD_FIFO_byte286 0x06E2 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte286 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte286 0 |
| #define bHDRX_HDCP_RD_FIFO_byte286 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte286 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte287 0x06E3 |
| #define B16HDRX_HDCP_RD_FIFO_byte287 0x06E2 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte287 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte287 8 |
| #define bHDRX_HDCP_RD_FIFO_byte287 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte287 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO72 0x06E4 |
| #define BA_HDRX_HDCP_RD_FIFO_byte288 0x06E4 |
| #define B16HDRX_HDCP_RD_FIFO_byte288 0x06E4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte288 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte288 0 |
| #define bHDRX_HDCP_RD_FIFO_byte288 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte288 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte289 0x06E5 |
| #define B16HDRX_HDCP_RD_FIFO_byte289 0x06E4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte289 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte289 8 |
| #define bHDRX_HDCP_RD_FIFO_byte289 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte289 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte290 0x06E6 |
| #define B16HDRX_HDCP_RD_FIFO_byte290 0x06E6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte290 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte290 0 |
| #define bHDRX_HDCP_RD_FIFO_byte290 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte290 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte291 0x06E7 |
| #define B16HDRX_HDCP_RD_FIFO_byte291 0x06E6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte291 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte291 8 |
| #define bHDRX_HDCP_RD_FIFO_byte291 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte291 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO73 0x06E8 |
| #define BA_HDRX_HDCP_RD_FIFO_byte292 0x06E8 |
| #define B16HDRX_HDCP_RD_FIFO_byte292 0x06E8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte292 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte292 0 |
| #define bHDRX_HDCP_RD_FIFO_byte292 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte292 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte293 0x06E9 |
| #define B16HDRX_HDCP_RD_FIFO_byte293 0x06E8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte293 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte293 8 |
| #define bHDRX_HDCP_RD_FIFO_byte293 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte293 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte294 0x06EA |
| #define B16HDRX_HDCP_RD_FIFO_byte294 0x06EA |
| #define LSb32HDRX_HDCP_RD_FIFO_byte294 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte294 0 |
| #define bHDRX_HDCP_RD_FIFO_byte294 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte294 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte295 0x06EB |
| #define B16HDRX_HDCP_RD_FIFO_byte295 0x06EA |
| #define LSb32HDRX_HDCP_RD_FIFO_byte295 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte295 8 |
| #define bHDRX_HDCP_RD_FIFO_byte295 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte295 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO74 0x06EC |
| #define BA_HDRX_HDCP_RD_FIFO_byte296 0x06EC |
| #define B16HDRX_HDCP_RD_FIFO_byte296 0x06EC |
| #define LSb32HDRX_HDCP_RD_FIFO_byte296 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte296 0 |
| #define bHDRX_HDCP_RD_FIFO_byte296 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte296 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte297 0x06ED |
| #define B16HDRX_HDCP_RD_FIFO_byte297 0x06EC |
| #define LSb32HDRX_HDCP_RD_FIFO_byte297 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte297 8 |
| #define bHDRX_HDCP_RD_FIFO_byte297 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte297 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte298 0x06EE |
| #define B16HDRX_HDCP_RD_FIFO_byte298 0x06EE |
| #define LSb32HDRX_HDCP_RD_FIFO_byte298 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte298 0 |
| #define bHDRX_HDCP_RD_FIFO_byte298 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte298 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte299 0x06EF |
| #define B16HDRX_HDCP_RD_FIFO_byte299 0x06EE |
| #define LSb32HDRX_HDCP_RD_FIFO_byte299 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte299 8 |
| #define bHDRX_HDCP_RD_FIFO_byte299 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte299 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO75 0x06F0 |
| #define BA_HDRX_HDCP_RD_FIFO_byte300 0x06F0 |
| #define B16HDRX_HDCP_RD_FIFO_byte300 0x06F0 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte300 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte300 0 |
| #define bHDRX_HDCP_RD_FIFO_byte300 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte300 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte301 0x06F1 |
| #define B16HDRX_HDCP_RD_FIFO_byte301 0x06F0 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte301 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte301 8 |
| #define bHDRX_HDCP_RD_FIFO_byte301 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte301 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte302 0x06F2 |
| #define B16HDRX_HDCP_RD_FIFO_byte302 0x06F2 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte302 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte302 0 |
| #define bHDRX_HDCP_RD_FIFO_byte302 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte302 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte303 0x06F3 |
| #define B16HDRX_HDCP_RD_FIFO_byte303 0x06F2 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte303 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte303 8 |
| #define bHDRX_HDCP_RD_FIFO_byte303 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte303 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO76 0x06F4 |
| #define BA_HDRX_HDCP_RD_FIFO_byte304 0x06F4 |
| #define B16HDRX_HDCP_RD_FIFO_byte304 0x06F4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte304 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte304 0 |
| #define bHDRX_HDCP_RD_FIFO_byte304 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte304 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte305 0x06F5 |
| #define B16HDRX_HDCP_RD_FIFO_byte305 0x06F4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte305 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte305 8 |
| #define bHDRX_HDCP_RD_FIFO_byte305 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte305 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte306 0x06F6 |
| #define B16HDRX_HDCP_RD_FIFO_byte306 0x06F6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte306 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte306 0 |
| #define bHDRX_HDCP_RD_FIFO_byte306 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte306 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte307 0x06F7 |
| #define B16HDRX_HDCP_RD_FIFO_byte307 0x06F6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte307 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte307 8 |
| #define bHDRX_HDCP_RD_FIFO_byte307 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte307 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO77 0x06F8 |
| #define BA_HDRX_HDCP_RD_FIFO_byte308 0x06F8 |
| #define B16HDRX_HDCP_RD_FIFO_byte308 0x06F8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte308 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte308 0 |
| #define bHDRX_HDCP_RD_FIFO_byte308 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte308 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte309 0x06F9 |
| #define B16HDRX_HDCP_RD_FIFO_byte309 0x06F8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte309 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte309 8 |
| #define bHDRX_HDCP_RD_FIFO_byte309 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte309 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte310 0x06FA |
| #define B16HDRX_HDCP_RD_FIFO_byte310 0x06FA |
| #define LSb32HDRX_HDCP_RD_FIFO_byte310 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte310 0 |
| #define bHDRX_HDCP_RD_FIFO_byte310 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte310 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte311 0x06FB |
| #define B16HDRX_HDCP_RD_FIFO_byte311 0x06FA |
| #define LSb32HDRX_HDCP_RD_FIFO_byte311 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte311 8 |
| #define bHDRX_HDCP_RD_FIFO_byte311 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte311 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO78 0x06FC |
| #define BA_HDRX_HDCP_RD_FIFO_byte312 0x06FC |
| #define B16HDRX_HDCP_RD_FIFO_byte312 0x06FC |
| #define LSb32HDRX_HDCP_RD_FIFO_byte312 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte312 0 |
| #define bHDRX_HDCP_RD_FIFO_byte312 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte312 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte313 0x06FD |
| #define B16HDRX_HDCP_RD_FIFO_byte313 0x06FC |
| #define LSb32HDRX_HDCP_RD_FIFO_byte313 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte313 8 |
| #define bHDRX_HDCP_RD_FIFO_byte313 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte313 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte314 0x06FE |
| #define B16HDRX_HDCP_RD_FIFO_byte314 0x06FE |
| #define LSb32HDRX_HDCP_RD_FIFO_byte314 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte314 0 |
| #define bHDRX_HDCP_RD_FIFO_byte314 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte314 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte315 0x06FF |
| #define B16HDRX_HDCP_RD_FIFO_byte315 0x06FE |
| #define LSb32HDRX_HDCP_RD_FIFO_byte315 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte315 8 |
| #define bHDRX_HDCP_RD_FIFO_byte315 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte315 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO79 0x0700 |
| #define BA_HDRX_HDCP_RD_FIFO_byte316 0x0700 |
| #define B16HDRX_HDCP_RD_FIFO_byte316 0x0700 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte316 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte316 0 |
| #define bHDRX_HDCP_RD_FIFO_byte316 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte316 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte317 0x0701 |
| #define B16HDRX_HDCP_RD_FIFO_byte317 0x0700 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte317 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte317 8 |
| #define bHDRX_HDCP_RD_FIFO_byte317 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte317 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte318 0x0702 |
| #define B16HDRX_HDCP_RD_FIFO_byte318 0x0702 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte318 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte318 0 |
| #define bHDRX_HDCP_RD_FIFO_byte318 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte318 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte319 0x0703 |
| #define B16HDRX_HDCP_RD_FIFO_byte319 0x0702 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte319 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte319 8 |
| #define bHDRX_HDCP_RD_FIFO_byte319 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte319 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO80 0x0704 |
| #define BA_HDRX_HDCP_RD_FIFO_byte320 0x0704 |
| #define B16HDRX_HDCP_RD_FIFO_byte320 0x0704 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte320 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte320 0 |
| #define bHDRX_HDCP_RD_FIFO_byte320 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte320 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte321 0x0705 |
| #define B16HDRX_HDCP_RD_FIFO_byte321 0x0704 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte321 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte321 8 |
| #define bHDRX_HDCP_RD_FIFO_byte321 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte321 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte322 0x0706 |
| #define B16HDRX_HDCP_RD_FIFO_byte322 0x0706 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte322 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte322 0 |
| #define bHDRX_HDCP_RD_FIFO_byte322 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte322 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte323 0x0707 |
| #define B16HDRX_HDCP_RD_FIFO_byte323 0x0706 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte323 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte323 8 |
| #define bHDRX_HDCP_RD_FIFO_byte323 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte323 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO81 0x0708 |
| #define BA_HDRX_HDCP_RD_FIFO_byte324 0x0708 |
| #define B16HDRX_HDCP_RD_FIFO_byte324 0x0708 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte324 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte324 0 |
| #define bHDRX_HDCP_RD_FIFO_byte324 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte324 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte325 0x0709 |
| #define B16HDRX_HDCP_RD_FIFO_byte325 0x0708 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte325 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte325 8 |
| #define bHDRX_HDCP_RD_FIFO_byte325 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte325 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte326 0x070A |
| #define B16HDRX_HDCP_RD_FIFO_byte326 0x070A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte326 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte326 0 |
| #define bHDRX_HDCP_RD_FIFO_byte326 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte326 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte327 0x070B |
| #define B16HDRX_HDCP_RD_FIFO_byte327 0x070A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte327 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte327 8 |
| #define bHDRX_HDCP_RD_FIFO_byte327 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte327 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO82 0x070C |
| #define BA_HDRX_HDCP_RD_FIFO_byte328 0x070C |
| #define B16HDRX_HDCP_RD_FIFO_byte328 0x070C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte328 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte328 0 |
| #define bHDRX_HDCP_RD_FIFO_byte328 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte328 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte329 0x070D |
| #define B16HDRX_HDCP_RD_FIFO_byte329 0x070C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte329 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte329 8 |
| #define bHDRX_HDCP_RD_FIFO_byte329 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte329 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte330 0x070E |
| #define B16HDRX_HDCP_RD_FIFO_byte330 0x070E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte330 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte330 0 |
| #define bHDRX_HDCP_RD_FIFO_byte330 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte330 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte331 0x070F |
| #define B16HDRX_HDCP_RD_FIFO_byte331 0x070E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte331 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte331 8 |
| #define bHDRX_HDCP_RD_FIFO_byte331 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte331 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO83 0x0710 |
| #define BA_HDRX_HDCP_RD_FIFO_byte332 0x0710 |
| #define B16HDRX_HDCP_RD_FIFO_byte332 0x0710 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte332 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte332 0 |
| #define bHDRX_HDCP_RD_FIFO_byte332 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte332 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte333 0x0711 |
| #define B16HDRX_HDCP_RD_FIFO_byte333 0x0710 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte333 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte333 8 |
| #define bHDRX_HDCP_RD_FIFO_byte333 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte333 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte334 0x0712 |
| #define B16HDRX_HDCP_RD_FIFO_byte334 0x0712 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte334 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte334 0 |
| #define bHDRX_HDCP_RD_FIFO_byte334 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte334 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte335 0x0713 |
| #define B16HDRX_HDCP_RD_FIFO_byte335 0x0712 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte335 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte335 8 |
| #define bHDRX_HDCP_RD_FIFO_byte335 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte335 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO84 0x0714 |
| #define BA_HDRX_HDCP_RD_FIFO_byte336 0x0714 |
| #define B16HDRX_HDCP_RD_FIFO_byte336 0x0714 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte336 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte336 0 |
| #define bHDRX_HDCP_RD_FIFO_byte336 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte336 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte337 0x0715 |
| #define B16HDRX_HDCP_RD_FIFO_byte337 0x0714 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte337 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte337 8 |
| #define bHDRX_HDCP_RD_FIFO_byte337 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte337 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte338 0x0716 |
| #define B16HDRX_HDCP_RD_FIFO_byte338 0x0716 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte338 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte338 0 |
| #define bHDRX_HDCP_RD_FIFO_byte338 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte338 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte339 0x0717 |
| #define B16HDRX_HDCP_RD_FIFO_byte339 0x0716 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte339 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte339 8 |
| #define bHDRX_HDCP_RD_FIFO_byte339 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte339 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO85 0x0718 |
| #define BA_HDRX_HDCP_RD_FIFO_byte340 0x0718 |
| #define B16HDRX_HDCP_RD_FIFO_byte340 0x0718 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte340 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte340 0 |
| #define bHDRX_HDCP_RD_FIFO_byte340 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte340 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte341 0x0719 |
| #define B16HDRX_HDCP_RD_FIFO_byte341 0x0718 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte341 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte341 8 |
| #define bHDRX_HDCP_RD_FIFO_byte341 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte341 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte342 0x071A |
| #define B16HDRX_HDCP_RD_FIFO_byte342 0x071A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte342 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte342 0 |
| #define bHDRX_HDCP_RD_FIFO_byte342 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte342 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte343 0x071B |
| #define B16HDRX_HDCP_RD_FIFO_byte343 0x071A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte343 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte343 8 |
| #define bHDRX_HDCP_RD_FIFO_byte343 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte343 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO86 0x071C |
| #define BA_HDRX_HDCP_RD_FIFO_byte344 0x071C |
| #define B16HDRX_HDCP_RD_FIFO_byte344 0x071C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte344 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte344 0 |
| #define bHDRX_HDCP_RD_FIFO_byte344 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte344 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte345 0x071D |
| #define B16HDRX_HDCP_RD_FIFO_byte345 0x071C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte345 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte345 8 |
| #define bHDRX_HDCP_RD_FIFO_byte345 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte345 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte346 0x071E |
| #define B16HDRX_HDCP_RD_FIFO_byte346 0x071E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte346 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte346 0 |
| #define bHDRX_HDCP_RD_FIFO_byte346 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte346 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte347 0x071F |
| #define B16HDRX_HDCP_RD_FIFO_byte347 0x071E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte347 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte347 8 |
| #define bHDRX_HDCP_RD_FIFO_byte347 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte347 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO87 0x0720 |
| #define BA_HDRX_HDCP_RD_FIFO_byte348 0x0720 |
| #define B16HDRX_HDCP_RD_FIFO_byte348 0x0720 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte348 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte348 0 |
| #define bHDRX_HDCP_RD_FIFO_byte348 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte348 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte349 0x0721 |
| #define B16HDRX_HDCP_RD_FIFO_byte349 0x0720 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte349 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte349 8 |
| #define bHDRX_HDCP_RD_FIFO_byte349 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte349 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte350 0x0722 |
| #define B16HDRX_HDCP_RD_FIFO_byte350 0x0722 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte350 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte350 0 |
| #define bHDRX_HDCP_RD_FIFO_byte350 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte350 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte351 0x0723 |
| #define B16HDRX_HDCP_RD_FIFO_byte351 0x0722 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte351 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte351 8 |
| #define bHDRX_HDCP_RD_FIFO_byte351 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte351 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO88 0x0724 |
| #define BA_HDRX_HDCP_RD_FIFO_byte352 0x0724 |
| #define B16HDRX_HDCP_RD_FIFO_byte352 0x0724 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte352 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte352 0 |
| #define bHDRX_HDCP_RD_FIFO_byte352 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte352 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte353 0x0725 |
| #define B16HDRX_HDCP_RD_FIFO_byte353 0x0724 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte353 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte353 8 |
| #define bHDRX_HDCP_RD_FIFO_byte353 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte353 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte354 0x0726 |
| #define B16HDRX_HDCP_RD_FIFO_byte354 0x0726 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte354 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte354 0 |
| #define bHDRX_HDCP_RD_FIFO_byte354 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte354 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte355 0x0727 |
| #define B16HDRX_HDCP_RD_FIFO_byte355 0x0726 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte355 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte355 8 |
| #define bHDRX_HDCP_RD_FIFO_byte355 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte355 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO89 0x0728 |
| #define BA_HDRX_HDCP_RD_FIFO_byte356 0x0728 |
| #define B16HDRX_HDCP_RD_FIFO_byte356 0x0728 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte356 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte356 0 |
| #define bHDRX_HDCP_RD_FIFO_byte356 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte356 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte357 0x0729 |
| #define B16HDRX_HDCP_RD_FIFO_byte357 0x0728 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte357 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte357 8 |
| #define bHDRX_HDCP_RD_FIFO_byte357 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte357 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte358 0x072A |
| #define B16HDRX_HDCP_RD_FIFO_byte358 0x072A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte358 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte358 0 |
| #define bHDRX_HDCP_RD_FIFO_byte358 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte358 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte359 0x072B |
| #define B16HDRX_HDCP_RD_FIFO_byte359 0x072A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte359 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte359 8 |
| #define bHDRX_HDCP_RD_FIFO_byte359 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte359 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO90 0x072C |
| #define BA_HDRX_HDCP_RD_FIFO_byte360 0x072C |
| #define B16HDRX_HDCP_RD_FIFO_byte360 0x072C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte360 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte360 0 |
| #define bHDRX_HDCP_RD_FIFO_byte360 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte360 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte361 0x072D |
| #define B16HDRX_HDCP_RD_FIFO_byte361 0x072C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte361 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte361 8 |
| #define bHDRX_HDCP_RD_FIFO_byte361 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte361 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte362 0x072E |
| #define B16HDRX_HDCP_RD_FIFO_byte362 0x072E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte362 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte362 0 |
| #define bHDRX_HDCP_RD_FIFO_byte362 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte362 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte363 0x072F |
| #define B16HDRX_HDCP_RD_FIFO_byte363 0x072E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte363 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte363 8 |
| #define bHDRX_HDCP_RD_FIFO_byte363 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte363 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO91 0x0730 |
| #define BA_HDRX_HDCP_RD_FIFO_byte364 0x0730 |
| #define B16HDRX_HDCP_RD_FIFO_byte364 0x0730 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte364 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte364 0 |
| #define bHDRX_HDCP_RD_FIFO_byte364 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte364 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte365 0x0731 |
| #define B16HDRX_HDCP_RD_FIFO_byte365 0x0730 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte365 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte365 8 |
| #define bHDRX_HDCP_RD_FIFO_byte365 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte365 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte366 0x0732 |
| #define B16HDRX_HDCP_RD_FIFO_byte366 0x0732 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte366 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte366 0 |
| #define bHDRX_HDCP_RD_FIFO_byte366 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte366 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte367 0x0733 |
| #define B16HDRX_HDCP_RD_FIFO_byte367 0x0732 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte367 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte367 8 |
| #define bHDRX_HDCP_RD_FIFO_byte367 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte367 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO92 0x0734 |
| #define BA_HDRX_HDCP_RD_FIFO_byte368 0x0734 |
| #define B16HDRX_HDCP_RD_FIFO_byte368 0x0734 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte368 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte368 0 |
| #define bHDRX_HDCP_RD_FIFO_byte368 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte368 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte369 0x0735 |
| #define B16HDRX_HDCP_RD_FIFO_byte369 0x0734 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte369 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte369 8 |
| #define bHDRX_HDCP_RD_FIFO_byte369 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte369 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte370 0x0736 |
| #define B16HDRX_HDCP_RD_FIFO_byte370 0x0736 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte370 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte370 0 |
| #define bHDRX_HDCP_RD_FIFO_byte370 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte370 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte371 0x0737 |
| #define B16HDRX_HDCP_RD_FIFO_byte371 0x0736 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte371 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte371 8 |
| #define bHDRX_HDCP_RD_FIFO_byte371 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte371 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO93 0x0738 |
| #define BA_HDRX_HDCP_RD_FIFO_byte372 0x0738 |
| #define B16HDRX_HDCP_RD_FIFO_byte372 0x0738 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte372 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte372 0 |
| #define bHDRX_HDCP_RD_FIFO_byte372 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte372 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte373 0x0739 |
| #define B16HDRX_HDCP_RD_FIFO_byte373 0x0738 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte373 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte373 8 |
| #define bHDRX_HDCP_RD_FIFO_byte373 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte373 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte374 0x073A |
| #define B16HDRX_HDCP_RD_FIFO_byte374 0x073A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte374 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte374 0 |
| #define bHDRX_HDCP_RD_FIFO_byte374 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte374 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte375 0x073B |
| #define B16HDRX_HDCP_RD_FIFO_byte375 0x073A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte375 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte375 8 |
| #define bHDRX_HDCP_RD_FIFO_byte375 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte375 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO94 0x073C |
| #define BA_HDRX_HDCP_RD_FIFO_byte376 0x073C |
| #define B16HDRX_HDCP_RD_FIFO_byte376 0x073C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte376 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte376 0 |
| #define bHDRX_HDCP_RD_FIFO_byte376 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte376 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte377 0x073D |
| #define B16HDRX_HDCP_RD_FIFO_byte377 0x073C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte377 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte377 8 |
| #define bHDRX_HDCP_RD_FIFO_byte377 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte377 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte378 0x073E |
| #define B16HDRX_HDCP_RD_FIFO_byte378 0x073E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte378 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte378 0 |
| #define bHDRX_HDCP_RD_FIFO_byte378 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte378 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte379 0x073F |
| #define B16HDRX_HDCP_RD_FIFO_byte379 0x073E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte379 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte379 8 |
| #define bHDRX_HDCP_RD_FIFO_byte379 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte379 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO95 0x0740 |
| #define BA_HDRX_HDCP_RD_FIFO_byte380 0x0740 |
| #define B16HDRX_HDCP_RD_FIFO_byte380 0x0740 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte380 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte380 0 |
| #define bHDRX_HDCP_RD_FIFO_byte380 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte380 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte381 0x0741 |
| #define B16HDRX_HDCP_RD_FIFO_byte381 0x0740 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte381 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte381 8 |
| #define bHDRX_HDCP_RD_FIFO_byte381 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte381 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte382 0x0742 |
| #define B16HDRX_HDCP_RD_FIFO_byte382 0x0742 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte382 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte382 0 |
| #define bHDRX_HDCP_RD_FIFO_byte382 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte382 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte383 0x0743 |
| #define B16HDRX_HDCP_RD_FIFO_byte383 0x0742 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte383 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte383 8 |
| #define bHDRX_HDCP_RD_FIFO_byte383 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte383 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO96 0x0744 |
| #define BA_HDRX_HDCP_RD_FIFO_byte384 0x0744 |
| #define B16HDRX_HDCP_RD_FIFO_byte384 0x0744 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte384 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte384 0 |
| #define bHDRX_HDCP_RD_FIFO_byte384 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte384 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte385 0x0745 |
| #define B16HDRX_HDCP_RD_FIFO_byte385 0x0744 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte385 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte385 8 |
| #define bHDRX_HDCP_RD_FIFO_byte385 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte385 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte386 0x0746 |
| #define B16HDRX_HDCP_RD_FIFO_byte386 0x0746 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte386 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte386 0 |
| #define bHDRX_HDCP_RD_FIFO_byte386 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte386 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte387 0x0747 |
| #define B16HDRX_HDCP_RD_FIFO_byte387 0x0746 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte387 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte387 8 |
| #define bHDRX_HDCP_RD_FIFO_byte387 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte387 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO97 0x0748 |
| #define BA_HDRX_HDCP_RD_FIFO_byte388 0x0748 |
| #define B16HDRX_HDCP_RD_FIFO_byte388 0x0748 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte388 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte388 0 |
| #define bHDRX_HDCP_RD_FIFO_byte388 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte388 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte389 0x0749 |
| #define B16HDRX_HDCP_RD_FIFO_byte389 0x0748 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte389 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte389 8 |
| #define bHDRX_HDCP_RD_FIFO_byte389 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte389 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte390 0x074A |
| #define B16HDRX_HDCP_RD_FIFO_byte390 0x074A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte390 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte390 0 |
| #define bHDRX_HDCP_RD_FIFO_byte390 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte390 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte391 0x074B |
| #define B16HDRX_HDCP_RD_FIFO_byte391 0x074A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte391 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte391 8 |
| #define bHDRX_HDCP_RD_FIFO_byte391 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte391 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO98 0x074C |
| #define BA_HDRX_HDCP_RD_FIFO_byte392 0x074C |
| #define B16HDRX_HDCP_RD_FIFO_byte392 0x074C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte392 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte392 0 |
| #define bHDRX_HDCP_RD_FIFO_byte392 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte392 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte393 0x074D |
| #define B16HDRX_HDCP_RD_FIFO_byte393 0x074C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte393 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte393 8 |
| #define bHDRX_HDCP_RD_FIFO_byte393 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte393 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte394 0x074E |
| #define B16HDRX_HDCP_RD_FIFO_byte394 0x074E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte394 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte394 0 |
| #define bHDRX_HDCP_RD_FIFO_byte394 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte394 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte395 0x074F |
| #define B16HDRX_HDCP_RD_FIFO_byte395 0x074E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte395 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte395 8 |
| #define bHDRX_HDCP_RD_FIFO_byte395 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte395 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO99 0x0750 |
| #define BA_HDRX_HDCP_RD_FIFO_byte396 0x0750 |
| #define B16HDRX_HDCP_RD_FIFO_byte396 0x0750 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte396 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte396 0 |
| #define bHDRX_HDCP_RD_FIFO_byte396 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte396 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte397 0x0751 |
| #define B16HDRX_HDCP_RD_FIFO_byte397 0x0750 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte397 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte397 8 |
| #define bHDRX_HDCP_RD_FIFO_byte397 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte397 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte398 0x0752 |
| #define B16HDRX_HDCP_RD_FIFO_byte398 0x0752 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte398 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte398 0 |
| #define bHDRX_HDCP_RD_FIFO_byte398 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte398 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte399 0x0753 |
| #define B16HDRX_HDCP_RD_FIFO_byte399 0x0752 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte399 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte399 8 |
| #define bHDRX_HDCP_RD_FIFO_byte399 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte399 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO100 0x0754 |
| #define BA_HDRX_HDCP_RD_FIFO_byte400 0x0754 |
| #define B16HDRX_HDCP_RD_FIFO_byte400 0x0754 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte400 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte400 0 |
| #define bHDRX_HDCP_RD_FIFO_byte400 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte400 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte401 0x0755 |
| #define B16HDRX_HDCP_RD_FIFO_byte401 0x0754 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte401 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte401 8 |
| #define bHDRX_HDCP_RD_FIFO_byte401 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte401 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte402 0x0756 |
| #define B16HDRX_HDCP_RD_FIFO_byte402 0x0756 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte402 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte402 0 |
| #define bHDRX_HDCP_RD_FIFO_byte402 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte402 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte403 0x0757 |
| #define B16HDRX_HDCP_RD_FIFO_byte403 0x0756 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte403 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte403 8 |
| #define bHDRX_HDCP_RD_FIFO_byte403 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte403 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO101 0x0758 |
| #define BA_HDRX_HDCP_RD_FIFO_byte404 0x0758 |
| #define B16HDRX_HDCP_RD_FIFO_byte404 0x0758 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte404 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte404 0 |
| #define bHDRX_HDCP_RD_FIFO_byte404 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte404 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte405 0x0759 |
| #define B16HDRX_HDCP_RD_FIFO_byte405 0x0758 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte405 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte405 8 |
| #define bHDRX_HDCP_RD_FIFO_byte405 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte405 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte406 0x075A |
| #define B16HDRX_HDCP_RD_FIFO_byte406 0x075A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte406 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte406 0 |
| #define bHDRX_HDCP_RD_FIFO_byte406 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte406 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte407 0x075B |
| #define B16HDRX_HDCP_RD_FIFO_byte407 0x075A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte407 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte407 8 |
| #define bHDRX_HDCP_RD_FIFO_byte407 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte407 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO102 0x075C |
| #define BA_HDRX_HDCP_RD_FIFO_byte408 0x075C |
| #define B16HDRX_HDCP_RD_FIFO_byte408 0x075C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte408 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte408 0 |
| #define bHDRX_HDCP_RD_FIFO_byte408 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte408 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte409 0x075D |
| #define B16HDRX_HDCP_RD_FIFO_byte409 0x075C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte409 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte409 8 |
| #define bHDRX_HDCP_RD_FIFO_byte409 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte409 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte410 0x075E |
| #define B16HDRX_HDCP_RD_FIFO_byte410 0x075E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte410 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte410 0 |
| #define bHDRX_HDCP_RD_FIFO_byte410 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte410 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte411 0x075F |
| #define B16HDRX_HDCP_RD_FIFO_byte411 0x075E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte411 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte411 8 |
| #define bHDRX_HDCP_RD_FIFO_byte411 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte411 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO103 0x0760 |
| #define BA_HDRX_HDCP_RD_FIFO_byte412 0x0760 |
| #define B16HDRX_HDCP_RD_FIFO_byte412 0x0760 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte412 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte412 0 |
| #define bHDRX_HDCP_RD_FIFO_byte412 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte412 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte413 0x0761 |
| #define B16HDRX_HDCP_RD_FIFO_byte413 0x0760 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte413 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte413 8 |
| #define bHDRX_HDCP_RD_FIFO_byte413 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte413 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte414 0x0762 |
| #define B16HDRX_HDCP_RD_FIFO_byte414 0x0762 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte414 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte414 0 |
| #define bHDRX_HDCP_RD_FIFO_byte414 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte414 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte415 0x0763 |
| #define B16HDRX_HDCP_RD_FIFO_byte415 0x0762 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte415 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte415 8 |
| #define bHDRX_HDCP_RD_FIFO_byte415 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte415 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO104 0x0764 |
| #define BA_HDRX_HDCP_RD_FIFO_byte416 0x0764 |
| #define B16HDRX_HDCP_RD_FIFO_byte416 0x0764 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte416 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte416 0 |
| #define bHDRX_HDCP_RD_FIFO_byte416 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte416 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte417 0x0765 |
| #define B16HDRX_HDCP_RD_FIFO_byte417 0x0764 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte417 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte417 8 |
| #define bHDRX_HDCP_RD_FIFO_byte417 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte417 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte418 0x0766 |
| #define B16HDRX_HDCP_RD_FIFO_byte418 0x0766 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte418 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte418 0 |
| #define bHDRX_HDCP_RD_FIFO_byte418 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte418 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte419 0x0767 |
| #define B16HDRX_HDCP_RD_FIFO_byte419 0x0766 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte419 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte419 8 |
| #define bHDRX_HDCP_RD_FIFO_byte419 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte419 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO105 0x0768 |
| #define BA_HDRX_HDCP_RD_FIFO_byte420 0x0768 |
| #define B16HDRX_HDCP_RD_FIFO_byte420 0x0768 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte420 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte420 0 |
| #define bHDRX_HDCP_RD_FIFO_byte420 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte420 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte421 0x0769 |
| #define B16HDRX_HDCP_RD_FIFO_byte421 0x0768 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte421 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte421 8 |
| #define bHDRX_HDCP_RD_FIFO_byte421 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte421 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte422 0x076A |
| #define B16HDRX_HDCP_RD_FIFO_byte422 0x076A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte422 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte422 0 |
| #define bHDRX_HDCP_RD_FIFO_byte422 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte422 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte423 0x076B |
| #define B16HDRX_HDCP_RD_FIFO_byte423 0x076A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte423 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte423 8 |
| #define bHDRX_HDCP_RD_FIFO_byte423 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte423 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO106 0x076C |
| #define BA_HDRX_HDCP_RD_FIFO_byte424 0x076C |
| #define B16HDRX_HDCP_RD_FIFO_byte424 0x076C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte424 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte424 0 |
| #define bHDRX_HDCP_RD_FIFO_byte424 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte424 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte425 0x076D |
| #define B16HDRX_HDCP_RD_FIFO_byte425 0x076C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte425 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte425 8 |
| #define bHDRX_HDCP_RD_FIFO_byte425 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte425 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte426 0x076E |
| #define B16HDRX_HDCP_RD_FIFO_byte426 0x076E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte426 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte426 0 |
| #define bHDRX_HDCP_RD_FIFO_byte426 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte426 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte427 0x076F |
| #define B16HDRX_HDCP_RD_FIFO_byte427 0x076E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte427 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte427 8 |
| #define bHDRX_HDCP_RD_FIFO_byte427 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte427 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO107 0x0770 |
| #define BA_HDRX_HDCP_RD_FIFO_byte428 0x0770 |
| #define B16HDRX_HDCP_RD_FIFO_byte428 0x0770 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte428 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte428 0 |
| #define bHDRX_HDCP_RD_FIFO_byte428 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte428 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte429 0x0771 |
| #define B16HDRX_HDCP_RD_FIFO_byte429 0x0770 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte429 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte429 8 |
| #define bHDRX_HDCP_RD_FIFO_byte429 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte429 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte430 0x0772 |
| #define B16HDRX_HDCP_RD_FIFO_byte430 0x0772 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte430 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte430 0 |
| #define bHDRX_HDCP_RD_FIFO_byte430 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte430 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte431 0x0773 |
| #define B16HDRX_HDCP_RD_FIFO_byte431 0x0772 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte431 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte431 8 |
| #define bHDRX_HDCP_RD_FIFO_byte431 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte431 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO108 0x0774 |
| #define BA_HDRX_HDCP_RD_FIFO_byte432 0x0774 |
| #define B16HDRX_HDCP_RD_FIFO_byte432 0x0774 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte432 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte432 0 |
| #define bHDRX_HDCP_RD_FIFO_byte432 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte432 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte433 0x0775 |
| #define B16HDRX_HDCP_RD_FIFO_byte433 0x0774 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte433 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte433 8 |
| #define bHDRX_HDCP_RD_FIFO_byte433 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte433 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte434 0x0776 |
| #define B16HDRX_HDCP_RD_FIFO_byte434 0x0776 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte434 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte434 0 |
| #define bHDRX_HDCP_RD_FIFO_byte434 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte434 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte435 0x0777 |
| #define B16HDRX_HDCP_RD_FIFO_byte435 0x0776 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte435 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte435 8 |
| #define bHDRX_HDCP_RD_FIFO_byte435 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte435 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO109 0x0778 |
| #define BA_HDRX_HDCP_RD_FIFO_byte436 0x0778 |
| #define B16HDRX_HDCP_RD_FIFO_byte436 0x0778 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte436 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte436 0 |
| #define bHDRX_HDCP_RD_FIFO_byte436 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte436 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte437 0x0779 |
| #define B16HDRX_HDCP_RD_FIFO_byte437 0x0778 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte437 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte437 8 |
| #define bHDRX_HDCP_RD_FIFO_byte437 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte437 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte438 0x077A |
| #define B16HDRX_HDCP_RD_FIFO_byte438 0x077A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte438 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte438 0 |
| #define bHDRX_HDCP_RD_FIFO_byte438 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte438 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte439 0x077B |
| #define B16HDRX_HDCP_RD_FIFO_byte439 0x077A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte439 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte439 8 |
| #define bHDRX_HDCP_RD_FIFO_byte439 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte439 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO110 0x077C |
| #define BA_HDRX_HDCP_RD_FIFO_byte440 0x077C |
| #define B16HDRX_HDCP_RD_FIFO_byte440 0x077C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte440 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte440 0 |
| #define bHDRX_HDCP_RD_FIFO_byte440 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte440 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte441 0x077D |
| #define B16HDRX_HDCP_RD_FIFO_byte441 0x077C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte441 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte441 8 |
| #define bHDRX_HDCP_RD_FIFO_byte441 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte441 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte442 0x077E |
| #define B16HDRX_HDCP_RD_FIFO_byte442 0x077E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte442 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte442 0 |
| #define bHDRX_HDCP_RD_FIFO_byte442 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte442 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte443 0x077F |
| #define B16HDRX_HDCP_RD_FIFO_byte443 0x077E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte443 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte443 8 |
| #define bHDRX_HDCP_RD_FIFO_byte443 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte443 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO111 0x0780 |
| #define BA_HDRX_HDCP_RD_FIFO_byte444 0x0780 |
| #define B16HDRX_HDCP_RD_FIFO_byte444 0x0780 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte444 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte444 0 |
| #define bHDRX_HDCP_RD_FIFO_byte444 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte444 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte445 0x0781 |
| #define B16HDRX_HDCP_RD_FIFO_byte445 0x0780 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte445 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte445 8 |
| #define bHDRX_HDCP_RD_FIFO_byte445 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte445 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte446 0x0782 |
| #define B16HDRX_HDCP_RD_FIFO_byte446 0x0782 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte446 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte446 0 |
| #define bHDRX_HDCP_RD_FIFO_byte446 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte446 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte447 0x0783 |
| #define B16HDRX_HDCP_RD_FIFO_byte447 0x0782 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte447 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte447 8 |
| #define bHDRX_HDCP_RD_FIFO_byte447 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte447 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO112 0x0784 |
| #define BA_HDRX_HDCP_RD_FIFO_byte448 0x0784 |
| #define B16HDRX_HDCP_RD_FIFO_byte448 0x0784 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte448 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte448 0 |
| #define bHDRX_HDCP_RD_FIFO_byte448 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte448 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte449 0x0785 |
| #define B16HDRX_HDCP_RD_FIFO_byte449 0x0784 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte449 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte449 8 |
| #define bHDRX_HDCP_RD_FIFO_byte449 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte449 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte450 0x0786 |
| #define B16HDRX_HDCP_RD_FIFO_byte450 0x0786 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte450 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte450 0 |
| #define bHDRX_HDCP_RD_FIFO_byte450 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte450 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte451 0x0787 |
| #define B16HDRX_HDCP_RD_FIFO_byte451 0x0786 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte451 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte451 8 |
| #define bHDRX_HDCP_RD_FIFO_byte451 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte451 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO113 0x0788 |
| #define BA_HDRX_HDCP_RD_FIFO_byte452 0x0788 |
| #define B16HDRX_HDCP_RD_FIFO_byte452 0x0788 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte452 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte452 0 |
| #define bHDRX_HDCP_RD_FIFO_byte452 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte452 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte453 0x0789 |
| #define B16HDRX_HDCP_RD_FIFO_byte453 0x0788 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte453 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte453 8 |
| #define bHDRX_HDCP_RD_FIFO_byte453 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte453 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte454 0x078A |
| #define B16HDRX_HDCP_RD_FIFO_byte454 0x078A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte454 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte454 0 |
| #define bHDRX_HDCP_RD_FIFO_byte454 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte454 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte455 0x078B |
| #define B16HDRX_HDCP_RD_FIFO_byte455 0x078A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte455 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte455 8 |
| #define bHDRX_HDCP_RD_FIFO_byte455 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte455 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO114 0x078C |
| #define BA_HDRX_HDCP_RD_FIFO_byte456 0x078C |
| #define B16HDRX_HDCP_RD_FIFO_byte456 0x078C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte456 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte456 0 |
| #define bHDRX_HDCP_RD_FIFO_byte456 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte456 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte457 0x078D |
| #define B16HDRX_HDCP_RD_FIFO_byte457 0x078C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte457 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte457 8 |
| #define bHDRX_HDCP_RD_FIFO_byte457 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte457 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte458 0x078E |
| #define B16HDRX_HDCP_RD_FIFO_byte458 0x078E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte458 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte458 0 |
| #define bHDRX_HDCP_RD_FIFO_byte458 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte458 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte459 0x078F |
| #define B16HDRX_HDCP_RD_FIFO_byte459 0x078E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte459 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte459 8 |
| #define bHDRX_HDCP_RD_FIFO_byte459 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte459 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO115 0x0790 |
| #define BA_HDRX_HDCP_RD_FIFO_byte460 0x0790 |
| #define B16HDRX_HDCP_RD_FIFO_byte460 0x0790 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte460 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte460 0 |
| #define bHDRX_HDCP_RD_FIFO_byte460 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte460 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte461 0x0791 |
| #define B16HDRX_HDCP_RD_FIFO_byte461 0x0790 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte461 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte461 8 |
| #define bHDRX_HDCP_RD_FIFO_byte461 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte461 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte462 0x0792 |
| #define B16HDRX_HDCP_RD_FIFO_byte462 0x0792 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte462 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte462 0 |
| #define bHDRX_HDCP_RD_FIFO_byte462 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte462 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte463 0x0793 |
| #define B16HDRX_HDCP_RD_FIFO_byte463 0x0792 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte463 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte463 8 |
| #define bHDRX_HDCP_RD_FIFO_byte463 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte463 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO116 0x0794 |
| #define BA_HDRX_HDCP_RD_FIFO_byte464 0x0794 |
| #define B16HDRX_HDCP_RD_FIFO_byte464 0x0794 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte464 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte464 0 |
| #define bHDRX_HDCP_RD_FIFO_byte464 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte464 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte465 0x0795 |
| #define B16HDRX_HDCP_RD_FIFO_byte465 0x0794 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte465 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte465 8 |
| #define bHDRX_HDCP_RD_FIFO_byte465 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte465 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte466 0x0796 |
| #define B16HDRX_HDCP_RD_FIFO_byte466 0x0796 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte466 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte466 0 |
| #define bHDRX_HDCP_RD_FIFO_byte466 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte466 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte467 0x0797 |
| #define B16HDRX_HDCP_RD_FIFO_byte467 0x0796 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte467 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte467 8 |
| #define bHDRX_HDCP_RD_FIFO_byte467 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte467 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO117 0x0798 |
| #define BA_HDRX_HDCP_RD_FIFO_byte468 0x0798 |
| #define B16HDRX_HDCP_RD_FIFO_byte468 0x0798 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte468 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte468 0 |
| #define bHDRX_HDCP_RD_FIFO_byte468 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte468 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte469 0x0799 |
| #define B16HDRX_HDCP_RD_FIFO_byte469 0x0798 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte469 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte469 8 |
| #define bHDRX_HDCP_RD_FIFO_byte469 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte469 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte470 0x079A |
| #define B16HDRX_HDCP_RD_FIFO_byte470 0x079A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte470 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte470 0 |
| #define bHDRX_HDCP_RD_FIFO_byte470 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte470 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte471 0x079B |
| #define B16HDRX_HDCP_RD_FIFO_byte471 0x079A |
| #define LSb32HDRX_HDCP_RD_FIFO_byte471 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte471 8 |
| #define bHDRX_HDCP_RD_FIFO_byte471 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte471 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO118 0x079C |
| #define BA_HDRX_HDCP_RD_FIFO_byte472 0x079C |
| #define B16HDRX_HDCP_RD_FIFO_byte472 0x079C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte472 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte472 0 |
| #define bHDRX_HDCP_RD_FIFO_byte472 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte472 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte473 0x079D |
| #define B16HDRX_HDCP_RD_FIFO_byte473 0x079C |
| #define LSb32HDRX_HDCP_RD_FIFO_byte473 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte473 8 |
| #define bHDRX_HDCP_RD_FIFO_byte473 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte473 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte474 0x079E |
| #define B16HDRX_HDCP_RD_FIFO_byte474 0x079E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte474 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte474 0 |
| #define bHDRX_HDCP_RD_FIFO_byte474 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte474 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte475 0x079F |
| #define B16HDRX_HDCP_RD_FIFO_byte475 0x079E |
| #define LSb32HDRX_HDCP_RD_FIFO_byte475 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte475 8 |
| #define bHDRX_HDCP_RD_FIFO_byte475 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte475 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO119 0x07A0 |
| #define BA_HDRX_HDCP_RD_FIFO_byte476 0x07A0 |
| #define B16HDRX_HDCP_RD_FIFO_byte476 0x07A0 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte476 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte476 0 |
| #define bHDRX_HDCP_RD_FIFO_byte476 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte476 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte477 0x07A1 |
| #define B16HDRX_HDCP_RD_FIFO_byte477 0x07A0 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte477 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte477 8 |
| #define bHDRX_HDCP_RD_FIFO_byte477 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte477 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte478 0x07A2 |
| #define B16HDRX_HDCP_RD_FIFO_byte478 0x07A2 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte478 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte478 0 |
| #define bHDRX_HDCP_RD_FIFO_byte478 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte478 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte479 0x07A3 |
| #define B16HDRX_HDCP_RD_FIFO_byte479 0x07A2 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte479 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte479 8 |
| #define bHDRX_HDCP_RD_FIFO_byte479 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte479 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO120 0x07A4 |
| #define BA_HDRX_HDCP_RD_FIFO_byte480 0x07A4 |
| #define B16HDRX_HDCP_RD_FIFO_byte480 0x07A4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte480 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte480 0 |
| #define bHDRX_HDCP_RD_FIFO_byte480 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte480 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte481 0x07A5 |
| #define B16HDRX_HDCP_RD_FIFO_byte481 0x07A4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte481 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte481 8 |
| #define bHDRX_HDCP_RD_FIFO_byte481 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte481 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte482 0x07A6 |
| #define B16HDRX_HDCP_RD_FIFO_byte482 0x07A6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte482 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte482 0 |
| #define bHDRX_HDCP_RD_FIFO_byte482 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte482 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte483 0x07A7 |
| #define B16HDRX_HDCP_RD_FIFO_byte483 0x07A6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte483 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte483 8 |
| #define bHDRX_HDCP_RD_FIFO_byte483 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte483 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO121 0x07A8 |
| #define BA_HDRX_HDCP_RD_FIFO_byte484 0x07A8 |
| #define B16HDRX_HDCP_RD_FIFO_byte484 0x07A8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte484 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte484 0 |
| #define bHDRX_HDCP_RD_FIFO_byte484 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte484 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte485 0x07A9 |
| #define B16HDRX_HDCP_RD_FIFO_byte485 0x07A8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte485 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte485 8 |
| #define bHDRX_HDCP_RD_FIFO_byte485 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte485 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte486 0x07AA |
| #define B16HDRX_HDCP_RD_FIFO_byte486 0x07AA |
| #define LSb32HDRX_HDCP_RD_FIFO_byte486 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte486 0 |
| #define bHDRX_HDCP_RD_FIFO_byte486 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte486 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte487 0x07AB |
| #define B16HDRX_HDCP_RD_FIFO_byte487 0x07AA |
| #define LSb32HDRX_HDCP_RD_FIFO_byte487 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte487 8 |
| #define bHDRX_HDCP_RD_FIFO_byte487 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte487 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO122 0x07AC |
| #define BA_HDRX_HDCP_RD_FIFO_byte488 0x07AC |
| #define B16HDRX_HDCP_RD_FIFO_byte488 0x07AC |
| #define LSb32HDRX_HDCP_RD_FIFO_byte488 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte488 0 |
| #define bHDRX_HDCP_RD_FIFO_byte488 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte488 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte489 0x07AD |
| #define B16HDRX_HDCP_RD_FIFO_byte489 0x07AC |
| #define LSb32HDRX_HDCP_RD_FIFO_byte489 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte489 8 |
| #define bHDRX_HDCP_RD_FIFO_byte489 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte489 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte490 0x07AE |
| #define B16HDRX_HDCP_RD_FIFO_byte490 0x07AE |
| #define LSb32HDRX_HDCP_RD_FIFO_byte490 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte490 0 |
| #define bHDRX_HDCP_RD_FIFO_byte490 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte490 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte491 0x07AF |
| #define B16HDRX_HDCP_RD_FIFO_byte491 0x07AE |
| #define LSb32HDRX_HDCP_RD_FIFO_byte491 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte491 8 |
| #define bHDRX_HDCP_RD_FIFO_byte491 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte491 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO123 0x07B0 |
| #define BA_HDRX_HDCP_RD_FIFO_byte492 0x07B0 |
| #define B16HDRX_HDCP_RD_FIFO_byte492 0x07B0 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte492 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte492 0 |
| #define bHDRX_HDCP_RD_FIFO_byte492 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte492 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte493 0x07B1 |
| #define B16HDRX_HDCP_RD_FIFO_byte493 0x07B0 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte493 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte493 8 |
| #define bHDRX_HDCP_RD_FIFO_byte493 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte493 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte494 0x07B2 |
| #define B16HDRX_HDCP_RD_FIFO_byte494 0x07B2 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte494 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte494 0 |
| #define bHDRX_HDCP_RD_FIFO_byte494 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte494 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte495 0x07B3 |
| #define B16HDRX_HDCP_RD_FIFO_byte495 0x07B2 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte495 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte495 8 |
| #define bHDRX_HDCP_RD_FIFO_byte495 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte495 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO124 0x07B4 |
| #define BA_HDRX_HDCP_RD_FIFO_byte496 0x07B4 |
| #define B16HDRX_HDCP_RD_FIFO_byte496 0x07B4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte496 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte496 0 |
| #define bHDRX_HDCP_RD_FIFO_byte496 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte496 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte497 0x07B5 |
| #define B16HDRX_HDCP_RD_FIFO_byte497 0x07B4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte497 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte497 8 |
| #define bHDRX_HDCP_RD_FIFO_byte497 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte497 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte498 0x07B6 |
| #define B16HDRX_HDCP_RD_FIFO_byte498 0x07B6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte498 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte498 0 |
| #define bHDRX_HDCP_RD_FIFO_byte498 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte498 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte499 0x07B7 |
| #define B16HDRX_HDCP_RD_FIFO_byte499 0x07B6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte499 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte499 8 |
| #define bHDRX_HDCP_RD_FIFO_byte499 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte499 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO125 0x07B8 |
| #define BA_HDRX_HDCP_RD_FIFO_byte500 0x07B8 |
| #define B16HDRX_HDCP_RD_FIFO_byte500 0x07B8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte500 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte500 0 |
| #define bHDRX_HDCP_RD_FIFO_byte500 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte500 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte501 0x07B9 |
| #define B16HDRX_HDCP_RD_FIFO_byte501 0x07B8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte501 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte501 8 |
| #define bHDRX_HDCP_RD_FIFO_byte501 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte501 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte502 0x07BA |
| #define B16HDRX_HDCP_RD_FIFO_byte502 0x07BA |
| #define LSb32HDRX_HDCP_RD_FIFO_byte502 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte502 0 |
| #define bHDRX_HDCP_RD_FIFO_byte502 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte502 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte503 0x07BB |
| #define B16HDRX_HDCP_RD_FIFO_byte503 0x07BA |
| #define LSb32HDRX_HDCP_RD_FIFO_byte503 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte503 8 |
| #define bHDRX_HDCP_RD_FIFO_byte503 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte503 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO126 0x07BC |
| #define BA_HDRX_HDCP_RD_FIFO_byte504 0x07BC |
| #define B16HDRX_HDCP_RD_FIFO_byte504 0x07BC |
| #define LSb32HDRX_HDCP_RD_FIFO_byte504 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte504 0 |
| #define bHDRX_HDCP_RD_FIFO_byte504 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte504 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte505 0x07BD |
| #define B16HDRX_HDCP_RD_FIFO_byte505 0x07BC |
| #define LSb32HDRX_HDCP_RD_FIFO_byte505 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte505 8 |
| #define bHDRX_HDCP_RD_FIFO_byte505 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte505 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte506 0x07BE |
| #define B16HDRX_HDCP_RD_FIFO_byte506 0x07BE |
| #define LSb32HDRX_HDCP_RD_FIFO_byte506 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte506 0 |
| #define bHDRX_HDCP_RD_FIFO_byte506 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte506 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte507 0x07BF |
| #define B16HDRX_HDCP_RD_FIFO_byte507 0x07BE |
| #define LSb32HDRX_HDCP_RD_FIFO_byte507 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte507 8 |
| #define bHDRX_HDCP_RD_FIFO_byte507 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte507 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO127 0x07C0 |
| #define BA_HDRX_HDCP_RD_FIFO_byte508 0x07C0 |
| #define B16HDRX_HDCP_RD_FIFO_byte508 0x07C0 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte508 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte508 0 |
| #define bHDRX_HDCP_RD_FIFO_byte508 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte508 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte509 0x07C1 |
| #define B16HDRX_HDCP_RD_FIFO_byte509 0x07C0 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte509 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte509 8 |
| #define bHDRX_HDCP_RD_FIFO_byte509 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte509 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte510 0x07C2 |
| #define B16HDRX_HDCP_RD_FIFO_byte510 0x07C2 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte510 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte510 0 |
| #define bHDRX_HDCP_RD_FIFO_byte510 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte510 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte511 0x07C3 |
| #define B16HDRX_HDCP_RD_FIFO_byte511 0x07C2 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte511 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte511 8 |
| #define bHDRX_HDCP_RD_FIFO_byte511 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte511 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO128 0x07C4 |
| #define BA_HDRX_HDCP_RD_FIFO_byte512 0x07C4 |
| #define B16HDRX_HDCP_RD_FIFO_byte512 0x07C4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte512 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte512 0 |
| #define bHDRX_HDCP_RD_FIFO_byte512 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte512 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte513 0x07C5 |
| #define B16HDRX_HDCP_RD_FIFO_byte513 0x07C4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte513 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte513 8 |
| #define bHDRX_HDCP_RD_FIFO_byte513 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte513 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte514 0x07C6 |
| #define B16HDRX_HDCP_RD_FIFO_byte514 0x07C6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte514 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte514 0 |
| #define bHDRX_HDCP_RD_FIFO_byte514 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte514 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte515 0x07C7 |
| #define B16HDRX_HDCP_RD_FIFO_byte515 0x07C6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte515 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte515 8 |
| #define bHDRX_HDCP_RD_FIFO_byte515 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte515 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO129 0x07C8 |
| #define BA_HDRX_HDCP_RD_FIFO_byte516 0x07C8 |
| #define B16HDRX_HDCP_RD_FIFO_byte516 0x07C8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte516 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte516 0 |
| #define bHDRX_HDCP_RD_FIFO_byte516 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte516 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte517 0x07C9 |
| #define B16HDRX_HDCP_RD_FIFO_byte517 0x07C8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte517 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte517 8 |
| #define bHDRX_HDCP_RD_FIFO_byte517 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte517 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte518 0x07CA |
| #define B16HDRX_HDCP_RD_FIFO_byte518 0x07CA |
| #define LSb32HDRX_HDCP_RD_FIFO_byte518 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte518 0 |
| #define bHDRX_HDCP_RD_FIFO_byte518 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte518 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte519 0x07CB |
| #define B16HDRX_HDCP_RD_FIFO_byte519 0x07CA |
| #define LSb32HDRX_HDCP_RD_FIFO_byte519 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte519 8 |
| #define bHDRX_HDCP_RD_FIFO_byte519 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte519 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO130 0x07CC |
| #define BA_HDRX_HDCP_RD_FIFO_byte520 0x07CC |
| #define B16HDRX_HDCP_RD_FIFO_byte520 0x07CC |
| #define LSb32HDRX_HDCP_RD_FIFO_byte520 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte520 0 |
| #define bHDRX_HDCP_RD_FIFO_byte520 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte520 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte521 0x07CD |
| #define B16HDRX_HDCP_RD_FIFO_byte521 0x07CC |
| #define LSb32HDRX_HDCP_RD_FIFO_byte521 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte521 8 |
| #define bHDRX_HDCP_RD_FIFO_byte521 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte521 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte522 0x07CE |
| #define B16HDRX_HDCP_RD_FIFO_byte522 0x07CE |
| #define LSb32HDRX_HDCP_RD_FIFO_byte522 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte522 0 |
| #define bHDRX_HDCP_RD_FIFO_byte522 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte522 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte523 0x07CF |
| #define B16HDRX_HDCP_RD_FIFO_byte523 0x07CE |
| #define LSb32HDRX_HDCP_RD_FIFO_byte523 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte523 8 |
| #define bHDRX_HDCP_RD_FIFO_byte523 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte523 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO131 0x07D0 |
| #define BA_HDRX_HDCP_RD_FIFO_byte524 0x07D0 |
| #define B16HDRX_HDCP_RD_FIFO_byte524 0x07D0 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte524 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte524 0 |
| #define bHDRX_HDCP_RD_FIFO_byte524 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte524 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte525 0x07D1 |
| #define B16HDRX_HDCP_RD_FIFO_byte525 0x07D0 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte525 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte525 8 |
| #define bHDRX_HDCP_RD_FIFO_byte525 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte525 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte526 0x07D2 |
| #define B16HDRX_HDCP_RD_FIFO_byte526 0x07D2 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte526 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte526 0 |
| #define bHDRX_HDCP_RD_FIFO_byte526 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte526 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte527 0x07D3 |
| #define B16HDRX_HDCP_RD_FIFO_byte527 0x07D2 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte527 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte527 8 |
| #define bHDRX_HDCP_RD_FIFO_byte527 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte527 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO132 0x07D4 |
| #define BA_HDRX_HDCP_RD_FIFO_byte528 0x07D4 |
| #define B16HDRX_HDCP_RD_FIFO_byte528 0x07D4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte528 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte528 0 |
| #define bHDRX_HDCP_RD_FIFO_byte528 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte528 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte529 0x07D5 |
| #define B16HDRX_HDCP_RD_FIFO_byte529 0x07D4 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte529 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte529 8 |
| #define bHDRX_HDCP_RD_FIFO_byte529 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte529 0x0000FF00 |
| #define BA_HDRX_HDCP_RD_FIFO_byte530 0x07D6 |
| #define B16HDRX_HDCP_RD_FIFO_byte530 0x07D6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte530 16 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte530 0 |
| #define bHDRX_HDCP_RD_FIFO_byte530 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte530 0x00FF0000 |
| #define BA_HDRX_HDCP_RD_FIFO_byte531 0x07D7 |
| #define B16HDRX_HDCP_RD_FIFO_byte531 0x07D6 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte531 24 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte531 8 |
| #define bHDRX_HDCP_RD_FIFO_byte531 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte531 0xFF000000 |
| #define RA_HDRX_HDCP_RD_FIFO133 0x07D8 |
| #define BA_HDRX_HDCP_RD_FIFO_byte532 0x07D8 |
| #define B16HDRX_HDCP_RD_FIFO_byte532 0x07D8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte532 0 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte532 0 |
| #define bHDRX_HDCP_RD_FIFO_byte532 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte532 0x000000FF |
| #define BA_HDRX_HDCP_RD_FIFO_byte533 0x07D9 |
| #define B16HDRX_HDCP_RD_FIFO_byte533 0x07D8 |
| #define LSb32HDRX_HDCP_RD_FIFO_byte533 8 |
| #define LSb16HDRX_HDCP_RD_FIFO_byte533 8 |
| #define bHDRX_HDCP_RD_FIFO_byte533 8 |
| #define MSK32HDRX_HDCP_RD_FIFO_byte533 0x0000FF00 |
| #define RA_HDRX_HDCP22_HMAC_SHA_CTRL 0x07DC |
| #define BA_HDRX_HDCP22_HMAC_SHA_CTRL_soft_reset 0x07DC |
| #define B16HDRX_HDCP22_HMAC_SHA_CTRL_soft_reset 0x07DC |
| #define LSb32HDRX_HDCP22_HMAC_SHA_CTRL_soft_reset 0 |
| #define LSb16HDRX_HDCP22_HMAC_SHA_CTRL_soft_reset 0 |
| #define bHDRX_HDCP22_HMAC_SHA_CTRL_soft_reset 1 |
| #define MSK32HDRX_HDCP22_HMAC_SHA_CTRL_soft_reset 0x00000001 |
| #define BA_HDRX_HDCP22_HMAC_SHA_CTRL_lc_trigger 0x07DC |
| #define B16HDRX_HDCP22_HMAC_SHA_CTRL_lc_trigger 0x07DC |
| #define LSb32HDRX_HDCP22_HMAC_SHA_CTRL_lc_trigger 1 |
| #define LSb16HDRX_HDCP22_HMAC_SHA_CTRL_lc_trigger 1 |
| #define bHDRX_HDCP22_HMAC_SHA_CTRL_lc_trigger 1 |
| #define MSK32HDRX_HDCP22_HMAC_SHA_CTRL_lc_trigger 0x00000002 |
| #define BA_HDRX_HDCP22_HMAC_SHA_CTRL_hmac_ctl 0x07DC |
| #define B16HDRX_HDCP22_HMAC_SHA_CTRL_hmac_ctl 0x07DC |
| #define LSb32HDRX_HDCP22_HMAC_SHA_CTRL_hmac_ctl 2 |
| #define LSb16HDRX_HDCP22_HMAC_SHA_CTRL_hmac_ctl 2 |
| #define bHDRX_HDCP22_HMAC_SHA_CTRL_hmac_ctl 1 |
| #define MSK32HDRX_HDCP22_HMAC_SHA_CTRL_hmac_ctl 0x00000004 |
| #define BA_HDRX_HDCP22_HMAC_SHA_CTRL_hmac_trigger 0x07DC |
| #define B16HDRX_HDCP22_HMAC_SHA_CTRL_hmac_trigger 0x07DC |
| #define LSb32HDRX_HDCP22_HMAC_SHA_CTRL_hmac_trigger 3 |
| #define LSb16HDRX_HDCP22_HMAC_SHA_CTRL_hmac_trigger 3 |
| #define bHDRX_HDCP22_HMAC_SHA_CTRL_hmac_trigger 1 |
| #define MSK32HDRX_HDCP22_HMAC_SHA_CTRL_hmac_trigger 0x00000008 |
| #define BA_HDRX_HDCP22_HMAC_SHA_CTRL_hw_pad 0x07DC |
| #define B16HDRX_HDCP22_HMAC_SHA_CTRL_hw_pad 0x07DC |
| #define LSb32HDRX_HDCP22_HMAC_SHA_CTRL_hw_pad 4 |
| #define LSb16HDRX_HDCP22_HMAC_SHA_CTRL_hw_pad 4 |
| #define bHDRX_HDCP22_HMAC_SHA_CTRL_hw_pad 1 |
| #define MSK32HDRX_HDCP22_HMAC_SHA_CTRL_hw_pad 0x00000010 |
| #define BA_HDRX_HDCP22_HMAC_SHA_CTRL_key_size 0x07DC |
| #define B16HDRX_HDCP22_HMAC_SHA_CTRL_key_size 0x07DC |
| #define LSb32HDRX_HDCP22_HMAC_SHA_CTRL_key_size 5 |
| #define LSb16HDRX_HDCP22_HMAC_SHA_CTRL_key_size 5 |
| #define bHDRX_HDCP22_HMAC_SHA_CTRL_key_size 7 |
| #define MSK32HDRX_HDCP22_HMAC_SHA_CTRL_key_size 0x00000FE0 |
| #define BA_HDRX_HDCP22_HMAC_SHA_CTRL_monitor_ctl_sel 0x07DD |
| #define B16HDRX_HDCP22_HMAC_SHA_CTRL_monitor_ctl_sel 0x07DC |
| #define LSb32HDRX_HDCP22_HMAC_SHA_CTRL_monitor_ctl_sel 12 |
| #define LSb16HDRX_HDCP22_HMAC_SHA_CTRL_monitor_ctl_sel 12 |
| #define bHDRX_HDCP22_HMAC_SHA_CTRL_monitor_ctl_sel 2 |
| #define MSK32HDRX_HDCP22_HMAC_SHA_CTRL_monitor_ctl_sel 0x00003000 |
| #define BA_HDRX_HDCP22_HMAC_SHA_CTRL_input_data_swp 0x07DD |
| #define B16HDRX_HDCP22_HMAC_SHA_CTRL_input_data_swp 0x07DC |
| #define LSb32HDRX_HDCP22_HMAC_SHA_CTRL_input_data_swp 14 |
| #define LSb16HDRX_HDCP22_HMAC_SHA_CTRL_input_data_swp 14 |
| #define bHDRX_HDCP22_HMAC_SHA_CTRL_input_data_swp 1 |
| #define MSK32HDRX_HDCP22_HMAC_SHA_CTRL_input_data_swp 0x00004000 |
| #define BA_HDRX_HDCP22_HMAC_SHA_CTRL_digest_swp 0x07DD |
| #define B16HDRX_HDCP22_HMAC_SHA_CTRL_digest_swp 0x07DC |
| #define LSb32HDRX_HDCP22_HMAC_SHA_CTRL_digest_swp 15 |
| #define LSb16HDRX_HDCP22_HMAC_SHA_CTRL_digest_swp 15 |
| #define bHDRX_HDCP22_HMAC_SHA_CTRL_digest_swp 1 |
| #define MSK32HDRX_HDCP22_HMAC_SHA_CTRL_digest_swp 0x00008000 |
| #define RA_HDRX_HDCP22_HMAC_SHA_CFG_ADDR 0x07E0 |
| #define BA_HDRX_HDCP22_HMAC_SHA_CFG_ADDR_cfg_addr 0x07E0 |
| #define B16HDRX_HDCP22_HMAC_SHA_CFG_ADDR_cfg_addr 0x07E0 |
| #define LSb32HDRX_HDCP22_HMAC_SHA_CFG_ADDR_cfg_addr 0 |
| #define LSb16HDRX_HDCP22_HMAC_SHA_CFG_ADDR_cfg_addr 0 |
| #define bHDRX_HDCP22_HMAC_SHA_CFG_ADDR_cfg_addr 6 |
| #define MSK32HDRX_HDCP22_HMAC_SHA_CFG_ADDR_cfg_addr 0x0000003F |
| #define RA_HDRX_HDCP22_HMAC_SHA_CFG_DATA 0x07E4 |
| #define BA_HDRX_HDCP22_HMAC_SHA_CFG_DATA_cfg_data 0x07E4 |
| #define B16HDRX_HDCP22_HMAC_SHA_CFG_DATA_cfg_data 0x07E4 |
| #define LSb32HDRX_HDCP22_HMAC_SHA_CFG_DATA_cfg_data 0 |
| #define LSb16HDRX_HDCP22_HMAC_SHA_CFG_DATA_cfg_data 0 |
| #define bHDRX_HDCP22_HMAC_SHA_CFG_DATA_cfg_data 32 |
| #define MSK32HDRX_HDCP22_HMAC_SHA_CFG_DATA_cfg_data 0xFFFFFFFF |
| #define RA_HDRX_HDCP22_HMAC_SHA_msg_len 0x07E8 |
| #define BA_HDRX_HDCP22_HMAC_SHA_msg_len_msg_len 0x07E8 |
| #define B16HDRX_HDCP22_HMAC_SHA_msg_len_msg_len 0x07E8 |
| #define LSb32HDRX_HDCP22_HMAC_SHA_msg_len_msg_len 0 |
| #define LSb16HDRX_HDCP22_HMAC_SHA_msg_len_msg_len 0 |
| #define bHDRX_HDCP22_HMAC_SHA_msg_len_msg_len 32 |
| #define MSK32HDRX_HDCP22_HMAC_SHA_msg_len_msg_len 0xFFFFFFFF |
| #define RA_HDRX_HDCP22_HMAC_SHA_seg_size 0x07EC |
| #define BA_HDRX_HDCP22_HMAC_SHA_seg_size_segment_size 0x07EC |
| #define B16HDRX_HDCP22_HMAC_SHA_seg_size_segment_size 0x07EC |
| #define LSb32HDRX_HDCP22_HMAC_SHA_seg_size_segment_size 0 |
| #define LSb16HDRX_HDCP22_HMAC_SHA_seg_size_segment_size 0 |
| #define bHDRX_HDCP22_HMAC_SHA_seg_size_segment_size 32 |
| #define MSK32HDRX_HDCP22_HMAC_SHA_seg_size_segment_size 0xFFFFFFFF |
| #define RA_HDRX_HDCP22_HMAC_SHA_data 0x07F0 |
| #define BA_HDRX_HDCP22_HMAC_SHA_data_idata 0x07F0 |
| #define B16HDRX_HDCP22_HMAC_SHA_data_idata 0x07F0 |
| #define LSb32HDRX_HDCP22_HMAC_SHA_data_idata 0 |
| #define LSb16HDRX_HDCP22_HMAC_SHA_data_idata 0 |
| #define bHDRX_HDCP22_HMAC_SHA_data_idata 32 |
| #define MSK32HDRX_HDCP22_HMAC_SHA_data_idata 0xFFFFFFFF |
| #define RA_HDRX_HDCP22_HMAC_SHA_status 0x07F4 |
| #define BA_HDRX_HDCP22_HMAC_SHA_status_digest_rdy 0x07F4 |
| #define B16HDRX_HDCP22_HMAC_SHA_status_digest_rdy 0x07F4 |
| #define LSb32HDRX_HDCP22_HMAC_SHA_status_digest_rdy 0 |
| #define LSb16HDRX_HDCP22_HMAC_SHA_status_digest_rdy 0 |
| #define bHDRX_HDCP22_HMAC_SHA_status_digest_rdy 1 |
| #define MSK32HDRX_HDCP22_HMAC_SHA_status_digest_rdy 0x00000001 |
| #define BA_HDRX_HDCP22_HMAC_SHA_status_sm_ready 0x07F4 |
| #define B16HDRX_HDCP22_HMAC_SHA_status_sm_ready 0x07F4 |
| #define LSb32HDRX_HDCP22_HMAC_SHA_status_sm_ready 1 |
| #define LSb16HDRX_HDCP22_HMAC_SHA_status_sm_ready 1 |
| #define bHDRX_HDCP22_HMAC_SHA_status_sm_ready 1 |
| #define MSK32HDRX_HDCP22_HMAC_SHA_status_sm_ready 0x00000002 |
| #define BA_HDRX_HDCP22_HMAC_SHA_status_hash_normal_sm_busy 0x07F4 |
| #define B16HDRX_HDCP22_HMAC_SHA_status_hash_normal_sm_busy 0x07F4 |
| #define LSb32HDRX_HDCP22_HMAC_SHA_status_hash_normal_sm_busy 2 |
| #define LSb16HDRX_HDCP22_HMAC_SHA_status_hash_normal_sm_busy 2 |
| #define bHDRX_HDCP22_HMAC_SHA_status_hash_normal_sm_busy 1 |
| #define MSK32HDRX_HDCP22_HMAC_SHA_status_hash_normal_sm_busy 0x00000004 |
| #define BA_HDRX_HDCP22_HMAC_SHA_status_sm_busy 0x07F4 |
| #define B16HDRX_HDCP22_HMAC_SHA_status_sm_busy 0x07F4 |
| #define LSb32HDRX_HDCP22_HMAC_SHA_status_sm_busy 3 |
| #define LSb16HDRX_HDCP22_HMAC_SHA_status_sm_busy 3 |
| #define bHDRX_HDCP22_HMAC_SHA_status_sm_busy 1 |
| #define MSK32HDRX_HDCP22_HMAC_SHA_status_sm_busy 0x00000008 |
| #define BA_HDRX_HDCP22_HMAC_SHA_status_xfer_sm_busy 0x07F4 |
| #define B16HDRX_HDCP22_HMAC_SHA_status_xfer_sm_busy 0x07F4 |
| #define LSb32HDRX_HDCP22_HMAC_SHA_status_xfer_sm_busy 4 |
| #define LSb16HDRX_HDCP22_HMAC_SHA_status_xfer_sm_busy 4 |
| #define bHDRX_HDCP22_HMAC_SHA_status_xfer_sm_busy 1 |
| #define MSK32HDRX_HDCP22_HMAC_SHA_status_xfer_sm_busy 0x00000010 |
| #define BA_HDRX_HDCP22_HMAC_SHA_status_hash_busy 0x07F4 |
| #define B16HDRX_HDCP22_HMAC_SHA_status_hash_busy 0x07F4 |
| #define LSb32HDRX_HDCP22_HMAC_SHA_status_hash_busy 5 |
| #define LSb16HDRX_HDCP22_HMAC_SHA_status_hash_busy 5 |
| #define bHDRX_HDCP22_HMAC_SHA_status_hash_busy 1 |
| #define MSK32HDRX_HDCP22_HMAC_SHA_status_hash_busy 0x00000020 |
| #define BA_HDRX_HDCP22_HMAC_SHA_status_hash_done_status 0x07F4 |
| #define B16HDRX_HDCP22_HMAC_SHA_status_hash_done_status 0x07F4 |
| #define LSb32HDRX_HDCP22_HMAC_SHA_status_hash_done_status 6 |
| #define LSb16HDRX_HDCP22_HMAC_SHA_status_hash_done_status 6 |
| #define bHDRX_HDCP22_HMAC_SHA_status_hash_done_status 1 |
| #define MSK32HDRX_HDCP22_HMAC_SHA_status_hash_done_status 0x00000040 |
| #define BA_HDRX_HDCP22_HMAC_SHA_status_hmac_sha_test_mux_out 0x07F4 |
| #define B16HDRX_HDCP22_HMAC_SHA_status_hmac_sha_test_mux_out 0x07F4 |
| #define LSb32HDRX_HDCP22_HMAC_SHA_status_hmac_sha_test_mux_out 7 |
| #define LSb16HDRX_HDCP22_HMAC_SHA_status_hmac_sha_test_mux_out 7 |
| #define bHDRX_HDCP22_HMAC_SHA_status_hmac_sha_test_mux_out 16 |
| #define MSK32HDRX_HDCP22_HMAC_SHA_status_hmac_sha_test_mux_out 0x007FFF80 |
| #define RA_HDRX_HDCP22_HMAC_digestA 0x07F8 |
| #define BA_HDRX_HDCP22_HMAC_digestA_digest 0x07F8 |
| #define B16HDRX_HDCP22_HMAC_digestA_digest 0x07F8 |
| #define LSb32HDRX_HDCP22_HMAC_digestA_digest 0 |
| #define LSb16HDRX_HDCP22_HMAC_digestA_digest 0 |
| #define bHDRX_HDCP22_HMAC_digestA_digest 32 |
| #define MSK32HDRX_HDCP22_HMAC_digestA_digest 0xFFFFFFFF |
| #define RA_HDRX_HDCP22_HMAC_digestB 0x07FC |
| #define BA_HDRX_HDCP22_HMAC_digestB_digest 0x07FC |
| #define B16HDRX_HDCP22_HMAC_digestB_digest 0x07FC |
| #define LSb32HDRX_HDCP22_HMAC_digestB_digest 0 |
| #define LSb16HDRX_HDCP22_HMAC_digestB_digest 0 |
| #define bHDRX_HDCP22_HMAC_digestB_digest 32 |
| #define MSK32HDRX_HDCP22_HMAC_digestB_digest 0xFFFFFFFF |
| #define RA_HDRX_HDCP22_HMAC_digestC 0x0800 |
| #define BA_HDRX_HDCP22_HMAC_digestC_digest 0x0800 |
| #define B16HDRX_HDCP22_HMAC_digestC_digest 0x0800 |
| #define LSb32HDRX_HDCP22_HMAC_digestC_digest 0 |
| #define LSb16HDRX_HDCP22_HMAC_digestC_digest 0 |
| #define bHDRX_HDCP22_HMAC_digestC_digest 32 |
| #define MSK32HDRX_HDCP22_HMAC_digestC_digest 0xFFFFFFFF |
| #define RA_HDRX_HDCP22_HMAC_digestD 0x0804 |
| #define BA_HDRX_HDCP22_HMAC_digestD_digest 0x0804 |
| #define B16HDRX_HDCP22_HMAC_digestD_digest 0x0804 |
| #define LSb32HDRX_HDCP22_HMAC_digestD_digest 0 |
| #define LSb16HDRX_HDCP22_HMAC_digestD_digest 0 |
| #define bHDRX_HDCP22_HMAC_digestD_digest 32 |
| #define MSK32HDRX_HDCP22_HMAC_digestD_digest 0xFFFFFFFF |
| #define RA_HDRX_HDCP22_HMAC_digestE 0x0808 |
| #define BA_HDRX_HDCP22_HMAC_digestE_digest 0x0808 |
| #define B16HDRX_HDCP22_HMAC_digestE_digest 0x0808 |
| #define LSb32HDRX_HDCP22_HMAC_digestE_digest 0 |
| #define LSb16HDRX_HDCP22_HMAC_digestE_digest 0 |
| #define bHDRX_HDCP22_HMAC_digestE_digest 32 |
| #define MSK32HDRX_HDCP22_HMAC_digestE_digest 0xFFFFFFFF |
| #define RA_HDRX_HDCP22_HMAC_digestF 0x080C |
| #define BA_HDRX_HDCP22_HMAC_digestF_digest 0x080C |
| #define B16HDRX_HDCP22_HMAC_digestF_digest 0x080C |
| #define LSb32HDRX_HDCP22_HMAC_digestF_digest 0 |
| #define LSb16HDRX_HDCP22_HMAC_digestF_digest 0 |
| #define bHDRX_HDCP22_HMAC_digestF_digest 32 |
| #define MSK32HDRX_HDCP22_HMAC_digestF_digest 0xFFFFFFFF |
| #define RA_HDRX_HDCP22_HMAC_digestG 0x0810 |
| #define BA_HDRX_HDCP22_HMAC_digestG_digest 0x0810 |
| #define B16HDRX_HDCP22_HMAC_digestG_digest 0x0810 |
| #define LSb32HDRX_HDCP22_HMAC_digestG_digest 0 |
| #define LSb16HDRX_HDCP22_HMAC_digestG_digest 0 |
| #define bHDRX_HDCP22_HMAC_digestG_digest 32 |
| #define MSK32HDRX_HDCP22_HMAC_digestG_digest 0xFFFFFFFF |
| #define RA_HDRX_HDCP22_HMAC_digestH 0x0814 |
| #define BA_HDRX_HDCP22_HMAC_digestH_digest 0x0814 |
| #define B16HDRX_HDCP22_HMAC_digestH_digest 0x0814 |
| #define LSb32HDRX_HDCP22_HMAC_digestH_digest 0 |
| #define LSb16HDRX_HDCP22_HMAC_digestH_digest 0 |
| #define bHDRX_HDCP22_HMAC_digestH_digest 32 |
| #define MSK32HDRX_HDCP22_HMAC_digestH_digest 0xFFFFFFFF |
| #define RA_HDRX_CLK_RST_CTRL 0x0818 |
| #define BA_HDRX_CLK_RST_CTRL_pclk_sw_rst_l 0x0818 |
| #define B16HDRX_CLK_RST_CTRL_pclk_sw_rst_l 0x0818 |
| #define LSb32HDRX_CLK_RST_CTRL_pclk_sw_rst_l 0 |
| #define LSb16HDRX_CLK_RST_CTRL_pclk_sw_rst_l 0 |
| #define bHDRX_CLK_RST_CTRL_pclk_sw_rst_l 1 |
| #define MSK32HDRX_CLK_RST_CTRL_pclk_sw_rst_l 0x00000001 |
| #define BA_HDRX_CLK_RST_CTRL_tclk_sw_rst_l 0x0818 |
| #define B16HDRX_CLK_RST_CTRL_tclk_sw_rst_l 0x0818 |
| #define LSb32HDRX_CLK_RST_CTRL_tclk_sw_rst_l 1 |
| #define LSb16HDRX_CLK_RST_CTRL_tclk_sw_rst_l 1 |
| #define bHDRX_CLK_RST_CTRL_tclk_sw_rst_l 1 |
| #define MSK32HDRX_CLK_RST_CTRL_tclk_sw_rst_l 0x00000002 |
| #define BA_HDRX_CLK_RST_CTRL_dc_clk_sw_rst_l 0x0818 |
| #define B16HDRX_CLK_RST_CTRL_dc_clk_sw_rst_l 0x0818 |
| #define LSb32HDRX_CLK_RST_CTRL_dc_clk_sw_rst_l 2 |
| #define LSb16HDRX_CLK_RST_CTRL_dc_clk_sw_rst_l 2 |
| #define bHDRX_CLK_RST_CTRL_dc_clk_sw_rst_l 1 |
| #define MSK32HDRX_CLK_RST_CTRL_dc_clk_sw_rst_l 0x00000004 |
| #define BA_HDRX_CLK_RST_CTRL_mclk_sw_rst_l 0x0818 |
| #define B16HDRX_CLK_RST_CTRL_mclk_sw_rst_l 0x0818 |
| #define LSb32HDRX_CLK_RST_CTRL_mclk_sw_rst_l 3 |
| #define LSb16HDRX_CLK_RST_CTRL_mclk_sw_rst_l 3 |
| #define bHDRX_CLK_RST_CTRL_mclk_sw_rst_l 1 |
| #define MSK32HDRX_CLK_RST_CTRL_mclk_sw_rst_l 0x00000008 |
| #define BA_HDRX_CLK_RST_CTRL_ref_clk_sw_rst_l 0x0818 |
| #define B16HDRX_CLK_RST_CTRL_ref_clk_sw_rst_l 0x0818 |
| #define LSb32HDRX_CLK_RST_CTRL_ref_clk_sw_rst_l 4 |
| #define LSb16HDRX_CLK_RST_CTRL_ref_clk_sw_rst_l 4 |
| #define bHDRX_CLK_RST_CTRL_ref_clk_sw_rst_l 1 |
| #define MSK32HDRX_CLK_RST_CTRL_ref_clk_sw_rst_l 0x00000010 |
| #define BA_HDRX_CLK_RST_CTRL_mhl_3xck_sw_rst_l 0x0818 |
| #define B16HDRX_CLK_RST_CTRL_mhl_3xck_sw_rst_l 0x0818 |
| #define LSb32HDRX_CLK_RST_CTRL_mhl_3xck_sw_rst_l 5 |
| #define LSb16HDRX_CLK_RST_CTRL_mhl_3xck_sw_rst_l 5 |
| #define bHDRX_CLK_RST_CTRL_mhl_3xck_sw_rst_l 1 |
| #define MSK32HDRX_CLK_RST_CTRL_mhl_3xck_sw_rst_l 0x00000020 |
| #define BA_HDRX_CLK_RST_CTRL_phy_mon_tclk_sw_rst_l 0x0818 |
| #define B16HDRX_CLK_RST_CTRL_phy_mon_tclk_sw_rst_l 0x0818 |
| #define LSb32HDRX_CLK_RST_CTRL_phy_mon_tclk_sw_rst_l 6 |
| #define LSb16HDRX_CLK_RST_CTRL_phy_mon_tclk_sw_rst_l 6 |
| #define bHDRX_CLK_RST_CTRL_phy_mon_tclk_sw_rst_l 1 |
| #define MSK32HDRX_CLK_RST_CTRL_phy_mon_tclk_sw_rst_l 0x00000040 |
| #define BA_HDRX_CLK_RST_CTRL_phy_chn1_tclk10_sw_rst_l 0x0818 |
| #define B16HDRX_CLK_RST_CTRL_phy_chn1_tclk10_sw_rst_l 0x0818 |
| #define LSb32HDRX_CLK_RST_CTRL_phy_chn1_tclk10_sw_rst_l 7 |
| #define LSb16HDRX_CLK_RST_CTRL_phy_chn1_tclk10_sw_rst_l 7 |
| #define bHDRX_CLK_RST_CTRL_phy_chn1_tclk10_sw_rst_l 1 |
| #define MSK32HDRX_CLK_RST_CTRL_phy_chn1_tclk10_sw_rst_l 0x00000080 |
| #define BA_HDRX_CLK_RST_CTRL_phy_chn2_tclk10_sw_rst_l 0x0819 |
| #define B16HDRX_CLK_RST_CTRL_phy_chn2_tclk10_sw_rst_l 0x0818 |
| #define LSb32HDRX_CLK_RST_CTRL_phy_chn2_tclk10_sw_rst_l 8 |
| #define LSb16HDRX_CLK_RST_CTRL_phy_chn2_tclk10_sw_rst_l 8 |
| #define bHDRX_CLK_RST_CTRL_phy_chn2_tclk10_sw_rst_l 1 |
| #define MSK32HDRX_CLK_RST_CTRL_phy_chn2_tclk10_sw_rst_l 0x00000100 |
| #define BA_HDRX_CLK_RST_CTRL_LB_CLK_sw_rst_l 0x0819 |
| #define B16HDRX_CLK_RST_CTRL_LB_CLK_sw_rst_l 0x0818 |
| #define LSb32HDRX_CLK_RST_CTRL_LB_CLK_sw_rst_l 9 |
| #define LSb16HDRX_CLK_RST_CTRL_LB_CLK_sw_rst_l 9 |
| #define bHDRX_CLK_RST_CTRL_LB_CLK_sw_rst_l 1 |
| #define MSK32HDRX_CLK_RST_CTRL_LB_CLK_sw_rst_l 0x00000200 |
| #define RA_HDRX_FPLL_CTRL1 0x081C |
| #define BA_HDRX_FPLL_CTRL1_ctrl 0x081C |
| #define B16HDRX_FPLL_CTRL1_ctrl 0x081C |
| #define LSb32HDRX_FPLL_CTRL1_ctrl 0 |
| #define LSb16HDRX_FPLL_CTRL1_ctrl 0 |
| #define bHDRX_FPLL_CTRL1_ctrl 8 |
| #define MSK32HDRX_FPLL_CTRL1_ctrl 0x000000FF |
| #define BA_HDRX_FPLL_CTRL1_sw_rst 0x081D |
| #define B16HDRX_FPLL_CTRL1_sw_rst 0x081C |
| #define LSb32HDRX_FPLL_CTRL1_sw_rst 8 |
| #define LSb16HDRX_FPLL_CTRL1_sw_rst 8 |
| #define bHDRX_FPLL_CTRL1_sw_rst 1 |
| #define MSK32HDRX_FPLL_CTRL1_sw_rst 0x00000100 |
| #define BA_HDRX_FPLL_CTRL1_gain 0x081D |
| #define B16HDRX_FPLL_CTRL1_gain 0x081C |
| #define LSb32HDRX_FPLL_CTRL1_gain 9 |
| #define LSb16HDRX_FPLL_CTRL1_gain 9 |
| #define bHDRX_FPLL_CTRL1_gain 6 |
| #define MSK32HDRX_FPLL_CTRL1_gain 0x00007E00 |
| #define BA_HDRX_FPLL_CTRL1_res 0x081D |
| #define B16HDRX_FPLL_CTRL1_res 0x081C |
| #define LSb32HDRX_FPLL_CTRL1_res 15 |
| #define LSb16HDRX_FPLL_CTRL1_res 15 |
| #define bHDRX_FPLL_CTRL1_res 3 |
| #define MSK32HDRX_FPLL_CTRL1_res 0x00038000 |
| #define RA_HDRX_FPLL_CTRL2 0x0820 |
| #define BA_HDRX_FPLL_CTRL2_ph_off 0x0820 |
| #define B16HDRX_FPLL_CTRL2_ph_off 0x0820 |
| #define LSb32HDRX_FPLL_CTRL2_ph_off 0 |
| #define LSb16HDRX_FPLL_CTRL2_ph_off 0 |
| #define bHDRX_FPLL_CTRL2_ph_off 8 |
| #define MSK32HDRX_FPLL_CTRL2_ph_off 0x000000FF |
| #define BA_HDRX_FPLL_CTRL2_thresh0 0x0821 |
| #define B16HDRX_FPLL_CTRL2_thresh0 0x0820 |
| #define LSb32HDRX_FPLL_CTRL2_thresh0 8 |
| #define LSb16HDRX_FPLL_CTRL2_thresh0 8 |
| #define bHDRX_FPLL_CTRL2_thresh0 8 |
| #define MSK32HDRX_FPLL_CTRL2_thresh0 0x0000FF00 |
| #define BA_HDRX_FPLL_CTRL2_thresh1 0x0822 |
| #define B16HDRX_FPLL_CTRL2_thresh1 0x0822 |
| #define LSb32HDRX_FPLL_CTRL2_thresh1 16 |
| #define LSb16HDRX_FPLL_CTRL2_thresh1 0 |
| #define bHDRX_FPLL_CTRL2_thresh1 8 |
| #define MSK32HDRX_FPLL_CTRL2_thresh1 0x00FF0000 |
| #define RA_HDRX_FPLL_CTRL3 0x0824 |
| #define BA_HDRX_FPLL_CTRL3_W 0x0824 |
| #define B16HDRX_FPLL_CTRL3_W 0x0824 |
| #define LSb32HDRX_FPLL_CTRL3_W 0 |
| #define LSb16HDRX_FPLL_CTRL3_W 0 |
| #define bHDRX_FPLL_CTRL3_W 29 |
| #define MSK32HDRX_FPLL_CTRL3_W 0x1FFFFFFF |
| #define RA_HDRX_MEM_CTRL 0x0828 |
| #define BA_HDRX_MEM_CTRL_RF_1P_cen 0x0828 |
| #define B16HDRX_MEM_CTRL_RF_1P_cen 0x0828 |
| #define LSb32HDRX_MEM_CTRL_RF_1P_cen 0 |
| #define LSb16HDRX_MEM_CTRL_RF_1P_cen 0 |
| #define bHDRX_MEM_CTRL_RF_1P_cen 2 |
| #define MSK32HDRX_MEM_CTRL_RF_1P_cen 0x00000003 |
| |
| #define w32HDRX_PHY_CLK_CTRL {\ |
| UNSG32 uPHY_CLK_CTRL_rt_en_c : 1;\ |
| UNSG32 uPHY_CLK_CTRL_polswap_rx_c : 1;\ |
| UNSG32 uPHY_CLK_CTRL_chn0_clkg_enb : 1;\ |
| UNSG32 uPHY_CLK_CTRL_testck_sel : 2;\ |
| UNSG32 RSVDx4A4_b5 : 27;\ |
| } |
| |
| #define w32HDRX_PHY_PM {\ |
| UNSG32 uPHY_PM_pd_rxck : 1;\ |
| UNSG32 uPHY_PM_syn_ck2rx : 1;\ |
| UNSG32 uPHY_PM_pd_comm : 1;\ |
| UNSG32 uPHY_PM_pd_pll : 1;\ |
| UNSG32 uPHY_PM_pd_cdr : 1;\ |
| UNSG32 uPHY_PM_pd_frt_c : 1;\ |
| UNSG32 uPHY_PM_pd_frt_d : 1;\ |
| UNSG32 uPHY_PM_reset_rx : 1;\ |
| UNSG32 uPHY_PM_reset_pll : 1;\ |
| UNSG32 RSVDx4D4_b9 : 23;\ |
| } |
| |
| #define w32HDRX_ARC_TX_CTRL {\ |
| UNSG32 uARC_TX_CTRL_en : 1;\ |
| UNSG32 uARC_TX_CTRL_pd : 1;\ |
| UNSG32 uARC_TX_CTRL_amp : 2;\ |
| UNSG32 uARC_TX_CTRL_pull_ud : 2;\ |
| UNSG32 uARC_TX_CTRL_trf : 2;\ |
| UNSG32 RSVDx4D8_b8 : 24;\ |
| } |
| |
| typedef union T32HDRX_PHY_CLK_CTRL |
| { UNSG32 u32; |
| struct w32HDRX_PHY_CLK_CTRL; |
| } T32HDRX_PHY_CLK_CTRL; |
| |
| typedef union T32HDRX_PHY_PM |
| { UNSG32 u32; |
| struct w32HDRX_PHY_PM; |
| } T32HDRX_PHY_PM; |
| |
| typedef union T32HDRX_ARC_TX_CTRL |
| { UNSG32 u32; |
| struct w32HDRX_ARC_TX_CTRL; |
| } T32HDRX_ARC_TX_CTRL; |
| #endif |
| |
