| #ifndef MC6_DEFINES_H | |
| #define MC6_DEFINES_H | |
| // updated based on mc6c_reg_bg5ctpz1.html | |
| #define MC6_MC_ID 0x0000 | |
| #define MC6_MC_STATUS_CH0 0x0004 | |
| #define MC6_DRAM_STATUS 0x0008 | |
| #define MC6_DRAM_MODE 0x000C | |
| #define MC6_MC_STATUS_CH1 0x0010 | |
| #define MC6_USER_COMMAND_0 0x0020 | |
| #define MC6_USER_COMMAND_1 0x0024 | |
| #define MC6_USER_COMMAND_2 0x0028 | |
| #define MC6_SRAM_control 0x0040 | |
| #define MC6_MC_Control_0 0x0044 | |
| #define MC6_Exclusive_Monitor 0x0048 | |
| #define MC6_RAS_Control 0x004C | |
| #define MC6_Spool_Control 0x0050 | |
| #define MC6_MC_pwr_ctl 0x0054 | |
| #define MC6_WB_Control 0x0058 | |
| #define MC6_Cat_Priority_ctl 0x005C | |
| #define MC6_ROB_Control 0x0060 | |
| #define MC6_RDP_Control 0x0064 | |
| #define MC6_AXI_Port_Control 0x0068 | |
| #define MC6_RegTable_Control 0x0070 | |
| #define MC6_RegTable_Data_0 0x0074 | |
| #define MC6_RegTable_Data_1 0x0078 | |
| #define MC6_RZ_access_ctl 0x007C | |
| #define MC6_TZ_Range0_Low 0x0080 | |
| #define MC6_TZ_Range0_High 0x0084 | |
| #define MC6_TZ_Range1_Low 0x0088 | |
| #define MC6_TZ_Range1_High 0x008C | |
| #define MC6_TZ_Range2_Low 0x0090 | |
| #define MC6_TZ_Range2_High 0x0094 | |
| #define MC6_TZ_Range3_Low 0x0098 | |
| #define MC6_TZ_Range3_High 0x009C | |
| #define MC6_TZ_Range4_Low 0x00A0 | |
| #define MC6_TZ_Range4_High 0x00A4 | |
| #define MC6_TZ_Range5_Low 0x00A8 | |
| #define MC6_TZ_Range5_High 0x00AC | |
| #define MC6_TZ_Range6_Low 0x00B0 | |
| #define MC6_TZ_Range6_High 0x00B4 | |
| #define MC6_TZ_Range7_Low 0x00B8 | |
| #define MC6_TZ_Range7_High 0x00BC | |
| #define MC6_TZ_Range8_Low 0x00C0 | |
| #define MC6_TZ_Range8_High 0x00C4 | |
| #define MC6_TZ_Range9_Low 0x00C8 | |
| #define MC6_TZ_Range9_High 0x00CC | |
| #define MC6_TZ_Range10_Low 0x00D0 | |
| #define MC6_TZ_Range10_High 0x00D4 | |
| #define MC6_TZ_Range11_Low 0x00D8 | |
| #define MC6_TZ_Range11_High 0x00DC | |
| #define MC6_TZ_Range12_Low 0x00E0 | |
| #define MC6_TZ_Range12_High 0x00E4 | |
| #define MC6_TZ_Range13_Low 0x00E8 | |
| #define MC6_TZ_Range13_High 0x00EC | |
| #define MC6_TZ_Range14_Low 0x00F0 | |
| #define MC6_TZ_Range14_High 0x00F4 | |
| #define MC6_TZ_Range15_Low 0x00F8 | |
| #define MC6_TZ_Range15_High 0x00FC | |
| #define MC6_PC_config0 0x0100 | |
| #define MC6_PC_config1 0x0104 | |
| #define MC6_PC_status 0x0108 | |
| #define MC6_PC_Control 0x010C | |
| #define MC6_PC0 0x0110 | |
| #define MC6_PC1 0x0114 | |
| #define MC6_PC2 0x0118 | |
| #define MC6_PC3 0x011C | |
| #define MC6_PC4 0x0120 | |
| #define MC6_PC5 0x0124 | |
| #define MC6_PC6 0x0128 | |
| #define MC6_PC7 0x012C | |
| #define MC6_ISR 0x0140 | |
| #define MC6_IER 0x0144 | |
| #define MC6_ADC_ERR_ID 0x0150 | |
| #define MC6_ADC_ERR_ADR_L 0x0154 | |
| #define MC6_ADC_ERR_ADR_H 0x0158 | |
| #define MC6_AM_PERIOD 0x0160 | |
| #define MC6_AM_TH 0x0164 | |
| #define MC6_AM2_PERIOD 0x0170 | |
| #define MC6_AM2_LOW_TH 0x0174 | |
| #define MC6_AM2_HIGH_TH 0x0178 | |
| #define MC6_AM2_Busy_Cycle 0x017C | |
| #define MC6_RPP_Starvation_Control 0x0180 | |
| #define MC6_BW_allocation_tc_window0 0x0184 | |
| #define MC6_BW_allocation_tc_window1 0x0188 | |
| #define MC6_BW_allocation_tc_window2 0x018C | |
| #define MC6_BW_allocation_tc_window3 0x0190 | |
| #define MC6_BW_allocation_tc_window4 0x0194 | |
| #define MC6_BW_allocation_tc_window5 0x0198 | |
| #define MC6_BW_allocation_tc_window6 0x019C | |
| #define MC6_BW_allocation_tc_window7 0x01A0 | |
| #define MC6_BW_allocation_tc_window8 0x01A4 | |
| #define MC6_BW_allocation_tc_window9 0x01A8 | |
| #define MC6_BW_allocation_tc_window10 0x01AC | |
| #define MC6_BW_allocation_tc_window11 0x01B0 | |
| #define MC6_BW_allocation_tc_window12 0x01B4 | |
| #define MC6_BW_allocation_tc_window13 0x01B8 | |
| #define MC6_BW_allocation_tc_window14 0x01BC | |
| #define MC6_BW_allocation_tc_window15 0x01C0 | |
| #define MC6_Cat_Priority_ctl_ddr4 0x01C4 | |
| #define MC6_TRR_Control 0x01C8 | |
| #define MC6_MMAP0_Low_CH0 0x0200 | |
| #define MC6_MMAP0_High_CH0 0x0204 | |
| #define MC6_MMAP1_Low_CH0 0x0208 | |
| #define MC6_MMAP1_High_CH0 0x020C | |
| #define MC6_CH0_MC_CONFIG_CS0 0x0220 | |
| #define MC6_CH0_MC_CONFIG_CS1 0x0224 | |
| #define MC6_CH0_MRR_Data_1 0x0230 | |
| #define MC6_CH0_MRR_Data_2 0x0234 | |
| #define MC6_CH0_MRR_Data_3 0x0238 | |
| #define MC6_CH0_MRR_Data_4 0x023C | |
| #define MC6_CH0_MRR_Data_5 0x0240 | |
| #define MC6_CH0_MRR_Data_6 0x0244 | |
| #define MC6_CH0_MRR_Data_7 0x0248 | |
| #define MC6_CH0_MC_Control_1 0x02C0 | |
| #define MC6_CH0_MC_Control_2 0x02C4 | |
| #define MC6_CH0_MC_Control_3 0x02C8 | |
| #define MC6_CH0_MC_Control_4 0x02CC | |
| #define MC6_CH0_MC_Control_5 0x02D0 | |
| #define MC6_CH0_DRAM_Config_1 0x0300 | |
| #define MC6_CH0_DRAM_Config_2 0x0304 | |
| #define MC6_CH0_DRAM_Config_3 0x0308 | |
| #define MC6_CH0_DRAM_Config_4 0x030C | |
| #define MC6_CH0_DRAM_Config_5_CS0 0x0310 | |
| #define MC6_CH0_DRAM_Config_5_CS1 0x0314 | |
| #define MC6_CH0_DRAM_Config_6 0x0320 | |
| #define MC6_CH0_ODT_Control_0 0x0340 | |
| #define MC6_CH0_ODT_Control_1 0x0344 | |
| #define MC6_CH0_ODT_Control_2 0x0348 | |
| #define MC6_CH0_ODT_Control_3 0x034C | |
| #define MC6_CH0_MRR_Data 0x0370 | |
| #define MC6_CH0_MPR_Data 0x0374 | |
| #define MC6_CH0_DDR_init_timing_control_0 0x0380 | |
| #define MC6_CH0_DDR_init_timing_control_1 0x0384 | |
| #define MC6_CH0_DDR_init_timing_control_2 0x0388 | |
| #define MC6_CH0_ZQC_Timing_0 0x038C | |
| #define MC6_CH0_ZQC_Timing_1 0x0390 | |
| #define MC6_CH0_Refresh_timing 0x0394 | |
| #define MC6_CH0_SelfRefresh_timing_0 0x0398 | |
| #define MC6_CH0_SelfRefresh_timing_1 0x039C | |
| #define MC6_CH0_PowerDown_timing_0 0x03A0 | |
| #define MC6_CH0_PowerDown_timing_1 0x03A4 | |
| #define MC6_CH0_MRS_timing 0x03A8 | |
| #define MC6_CH0_ACT_timing 0x03AC | |
| #define MC6_CH0_PreCharge_Timing 0x03B0 | |
| #define MC6_CH0_CAS_RAS_timing_0 0x03B4 | |
| #define MC6_CH0_CAS_RAS_timing_1 0x03B8 | |
| #define MC6_CH0_Off_spec_timing_0 0x03BC | |
| #define MC6_CH0_Off_spec_timing_1 0x03C0 | |
| #define MC6_CH0_dram_read_timing 0x03C4 | |
| #define MC6_CH0_dram_ca_train_timing 0x03C8 | |
| #define MC6_CH0_dram_mpd_timing 0x03CC | |
| #define MC6_CH0_dram_pda_timing 0x03D0 | |
| #define MC6_CH0_crc_par_timing 0x03D4 | |
| #define MC6_CH0_dram_training_timing 0x03D8 | |
| #define MC6_CH0_stack_chip_timing 0x03F8 | |
| #define MC6_MMAP0_Low_CH1 0x0400 | |
| #define MC6_MMAP0_High_CH1 0x0404 | |
| #define MC6_MMAP1_Low_CH1 0x0408 | |
| #define MC6_MMAP1_High_CH1 0x040C | |
| #define MC6_CH1_MC_CONFIG_CS0 0x0420 | |
| #define MC6_CH1_MC_CONFIG_CS1 0x0424 | |
| #define MC6_CH1_MRR_Data_1 0x0430 | |
| #define MC6_CH1_MRR_Data_2 0x0434 | |
| #define MC6_CH1_MRR_Data_3 0x0438 | |
| #define MC6_CH1_MRR_Data_4 0x043C | |
| #define MC6_CH1_MRR_Data_5 0x0440 | |
| #define MC6_CH1_MRR_Data_6 0x0444 | |
| #define MC6_CH1_MRR_Data_7 0x0448 | |
| #define MC6_CH1_MC_Control_1 0x04C0 | |
| #define MC6_CH1_MC_Control_2 0x04C4 | |
| #define MC6_CH1_MC_Control_3 0x04C8 | |
| #define MC6_CH1_MC_Control_4 0x04CC | |
| #define MC6_CH1_MC_Control_5 0x04D0 | |
| #define MC6_CH1_DRAM_Config_1 0x0500 | |
| #define MC6_CH1_DRAM_Config_2 0x0504 | |
| #define MC6_CH1_DRAM_Config_3 0x0508 | |
| #define MC6_CH1_DRAM_Config_4 0x050C | |
| #define MC6_CH1_DRAM_Config_5_CS0 0x0510 | |
| #define MC6_CH1_DRAM_Config_5_CS1 0x0514 | |
| #define MC6_CH1_DRAM_Config_6 0x0520 | |
| #define MC6_CH1_ODT_Control_0 0x0540 | |
| #define MC6_CH1_ODT_Control_1 0x0544 | |
| #define MC6_CH1_ODT_Control_2 0x0548 | |
| #define MC6_CH1_ODT_Control_3 0x054C | |
| #define MC6_CH1_MRR_Data 0x0570 | |
| #define MC6_CH1_MPR_Data 0x0574 | |
| #define MC6_CH1_DDR_init_timing_control_0 0x0580 | |
| #define MC6_CH1_DDR_init_timing_control_1 0x0584 | |
| #define MC6_CH1_DDR_init_timing_control_2 0x0588 | |
| #define MC6_CH1_ZQC_Timing_0 0x058C | |
| #define MC6_CH1_ZQC_Timing_1 0x0590 | |
| #define MC6_CH1_Refresh_timing 0x0594 | |
| #define MC6_CH1_SelfRefresh_timing_0 0x0598 | |
| #define MC6_CH1_SelfRefresh_timing_1 0x059C | |
| #define MC6_CH1_PowerDown_timing_0 0x05A0 | |
| #define MC6_CH1_PowerDown_timing_1 0x05A4 | |
| #define MC6_CH1_MRS_timing 0x05A8 | |
| #define MC6_CH1_ACT_timing 0x05AC | |
| #define MC6_CH1_PreCharge_Timing 0x05B0 | |
| #define MC6_CH1_CAS_RAS_timing_0 0x05B4 | |
| #define MC6_CH1_CAS_RAS_timing_1 0x05B8 | |
| #define MC6_CH1_Off_spec_timing_0 0x05BC | |
| #define MC6_CH1_Off_spec_timing_1 0x05C0 | |
| #define MC6_CH1_dram_read_timing 0x05C4 | |
| #define MC6_CH1_dram_ca_train_timing 0x05C8 | |
| #define MC6_CH1_dram_mpd_timing 0x05CC | |
| #define MC6_CH1_dram_pda_timing 0x05D0 | |
| #define MC6_CH1_crc_par_timing 0x05D4 | |
| #define MC6_CH1_dram_training_timing 0x05D8 | |
| #define MC6_CH1_stack_chip_timing 0x05F8 | |
| #define MC6_Test_Control 0x0A50 | |
| #define MC6_User_Trigger_IR 0x0A60 | |
| #define MC6_Training_Control 0x0A6C | |
| #define MC6_Training_Pattern0 0x0A70 | |
| #define MC6_Training_Pattern1 0x0A74 | |
| #define MC6_Training_Pattern2 0x0A78 | |
| #define MC6_Training_Pattern3 0x0A7C | |
| #define MC6_Training_Pattern4 0x0A80 | |
| #define MC6_Training_Pattern5 0x0A84 | |
| #define MC6_Training_Pattern6 0x0A88 | |
| #define MC6_Training_Pattern7 0x0A8C | |
| #define MC6_DMI_Training_Pattern 0x0A90 | |
| #define MC6_DFI_PHY_USER_COMMAND_0 0x13D0 | |
| #define MC6_CH0_DFI_PHY_Control_0 0x13E0 | |
| #define MC6_CH0_DFI_PHY_Control_1 0x13E4 | |
| #define MC6_CH0_DFI_PHY_Control_2 0x13E8 | |
| #define MC6_CH0_DFI_PHY_Control_3 0x13EC | |
| #define MC6_CH0_DFI_PHY_CA_Train 0x13F0 | |
| #define MC6_CH0_DFI_PHY_CA_Pattern 0x13F4 | |
| #define MC6_CH0_DFI_PHY_Write_DQ_Train 0x13F8 | |
| #define MC6_CH0_DFI_PHY_Leveling_Status 0x13FC | |
| #define MC6_CH1_DFI_PHY_Control_0 0x17E0 | |
| #define MC6_CH1_DFI_PHY_Control_1 0x17E4 | |
| #define MC6_CH1_DFI_PHY_Control_2 0x17E8 | |
| #define MC6_CH1_DFI_PHY_Control_3 0x17EC | |
| #define MC6_CH1_DFI_PHY_CA_Train 0x17F0 | |
| #define MC6_CH1_DFI_PHY_CA_Pattern 0x17F4 | |
| #define MC6_CH1_DFI_PHY_Write_DQ_Train 0x17F8 | |
| #define MC6_CH1_DFI_PHY_Leveling_Status 0x17FC | |
| #endif |