| /* |
| * Copyright (C) 2018 Synaptics Incorporated. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED "AS-IS," AND |
| * SYNAPTICS EXPRESSLY DISCLAIMS ALL EXPRESS AND IMPLIED WARRANTIES, |
| * INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| * A PARTICULAR PURPOSE, AND ANY WARRANTIES OF NON-INFRINGEMENT OF ANY |
| * INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT SHALL SYNAPTICS BE LIABLE |
| * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, OR |
| * CONSEQUENTIAL DAMAGES ARISING OUT OF OR IN CONNECTION WITH THE USE |
| * OF THE INFORMATION CONTAINED IN THIS DOCUMENT, HOWEVER CAUSED AND |
| * BASED ON ANY THEORY OF LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| * NEGLIGENCE OR OTHER TORTIOUS ACTION, AND EVEN IF SYNAPTICS WAS |
| * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. IF A TRIBUNAL OF |
| * COMPETENT JURISDICTION DOES NOT PERMIT THE DISCLAIMER OF DIRECT |
| * DAMAGES OR ANY OTHER DAMAGES, SYNAPTICS' TOTAL CUMULATIVE LIABILITY |
| * TO ANY PARTY SHALL NOT EXCEED ONE HUNDRED U.S. DOLLARS. |
| */ |
| |
| #ifndef __pcie_H__ |
| #define __pcie_H__ |
| |
| #define RA_REFCLK_CTRL 0x0000 |
| |
| #define BA_REFCLK_CTRL_PD 0x0000 |
| #define B16REFCLK_CTRL_PD 0x0000 |
| #define LSb32REFCLK_CTRL_PD 0 |
| #define LSb16REFCLK_CTRL_PD 0 |
| #define bREFCLK_CTRL_PD 1 |
| #define MSK32REFCLK_CTRL_PD 0x00000001 |
| |
| #define BA_REFCLK_CTRL_CLK_SEL_CMU 0x0000 |
| #define B16REFCLK_CTRL_CLK_SEL_CMU 0x0000 |
| #define LSb32REFCLK_CTRL_CLK_SEL_CMU 1 |
| #define LSb16REFCLK_CTRL_CLK_SEL_CMU 1 |
| #define bREFCLK_CTRL_CLK_SEL_CMU 1 |
| #define MSK32REFCLK_CTRL_CLK_SEL_CMU 0x00000002 |
| |
| #define BA_REFCLK_CTRL_AMP_CON 0x0000 |
| #define B16REFCLK_CTRL_AMP_CON 0x0000 |
| #define LSb32REFCLK_CTRL_AMP_CON 2 |
| #define LSb16REFCLK_CTRL_AMP_CON 2 |
| #define bREFCLK_CTRL_AMP_CON 2 |
| #define MSK32REFCLK_CTRL_AMP_CON 0x0000000C |
| |
| #define BA_REFCLK_CTRL_SPARE 0x0000 |
| #define B16REFCLK_CTRL_SPARE 0x0000 |
| #define LSb32REFCLK_CTRL_SPARE 4 |
| #define LSb16REFCLK_CTRL_SPARE 4 |
| #define bREFCLK_CTRL_SPARE 3 |
| #define MSK32REFCLK_CTRL_SPARE 0x00000070 |
| |
| #define BA_REFCLK_CTRL_BUF_EN 0x0000 |
| #define B16REFCLK_CTRL_BUF_EN 0x0000 |
| #define LSb32REFCLK_CTRL_BUF_EN 7 |
| #define LSb16REFCLK_CTRL_BUF_EN 7 |
| #define bREFCLK_CTRL_BUF_EN 1 |
| #define MSK32REFCLK_CTRL_BUF_EN 0x00000080 |
| |
| #define BA_REFCLK_CTRL_IMP 0x0001 |
| #define B16REFCLK_CTRL_IMP 0x0000 |
| #define LSb32REFCLK_CTRL_IMP 8 |
| #define LSb16REFCLK_CTRL_IMP 8 |
| #define bREFCLK_CTRL_IMP 3 |
| #define MSK32REFCLK_CTRL_IMP 0x00000700 |
| /////////////////////////////////////////////////////////// |
| |
| #define RA_PCIE_IP_REGSP_0 0x0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCIE_IP_REGSP_1 0x8000 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCIE_MSI_INTR_RX 0xA000 |
| |
| #define BA_PCIE_MSI_INTR_RX_DATA 0xA000 |
| #define B16PCIE_MSI_INTR_RX_DATA 0xA000 |
| #define LSb32PCIE_MSI_INTR_RX_DATA 0 |
| #define LSb16PCIE_MSI_INTR_RX_DATA 0 |
| #define bPCIE_MSI_INTR_RX_DATA 32 |
| #define MSK32PCIE_MSI_INTR_RX_DATA 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_PCIE_MSI_INTR_STATUS 0xA004 |
| |
| #define BA_PCIE_MSI_INTR_STATUS_VALUE 0xA004 |
| #define B16PCIE_MSI_INTR_STATUS_VALUE 0xA004 |
| #define LSb32PCIE_MSI_INTR_STATUS_VALUE 0 |
| #define LSb16PCIE_MSI_INTR_STATUS_VALUE 0 |
| #define bPCIE_MSI_INTR_STATUS_VALUE 32 |
| #define MSK32PCIE_MSI_INTR_STATUS_VALUE 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_PCIE_MSI_INTR_MASK 0xA008 |
| |
| #define BA_PCIE_MSI_INTR_MASK_VALUE 0xA008 |
| #define B16PCIE_MSI_INTR_MASK_VALUE 0xA008 |
| #define LSb32PCIE_MSI_INTR_MASK_VALUE 0 |
| #define LSb16PCIE_MSI_INTR_MASK_VALUE 0 |
| #define bPCIE_MSI_INTR_MASK_VALUE 32 |
| #define MSK32PCIE_MSI_INTR_MASK_VALUE 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_PCIE_MAC_INTR_STATUS 0xA00C |
| |
| #define BA_PCIE_MAC_INTR_STATUS_AXI_ADDR_OOR 0xA00C |
| #define B16PCIE_MAC_INTR_STATUS_AXI_ADDR_OOR 0xA00C |
| #define LSb32PCIE_MAC_INTR_STATUS_AXI_ADDR_OOR 0 |
| #define LSb16PCIE_MAC_INTR_STATUS_AXI_ADDR_OOR 0 |
| #define bPCIE_MAC_INTR_STATUS_AXI_ADDR_OOR 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_AXI_ADDR_OOR 0x00000001 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_MSI_CTRL_INT 0xA00C |
| #define B16PCIE_MAC_INTR_STATUS_MSI_CTRL_INT 0xA00C |
| #define LSb32PCIE_MAC_INTR_STATUS_MSI_CTRL_INT 1 |
| #define LSb16PCIE_MAC_INTR_STATUS_MSI_CTRL_INT 1 |
| #define bPCIE_MAC_INTR_STATUS_MSI_CTRL_INT 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_MSI_CTRL_INT 0x00000002 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_HP_INT 0xA00C |
| #define B16PCIE_MAC_INTR_STATUS_HP_INT 0xA00C |
| #define LSb32PCIE_MAC_INTR_STATUS_HP_INT 2 |
| #define LSb16PCIE_MAC_INTR_STATUS_HP_INT 2 |
| #define bPCIE_MAC_INTR_STATUS_HP_INT 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_HP_INT 0x00000004 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_CFG_PME_INT 0xA00C |
| #define B16PCIE_MAC_INTR_STATUS_CFG_PME_INT 0xA00C |
| #define LSb32PCIE_MAC_INTR_STATUS_CFG_PME_INT 3 |
| #define LSb16PCIE_MAC_INTR_STATUS_CFG_PME_INT 3 |
| #define bPCIE_MAC_INTR_STATUS_CFG_PME_INT 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_CFG_PME_INT 0x00000008 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_CFG_AER_RC_ERR_INT 0xA00C |
| #define B16PCIE_MAC_INTR_STATUS_CFG_AER_RC_ERR_INT 0xA00C |
| #define LSb32PCIE_MAC_INTR_STATUS_CFG_AER_RC_ERR_INT 4 |
| #define LSb16PCIE_MAC_INTR_STATUS_CFG_AER_RC_ERR_INT 4 |
| #define bPCIE_MAC_INTR_STATUS_CFG_AER_RC_ERR_INT 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_CFG_AER_RC_ERR_INT 0x00000010 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_CFG_AER_RC_ERR_MSI 0xA00C |
| #define B16PCIE_MAC_INTR_STATUS_CFG_AER_RC_ERR_MSI 0xA00C |
| #define LSb32PCIE_MAC_INTR_STATUS_CFG_AER_RC_ERR_MSI 5 |
| #define LSb16PCIE_MAC_INTR_STATUS_CFG_AER_RC_ERR_MSI 5 |
| #define bPCIE_MAC_INTR_STATUS_CFG_AER_RC_ERR_MSI 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_CFG_AER_RC_ERR_MSI 0x00000020 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_CFG_SYS_ERR_RC 0xA00C |
| #define B16PCIE_MAC_INTR_STATUS_CFG_SYS_ERR_RC 0xA00C |
| #define LSb32PCIE_MAC_INTR_STATUS_CFG_SYS_ERR_RC 6 |
| #define LSb16PCIE_MAC_INTR_STATUS_CFG_SYS_ERR_RC 6 |
| #define bPCIE_MAC_INTR_STATUS_CFG_SYS_ERR_RC 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_CFG_SYS_ERR_RC 0x00000040 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_CFG_PME_MSI 0xA00C |
| #define B16PCIE_MAC_INTR_STATUS_CFG_PME_MSI 0xA00C |
| #define LSb32PCIE_MAC_INTR_STATUS_CFG_PME_MSI 7 |
| #define LSb16PCIE_MAC_INTR_STATUS_CFG_PME_MSI 7 |
| #define bPCIE_MAC_INTR_STATUS_CFG_PME_MSI 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_CFG_PME_MSI 0x00000080 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_RADM_CORRECTABLE_ERR 0xA00D |
| #define B16PCIE_MAC_INTR_STATUS_RADM_CORRECTABLE_ERR 0xA00C |
| #define LSb32PCIE_MAC_INTR_STATUS_RADM_CORRECTABLE_ERR 8 |
| #define LSb16PCIE_MAC_INTR_STATUS_RADM_CORRECTABLE_ERR 8 |
| #define bPCIE_MAC_INTR_STATUS_RADM_CORRECTABLE_ERR 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_RADM_CORRECTABLE_ERR 0x00000100 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_RADM_NONFATAL_ERR 0xA00D |
| #define B16PCIE_MAC_INTR_STATUS_RADM_NONFATAL_ERR 0xA00C |
| #define LSb32PCIE_MAC_INTR_STATUS_RADM_NONFATAL_ERR 9 |
| #define LSb16PCIE_MAC_INTR_STATUS_RADM_NONFATAL_ERR 9 |
| #define bPCIE_MAC_INTR_STATUS_RADM_NONFATAL_ERR 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_RADM_NONFATAL_ERR 0x00000200 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_RADM_FATAL_ERR 0xA00D |
| #define B16PCIE_MAC_INTR_STATUS_RADM_FATAL_ERR 0xA00C |
| #define LSb32PCIE_MAC_INTR_STATUS_RADM_FATAL_ERR 10 |
| #define LSb16PCIE_MAC_INTR_STATUS_RADM_FATAL_ERR 10 |
| #define bPCIE_MAC_INTR_STATUS_RADM_FATAL_ERR 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_RADM_FATAL_ERR 0x00000400 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_RADM_PM_PME 0xA00D |
| #define B16PCIE_MAC_INTR_STATUS_RADM_PM_PME 0xA00C |
| #define LSb32PCIE_MAC_INTR_STATUS_RADM_PM_PME 11 |
| #define LSb16PCIE_MAC_INTR_STATUS_RADM_PM_PME 11 |
| #define bPCIE_MAC_INTR_STATUS_RADM_PM_PME 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_RADM_PM_PME 0x00000800 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_RADM_PM_TO_ACK 0xA00D |
| #define B16PCIE_MAC_INTR_STATUS_RADM_PM_TO_ACK 0xA00C |
| #define LSb32PCIE_MAC_INTR_STATUS_RADM_PM_TO_ACK 12 |
| #define LSb16PCIE_MAC_INTR_STATUS_RADM_PM_TO_ACK 12 |
| #define bPCIE_MAC_INTR_STATUS_RADM_PM_TO_ACK 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_RADM_PM_TO_ACK 0x00001000 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_HP_PME 0xA00D |
| #define B16PCIE_MAC_INTR_STATUS_HP_PME 0xA00C |
| #define LSb32PCIE_MAC_INTR_STATUS_HP_PME 13 |
| #define LSb16PCIE_MAC_INTR_STATUS_HP_PME 13 |
| #define bPCIE_MAC_INTR_STATUS_HP_PME 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_HP_PME 0x00002000 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_HP_MSI 0xA00D |
| #define B16PCIE_MAC_INTR_STATUS_HP_MSI 0xA00C |
| #define LSb32PCIE_MAC_INTR_STATUS_HP_MSI 14 |
| #define LSb16PCIE_MAC_INTR_STATUS_HP_MSI 14 |
| #define bPCIE_MAC_INTR_STATUS_HP_MSI 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_HP_MSI 0x00004000 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_CFG_LINK_AUTO_BW_INT 0xA00D |
| #define B16PCIE_MAC_INTR_STATUS_CFG_LINK_AUTO_BW_INT 0xA00C |
| #define LSb32PCIE_MAC_INTR_STATUS_CFG_LINK_AUTO_BW_INT 15 |
| #define LSb16PCIE_MAC_INTR_STATUS_CFG_LINK_AUTO_BW_INT 15 |
| #define bPCIE_MAC_INTR_STATUS_CFG_LINK_AUTO_BW_INT 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_CFG_LINK_AUTO_BW_INT 0x00008000 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_CFG_LINK_AUTO_BW_MSI 0xA00E |
| #define B16PCIE_MAC_INTR_STATUS_CFG_LINK_AUTO_BW_MSI 0xA00E |
| #define LSb32PCIE_MAC_INTR_STATUS_CFG_LINK_AUTO_BW_MSI 16 |
| #define LSb16PCIE_MAC_INTR_STATUS_CFG_LINK_AUTO_BW_MSI 0 |
| #define bPCIE_MAC_INTR_STATUS_CFG_LINK_AUTO_BW_MSI 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_CFG_LINK_AUTO_BW_MSI 0x00010000 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_CFG_BW_MGT_INT 0xA00E |
| #define B16PCIE_MAC_INTR_STATUS_CFG_BW_MGT_INT 0xA00E |
| #define LSb32PCIE_MAC_INTR_STATUS_CFG_BW_MGT_INT 17 |
| #define LSb16PCIE_MAC_INTR_STATUS_CFG_BW_MGT_INT 1 |
| #define bPCIE_MAC_INTR_STATUS_CFG_BW_MGT_INT 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_CFG_BW_MGT_INT 0x00020000 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_CFG_BW_MGT_MSI 0xA00E |
| #define B16PCIE_MAC_INTR_STATUS_CFG_BW_MGT_MSI 0xA00E |
| #define LSb32PCIE_MAC_INTR_STATUS_CFG_BW_MGT_MSI 18 |
| #define LSb16PCIE_MAC_INTR_STATUS_CFG_BW_MGT_MSI 2 |
| #define bPCIE_MAC_INTR_STATUS_CFG_BW_MGT_MSI 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_CFG_BW_MGT_MSI 0x00040000 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_RADM_INTA_ASSERTED 0xA00E |
| #define B16PCIE_MAC_INTR_STATUS_RADM_INTA_ASSERTED 0xA00E |
| #define LSb32PCIE_MAC_INTR_STATUS_RADM_INTA_ASSERTED 19 |
| #define LSb16PCIE_MAC_INTR_STATUS_RADM_INTA_ASSERTED 3 |
| #define bPCIE_MAC_INTR_STATUS_RADM_INTA_ASSERTED 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_RADM_INTA_ASSERTED 0x00080000 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_RADM_INTB_ASSERTED 0xA00E |
| #define B16PCIE_MAC_INTR_STATUS_RADM_INTB_ASSERTED 0xA00E |
| #define LSb32PCIE_MAC_INTR_STATUS_RADM_INTB_ASSERTED 20 |
| #define LSb16PCIE_MAC_INTR_STATUS_RADM_INTB_ASSERTED 4 |
| #define bPCIE_MAC_INTR_STATUS_RADM_INTB_ASSERTED 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_RADM_INTB_ASSERTED 0x00100000 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_RADM_INTC_ASSERTED 0xA00E |
| #define B16PCIE_MAC_INTR_STATUS_RADM_INTC_ASSERTED 0xA00E |
| #define LSb32PCIE_MAC_INTR_STATUS_RADM_INTC_ASSERTED 21 |
| #define LSb16PCIE_MAC_INTR_STATUS_RADM_INTC_ASSERTED 5 |
| #define bPCIE_MAC_INTR_STATUS_RADM_INTC_ASSERTED 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_RADM_INTC_ASSERTED 0x00200000 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_RADM_INTD_ASSERTED 0xA00E |
| #define B16PCIE_MAC_INTR_STATUS_RADM_INTD_ASSERTED 0xA00E |
| #define LSb32PCIE_MAC_INTR_STATUS_RADM_INTD_ASSERTED 22 |
| #define LSb16PCIE_MAC_INTR_STATUS_RADM_INTD_ASSERTED 6 |
| #define bPCIE_MAC_INTR_STATUS_RADM_INTD_ASSERTED 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_RADM_INTD_ASSERTED 0x00400000 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_RADM_INTA_DEASSERTED 0xA00E |
| #define B16PCIE_MAC_INTR_STATUS_RADM_INTA_DEASSERTED 0xA00E |
| #define LSb32PCIE_MAC_INTR_STATUS_RADM_INTA_DEASSERTED 23 |
| #define LSb16PCIE_MAC_INTR_STATUS_RADM_INTA_DEASSERTED 7 |
| #define bPCIE_MAC_INTR_STATUS_RADM_INTA_DEASSERTED 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_RADM_INTA_DEASSERTED 0x00800000 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_RADM_INTB_DEASSERTED 0xA00F |
| #define B16PCIE_MAC_INTR_STATUS_RADM_INTB_DEASSERTED 0xA00E |
| #define LSb32PCIE_MAC_INTR_STATUS_RADM_INTB_DEASSERTED 24 |
| #define LSb16PCIE_MAC_INTR_STATUS_RADM_INTB_DEASSERTED 8 |
| #define bPCIE_MAC_INTR_STATUS_RADM_INTB_DEASSERTED 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_RADM_INTB_DEASSERTED 0x01000000 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_RADM_INTC_DEASSERTED 0xA00F |
| #define B16PCIE_MAC_INTR_STATUS_RADM_INTC_DEASSERTED 0xA00E |
| #define LSb32PCIE_MAC_INTR_STATUS_RADM_INTC_DEASSERTED 25 |
| #define LSb16PCIE_MAC_INTR_STATUS_RADM_INTC_DEASSERTED 9 |
| #define bPCIE_MAC_INTR_STATUS_RADM_INTC_DEASSERTED 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_RADM_INTC_DEASSERTED 0x02000000 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_RADM_INTD_DEASSERTED 0xA00F |
| #define B16PCIE_MAC_INTR_STATUS_RADM_INTD_DEASSERTED 0xA00E |
| #define LSb32PCIE_MAC_INTR_STATUS_RADM_INTD_DEASSERTED 26 |
| #define LSb16PCIE_MAC_INTR_STATUS_RADM_INTD_DEASSERTED 10 |
| #define bPCIE_MAC_INTR_STATUS_RADM_INTD_DEASSERTED 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_RADM_INTD_DEASSERTED 0x04000000 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_RADM_QOVERFLOW 0xA00F |
| #define B16PCIE_MAC_INTR_STATUS_RADM_QOVERFLOW 0xA00E |
| #define LSb32PCIE_MAC_INTR_STATUS_RADM_QOVERFLOW 27 |
| #define LSb16PCIE_MAC_INTR_STATUS_RADM_QOVERFLOW 11 |
| #define bPCIE_MAC_INTR_STATUS_RADM_QOVERFLOW 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_RADM_QOVERFLOW 0x08000000 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_ASSERT_INTA_GRT 0xA00F |
| #define B16PCIE_MAC_INTR_STATUS_ASSERT_INTA_GRT 0xA00E |
| #define LSb32PCIE_MAC_INTR_STATUS_ASSERT_INTA_GRT 28 |
| #define LSb16PCIE_MAC_INTR_STATUS_ASSERT_INTA_GRT 12 |
| #define bPCIE_MAC_INTR_STATUS_ASSERT_INTA_GRT 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_ASSERT_INTA_GRT 0x10000000 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_ASSERT_INTB_GRT 0xA00F |
| #define B16PCIE_MAC_INTR_STATUS_ASSERT_INTB_GRT 0xA00E |
| #define LSb32PCIE_MAC_INTR_STATUS_ASSERT_INTB_GRT 29 |
| #define LSb16PCIE_MAC_INTR_STATUS_ASSERT_INTB_GRT 13 |
| #define bPCIE_MAC_INTR_STATUS_ASSERT_INTB_GRT 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_ASSERT_INTB_GRT 0x20000000 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_ASSERT_INTC_GRT 0xA00F |
| #define B16PCIE_MAC_INTR_STATUS_ASSERT_INTC_GRT 0xA00E |
| #define LSb32PCIE_MAC_INTR_STATUS_ASSERT_INTC_GRT 30 |
| #define LSb16PCIE_MAC_INTR_STATUS_ASSERT_INTC_GRT 14 |
| #define bPCIE_MAC_INTR_STATUS_ASSERT_INTC_GRT 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_ASSERT_INTC_GRT 0x40000000 |
| |
| #define BA_PCIE_MAC_INTR_STATUS_ASSERT_INTD_GRT 0xA00F |
| #define B16PCIE_MAC_INTR_STATUS_ASSERT_INTD_GRT 0xA00E |
| #define LSb32PCIE_MAC_INTR_STATUS_ASSERT_INTD_GRT 31 |
| #define LSb16PCIE_MAC_INTR_STATUS_ASSERT_INTD_GRT 15 |
| #define bPCIE_MAC_INTR_STATUS_ASSERT_INTD_GRT 1 |
| #define MSK32PCIE_MAC_INTR_STATUS_ASSERT_INTD_GRT 0x80000000 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCIE_MAC_INTR_STATUS1 0xA010 |
| |
| #define BA_PCIE_MAC_INTR_STATUS1_DEASSERT_INTA_GRT 0xA010 |
| #define B16PCIE_MAC_INTR_STATUS1_DEASSERT_INTA_GRT 0xA010 |
| #define LSb32PCIE_MAC_INTR_STATUS1_DEASSERT_INTA_GRT 0 |
| #define LSb16PCIE_MAC_INTR_STATUS1_DEASSERT_INTA_GRT 0 |
| #define bPCIE_MAC_INTR_STATUS1_DEASSERT_INTA_GRT 1 |
| #define MSK32PCIE_MAC_INTR_STATUS1_DEASSERT_INTA_GRT 0x00000001 |
| |
| #define BA_PCIE_MAC_INTR_STATUS1_DEASSERT_INTB_GRT 0xA010 |
| #define B16PCIE_MAC_INTR_STATUS1_DEASSERT_INTB_GRT 0xA010 |
| #define LSb32PCIE_MAC_INTR_STATUS1_DEASSERT_INTB_GRT 1 |
| #define LSb16PCIE_MAC_INTR_STATUS1_DEASSERT_INTB_GRT 1 |
| #define bPCIE_MAC_INTR_STATUS1_DEASSERT_INTB_GRT 1 |
| #define MSK32PCIE_MAC_INTR_STATUS1_DEASSERT_INTB_GRT 0x00000002 |
| |
| #define BA_PCIE_MAC_INTR_STATUS1_DEASSERT_INTC_GRT 0xA010 |
| #define B16PCIE_MAC_INTR_STATUS1_DEASSERT_INTC_GRT 0xA010 |
| #define LSb32PCIE_MAC_INTR_STATUS1_DEASSERT_INTC_GRT 2 |
| #define LSb16PCIE_MAC_INTR_STATUS1_DEASSERT_INTC_GRT 2 |
| #define bPCIE_MAC_INTR_STATUS1_DEASSERT_INTC_GRT 1 |
| #define MSK32PCIE_MAC_INTR_STATUS1_DEASSERT_INTC_GRT 0x00000004 |
| |
| #define BA_PCIE_MAC_INTR_STATUS1_DEASSERT_INTD_GRT 0xA010 |
| #define B16PCIE_MAC_INTR_STATUS1_DEASSERT_INTD_GRT 0xA010 |
| #define LSb32PCIE_MAC_INTR_STATUS1_DEASSERT_INTD_GRT 3 |
| #define LSb16PCIE_MAC_INTR_STATUS1_DEASSERT_INTD_GRT 3 |
| #define bPCIE_MAC_INTR_STATUS1_DEASSERT_INTD_GRT 1 |
| #define MSK32PCIE_MAC_INTR_STATUS1_DEASSERT_INTD_GRT 0x00000008 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCIE_MAC_INTR_MASK 0xA014 |
| |
| #define BA_PCIE_MAC_INTR_MASK_INTR_MASK 0xA014 |
| #define B16PCIE_MAC_INTR_MASK_INTR_MASK 0xA014 |
| #define LSb32PCIE_MAC_INTR_MASK_INTR_MASK 0 |
| #define LSb16PCIE_MAC_INTR_MASK_INTR_MASK 0 |
| #define bPCIE_MAC_INTR_MASK_INTR_MASK 32 |
| #define MSK32PCIE_MAC_INTR_MASK_INTR_MASK 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_PCIE_MAC_INTR_MASK1 0xA018 |
| |
| #define BA_PCIE_MAC_INTR_MASK1_INTR_MASK 0xA018 |
| #define B16PCIE_MAC_INTR_MASK1_INTR_MASK 0xA018 |
| #define LSb32PCIE_MAC_INTR_MASK1_INTR_MASK 0 |
| #define LSb16PCIE_MAC_INTR_MASK1_INTR_MASK 0 |
| #define bPCIE_MAC_INTR_MASK1_INTR_MASK 4 |
| #define MSK32PCIE_MAC_INTR_MASK1_INTR_MASK 0x0000000F |
| /////////////////////////////////////////////////////////// |
| #define RA_PCIE_MAC_CTRL 0xA01C |
| |
| #define BA_PCIE_MAC_CTRL_SYSWREQ 0xA01C |
| #define B16PCIE_MAC_CTRL_SYSWREQ 0xA01C |
| #define LSb32PCIE_MAC_CTRL_SYSWREQ 0 |
| #define LSb16PCIE_MAC_CTRL_SYSWREQ 0 |
| #define bPCIE_MAC_CTRL_SYSWREQ 1 |
| #define MSK32PCIE_MAC_CTRL_SYSWREQ 0x00000001 |
| |
| #define BA_PCIE_MAC_CTRL_CPU_INTERFACE_SEL 0xA01C |
| #define B16PCIE_MAC_CTRL_CPU_INTERFACE_SEL 0xA01C |
| #define LSb32PCIE_MAC_CTRL_CPU_INTERFACE_SEL 1 |
| #define LSb16PCIE_MAC_CTRL_CPU_INTERFACE_SEL 1 |
| #define bPCIE_MAC_CTRL_CPU_INTERFACE_SEL 1 |
| #define MSK32PCIE_MAC_CTRL_CPU_INTERFACE_SEL 0x00000002 |
| |
| #define BA_PCIE_MAC_CTRL_CFG_TYPE 0xA01C |
| #define B16PCIE_MAC_CTRL_CFG_TYPE 0xA01C |
| #define LSb32PCIE_MAC_CTRL_CFG_TYPE 2 |
| #define LSb16PCIE_MAC_CTRL_CFG_TYPE 2 |
| #define bPCIE_MAC_CTRL_CFG_TYPE 1 |
| #define MSK32PCIE_MAC_CTRL_CFG_TYPE 0x00000004 |
| |
| #define BA_PCIE_MAC_CTRL_MEMMAP_CFG_VALID 0xA01C |
| #define B16PCIE_MAC_CTRL_MEMMAP_CFG_VALID 0xA01C |
| #define LSb32PCIE_MAC_CTRL_MEMMAP_CFG_VALID 3 |
| #define LSb16PCIE_MAC_CTRL_MEMMAP_CFG_VALID 3 |
| #define bPCIE_MAC_CTRL_MEMMAP_CFG_VALID 1 |
| #define MSK32PCIE_MAC_CTRL_MEMMAP_CFG_VALID 0x00000008 |
| |
| #define BA_PCIE_MAC_CTRL_SYS_AUX_PWR_DET 0xA01C |
| #define B16PCIE_MAC_CTRL_SYS_AUX_PWR_DET 0xA01C |
| #define LSb32PCIE_MAC_CTRL_SYS_AUX_PWR_DET 4 |
| #define LSb16PCIE_MAC_CTRL_SYS_AUX_PWR_DET 4 |
| #define bPCIE_MAC_CTRL_SYS_AUX_PWR_DET 1 |
| #define MSK32PCIE_MAC_CTRL_SYS_AUX_PWR_DET 0x00000010 |
| |
| #define BA_PCIE_MAC_CTRL_APP_LTSSM_ENABLE 0xA01C |
| #define B16PCIE_MAC_CTRL_APP_LTSSM_ENABLE 0xA01C |
| #define LSb32PCIE_MAC_CTRL_APP_LTSSM_ENABLE 5 |
| #define LSb16PCIE_MAC_CTRL_APP_LTSSM_ENABLE 5 |
| #define bPCIE_MAC_CTRL_APP_LTSSM_ENABLE 1 |
| #define MSK32PCIE_MAC_CTRL_APP_LTSSM_ENABLE 0x00000020 |
| |
| #define BA_PCIE_MAC_CTRL_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN 0xA01C |
| #define B16PCIE_MAC_CTRL_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN 0xA01C |
| #define LSb32PCIE_MAC_CTRL_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN 6 |
| #define LSb16PCIE_MAC_CTRL_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN 6 |
| #define bPCIE_MAC_CTRL_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN 1 |
| #define MSK32PCIE_MAC_CTRL_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN 0x00000040 |
| |
| #define BA_PCIE_MAC_CTRL_CFG_L1_MAC_POWERDOWN_OVERRIDE_TO_P2_EN 0xA01C |
| #define B16PCIE_MAC_CTRL_CFG_L1_MAC_POWERDOWN_OVERRIDE_TO_P2_EN 0xA01C |
| #define LSb32PCIE_MAC_CTRL_CFG_L1_MAC_POWERDOWN_OVERRIDE_TO_P2_EN 7 |
| #define LSb16PCIE_MAC_CTRL_CFG_L1_MAC_POWERDOWN_OVERRIDE_TO_P2_EN 7 |
| #define bPCIE_MAC_CTRL_CFG_L1_MAC_POWERDOWN_OVERRIDE_TO_P2_EN 1 |
| #define MSK32PCIE_MAC_CTRL_CFG_L1_MAC_POWERDOWN_OVERRIDE_TO_P2_EN 0x00000080 |
| |
| #define BA_PCIE_MAC_CTRL_ADDR_FILTER_FLAG 0xA01D |
| #define B16PCIE_MAC_CTRL_ADDR_FILTER_FLAG 0xA01C |
| #define LSb32PCIE_MAC_CTRL_ADDR_FILTER_FLAG 8 |
| #define LSb16PCIE_MAC_CTRL_ADDR_FILTER_FLAG 8 |
| #define bPCIE_MAC_CTRL_ADDR_FILTER_FLAG 1 |
| #define MSK32PCIE_MAC_CTRL_ADDR_FILTER_FLAG 0x00000100 |
| |
| #define BA_PCIE_MAC_CTRL_PCIEM_DS_RESP_MASK_N 0xA01D |
| #define B16PCIE_MAC_CTRL_PCIEM_DS_RESP_MASK_N 0xA01C |
| #define LSb32PCIE_MAC_CTRL_PCIEM_DS_RESP_MASK_N 9 |
| #define LSb16PCIE_MAC_CTRL_PCIEM_DS_RESP_MASK_N 9 |
| #define bPCIE_MAC_CTRL_PCIEM_DS_RESP_MASK_N 1 |
| #define MSK32PCIE_MAC_CTRL_PCIEM_DS_RESP_MASK_N 0x00000200 |
| |
| #define BA_PCIE_MAC_CTRL_CLK_RST_BYPASS 0xA01D |
| #define B16PCIE_MAC_CTRL_CLK_RST_BYPASS 0xA01C |
| #define LSb32PCIE_MAC_CTRL_CLK_RST_BYPASS 10 |
| #define LSb16PCIE_MAC_CTRL_CLK_RST_BYPASS 10 |
| #define bPCIE_MAC_CTRL_CLK_RST_BYPASS 1 |
| #define MSK32PCIE_MAC_CTRL_CLK_RST_BYPASS 0x00000400 |
| |
| #define BA_PCIE_MAC_CTRL_MAC_DBI_CS2_ENABLE 0xA01D |
| #define B16PCIE_MAC_CTRL_MAC_DBI_CS2_ENABLE 0xA01C |
| #define LSb32PCIE_MAC_CTRL_MAC_DBI_CS2_ENABLE 11 |
| #define LSb16PCIE_MAC_CTRL_MAC_DBI_CS2_ENABLE 11 |
| #define bPCIE_MAC_CTRL_MAC_DBI_CS2_ENABLE 1 |
| #define MSK32PCIE_MAC_CTRL_MAC_DBI_CS2_ENABLE 0x00000800 |
| |
| #define BA_PCIE_MAC_CTRL_MAC_DBI_iATU_ADDR_SEL 0xA01D |
| #define B16PCIE_MAC_CTRL_MAC_DBI_iATU_ADDR_SEL 0xA01C |
| #define LSb32PCIE_MAC_CTRL_MAC_DBI_iATU_ADDR_SEL 12 |
| #define LSb16PCIE_MAC_CTRL_MAC_DBI_iATU_ADDR_SEL 12 |
| #define bPCIE_MAC_CTRL_MAC_DBI_iATU_ADDR_SEL 1 |
| #define MSK32PCIE_MAC_CTRL_MAC_DBI_iATU_ADDR_SEL 0x00001000 |
| |
| #define BA_PCIE_MAC_CTRL_APP_CLK_REQ_N 0xA01D |
| #define B16PCIE_MAC_CTRL_APP_CLK_REQ_N 0xA01C |
| #define LSb32PCIE_MAC_CTRL_APP_CLK_REQ_N 13 |
| #define LSb16PCIE_MAC_CTRL_APP_CLK_REQ_N 13 |
| #define bPCIE_MAC_CTRL_APP_CLK_REQ_N 1 |
| #define MSK32PCIE_MAC_CTRL_APP_CLK_REQ_N 0x00002000 |
| |
| #define BA_PCIE_MAC_CTRL_APP_REQ_EXIT_L1 0xA01D |
| #define B16PCIE_MAC_CTRL_APP_REQ_EXIT_L1 0xA01C |
| #define LSb32PCIE_MAC_CTRL_APP_REQ_EXIT_L1 14 |
| #define LSb16PCIE_MAC_CTRL_APP_REQ_EXIT_L1 14 |
| #define bPCIE_MAC_CTRL_APP_REQ_EXIT_L1 1 |
| #define MSK32PCIE_MAC_CTRL_APP_REQ_EXIT_L1 0x00004000 |
| |
| #define BA_PCIE_MAC_CTRL_APP_XFER_PENDING 0xA01D |
| #define B16PCIE_MAC_CTRL_APP_XFER_PENDING 0xA01C |
| #define LSb32PCIE_MAC_CTRL_APP_XFER_PENDING 15 |
| #define LSb16PCIE_MAC_CTRL_APP_XFER_PENDING 15 |
| #define bPCIE_MAC_CTRL_APP_XFER_PENDING 1 |
| #define MSK32PCIE_MAC_CTRL_APP_XFER_PENDING 0x00008000 |
| |
| #define BA_PCIE_MAC_CTRL_APP_CLK_PM_EN 0xA01E |
| #define B16PCIE_MAC_CTRL_APP_CLK_PM_EN 0xA01E |
| #define LSb32PCIE_MAC_CTRL_APP_CLK_PM_EN 16 |
| #define LSb16PCIE_MAC_CTRL_APP_CLK_PM_EN 0 |
| #define bPCIE_MAC_CTRL_APP_CLK_PM_EN 1 |
| #define MSK32PCIE_MAC_CTRL_APP_CLK_PM_EN 0x00010000 |
| |
| #define BA_PCIE_MAC_CTRL_PIPE2PIPE_BYPASS 0xA01E |
| #define B16PCIE_MAC_CTRL_PIPE2PIPE_BYPASS 0xA01E |
| #define LSb32PCIE_MAC_CTRL_PIPE2PIPE_BYPASS 17 |
| #define LSb16PCIE_MAC_CTRL_PIPE2PIPE_BYPASS 1 |
| #define bPCIE_MAC_CTRL_PIPE2PIPE_BYPASS 1 |
| #define MSK32PCIE_MAC_CTRL_PIPE2PIPE_BYPASS 0x00020000 |
| |
| #define BA_PCIE_MAC_CTRL_APPS_PM_XMT_TURNOFF 0xA01E |
| #define B16PCIE_MAC_CTRL_APPS_PM_XMT_TURNOFF 0xA01E |
| #define LSb32PCIE_MAC_CTRL_APPS_PM_XMT_TURNOFF 18 |
| #define LSb16PCIE_MAC_CTRL_APPS_PM_XMT_TURNOFF 2 |
| #define bPCIE_MAC_CTRL_APPS_PM_XMT_TURNOFF 1 |
| #define MSK32PCIE_MAC_CTRL_APPS_PM_XMT_TURNOFF 0x00040000 |
| |
| #define BA_PCIE_MAC_CTRL_CLEAR_L2_INTR 0xA01E |
| #define B16PCIE_MAC_CTRL_CLEAR_L2_INTR 0xA01E |
| #define LSb32PCIE_MAC_CTRL_CLEAR_L2_INTR 19 |
| #define LSb16PCIE_MAC_CTRL_CLEAR_L2_INTR 3 |
| #define bPCIE_MAC_CTRL_CLEAR_L2_INTR 1 |
| #define MSK32PCIE_MAC_CTRL_CLEAR_L2_INTR 0x00080000 |
| |
| #define BA_PCIE_MAC_CTRL_SLV_WMISC_INFO 0xA01E |
| #define B16PCIE_MAC_CTRL_SLV_WMISC_INFO 0xA01E |
| #define LSb32PCIE_MAC_CTRL_SLV_WMISC_INFO 20 |
| #define LSb16PCIE_MAC_CTRL_SLV_WMISC_INFO 4 |
| #define bPCIE_MAC_CTRL_SLV_WMISC_INFO 1 |
| #define MSK32PCIE_MAC_CTRL_SLV_WMISC_INFO 0x00100000 |
| |
| #define BA_PCIE_MAC_CTRL_APP_DBI_RO_WR_DISABLE 0xA01E |
| #define B16PCIE_MAC_CTRL_APP_DBI_RO_WR_DISABLE 0xA01E |
| #define LSb32PCIE_MAC_CTRL_APP_DBI_RO_WR_DISABLE 21 |
| #define LSb16PCIE_MAC_CTRL_APP_DBI_RO_WR_DISABLE 5 |
| #define bPCIE_MAC_CTRL_APP_DBI_RO_WR_DISABLE 1 |
| #define MSK32PCIE_MAC_CTRL_APP_DBI_RO_WR_DISABLE 0x00200000 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCIE_MAC_STATUS 0xA020 |
| |
| #define BA_PCIE_MAC_STATUS_DWACK 0xA020 |
| #define B16PCIE_MAC_STATUS_DWACK 0xA020 |
| #define LSb32PCIE_MAC_STATUS_DWACK 0 |
| #define LSb16PCIE_MAC_STATUS_DWACK 0 |
| #define bPCIE_MAC_STATUS_DWACK 1 |
| #define MSK32PCIE_MAC_STATUS_DWACK 0x00000001 |
| |
| #define BA_PCIE_MAC_STATUS_RDLH_LINK_UP 0xA020 |
| #define B16PCIE_MAC_STATUS_RDLH_LINK_UP 0xA020 |
| #define LSb32PCIE_MAC_STATUS_RDLH_LINK_UP 1 |
| #define LSb16PCIE_MAC_STATUS_RDLH_LINK_UP 1 |
| #define bPCIE_MAC_STATUS_RDLH_LINK_UP 1 |
| #define MSK32PCIE_MAC_STATUS_RDLH_LINK_UP 0x00000002 |
| |
| #define BA_PCIE_MAC_STATUS_PM_CURNT_STATE 0xA020 |
| #define B16PCIE_MAC_STATUS_PM_CURNT_STATE 0xA020 |
| #define LSb32PCIE_MAC_STATUS_PM_CURNT_STATE 2 |
| #define LSb16PCIE_MAC_STATUS_PM_CURNT_STATE 2 |
| #define bPCIE_MAC_STATUS_PM_CURNT_STATE 3 |
| #define MSK32PCIE_MAC_STATUS_PM_CURNT_STATE 0x0000001C |
| |
| #define BA_PCIE_MAC_STATUS_SMLH_LTSSM_STATE 0xA020 |
| #define B16PCIE_MAC_STATUS_SMLH_LTSSM_STATE 0xA020 |
| #define LSb32PCIE_MAC_STATUS_SMLH_LTSSM_STATE 5 |
| #define LSb16PCIE_MAC_STATUS_SMLH_LTSSM_STATE 5 |
| #define bPCIE_MAC_STATUS_SMLH_LTSSM_STATE 6 |
| #define MSK32PCIE_MAC_STATUS_SMLH_LTSSM_STATE 0x000007E0 |
| |
| #define BA_PCIE_MAC_STATUS_SMLH_LINK_UP 0xA021 |
| #define B16PCIE_MAC_STATUS_SMLH_LINK_UP 0xA020 |
| #define LSb32PCIE_MAC_STATUS_SMLH_LINK_UP 11 |
| #define LSb16PCIE_MAC_STATUS_SMLH_LINK_UP 11 |
| #define bPCIE_MAC_STATUS_SMLH_LINK_UP 1 |
| #define MSK32PCIE_MAC_STATUS_SMLH_LINK_UP 0x00000800 |
| |
| #define BA_PCIE_MAC_STATUS_RADM_Q_NOT_EMPTY 0xA021 |
| #define B16PCIE_MAC_STATUS_RADM_Q_NOT_EMPTY 0xA020 |
| #define LSb32PCIE_MAC_STATUS_RADM_Q_NOT_EMPTY 12 |
| #define LSb16PCIE_MAC_STATUS_RADM_Q_NOT_EMPTY 12 |
| #define bPCIE_MAC_STATUS_RADM_Q_NOT_EMPTY 1 |
| #define MSK32PCIE_MAC_STATUS_RADM_Q_NOT_EMPTY 0x00001000 |
| |
| #define BA_PCIE_MAC_STATUS_TRGT_CPL_TIMEOUT 0xA021 |
| #define B16PCIE_MAC_STATUS_TRGT_CPL_TIMEOUT 0xA020 |
| #define LSb32PCIE_MAC_STATUS_TRGT_CPL_TIMEOUT 13 |
| #define LSb16PCIE_MAC_STATUS_TRGT_CPL_TIMEOUT 13 |
| #define bPCIE_MAC_STATUS_TRGT_CPL_TIMEOUT 1 |
| #define MSK32PCIE_MAC_STATUS_TRGT_CPL_TIMEOUT 0x00002000 |
| |
| #define BA_PCIE_MAC_STATUS_PM_XTLH_BLOCK_TLP 0xA021 |
| #define B16PCIE_MAC_STATUS_PM_XTLH_BLOCK_TLP 0xA020 |
| #define LSb32PCIE_MAC_STATUS_PM_XTLH_BLOCK_TLP 14 |
| #define LSb16PCIE_MAC_STATUS_PM_XTLH_BLOCK_TLP 14 |
| #define bPCIE_MAC_STATUS_PM_XTLH_BLOCK_TLP 1 |
| #define MSK32PCIE_MAC_STATUS_PM_XTLH_BLOCK_TLP 0x00004000 |
| |
| #define BA_PCIE_MAC_STATUS_BRDG_SLV_XFER_PENDING 0xA021 |
| #define B16PCIE_MAC_STATUS_BRDG_SLV_XFER_PENDING 0xA020 |
| #define LSb32PCIE_MAC_STATUS_BRDG_SLV_XFER_PENDING 15 |
| #define LSb16PCIE_MAC_STATUS_BRDG_SLV_XFER_PENDING 15 |
| #define bPCIE_MAC_STATUS_BRDG_SLV_XFER_PENDING 1 |
| #define MSK32PCIE_MAC_STATUS_BRDG_SLV_XFER_PENDING 0x00008000 |
| |
| #define BA_PCIE_MAC_STATUS_RADM_CPL_TIMEOUT 0xA022 |
| #define B16PCIE_MAC_STATUS_RADM_CPL_TIMEOUT 0xA022 |
| #define LSb32PCIE_MAC_STATUS_RADM_CPL_TIMEOUT 16 |
| #define LSb16PCIE_MAC_STATUS_RADM_CPL_TIMEOUT 0 |
| #define bPCIE_MAC_STATUS_RADM_CPL_TIMEOUT 1 |
| #define MSK32PCIE_MAC_STATUS_RADM_CPL_TIMEOUT 0x00010000 |
| |
| #define BA_PCIE_MAC_STATUS_CFG_INT_PIN 0xA022 |
| #define B16PCIE_MAC_STATUS_CFG_INT_PIN 0xA022 |
| #define LSb32PCIE_MAC_STATUS_CFG_INT_PIN 17 |
| #define LSb16PCIE_MAC_STATUS_CFG_INT_PIN 1 |
| #define bPCIE_MAC_STATUS_CFG_INT_PIN 8 |
| #define MSK32PCIE_MAC_STATUS_CFG_INT_PIN 0x01FE0000 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCIE_MAC_CLK_CTRL 0xA024 |
| |
| #define BA_PCIE_MAC_CLK_CTRL_AXI_CLKEN 0xA024 |
| #define B16PCIE_MAC_CLK_CTRL_AXI_CLKEN 0xA024 |
| #define LSb32PCIE_MAC_CLK_CTRL_AXI_CLKEN 0 |
| #define LSb16PCIE_MAC_CLK_CTRL_AXI_CLKEN 0 |
| #define bPCIE_MAC_CLK_CTRL_AXI_CLKEN 1 |
| #define MSK32PCIE_MAC_CLK_CTRL_AXI_CLKEN 0x00000001 |
| |
| #define BA_PCIE_MAC_CLK_CTRL_AHB_CLKEN 0xA024 |
| #define B16PCIE_MAC_CLK_CTRL_AHB_CLKEN 0xA024 |
| #define LSb32PCIE_MAC_CLK_CTRL_AHB_CLKEN 1 |
| #define LSb16PCIE_MAC_CLK_CTRL_AHB_CLKEN 1 |
| #define bPCIE_MAC_CLK_CTRL_AHB_CLKEN 1 |
| #define MSK32PCIE_MAC_CLK_CTRL_AHB_CLKEN 0x00000002 |
| |
| #define BA_PCIE_MAC_CLK_CTRL_CORE_CLKEN 0xA024 |
| #define B16PCIE_MAC_CLK_CTRL_CORE_CLKEN 0xA024 |
| #define LSb32PCIE_MAC_CLK_CTRL_CORE_CLKEN 2 |
| #define LSb16PCIE_MAC_CLK_CTRL_CORE_CLKEN 2 |
| #define bPCIE_MAC_CLK_CTRL_CORE_CLKEN 1 |
| #define MSK32PCIE_MAC_CLK_CTRL_CORE_CLKEN 0x00000004 |
| |
| #define BA_PCIE_MAC_CLK_CTRL_PIPE_CLKEN 0xA024 |
| #define B16PCIE_MAC_CLK_CTRL_PIPE_CLKEN 0xA024 |
| #define LSb32PCIE_MAC_CLK_CTRL_PIPE_CLKEN 3 |
| #define LSb16PCIE_MAC_CLK_CTRL_PIPE_CLKEN 3 |
| #define bPCIE_MAC_CLK_CTRL_PIPE_CLKEN 1 |
| #define MSK32PCIE_MAC_CLK_CTRL_PIPE_CLKEN 0x00000008 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCIE_REFCLK 0xA028 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCIE_PHY_CTRL 0xA02C |
| |
| #define BA_PCIE_PHY_CTRL_refclk_cmos_sel 0xA02C |
| #define B16PCIE_PHY_CTRL_refclk_cmos_sel 0xA02C |
| #define LSb32PCIE_PHY_CTRL_refclk_cmos_sel 0 |
| #define LSb16PCIE_PHY_CTRL_refclk_cmos_sel 0 |
| #define bPCIE_PHY_CTRL_refclk_cmos_sel 1 |
| #define MSK32PCIE_PHY_CTRL_refclk_cmos_sel 0x00000001 |
| |
| #define BA_PCIE_PHY_CTRL_customer_pin_mode 0xA02C |
| #define B16PCIE_PHY_CTRL_customer_pin_mode 0xA02C |
| #define LSb32PCIE_PHY_CTRL_customer_pin_mode 1 |
| #define LSb16PCIE_PHY_CTRL_customer_pin_mode 1 |
| #define bPCIE_PHY_CTRL_customer_pin_mode 16 |
| #define MSK32PCIE_PHY_CTRL_customer_pin_mode 0x0001FFFE |
| |
| #define BA_PCIE_PHY_CTRL_debug_sel 0xA02E |
| #define B16PCIE_PHY_CTRL_debug_sel 0xA02E |
| #define LSb32PCIE_PHY_CTRL_debug_sel 17 |
| #define LSb16PCIE_PHY_CTRL_debug_sel 1 |
| #define bPCIE_PHY_CTRL_debug_sel 4 |
| #define MSK32PCIE_PHY_CTRL_debug_sel 0x001E0000 |
| |
| #define BA_PCIE_PHY_CTRL_tx_spare_l0 0xA02E |
| #define B16PCIE_PHY_CTRL_tx_spare_l0 0xA02E |
| #define LSb32PCIE_PHY_CTRL_tx_spare_l0 21 |
| #define LSb16PCIE_PHY_CTRL_tx_spare_l0 5 |
| #define bPCIE_PHY_CTRL_tx_spare_l0 3 |
| #define MSK32PCIE_PHY_CTRL_tx_spare_l0 0x00E00000 |
| |
| #define BA_PCIE_PHY_CTRL_rx_spare_l0 0xA02F |
| #define B16PCIE_PHY_CTRL_rx_spare_l0 0xA02E |
| #define LSb32PCIE_PHY_CTRL_rx_spare_l0 24 |
| #define LSb16PCIE_PHY_CTRL_rx_spare_l0 8 |
| #define bPCIE_PHY_CTRL_rx_spare_l0 4 |
| #define MSK32PCIE_PHY_CTRL_rx_spare_l0 0x0F000000 |
| |
| #define BA_PCIE_PHY_CTRL_rxtx_parlpbk_l0 0xA02F |
| #define B16PCIE_PHY_CTRL_rxtx_parlpbk_l0 0xA02E |
| #define LSb32PCIE_PHY_CTRL_rxtx_parlpbk_l0 28 |
| #define LSb16PCIE_PHY_CTRL_rxtx_parlpbk_l0 12 |
| #define bPCIE_PHY_CTRL_rxtx_parlpbk_l0 1 |
| #define MSK32PCIE_PHY_CTRL_rxtx_parlpbk_l0 0x10000000 |
| |
| #define BA_PCIE_PHY_CTRL_rxtx_revlpbk_l0 0xA02F |
| #define B16PCIE_PHY_CTRL_rxtx_revlpbk_l0 0xA02E |
| #define LSb32PCIE_PHY_CTRL_rxtx_revlpbk_l0 29 |
| #define LSb16PCIE_PHY_CTRL_rxtx_revlpbk_l0 13 |
| #define bPCIE_PHY_CTRL_rxtx_revlpbk_l0 1 |
| #define MSK32PCIE_PHY_CTRL_rxtx_revlpbk_l0 0x20000000 |
| |
| #define BA_PCIE_PHY_CTRL_txrx_lpbk_l0 0xA02F |
| #define B16PCIE_PHY_CTRL_txrx_lpbk_l0 0xA02E |
| #define LSb32PCIE_PHY_CTRL_txrx_lpbk_l0 30 |
| #define LSb16PCIE_PHY_CTRL_txrx_lpbk_l0 14 |
| #define bPCIE_PHY_CTRL_txrx_lpbk_l0 1 |
| #define MSK32PCIE_PHY_CTRL_txrx_lpbk_l0 0x40000000 |
| |
| #define BA_PCIE_PHY_CTRL_rcv_det_override_value 0xA02F |
| #define B16PCIE_PHY_CTRL_rcv_det_override_value 0xA02E |
| #define LSb32PCIE_PHY_CTRL_rcv_det_override_value 31 |
| #define LSb16PCIE_PHY_CTRL_rcv_det_override_value 15 |
| #define bPCIE_PHY_CTRL_rcv_det_override_value 1 |
| #define MSK32PCIE_PHY_CTRL_rcv_det_override_value 0x80000000 |
| |
| #define RA_PCIE_PHY_CTRL1 0xA030 |
| |
| #define BA_PCIE_PHY_CTRL_force_rcv_detect 0xA030 |
| #define B16PCIE_PHY_CTRL_force_rcv_detect 0xA030 |
| #define LSb32PCIE_PHY_CTRL_force_rcv_detect 0 |
| #define LSb16PCIE_PHY_CTRL_force_rcv_detect 0 |
| #define bPCIE_PHY_CTRL_force_rcv_detect 1 |
| #define MSK32PCIE_PHY_CTRL_force_rcv_detect 0x00000001 |
| |
| #define BA_PCIE_PHY_CTRL_force_rx_param 0xA030 |
| #define B16PCIE_PHY_CTRL_force_rx_param 0xA030 |
| #define LSb32PCIE_PHY_CTRL_force_rx_param 1 |
| #define LSb16PCIE_PHY_CTRL_force_rx_param 1 |
| #define bPCIE_PHY_CTRL_force_rx_param 1 |
| #define MSK32PCIE_PHY_CTRL_force_rx_param 0x00000002 |
| |
| #define BA_PCIE_PHY_CTRL_force_tx_margin_comm 0xA030 |
| #define B16PCIE_PHY_CTRL_force_tx_margin_comm 0xA030 |
| #define LSb32PCIE_PHY_CTRL_force_tx_margin_comm 2 |
| #define LSb16PCIE_PHY_CTRL_force_tx_margin_comm 2 |
| #define bPCIE_PHY_CTRL_force_tx_margin_comm 1 |
| #define MSK32PCIE_PHY_CTRL_force_tx_margin_comm 0x00000004 |
| |
| #define BA_PCIE_PHY_CTRL_force_tx_param 0xA030 |
| #define B16PCIE_PHY_CTRL_force_tx_param 0xA030 |
| #define LSb32PCIE_PHY_CTRL_force_tx_param 3 |
| #define LSb16PCIE_PHY_CTRL_force_tx_param 3 |
| #define bPCIE_PHY_CTRL_force_tx_param 1 |
| #define MSK32PCIE_PHY_CTRL_force_tx_param 0x00000008 |
| |
| #define BA_PCIE_PHY_CTRL_force_vcocal_start 0xA030 |
| #define B16PCIE_PHY_CTRL_force_vcocal_start 0xA030 |
| #define LSb32PCIE_PHY_CTRL_force_vcocal_start 4 |
| #define LSb16PCIE_PHY_CTRL_force_vcocal_start 4 |
| #define bPCIE_PHY_CTRL_force_vcocal_start 1 |
| #define MSK32PCIE_PHY_CTRL_force_vcocal_start 0x00000010 |
| |
| #define BA_PCIE_PHY_CTRL_ate_enable 0xA030 |
| #define B16PCIE_PHY_CTRL_ate_enable 0xA030 |
| #define LSb32PCIE_PHY_CTRL_ate_enable 5 |
| #define LSb16PCIE_PHY_CTRL_ate_enable 5 |
| #define bPCIE_PHY_CTRL_ate_enable 1 |
| #define MSK32PCIE_PHY_CTRL_ate_enable 0x00000020 |
| |
| #define BA_PCIE_PHY_CTRL_ate_clock_mdio_ahb 0xA030 |
| #define B16PCIE_PHY_CTRL_ate_clock_mdio_ahb 0xA030 |
| #define LSb32PCIE_PHY_CTRL_ate_clock_mdio_ahb 6 |
| #define LSb16PCIE_PHY_CTRL_ate_clock_mdio_ahb 6 |
| #define bPCIE_PHY_CTRL_ate_clock_mdio_ahb 1 |
| #define MSK32PCIE_PHY_CTRL_ate_clock_mdio_ahb 0x00000040 |
| |
| #define BA_PCIE_PHY_CTRL_ate_regresetn 0xA030 |
| #define B16PCIE_PHY_CTRL_ate_regresetn 0xA030 |
| #define LSb32PCIE_PHY_CTRL_ate_regresetn 7 |
| #define LSb16PCIE_PHY_CTRL_ate_regresetn 7 |
| #define bPCIE_PHY_CTRL_ate_regresetn 1 |
| #define MSK32PCIE_PHY_CTRL_ate_regresetn 0x00000080 |
| |
| #define BA_PCIE_PHY_CTRL_acjtag_en 0xA031 |
| #define B16PCIE_PHY_CTRL_acjtag_en 0xA030 |
| #define LSb32PCIE_PHY_CTRL_acjtag_en 8 |
| #define LSb16PCIE_PHY_CTRL_acjtag_en 8 |
| #define bPCIE_PHY_CTRL_acjtag_en 1 |
| #define MSK32PCIE_PHY_CTRL_acjtag_en 0x00000100 |
| |
| #define BA_PCIE_PHY_CTRL_jtagos 0xA031 |
| #define B16PCIE_PHY_CTRL_jtagos 0xA030 |
| #define LSb32PCIE_PHY_CTRL_jtagos 9 |
| #define LSb16PCIE_PHY_CTRL_jtagos 9 |
| #define bPCIE_PHY_CTRL_jtagos 2 |
| #define MSK32PCIE_PHY_CTRL_jtagos 0x00000600 |
| |
| #define BA_PCIE_PHY_CTRL_iddqn 0xA031 |
| #define B16PCIE_PHY_CTRL_iddqn 0xA030 |
| #define LSb32PCIE_PHY_CTRL_iddqn 11 |
| #define LSb16PCIE_PHY_CTRL_iddqn 11 |
| #define bPCIE_PHY_CTRL_iddqn 1 |
| #define MSK32PCIE_PHY_CTRL_iddqn 0x00000800 |
| |
| #define BA_PCIE_PHY_CTRL_phy_dbg_sel 0xA031 |
| #define B16PCIE_PHY_CTRL_phy_dbg_sel 0xA030 |
| #define LSb32PCIE_PHY_CTRL_phy_dbg_sel 12 |
| #define LSb16PCIE_PHY_CTRL_phy_dbg_sel 12 |
| #define bPCIE_PHY_CTRL_phy_dbg_sel 1 |
| #define MSK32PCIE_PHY_CTRL_phy_dbg_sel 0x00001000 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCIE_PHY_STS 0xA034 |
| |
| #define BA_PCIE_PHY_STS_o_pll_rdy 0xA034 |
| #define B16PCIE_PHY_STS_o_pll_rdy 0xA034 |
| #define LSb32PCIE_PHY_STS_o_pll_rdy 0 |
| #define LSb16PCIE_PHY_STS_o_pll_rdy 0 |
| #define bPCIE_PHY_STS_o_pll_rdy 1 |
| #define MSK32PCIE_PHY_STS_o_pll_rdy 0x00000001 |
| |
| #define BA_PCIE_PHY_STS_phy_config_done 0xA034 |
| #define B16PCIE_PHY_STS_phy_config_done 0xA034 |
| #define LSb32PCIE_PHY_STS_phy_config_done 1 |
| #define LSb16PCIE_PHY_STS_phy_config_done 1 |
| #define bPCIE_PHY_STS_phy_config_done 1 |
| #define MSK32PCIE_PHY_STS_phy_config_done 0x00000002 |
| |
| #define BA_PCIE_PHY_STS_o_tx_spare 0xA034 |
| #define B16PCIE_PHY_STS_o_tx_spare 0xA034 |
| #define LSb32PCIE_PHY_STS_o_tx_spare 2 |
| #define LSb16PCIE_PHY_STS_o_tx_spare 2 |
| #define bPCIE_PHY_STS_o_tx_spare 3 |
| #define MSK32PCIE_PHY_STS_o_tx_spare 0x0000001C |
| |
| #define BA_PCIE_PHY_STS_o_rx_spare 0xA034 |
| #define B16PCIE_PHY_STS_o_rx_spare 0xA034 |
| #define LSb32PCIE_PHY_STS_o_rx_spare 5 |
| #define LSb16PCIE_PHY_STS_o_rx_spare 5 |
| #define bPCIE_PHY_STS_o_rx_spare 4 |
| #define MSK32PCIE_PHY_STS_o_rx_spare 0x000001E0 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCIE_HWDBG_CTRL 0xA038 |
| |
| #define BA_PCIE_HWDBG_CTRL_PCIESEL 0xA038 |
| #define B16PCIE_HWDBG_CTRL_PCIESEL 0xA038 |
| #define LSb32PCIE_HWDBG_CTRL_PCIESEL 0 |
| #define LSb16PCIE_HWDBG_CTRL_PCIESEL 0 |
| #define bPCIE_HWDBG_CTRL_PCIESEL 2 |
| #define MSK32PCIE_HWDBG_CTRL_PCIESEL 0x00000003 |
| |
| #define BA_PCIE_HWDBG_CTRL_DATASEL 0xA038 |
| #define B16PCIE_HWDBG_CTRL_DATASEL 0xA038 |
| #define LSb32PCIE_HWDBG_CTRL_DATASEL 2 |
| #define LSb16PCIE_HWDBG_CTRL_DATASEL 2 |
| #define bPCIE_HWDBG_CTRL_DATASEL 1 |
| #define MSK32PCIE_HWDBG_CTRL_DATASEL 0x00000004 |
| |
| #define BA_PCIE_HWDBG_CTRL_SIGSEL 0xA038 |
| #define B16PCIE_HWDBG_CTRL_SIGSEL 0xA038 |
| #define LSb32PCIE_HWDBG_CTRL_SIGSEL 3 |
| #define LSb16PCIE_HWDBG_CTRL_SIGSEL 3 |
| #define bPCIE_HWDBG_CTRL_SIGSEL 8 |
| #define MSK32PCIE_HWDBG_CTRL_SIGSEL 0x000007F8 |
| /////////////////////////////////////////////////////////// |
| #define RA_PCIE_HWDBG_DATA 0xA03C |
| |
| #define BA_PCIE_HWDBG_DATA_VAL 0xA03C |
| #define B16PCIE_HWDBG_DATA_VAL 0xA03C |
| #define LSb32PCIE_HWDBG_DATA_VAL 0 |
| #define LSb16PCIE_HWDBG_DATA_VAL 0 |
| #define bPCIE_HWDBG_DATA_VAL 32 |
| #define MSK32PCIE_HWDBG_DATA_VAL 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_PCIE_AXI_LIMIT_LOWER 0xA040 |
| |
| #define BA_PCIE_AXI_LIMIT_LOWER_ADDR_FILTER_LOWER 0xA040 |
| #define B16PCIE_AXI_LIMIT_LOWER_ADDR_FILTER_LOWER 0xA040 |
| #define LSb32PCIE_AXI_LIMIT_LOWER_ADDR_FILTER_LOWER 0 |
| #define LSb16PCIE_AXI_LIMIT_LOWER_ADDR_FILTER_LOWER 0 |
| #define bPCIE_AXI_LIMIT_LOWER_ADDR_FILTER_LOWER 32 |
| #define MSK32PCIE_AXI_LIMIT_LOWER_ADDR_FILTER_LOWER 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_PCIE_AXI_LIMIT_UPPER 0xA044 |
| |
| #define BA_PCIE_AXI_LIMIT_UPPER_ADDR_FILTER_UPPER 0xA044 |
| #define B16PCIE_AXI_LIMIT_UPPER_ADDR_FILTER_UPPER 0xA044 |
| #define LSb32PCIE_AXI_LIMIT_UPPER_ADDR_FILTER_UPPER 0 |
| #define LSb16PCIE_AXI_LIMIT_UPPER_ADDR_FILTER_UPPER 0 |
| #define bPCIE_AXI_LIMIT_UPPER_ADDR_FILTER_UPPER 32 |
| #define MSK32PCIE_AXI_LIMIT_UPPER_ADDR_FILTER_UPPER 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_PCIE_SPARE_0 0xA048 |
| |
| #define BA_PCIE_SPARE_0_REGBITS 0xA048 |
| #define B16PCIE_SPARE_0_REGBITS 0xA048 |
| #define LSb32PCIE_SPARE_0_REGBITS 0 |
| #define LSb16PCIE_SPARE_0_REGBITS 0 |
| #define bPCIE_SPARE_0_REGBITS 32 |
| #define MSK32PCIE_SPARE_0_REGBITS 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_PCIE_SPARE_1 0xA04C |
| |
| #define BA_PCIE_SPARE_1_REGBITS 0xA04C |
| #define B16PCIE_SPARE_1_REGBITS 0xA04C |
| #define LSb32PCIE_SPARE_1_REGBITS 0 |
| #define LSb16PCIE_SPARE_1_REGBITS 0 |
| #define bPCIE_SPARE_1_REGBITS 32 |
| #define MSK32PCIE_SPARE_1_REGBITS 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_PCIE_SPARE_2 0xA050 |
| |
| #define BA_PCIE_SPARE_2_REGBITS 0xA050 |
| #define B16PCIE_SPARE_2_REGBITS 0xA050 |
| #define LSb32PCIE_SPARE_2_REGBITS 0 |
| #define LSb16PCIE_SPARE_2_REGBITS 0 |
| #define bPCIE_SPARE_2_REGBITS 32 |
| #define MSK32PCIE_SPARE_2_REGBITS 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| #define RA_PCIE_SPARE_3 0xA054 |
| |
| #define BA_PCIE_SPARE_3_REGBITS 0xA054 |
| #define B16PCIE_SPARE_3_REGBITS 0xA054 |
| #define LSb32PCIE_SPARE_3_REGBITS 0 |
| #define LSb16PCIE_SPARE_3_REGBITS 0 |
| #define bPCIE_SPARE_3_REGBITS 32 |
| #define MSK32PCIE_SPARE_3_REGBITS 0xFFFFFFFF |
| /////////////////////////////////////////////////////////// |
| |
| #endif |
