| /* | 
 |  * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ | 
 |  * | 
 |  * This program is free software; you can redistribute it and/or modify | 
 |  * it under the terms of the GNU General Public License version 2 as | 
 |  * published by the Free Software Foundation. | 
 |  * Based on "omap4.dtsi" | 
 |  */ | 
 |  | 
 | #include "dra7.dtsi" | 
 |  | 
 | / { | 
 | 	compatible = "ti,dra742", "ti,dra74", "ti,dra7"; | 
 |  | 
 | 	cpus { | 
 | 		#address-cells = <1>; | 
 | 		#size-cells = <0>; | 
 |  | 
 | 		cpu0: cpu@0 { | 
 | 			device_type = "cpu"; | 
 | 			compatible = "arm,cortex-a15"; | 
 | 			reg = <0>; | 
 |  | 
 | 			operating-points = < | 
 | 				/* kHz    uV */ | 
 | 				1000000	1060000 | 
 | 				1176000	1160000 | 
 | 				>; | 
 |  | 
 | 			clocks = <&dpll_mpu_ck>; | 
 | 			clock-names = "cpu"; | 
 |  | 
 | 			clock-latency = <300000>; /* From omap-cpufreq driver */ | 
 |  | 
 | 			/* cooling options */ | 
 | 			cooling-min-level = <0>; | 
 | 			cooling-max-level = <2>; | 
 | 			#cooling-cells = <2>; /* min followed by max */ | 
 | 		}; | 
 | 		cpu@1 { | 
 | 			device_type = "cpu"; | 
 | 			compatible = "arm,cortex-a15"; | 
 | 			reg = <1>; | 
 | 		}; | 
 | 	}; | 
 |  | 
 | 	pmu { | 
 | 		compatible = "arm,cortex-a15-pmu"; | 
 | 		interrupt-parent = <&wakeupgen>; | 
 | 		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, | 
 | 			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; | 
 | 	}; | 
 |  | 
 | 	ocp { | 
 | 		omap_dwc3_4: omap_dwc3_4@48940000 { | 
 | 			compatible = "ti,dwc3"; | 
 | 			ti,hwmods = "usb_otg_ss4"; | 
 | 			reg = <0x48940000 0x10000>; | 
 | 			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; | 
 | 			#address-cells = <1>; | 
 | 			#size-cells = <1>; | 
 | 			utmi-mode = <2>; | 
 | 			ranges; | 
 | 			status = "disabled"; | 
 | 			usb4: usb@48950000 { | 
 | 				compatible = "snps,dwc3"; | 
 | 				reg = <0x48950000 0x17000>; | 
 | 				interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; | 
 | 				tx-fifo-resize; | 
 | 				maximum-speed = "high-speed"; | 
 | 				dr_mode = "otg"; | 
 | 			}; | 
 | 		}; | 
 | 	}; | 
 | }; | 
 |  | 
 | &dss { | 
 | 	reg = <0x58000000 0x80>, | 
 | 	      <0x58004054 0x4>, | 
 | 	      <0x58004300 0x20>, | 
 | 	      <0x58005054 0x4>, | 
 | 	      <0x58005300 0x20>; | 
 | 	reg-names = "dss", "pll1_clkctrl", "pll1", | 
 | 		    "pll2_clkctrl", "pll2"; | 
 |  | 
 | 	clocks = <&dss_dss_clk>, | 
 | 		 <&dss_video1_clk>, | 
 | 		 <&dss_video2_clk>; | 
 | 	clock-names = "fck", "video1_clk", "video2_clk"; | 
 | }; |