| Exynos Display port controller | 
 | ============================== | 
 |  | 
 | Required properties: | 
 | SOC specific: | 
 | 	compatible: should be "samsung,exynos5-dp" | 
 | 	reg: Base address of DP IP | 
 |  | 
 | Optional properties: | 
 | 	samsung,h-res: X resolution of the panel | 
 | 	samsung,h-sync-width: hsync value | 
 | 	samsung,h-back-porch: left margin | 
 | 	samsung,h-front-porch right margin | 
 | 	samsung,v-res: Y resolution of the panel | 
 | 	samsung,v-sync-width: vsync value | 
 | 	samsung,v-back-porch: upper margin | 
 | 	samsung,v-front-porch: lower margin | 
 | 	samsung,v-sync-rate: refresh rate | 
 |  | 
 | 	samsung,lt-status: Link training status | 
 | 		0(DP_LT_NONE), 1(DP_LT_START), 2(DP_LT_CR), 3(DP_LT_ET), | 
 | 		4(DP_LT_FINISHED), 5(DP_LT_FAIL) | 
 |  | 
 | 	samsung,master-mode: 1 if you want to run DP as master, else 0 | 
 | 	samsung,bist-mode: 1 to enable video bist mode, else 0 | 
 | 	samsung,bist-pattern: bist mode pattern type | 
 | 		0(NO_PATTERN), 1(COLOR_RAMP), 2(BALCK_WHITE_V_LINES), | 
 | 		3(COLOR_SQUARE), 4(INVALID_PATTERN), 5(COLORBAR_32), | 
 | 		6(COLORBAR_64),7(WHITE_GRAY_BALCKBAR_32), | 
 | 		8(WHITE_GRAY_BALCKBAR_64),9(MOBILE_WHITEBAR_32), | 
 | 		10(MOBILE_WHITEBAR_64) | 
 | 	samsung,h-sync-polarity: Horizontal Sync polarity | 
 | 			CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH | 
 | 	samsung,v-sync-polarity: Vertical Sync polarity | 
 | 			CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH | 
 | 	samsung,interlaced: Progressive if 0, else Interlaced | 
 | 	samsung,color-space: input video data format | 
 | 		COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2 | 
 | 	samsung,dynamic-range: dynamic range for input video data | 
 | 		VESA = 0, CEA = 1 | 
 | 	samsung,ycbcr-coeff: YCbCr co-efficients for input video | 
 | 		COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1 | 
 | 	samsung,color-depth: number of bits per colour component | 
 | 		COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3 | 
 |  | 
 | Example: | 
 | SOC specific part: | 
 | 	dp@145b0000 { | 
 | 		compatible = "samsung,exynos5-dp"; | 
 | 		reg = <0x145b0000 0x1000>; | 
 | 		#address-cells = <1>; | 
 | 		#size-cells = <1>; | 
 | 	}; | 
 |  | 
 | Board(panel) specific part: | 
 | 	dp@145b0000 { | 
 | 		samsung,lt-status = <0>; | 
 |  | 
 | 		samsung,master-mode = <0>; | 
 | 		samsung,bist-mode = <0>; | 
 | 		samsung,bist-pattern = <0>; | 
 | 		samsung,h-sync-polarity = <0>; | 
 | 		samsung,v-sync-polarity = <0>; | 
 | 		samsung,interlaced = <0>; | 
 | 		samsung,color-space = <0>; | 
 | 		samsung,dynamic-range = <0>; | 
 | 		samsung,ycbcr-coeff = <0>; | 
 | 		samsung,color-depth = <1>; | 
 | 	}; |