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<h4 class="subsection">3.17.1 AArch64 Options</h4>
<p><a name="index-AArch64-Options-1079"></a>
These options are defined for AArch64 implementations:
<dl>
<dt><code>-mbig-endian</code><dd><a name="index-mbig_002dendian-1080"></a>Generate big-endian code. This is the default when GCC is configured for an
&lsquo;<samp><span class="samp">aarch64_be-*-*</span></samp>&rsquo; target.
<br><dt><code>-mgeneral-regs-only</code><dd><a name="index-mgeneral_002dregs_002donly-1081"></a>Generate code which uses only the general registers.
<br><dt><code>-mlittle-endian</code><dd><a name="index-mlittle_002dendian-1082"></a>Generate little-endian code. This is the default when GCC is configured for an
&lsquo;<samp><span class="samp">aarch64-*-*</span></samp>&rsquo; but not an &lsquo;<samp><span class="samp">aarch64_be-*-*</span></samp>&rsquo; target.
<br><dt><code>-mcmodel=tiny</code><dd><a name="index-mcmodel_003dtiny-1083"></a>Generate code for the tiny code model. The program and its statically defined
symbols must be within 1GB of each other. Pointers are 64 bits. Programs can
be statically or dynamically linked. This model is not fully implemented and
mostly treated as &lsquo;<samp><span class="samp">small</span></samp>&rsquo;.
<br><dt><code>-mcmodel=small</code><dd><a name="index-mcmodel_003dsmall-1084"></a>Generate code for the small code model. The program and its statically defined
symbols must be within 4GB of each other. Pointers are 64 bits. Programs can
be statically or dynamically linked. This is the default code model.
<br><dt><code>-mcmodel=large</code><dd><a name="index-mcmodel_003dlarge-1085"></a>Generate code for the large code model. This makes no assumptions about
addresses and sizes of sections. Pointers are 64 bits. Programs can be
statically linked only.
<br><dt><code>-mstrict-align</code><dd><a name="index-mstrict_002dalign-1086"></a>Do not assume that unaligned memory references will be handled by the system.
<br><dt><code>-momit-leaf-frame-pointer</code><dt><code>-mno-omit-leaf-frame-pointer</code><dd><a name="index-momit_002dleaf_002dframe_002dpointer-1087"></a><a name="index-mno_002domit_002dleaf_002dframe_002dpointer-1088"></a>Omit or keep the frame pointer in leaf functions. The former behaviour is the
default.
<br><dt><code>-mtls-dialect=desc</code><dd><a name="index-mtls_002ddialect_003ddesc-1089"></a>Use TLS descriptors as the thread-local storage mechanism for dynamic accesses
of TLS variables. This is the default.
<br><dt><code>-mtls-dialect=traditional</code><dd><a name="index-mtls_002ddialect_003dtraditional-1090"></a>Use traditional TLS as the thread-local storage mechanism for dynamic accesses
of TLS variables.
<br><dt><code>-march=</code><var>name</var><dd><a name="index-march-1091"></a>Specify the name of the target architecture, optionally suffixed by one or
more feature modifiers. This option has the form
<samp><span class="option">-march=</span><var>arch</var><span class="option">{+[no]</span><var>feature</var><span class="option">}*</span></samp>, where the
only value for <var>arch</var> is &lsquo;<samp><span class="samp">armv8-a</span></samp>&rsquo;. The possible values for
<var>feature</var> are documented in the sub-section below.
<p>Where conflicting feature modifiers are specified, the right-most feature is
used.
<p>GCC uses this name to determine what kind of instructions it can emit when
generating assembly code. This option can be used in conjunction with or
instead of the <samp><span class="option">-mcpu=</span></samp> option.
<br><dt><code>-mcpu=</code><var>name</var><dd><a name="index-mcpu-1092"></a>Specify the name of the target processor, optionally suffixed by one or more
feature modifiers. This option has the form
<samp><span class="option">-mcpu=</span><var>cpu</var><span class="option">{+[no]</span><var>feature</var><span class="option">}*</span></samp>, where the
possible values for <var>cpu</var> are &lsquo;<samp><span class="samp">generic</span></samp>&rsquo;, &lsquo;<samp><span class="samp">large</span></samp>&rsquo;. The
possible values for <var>feature</var> are documented in the sub-section
below.
<p>Where conflicting feature modifiers are specified, the right-most feature is
used.
<p>GCC uses this name to determine what kind of instructions it can emit when
generating assembly code.
<br><dt><code>-mtune=</code><var>name</var><dd><a name="index-mtune-1093"></a>Specify the name of the processor to tune the performance for. The code will
be tuned as if the target processor were of the type specified in this option,
but still using instructions compatible with the target processor specified
by a <samp><span class="option">-mcpu=</span></samp> option. This option cannot be suffixed by feature
modifiers.
</dl>
<h5 class="subsubsection">3.17.1.1 <samp><span class="option">-march</span></samp> and <samp><span class="option">-mcpu</span></samp> feature modifiers</h5>
<p><a name="index-g_t_0040option_007b_002dmarch_007d-feature-modifiers-1094"></a><a name="index-g_t_0040option_007b_002dmcpu_007d-feature-modifiers-1095"></a>Feature modifiers used with <samp><span class="option">-march</span></samp> and <samp><span class="option">-mcpu</span></samp> can be one
the following:
<dl>
<dt>&lsquo;<samp><span class="samp">crc</span></samp>&rsquo;<dd>Enable CRC extension.
<br><dt>&lsquo;<samp><span class="samp">crypto</span></samp>&rsquo;<dd>Enable Crypto extension. This implies Advanced SIMD is enabled.
<br><dt>&lsquo;<samp><span class="samp">fp</span></samp>&rsquo;<dd>Enable floating-point instructions.
<br><dt>&lsquo;<samp><span class="samp">simd</span></samp>&rsquo;<dd>Enable Advanced SIMD instructions. This implies floating-point instructions
are enabled. This is the default for all current possible values for options
<samp><span class="option">-march</span></samp> and <samp><span class="option">-mcpu=</span></samp>.
</dl>
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