Google Git
Sign in
nest-open-source / manifest_repos / kernel / 38bda478e46f3b6ec246861d597470685679add1 / . / arch / arm64 / boot / dts / amlogic / mesonp1.dtsi
blob: 2d6ae362629dea65ef0b6a82bb4a2c6cca4fc00b [file] [log] [blame]
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <dt-bindings/clock/p1-clkc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/p1-pd.h>
#include <dt-bindings/clock/amlogic,p1-audio-clk.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/meson-p1-gpio.h>
#include <dt-bindings/reset/amlogic,meson-p1-reset.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/pwm/meson.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/input/meson_ir.h>
#include <dt-bindings/mailbox/amlogic,mbox.h>
#include "meson-ir-map.dtsi"
#include "mesong12a-bifrost.dtsi"
#include <dt-bindings/memory/meson-p1-sid-map.h>
#include <dt-bindings/hwspinlock/amlogic,hwspinlock.h>
/ {
cpus:cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0:cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
core4 {
cpu = <&CPU4>;
};
core5 {
cpu = <&CPU5>;
};
core6 {
cpu = <&CPU6>;
};
core7 {
cpu = <&CPU7>;
};
};
};
CPU0:cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55","arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
#cooling-cells = <2>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_DYN_CLK>,
<&clkc CLKID_SYS_PLL>,
<&clkc CLKID_DSU_CLK>,
<&clkc CLKID_DSU_DYN_CLK>,
<&clkc CLKID_GP1_PLL>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent",
"dsu_clk",
"dsu_pre_parent",
"dsu_pre_parent2";
operating-points-v2 = <&a55_opp_table0>;
voltage-tolerance = <0>;
clock-latency = <50000>;
capacity-dmips-mhz = <512>;
dynamic-power-coefficient = <1024>;
// #cooling-cells = <2>;
cpu-supply = <&VDD_CPUA>;
cpu_supply_external_used;
dsu-opp-table = <1200000 880000 1500000 940000>;
dsu_clock_shared;
dsu-low-rate = <1000000>;
// cpufreq_voltage_set_skip;
cpu_reg_use_buck;
dvfs_sibling_core_num = <6>;
dvfs_sibling_cores = <0 1 2 3 4 5>;
};
CPU1:cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a55","arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
// #cooling-cells = <2>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_DYN_CLK>,
<&clkc CLKID_SYS_PLL>,
<&clkc CLKID_DSU_CLK>,
<&clkc CLKID_DSU_DYN_CLK>,
<&clkc CLKID_GP1_PLL>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent",
"dsu_clk",
"dsu_pre_parent",
"dsu_pre_parent2";
operating-points-v2 = <&a55_opp_table0>;
voltage-tolerance = <0>;
// clock-latency = <50000>;
capacity-dmips-mhz = <512>;
dynamic-power-coefficient = <1024>;
// #cooling-cells = <2>;
cpu-supply = <&VDD_CPUA>;
cpu_supply_external_used;
dsu-opp-table = <1200000 880000 1500000 940000>;
dsu_clock_shared;
dsu-low-rate = <1000000>;
// cpufreq_voltage_set_skip;
cpu_reg_use_buck;
dvfs_sibling_core_num = <6>;
dvfs_sibling_cores = <0 1 2 3 4 5>;
};
CPU2:cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a55","arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
// #cooling-cells = <2>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_DYN_CLK>,
<&clkc CLKID_SYS_PLL>,
<&clkc CLKID_DSU_CLK>,
<&clkc CLKID_DSU_DYN_CLK>,
<&clkc CLKID_GP1_PLL>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent",
"dsu_clk",
"dsu_pre_parent",
"dsu_pre_parent2";
operating-points-v2 = <&a55_opp_table0>;
voltage-tolerance = <0>;
// clock-latency = <50000>;
capacity-dmips-mhz = <512>;
dynamic-power-coefficient = <1024>;
// #cooling-cells = <2>;
cpu-supply = <&VDD_CPUA>;
cpu_supply_external_used;
dsu-opp-table = <1200000 880000 1500000 940000>;
dsu_clock_shared;
dsu-low-rate = <1000000>;
// cpufreq_voltage_set_skip;
cpu_reg_use_buck;
dvfs_sibling_core_num = <6>;
dvfs_sibling_cores = <0 1 2 3 4 5>;
};
CPU3:cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a55","arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
// #cooling-cells = <2>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_DYN_CLK>,
<&clkc CLKID_SYS_PLL>,
<&clkc CLKID_DSU_CLK>,
<&clkc CLKID_DSU_DYN_CLK>,
<&clkc CLKID_GP1_PLL>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent",
"dsu_clk",
"dsu_pre_parent",
"dsu_pre_parent2";
operating-points-v2 = <&a55_opp_table0>;
voltage-tolerance = <0>;
// clock-latency = <50000>;
capacity-dmips-mhz = <512>;
dynamic-power-coefficient = <1024>;
// #cooling-cells = <2>;
cpu-supply = <&VDD_CPUA>;
cpu_supply_external_used;
dsu-opp-table = <1200000 880000 1500000 940000>;
dsu_clock_shared;
dsu-low-rate = <1000000>;
// cpufreq_voltage_set_skip;
cpu_reg_use_buck;
dvfs_sibling_core_num = <6>;
dvfs_sibling_cores = <0 1 2 3 4 5>;
};
CPU4:cpu@4 {
device_type = "cpu";
compatible = "arm,cortex-a55","arm,armv8";
reg = <0x0 0x4>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
// #cooling-cells = <2>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_DYN_CLK>,
<&clkc CLKID_SYS_PLL>,
<&clkc CLKID_DSU_CLK>,
<&clkc CLKID_DSU_DYN_CLK>,
<&clkc CLKID_GP1_PLL>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent",
"dsu_clk",
"dsu_pre_parent",
"dsu_pre_parent2";
operating-points-v2 = <&a55_opp_table0>;
voltage-tolerance = <0>;
// clock-latency = <50000>;
capacity-dmips-mhz = <512>;
dynamic-power-coefficient = <1024>;
// #cooling-cells = <2>;
cpu-supply = <&VDD_CPUA>;
cpu_supply_external_used;
dsu-opp-table = <1200000 880000 1500000 940000>;
dsu_clock_shared;
dsu-low-rate = <1000000>;
// cpufreq_voltage_set_skip;
cpu_reg_use_buck;
dvfs_sibling_core_num = <6>;
dvfs_sibling_cores = <0 1 2 3 4 5>;
};
CPU5:cpu@5{
device_type = "cpu";
compatible = "arm,cortex-a55","arm,armv8";
reg = <0x0 0x5>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
// #cooling-cells = <2>;
clocks = <&clkc CLKID_CPU_CLK>,
<&clkc CLKID_CPU_DYN_CLK>,
<&clkc CLKID_SYS_PLL>,
<&clkc CLKID_DSU_CLK>,
<&clkc CLKID_DSU_DYN_CLK>,
<&clkc CLKID_GP1_PLL>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent",
"dsu_clk",
"dsu_pre_parent",
"dsu_pre_parent2";
operating-points-v2 = <&a55_opp_table0>;
voltage-tolerance = <0>;
// clock-latency = <50000>;
capacity-dmips-mhz = <512>;
dynamic-power-coefficient = <1024>;
// #cooling-cells = <2>;
cpu-supply = <&VDD_CPUA>;
cpu_supply_external_used;
dsu-opp-table = <1200000 880000 1500000 940000>;
dsu_clock_shared;
dsu-low-rate = <1000000>;
// cpufreq_voltage_set_skip;
cpu_reg_use_buck;
dvfs_sibling_core_num = <6>;
dvfs_sibling_cores = <0 1 2 3 4 5>;
};
CPU6:cpu@6 {
device_type = "cpu";
compatible = "arm,cortex-a76","arm,armv8";
reg = <0x0 0x6>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
#cooling-cells = <2>;
clocks = <&clkc CLKID_A76_CLK>,
<&clkc CLKID_A76_DYN_CLK>,
<&clkc CLKID_SYS1_PLL>,
<&clkc CLKID_DSU_CLK>,
<&clkc CLKID_DSU_DYN_CLK>,
<&clkc CLKID_GP1_PLL>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent",
"dsu_clk",
"dsu_pre_parent",
"dsu_pre_parent2";
operating-points-v2 = <&a76_opp_table0>;
voltage-tolerance = <0>;
// clock-latency = <50000>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <512>;
// #cooling-cells = <2>;
cpu-supply = <&VDD_CPUB>;
dsu-supply = <&VDD_CPUA>;
dsu-opp-table = <1200000 870000 1500000 910000>;
dsu_clock_shared;
dsu-low-rate = <1000000>;
// cpufreq_voltage_set_skip;
cpu_reg_use_buck;
dvfs_sibling_core_num = <2>;
dvfs_sibling_cores = <6 7>;
};
CPU7:cpu@7 {
device_type = "cpu";
compatible = "arm,cortex-a76","arm,armv8";
reg = <0x0 0x7>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &SYSTEM_SLEEP_0>;
// #cooling-cells = <2>;
clocks = <&clkc CLKID_A76_CLK>,
<&clkc CLKID_A76_DYN_CLK>,
<&clkc CLKID_SYS1_PLL>,
<&clkc CLKID_DSU_CLK>,
<&clkc CLKID_DSU_DYN_CLK>,
<&clkc CLKID_GP1_PLL>;
clock-names = "core_clk",
"low_freq_clk_parent",
"high_freq_clk_parent",
"dsu_clk",
"dsu_pre_parent",
"dsu_pre_parent2";
operating-points-v2 = <&a76_opp_table0>;
voltage-tolerance = <0>;
// clock-latency = <50000>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <512>;
// #cooling-cells = <2>;
cpu-supply = <&VDD_CPUB>;
dsu-supply = <&VDD_CPUA>;
dsu-opp-table = <1200000 870000 1500000 910000>;
dsu_clock_shared;
dsu-low-rate = <1000000>;
// cpufreq_voltage_set_skip;
cpu_reg_use_buck;
dvfs_sibling_core_num = <2>;
dvfs_sibling_cores = <6 7>;
};
idle-states {
entry-method = "arm,psci-0.2";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
local-timer-stop;
entry-latency-us = <4000>;
exit-latency-us = <5000>;
min-residency-us = <10000>;
};
SYSTEM_SLEEP_0: system-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0000000>;
entry-latency-us = <0x3fffffff>;
exit-latency-us = <0x40000000>;
min-residency-us = <0xffffffff>;
};
};
};
dsu-pmu-0 {
compatible = "arm,dsu-pmu";
status = "okay";
cpus = <&CPU0>,<&CPU1>,<&CPU2>,<&CPU3>,<&CPU4>,<&CPU5>;
interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 0xff08>,
<GIC_PPI 14 0xff08>,
<GIC_PPI 11 0xff08>,
<GIC_PPI 10 0xff08>;
};
timer_bc {
/*compatible = "amlogic,bc-timer";*/
reg= <0x0 0xfe0100D8 0x0 0x4 0x0 0xfe0100DC 0x0 0x4>;
timer_name = "Meson TimerD";
clockevent-rating=<300>;
clockevent-shift=<20>;
clockevent-features=<0x23>;
interrupts = <0 3 1>;
bit_enable=<7>;
bit_mode=<6>;
bit_resolution=<0>;
resolution_1us=<1>;
min_delta_ns=<10>;
};
arm_pmu {
compatible = "arm,armv8-pmuv3";
private-interrupts;
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@fff01000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xfff01000 0 0x1000>,
<0x0 0xfff02000 0 0x0100>;
interrupts = <GIC_PPI 9 0xf04>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
meson_suspend:pm {
compatible = "amlogic, pm";
status = "disabled";
device_name = "aml_pm";
reg = <0x0 0xfe010288 0x0 0x4>, /*SYSCTRL_STATUS_REG2*/
<0x0 0xfe0102dc 0x0 0x4>; /*SYSCTRL_STICKY_REG7*/
};
aml_reboot {
compatible = "aml, reboot";
sys_reset = <0x84000009>;
sys_poweroff = <0x84000008>;
dis_nb_cpus_in_shutdown;
};
secmon {
compatible = "amlogic, secmon";
memory-region = <&secmon_reserved>;
in_base_func = <0x82000020>;
out_base_func = <0x82000021>;
reserve_mem_size = <0x00400000>;
clear_range = <0x05100000 0x200000>;
};
cma_shrinker: cma_shrinker {
compatible = "amlogic, cma-shrinker";
status = "disabled";
adj = <0 100 200 250 900 950>;
free = <8192 12288 16384 24576 28672 32768>;
};
xtal: xtal-clk {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xtal";
#clock-cells = <0>;
};
smmu: smmu@fe600000 {
compatible = "arm,smmu-v3";
status = "okay";
reg = <0x0 0xfe600000 0x0 0x200000
0x0 0xfe098000 0x0 0x80
0x0 0xfe098140 0x0 0x74>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "combined";
smc_irq_cmd = <0x82000078>;
#iommu-cells = <1>;
};
cpu_info {
compatible = "amlogic, cpuinfo";
status = "okay";
cpuinfo_cmd = <0x82000044>;
};
vrtc: rtc@0xfe010288 {
compatible = "amlogic,meson-vrtc";
reg = <0x0 0xfe010288 0x0 0x4>;
status = "okay";
mboxes = <&mhu_fifo P1_REE2AO>;
};
pwrdm: power-domains {
compatible = "amlogic,p1-power-domain";
#power-domain-cells = <1>;
status = "okay";
};
nna_top_ports_wrapper_0: nna_top_ports_wrapper@fe370000 {
compatible = "amazon,nna-1.0";
device-name = "acenna0";
status = "okay";
clocks = <&clkc CLKID_NNA0>;
assigned-clocks =<&clkc CLKID_NNA0>;
assigned-clock-parentsd = <&clkc CLKID_FCLK_DIV2P5>;
assigned-clock-rates = <800000000>;
clock-names = "nna_clk_gate";
interrupt-names = "nna_interrupt";
interrupts = <0 148 1>;
minor-number = <0>;
power-domains = <&pwrdm PDID_P1_NNA_A>,
<&pwrdm PDID_P1_NNA_TOP>;
power-domain-names = "pwrc-core","pwrc-top";
reg = <0x0 0xfe370000 0x0 0x1000>;
reg-names = "nna_irq_wrapper";
};
nna_top_ports_wrapper_1: nna_top_ports_wrapper@fe371000 {
compatible = "amazon,nna-1.0";
device-name = "acenna1";
status = "okay";
clocks = <&clkc CLKID_NNA1>;
assigned-clocks =<&clkc CLKID_NNA1>;
assigned-clock-parentsd = <&clkc CLKID_FCLK_DIV2P5>;
assigned-clock-rates = <800000000>;
clock-names = "nna_clk_gate";
interrupt-names = "nna_interrupt";
interrupts = <0 149 1>;
minor-number = <1>;
power-domains = <&pwrdm PDID_P1_NNA_B>,
<&pwrdm PDID_P1_NNA_TOP>;
power-domain-names = "pwrc-core","pwrc-top";
reg = <0x0 0xfe371000 0x0 0x1000>;
reg-names = "nna_irq_wrapper";
};
nna_top_ports_wrapper_2: nna_top_ports_wrapper@fe372000 {
compatible = "amazon,nna-1.0";
device-name = "acenna2";
status = "okay";
clocks = <&clkc CLKID_NNA2>;
assigned-clocks =<&clkc CLKID_NNA2>;
assigned-clock-parentsd = <&clkc CLKID_FCLK_DIV2P5>;
assigned-clock-rates = <800000000>;
clock-names = "nna_clk_gate";
interrupt-names = "nna_interrupt";
interrupts = <0 150 1>;
minor-number = <2>;
power-domains = <&pwrdm PDID_P1_NNA_C>,
<&pwrdm PDID_P1_NNA_TOP>;
power-domain-names = "pwrc-core","pwrc-top";
reg = <0x0 0xfe372000 0x0 0x1000>;
reg-names = "nna_irq_wrapper";
};
nna_top_ports_wrapper_3: nna_top_ports_wrapper@fe373000 {
compatible = "amazon,nna-1.0";
device-name = "acenna3";
status = "okay";
clocks = <&clkc CLKID_NNA3>;
assigned-clocks =<&clkc CLKID_NNA3>;
assigned-clock-parentsd = <&clkc CLKID_FCLK_DIV2P5>;
assigned-clock-rates = <800000000>;
clock-names = "nna_clk_gate";
interrupt-names = "nna_interrupt";
interrupts = <0 151 1>;
minor-number = <3>;
power-domains = <&pwrdm PDID_P1_NNA_D>,
<&pwrdm PDID_P1_NNA_TOP>;
power-domain-names = "pwrc-core","pwrc-top";
reg = <0x0 0xfe373000 0x0 0x1000>;
reg-names = "nna_irq_wrapper";
};
nna_top_ports_wrapper_4: nna_top_ports_wrapper@fe374000 {
compatible = "amazon,nna-1.0";
device-name = "acenna4";
status = "okay";
clocks = <&clkc CLKID_NNA4>;
assigned-clocks =<&clkc CLKID_NNA4>;
assigned-clock-parentsd = <&clkc CLKID_FCLK_DIV2P5>;
assigned-clock-rates = <800000000>;
clock-names = "nna_clk_gate";
interrupt-names = "nna_interrupt";
interrupts = <0 152 1>;
minor-number = <4>;
power-domains = <&pwrdm PDID_P1_NNA_E>,
<&pwrdm PDID_P1_NNA_TOP>;
power-domain-names = "pwrc-core","pwrc-top";
reg = <0x0 0xfe374000 0x0 0x1000>;
reg-names = "nna_irq_wrapper";
};
nna_top_ports_wrapper_5: nna_top_ports_wrapper@fe375000 {
compatible = "amazon,nna-1.0";
device-name = "acenna5";
status = "okay";
clocks = <&clkc CLKID_NNA5>;
assigned-clocks =<&clkc CLKID_NNA5>;
assigned-clock-parentsd = <&clkc CLKID_FCLK_DIV2P5>;
assigned-clock-rates = <800000000>;
clock-names = "nna_clk_gate";
interrupt-names = "nna_interrupt";
interrupts = <0 153 1>;
minor-number = <5>;
power-domains = <&pwrdm PDID_P1_NNA_F>,
<&pwrdm PDID_P1_NNA_TOP>;
power-domain-names = "pwrc-core","pwrc-top";
reg = <0x0 0xfe375000 0x0 0x1000>;
reg-names = "nna_irq_wrapper";
};
jtag {
compatible = "amlogic, jtag";
status = "okay";
select = "disable"; /* disable/jtag_a */
//amlogic,support-jtag-trace;
pinctrl-names="jtag_a_pins", "jtag_trace_pins";
pinctrl-0=<&jtag_a_pins>;
pinctrl-1=<&jtag_trace_pins>;
};
hifi4dsp: hifi4dsp {
compatible = "amlogic, hifi4dsp";
memory-region = <&dsp_fw_reserved>;
reg = <0 0xfe340018 0 0x114>, /*dspa base address*/
<0 0xfe350018 0 0x114>, /*dspb base address*/
<0 0xfe010258 0 0x4>, /*dspa status counter*/
<0 0xfe01025c 0 0x4>, /*dspb status counter*/
<0 0x30820000 0 0x80000>; /*dsp shm region*/
dsp-monitor-period-ms = <1000>;
reg-names = "dspa_top_reg", "dspb_top_reg";
clocks = <&clkc CLKID_DSPA>, <&clkc CLKID_DSPB>;
clock-names = "dspa_clk", "dspb_clk";
dsp-start-mode = <1>; /*0:scpi start mode,1:smc start mode*/
dsp-cnt = <2>;
dspaoffset = <0x00000>;
dspboffset = <0x800000>;
bootlocation = <1>; /*1: boot from DDR, 2: from sram, 3...*/
boot_sram_addr = <0xfff00000>;
boot_sram_size = <0x80000>;
//dspsrambase = <0xf7100000>;
//dspsramsize = <0x100000>;
power-domains = <&pwrdm PDID_P1_DSPA>,
<&pwrdm PDID_P1_DSPB>;
power-domain-names = "dspa", "dspb";
status = "okay";
};
vddcpua: pwmao_d-regulator {
compatible = "pwm-regulator";
//pwms = <&pwmao_cd MESON_PWM_1 1500 0>;
regulator-name = "vddcpua";
regulator-min-microvolt = <689000>;
regulator-max-microvolt = <1049000>;
regulator-always-on;
max-duty-cycle = <1500>;
/* Voltage Duty-Cycle */
voltage-table = <1049000 0>,
<1039000 3>,
<1029000 6>,
<1019000 9>,
<1009000 12>,
<999000 14>,
<989000 17>,
<979000 20>,
<969000 23>,
<959000 26>,
<949000 29>,
<939000 31>,
<929000 34>,
<919000 37>,
<909000 40>,
<899000 43>,
<889000 45>,
<879000 48>,
<869000 51>,
<859000 54>,
<849000 56>,
<839000 59>,
<829000 62>,
<819000 65>,
<809000 68>,
<799000 70>,
<789000 73>,
<779000 76>,
<769000 79>,
<759000 81>,
<749000 84>,
<739000 87>,
<729000 89>,
<719000 92>,
<709000 95>,
<699000 98>,
<689000 100>;
status = "disabled";
};
vddcpub: pwmao_b-regulator {
compatible = "pwm-regulator";
//pwms = <&pwmao_ab MESON_PWM_1 1500 0>;
regulator-name = "vddcpub";
regulator-min-microvolt = <689000>;
regulator-max-microvolt = <1049000>;
regulator-always-on;
max-duty-cycle = <1500>;
/* Voltage Duty-Cycle */
voltage-table = <1049000 0>,
<1039000 3>,
<1029000 6>,
<1019000 9>,
<1009000 12>,
<999000 14>,
<989000 17>,
<979000 20>,
<969000 23>,
<959000 26>,
<949000 29>,
<939000 31>,
<929000 34>,
<919000 37>,
<909000 40>,
<899000 43>,
<889000 45>,
<879000 48>,
<869000 51>,
<859000 54>,
<849000 56>,
<839000 59>,
<829000 62>,
<819000 65>,
<809000 68>,
<799000 70>,
<789000 73>,
<779000 76>,
<769000 79>,
<759000 81>,
<749000 84>,
<739000 87>,
<729000 89>,
<719000 92>,
<709000 95>,
<699000 98>,
<689000 100>;
status = "disabled";
};
a76_opp_table0: a76_opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <840000>;
};
opp01 {
opp-hz = /bits/ 64 <666000000>;
opp-microvolt = <840000>;
};
opp02 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <850000>;
};
opp03 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <870000>;
};
opp04 {
opp-hz = /bits/ 64 <1392000000>;
opp-microvolt = <890000>;
};
opp05 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <910000>;
};
opp06 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <930000>;
};
opp07 {
opp-hz = /bits/ 64 <1704000000>;
opp-microvolt = <950000>;
};
opp08 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <970000>;
};
opp09 {
opp-hz = /bits/ 64 <1896000000>;
opp-microvolt = <990000>;
};
opp10 {
opp-hz = /bits/ 64 <1944000000>;
opp-microvolt = <1010000>;
};
};
a55_opp_table0: a55_opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <840000>;
};
opp01 {
opp-hz = /bits/ 64 <666000000>;
opp-microvolt = <840000>;
};
opp02 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <870000>;
};
opp03 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <880000>;
};
opp04 {
opp-hz = /bits/ 64 <1392000000>;
opp-microvolt = <920000>;
};
opp05 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <940000>;
};
opp06 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <960000>;
};
opp07 {
opp-hz = /bits/ 64 <1704000000>;
opp-microvolt = <980000>;
};
opp08 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <990000>;
};
opp09 {
opp-hz = /bits/ 64 <1896000000>;
opp-microvolt = <1000000>;
};
opp10 {
opp-hz = /bits/ 64 <1992000000>;
opp-microvolt = <1010000>;
};
};
cpufreq-meson {
compatible = "amlogic, cpufreq-meson";
status = "okay";
};
saradc: saradc@fe026000 {
compatible = "amlogic,meson-g12a-saradc",
"amlogic,meson-saradc";
status = "disabled";
#io-channel-cells = <1>;
clocks = <&xtal>,
<&clkc CLKID_SYS_CLK_SAR_ADC>,
<&clkc CLKID_SARADC>,
<&clkc CLKID_SARADC_SEL>;
clock-names = "clkin", "core",
"adc_clk", "adc_sel";
interrupts = <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>;
reg = <0x00 0xfe026000 0x00 0x48>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
apb4: apb4@fe000000 {
compatible = "simple-bus";
reg = <0x0 0xfe000000 0x0 0x480000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
status = "okay";
clkc: clock-controller {
compatible = "amlogic,p1-clkc";
#clock-cells = <1>;
reg = <0x0 0x0 0x0 0xb50>,
<0x0 0x8000 0x0 0x34c>,
<0x0 0xe040 0x0 0xbc>;
reg-names = "basic", "pll", "cpu_clk";
clocks = <&xtal>;
clock-names = "xtal";
status = "okay";
};
meson_clk_msr@48000 {
compatible = "amlogic,meson-p1-clk-measure";
reg = <0x0 0x48000 0x0 0x1c>;
status = "okay";
};
watchdog@2100 {
compatible = "amlogic,meson-sc2-wdt";
status = "okay";
/* 0:userspace, 1:kernel */
amlogic,feed_watchdog_mode = <1>;
reg = <0x0 0x2100 0x0 0x10>;
clocks = <&xtal>;
};
periphs_pinctrl: pinctrl@4008 {
compatible = "amlogic,meson-p1-periphs-pinctrl";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio: bank@4008 {
reg = <0x0 0x4008 0x0 0x008c>,
<0x0 0x4200 0x0 0x035c>;
reg-names = "mux", "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&periphs_pinctrl 0 0 218>;
};
};
storage_pinctrl: pinctrl@86000 {
compatible = "amlogic,meson-p1-storage-pinctrl";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio_sto: bank@86000 {
reg = <0x0 0x86000 0x0 0x8>,
<0x0 0x86380 0x0 0x020>;
reg-names = "mux", "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&storage_pinctrl 0 0 13>;
};
};
gpio_intc: interrupt-controller@40c0 {
compatible = "amlogic,meson-p1-gpio-intc",
"amlogic,meson-gpio-intc";
reg = <0x0 0x40c0 0x0 0x50>;
interrupt-controller;
#interrupt-cells = <2>;
amlogic,channel-interrupts =
<288 289 290 291 292 293 294 295 296 297 298 299
300 301 302 303 304 305 306 307 308 309 310 311
312 313 314 315 316 317 318 319>;
};
spicc0: spi@50000 {
compatible = "amlogic,meson-g12-spicc";
reg = <0x0 0x50000 0x0 0x44>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SYS_CLK_SPICC0>,
<&clkc CLKID_SPICC0>;
clock-names = "core", "async";
#address-cells = <1>;
#size-cells = <0>;
//power-domains = <&pwrdm PDID_T7_SPICC0>;
status = "disabled";
};
spicc1: spi@52000 {
compatible = "amlogic,meson-g12-spicc";
reg = <0x0 0x52000 0x0 0x44>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SYS_CLK_SPICC1>,
<&clkc CLKID_SPICC1>;
clock-names = "core", "async";
#address-cells = <1>;
#size-cells = <0>;
//power-domains = <&pwrdm PDID_T7_SPICC1>;
status = "disabled";
};
sspicc1: sspi@52000 {
compatible = "amlogic,slave-spicc";
reg = <0x0 0x52000 0x0 0x44>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "comp";
clocks = <&clkc CLKID_SYS_CLK_SPICC1>,
<&clkc CLKID_SPICC1>;
#address-cells = <1>;
#size-cells = <0>;
//power-domains = <&pwrdm PDID_T7_SPICC1>;
status = "disabled";
};
spicc2: spi@54000 {
compatible = "amlogic,meson-g12-spicc";
reg = <0x0 0x54000 0x0 0x44>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SYS_CLK_SPICC2>,
<&clkc CLKID_SPICC2>;
clock-names = "core", "async";
#address-cells = <1>;
#size-cells = <0>;
//power-domains = <&pwrdm PDID_T7_SPICC2>;
status = "disabled";
};
spicc3: spi@4a000 {
compatible = "amlogic,meson-g12-spicc";
reg = <0x0 0x4a000 0x0 0x44>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SYS_CLK_SPICC3>,
<&clkc CLKID_SPICC3>;
clock-names = "core", "async";
#address-cells = <1>;
#size-cells = <0>;
//power-domains = <&pwrdm PDID_T7_SPICC3>;
status = "disabled";
};
spicc4: spi@4c000 {
compatible = "amlogic,meson-g12-spicc";
reg = <0x0 0x4c000 0x0 0x44>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SYS_CLK_SPICC4>,
<&clkc CLKID_SPICC4>;
clock-names = "core", "async";
#address-cells = <1>;
#size-cells = <0>;
//power-domains = <&pwrdm PDID_T7_SPICC4>;
status = "disabled";
};
spicc5: spi@4e000 {
compatible = "amlogic,meson-g12-spicc";
reg = <0x0 0x4e000 0x0 0x44>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SYS_CLK_SPICC5>,
<&clkc CLKID_SPICC5>;
clock-names = "core", "async";
#address-cells = <1>;
#size-cells = <0>;
//power-domains = <&pwrdm PDID_T7_SPICC5>;
status = "disabled";
};
spifc: spi@56000 {
compatible = "amlogic,meson-spifc";
status = "disabled";
reg = <0x0 0x56000 0x0 0x80>;
clock-names = "default";
clocks = <&clkc CLKID_SYS_CLK_SPIFC>;
pinctrl-names = "default";
pinctrl-0 = <&spifc_all_pins>;
#address-cells = <1>;
#size-cells = <0>;
spi-nor@0 {
compatible = "jedec,spi-nor";
status = "disabled";
reg = <0>;
spi-max-frequency = <16000000>;
};
};
pwm_ab: pwm@58000 {
compatible = "amlogic,meson-v2-pwm";
reg = <0x0 0x58000 0x0 0x24>;
#pwm-cells = <3>;
clocks = <&clkc CLKID_PWM_A>,
<&clkc CLKID_PWM_B>;
clock-names = "clkin0", "clkin1";
status = "disabled";
};
pwm_cd: pwm@5a000 {
compatible = "amlogic,meson-v2-pwm";
reg = <0x0 0x5a000 0x0 0x24>;
#pwm-cells = <3>;
clocks = <&clkc CLKID_PWM_C>,
<&clkc CLKID_PWM_D>;
clock-names = "clkin0", "clkin1";
status = "disabled";
};
pwm_ef: pwm@5c000 {
compatible = "amlogic,meson-v2-pwm";
reg = <0x0 0x5c000 0x0 0x24>;
#pwm-cells = <3>;
clocks = <&clkc CLKID_PWM_E>,
<&clkc CLKID_PWM_F>;
clock-names = "clkin0", "clkin1";
status = "disabled";
};
pwm_gh: pwm@5e000 {
compatible = "amlogic,meson-v2-pwm";
reg = <0x0 0x5e000 0x0 0x24>;
#pwm-cells = <3>;
clocks = <&clkc CLKID_PWM_G>,
<&clkc CLKID_PWM_H>;
clock-names = "clkin0", "clkin1";
status = "disabled";
};
pwm_ij: pwm@60000 {
compatible = "amlogic,meson-v2-pwm";
reg = <0x0 0x60000 0x0 0x24>;
#pwm-cells = <3>;
clocks = <&clkc CLKID_PWM_I>,
<&clkc CLKID_PWM_J>;
clock-names = "clkin0", "clkin1";
status = "disabled";
};
i2c0: i2c@66000 {
compatible = "amlogic,meson-i2c";
reg = <0x0 0x66000 0x0 0x48>;
interrupts = <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_SYS_CLK_I2C_M_A>;
status = "disabled";
};
i2c1: i2c@68000 {
compatible = "amlogic,meson-i2c";
reg = <0x0 0x68000 0x0 0x48>;
interrupts = <GIC_SPI 161 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_SYS_CLK_I2C_M_B>;
status = "disabled";
};
i2c2: i2c@6a000 {
compatible = "amlogic,meson-i2c";
reg = <0x0 0x6a000 0x0 0x48>;
interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_SYS_CLK_I2C_M_C>;
status = "disabled";
};
i2c3: i2c@6c000 {
compatible = "amlogic,meson-i2c";
reg = <0x0 0x6c000 0x0 0x48>;
interrupts = <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_SYS_CLK_I2C_M_D>;
status = "disabled";
};
i2c4: i2c@6e000 {
compatible = "amlogic,meson-i2c";
reg = <0x0 0x6e000 0x0 0x48>;
interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_SYS_CLK_I2C_M_E>;
status = "disabled";
};
i2c5: i2c@70000 {
compatible = "amlogic,meson-i2c";
reg = <0x0 0x070000 0x0 0x48>;
interrupts = <GIC_SPI 165 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_SYS_CLK_I2C_M_F>;
status = "disabled";
};
i2c6: i2c@a2000 {
compatible = "amlogic,meson-i2c";
reg = <0x0 0xa2000 0x0 0x48>;
interrupts = <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_SYS_CLK_I2C_M_G>;
status = "disabled";
};
i2c7: i2c@a4000 {
compatible = "amlogic,meson-i2c";
reg = <0x0 0xa4000 0x0 0x48>;
interrupts = <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_SYS_CLK_I2C_M_H>;
status = "disabled";
};
i2c8: i2c@a6000 {
compatible = "amlogic,meson-i2c";
reg = <0x0 0xa6000 0x0 0x48>;
interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_SYS_CLK_I2C_M_I>;
status = "disabled";
};
i2c9: i2c@a8000 {
compatible = "amlogic,meson-i2c";
reg = <0x0 0xa8000 0x0 0x48>;
interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_SYS_CLK_I2C_M_J>;
status = "disabled";
};
i2c10: i2c@aa000 {
compatible = "amlogic,meson-i2c";
reg = <0x0 0xaa000 0x0 0x48>;
interrupts = <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc CLKID_SYS_CLK_I2C_M_K>;
status = "disabled";
};
i2c0_slave: i2c0_slave@64000 {
compatible = "amlogic, meson-i2c-slave";
status = "disabled";
reg = <0x0 0x64000 0x0 0xf>;
interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
};
i2c1_slave: i2c1_slave@ac000 {
compatible = "amlogic, meson-i2c-slave";
status = "disabled";
reg = <0x0 0xac000 0x0 0xf>;
interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>;
};
i2c2_slave: i2c2_slave@ae000 {
compatible = "amlogic, meson-i2c-slave";
status = "disabled";
reg = <0x0 0xae000 0x0 0xf>;
interrupts = <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>;
};
i2c3_slave: i2c3_slave@b0000 {
compatible = "amlogic, meson-i2c-slave";
status = "disabled";
reg = <0x0 0xb0000 0x0 0xf>;
interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>;
};
i2c4_slave: i2c4_slave@b2000 {
compatible = "amlogic, meson-i2c-slave";
status = "disabled";
reg = <0x0 0xb2000 0x0 0xf>;
interrupts = <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>;
};
i2c5_slave: i2c5_slave@b4000 {
compatible = "amlogic, meson-i2c-slave";
status = "disabled";
reg = <0x0 0xb4000 0x0 0xf>;
interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
};
i2c6_slave: i2c6_slave@b6000 {
compatible = "amlogic, meson-i2c-slave";
status = "disabled";
reg = <0x0 0xb6000 0x0 0xf>;
interrupts = <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>;
};
i2c7_slave: i2c7_slave@b8000 {
compatible = "amlogic, meson-i2c-slave";
status = "disabled";
reg = <0x0 0xb8000 0x0 0xf>;
interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
};
i2c8_slave: i2c8_slave@ba000 {
compatible = "amlogic, meson-i2c-slave";
status = "disabled";
reg = <0x0 0xba000 0x0 0xf>;
interrupts = <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>;
};
i2c9_slave: i2c9_slave@bc000 {
compatible = "amlogic, meson-i2c-slave";
status = "disabled";
reg = <0x0 0xbc000 0x0 0xf>;
interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
};
i2c10_slave: i2c10_slave@be000 {
compatible = "amlogic, meson-i2c-slave";
status = "disabled";
reg = <0x0 0xbe000 0x0 0xf>;
interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
};
uart_B: serial@7a000 {
compatible = "amlogic,meson-uart";
reg = <0x0 0x7a000 0x0 0x18>;
interrupts = <0 169 1>;
status = "disabled";
clocks = <&xtal
&clkc CLKID_SYS_CLK_UART_B>;
clock-names = "clk_uart",
"clk_gate";
xtal_tick_en = <2>;
fifosize = < 64 >;
pinctrl-names = "default";
pinctrl-0 = <&b_uart_pins1>;
};
reset: reset-controller@2000 {
compatible = "amlogic,meson-p1-reset";
reg = <0x0 0x2000 0x0 0xa0>;
#reset-cells = <1>;
};
cpu_version {
compatible = "amlogic,meson-gx-ao-secure", "syscon";
status = "disable";
reg=<0x0 0x10220 0x0 0x140>;
};
gbl_timer_core: global-timer@8e000 {
compatible = "amlogic,meson-glb-timer-core";
reg = <0x0 0x8e000 0x0 0x28>;
reg-names = "topctrl";
clocks = <&clkc CLKID_SYS_CLK_GLB>;
clock-names = "glb_clk";
hwlocks = <&aml_hwlock HWSPINLOCK_ID_GLB_TIMER>;
};
gbl_timer_isp: global-timer@8e040 {
compatible = "amlogic,meson-glb-timer-isp";
reg = <0x0 0x8e040 0x0 0x140>;
reg-names = "isp";
};
gbl_timer_gpio_input: global-timer@8e180 {
compatible = "amlogic,meson-glb-timer-gpio-input";
reg-names = "input-src-sel";
reg = <0x0 0x8e180 0x0 0x56c>;
};
};
crg21_otg: crg21otg@fe03a000 {
compatible = "amlogic, amlogic-crg-otg";
status = "disabled";
usb2-phy-reg = <0xfe03a08c>;
usb2-phy-reg-size = <0x80>;
m31-phy-reg = <0xfe076000>;
m31-phy-reg-size = <0x80>;
usb3-phy-reg = <0xfe03a080>;
usb3-phy-reg-size = <0x20>;
interrupts = <0 128 IRQ_TYPE_EDGE_RISING>;
udc-name = "fde00000.crgudc2";
};
crg30: crg@fdd00000 {
compatible = "amlogic, crg";
status = "disabled";
reg = <0x0 0xfdd00000 0x0 0x100000>;
interrupts = <0 131 4>;
usb-phy = <&usb2_m31_0_phy>, <&usb3_m31_0_phy>;
cpu-type = "gxl";
clock-src = "usb3.0";
clocks = <&clkc CLKID_SYS_CLK_USB>;
clock-names = "crg_general";
};
crg31_drd: crg2drd@fde00000 {
status = "disabled";
reg = <0x0 0xfde00000 0x0 0x100000>;
interrupts = <0 130 4>;
usb-phy = <&usb2_m31_1_phy>, <&usb3_m31_1_phy>;
cpu-type = "gxl";
clock-src = "usb3.0";
clocks = <&clkc CLKID_SYS_CLK_USB>;
clock-names = "crg_general";
};
crg32: crg@fdf00000 {
compatible = "amlogic, crg";
status = "disabled";
reg = <0x0 0xfdf00000 0x0 0x100000>;
interrupts = <0 129 4>;
usb-phy = <&usb2_m31_2_phy>, <&usb3_m31_2_phy>;
cpu-type = "gxl";
clock-src = "usb3.0";
clocks = <&clkc CLKID_SYS_CLK_USB>;
clock-names = "crg_general";
};
usb2_m31_0_phy: usb2m310phy {
compatible = "amlogic, amlogic-usb2-m31-phy";
status = "disable";
#phy-cells = <0>;
};
usb3_m31_0_phy: usb3m310phy {
compatible = "amlogic, amlogic-usb3-m31-phy";
status = "disable";
#phy-cells = <0>;
reg = <0x0 0xfe002000 0x0 0x100>;
reset-level = <0x40>;
phy-reg = <0xfe02a000>;
phy-reg-size = <0x2000>;
m31phy-reset-level-bit = <10>;
m31ctl-reset-level-bit = <6>;
uncomposite = <1>;
};
usb2_m31_1_phy: usb2m311phy {
compatible = "amlogic, amlogic-usb2-m31-phy";
status = "disable";
#phy-cells = <0>;
};
usb3_m31_1_phy: usb3m311phy {
compatible = "amlogic, amlogic-usb3-m31-phy";
status = "disable";
#phy-cells = <0>;
reg = <0x0 0xfe002000 0x0 0x100>;
reset-level = <0x40>;
phy-reg = <0xfe076000>;
phy-reg-size = <0x2000>;
m31phy-reset-level-bit = <9>;
m31ctl-reset-level-bit = <5>;
uncomposite = <1>;
};
usb2_m31_2_phy: usb2m312phy {
compatible = "amlogic, amlogic-usb2-m31-phy";
status = "disable";
#phy-cells = <0>;
};
usb3_m31_2_phy: usb3m312phy {
compatible = "amlogic, amlogic-usb3-m31-phy";
status = "disable";
#phy-cells = <0>;
reg = <0x0 0xfe002000 0x0 0x100>;
reset-level = <0x40>;
phy-reg = <0xfe074000>;
phy-reg-size = <0x2000>;
m31phy-reset-level-bit = <8>;
m31ctl-reset-level-bit = <3>;
uncomposite = <1>;
};
crg_udc_2: crgudc2@0xfde00000 {
compatible = "amlogic, crg_udc";
status = "disable";
device_name = "crg_udc_2";
reg = <0x0 0xfde00000 0x0 0x100000>;
interrupts = <0 130 4>;
clock-src = "usb0"; /** clock src */
port-speed = <3>; /** 0: default, high, 1: full */
phy-reg = <0xfe076000>;
phy-reg-size = <0x1000>;
clocks = <&clkc CLKID_SYS_CLK_USB>;
clock-names = "usb_general";
phy-id = <2>;
controller-type = <4>;
};
dummy_codec:dummy{
#sound-dai-cells = <0>;
compatible = "amlogic, aml_dummy_codec";
status = "okay";
};
acodec:codec {
#sound-dai-cells = <0>;
compatible = "amlogic, tm2_revb_acodec";
reg = <0x0 0xfe01a000 0x0 0x1c>;
tdmout_index = <0>;
tdmin_index = <0>;
dat0_ch_sel = <1>;
status = "disabled";
};
audio_data: audio_data {
compatible = "amlogic, audio_data";
mem_in_base_cmd = <0x82000020>;
query_licence_cmd = <0x82000050>;
status = "disabled";
};
audiobus: audiobus@0xFE330000 {
compatible = "amlogic, audio-controller", "simple-bus";
reg = <0x0 0xFE330000 0x0 0x3000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xFE330000 0x0 0x3000>;
// power-domains = <&pwrdm PDID_T7_AUDIO>;
status = "okay";
clkaudio: audio_clocks {
compatible = "amlogic, p1-audio-clocks";
#clock-cells = <1>;
reg = <0x0 0x0 0x0 0xb0>;
status = "okay";
};
ddr_manager {
compatible =
"amlogic, p1-audio-ddr-manager";
interrupts = <
GIC_SPI 32 IRQ_TYPE_EDGE_RISING
GIC_SPI 33 IRQ_TYPE_EDGE_RISING
GIC_SPI 34 IRQ_TYPE_EDGE_RISING
GIC_SPI 45 IRQ_TYPE_EDGE_RISING
GIC_SPI 36 IRQ_TYPE_EDGE_RISING
GIC_SPI 37 IRQ_TYPE_EDGE_RISING
GIC_SPI 38 IRQ_TYPE_EDGE_RISING
GIC_SPI 46 IRQ_TYPE_EDGE_RISING
>;
interrupt-names =
"toddr_a", "toddr_b", "toddr_c",
"toddr_d",
"frddr_a", "frddr_b", "frddr_c",
"frddr_d";
status = "okay";
};
pinctrl_audio: pinctrl {
compatible = "amlogic, audio-pinctrl";
status = "okay";
};
};/* end of audiobus*/
/* eARC */
audio_earc: bus@fe333000 {
compatible = "simple-bus";
reg = <0x0 0xfe333000 0x0 0x1000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xfe333000 0x0 0x1000>;
status = "disabled";
earc: earc@0 {
compatible = "amlogic, t7-snd-earc";
#sound-dai-cells = <0>;
status = "disabled";
reg = <0x0 0x0 0x0 0x400>,
<0x0 0x400 0x0 0x200>,
<0x0 0x600 0x0 0x200>,
<0x0 0x800 0x0 0x400>,
<0x0 0xc00 0x0 0x200>,
<0x0 0xe00 0x0 0x200>;
reg-names = "tx_cmdc",
"tx_dmac",
"tx_top",
"rx_cmdc",
"rx_dmac",
"rx_top";
clocks = < &clkaudio CLKID_EARCRX_CMDC
&clkaudio CLKID_EARCRX_DMAC
&clkc CLKID_FCLK_DIV4
&clkc CLKID_FCLK_DIV4
&clkaudio CLKID_EARCTX_CMDC
&clkaudio CLKID_EARCTX_DMAC
&clkc CLKID_FCLK_DIV4
&clkc CLKID_MPLL1
>;
clock-names =
"rx_cmdc",
"rx_dmac",
"rx_cmdc_srcpll",
"rx_dmac_srcpll",
"tx_cmdc",
"tx_dmac",
"tx_cmdc_srcpll",
"tx_dmac_srcpll";
interrupts = <
GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "earc_rx", "earc_tx";
};
};
/* Sound iomap */
aml_snd_iomap {
compatible = "amlogic, snd-iomap";
status = "okay";
#address-cells=<2>;
#size-cells=<2>;
ranges;
pdm_bus {
reg = <0x0 0xFE331000 0x0 0x400>;
};
audiobus_base {
reg = <0x0 0xFE330000 0x0 0x1000>;
};
audiolocker_base {
reg = <0x0 0xFE331400 0x0 0x400>;
};
eqdrc_base {
reg = <0x0 0xFE332000 0x0 0x1000>;
};
vad_base {
reg = <0x0 0xFE331800 0x0 0x400>;
};
resampleA_base {
reg = <0x0 0xFE331c00 0x0 0x104>;
};
resampleB_base {
reg = <0x0 0xFE334000 0x0 0x104>;
};
pdm_bus_b {
reg = <0x0 0xFE334800 0x0 0x400>;
};
};
pcie: pcie@0xe0000000 {
compatible = "amlogic, amlogic-pcie-v3";
reg = <0x0 0xe0000000 0x0 0x1000
0x0 0xfe02c000 0x0 0x2000
0x0 0xe0000000 0x0 0x10000000
0x0 0xefe00000 0x0 0x200000
0x0 0xfe072000 0x0 0x2000
0x0 0xfe002040 0x0 0x10>;
reg-names = "apb-base", "pcictrl-base", "axi-base",
"ecam-base", "phy-base", "reset-base";
interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
#interrupt-cells = <1>;
msi-controller;
msi-parent = <&pcie>;
interrupt-parent = <&gic>;
bus-range = <0x0 0xff>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &gic GIC_SPI 188
IRQ_TYPE_EDGE_RISING>,
<0 0 0 2 &gic GIC_SPI 91
IRQ_TYPE_EDGE_RISING>,
<0 0 0 3 &gic GIC_SPI 92
IRQ_TYPE_EDGE_RISING>,
<0 0 0 4 &gic GIC_SPI 93
IRQ_TYPE_EDGE_RISING>;
device_type = "pci";
ranges =
/*
* <0x81000000 0 0xff000000
* 0 0xe1000000 0x0 0x100000
*/
/*downstream I/O */
<0x82000000 0 0xe4000000 0x0 0xe4000000
0 0x8000000>;
/* non-prefetchable memory */
num-lanes = <1>;
pcie-num = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pcieck_pins>;
clocks = <&clkc CLKID_PCIE_PLL
&clkc CLKID_SYS_CLK_PCIE
&clkc CLKID_SYS_CLK_PCIEPHY
&clkc CLKID_PCIE_HCSL
&clkc CLKID_PCIE_400M
&clkc CLKID_PCIE_TL_CLK
&clkc CLKID_PCIE_CLK>;
clock-names = "pcie_refpll",
"pcie",
"pcie_phy",
"pcie_hcsl",
"pcie_400m_clk",
"pcie_tl_clk",
"cts_pcie_clk";
/*reset-gpio-type
*0:Shared pad(no reset)
*1:OD pad2:Normal pad
*/
gpio-type = <2>;
pcie-m31phy-rst-bit = <21>;
pcie-gen3-l0-rst-bit = <18>;
pcie-apb-rst-bit = <14>;
pcie-phy-rst-bit = <13>;
pcie-a-rst-bit = <12>;
pcie-rst-bit = <12>;
pcie-rst-mask = <0xff>;
power-domains = <&pwrdm PDID_P1_PCIE>;
status = "disabled";
iommu-map = <0x100 &smmu P1_SID_PCIE 0x10>;
dma-ranges = <0x0 0x0 0x0 0x0 0x0 0x0 0x80000000>;
};
pcie_ep: pcie-ep@0xe0000000 {
compatible = "amlogic, amlogic-pcie-ep";
reg = <0x0 0xe0000000 0x0 0x1000
0x0 0xfe02c000 0x0 0x2000
0x0 0xe0000000 0x0 0x10000000
0x0 0xefe00000 0x0 0x200000
0x0 0xfe072000 0x0 0x2000
0x0 0xfe002040 0x0 0x10
0x0 0xe4000000 0x0 0x8000000>;
reg-names = "apb-base", "pcictrl-base", "axi-base",
"ecam-base", "phy-base", "reset-base",
"mem0";
interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&pcieck_pins>;
clocks = <&clkc CLKID_PCIE_PLL
&clkc CLKID_SYS_CLK_PCIE
&clkc CLKID_SYS_CLK_PCIEPHY
&clkc CLKID_PCIE_HCSL
&clkc CLKID_PCIE_400M
&clkc CLKID_PCIE_TL_CLK
&clkc CLKID_PCIE_CLK>;
clock-names = "pcie_refpll",
"pcie",
"pcie_phy",
"pcie_hcsl",
"pcie_400m_clk",
"pcie_tl_clk",
"cts_pcie_clk";
/*reset-gpio-type 0:Shared pad(no reset)1:OD pad2:Normal pad*/
gpio-type = <2>;
pcie-m31phy-rst-bit = <21>;
pcie-gen3-l0-rst-bit = <18>;
pcie-apb-rst-bit = <14>;
pcie-phy-rst-bit = <13>;
pcie-a-rst-bit = <12>;
pcie-rst-bit = <12>;
pcie-rst-mask = <0xff>;
power-domains = <&pwrdm PDID_P1_PCIE>;
status = "disabled";
};
sd_emmc_c: mmc@fe08c000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0xfe08c000 0x0 0x800>,
<0x0 0xfe000168 0x0 0x4>,
<0x0 0xfe086000 0x0 0x4>;
interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
clocks = <&clkc CLKID_SYS_CLK_SD_EMMC_C>,
<&clkc CLKID_SD_EMMC_C_CLK_SEL>,
<&clkc CLKID_SD_EMMC_C_CLK>,
<&xtal>,
<&clkc CLKID_GP0_PLL>,
<&clkc CLKID_GP0_PLL>;
clock-names = "core", "mux0", "mux1",
"clkin0", "clkin1", "clkin2";
card_type = <1>;
src_clk_rate = <1152000000>;
mmc_debug_flag;
ignore_desc_busy;
tx_delay = <20>;
nwr_cnt = <12>;
// resets = <&reset RESET_SD_EMMC_C>;
};
sd_emmc_a: sdio@fe088000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0xfe088000 0x0 0x800>,
<0x0 0xfe00016c 0x0 0x4>,
<0x0 0xfe004030 0x0 0x4>;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&clkc CLKID_SYS_CLK_SD_EMMC_A>,
<&clkc CLKID_SD_EMMC_A_CLK_SEL>,
<&clkc CLKID_SD_EMMC_A_CLK>,
<&xtal>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "mux0", "mux1",
"clkin0", "clkin1";
card_type = <3>;
cap-sdio-irq;
keep-power-in-suspend;
use_intf3_tuning;
mmc_debug_flag;
//resets = <&reset RESET_SD_EMMC_A>;
};
ethmac: ethernet@fdc00000 {
compatible = "amlogic,meson-axg-dwmac",
"snps,dwmac-4.00";
reg = <0x0 0xfdc00000 0x0 0x10000>,
<0x0 0xfe024000 0x0 0x8>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
power-domains = <&pwrdm PDID_P1_ETH>;
clocks = <&clkc CLKID_SYS_CLK_ETH>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
rx-fifo-depth = <4096>;
tx-fifo-depth = <2048>;
/*1:inphy; 2:exphy;*/
internal_phy = <2>;
cali_val = <0x6A0000>;
status = "disabled";
ext_mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
external_phy: ethernet-phy@0 {
reg = <0>;
max-speed = <1000>;
reset-assert-us = <10000>;
reset-deassert-us = <15000>;
reset-gpios = <&gpio GPIOZ_7 (GPIO_ACTIVE_LOW |
GPIO_OPEN_DRAIN)>;
};
};
};
uart_A: serial@fe078000 {
compatible = "amlogic,meson-uart";
reg = <0x0 0xfe078000 0x0 0x18>;
interrupts = <0 168 1>;
status = "disabled";
clocks = <&xtal
&clkc CLKID_SYS_CLK_UART_A>;
clock-names = "clk_uart",
"clk_gate";
xtal_tick_en = <2>;
fifosize = < 64 >;
pinctrl-names = "default";
support-sysrq = <1>; /* 0 not support*/
//pinctrl-0 = <&a_uart_pins1>;
};
// uart_A: serial@fe078000 {
// compatible = "amlogic, meson-uart";
// reg = <0x0 0xfe078000 0x0 0x18>;
// interrupts = <0 168 1>;
// status = "disabled";
// clocks = <&xtal
// &clkc CLKID_UART_A>;
// clock-names = "clk_uart",
// "clk_gate";
// xtal_tick_en = <3>;
// fifosize = < 128 >;
// pinctrl-names = "default";
// pinctrl-0 = <&a_uart_pins1>;
// };
//
uart_C: serial@fe07c000 {
compatible = "amlogic,meson-uart";
reg = <0x0 0xfe07c000 0x0 0x18>;
interrupts = <0 170 1>;
status = "disabled";
clocks = <&xtal
&clkc CLKID_SYS_CLK_UART_C>;
clock-names = "clk_uart",
"clk_gate";
fifosize = < 64 >;
pinctrl-names = "default";
pinctrl-0 = <&c_uart_pins>;
};
uart_D: serial@fe07e000 {
compatible = "amlogic,meson-uart";
status = "disabled";
reg = <0x0 0xfe07e000 0x0 0x18>;
interrupts = <0 171 1>;
clocks = <&xtal
&clkc CLKID_SYS_CLK_UART_D>;
clock-names = "clk_uart",
"clk_gate";
fifosize = < 64 >;
pinctrl-names = "default";
pinctrl-0 = <&d_uart_pins>;
};
uart_E: serial@fe080000 {
compatible = "amlogic,meson-uart";
status = "disabled";
reg = <0x0 0xfe080000 0x0 0x18>;
interrupts = <0 172 1>;
clocks = <&xtal
&clkc CLKID_SYS_CLK_UART_E>;
clock-names = "clk_uart",
"clk_gate";
fifosize = < 64 >;
pinctrl-names = "default";
pinctrl-0 = <&e_uart_pins1>;
};
uart_F: serial@fe082000 {
compatible = "amlogic,meson-uart";
status = "disabled";
reg = <0x0 0xfe082000 0x0 0x18>;
interrupts = <0 180 1>;
clocks = <&xtal
&clkc CLKID_SYS_CLK_UART_F>;
clock-names = "clk_uart",
"clk_gate";
fifosize = < 64 >;
pinctrl-names = "default";
pinctrl-0 = <&f_uart_pins1>;
};
};
mesonstream {
compatible = "amlogic, codec, streambuf";
dev_name = "mesonstream";
status = "disabled";
//clocks = <&clkc CLKID_DOS
// &clkc CLKID_VDEC_MUX
// &clkc CLKID_HCODEC_MUX
// &clkc CLKID_HEVCF_MUX
// &clkc CLKID_HEVCB_MUX>;
//clock-names = "vdec",
// "clk_vdec_mux",
// "clk_hcodec_mux",
// "clk_hevcf_mux",
// "clk_hevcb_mux";
//assigned-clock-parents = <&clkc CLKID_VDEC_P0>,
// <&clkc CLKID_HEVCF_P0>,
// <&clkc CLKID_HEVCB_P0>;
//assigned-clocks = <&clkc CLKID_VDEC_MUX>,
// <&clkc CLKID_HEVCF_MUX>,
// <&clkc CLKID_HEVCB_MUX>;
};
csiphy0: csiphy0@ff918000 {
compatible = "amlogic, csiphy";
reg = <0x0 0xff918000 0x0 0x3000>,
<0x0 0xff9a0000 0x0 0x400>;
reg-names = "csi_phy","csi_aphy";
power-domains = <&pwrdm PDID_P1_MIPI_ISP_TOP>;
clocks = <&clkc CLKID_CSIPHY0>;
clock-names = "cts_mipi_csi_phy_clk";
};
adapter0: adapter0@ff918000 {
compatible = "amlogic, adapter";
reg = <0x0 0xff918000 0x0 0x6000>;
reg-names = "adapter";
};
isp0: isp0@ff900000 {
compatible = "amlogic, isp";
reg = <0x0 0xff900000 0x0 0x10000>;
/* interrupt-parent = <&intc>; */
power-domains = <&pwrdm PDID_P1_ISP_A>;
clocks = <&clkc CLKID_ISP0>;
clock-names = "cts_mipi_isp_clk";
interrupts = <0 97 1>;
};
camera0 {
status = "okay";
compatible = "amlogic, camera";
index = <0>;
csiphy = <&csiphy0>;
adapter = <&adapter0>;
isp = <&isp0>;
};
csiphy1: csiphy1@ff938000 {
compatible = "amlogic, csiphy";
reg = <0x0 0xff938000 0x0 0x3000>,
<0x0 0xff9a0000 0x0 0x400>;
reg-names = "csi_phy","csi_aphy";
power-domains = <&pwrdm PDID_P1_MIPI_ISP_TOP>;
clocks = <&clkc CLKID_CSIPHY1>;
clock-names = "cts_mipi_csi_phy_clk";
};
adapter1: adapter1@ff938000 {
compatible = "amlogic, adapter";
reg = <0x0 0xff938000 0x0 0x6000>;
reg-names = "adapter";
};
isp1: isp1@ff920000 {
compatible = "amlogic, isp";
reg = <0x0 0xff920000 0x0 0x10000>;
/* interrupt-parent = <&intc>; */
power-domains = <&pwrdm PDID_P1_ISP_B>;
clocks = <&clkc CLKID_ISP1>;
clock-names = "cts_mipi_isp_clk";
interrupts = <0 105 1>;
};
camera1 {
status = "okay";
compatible = "amlogic, camera";
index = <1>;
csiphy = <&csiphy1>;
adapter = <&adapter1>;
isp = <&isp1>;
};
csiphy2: csiphy2@ff958000 {
compatible = "amlogic, csiphy";
reg = <0x0 0xff958000 0x0 0x3000>,
<0x0 0xff9a0000 0x0 0x400>;
reg-names = "csi_phy","csi_aphy";
power-domains = <&pwrdm PDID_P1_MIPI_ISP_TOP>;
clocks = <&clkc CLKID_CSIPHY2>;
clock-names = "cts_mipi_csi_phy_clk";
};
adapter2: adapter2@ff958000 {
compatible = "amlogic, adapter";
reg = <0x0 0xff958000 0x0 0x6000>;
reg-names = "adapter";
};
isp2: isp2@ff940000 {
compatible = "amlogic, isp";
reg = <0x0 0xff940000 0x0 0x10000>;
/* interrupt-parent = <&intc>; */
power-domains = <&pwrdm PDID_P1_ISP_C>;
clocks = <&clkc CLKID_ISP2>;
clock-names = "cts_mipi_isp_clk";
interrupts = <0 113 1>;
};
camera2 {
status = "okay";
compatible = "amlogic, camera";
index = <2>;
csiphy = <&csiphy2>;
adapter = <&adapter2>;
isp = <&isp2>;
};
csiphy3: csiphy3@ff978000 {
compatible = "amlogic, csiphy";
reg = <0x0 0xff978000 0x0 0x3000>,
<0x0 0xff9a0000 0x0 0x400>;
reg-names = "csi_phy","csi_aphy";
power-domains = <&pwrdm PDID_P1_MIPI_ISP_TOP>;
clocks = <&clkc CLKID_CSIPHY3>;
clock-names = "cts_mipi_csi_phy_clk";
};
adapter3: adapter3@ff978000 {
compatible = "amlogic, adapter";
reg = <0x0 0xff978000 0x0 0x6000>;
reg-names = "adapter";
};
isp3: isp3@ff960000 {
compatible = "amlogic, isp";
reg = <0x0 0xff960000 0x0 0x10000>;
/* interrupt-parent = <&intc>; */
power-domains = <&pwrdm PDID_P1_ISP_D>;
clocks = <&clkc CLKID_ISP3>;
clock-names = "cts_mipi_isp_clk";
interrupts = <0 121 1>;
};
camera3 {
status = "okay";
compatible = "amlogic, camera";
index = <3>;
csiphy = <&csiphy3>;
adapter = <&adapter3>;
isp = <&isp3>;
};
csiphy4: csiphy4@ff998000 {
compatible = "amlogic, csiphy";
reg = <0x0 0xff998000 0x0 0x3000>,
<0x0 0xff9a0000 0x0 0x400>;
reg-names = "csi_phy","csi_aphy";
power-domains = <&pwrdm PDID_P1_MIPI_ISP_TOP>;
clocks = <&clkc CLKID_CSIPHY4>;
clock-names = "cts_mipi_csi_phy_clk";
};
adapter4: adapter4@ff998000 {
compatible = "amlogic, adapter";
reg = <0x0 0xff998000 0x0 0x6000>,
<0x0 0xff980000 0x0 0x1000>;
reg-names = "adapter","wrmif";
clocks = <&clkc CLKID_ISP4>;
clock-names = "cts_mipi_wrmif_clk";
interrupts = <0 81 1>;
};
camera4 {
status = "okay";
compatible = "amlogic, camera";
index = <4>;
csiphy = <&csiphy4>;
adapter = <&adapter4>;
};
vdec {
compatible = "amlogic, vdec-pm-pd";
dev_name = "vdec.0";
status = "disabled";
interrupts = <0 3 1
0 23 1
0 32 1
0 91 1
0 92 1
0 93 1
0 72 1>;
interrupt-names = "vsync",
"demux",
"parser",
"mailbox_0",
"mailbox_1",
"mailbox_2",
"parser_b";
//power-domains = <&pwrdm PDID_T7_DOS_VDEC>,
// <&pwrdm PDID_T7_DOS_HCODEC>,
// <&pwrdm PDID_T7_DOS_HEVC>,
// <&pwrdm PDID_T7_DOS_WAVE>;
//power-domain-names = "pwrc-vdec",
// "pwrc-hcodec",
// "pwrc-hevc",
// "pwrc-wave";
};
cpu_ver_name {
compatible = "amlogic, cpu-major-id-t7";
status = "disabled";
};
vcodec_dec {
compatible = "amlogic, vcodec-dec";
dev_name = "aml-vcodec-dec";
status = "disabled";
};
ddr_bandwidth {
compatible = "amlogic,ddr-bandwidth-p1";
status = "okay";
reg = <0 0xfe036000 0 0x200
0 0xfe034000 0 0x200
0 0xfe032000 0 0x200
0 0xfe030000 0 0x200
0 0xfe0a0000 0 0x100>;
interrupts = <0 332 IRQ_TYPE_EDGE_RISING
0 336 IRQ_TYPE_EDGE_RISING
0 340 IRQ_TYPE_EDGE_RISING
0 54 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ddr_bandwidth";
};
dmc_monitor {
compatible = "amlogic,dmc_monitor-p1";
status = "okay";
reg = <0 0xfe036000 0 0x200
0 0xfe034000 0 0x200
0 0xfe032000 0 0x200
0 0xfe030000 0 0x200>;
reg_base = <0xfe036000>;
interrupts = <0 333 IRQ_TYPE_EDGE_RISING
0 337 IRQ_TYPE_EDGE_RISING
0 341 IRQ_TYPE_EDGE_RISING
0 55 IRQ_TYPE_EDGE_RISING>;
};
amhdmitx: amhdmitx{
compatible = "amlogic, amhdmitx-t7";
dev_name = "amhdmitx";
status = "disabled";
//power-domains = <&pwrdm PDID_T7_VI_CLK2>;
vend-data = <&vend_data>;
pinctrl-names="hdmitx_hpd", "hdmitx_ddc";
pinctrl-0=<&hdmitx_hpd>;
pinctrl-1=<&hdmitx_ddc>;
interrupts = <0 204 1>;
interrupt-names = "hdmitx_hpd";
reg = <0x0 0xff000000 0x0 0x40000>,
<0x0 0xfe380000 0x0 0x10000>,
<0x0 0xfe300000 0x0 0x10000>,
<0x0 0xfe010000 0x0 0x2000>,
<0x0 0xfe00c000 0x0 0x2000>,
<0x0 0xfe008000 0x0 0x2000>,
<0x0 0xfe002000 0x0 0x2000>,
<0x0 0xfe000000 0x0 0x2000>,
<0x0 0xfe004000 0x0 0x200>;
reg-names = "vpu",
"hdmitxcor",
"hdmitxtop",
"sysctrl",
"pwrctrl",
"anactrl",
"resetctrl",
"clkctrl",
"padctrl";
vend_data: vend_data{ /* Should modified by Customer */
vendor_name = "Amlogic"; /* Max Chars: 8 */
product_desc = "MBox Meson Ref"; /* Max Chars: 16 */
/* standards.ieee.org/develop/regauth/oui/oui.txt */
vendor_id = <0x000000>;
};
};
aocec: aocec {
compatible = "amlogic, aocec-t7";
dev_name = "aocec";
status = "disabled";
vendor_name = "Amlogic"; /* Max Chars: 8 */
/* Refer to the following URL at:
* http://standards.ieee.org/develop/regauth/oui/oui.txt
*/
vendor_id = <0x000000>;
product_desc = "T7"; /* Max Chars: 16 */
cec_osd_string = "AML_TV"; /* Max Chars: 14 */
cec_version = <5>;/*5:1.4;6:2.0*/
port_num = <4>;
output = <1>;
cec_sel = <1>;/*1:use one ip, 2:use 2 ip*/
/*ee_cec;*/ /*use cec a or b*/
arc_port_mask = <0x2>;
interrupts = <GIC_SPI 180 IRQ_TYPE_EDGE_RISING/*0:snps*/
GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;/*1:ts*/
interrupt-names = "hdmi_aocecb","hdmi_aocec";
pinctrl-names = "default","hdmitx_aocecb","cec_pin_sleep";
pinctrl-0=<&cec_a>;
pinctrl-1=<&cec_b>;
pinctrl-2=<&cec_b>;
//clocks = <&clkc CLKID_CECA_32K_CLKOUT>,
// <&clkc CLKID_CECB_32K_CLKOUT>;
clock-names = "ceca_clk","cecb_clk";
reg = <0x0 0xfe044000 0x0 0x2ff
0x0 0xfe010000 0x0 0xfff
0x0 0xfe000000 0x0 0xfff>;
reg-names = "ao","periphs","clock"/*ao_exit hdmirx hhi*/;
};
aml_dma {
compatible = "amlogic,aml_txlx_dma";
reg = <0x0 0xfe440400 0x0 0x48>;
interrupts = <0 24 1>;
status = "okay";
aml_aes {
compatible = "amlogic,aes_g12a_dma";
dev_name = "aml_aes_dma";
status = "okay";
iv_swap = /bits/ 8 <0x0>;
};
aml_sha {
compatible = "amlogic,sha_dma";
dev_name = "aml_sha_dma";
status = "okay";
};
aml_tdes {
compatible = "amlogic,tdes_dma";
dev_name = "aml_tdes_dma";
status = "okay";
};
};
rng {
compatible = "amlogic,meson-rng";
status = "okay";
#address-cells = <2>;
#size-cells = <2>;
reg = <0x0 0xfe440788 0x0 0x0c>;
quality = /bits/ 16 <1000>;
version = <2>;
};
canvas: canvas{
compatible = "amlogic, meson, canvas";
dev_name = "amlogic-canvas";
status = "disabled";
reg = <0x0 0xfe036048 0x0 0x2000>;
};
codec_io: codec_io {
compatible = "amlogic, meson-t7, codec-io";
status = "disabled";
#address-cells=<2>;
#size-cells=<2>;
ranges;
/* use cbus space for reset_ctrl*/
reg = <0x0 0xfe002000 0x0 0x2000>,
<0x0 0xfe320000 0x0 0x10000>,
<0x0 0x0 0x0 0x0>,
<0x0 0x0 0x0 0x00>,
<0x0 0xff000000 0x0 0x40000>,
<0x0 0xfe036000 0x0 0x2000>,
<0x0 0x0 0x0 0x0>;
reg-names = "cbus",
"dosbus",
"hiubus",
"aobus",
"vcbus",
"dmcbus",
"efusebus";
};
jpegenc{
compatible = "amlogic, jpegenc";
dev_name = "jpegenc";
status = "disabled";
//clocks = <&clkc CLKID_DOS
// &clkc CLKID_VAPB
// &clkc CLKID_HCODEC_MUX>;
//clock-names =
// "clk_dos",
// "clk_apb_dos",
// "clk_jpeg_enc";
/*
clocks = <&clkc CLKID_HCODEC_P0>;
clock-names = "hcodec_p0";
*/
//power-domains = <&pwrdm PDID_T7_DOS_HCODEC>;
interrupts = <0 91 1 0 92 1 0 93 1>;
interrupt-names = "dos_mbox_slow_irq0", "dos_mbox_slow_irq1", "dos_mbox_slow_irq2";
//reset-names = "jpegenc_rst";
//resets = <&reset RESET_BRG_HCODEC_PIPL0>;
};
aml_enc {
compatible = "cnm, MultiEnc";
dev_name = "amvenc_multi";
status = "disabled";
config_mm_sz_mb = <200>;
//clocks = <&clkc CLKID_DOS
// &clkc CLKID_VAPB
// &clkc CLKID_WAVE_A_GATE
// &clkc CLKID_WAVE_B_GATE
// &clkc CLKID_WAVE_C_GATE>;
//clock-names =
// "clk_dos",
// "clk_apb_dos",
// "clk_MultiEnc_A",
// "clk_MultiEnc_B",
// "clk_MultiEnc_C";
interrupts = <0 94 1 0 95 1>;
interrupt-names = "multienc_irq", "multienc_idle_irq";
#address-cells=<2>;
#size-cells=<2>;
pwr-ctl = <0>;
//power-domains = <&pwrdm PDID_T7_DOS_WAVE>;
ranges;
io_reg_base {
reg = <0x0 0xfe310000 0x0 0x10000>;
};
};
vpu: vpu {
compatible = "amlogic, vpu-t7";
status = "disabled";
reg = <0x0 0xfe000000 0x0 0x100 /* clk */
0x0 0xfe00c000 0x0 0x70 /* pwrctrl */
0x0 0xff000000 0x0 0xa000>; /* vcbus */
//clocks = <&clkc CLKID_VAPB>,
// <&clkc CLKID_VPU_INTR>,
// <&clkc CLKID_VPU_0>,
// <&clkc CLKID_VPU_1>,
// <&clkc CLKID_VPU>;
//clock-names = "vapb_clk",
// "vpu_intr_gate",
// "vpu_clk0",
// "vpu_clk1",
// "vpu_clk";
clk_level = <7>;
/* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */
/* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */
};
meson_uvm{
compatible = "amlogic, meson_uvm";
status = "disabled";
};
meson_videotunnel{
compatible = "amlogic, meson_videotunnel";
status = "disabled";
};
video_composer {
compatible = "amlogic, video_composer";
dev_name = "video_composer";
status = "disabled";
};
rdma{
compatible = "amlogic, meson-t7, rdma";
status = "disabled";
interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "rdma";
/* after sc2 */
//reset-names = "rdma";
//resets = <&reset RESET_RDMA>;
rdma_table_page_count = <16>;
};
vclk_serve: vclk_serve {
compatible = "amlogic, vclk_serve";
status = "disabled";
reg = <0x0 0xfe008000 0x0 0x400 /* ana reg */
0x0 0xfe000000 0x0 0x4a0>; /* clk reg */
};
vout_venc: vout_venc {
compatible = "amlogic, vout_venc-t7";
status = "disabled";
};
vout: vout {
compatible = "amlogic, vout";
status = "disabled";
/* fr_policy:
* 0: disable
* 1: nearby (only for 60->59.94 and 30->29.97)
* 2: force (60/50/30/24/59.94/23.97)
*/
fr_policy = <2>;
};
vout2: vout2 {
compatible = "amlogic, vout2";
status = "disabled";
/* fr_policy:
* 0: disable
* 1: nearby (only for 60->59.94 and 30->29.97)
* 2: force (60/50/30/24/59.94/23.97)
*/
fr_policy = <2>;
};
vout3: vout3 {
compatible = "amlogic, vout3";
status = "disabled";
/* fr_policy:
* 0: disable
* 1: nearby (only for 60->59.94 and 30->29.97)
* 2: force (60/50/30/24/59.94/23.97)
*/
fr_policy = <2>;
};
ir: ir@8000 {
compatible = "amlogic, meson-ir";
reg = <0x0 0xfe084040 0x0 0x44>,
<0x0 0xfe084000 0x0 0x20>;
status = "disable";
protocol = <REMOTE_TYPE_NEC>;
interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
map = <&custom_maps>;
max_frame_time = <200>;
};
a76_tsensor: a76_tsensor@fe020000 {
compatible = "amlogic, r1p1-tsensor";
status = "okay";
reg = <0x0 0xfe020000 0x0 0x50>;
tsensor_id = <1>;
cal_type = <0x11>;
cal_coeff = <324 424 3159 9411>;
rtemp = <115000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_TS_CLK>;
clock-names = "ts_comp";
#thermal-sensor-cells = <1>;
};
a55_tsensor: a55_tsensor@fe022000 {
compatible = "amlogic, r1p1-tsensor";
status = "okay";
reg = <0x0 0xfe022000 0x0 0x50>;
tsensor_id = <2>;
cal_type = <0x11>;
cal_coeff = <324 424 3159 9411>;
rtemp = <115000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_TS_CLK>;
clock-names = "ts_comp";
#thermal-sensor-cells = <1>;
};
ddr0_tsensor: ddr0_tsensor@fe01e000 {
compatible = "amlogic, r1p1-tsensor";
status = "okay";
reg = <0x0 0xfe01e000 0x0 0x50>;
tsensor_id = <3>;
cal_type = <0x11>;
cal_coeff = <324 424 3159 9411>;
rtemp = <115000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_TS_CLK>;
clock-names = "ts_comp";
#thermal-sensor-cells = <1>;
};
ddr1_tsensor: ddr1_tsensor@fe01c000 {
compatible = "amlogic, r1p1-tsensor";
status = "okay";
reg = <0x0 0xfe01c000 0x0 0x50>;
tsensor_id = <4>;
cal_type = <0x11>;
cal_coeff = <324 424 3159 9411>;
rtemp = <115000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_TS_CLK>;
clock-names = "ts_comp";
#thermal-sensor-cells = <1>;
};
nna_tsensor: nna_tsensor@fe096000 {
compatible = "amlogic, r1p1-tsensor";
status = "okay";
reg = <0x0 0xfe096000 0x0 0x50>;
tsensor_id = <5>;
cal_type = <0x11>;
cal_coeff = <324 424 3159 9411>;
rtemp = <115000>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_TS_CLK>;
clock-names = "ts_comp";
#thermal-sensor-cells = <1>;
power-domains = <&pwrdm PDID_P1_NNA_TOP>;
};
meson_cooldev: meson-cooldev@0 {
status = "okay";
compatible = "amlogic, meson-cooldev";
cooling_devices {
cpucore_cool_cluster0 {
cluster_id = <0>;
node_name = "cpucore_cool0";
device_type = "cpucore";
};
cpucore_cool_cluster1 {
cluster_id = <1>;
node_name = "cpucore_cool1";
device_type = "cpucore";
};
gpufreq_cool {
dyn_coeff = <358>;
node_name = "bifrost";
device_type = "gpufreq";
};
};
cpucore_cool0:cpucore_cool0 {
#cooling-cells = <2>;
};
cpucore_cool1:cpucore_cool1 {
#cooling-cells = <2>;
};
};/*meson cooling devices end*/
thermal-zones {
soc_thermal: soc_thermal {
status = "okay";
polling-delay = <1000>;
polling-delay-passive = <100>;
sustainable-power = <5160>;
thermal-sensors = <&a76_tsensor 0>;
trips {
a76switch_on: trip-point@0 {
temperature = <80000>;
hysteresis = <5000>;
type = "passive";
};
a76control: trip-point@1 {
temperature = <90000>;
hysteresis = <5000>;
type = "passive";
};
a76hot: trip-point@2 {
temperature = <100000>;
hysteresis = <5000>;
type = "hot";
};
a76critical: trip-point@3 {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
cpufreq_cooling_map {
trip = <&a76control>;
cooling-device = <&CPU6 0 8>;
contribution = <1024>;
};
cpucore_cooling_map {
trip = <&a76hot>;
cooling-device = <&cpucore_cool1 0 2>;
contribution = <1024>;
};
};
};
a55_thermal: a55_thermal {
status = "okay";
polling-delay = <2000>;
polling-delay-passive = <1000>;
sustainable-power = <960>;
thermal-sensors = <&a55_tsensor 1>;
trips {
a55switch_on: trip-point@0 {
temperature = <80000>;
hysteresis = <5000>;
type = "passive";
};
a55control: trip-point@1 {
temperature = <90000>;
hysteresis = <5000>;
type = "passive";
};
a55hot: trip-point@2 {
temperature = <100000>;
hysteresis = <5000>;
type = "hot";
};
a55critical: trip-point@3 {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
cpucore_cooling_map {
trip = <&a55hot>;
cooling-device = <&cpucore_cool0 0 6>;
contribution = <1024>;
};
cpufreq_cooling_map {
trip = <&a55control>;
cooling-device = <&CPU0 0 8>;
contribution = <1024>;
};
};
};
ddr0_thermal: ddr0_thermal {
status = "okay";
polling-delay = <2000>;
polling-delay-passive = <1000>;
sustainable-power = <400>;
thermal-sensors = <&ddr0_tsensor 2>;
trips {
ddr0switch_on: trip-point@0 {
temperature = <80000>;
hysteresis = <5000>;
type = "passive";
};
ddr0control: trip-point@1 {
temperature = <90000>;
hysteresis = <5000>;
type = "passive";
};
ddr0critical: trip-point@2 {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
};
ddr1_thermal: ddr1_thermal {
status = "okay";
polling-delay = <2000>;
polling-delay-passive = <1000>;
sustainable-power = <400>;
thermal-sensors = <&ddr1_tsensor 3>;
trips {
ddr1switch_on: trip-point@0 {
temperature = <80000>;
hysteresis = <5000>;
type = "passive";
};
ddr1control: trip-point@1 {
temperature = <90000>;
hysteresis = <5000>;
type = "passive";
};
ddr1critical: trip-point@2 {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
};
nna_thermal: nna_thermal {
status = "okay";
polling-delay = <2000>;
polling-delay-passive = <1000>;
sustainable-power = <3550>;
thermal-sensors = <&nna_tsensor 4>;
trips {
nnaswitch_on: trip-point@0 {
temperature = <80000>;
hysteresis = <5000>;
type = "passive";
};
nnacontrol: trip-point@1 {
temperature = <90000>;
hysteresis = <5000>;
type = "passive";
};
nnacritical: trip-point@2 {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
};
};/*thermal zone end*/
ion_dev {
compatible = "amlogic, ion_dev";
memory-region = <&ion_cma_reserved>;
status = "okay";
};
fb: fb {
compatible = "amlogic, fb-t7";
memory-region = <&logo_reserved>;
status = "disabled";
interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING
GIC_SPI 194 IRQ_TYPE_EDGE_RISING
GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "viu-vsync", "viu2-vsync", "rdma";
/* uboot logo,fb0/fb1 memory size,if afbcd fb0=0x01851000*/
display_mode_default = "1080p60hz";
scale_mode = <1>;
/** 0:VPU free scale 1:OSD free scale 2:OSD super scale */
display_size_default = <1920 1080 1920 2160 32>;
/*1920*1080*4*3 = 0x17BB000*/
//clocks = <&clkc CLKID_VPU_CLKC_MUX>;
clock-names = "vpu_clkc";
};
irblaster: meson-irblaster@fe08410c {
compatible = "amlogic, meson_irblaster";
status = "disabled";
reg = <0x0 0xfe08410c 0x0 0x10>;
#irblaster-cells = <2>;
interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
};
/*if you want to use vdin just modify status to "ok"*/
vdin0: vdin0 {/*common define*/
compatible = "amlogic, vdin-t7";
dev_name = "vdin0";
status = "disabled";
/*memory-region = <&vdin0_cma_reserved>;*/
reserve-iomap = "true";
flag_cma = <0x101>;/*1:share with codec_mm;2:cma alone*/
/*MByte, if 10bit disable: 64M(YUV422),
*if 10bit enable: 64*1.5 = 96M(YUV422)
*if support 4K2K-YUV444-10bit-WR:3840*2160*4*4 ~= 128M
*if support 4K2K-YUV422-10bit-wr:3840*2160*3*4 ~= 96M
*if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M
*if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M
* onebuffer:
* worst case:(4096*2160*3 + 2M(afbce issue)) = 27.5M
* dw:960x540x3 = 1.5M
* total size:(27.5+1.5)x buffernumber
*/
/*cma_size = <174>;*/
/*frame_buff_num = <6>;*/
interrupts = <0 210 1 /* vdin0 vsync */
0 214 1 /* vdin1 write down*/
/*0 206 1*/ /* vpu crash */
/*0 213 1*/>; /* vdin0 write down*/
interrupt-names = "vsync_int",
"mif2_meta_wr_done_int"
/*"vpu_crash_int",*/
/*"write_done_int"*/;
rdma-irq = <2>;
//clocks = <&clkc CLKID_FCLK_DIV5>, <&clkc CLKID_VDIN_MEAS_GATE>;
clock-names = "fclk_div5", "cts_vdin_meas_clk";
vdin_id = <0>;
/*vdin write mem color depth support:
* bit0:support 8bit
* bit1:support 9bit
* bit2:support 10bit
* bit3:support 12bit
* bit4:support yuv422 10bit full pack mode (from txl new add)
* bit8:use 8bit at 4k_50/60hz_10bit
* bit9:use 10bit at 4k_50/60hz_10bit
* bit10: support 10bit when double write
*/
tv_bit_mode = <0x215>;
/* afbce_bit_mode: (amlogic frame buff compression encoder)
* bit0 -- enable afbce
* bit1 -- enable afbce compression-lossy
* bit4 -- afbce for 4k
* bit5 -- afbce for 1080p
* bit6 -- afbce for 720p
* bit7 -- afbce for smaller resolution
*/
afbce_bit_mode = <0x31>;
/* urgent_en; */
double_write_en;
};
vdin1: vdin1 {/*common define*/
compatible = "amlogic, vdin-t7";
dev_name = "vdin1";
status = "disabled";
reserve-iomap = "true";
/*memory-region = <&vdin1_cma_reserved>;*/
flag_cma = <0>;/*1:share with codec_mm;0:cma alone*/
interrupts = <0 212 1>;
interrupt-names = "vsync_int"/*, "vpu_crash_int",*/
/*"write_done_int"*/;
rdma-irq = <4>;
/*clocks = <&clock CLK_FPLL_DIV5>,
* <&clock CLK_VDIN_MEAS_CLK>;
*clock-names = "fclk_div5", "cts_vdin_meas_clk";
*/
vdin_id = <1>;
tv_bit_mode = <0x15>;
};
amlvecm: amlvecm {
compatible = "amlogic, vecm-t7";
status = "disable";
dev_name = "aml_vecm";
/*status = "okay";*/
/*gamma_en = <1>;*/ /*1:enabel ;0:disable*/
/*wb_en = <1>;*/ /*1:enabel ;0:disable*/
/*cm_en = <1>;*/ /*1:enabel ;0:disable*/
/*wb_sel = <0>;*/ /*1:mtx ;0:gainoff*/
/*vlock_en = <1>;*/ /*1:enable;0:disable*/
/*vlock_mode = <0x8>;*/
/* vlock work mode:
*bit0:auto ENC
*bit1:auto PLL
*bit2:manual PLL
*bit3:manual ENC
*bit4:manual soft ENC
*bit5:manual MIX PLL ENC
*/
/* vlock_pll_m_limit = <1>;*/
/* vlock_line_limit = <2>;*/
//clocks = <&clkc CLKID_VID_LOCK>;
clock-names = "cts_vid_lock_clk";
};
meson-amvideom {
compatible = "amlogic, amvideom-t7";
dev_name = "amvideom";
status = "disable";
interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING
GIC_SPI 194 IRQ_TYPE_EDGE_RISING
GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "vsync", "vsync_viu2", "vsync_viu3";
};
vpu_security {
compatible = "amlogic, meson-t7, vpu_security";
dev_name = "amlogic-vpu-security";
status = "disabled";
interrupts = <GIC_SPI 220 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "vpu_security";
};
dmx_aucpu: aucpu {
compatible = "amlogic, aucpu";
dev_name = "aml_aucpu";
status = "disabled";
interrupts = <0 77 1>;
interrupt-names = "aucpu_irq";
#address-cells=<2>;
#size-cells=<2>;
ranges;
io_reg_base{
reg = <0x0 0xfe09e080 0x0 0x100>;
};
};
ge2d {
compatible = "amlogic, ge2d-p1";
status = "okay";
interrupts = <GIC_SPI 94 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ge2d";
clocks = <&clkc CLKID_VAPB_0>,
<&clkc CLKID_GE2D>;
clock-names = "clk_vapb_0",
"clk_ge2d_gate";
reg = <0x0 0xff840000 0x0 0x100>;
power-domains = <&pwrdm PDID_P1_GE2D>;
};
aml_bt: aml_bt {
compatible = "amlogic, aml-bt";
status = "disabled";
};
aml_wifi: aml_wifi {
compatible = "amlogic, aml-wifi";
status = "disabled";
irq_trigger_type = "GPIO_IRQ_LOW";
dhd_static_buf;
//pinctrl-0 = <&pwm_e_pins>;
//pinctrl-names = "default";
pwm_config = <&wifi_pwm_conf>;
};
wifi_pwm_conf:wifi_pwm_conf{
pwm_channel1_conf {
pwms = <&pwm_ab 0 30550 0>;
duty-cycle = <15270>;
times = <8>;
};
pwm_channel2_conf {
pwms = <&pwm_ab 2 30500 0>;
duty-cycle = <15250>;
times = <12>;
};
};
gdc {
#address-cells=<2>;
#size-cells=<2>;
status = "disabled";
compatible = "amlogic, arm-gdc";
reg = <0 0xfe08e000 0 0x0000100>;
interrupts = <GIC_SPI 223 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "gdc";
//clocks = <&clkc CLKID_GDCCLK_0>,
// <&clkc CLKID_GDCCLK>,
// <&clkc CLKID_GDC_CLK>;
//clock-names = "mux_gate", "mux_sel", "clk_gate";
clk-rate = <800000000>;
// power-domains = <&pwrdm PDID_T7_GDC>;
};
amlgdc {
#address-cells=<2>;
#size-cells=<2>;
status = "okay";
compatible = "amlogic, aml-gdc-v2";
reg = <0 0xfe040000 0 0x000015c>,
<0 0xfe03e000 0 0x000015c>,
<0 0xfe03c000 0 0x000015c>;
interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 61 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "amlgdc", "amlgdc1", "amlgdc2";
clocks = <&clkc CLKID_DEWARPA>,
<&clkc CLKID_DEWARPB>,
<&clkc CLKID_DEWARPC>;
clock-names = "clk_gate",
"clk_gate1",
"clk_gate2";
clk-rate = <800000000>;
power-domains = <&pwrdm PDID_P1_DEWA>,
<&pwrdm PDID_P1_DEWB>,
<&pwrdm PDID_P1_DEWC>;
};
mhu_fifo: mhu@0 {
status = "okay";
compatible = "amlogic, meson_mhu_fifo";
reg = <0x0 0xfe006000 0x0 0x1000>, /* mhu wr fifo */
<0x0 0xfe00719C 0x0 0x80>, /* mhu set reg */
<0x0 0xfe00721C 0x0 0x80>, /* mhu clr reg */
<0x0 0xfe00729C 0x0 0x80>, /* mhu sts reg */
<0x0 0xfe007044 0x0 0xc0>; /* mhu irqctrl reg */
interrupts = <0 248 1>; /* irq top */
mbox-irqmax = <64>;
mbox-irqctlr = <2>;
mbox-irqclr = <1>;
mbox-nums = <10>;
mbox-names = "dsp_dev",
"ap_to_dspa",
"dspb_dev",
"ap_to_dspb",
"ao_to_ap",
"ap_to_ao",
"ree2bl40a",
"ree2bl40a_send",
"ree2bl40b",
"ree2bl40b_send";
mboxes = <&mhu_fifo P1_DSPA2REE>,
<&mhu_fifo P1_REE2DSPA>,
<&mhu_fifo P1_DSPB2REE>,
<&mhu_fifo P1_REE2DSPB>,
<&mhu_fifo P1_AO2REE>,
<&mhu_fifo P1_REE2AO>,
<&mhu_fifo P1_BL40A2REE>,
<&mhu_fifo P1_REE2BL40A>,
<&mhu_fifo P1_BL40B2REE>,
<&mhu_fifo P1_REE2BL40B>;
mbox-id = <0x0 0x1 0x6 0x7 0x2 0x3 0xe 0xf 0x12 0x13>;
mbox-wr-rd = <1>;
#mbox-cells = <1>;
};
mbox_user: mbox-user@0 {
status = "okay";
compatible = "amlogic, meson-mbox-user";
mbox-nums = <5>;
mbox-names = "ree2aocpu",
"tree2dspa",
"tree2dspb",
"tree2mfa",
"tree2mfb";
mboxes = <&mhu_fifo P1_REE2AO>,
<&mhu_fifo P1_REE2DSPA>,
<&mhu_fifo P1_REE2DSPB>,
<&mhu_fifo P1_REE2BL40A>,
<&mhu_fifo P1_REE2BL40B>;
mbox-dests = <MAILBOX_AOCPU>,
<MAILBOX_DSP>,
<MAILBOX_DSP>,
<MAILBOX_MF>,
<MAILBOX_MF>;
};
aml_hwlock: aml_hwlock@0 {
status = "okay";
compatible = "amlogic, meson-hwspinlock";
reg = <0x0 0xfe006a80 0x0 0x80>;
bakery-cpus = <5>;
#hwlock-cells = <1>;
};
lut_dma:lut_dma {
compatible = "amlogic, meson-t7, lut_dma";
status = "disabled";
};
state_led:state_led {
compatible = "amlogic,state-led-aocpu";
status = "disabled";
};
efuse: efuse{
compatible = "amlogic, efuse";
read_cmd = <0x82000030>;
write_cmd = <0x82000031>;
get_max_cmd = <0x82000033>;
mem_in_base_cmd = <0x82000020>;
mem_out_base_cmd = <0x82000021>;
efuse_pattern_size = <0x600>;
key = <&efusekey>;
clock-names = "efuse_clk";
status = "disabled";
};
efusekey:efusekey{
status = "disabled";
keynum = <4>;
key0 = <&key_0>;
key1 = <&key_1>;
key2 = <&key_2>;
key3 = <&key_3>;
key_0:key_0{
keyname = "mac";
offset = <0>;
size = <6>;
};
key_1:key_1{
keyname = "mac_bt";
offset = <6>;
size = <6>;
};
key_2:key_2{
keyname = "mac_wifi";
offset = <12>;
size = <6>;
};
key_3:key_3{
keyname = "usid";
offset = <18>;
size = <16>;
};
};
mfh: mfh {
compatible = "amlogic, mfh";
#address-cells = <2>;
#size-cells = <2>;
memory-region = <&mfh_fw_reserved>;
power-domains = <&pwrdm PDID_P1_M4A>,
<&pwrdm PDID_P1_M4B>;
power-domain-names = "m4a-core","m4b-core";
clocks = <&clkc CLKID_M4_CLK_0>,
<&clkc CLKID_M4_CLK_1>,
<&clkc CLKID_M4_CLK>,
<&clkc CLKID_M4_PLL>;
clock-names = "m4_clk0", "m4_clk1", "m4_clk", "m4_pll";
mfh-cnt = <2>;
mfh-addr-offset = <0x40000>;
mfh-name = "mfha",
"mfhb";
};
};
&periphs_pinctrl {
i2c0_pins1:i2c0_pins1 {
mux {
groups = "i2c0_sda",
"i2c0_sck";
function = "i2c0";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c1_pins1:i2c1_pins1 {
mux {
groups = "i2c1_sda_x",
"i2c1_sck_x";
function = "i2c1";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c1_pins2:i2c1_pins2 {
mux {
groups = "i2c1_sda_k",
"i2c1_sck_k";
function = "i2c1";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c2_pins1:i2c2_pins1 {
mux {
groups = "i2c2_sda_x",
"i2c2_sck_x";
function = "i2c2";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c2_pins2:i2c2_pins2 {
mux {
groups = "i2c2_sda_k",
"i2c2_sck_k";
function = "i2c2";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c3_pins1:i2c3_pins1 {
mux {
groups = "i2c3_sda_h",
"i2c3_sck_h";
function = "i2c3";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c3_pins2:i2c3_pins2 {
mux {
groups = "i2c3_sda_w",
"i2c3_sck_w";
function = "i2c3";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c4_pins1:i2c4_pins1 {
mux {
groups = "i2c4_sda_t8",
"i2c4_sck_t9";
function = "i2c4";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c4_pins2:i2c4_pins2 {
mux {
groups = "i2c4_sda_t28",
"i2c4_sck_t26";
function = "i2c4";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c5_pins1:i2c5_pins1 {
mux {
groups = "i2c5_sda",
"i2c5_sck";
function = "i2c5";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c6_pins1:i2c6_pins1 {
mux {
groups = "i2c6_sda_c",
"i2c6_sck_c";
function = "i2c6";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c6_pins2:i2c6_pins2 {
mux {
groups = "i2c6_sda_w",
"i2c6_sck_w";
function = "i2c6";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c7_pins1:i2c7_pins1 {
mux {
groups = "i2c7_sda_e",
"i2c7_sck_e";
function = "i2c7";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c7_pins2:i2c7_pins2 {
mux {
groups = "i2c7_sda_c",
"i2c7_sck_c";
function = "i2c7";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c8_pins1:i2c8_pins1 {
mux {
groups = "i2c8_sda_c",
"i2c8_sck_c";
function = "i2c8";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c8_pins2:i2c8_pins2 {
mux {
groups = "i2c8_sda_e",
"i2c8_sck_e";
function = "i2c8";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c9_pins1:i2c9_pins1 {
mux {
groups = "i2c9_sda",
"i2c9_sck";
function = "i2c9";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c10_pins1:i2c10_pins1 {
mux {
groups = "i2c10_sda",
"i2c10_sck";
function = "i2c10";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c0_slave_pins:i2c0_slave_pins {
mux {
groups = "i2c0_slave_sda",
"i2c0_slave_sck";
function = "i2c0_slave";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c1_slave_pins:i2c1_slave_pins {
mux {
groups = "i2c1_slave_sda",
"i2c1_slave_sck";
function = "i2c1_slave";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c2_slave_pins:i2c2_slave_pins {
mux {
groups = "i2c2_slave_sda",
"i2c2_slave_sck";
function = "i2c2_slave";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c3_slave_pins:i2c3_slave_pins {
mux {
groups = "i2c3_slave_sda",
"i2c3_slave_sck";
function = "i2c3_slave";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c4_slave_pins:i2c4_slave_pins {
mux {
groups = "i2c4_slave_sda",
"i2c4_slave_sck";
function = "i2c4_slave";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c5_slave_pins:i2c5_slave_pins {
mux {
groups = "i2c5_slave_sda",
"i2c5_slave_sck";
function = "i2c5_slave";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c6_slave_pins:i2c6_slave_pins {
mux {
groups = "i2c6_slave_sda",
"i2c6_slave_sck";
function = "i2c6_slave";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c7_slave_pins:i2c7_slave_pins {
mux {
groups = "i2c7_slave_sda_e",
"i2c7_slave_sck_e";
function = "i2c7_slave";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c8_slave_pins:i2c8_slave_pins {
mux {
groups = "i2c8_slave_sda",
"i2c8_slave_sck";
function = "i2c8_slave";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c9_slave_pins:i2c9_slave_pins {
mux {
groups = "i2c9_slave_sda",
"i2c9_slave_sck";
function = "i2c9_slave";
drive-strength-microamp = <3000>;
bias-disable;
};
};
i2c10_slave_pins:i2c10_slave_pins {
mux {
groups = "i2c10_slave_sda",
"i2c10_slave_sck";
function = "i2c10_slave";
drive-strength-microamp = <3000>;
bias-disable;
};
};
a_uart_pins1:a_uart1 {
mux {
groups = "uart_a_tx_d2",
"uart_a_rx_d3";
function = "uart_a";
};
};
a_uart_pins2:a_uart2 {
mux {
groups = "uart_a_tx_d8",
"uart_a_rx_d9";
function = "uart_a";
};
};
b_uart_pins1:b_uart1 {
mux {
groups = "uart_b_tx_h",
"uart_b_rx_h";
function = "uart_b";
};
};
b_uart_pins2:b_uart2 {
mux {
groups = "uart_b_tx_w",
"uart_b_rx_w";
function = "uart_b";
};
};
c_uart_pins:c_uart {
mux {
groups = "uart_c_tx",
"uart_c_rx",
"uart_c_cts",
"uart_c_rts";
bias-pull-up;
output-high;
function = "uart_c";
};
};
d_uart_pins:d_uart {
mux {
groups = "uart_d_tx",
"uart_d_rx";
function = "uart_d";
};
};
e_uart_pins1:e_uart1 {
mux {
groups = "uart_e_tx_k",
"uart_e_rx_k";
function = "uart_e";
};
};
e_uart_pins2:e_uart2 {
mux {
groups = "uart_e_tx_z",
"uart_e_rx_z";
function = "uart_e";
};
};
f_uart_pins1:f_uart1 {
mux {
groups = "uart_f_tx_k",
"uart_f_rx_k";
function = "uart_f";
};
};
f_uart_pins2:f_uart2 {
mux {
groups = "uart_f_tx_y",
"uart_f_rx_y";
function = "uart_f";
};
};
/* sdemmc portB */
sd_clk_cmd_pins:sd_clk_cmd_pins {
mux {
groups = "sdcard_cmd";
function = "sdcard";
bias-pull-up;
drive-strength-microamp = <4000>;
};
mux1 {
groups = "sdcard_clk";
function = "sdcard";
bias-pull-up;
drive-strength-microamp = <4000>;
};
};
sd_all_pins:sd_all_pins {
mux {
groups = "sdcard_d0",
"sdcard_d1",
"sdcard_d2",
"sdcard_d3",
"sdcard_cmd";
function = "sdcard";
bias-pull-up;
drive-strength-microamp = <4000>;
};
mux1 {
groups = "sdcard_clk";
function = "sdcard";
bias-pull-up;
drive-strength-microamp = <4000>;
};
};
sd_clk_gate_pins: sd_clk_gate {
mux {
groups = "GPIOC_4";
function = "gpio_periphs";
bias-pull-down;
drive-strength-microamp = <4000>;
};
};
sd_all_pd_pins:sd_all_pd_pins {
mux {
groups = "GPIOC_0",
"GPIOC_1",
"GPIOC_2",
"GPIOC_3",
"GPIOC_4",
"GPIOC_5";
function = "gpio_periphs";
bias-pull-down;
output-low;
};
};
sd_1bit_pins:sd_1bit_pins {
mux {
groups = "sdcard_d0",
"sdcard_cmd";
function = "sdcard";
bias-pull-up;
drive-strength-microamp = <4000>;
};
mux1 {
groups = "sdcard_clk";
function = "sdcard";
bias-pull-up;
drive-strength-microamp = <4000>;
};
};
sd_clr_all_pins:sd_clr_all_pins {
mux {
groups = "GPIOC_0",
"GPIOC_1",
"GPIOC_2",
"GPIOC_3",
"GPIOC_5";
function = "gpio_periphs";
output-high;
};
mux1 {
groups = "GPIOC_4";
function = "gpio_periphs";
output-low;
};
};
sd_clr_noall_pins:sd_clr_noall_pins {
mux {
groups = "GPIOC_0",
"GPIOC_1",
"GPIOC_4",
"GPIOC_5";
function = "gpio_periphs";
output-high;
};
};
ao_to_sd_uart_pins:ao_to_sd_uart_pins {
mux {
groups = "uart_ao_tx_a_c3",
"uart_ao_rx_a_c2";
function = "uart_ao_a_ee";
bias-pull-up;
input-enable;
};
};
sd_iso7816_pins:sd_iso7816_pins {
mux {
groups = "iso7816_clk_z",
"iso7816_data_z";
function = "iso7816";
input-enable;
bias-pull-down;
};
};
/* sdio port A */
sdio_pins: sdio {
mux {
groups = "sdio_d0",
"sdio_d1",
"sdio_d2",
"sdio_d3",
"sdio_clk",
"sdio_cmd";
function = "sdio";
//bias-disable;
bias-pull-up;
drive-strength-microamp = <4000>;
};
};
sdio_clk_gate_pins: sdio_clk_gate {
mux {
groups = "GPIOM_4";
function = "gpio_periphs";
bias-pull-down;
drive-strength-microamp = <4000>;
};
};
hdmitx_hpd: hdmitx_hpd {
mux {
groups = "hdmitx_hpd_in";
function = "hdmitx";
bias-disable;
};
};
hdmitx_hpd_gpio: hdmitx_hpd_gpio {
mux {
groups = "GPIOW_15";
function = "gpio_periphs";
bias-disable;
};
};
hdmitx_ddc: hdmitx_ddc {
mux {
groups = "hdmitx_sda_w13",
"hdmitx_sck_w14";
function = "hdmitx";
bias-disable;
drive-strength-microamp = <3000>;
};
};
hdmirx_a_mux:hdmirx_a_mux {
mux {
groups = "hdmirx_a_hpd",
"hdmirx_a_det",
"hdmirx_a_sda",
"hdmirx_a_sck";
function = "hdmirx_a";
};
};
hdmirx_b_mux:hdmirx_b_mux {
mux {
groups = "hdmirx_b_hpd",
"hdmirx_b_det",
"hdmirx_b_sda",
"hdmirx_b_sck";
function = "hdmirx_b";
};
};
hdmirx_c_mux:hdmirx_c_mux {
mux {
groups = "hdmirx_c_hpd",
"hdmirx_c_det",
"hdmirx_c_sda",
"hdmirx_c_sck";
function = "hdmirx_c";
};
};
cec_a: cec_a {
mux {
groups = "cec_a";
function = "cec_a";
};
};
cec_b: cec_b {
mux {
groups = "cec_b";
function = "cec_b";
};
};
jtag_a_pins: jtag_a_pin {
mux {
groups = "jtag_a_tdi",
"jtag_a_tdo",
"jtag_a_clk",
"jtag_a_tms";
function = "jtag_a";
};
};
jtag_trace_pins: jtag_trace_pin {
mux {
groups = "jtag_trace_clka",
"jtag_trace_ctl",
"jtag_trace_d0",
"jtag_trace_d1",
"jtag_trace_d2",
"jtag_trace_d3",
"jtag_trace_d4",
"jtag_trace_d5",
"jtag_trace_d6",
"jtag_trace_d7",
"jtag_trace_d8",
"jtag_trace_d9",
"jtag_trace_d10",
"jtag_trace_d11",
"jtag_trace_d12",
"jtag_trace_d13",
"jtag_trace_d14",
"jtag_trace_d15";
function = "jtag_trace";
};
};
pwm_a_pins1: pwm_a_pins1 {
mux {
groups = "pwm_a_e";
function = "pwm_a";
drive-strength-microamp = <500>;
};
};
pwm_a_pins2: pwm_a_pins2 {
mux {
groups = "pwm_a_t";
function = "pwm_a";
drive-strength-microamp = <500>;
};
};
pwm_b_pins: pwm_b_pins {
mux {
groups = "pwm_b";
function = "pwm_b";
};
};
pwm_c_pins: pwm_c_pins {
mux {
groups = "pwm_c";
function = "pwm_c";
};
};
pwm_d_pins1: pwm_d_pins1 {
mux {
groups = "pwm_d_d";
function = "pwm_d";
};
};
pwm_d_pins2: pwm_d_pins2 {
mux {
groups = "pwm_d_e";
function = "pwm_d";
};
};
pwm_e_pins: pwm_e_pins {
mux {
groups = "pwm_e";
function = "pwm_e";
};
};
pwm_f_pins: pwm_f_pins {
mux {
groups = "pwm_f";
function = "pwm_f";
};
};
pwm_g_pins: pwm_g_pins {
mux {
groups = "pwm_g";
function = "pwm_g";
};
};
pwm_h_pins: pwm_h_pins {
mux {
groups = "pwm_h";
function = "pwm_h";
};
};
pwm_i_pins: pwm_i_pins {
mux {
groups = "pwm_i";
function = "pwm_i";
};
};
pwm_j_pins: pwm_j_pins {
mux {
groups = "pwm_j";
function = "pwm_j";
};
};
remote_pins: remote_pin {
mux {
groups = "remote_in";
function = "remote_in";
bias-disable;
};
};
spicc0_pins: spicc0_pins {
mux {
groups = "spi_a_mosi",
"spi_a_miso",
//"spi_a_ss0",used as GPIOH_9
"spi_a_clk";
function = "spi_a";
drive-strength-microamp = <2000>;
};
};
spicc1_pins: spicc1_pins {
mux {
groups = "spi_b_mosi",
"spi_b_miso",
//"spi_b_ss0",used as GPIOH_13
"spi_b_clk";
function = "spi_b";
drive-strength-microamp = <2000>;
};
};
spicc1_cs_pins: spicc1_cs_pins {
mux {
groups = "spi_b_ss0";
function = "spi_b";
drive-strength-microamp = <2000>;
};
};
spicc2_pins_h: spicc2_pins_h {
mux {
groups = "spi_c_mosi_h",
"spi_c_miso_h",
//"spi_c_ss0_h",used as GPIOH_17
"spi_c_clk_h";
function = "spi_c";
drive-strength-microamp = <2000>;
};
};
spicc2_pins_x: spicc2_pins_x {
mux {
groups = "spi_c_mosi_x",
"spi_c_miso_x",
//"spi_c_ss0_x",used as GPIOX_29
"spi_c_clk_x";
function = "spi_c";
drive-strength-microamp = <2000>;
};
};
spicc3_pins_k: spicc3_pins_k {
mux {
groups = "spi_d_mosi_k",
"spi_d_miso_k",
//"spi_d_ss0_k",used as GPIOK_3
"spi_d_clk_k";
function = "spi_d";
drive-strength-microamp = <2000>;
};
};
spicc3_pins_x: spicc3_pins_x {
mux {
groups = "spi_d_mosi_x",
"spi_d_miso_x",
//"spi_d_ss0_x",used as GPIOX_3
"spi_d_clk_x";
function = "spi_d";
drive-strength-microamp = <2000>;
};
};
spicc4_pins_k: spicc4_pins_k {
mux {
groups = "spi_e_mosi_k",
"spi_e_miso_k",
//"spi_e_ss0_k",used as GPIOK_7
"spi_e_clk_k";
function = "spi_e";
drive-strength-microamp = <2000>;
};
};
spicc4_pins_x: spicc4_pins_x {
mux {
groups = "spi_e_mosi_x",
"spi_e_miso_x",
//"spi_e_ss0_x",used as GPIOX_18
"spi_e_clk_x";
function = "spi_e";
drive-strength-microamp = <2000>;
};
};
spicc5_pins: spicc5_pins {
mux {
groups = "spi_f_mosi",
"spi_f_miso",
//"spi_f_ss0",used as GPIOT_13
"spi_f_clk";
function = "spi_f";
drive-strength-microamp = <2000>;
};
};
irblaster_pins1:irblaster_pin1 {
mux {
groups = "remote_out_d4";
function = "remote_out";
};
};
irblaster_pins2:irblaster_pin2 {
mux {
groups = "remote_out_d6";
function = "remote_out";
};
};
spdifout_d: spdifout_d {
mux { /* GPIOD_8 */
groups = "spdif_out_d";
function = "spdif_out";
};
};
spdifout_d_mute: spdifout_d_mute {
mux { /* GPIOD_8 */
groups = "GPIOD_8";
function = "gpio_periphs";
output-low;
};
};
spdifout_t: spdifout_t {
mux { /* GPIOT_3 */
groups = "spdif_out_t";
function = "spdif_out";
};
};
spdifout_t_mute: spdifout_t_mute {
mux { /* GPIOT_3 */
groups = "GPIOT_3";
function = "gpio_periphs";
output-low;
};
};
spdifin_d: spdifin_d {
mux {/* GPIOD_9 */
groups = "spdif_in_d";
function = "spdif_in";
};
};
spdifin_t: spdifin_t {
mux {/* GPIOT_4 */
groups = "spdif_in_t";
function = "spdif_in";
};
};
mclk_0_pins: mclk_0_pin {
mux { /* GPIOT_14 */
groups = "mclk_0";
function = "mclk";
};
};
mclk_1_pins: mclk_1_pin {
mux { /* GPIOT_19 */
groups = "mclk_1";
function = "mclk";
};
};
mclk_2_pins: mclk_2_pin {
mux { /* GPIOT_K8 */
groups = "mclk_2";
function = "mclk";
};
};
mclk_3_pins: mclk_3_pin {
mux { /* GPIOT_W0 */
groups = "mclk_3_w";
function = "mclk";
};
};
lcd_vbyone_a_pins: lcd_vbyone_a_pin {
mux {
groups = "vx1_a_htpdn","vx1_a_lockn";
function = "vx1_a";
};
};
lcd_vbyone_b_pins: lcd_vbyone_b_pin {
mux {
groups = "vx1_b_htpdn","vx1_b_lockn";
function = "vx1_b";
};
};
lcd_edp_a_pins: lcd_edp_a_pin {
mux {
groups = "edp_a_hpd";
function = "edp_a";
};
};
lcd_edp_b_pins: lcd_edp_b_pin {
mux {
groups = "edp_b_hpd";
function = "edp_b";
};
};
eth_pins: eth {
mux {
groups = "eth_mdio",
"eth_mdc",
"eth_rgmii_rx_clk",
"eth_rx_dv",
"eth_rxd0",
"eth_rxd1",
"eth_txen",
"eth_txd0",
"eth_txd1";
function = "eth";
drive-strength-microamp = <4000>;
bias-disable;
};
};
eth_rgmii_pins: eth-rgmii {
mux {
groups = "eth_rxd2_rgmii",
"eth_rxd3_rgmii",
"eth_rgmii_tx_clk",
"eth_txd2_rgmii",
"eth_txd3_rgmii";
function = "eth";
drive-strength-microamp = <4000>;
bias-disable;
};
};
pcieck_pins: pcieck_pin {
mux {
groups = "pcieck_reqn_d";
function = "pcieck";
};
};
};
&storage_pinctrl {
emmc_pins: emmc {
mux-0 {
groups = "emmc_nand_d0",
"emmc_nand_d1",
"emmc_nand_d2",
"emmc_nand_d3",
"emmc_nand_d4",
"emmc_nand_d5",
"emmc_nand_d6",
"emmc_nand_d7",
"emmc_cmd";
function = "emmc";
bias-pull-up;
drive-strength-microamp = <4000>;
};
mux-1 {
groups = "emmc_clk";
function = "emmc";
bias-disable;
drive-strength-microamp = <4000>;
};
};
emmc_ds_pins: emmc-ds {
mux {
groups = "emmc_nand_ds";
function = "emmc";
bias-pull-down;
drive-strength-microamp = <4000>;
};
};
emmc_clk_gate_pins: emmc_clk_gate {
mux {
groups = "GPIOB_8";
function = "gpio_storage";
bias-pull-down;
drive-strength-microamp = <4000>;
};
};
spifc_all_pins: spifc_all_pins {
mux {
groups = "spif_hold",
"spif_mo",
"spif_mi",
"spif_clk",
"spif_wp",
"spif_cs";
function = "spif";
drive-strength-microamp = <3000>;
};
};
};
&gpu{
status = "disabled";
reg = <0 0xFE400000 0 0x04000>, /*mali APB bus base address*/
<0 0xFE002000 0 0x01000>, /*reset register*/
<0 0xFF800000 0 0x01000>, /*aobus TODO update*/
<0 0xFE000000 0 0x01000>, /*hiubus for clk cntl*/
<0 0xFE002000 0 0x01000>; /*reset register*/
interrupts = <0 144 4>, <0 145 4>, <0 146 4>;
interrupt-names = "GPU", "MMU", "JOB";
// power-domains = <&pwrdm PDID_T7_MALI_TOP>;
num_of_pp = <4>;
system-coherency = <0>;
//clocks = <&clkc CLKID_MALI_MUX>;
clock-names = "gpu_mux";
/*
* Mali clocking is provided by two identical clock paths
* MALI_0 and MALI_1 muxed to a single clock by a glitch
* free mux to safely change frequency while running.
*/
//assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
// <&clkc CLKID_MALI_0>,
// <&clkc CLKID_MALI_MUX>; /* Glitch free mux */
//assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>,
// <0>, /* Do Nothing */
// <&clkc CLKID_MALI_0>;
//assigned-clock-rates = <0>, /* Do Nothing */
// <800000000>,
// <0>; /* Do Nothing */
tbl = <&dvfs250_cfg
&dvfs400_cfg
&dvfs500_cfg
&dvfs666_cfg
&dvfs800_cfg
&dvfs800_cfg>;
reset_cfg:reset_cfg {
reg_level = <0x11>;
reg_mask = <0x21>;
reg_bit = <2>;
};
capb_reset:capb_reset {
reg_level = <0x11>;
reg_mask = <0x21>;
reg_bit = <1>;
};
};