| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright (c) 2019 Amlogic, Inc. All rights reserved. |
| */ |
| |
| /dts-v1/; |
| |
| #include "meson-tm2.dtsi" |
| #include "mesontm2_drm.dtsi" |
| #include "partition_normal_linux.dtsi" |
| |
| / { |
| compatible = "amlogic,tm2"; |
| model = "AML AB311"; |
| |
| aliases { |
| serial0 = &uart_AO; |
| serial1 = &uart_A; |
| serial2 = &uart_B; |
| serial3 = &uart_C; |
| serial4 = &uart_AO_B; |
| ethernet0 = ðmac; |
| i2c0 = &i2c0; |
| i2c1 = &i2c1; |
| i2c2 = &i2c2; |
| i2c3 = &i2c3; |
| i2c4 = &i2c_AO; |
| spi1 = &spicc0; |
| spi2 = &spicc1; |
| tsensor0 = &p_tsensor; |
| tsensor1 = &d_tsensor; |
| }; |
| |
| chosen { |
| stdout-path = "serial0:115200n8"; |
| }; |
| |
| memory@0 { |
| device_type = "memory"; |
| reg = <0x0 0x0 0x0 0x80000000>; |
| }; |
| |
| adc_keypad { |
| compatible = "amlogic, adc_keypad"; |
| status = "okay"; |
| key_name = "vol-", "vol+", "enter"; |
| key_num = <3>; |
| io-channels = <&saradc 2>; |
| io-channel-names = "key-chan-2"; |
| key_chan = <2 2 2>; |
| key_code = <114 115 28>; |
| key_val = <143 266 389>; //val=voltage/1800mV*1023 |
| key_tolerance = <40 40 40>; |
| }; |
| |
| ao_5v: regulator-ao_5v { |
| compatible = "regulator-fixed"; |
| regulator-name = "AO_5V"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| vin-supply = <&dc_in>; |
| regulator-always-on; |
| }; |
| |
| dc_in: regulator-dc_in { |
| compatible = "regulator-fixed"; |
| regulator-name = "DC_IN"; |
| regulator-min-microvolt = <12000000>; |
| regulator-max-microvolt = <12000000>; |
| regulator-always-on; |
| }; |
| |
| reserved-memory { |
| secmon_reserved:linux,secmon { |
| compatible = "shared-dma-pool"; |
| reusable; |
| size = <0x0 0x400000>; |
| alignment = <0x0 0x400000>; |
| alloc-ranges = <0x0 0x05000000 0x0 0x400000>; |
| }; |
| |
| dsp_fw_reserved:linux,dsp_fw { |
| compatible = "shared-dma-pool"; |
| reusable; |
| size = <0x0 0x1000000>; |
| alignment = <0x0 0x400000>; |
| alloc-ranges = <0x0 0x30000000 0x0 0x1000000>; |
| }; |
| |
| /* POST PROCESS MANAGER */ |
| ppmgr_reserved:linux,ppmgr { |
| compatible = "shared-dma-pool"; |
| size = <0x0>; |
| }; |
| |
| logo_reserved:linux,meson-fb { |
| compatible = "shared-dma-pool"; |
| reusable; |
| size = <0x0 0x800000>; |
| alignment = <0x0 0x400000>; |
| alloc-ranges = <0x0 0x7f800000 0x0 0x800000>; |
| }; |
| |
| ion_cma_reserved:linux,ion-dev { |
| compatible = "shared-dma-pool"; |
| reusable; |
| size = <0x0 0x8000000>; |
| alignment = <0x0 0x400000>; |
| }; |
| ion_fb_reserved:linux,ion-fb { |
| compatible = "shared-dma-pool"; |
| reusable; |
| /* 1920x1080x4x3 round up 4M align */ |
| size = <0x0 0x0000000>; |
| alignment = <0x0 0x400000>; |
| }; |
| |
| codec_mm_cma:linux,codec_mm_cma { |
| compatible = "shared-dma-pool"; |
| reusable; |
| /* ion_codec_mm max can alloc size 80M*/ |
| size = <0x0 0x1bc00000>; |
| alignment = <0x0 0x400000>; |
| linux,contiguous-region; |
| }; |
| |
| /* codec shared reserved */ |
| codec_mm_reserved:linux,codec_mm_reserved { |
| compatible = "amlogic, codec-mm-reserved"; |
| size = <0x0 0x0>; |
| alignment = <0x0 0x100000>; |
| }; |
| |
| /*di CMA pool */ |
| di_cma_reserved:linux,di_cma { |
| //compatible = "shared-dma-pool"; |
| //reusable; |
| //size = <0x0 0x02800000>; |
| //alignment = <0x0 0x400000>; |
| }; |
| |
| /* vdin0 CMA pool */ |
| //vdin0_cma_reserved:linux,vdin0_cma { |
| // compatible = "shared-dma-pool"; |
| // reusable; |
| /* 3840x2160x4x4 ~=128 M */ |
| // size = <0x0 0xc400000>; |
| // alignment = <0x0 0x400000>; |
| //}; |
| |
| /* vdin1 CMA pool */ |
| vdin1_cma_reserved:linux,vdin1_cma { |
| compatible = "shared-dma-pool"; |
| reusable; |
| /* 1920x1080x2x5 =20 M */ |
| size = <0x0 0x1400000>; |
| alignment = <0x0 0x400000>; |
| }; |
| |
| /*demod_reserved:linux,demod { |
| * compatible = "amlogic, demod-mem"; |
| * size = <0x0 0x800000>; //8M //100m 0x6400000 |
| * alloc-ranges = <0x0 0x0 0x0 0x30000000>; |
| * //multi-use; |
| * //no-map; |
| *}; |
| */ |
| |
| demod_cma_reserved:linux,demod_cma { |
| compatible = "shared-dma-pool"; |
| reusable; |
| /* 8M */ |
| size = <0x0 0x0800000>; |
| alignment = <0x0 0x400000>; |
| }; |
| }; |
| |
| codec_mm { |
| compatible = "amlogic, codec, mm"; |
| memory-region = <&codec_mm_cma &codec_mm_reserved>; |
| dev_name = "codec_mm"; |
| status = "okay"; |
| }; |
| |
| ppmgr { |
| compatible = "amlogic, ppmgr"; |
| memory-region = <&ppmgr_reserved>; |
| dev_name = "ppmgr"; |
| status = "okay"; |
| }; |
| |
| hdmirx { |
| compatible = "amlogic, hdmirx_tm2_b"; |
| #address-cells=<1>; |
| #size-cells=<1>; |
| /*memory-region = <&hdmirx_emp_cma_reserved>;*/ |
| status = "okay"; |
| pinctrl-names = "hdmirx_pins"; |
| pinctrl-0 = <&hdmirx_a_mux &hdmirx_b_mux |
| &hdmirx_c_mux>; |
| repeat = <0>; |
| /* bit 4: tdr enable bit |
| * bits [3:0]: tdr level control |
| */ |
| term_lvl = <0x11>; |
| interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clkc CLKID_HDMIRX_MODET_GATE>, |
| <&clkc CLKID_HDMIRX_CFG_GATE>, |
| <&clkc CLKID_HDMIRX_ACR_GATE>, |
| <&clkc CLKID_HDMIRX_METER_GATE>, |
| <&clkc CLKID_HDMIRX_AXI_GATE>, |
| <&xtal>, |
| <&clkc CLKID_FCLK_DIV3>, |
| <&clkc CLKID_FCLK_DIV5>, |
| <&clkc CLKID_FCLK_DIV7>, |
| <&clkc CLKID_HDMIRX_SKP_GATE>, |
| <&clkc CLKID_HDMIRX_ESM_GATE>; |
| //<&clkc CLK_AUD_PLL2FS>, |
| //<&clkc CLK_AUD_PLL4FS>, |
| //<&clkc CLK_AUD_OUT>; |
| clock-names = "hdmirx_modet_clk", |
| "hdmirx_cfg_clk", |
| "hdmirx_acr_ref_clk", |
| "cts_hdmirx_meter_clk", |
| "cts_hdmi_axi_clk", |
| "xtal", |
| "fclk_div3", |
| "fclk_div5", |
| "fclk_div7", |
| "hdcp_rx22_skp", |
| "hdcp_rx22_esm"; |
| //"hdmirx_aud_pll2fs", |
| //"hdmirx_aud_pll4f", |
| //"clk_aud_out"; |
| hdmirx_id = <0>; |
| en_4k_2_2k = <0>; |
| hpd_low_cec_off = <0>; |
| cec_dev_en = <0>; |
| arc_port = <1>; |
| /* bit4: enable feature, bit3~0: port number */ |
| disable_port = <0x0>; |
| /* hdcp_tee_path = <1>; */ |
| /* MAP_ADDR_MODULE_CBUS */ |
| /* MAP_ADDR_MODULE_HIU */ |
| /* MAP_ADDR_MODULE_HDMIRX_CAPB3 */ |
| /* MAP_ADDR_MODULE_SEC_AHB */ |
| /* MAP_ADDR_MODULE_SEC_AHB2 */ |
| /* MAP_ADDR_MODULE_APB4 */ |
| /* MAP_ADDR_MODULE_TOP */ |
| /* MAP_ADDR_MODULE_CLK_CTRL */ |
| reg = < 0x0 0x0 0x0 0x0 |
| 0x0 0xff63C000 0x0 0x2000 |
| 0x0 0xffe0d000 0x0 0x2000 |
| 0x0 0x0 0x0 0x0 |
| 0x0 0x0 0x0 0x0 |
| 0x0 0x0 0x0 0x0 |
| 0x0 0xff610000 0x0 0xa000>; |
| }; |
| |
| aml_dtv_demod { |
| compatible = "amlogic, ddemod-tm2"; |
| dev_name = "aml_dtv_demod"; |
| status = "okay"; |
| |
| //pinctrl-names="dtvdemod_agc"; |
| //pinctrl-0=<&dtvdemod_agc>; |
| |
| clocks = <&clkc CLKID_DAC_CLK>; |
| clock-names = "vdac_clk_gate"; |
| |
| reg = <0x0 0xff650000 0x0 0x4000 /*dtv demod base*/ |
| 0x0 0xff63c000 0x0 0x2000 /*hiu reg base*/ |
| 0x0 0xff800000 0x0 0x1000 /*io_aobus_base*/ |
| 0x0 0xffd01000 0x0 0x1000 /*reset*/ |
| >; |
| |
| dtv_demod0_mem = <0>; // need move to aml_dtv_demod ? |
| spectrum = <1>; |
| cma_flag = <1>; |
| cma_mem_size = <8>; |
| memory-region = <&demod_cma_reserved>;//<&demod_reserved>; |
| |
| power-domains = <&pwrc PWRC_TM2_DEMOD_ID>; |
| }; |
| |
| atv-demod { |
| compatible = "amlogic, atv-demod"; |
| status = "okay"; |
| btsc_sap_mode = <1>; |
| interrupts = <0 236 1>; |
| /* pinctrl-names="atvdemod_agc_pins"; */ |
| /* pinctrl-0=<&atvdemod_agc_pins>; */ |
| reg = <0x0 0xff656000 0x0 0x2000 /* demod reg */ |
| 0x0 0xff63c000 0x0 0x2000 /* hiu reg */ |
| 0x0 0xff634000 0x0 0x2000 /* periphs reg */ |
| 0x0 0xff64a000 0x0 0x2000>; /* audio reg */ |
| reg_23cf = <0x88188832>; |
| /*default:0x88188832;r840 on haier:0x48188832*/ |
| power-domains = <&pwrc PWRC_TM2_ATVDEMOD_ID>; |
| }; |
| |
| dvb-extern { |
| compatible = "amlogic, dvb-extern"; |
| dev_name = "dvb-extern"; |
| status = "okay"; |
| |
| fe_num = <1>; |
| fe0_demod = "internal"; |
| |
| tuner_num = <1>; /* tuner number, multi tuner support */ |
| tuner0_name = "si2151_tuner"; |
| tuner0_i2c_adap = <&i2c0>; |
| tuner0_i2c_addr = <0x60>; |
| /* tuner0_xtal = <0>; */ /* unuse for si2151 */ |
| /* tuner0_xtal_mode = <0>; */ |
| /* tuner0_xtal_cap = <0>; */ |
| }; |
| |
| dvb-demux { |
| compatible = "amlogic, dvb-demux"; |
| dev_name = "dvb-demux"; |
| status = "okay"; |
| |
| dmx = <&demux>; |
| key_endia = <1>; |
| add_s2p2 = <1>; |
| add_ts_in = <1>; |
| add_asyncfifo = <1>; |
| |
| /*"parallel","serial","disable"*/ |
| ts2 = "parallel"; |
| ts2_control = <0>; |
| ts2_invert = <0>; |
| |
| clocks = <&clkc CLKID_DEMUX |
| &clkc CLKID_AHB_ARB0 |
| &clkc CLKID_U_PARSER>; |
| clock-names = "demux", "ahbarb0", "parser_top"; |
| pinctrl-names = "p_ts2"; |
| pinctrl-0 = <&dvb_p_ts2_pins>; |
| }; |
| |
| tvafe_avin_detect { |
| compatible = "amlogic, tm2_tvafe_avin_detect"; |
| status = "disabled"; |
| device_mask = <1>;/*bit0:ch1;bit1:ch2*/ |
| reg = <0x0 0xffd0f090 0x0 0x20>;/*cbus register*/ |
| interrupts = <0 12 1>, |
| <0 13 1>; |
| }; |
| |
| auge_sound { |
| compatible = "amlogic, auge-sound-card"; |
| aml-audio-card,name = "AML-AUGESOUND"; |
| |
| avout_mute-gpios = <&gpio GPIODV_3 GPIO_ACTIVE_HIGH>; |
| |
| interrupts = <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "audio_exception64"; |
| |
| aml-audio-card,dai-link@0 { |
| format = "i2s"; |
| mclk-fs = <256>; |
| continuous-clock; |
| //bitclock-inversion; |
| //frame-inversion; |
| /* master mode */ |
| bitclock-master = <&tdma>; |
| frame-master = <&tdma>; |
| /* slave mode */ |
| /* |
| * bitclock-master = <&tdmacodec>; |
| * frame-master = <&tdmacodec>; |
| */ |
| /* suffix-name, sync with android audio hal used for */ |
| suffix-name = "alsaPORT-i2s"; |
| tdmacpu: cpu { |
| sound-dai = <&tdma>; |
| dai-tdm-slot-tx-mask = |
| <1 1>; |
| dai-tdm-slot-rx-mask = |
| <1 1>; |
| dai-tdm-slot-num = <2>; |
| dai-tdm-slot-width = <32>; |
| system-clock-frequency = <12288000>; |
| }; |
| tdmacodec: codec { |
| //sound-dai = <&dummy_codec>; |
| prefix-names = "AMP", "AMP1"; |
| sound-dai = <&ad82584f &ad82584f1 &tl1_codec>; |
| }; |
| }; |
| |
| aml-audio-card,dai-link@1 { |
| format = "i2s"; |
| mclk-fs = <256>; |
| //continuous-clock; |
| //bitclock-inversion; |
| //frame-inversion; |
| /* master mode */ |
| bitclock-master = <&tdmb>; |
| frame-master = <&tdmb>; |
| /* slave mode */ |
| //bitclock-master = <&tdmbcodec>; |
| //frame-master = <&tdmbcodec>; |
| /* suffix-name, sync with android audio hal used for */ |
| suffix-name = "alsaPORT-pcm"; |
| cpu { |
| sound-dai = <&tdmb>; |
| dai-tdm-slot-tx-mask = <1 1>; |
| dai-tdm-slot-rx-mask = <1 1>; |
| dai-tdm-slot-num = <2>; |
| /* |
| * dai-tdm-slot-tx-mask = |
| * <1 1 1 1 1 1 1 1>; |
| * dai-tdm-slot-rx-mask = |
| * <1 1 1 1 1 1 1 1>; |
| * dai-tdm-slot-num = <8>; |
| */ |
| dai-tdm-slot-width = <32>; |
| system-clock-frequency = <12288000>; |
| }; |
| tdmbcodec: codec { |
| sound-dai = <&dummy_codec>; |
| }; |
| }; |
| |
| aml-audio-card,dai-link@2 { |
| format = "i2s"; |
| mclk-fs = <256>; |
| //continuous-clock; |
| //bitclock-inversion; |
| //frame-inversion; |
| /* master mode */ |
| bitclock-master = <&tdmc>; |
| frame-master = <&tdmc>; |
| /* slave mode */ |
| //bitclock-master = <&tdmccodec>; |
| //frame-master = <&tdmccodec>; |
| /* suffix-name, sync with android audio hal used for */ |
| //suffix-name = "alsaPORT-tdm"; |
| cpu { |
| sound-dai = <&tdmc>; |
| dai-tdm-slot-tx-mask = <1 1>; |
| dai-tdm-slot-rx-mask = <1 1>; |
| dai-tdm-slot-num = <2>; |
| dai-tdm-slot-width = <32>; |
| system-clock-frequency = <12288000>; |
| }; |
| tdmccodec: codec { |
| sound-dai = <&dummy_codec>; |
| }; |
| }; |
| |
| aml-audio-card,dai-link@3 { |
| mclk-fs = <64>; |
| /* suffix-name, sync with android audio hal used for */ |
| suffix-name = "alsaPORT-pdm"; |
| cpu { |
| sound-dai = <&pdm>; |
| }; |
| codec { |
| sound-dai = <&dummy_codec>; |
| }; |
| }; |
| |
| aml-audio-card,dai-link@4 { |
| mclk-fs = <128>; |
| continuous-clock; |
| /* suffix-name, sync with android audio hal used for */ |
| suffix-name = "alsaPORT-spdif"; |
| cpu { |
| sound-dai = <&spdifa>; |
| system-clock-frequency = <6144000>; |
| }; |
| codec { |
| sound-dai = <&dummy_codec>; |
| }; |
| }; |
| |
| aml-audio-card,dai-link@5 { |
| mclk-fs = <128>; |
| suffix-name = "alsaPORT-spdifb"; |
| cpu { |
| sound-dai = <&spdifb>; |
| system-clock-frequency = <6144000>; |
| }; |
| codec { |
| sound-dai = <&dummy_codec>; |
| }; |
| }; |
| |
| aml-audio-card,dai-link@6 { |
| mclk-fs = <256>; |
| suffix-name = "alsaPORT-tv"; |
| cpu { |
| sound-dai = <&extn>; |
| system-clock-frequency = <12288000>; |
| }; |
| codec { |
| sound-dai = <&dummy_codec>; |
| }; |
| }; |
| |
| aml-audio-card,dai-link@7 { |
| mclk-fs = <256>; |
| suffix-name = "alsaPORT-earc"; |
| cpu { |
| sound-dai = <&earc>; |
| system-clock-frequency = <12288000>; |
| }; |
| codec { |
| sound-dai = <&dummy_codec>; |
| }; |
| }; |
| |
| aml-audio-card,dai-link@8 { |
| mclk-fs = <256>; |
| continuous-clock; |
| suffix-name = "alsaPORT-loopback"; |
| cpu { |
| sound-dai = <&loopbacka>; |
| system-clock-frequency = <12288000>; |
| }; |
| codec { |
| sound-dai = <&dummy_codec>; |
| }; |
| }; |
| }; |
| |
| amlvecm { |
| compatible = "amlogic, vecm-tm2-verb"; |
| dev_name = "aml_vecm"; |
| status = "okay"; |
| gamma_en = <0>;/*1:enabel ;0:disable*/ |
| wb_en = <0>;/*1:enabel ;0:disable*/ |
| cm_en = <0>;/*1:enabel ;0:disable*/ |
| wb_sel = <0>;/*1:mtx ;0:gainoff*/ |
| vlock_en = <0>;/*1:enable;0:disable*/ |
| vlock_mode = <0x8>; |
| /* vlock work mode: |
| *bit0:auto ENC |
| *bit1:auto PLL |
| *bit2:manual PLL |
| *bit3:manual ENC |
| *bit4:manual soft ENC |
| *bit5:manual MIX PLL ENC |
| */ |
| vlock_pll_m_limit = <1>; |
| vlock_line_limit = <2>; |
| }; |
| |
| amdolby_vision { |
| compatible = "amlogic, dolby_vision_tm2"; |
| dev_name = "aml_amdolby_vision_driver"; |
| status = "okay"; |
| tv_mode = <0>;/*1:enabel ;0:disable*/ |
| }; |
| |
| vdin@0 { |
| compatible = "amlogic, vdin-tm2verb"; |
| /*memory-region = <&vdin0_cma_reserved>;*/ |
| status = "okay"; |
| /*bit0:(1:share with codec_mm;0:cma alone) |
| *bit8:(1:alloc in discontinus way;0:alone in continuous way) |
| */ |
| flag_cma = <0x101>; |
| /*MByte, if 10bit disable: 64M(YUV422), |
| *if 10bit enable: 64*1.5 = 96M(YUV422) |
| *if support 4K2K-YUV444-10bit-WR:3840*2160*4*6 ~= 200M |
| *if support 4K2K-YUV422-10bit-wr:3840*2160*3*6 ~= 160M |
| *if support 4K2K-YUV422-8BIT-WR:3840*2160*2*4 ~= 64M |
| *if support 1080p-YUV422-8BIT-WR:1920*1080*2*4 ~= 16M |
| *worst case:(4096*2160*3 + 2M(afbce issue)) *10buf = 273.5M |
| *for double write 4k, need extra 25M for 960x540(1/4 down) |
| */ |
| cma_size = <300>; |
| /* max buffer number */ |
| frame_buff_num = <10>; |
| interrupts = <0 83 1 /* vdin0 vsync */ |
| 0 72 1>;/* vpu crash */ |
| rdma-irq = <2>; |
| clocks = <&clkc CLKID_FCLK_DIV5>, |
| <&clkc CLKID_VDIN_MEAS>; |
| clock-names = "fclk_div5", "cts_vdin_meas_clk"; |
| vdin_id = <0>; |
| /*vdin write mem color depth support: |
| * bit0:support 8bit |
| * bit1:support 9bit |
| * bit2:support 10bit |
| * bit3:support 12bit |
| * bit4:support yuv422 10bit full pack mode (from txl new add) |
| * bit5:force yuv422 to yuv444 malloc (for vdin0 debug) |
| * bit8:use 8bit at 4k_50/60hz_10bit |
| * bit9:use 10bit at 4k_50/60hz_10bit |
| * bit10: support 10bit when double write |
| */ |
| tv_bit_mode = <0x235>; |
| /* afbce_bit_mode: (amlogic frame buff compression encoder) |
| * bit0 -- enable afbce |
| * bit1 -- enable afbce compression-lossy |
| * bit4 -- afbce for 4k |
| * bit5 -- afbce for 1080p |
| * bit6 -- afbce for 720p |
| * bit7 -- afbce for smaller resolution |
| */ |
| afbce_bit_mode = <0x11>; |
| /* urgent_en; */ |
| double_write_en; |
| v4l_support_en; |
| }; |
| |
| vdin@1 { |
| compatible = "amlogic, vdin-tm2verb"; |
| memory-region = <&vdin1_cma_reserved>; |
| status = "okay"; |
| /*bit0:(1:share with codec_mm;0:cma alone) |
| *bit8:(1:alloc in discontinus way;0:alone in continuous way) |
| */ |
| flag_cma = <0>; |
| interrupts = <0 85 1>; |
| rdma-irq = <4>; |
| clocks = <&clkc CLKID_FCLK_DIV5>, |
| <&clkc CLKID_VDIN_MEAS>; |
| clock-names = "fclk_div5", "cts_vdin_meas_clk"; |
| vdin_id = <1>; |
| /*vdin write mem color depth support: |
| *bit0:support 8bit |
| *bit1:support 9bit |
| *bit2:support 10bit |
| *bit3:support 12bit |
| */ |
| tv_bit_mode = <0x15>; |
| /*urgent_en*/ |
| }; |
| |
| vddao_1v8: regulator-vddao_1v8 { |
| compatible = "regulator-fixed"; |
| regulator-name = "VDDAO_1V8"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| vin-supply = <&vddao_3v3>; |
| regulator-always-on; |
| }; |
| |
| vddao_3v3: regulator-vddao_3v3 { |
| compatible = "regulator-fixed"; |
| regulator-name = "VDDAO_3V3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| vin-supply = <&dc_in>; |
| regulator-always-on; |
| }; |
| |
| vad_3v3: regulator-vad_3v3 { |
| compatible = "regulator-fixed"; |
| regulator-name = "VAD_3V3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| vin-supply = <&vddao_3v3>; |
| regulator-always-on; |
| }; |
| |
| multi-di { |
| //status = "okay"; |
| /*************************************************** |
| * memory: default is 4 |
| * 0:use reserved; |
| * 1:use cma; |
| * 2:use cma as reserved |
| * 4:use codec mem |
| ***************************************************/ |
| //flag_cma = <4>;//t5d unsupport 4K,di 1CH need 42M |
| //memory-region = <&di_cma_reserved>; |
| /*************************************************** |
| * clock-range: <min max> |
| * default: <334 334> |
| ***************************************************/ |
| //clock-range = <334 334>; |
| /*************************************************** |
| * en_4k: t5d not support 4k |
| ***************************************************/ |
| //en_4k = <0>; |
| //keep_dec_vf = <0>; |
| //po_fmt = <0>; |
| /*************************************************** |
| * post_nub: default is 7 |
| ***************************************************/ |
| //post_nub = <7>; |
| }; |
| |
| aocec: aocec { |
| compatible = "amlogic, aocec-tm2"; |
| /*device_name = "aocec";*/ |
| status = "okay"; |
| vendor_name = "Amlogic"; /* Max Chars: 8 */ |
| /* Refer to the following URL at: |
| * http://standards.ieee.org/develop/regauth/oui/oui.txt |
| */ |
| vendor_id = <0xffffff>; |
| product_desc = "TM2"; /* Max Chars: 16 */ |
| cec_osd_string = "AML_TV"; /* Max Chars: 14 */ |
| port_num = <4>; |
| ee_cec; |
| /*cec_sel = <2>;*/ |
| output = <1>; /*output port number*/ |
| arc_port_mask = <0x2>; |
| port_seq = <0xf321>; |
| interrupts = <0 203 1 |
| 0 199 1>; |
| interrupt-names = "hdmi_aocecb","hdmi_aocec"; |
| pinctrl-names = "default","hdmitx_aocecb","cec_pin_sleep"; |
| pinctrl-0=<&aoceca_mux>; |
| pinctrl-1=<&aocecb_mux>; |
| pinctrl-2=<&aoceca_mux>; |
| reg = <0x0 0xFF80023c 0x0 0x4 |
| 0x0 0xFF800000 0x0 0x400>; |
| reg-names = "ao_exit","ao"; |
| hdmi-phandle = <&drm_amhdmitx>; |
| }; |
| |
| cpu_opp_table0: cpu_opp_table0 { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| opp00 { |
| opp-hz = /bits/ 64 <100000000>; |
| opp-microvolt = <780000>; |
| }; |
| opp01 { |
| opp-hz = /bits/ 64 <250000000>; |
| opp-microvolt = <780000>; |
| }; |
| opp02 { |
| opp-hz = /bits/ 64 <500000000>; |
| opp-microvolt = <780000>; |
| }; |
| opp03 { |
| opp-hz = /bits/ 64 <667000000>; |
| opp-microvolt = <780000>; |
| }; |
| opp04 { |
| opp-hz = /bits/ 64 <1000000000>; |
| opp-microvolt = <780000>; |
| }; |
| opp05 { |
| opp-hz = /bits/ 64 <1200000000>; |
| opp-microvolt = <800000>; |
| }; |
| opp06 { |
| opp-hz = /bits/ 64 <1404000000>; |
| opp-microvolt = <810000>; |
| }; |
| opp07 { |
| opp-hz = /bits/ 64 <1500000000>; |
| opp-microvolt = <820000>; |
| }; |
| opp08 { |
| opp-hz = /bits/ 64 <1608000000>; |
| opp-microvolt = <870000>; |
| }; |
| opp09 { |
| opp-hz = /bits/ 64 <1704000000>; |
| opp-microvolt = <920000>; |
| }; |
| opp10 { |
| opp-hz = /bits/ 64 <1800000000>; |
| opp-microvolt = <970000>; |
| }; |
| opp11 { |
| opp-hz = /bits/ 64 <1908000000>; |
| opp-microvolt = <1020000>; |
| }; |
| }; |
| |
| cpufreq-meson { |
| compatible = "amlogic, cpufreq-meson"; |
| pinctrl-names = "default"; |
| //pinctrl-0 = <&pwm_ao_d_pins3>; |
| status = "okay"; |
| }; |
| |
| picdec { |
| compatible = "amlogic, picdec"; |
| status = "okay"; |
| }; |
| |
| tvafe { |
| compatible = "amlogic, tvafe-tm2_b"; |
| /*memory-region = <&tvafe_cma_reserved>;*/ |
| status = "okay"; |
| flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/ |
| cma_size = <5>;/*MByte*/ |
| reg = <0x0 0xff654000 0x0 0x2000 /*tvafe reg base*/ |
| 0x0 0xff63c000 0x0 0x2000>; /*hiu reg base*/ |
| reserve-iomap = "true"; |
| tvafe_id = <0>; |
| //pinctrl-names = "default"; |
| /*!!particular sequence, no more and no less!!!*/ |
| tvafe_pin_mux = < |
| 3 /* TVAFE_CVBS_IN2, CVBS_IN0 = 0 */ |
| 1 /* TVAFE_CVBS_IN0, CVBS_IN1 */ |
| 2 /* TVAFE_CVBS_IN1, CVBS_IN2 */ |
| 4 /* TVAFE_CVBS_IN3, CVBS_IN3 */ |
| >; |
| clocks = <&clkc CLKID_DAC_CLK>; |
| clock-names = "vdac_clk_gate"; |
| |
| cutwindow_val_h = <0 0 0 0 8>; /* level 0~4 */ |
| cutwindow_val_v = <4 8 14 16 24>; /* level 0~4 */ |
| |
| power-domains = <&pwrc PWRC_TM2_TVFE_ID>; |
| }; |
| |
| vbi { |
| compatible = "amlogic, vbi"; |
| status = "disabled"; |
| interrupts = <0 83 1>; |
| }; |
| |
| cvbsout { |
| compatible = "amlogic, cvbsout-tm2"; |
| status = "okay"; |
| clocks = <&clkc CLKID_VCLK2_ENCI |
| &clkc CLKID_VCLK2_VENCI0 |
| &clkc CLKID_VCLK2_VENCI1 |
| &clkc CLKID_DAC_CLK>; |
| clock-names = "venci_top_gate", |
| "venci_0_gate", |
| "venci_1_gate", |
| "vdac_clk_gate"; |
| /* clk path */ |
| /* 0:vid_pll vid2_clk */ |
| /* 1:gp0_pll vid2_clk */ |
| /* 2:vid_pll vid1_clk */ |
| /* 3:gp0_pll vid1_clk */ |
| clk_path = <0>; |
| |
| /* performance: reg_address, reg_value */ |
| /* tm2 */ |
| performance = <0x1bf0 0x9 |
| 0x1b56 0x333 |
| 0x1b12 0x8080 |
| 0x1b05 0xfd |
| 0x1c59 0xf850 |
| 0xffff 0x0>; /* ending flag */ |
| performance_sarft = <0x1bf0 0x9 |
| 0x1b56 0x333 |
| 0x1b12 0x0 |
| 0x1b05 0x9 |
| 0x1c59 0xfc48 |
| 0xffff 0x0>; /* ending flag */ |
| performance_revB_telecom = <0x1bf0 0x9 |
| 0x1b56 0x546 |
| 0x1b12 0x8080 |
| 0x1b05 0x9 |
| 0x1c59 0xf850 |
| 0xffff 0x0>; /* ending flag */ |
| }; |
| }; |
| |
| /* Exposed via the on-board USB to Serial FT232RL IC */ |
| &uart_AO { |
| status = "okay"; |
| }; |
| |
| &sd_emmc_b { |
| status = "okay"; |
| pinctrl-0 = <&sdcard_pins>; |
| pinctrl-1 = <&sdcard_clk_gate_pins>; |
| pinctrl-names = "default", "clk-gate"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| bus-width = <4>; |
| cap-sd-highspeed; |
| sd-uhs-sdr50; |
| sd-uhs-sdr104; |
| max-frequency = <200000000>; |
| |
| non-removable; |
| disable-wp; |
| cap-sdio-irq; |
| keep-power-in-suspend; |
| card_type = <3>; |
| |
| power-domains = <&pwrc PWRC_TM2_EMMCB_ID>; |
| // mmc-pwrseq = <&sdio_pwrseq>; |
| |
| vmmc-supply = <&vddao_3v3>; |
| vqmmc-supply = <&vddao_1v8>; |
| |
| brcmf: wifi@1 { |
| reg = <1>; |
| compatible = "brcm,bcm4329-fmac"; |
| }; |
| }; |
| |
| &sd_emmc_c { |
| status = "okay"; |
| pinctrl-0 = <&emmc_pins>, <&emmc_ds_pins>; |
| pinctrl-1 = <&emmc_clk_gate_pins>; |
| pinctrl-names = "default", "clk-gate"; |
| |
| bus-width = <8>; |
| cap-mmc-highspeed; |
| //mmc-ddr-1_8v; |
| mmc-hs200-1_8v; |
| mmc-hs400-1_8v; |
| max-frequency = <200000000>; |
| non-removable; |
| disable-wp; |
| |
| power-domains = <&pwrc PWRC_TM2_EMMCC_ID>; |
| // mmc-pwrseq = <&emmc_pwrseq>; |
| vmmc-supply = <&vddao_3v3>; |
| vqmmc-supply = <&vddao_1v8>; |
| }; |
| |
| ðmac { |
| status = "okay"; |
| phy-handle = <&internal_ephy>; |
| phy-mode = "rmii"; |
| }; |
| |
| &i2c0 { |
| status = "okay"; |
| clock-frequency = <300000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c0_dv_pins>; |
| }; |
| |
| &ir { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&remote_input_ao_pins>; |
| }; |
| |
| &audiobus { |
| tdma:tdm@0 { |
| compatible = "amlogic, tm2-revb-snd-tdma"; |
| #sound-dai-cells = <0>; |
| |
| dai-tdm-lane-slot-mask-in = <1 0>; |
| dai-tdm-lane-slot-mask-out = <1 1 1 1>; |
| dai-tdm-clk-sel = <0>; |
| |
| clocks = <&clkaudio CLKID_AUDIO_MCLK_A |
| &clkaudio CLKID_AUDIO_MCLK_PAD0 |
| &clkc CLKID_MPLL0 |
| &clkc CLKID_MPLL1 |
| &clkaudio CLKID_AUDIO_SPDIFOUT_A>; |
| clock-names = "mclk", "mclk_pad", "clk_srcpll", |
| "samesource_srcpll", "samesource_clk"; |
| |
| pinctrl-names = "tdm_pins"; |
| pinctrl-0 = <&tdma_mclk &tdmout_a>; |
| |
| /* |
| * 0: tdmout_a; |
| * 1: tdmout_b; |
| * 2: tdmout_c; |
| * 3: spdifout; |
| * 4: spdifout_b; |
| */ |
| samesource_sel = <3>; |
| |
| /* In for ACODEC_ADC */ |
| tdmin-src-name = "acodec_adc"; |
| /*enable default mclk(12.288M), before extern codec start*/ |
| start_clk_enable = <1>; |
| |
| /*tdm clk tuning enable*/ |
| clk_tuning_enable = <1>; |
| |
| /* enable control gain */ |
| ctrl_gain = <1>; |
| |
| status = "okay"; |
| |
| /* !!!For --TV platform-- ONLY */ |
| Channel_Mask { |
| /*i2s has 4 pins, 8channel, mux output*/ |
| Spdif_samesource_Channel_Mask = "i2s_2/3"; |
| }; |
| }; |
| |
| tdmb:tdm@1 { |
| compatible = "amlogic, tm2-revb-snd-tdmb"; |
| #sound-dai-cells = <0>; |
| |
| dai-tdm-lane-slot-mask-in = <1 0 0 0>; |
| dai-tdm-lane-slot-mask-out = <0 1 0 0>; |
| dai-tdm-clk-sel = <1>; |
| |
| clocks = <&clkaudio CLKID_AUDIO_MCLK_B |
| &clkc CLKID_MPLL1>; |
| clock-names = "mclk", "clk_srcpll"; |
| |
| /* enable control gain */ |
| ctrl_gain = <1>; |
| |
| status = "okay"; |
| }; |
| |
| tdmc:tdm@2 { |
| compatible = "amlogic, tm2-revb-snd-tdmc"; |
| #sound-dai-cells = <0>; |
| |
| dai-tdm-lane-slot-mask-in = <1 0 0 0>; |
| dai-tdm-lane-slot-mask-out = <1 0 0 0>; |
| dai-tdm-clk-sel = <2>; |
| |
| clocks = <&clkaudio CLKID_AUDIO_MCLK_C |
| &clkc CLKID_MPLL2>; |
| clock-names = "mclk", "clk_srcpll"; |
| |
| pinctrl-names = "tdm_pins"; |
| pinctrl-0 = <&tdmout_c &tdmin_c>; |
| |
| /* enable control gain */ |
| ctrl_gain = <1>; |
| |
| status = "okay"; |
| }; |
| |
| tdmlb:tdm@3 { |
| compatible = "amlogic, tm2-snd-tdmlb"; |
| #sound-dai-cells = <0>; |
| |
| dai-tdm-lane-lb-slot-mask-in = <1 0 0 0>; |
| dai-tdm-clk-sel = <1>; |
| |
| clocks = <&clkaudio CLKID_AUDIO_MCLK_B |
| &clkc CLKID_MPLL1>; |
| clock-names = "mclk", "clk_srcpll"; |
| |
| /* |
| * select tdmin_lb src; |
| * AXG |
| * 0: TDMOUTA |
| * 1: TDMOUTB |
| * 2: TDMOUTC |
| * 3: PAD_TDMINA |
| * 4: PAD_TDMINB |
| * 5: PAD_TDMINC |
| * |
| * G12A/G12B |
| * 0: TDMOUTA |
| * 1: TDMOUTB |
| * 2: TDMOUTC |
| * 3: PAD_TDMINA_DIN* |
| * 4: PAD_TDMINB_DIN* |
| * 5: PAD_TDMINC_DIN* |
| * 6: PAD_TDMINA_D*, oe pin |
| * 7: PAD_TDMINB_D*, oe pin |
| * |
| * TL1/SM1 |
| * 0: TDMOUTA |
| * 1: TDMOUTB |
| * 2: TDMOUTC |
| * 3: PAD_TDMINA_DIN* |
| * 4: PAD_TDMINB_DIN* |
| * 5: PAD_TDMINC_DIN* |
| * 6: PAD_TDMINA_D* |
| * 7: PAD_TDMINB_D* |
| * 8: PAD_TDMINC_D* |
| * 9: HDMIRX_I2S |
| * 10: ACODEC_ADC |
| */ |
| lb-src-sel = <1>; |
| |
| status = "disabled"; |
| }; |
| |
| pdm:pdm { |
| compatible = "amlogic, tm2-snd-pdm"; |
| #sound-dai-cells = <0>; |
| |
| clocks = <&clkaudio CLKID_AUDIO_GATE_PDM |
| &clkc CLKID_FCLK_DIV3 |
| &clkc CLKID_MPLL3 |
| &clkaudio CLKID_AUDIO_PDMIN0 |
| &clkaudio CLKID_AUDIO_PDMIN1>; |
| clock-names = "gate", |
| "sysclk_srcpll", |
| "dclk_srcpll", |
| "pdm_dclk", |
| "pdm_sysclk"; |
| |
| pinctrl-names = "pdm_pins"; |
| pinctrl-0 = <&pdmin>; |
| |
| /* mode 0~4, defalut:1 */ |
| filter_mode = <1>; |
| |
| status = "okay"; |
| }; |
| |
| spdifa:spdif@0 { |
| compatible = "amlogic, tm2-revb-snd-spdif-a"; |
| #sound-dai-cells = <0>; |
| |
| clocks = <&clkc CLKID_MPLL1 |
| &clkc CLKID_FCLK_DIV4 |
| &clkaudio CLKID_AUDIO_GATE_SPDIFIN |
| &clkaudio CLKID_AUDIO_GATE_SPDIFOUT_A |
| &clkaudio CLKID_AUDIO_SPDIFIN |
| &clkaudio CLKID_AUDIO_SPDIFOUT_A>; |
| clock-names = "sysclk", "fixed_clk", "gate_spdifin", |
| "gate_spdifout", "clk_spdifin", "clk_spdifout"; |
| |
| interrupts = |
| <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "irq_spdifin"; |
| |
| pinctrl-names = "spdif_pins", |
| "spdif_pins_mute"; |
| pinctrl-0 = <&spdifin_a>; |
| //pinctrl-1 = <&spdifout_a_mute>; |
| |
| /* |
| * whether do asrc for pcm and resample a or b |
| * if raw data, asrc is disabled automatically |
| * 0: "Disable", |
| * 1: "Enable:32K", |
| * 2: "Enable:44K", |
| * 3: "Enable:48K", |
| * 4: "Enable:88K", |
| * 5: "Enable:96K", |
| * 6: "Enable:176K", |
| * 7: "Enable:192K", |
| */ |
| asrc_id = <0>; |
| auto_asrc = <0>; |
| |
| /*spdif clk tuning enable*/ |
| clk_tuning_enable = <1>; |
| status = "okay"; |
| }; |
| |
| spdifb:spdif@1 { |
| compatible = "amlogic, tm2-revb-snd-spdif-b"; |
| #sound-dai-cells = <0>; |
| |
| clocks = <&clkc CLKID_MPLL0 /*CLKID_HIFI_PLL*/ |
| &clkaudio CLKID_AUDIO_GATE_SPDIFOUT_B |
| &clkaudio CLKID_AUDIO_SPDIFOUT_B>; |
| clock-names = "sysclk", |
| "gate_spdifout", "clk_spdifout"; |
| |
| status = "okay"; |
| }; |
| |
| extn:extn { |
| compatible = "amlogic, tm2-snd-extn"; |
| #sound-dai-cells = <0>; |
| |
| interrupts = |
| <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "irq_frhdmirx"; |
| |
| status = "okay"; |
| }; |
| |
| aed:effect { |
| compatible = "amlogic, snd-effect-v4"; |
| #sound-dai-cells = <0>; |
| |
| clocks = <&clkaudio CLKID_AUDIO_GATE_EQDRC |
| &clkc CLKID_FCLK_DIV5 |
| &clkaudio CLKID_AUDIO_EQDRC>; |
| clock-names = "gate", "srcpll", "eqdrc"; |
| |
| /* |
| * 0:tdmout_a |
| * 1:tdmout_b |
| * 2:tdmout_c |
| * 3:spdifout |
| * 4:spdifout_b |
| */ |
| eqdrc_module = <0>; |
| /* max 0xf, each bit for one lane, usually one lane */ |
| lane_mask = <0x1>; |
| /* max 0xff, each bit for one channel */ |
| channel_mask = <0xff>; |
| |
| status = "okay"; |
| }; |
| |
| asrca: resample@0 { |
| compatible = "amlogic, tm2-revb-resample-a"; |
| clocks = <&clkc CLKID_MPLL0 |
| &clkaudio CLKID_AUDIO_MCLK_A |
| &clkaudio CLKID_AUDIO_RESAMPLE_A>; |
| clock-names = "resample_pll", "resample_src", "resample_clk"; |
| |
| /*same with toddr_src |
| * TDMIN_A, 0 |
| * TDMIN_B, 1 |
| * TDMIN_C, 2 |
| * SPDIFIN, 3 |
| * PDMIN, 4 |
| * FRATV, 5 |
| * TDMIN_LB, 6 |
| * LOOPBACK_A, 7 |
| * FRHDMIRX, 8 |
| * LOOPBACK_B, 9 |
| * SPDIFIN_LB, 10 |
| * EARC_RX, 11 |
| */ |
| resample_module = <8>; |
| |
| status = "okay"; |
| }; |
| |
| asrcb: resample@1 { |
| compatible = "amlogic, tm2-revb-resample-b"; |
| clocks = <&clkc CLKID_MPLL3 |
| &clkaudio CLKID_AUDIO_MCLK_F |
| &clkaudio CLKID_AUDIO_RESAMPLE_B>; |
| clock-names = "resample_pll", "resample_src", "resample_clk"; |
| |
| /*this resample is only used for loopback_A.*/ |
| |
| status = "okay"; |
| }; |
| |
| vad:vad { |
| compatible = "amlogic, snd-vad"; |
| #sound-dai-cells = <0>; |
| |
| clocks = <&clkaudio CLKID_AUDIO_GATE_TOVAD |
| &clkc CLKID_FCLK_DIV5 |
| &clkaudio CLKID_AUDIO_VAD>; |
| clock-names = "gate", "pll", "clk"; |
| |
| interrupts = <GIC_SPI 155 IRQ_TYPE_EDGE_RISING |
| GIC_SPI 47 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "irq_wakeup", "irq_frame_sync"; |
| |
| /* |
| * Data src sel: |
| * 0: tdmin_a; |
| * 1: tdmin_b; |
| * 2: tdmin_c; |
| * 3: spdifin; |
| * 4: pdmin; |
| * 5: loopback_b; |
| * 6: tdmin_lb; |
| * 7: loopback_a; |
| */ |
| src = <4>; |
| |
| /* |
| * deal with hot word in user space or kernel space |
| * 0: in user space |
| * 1: in kernel space |
| */ |
| level = <1>; |
| |
| status = "okay"; |
| }; |
| |
| loopbacka:loopback@0 { |
| compatible = "amlogic, tm2-revb-loopbacka"; |
| #sound-dai-cells = <0>; |
| |
| clocks = <&clkaudio CLKID_AUDIO_GATE_PDM |
| &clkc CLKID_FCLK_DIV3 |
| &clkc CLKID_MPLL3 |
| &clkaudio CLKID_AUDIO_PDMIN0 |
| &clkaudio CLKID_AUDIO_PDMIN1 |
| &clkc CLKID_MPLL0 |
| &clkaudio CLKID_AUDIO_MCLK_A>; |
| clock-names = "pdm_gate", |
| "pdm_sysclk_srcpll", |
| "pdm_dclk_srcpll", |
| "pdm_dclk", |
| "pdm_sysclk", |
| "tdminlb_mpll", |
| "tdminlb_mclk"; |
| |
| /* datain src |
| * 0: tdmin_a; |
| * 1: tdmin_b; |
| * 2: tdmin_c; |
| * 3: spdifin; |
| * 4: pdmin; |
| */ |
| datain_src = <4>; |
| datain_chnum = <4>; |
| datain_chmask = <0xf>; |
| /* config which data pin for loopback */ |
| datain-lane-mask-in = <1 0 1 0>; |
| |
| /* calc mclk for datalb */ |
| mclk-fs = <256>; |
| |
| /* tdmin_lb src |
| * 0: tdmoutA |
| * 1: tdmoutB |
| * 2: tdmoutC |
| * 3: PAD_TDMINA_DIN*, refer to core pinmux |
| * 4: PAD_TDMINB_DIN*, refer to core pinmux |
| * 5: PAD_TDMINC_DIN*, refer to core pinmux |
| * 6: PAD_TDMINA_D*, oe, refer to core pinmux |
| * 7: PAD_TDMINB_D*, oe, refer to core pinmux |
| */ |
| /* if tdmin_lb >= 3, use external loopback */ |
| datalb_src = <0>; |
| datalb_chnum = <2>; |
| datalb_chmask = <0x3>; |
| /* config which data pin as loopback */ |
| datalb-lane-mask-in = <1 0 0 0>; |
| |
| status = "okay"; |
| }; |
| |
| loopbackb:loopback@1 { |
| compatible = "amlogic, tm2-revb-loopbackb"; |
| #sound-dai-cells = <0>; |
| |
| clocks = <&clkaudio CLKID_AUDIO_GATE_PDM |
| &clkc CLKID_FCLK_DIV3 |
| &clkc CLKID_MPLL3 |
| &clkaudio CLKID_AUDIO_PDMIN0 |
| &clkaudio CLKID_AUDIO_PDMIN1 |
| &clkc CLKID_MPLL0 |
| &clkaudio CLKID_AUDIO_MCLK_A>; |
| clock-names = "pdm_gate", |
| "pdm_sysclk_srcpll", |
| "pdm_dclk_srcpll", |
| "pdm_dclk", |
| "pdm_sysclk", |
| "tdminlb_mpll", |
| "tdminlb_mclk"; |
| |
| /* calc mclk for datain_lb */ |
| mclk-fs = <256>; |
| |
| /* datain src |
| * 0: tdmin_a; |
| * 1: tdmin_b; |
| * 2: tdmin_c; |
| * 3: spdifin; |
| * 4: pdmin; |
| */ |
| datain_src = <4>; |
| datain_chnum = <4>; |
| datain_chmask = <0xf>; |
| /* config which data pin for loopback */ |
| datain-lane-mask-in = <1 0 1 0>; |
| |
| /* tdmin_lb src |
| * 0: tdmoutA |
| * 1: tdmoutB |
| * 2: tdmoutC |
| * 3: PAD_TDMINA_DIN*, refer to core pinmux |
| * 4: PAD_TDMINB_DIN*, refer to core pinmux |
| * 5: PAD_TDMINC_DIN*, refer to core pinmux |
| * 6: PAD_TDMINA_D*, oe, refer to core pinmux |
| * 7: PAD_TDMINB_D*, oe, refer to core pinmux |
| */ |
| /* if tdmin_lb >= 3, use external loopback */ |
| datalb_src = <1>; |
| datalb_chnum = <2>; |
| datalb_chmask = <0x3>; |
| /* config which data pin as loopback */ |
| datalb-lane-mask-in = <1 0 0 0>; |
| |
| status = "disabled"; |
| }; |
| }; /* end of audiobus */ |
| |
| &earc { |
| status = "okay"; |
| }; |
| |
| &periphs_pinctrl { |
| /* audio pin mux */ |
| |
| tdma_mclk: tdma_mclk { |
| mux { /* GPIOH_4 */ |
| groups = "mclk0_h"; |
| function = "mclk0"; |
| drive-strength = <1>; |
| }; |
| }; |
| |
| tdmout_a: tdmout_a { |
| mux { /* GPIOH_5, GPIOH_6, GPIOH_7, GPIOH_8*/ |
| groups = "tdma_fs_h", |
| "tdma_sclk_h", |
| "tdma_dout0_h", |
| "tdma_dout1_h"; |
| function = "tdma_out"; |
| drive-strength = <1>; |
| bias-pull-down; |
| }; |
| }; |
| |
| tdmin_a: tdmin_a { |
| mux { /* GPIOH_11, GPIOH_12 */ |
| groups = "tdma_din0_h", |
| "tdma_din1_h"; |
| function = "tdma_in"; |
| drive-strength = <1>; |
| }; |
| }; |
| |
| tdmout_c: tdmout_c { |
| mux { /* GPIODV_7, GPIODV_8, GPIODV_9 */ |
| groups = "tdmc_sclk", |
| "tdmc_fs", |
| "tdmc_dout0"; |
| function = "tdmc_out"; |
| drive-strength = <1>; |
| }; |
| }; |
| |
| tdmin_c: tdmin_c { |
| mux { /* GPIODV_10 */ |
| groups = "tdmc_din1"; |
| function = "tdmc_in"; |
| drive-strength = <1>; |
| }; |
| }; |
| |
| spdifin_a: spdifin_a { |
| mux { /* GPIODV_5 */ |
| groups = "spdif_in"; |
| function = "spdif_in"; |
| }; |
| }; |
| |
| spdifout_a: spdifout_a { |
| mux { /* GPIODV_4 */ |
| groups = "spdif_out_dv4"; |
| function = "spdif_out"; |
| }; |
| }; |
| |
| spdifout_a_mute: spdifout_a_mute { |
| mux { /* GPIODV_4 */ |
| groups = "GPIODV_4"; |
| function = "gpio_periphs"; |
| }; |
| }; |
| |
| pdmin: pdmin { |
| mux { /* GPIOZ_7, GPIOZ_8, GPIOZ_10 */ |
| groups = "pdm_dclk_z", |
| "pdm_din0_z", |
| "pdm_din2_z10"; |
| function = "pdm"; |
| }; |
| }; |
| |
| hdmirx_a_mux:hdmirx_a_mux { |
| mux { |
| groups = "hdmirx_a_hpd", "hdmirx_a_det", |
| "hdmirx_a_sda", "hdmirx_a_sck"; |
| function = "hdmirx_a"; |
| }; |
| }; |
| |
| hdmirx_b_mux:hdmirx_b_mux { |
| mux { |
| groups = "hdmirx_b_hpd", "hdmirx_b_det", |
| "hdmirx_b_sda", "hdmirx_b_sck"; |
| function = "hdmirx_b"; |
| }; |
| }; |
| |
| hdmirx_c_mux:hdmirx_c_mux { |
| mux { |
| groups = "hdmirx_c_hpd", "hdmirx_c_det", |
| "hdmirx_c_sda", "hdmirx_c_sck"; |
| function = "hdmirx_c"; |
| }; |
| }; |
| |
| }; /* end of pinctrl_periphs */ |
| |
| &audio_data{ |
| status = "okay"; |
| }; |
| |
| &spicc0 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spicc0_pins_h>; |
| cs-gpios = <&gpio GPIOH_20 0>; |
| }; |
| |
| &i2c3 { |
| status = "okay"; |
| pinctrl-names="default"; |
| pinctrl-0=<&i2c3_h1_pins>; |
| clock-frequency = <400000>; |
| |
| ad82584f: ad82584f@30 { |
| compatible = "ESMT, ad82584f"; |
| #sound-dai-cells = <0>; |
| reg = <0x30>; |
| status = "okay"; |
| reset_pin = <&gpio GPIOH_13 0>; |
| no_mclk; |
| }; |
| |
| ad82584f1: ad82584f@31 { |
| compatible = "ESMT, ad82584f"; |
| #sound-dai-cells = <0>; |
| reg = <0x31>; |
| status = "okay"; |
| no_mclk; |
| }; |
| }; |
| |
| &spicc1 { |
| status = "disabled"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spicc1_pins_c>; |
| cs-gpios = <&gpio GPIOC_3 0>; |
| }; |
| |
| &pwm_AO_cd { |
| status = "okay"; |
| }; |
| |
| &fb { |
| status = "disabled"; |
| display_size_default = <1920 1080 1920 2160 32>; |
| mem_size = <0x00800000 0x1980000 0x100000 0x100000 0x800000>; |
| logo_addr = "0x7f800000"; |
| mem_alloc = <0>; |
| pxp_mode = <0>; /** 0:normal mode 1:pxp mode */ |
| }; |
| |
| &amhdmitx { |
| status = "okay"; |
| repeater_tx = <0x0>; |
| /* hdcp ctrl 0:sysctrl, 1: drv, 2: linux app */ |
| hdcp_ctl_lvl = <2>; |
| }; |
| |
| &pcie_A { |
| reset-gpio = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>; |
| status = "disable"; |
| }; |
| |
| &pcie_B { |
| /* ab311 only pcie a, no pcie b */ |
| status = "disable"; |
| }; |
| |
| &usb0 { |
| status = "okay"; |
| }; |
| |
| &usb2_phy_v2 { |
| status = "okay"; |
| portnum = <3>; |
| }; |
| |
| &usb3_phy_v2 { |
| status = "okay"; |
| portnum = <2>; |
| portconfig-30 = <1>; |
| portconfig-31 = <1>; |
| }; |
| |
| &usb_otg { |
| status = "okay"; |
| otg = <0>; |
| }; |
| |
| &dwc2_a { |
| status = "okay"; |
| /** 0: normal, 1: otg+dwc3 host only, 2: otg+dwc3 device only*/ |
| controller-type = <1>; |
| }; |
| |
| &saradc { |
| status = "okay"; |
| vref-supply = <&vddao_1v8>; |
| }; |
| |
| &lut_dma { |
| status = "okay"; |
| }; |
| |
| &drm_vpu { |
| status = "okay"; |
| logo_addr = "0x7f800000"; |
| }; |
| |
| &drm_amhdmitx { |
| status = "okay"; |
| hdcp = "disabled"; |
| }; |
| |
| &drm_amcvbsout { |
| status = "okay"; |
| }; |
| |
| &drm_lcd { |
| status = "disabled"; |
| }; |
| |
| &aml_bt { |
| status = "okay"; |
| reset-gpios = <&gpio GPIOC_13 GPIO_ACTIVE_HIGH>; |
| }; |
| |
| &aml_wifi{ |
| status = "okay"; |
| dhd_static_buf; |
| interrupt-gpios = <&gpio GPIOC_12 GPIO_ACTIVE_HIGH>; |
| power_on-gpios = <&gpio GPIOC_11 GPIO_ACTIVE_HIGH>; |
| }; |
| |
| &pwm_ab { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pwm_b_c_pins>; |
| status = "okay"; |
| }; |
| |
| &uart_A { |
| status = "okay"; |
| pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; |
| uart-has-rtscts; |
| }; |
