| /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ |
| /* |
| * Copyright (c) 2019 Amlogic, Inc. All rights reserved. |
| */ |
| |
| #ifndef _GE2D_REG_H_ |
| #define _GE2D_REG_H_ |
| |
| #define GE2D_MATRIX2_PRE_OFFSET 0x1890 |
| #define GE2D_MATRIX2_COEF00_01 0x1891 |
| #define GE2D_MATRIX2_COEF02_10 0x1892 |
| #define GE2D_MATRIX2_COEF11_12 0x1893 |
| #define GE2D_MATRIX2_COEF20_21 0x1894 |
| #define GE2D_MATRIX2_COEF22_CTRL 0x1895 |
| #define GE2D_MATRIX2_OFFSET 0x1896 |
| #define GE2D_MATRIX3_PRE_OFFSET 0x1897 |
| #define GE2D_MATRIX3_COEF00_01 0x1898 |
| #define GE2D_MATRIX3_COEF02_10 0x1899 |
| #define GE2D_MATRIX3_COEF11_12 0x189a |
| #define GE2D_MATRIX3_COEF20_21 0x189b |
| #define GE2D_MATRIX3_COEF22_CTRL 0x189c |
| #define GE2D_MATRIX3_OFFSET 0x189d |
| #define GE2D_GEN_CTRL0 0x18a0 |
| #define GE2D_GEN_CTRL1 0x18a1 |
| #define GE2D_GEN_CTRL2 0x18a2 |
| #define GE2D_CMD_CTRL 0x18a3 |
| #define GE2D_STATUS0 0x18a4 |
| #define GE2D_STATUS1 0x18a5 |
| #define GE2D_SRC1_DEF_COLOR 0x18a6 |
| #define GE2D_SRC1_CLIPX_START_END 0x18a7 |
| #define GE2D_SRC1_CLIPY_START_END 0x18a8 |
| #define GE2D_SRC1_CANVAS 0x18a9 |
| #define GE2D_SRC1_X_START_END 0x18aa |
| #define GE2D_SRC1_Y_START_END 0x18ab |
| #define GE2D_SRC1_LUT_ADDR 0x18ac |
| #define GE2D_SRC1_LUT_DAT 0x18ad |
| #define GE2D_SRC1_FMT_CTRL 0x18ae |
| #define GE2D_SRC2_DEF_COLOR 0x18af |
| #define GE2D_SRC2_CLIPX_START_END 0x18b0 |
| #define GE2D_SRC2_CLIPY_START_END 0x18b1 |
| #define GE2D_SRC2_X_START_END 0x18b2 |
| #define GE2D_SRC2_Y_START_END 0x18b3 |
| #define GE2D_DST_CLIPX_START_END 0x18b4 |
| #define GE2D_DST_CLIPY_START_END 0x18b5 |
| #define GE2D_DST_X_START_END 0x18b6 |
| #define GE2D_DST_Y_START_END 0x18b7 |
| #define GE2D_SRC2_DST_CANVAS 0x18b8 |
| #define GE2D_VSC_START_PHASE_STEP 0x18b9 |
| #define GE2D_VSC_PHASE_SLOPE 0x18ba |
| #define GE2D_VSC_INI_CTRL 0x18bb |
| #define GE2D_HSC_START_PHASE_STEP 0x18bc |
| #define GE2D_HSC_PHASE_SLOPE 0x18bd |
| #define GE2D_HSC_INI_CTRL 0x18be |
| #define GE2D_HSC_ADV_CTRL 0x18bf |
| #define GE2D_SC_MISC_CTRL 0x18c0 |
| #define GE2D_VSC_NRND_POINT 0x18c1 |
| #define GE2D_VSC_NRND_PHASE 0x18c2 |
| #define GE2D_HSC_NRND_POINT 0x18c3 |
| #define GE2D_HSC_NRND_PHASE 0x18c4 |
| #define GE2D_MATRIX_PRE_OFFSET 0x18c5 |
| #define GE2D_MATRIX_COEF00_01 0x18c6 |
| #define GE2D_MATRIX_COEF02_10 0x18c7 |
| #define GE2D_MATRIX_COEF11_12 0x18c8 |
| #define GE2D_MATRIX_COEF20_21 0x18c9 |
| #define GE2D_MATRIX_COEF22_CTRL 0x18ca |
| #define GE2D_MATRIX_OFFSET 0x18cb |
| #define GE2D_ALU_OP_CTRL 0x18cc |
| #define GE2D_ALU_CONST_COLOR 0x18cd |
| #define GE2D_SRC1_KEY 0x18ce |
| #define GE2D_SRC1_KEY_MASK 0x18cf |
| #define GE2D_SRC2_KEY 0x18d0 |
| #define GE2D_SRC2_KEY_MASK 0x18d1 |
| #define GE2D_DST_BITMASK 0x18d2 |
| #define GE2D_DP_ONOFF_CTRL 0x18d3 |
| #define GE2D_SCALE_COEF_IDX 0x18d4 |
| #define GE2D_SCALE_COEF 0x18d5 |
| #define GE2D_SRC_OUTSIDE_ALPHA 0x18d6 |
| #define GE2D_ANTIFLICK_CTRL0 0x18d8 |
| #define GE2D_ANTIFLICK_CTRL1 0x18d9 |
| #define GE2D_ANTIFLICK_COLOR_FILT0 0x18da |
| #define GE2D_ANTIFLICK_COLOR_FILT1 0x18db |
| #define GE2D_ANTIFLICK_COLOR_FILT2 0x18dc |
| #define GE2D_ANTIFLICK_COLOR_FILT3 0x18dd |
| #define GE2D_ANTIFLICK_ALPHA_FILT0 0x18de |
| #define GE2D_ANTIFLICK_ALPHA_FILT1 0x18df |
| #define GE2D_ANTIFLICK_ALPHA_FILT2 0x18e0 |
| #define GE2D_ANTIFLICK_ALPHA_FILT3 0x18e1 |
| #define GE2D_SRC1_RANGE_MAP_Y_CTRL 0x18e3 |
| #define GE2D_SRC1_RANGE_MAP_CB_CTRL 0x18e4 |
| #define GE2D_SRC1_RANGE_MAP_CR_CTRL 0x18e5 |
| #define GE2D_ARB_BURST_NUM 0x18e6 |
| #define GE2D_TID_TOKEN 0x18e7 |
| #define GE2D_GEN_CTRL3 0x18e8 |
| #define GE2D_STATUS2 0x18e9 |
| #define GE2D_GEN_CTRL4 0x18ea |
| #define GE2D_DST1_BADDR_CTRL 0x18f1 |
| #define GE2D_DST1_STRIDE_CTRL 0x18f2 |
| #define GE2D_SRC1_BADDR_CTRL 0x18f3 |
| #define GE2D_SRC1_STRIDE_CTRL 0x18f4 |
| #define GE2D_SRC2_BADDR_CTRL 0x18f5 |
| #define GE2D_SRC2_STRIDE_CTRL 0x18f6 |
| #define GE2D_GEN_CTRL5 0x18f1 |
| |
| #define GE2D_C1_DST1_BADDR_CTRL 0x18f2 |
| #define GE2D_C1_DST1_STRIDE_CTRL 0x18f3 |
| #define GE2D_C1_DST2_BADDR_CTRL 0x18f4 |
| #define GE2D_C1_DST2_STRIDE_CTRL 0x18f5 |
| #define GE2D_C1_SRC1_BADDR_CTRL_Y 0x18f6 |
| #define GE2D_C1_SRC1_STRIDE_CTRL_Y 0x18f7 |
| #define GE2D_C1_SRC1_BADDR_CTRL_CB 0x18f8 |
| #define GE2D_C1_SRC1_STRIDE_CTRL_CB 0x18f9 |
| #define GE2D_C1_SRC1_BADDR_CTRL_CR 0x18fa |
| #define GE2D_C1_SRC1_STRIDE_CTRL_CR 0x18fb |
| #define GE2D_C1_SRC2_BADDR_CTRL 0x18fc |
| #define GE2D_C1_SRC2_STRIDE_CTRL 0x18fd |
| |
| #define VIU_OSD1_BLK0_CFG_W0 0x1a1b |
| |
| enum meson_chip_e { |
| MESON_CPU_MAJOR_ID_M8B = 0x1B, |
| MESON_CPU_MAJOR_ID_GXBB = 0x1F, |
| MESON_CPU_MAJOR_ID_GXTVBB = 0x20, |
| MESON_CPU_MAJOR_ID_GXL = 0x21, |
| MESON_CPU_MAJOR_ID_GXM = 0x22, |
| MESON_CPU_MAJOR_ID_TXL = 0x23, |
| MESON_CPU_MAJOR_ID_TXLX = 0x24, |
| MESON_CPU_MAJOR_ID_AXG = 0x25, |
| MESON_CPU_MAJOR_ID_GXLX = 0x26, |
| MESON_CPU_MAJOR_ID_TXHD = 0x27, |
| MESON_CPU_MAJOR_ID_G12A = 0x28, |
| MESON_CPU_MAJOR_ID_G12B = 0x29, |
| MESON_CPU_MAJOR_ID_GXLX2 = 0x2a, |
| MESON_CPU_MAJOR_ID_SM1 = 0x2B, |
| MESON_CPU_MAJOR_ID_TL1 = 0x2E, |
| MESON_CPU_MAJOR_ID_TM2, |
| MESON_CPU_MAJOR_ID_C1, |
| MESON_CPU_MAJOR_ID_C2, |
| MESON_CPU_MAJOR_ID_SC2, |
| MESON_CPU_MAJOR_ID_T5, |
| MESON_CPU_MAJOR_ID_T7, |
| MESON_CPU_MAJOR_ID_T3, |
| MESON_CPU_MAJOR_ID_S4, |
| MESON_CPU_MAJOR_ID_P1, |
| MESON_CPU_MAJOR_ID_T5W, |
| }; |
| #endif |
