| /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ |
| /* |
| * Copyright (c) 2019 Amlogic, Inc. All rights reserved. |
| */ |
| |
| #ifndef __ADDR_DTMB_SYNC_H__ |
| #define __ADDR_DTMB_SYNC_H__ |
| |
| #define DTMB_SYNC_TS_CFO_PN_VALUE (0x57) |
| #define DTMB_SYNC_TS_CFO_ERR_LIMIT (0x58) |
| #define DTMB_SYNC_TS_CFO_PN_MODIFY (0x59) |
| #define DTMB_SYNC_TS_GAIN (0x5a) |
| #define DTMB_SYNC_FE_CONFIG (0x5b) |
| #define DTMB_SYNC_PNPHASE_OFFSET (0x5c) |
| #define DTMB_SYNC_PNPHASE_CONFIG (0x5d) |
| #define DTMB_SYNC_SFO_SFO_PN0_MODIFY (0x5e) |
| #define DTMB_SYNC_SFO_SFO_PN1_MODIFY (0x5f) |
| #define DTMB_SYNC_SFO_SFO_PN2_MODIFY (0x60) |
| #define DTMB_SYNC_SFO_CONFIG (0x61) |
| #define DTMB_SYNC_FEC_CFG (0x67) |
| #define DTMB_SYNC_FEC_DEBUG_CFG (0x68) |
| #define DTMB_SYNC_DATA_DDR_ADR (0x69) |
| #define DTMB_SYNC_DEBUG_DDR_ADR (0x6a) |
| #define DTMB_SYNC_FEC_SIM_CFG1 (0x6b) |
| #define DTMB_SYNC_FEC_SIM_CFG2 (0x6c) |
| #define DTMB_SYNC_TRACK_CFO_MAX (0x6d) |
| #define DTMB_SYNC_CCI_DAGC_CONFIG1 (0x6e) |
| #define DTMB_SYNC_CCI_DAGC_CONFIG2 (0x6f) |
| #define DTMB_SYNC_CCI_RP (0x70) |
| #define DTMB_SYNC_CCI_DET_THRES (0x71) |
| #define DTMB_SYNC_CCI_NOTCH1_CONFIG1 (0x72) |
| #define DTMB_SYNC_CCI_NOTCH1_CONFIG2 (0x73) |
| #define DTMB_SYNC_CCI_NOTCH2_CONFIG1 (0x74) |
| #define DTMB_SYNC_CCI_NOTCH2_CONFIG2 (0x75) |
| |
| #endif |
