| /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ |
| /* |
| * drivers/amlogic/media/enhancement/amvecm/arch/vpp_dolbyvision_regs.h |
| * |
| * Copyright (C) 2017 Amlogic, Inc. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; either version 2 of the License, or |
| * (at your option) any later version. |
| * |
| * This program is distributed in the hope that it will be useful, but WITHOUT |
| * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| * more details. |
| * |
| */ |
| |
| #ifndef VPP_DOLBYVISION_REGS_H |
| #define VPP_DOLBYVISION_REGS_H |
| |
| #define CORE1A_OFFSET (0x1UL << 24) /*core1a*/ |
| #define CORE1B_OFFSET (0x1UL << 25) /*core1b*/ |
| #define CORE2A_OFFSET (0x1UL << 26) |
| #define CORE3_OFFSET (0x1UL << 27) |
| #define CORETV_OFFSET (0x1UL << 28) |
| #define CORE1C_OFFSET (0x1UL << 29) /*core1c*/ |
| #define CORE2C_OFFSET (0x1UL << 30) |
| |
| |
| #define DOLBY_CORE1A_REG_START (0x00 + CORE1A_OFFSET) |
| #define DOLBY_CORE1A_CLKGATE_CTRL (0xf2 + CORE1A_OFFSET) |
| #define DOLBY_CORE1A_SWAP_CTRL0 (0xf3 + CORE1A_OFFSET) |
| #define DOLBY_CORE1A_SWAP_CTRL1 (0xf4 + CORE1A_OFFSET) |
| #define DOLBY_CORE1A_SWAP_CTRL2 (0xf5 + CORE1A_OFFSET) |
| #define DOLBY_CORE1A_SWAP_CTRL3 (0xf6 + CORE1A_OFFSET) |
| #define DOLBY_CORE1A_SWAP_CTRL4 (0xf7 + CORE1A_OFFSET) |
| #define DOLBY_CORE1A_SWAP_CTRL5 (0xf8 + CORE1A_OFFSET) |
| #define DOLBY_CORE1A_DMA_CTRL (0xf9 + CORE1A_OFFSET) |
| #define DOLBY_CORE1A_DMA_STATUS (0xfa + CORE1A_OFFSET) |
| #define DOLBY_CORE1A_STATUS0 (0xfb + CORE1A_OFFSET) |
| #define DOLBY_CORE1A_STATUS1 (0xfc + CORE1A_OFFSET) |
| #define DOLBY_CORE1A_STATUS2 (0xfd + CORE1A_OFFSET) |
| #define DOLBY_CORE1A_STATUS3 (0xfe + CORE1A_OFFSET) |
| #define DOLBY_CORE1A_DMA_PORT (0xff + CORE1A_OFFSET) |
| |
| #define DOLBY_CORE1B_REG_START (0x00 + CORE1B_OFFSET) |
| #define DOLBY_CORE1B_CLKGATE_CTRL (0xf2 + CORE1B_OFFSET) |
| #define DOLBY_CORE1B_SWAP_CTRL0 (0xf3 + CORE1B_OFFSET) |
| #define DOLBY_CORE1B_SWAP_CTRL1 (0xf4 + CORE1B_OFFSET) |
| #define DOLBY_CORE1B_SWAP_CTRL2 (0xf5 + CORE1B_OFFSET) |
| #define DOLBY_CORE1B_SWAP_CTRL3 (0xf6 + CORE1B_OFFSET) |
| #define DOLBY_CORE1B_SWAP_CTRL4 (0xf7 + CORE1B_OFFSET) |
| #define DOLBY_CORE1B_SWAP_CTRL5 (0xf8 + CORE1B_OFFSET) |
| #define DOLBY_CORE1B_DMA_CTRL (0xf9 + CORE1B_OFFSET) |
| #define DOLBY_CORE1B_DMA_STATUS (0xfa + CORE1B_OFFSET) |
| #define DOLBY_CORE1B_STATUS0 (0xfb + CORE1B_OFFSET) |
| #define DOLBY_CORE1B_STATUS1 (0xfc + CORE1B_OFFSET) |
| #define DOLBY_CORE1B_STATUS2 (0xfd + CORE1B_OFFSET) |
| #define DOLBY_CORE1B_STATUS3 (0xfe + CORE1B_OFFSET) |
| #define DOLBY_CORE1B_DMA_PORT (0xff + CORE1B_OFFSET) |
| |
| #define DOLBY_CORE1C_REG_START (0x00 + CORE1C_OFFSET) |
| #define DOLBY_CORE1C_CLKGATE_CTRL (0xf2 + CORE1C_OFFSET) |
| #define DOLBY_CORE1C_SWAP_CTRL0 (0xf3 + CORE1C_OFFSET) |
| #define DOLBY_CORE1C_SWAP_CTRL1 (0xf4 + CORE1C_OFFSET) |
| #define DOLBY_CORE1C_SWAP_CTRL2 (0xf5 + CORE1C_OFFSET) |
| #define DOLBY_CORE1C_SWAP_CTRL3 (0xf6 + CORE1C_OFFSET) |
| #define DOLBY_CORE1C_SWAP_CTRL4 (0xf7 + CORE1C_OFFSET) |
| #define DOLBY_CORE1C_SWAP_CTRL5 (0xf8 + CORE1C_OFFSET) |
| #define DOLBY_CORE1C_DMA_CTRL (0xf9 + CORE1C_OFFSET) |
| #define DOLBY_CORE1C_DMA_STATUS (0xfa + CORE1C_OFFSET) |
| #define DOLBY_CORE1C_STATUS0 (0xfb + CORE1C_OFFSET) |
| #define DOLBY_CORE1C_STATUS1 (0xfc + CORE1C_OFFSET) |
| #define DOLBY_CORE1C_STATUS2 (0xfd + CORE1C_OFFSET) |
| #define DOLBY_CORE1C_STATUS3 (0xfe + CORE1C_OFFSET) |
| #define DOLBY_CORE1C_DMA_PORT (0xff + CORE1C_OFFSET) |
| |
| #define DOLBY_CORE2A_REG_START (0x00 + CORE2A_OFFSET) |
| #define DOLBY_CORE2A_CTRL (0x01 + CORE2A_OFFSET) |
| #define DOLBY_CORE2A_CLKGATE_CTRL (0x32 + CORE2A_OFFSET) |
| #define DOLBY_CORE2A_SWAP_CTRL0 (0x33 + CORE2A_OFFSET) |
| #define DOLBY_CORE2A_SWAP_CTRL1 (0x34 + CORE2A_OFFSET) |
| #define DOLBY_CORE2A_SWAP_CTRL2 (0x35 + CORE2A_OFFSET) |
| #define DOLBY_CORE2A_SWAP_CTRL3 (0x36 + CORE2A_OFFSET) |
| #define DOLBY_CORE2A_SWAP_CTRL4 (0x37 + CORE2A_OFFSET) |
| #define DOLBY_CORE2A_SWAP_CTRL5 (0x38 + CORE2A_OFFSET) |
| #define DOLBY_CORE2A_DMA_CTRL (0x39 + CORE2A_OFFSET) |
| #define DOLBY_CORE2A_DMA_STATUS (0x3a + CORE2A_OFFSET) |
| #define DOLBY_CORE2A_STATUS0 (0x3b + CORE2A_OFFSET) |
| #define DOLBY_CORE2A_STATUS1 (0x3c + CORE2A_OFFSET) |
| #define DOLBY_CORE2A_STATUS2 (0x3d + CORE2A_OFFSET) |
| #define DOLBY_CORE2A_STATUS3 (0x3e + CORE2A_OFFSET) |
| #define DOLBY_CORE2A_DMA_PORT (0x3f + CORE2A_OFFSET) |
| |
| #define DOLBY_CORE2C_REG_START (0x00 + CORE2C_OFFSET) |
| #define DOLBY_CORE2C_CTRL (0x01 + CORE2C_OFFSET) |
| #define DOLBY_CORE2C_CLKGATE_CTRL (0x32 + CORE2C_OFFSET) |
| #define DOLBY_CORE2C_SWAP_CTRL0 (0x33 + CORE2C_OFFSET) |
| #define DOLBY_CORE2C_SWAP_CTRL1 (0x34 + CORE2C_OFFSET) |
| #define DOLBY_CORE2C_SWAP_CTRL2 (0x35 + CORE2C_OFFSET) |
| #define DOLBY_CORE2C_SWAP_CTRL3 (0x36 + CORE2C_OFFSET) |
| #define DOLBY_CORE2C_SWAP_CTRL4 (0x37 + CORE2C_OFFSET) |
| #define DOLBY_CORE2C_SWAP_CTRL5 (0x38 + CORE2C_OFFSET) |
| #define DOLBY_CORE2C_DMA_CTRL (0x39 + CORE2C_OFFSET) |
| #define DOLBY_CORE2C_DMA_STATUS (0x3a + CORE2C_OFFSET) |
| #define DOLBY_CORE2C_STATUS0 (0x3b + CORE2C_OFFSET) |
| #define DOLBY_CORE2C_STATUS1 (0x3c + CORE2C_OFFSET) |
| #define DOLBY_CORE2C_STATUS2 (0x3d + CORE2C_OFFSET) |
| #define DOLBY_CORE2C_STATUS3 (0x3e + CORE2C_OFFSET) |
| #define DOLBY_CORE2C_DMA_PORT (0x3f + CORE2C_OFFSET) |
| |
| #define DOLBY_CORE3_REG_START (0x00 + CORE3_OFFSET) |
| #define DOLBY_CORE3_CLKGATE_CTRL (0xf0 + CORE3_OFFSET) |
| #define DOLBY_CORE3_SWAP_CTRL0 (0xf1 + CORE3_OFFSET) |
| #define DOLBY_CORE3_SWAP_CTRL1 (0xf2 + CORE3_OFFSET) |
| #define DOLBY_CORE3_SWAP_CTRL2 (0xf3 + CORE3_OFFSET) |
| #define DOLBY_CORE3_SWAP_CTRL3 (0xf4 + CORE3_OFFSET) |
| #define DOLBY_CORE3_SWAP_CTRL4 (0xf5 + CORE3_OFFSET) |
| #define DOLBY_CORE3_SWAP_CTRL5 (0xf6 + CORE3_OFFSET) |
| #define DOLBY_CORE3_SWAP_CTRL6 (0xf7 + CORE3_OFFSET) |
| #define DOLBY_CORE3_DIAG_CTRL (0xf8 + CORE3_OFFSET) |
| #define DOLBY_CORE3_CRC_CTRL (0xfb + CORE3_OFFSET) |
| #define DOLBY_CORE3_INPUT_CSC_CRC (0xfc + CORE3_OFFSET) |
| #define DOLBY_CORE3_OUTPUT_CSC_CRC (0xfd + CORE3_OFFSET) |
| |
| #define DOLBY_TV_REG_START (0x00 + CORETV_OFFSET) |
| #define DOLBY_TV_CLKGATE_CTRL (0xf1 + CORETV_OFFSET) |
| #define DOLBY_TV_SWAP_CTRL0 (0xf2 + CORETV_OFFSET) |
| #define DOLBY_TV_SWAP_CTRL1 (0xf3 + CORETV_OFFSET) |
| #define DOLBY_TV_SWAP_CTRL2 (0xf4 + CORETV_OFFSET) |
| #define DOLBY_TV_SWAP_CTRL3 (0xf5 + CORETV_OFFSET) |
| #define DOLBY_TV_SWAP_CTRL4 (0xf6 + CORETV_OFFSET) |
| #define DOLBY_TV_SWAP_CTRL5 (0xf7 + CORETV_OFFSET) |
| #define DOLBY_TV_SWAP_CTRL6 (0xf8 + CORETV_OFFSET) |
| #define DOLBY_TV_SWAP_CTRL7 (0xf9 + CORETV_OFFSET) |
| #define DOLBY_TV_AXI2DMA_CTRL0 (0xfa + CORETV_OFFSET) |
| #define DOLBY_TV_AXI2DMA_CTRL1 (0xfb + CORETV_OFFSET) |
| #define DOLBY_TV_AXI2DMA_CTRL2 (0xfc + CORETV_OFFSET) |
| #define DOLBY_TV_AXI2DMA_CTRL3 (0xfd + CORETV_OFFSET) |
| #define DOLBY_TV_STATUS0 (0xfe + CORETV_OFFSET) |
| #define DOLBY_TV_STATUS1 (0xff + CORETV_OFFSET) |
| #define DOLBY_TV_DIAG_CTRL (0xe7 + CORETV_OFFSET) |
| #define DOLBY_TV_CRC_CTRL (0xea + CORETV_OFFSET) |
| #define DOLBY_TV_OUTPUT_DM_CRC (0xef + CORETV_OFFSET) |
| |
| #define VPP_WRAP_OSD1_MATRIX_EN_CTRL 0x3d6d |
| #define VPP_WRAP_OSD2_MATRIX_EN_CTRL 0x3d7d |
| #define VPP_WRAP_OSD3_MATRIX_EN_CTRL 0x3dbd |
| #define DOLBY_PATH_CTRL 0x1a0c |
| #define VIU_MISC_CTRL1 0x1a07 |
| #define VPP_DOLBY_CTRL 0x1d93 |
| #define VIU_SW_RESET 0x1a01 |
| #define VIU_SW_RESET0 0x1a02 |
| |
| #define VPU_HDMI_FMT_CTRL 0x2743 |
| #define VPU_422T0444_CTRL0 0x274b |
| #define VPU_422T0444_CTRL1 0x274c |
| #define VPU_422T0444_CTRL2 0x274d |
| #define VPU_422T0444_RST 0x274a |
| #define VPP_TOP_VTRL 0x2749 |
| |
| #endif |
