| /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ |
| /* |
| * Copyright (c) 2019 Amlogic, Inc. All rights reserved. |
| */ |
| |
| #ifndef DT_BINDINGS_MEMORY_MESON_P1_SID_MAP |
| #define DT_BINDINGS_MEMORY_MESON_P1_SID_MAP |
| |
| #define P1_SID_RESERVED 0 |
| |
| #define P1_SID_NNA_A 8 |
| #define P1_SID_NNA_B 9 |
| #define P1_SID_NNA_C 10 |
| #define P1_SID_NNA_D 11 |
| #define P1_SID_NNA_E 12 |
| #define P1_SID_NNA_F 13 |
| |
| #define P1_SID_ISP_A 16 |
| #define P1_SID_ISP_B 17 |
| #define P1_SID_ISP_C 18 |
| #define P1_SID_ISP_D 19 |
| #define P1_SID_ISP_E 20 |
| |
| #define P1_SID_MOP_A 32 |
| #define P1_SID_MOP_B 33 |
| |
| #define P1_SID_DEP_A 34 |
| #define P1_SID_DEP_B 35 |
| |
| #define P1_SID_VFE 40 |
| |
| #define P1_SID_GE2D 41 |
| |
| #define P1_SID_DEWARP_A 42 |
| #define P1_SID_DEWARP_B 43 |
| #define P1_SID_DEWARP_C 44 |
| |
| #define P1_SID_USB3_A 48 |
| #define P1_SID_USB3_B 49 |
| #define P1_SID_USB3_C 50 |
| |
| #define P1_SID_PCIE 51 |
| |
| #define P1_SID_M4 67 |
| |
| #define P1_SID_DSP_A 68 |
| #define P1_SID_DSP_B 69 |
| |
| #define P1_SID_AOCPU 70 |
| |
| #define P1_SID_JTAG 71 |
| |
| #define P1_SID_DEV0_P0_SPICC0 72 |
| #define P1_SID_DEV0_P1_SPICC1 73 |
| #define P1_SID_DEV0_P2_RESERVED 74 |
| #define P1_SID_DEV0_P3_SDEMMCA 75 |
| #define P1_SID_DEV0_P4_RESERVED 76 |
| #define P1_SID_DEV0_P5_SPICC2 77 |
| #define P1_SID_DEV0_P6_RESERVED 78 |
| #define P1_SID_DEV0_P7_RESERVED 79 |
| |
| #define P1_SID_DEV1_P0_RESERVED 80 |
| #define P1_SID_DEV1_P1_RESERVED 81 |
| #define P1_SID_DEV1_P2_ETH 82 |
| #define P1_SID_DEV1_P3_AIFIFO 83 |
| #define P1_SID_DEV1_P4_AUDMA 84 |
| #define P1_SID_DEV1_P5_SPICC3 85 |
| #define P1_SID_DEV1_P6_SPICC4 86 |
| #define P1_SID_DEV1_P7_SPICC5 87 |
| |
| #define P1_SID_DEV2_P0_AUDIO 88 |
| #define P1_SID_DEV2_P1_RESERVED 89 |
| #define P1_SID_DEV2_P2_RESERVED 90 |
| #define P1_SID_DEV2_P3_RESERVED 91 |
| #define P1_SID_DEV2_P4_RESERVED 92 |
| #define P1_SID_DEV2_P5_RESERVED 93 |
| #define P1_SID_DEV2_P6_RESERVED 94 |
| #define P1_SID_DEV2_P7_RESERVED 95 |
| |
| #define P1_SID_EMMC 96 |
| #define P1_SID_DMA 97 |
| #endif |
| |