| /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ |
| /* |
| * Copyright (c) 2019 Amlogic, Inc. All rights reserved. |
| */ |
| |
| #ifndef _DT_BINDINGS_AMLOGIC_MESON_P1_RESET_H |
| #define _DT_BINDINGS_AMLOGIC_MESON_P1_RESET_H |
| |
| /* RESET0 */ |
| #define RESET_U3X2_M31_UTMI 0 |
| #define RESET_U3X1_M31_UTMI 1 |
| #define RESET_U3X0_M31_UTMI 2 |
| #define RESET_U3DRDX2 3 |
| #define RESET_USB 4 |
| #define RESET_U3DRDX1 5 |
| #define RESET_U3DRDX0 6 |
| #define RESET_U3DRD_PIPE0 7 |
| #define RESET_U3X2_PCIE_PHY 8 |
| #define RESET_U3X1_PCIE_PHY 9 |
| #define RESET_U3X0_PCIE_PHY 10 |
| #define RESET_APB_DECODE_DMC 11 |
| #define RESET_BRG_FDLE_APB_DEC 12 |
| #define RESET_DEWARPA 13 |
| #define RESET_DEWARPB 14 |
| #define RESET_DEWARPC 15 |
| #define RESET_BRG_SYS_APB_DEC 16 |
| #define RESET_BRG_VCBUS_DEC 17 |
| /* 18-19 */ |
| #define RESET_SMMU 20 |
| #define RESET_GE2D 21 |
| #define RESET_SMMU_APB 22 |
| /* 23 */ |
| #define RESET_VFE 24 |
| #define RESET_MOPB 25 |
| #define RESET_MOPA 26 |
| #define RESET_DEPB 27 |
| #define RESET_DEPA 28 |
| /* 29-31 */ |
| |
| /* RESET1 */ |
| #define RESET_AUDIO 32 |
| /* 33-34 */ |
| #define RESET_DDR_APB 35 |
| #define RESET_DDR 36 |
| #define RESET_U3X2_PCIE_APB 37 |
| #define RESET_U3X1_PCIE_APB 38 |
| #define RESET_U3X0_PCIE_APB 39 |
| #define RESET_DEBUG_B 40 |
| #define RESET_DEBUG_A 41 |
| #define RESET_DSP_B 42 |
| #define RESET_DSP_A 43 |
| #define RESET_PCIE_A 44 |
| #define RESET_PCIE_PHY 45 |
| #define RESET_PCIE_APB 46 |
| #define RESET_ANAKIN 47 |
| #define RESET_ETH 48 |
| #define RESET_GLOBAL_TIMER 49 |
| #define RESET_PCIE_GEN3_L0 50 |
| /* 51-52 */ |
| #define RESET_M31PHY_PCIE_WRAPPER 53 |
| /* 54-55 */ |
| #define RESET_DDR_1 56 |
| #define RESET_DDR_2 57 |
| #define RESET_DDR_3 58 |
| /* 59-63 */ |
| |
| /* RESET2 */ |
| /* 64 */ |
| #define RESET_TS_A55 65 |
| #define RESET_TS_A76 66 |
| #define RESET_TS_DDR_0 67 |
| #define RESET_SPICC_2 68 |
| #define RESET_SPICC_3 69 |
| #define RESET_SPICC_4 70 |
| #define RESET_SPICC_5 71 |
| /* 72 */ |
| #define RESET_SPICC_0 73 |
| #define RESET_SPICC_1 74 |
| #define RESET_RSA 75 |
| #define RESET_TS_DDR_1 76 |
| /* 77-79 */ |
| #define RESET_MSR_CLK 80 |
| #define RESET_SPIFC 81 |
| #define RESET_SAR_ADC 82 |
| /* 83-89 */ |
| #define RESET_AFIFO 90 |
| #define RESET_WATCHDOG 91 |
| /* 92-95 */ |
| |
| /* RESET3 */ |
| #define RESET_I2C_S_B 96 |
| #define RESET_I2C_S_C 97 |
| #define RESET_I2C_S_D 98 |
| #define RESET_I2C_S_E 99 |
| #define RESET_I2C_S_F 100 |
| #define RESET_I2C_S_G 101 |
| #define RESET_I2C_S_H 102 |
| #define RESET_I2C_S_I 103 |
| #define RESET_I2C_S_J 104 |
| #define RESET_I2C_S_K 105 |
| /* 106-115 */ |
| #define RESET_ISP_TOP 116 |
| #define RESET_ISP0 117 |
| #define RESET_ISP1 118 |
| #define RESET_ISP2 119 |
| #define RESET_ISP3 120 |
| #define RESET_ISP4 121 |
| /* 122-126 */ |
| #define RESET_A55_ACE 127 |
| |
| /* RESET4 */ |
| #define RESET_PWM_AB 128 |
| #define RESET_PWM_CD 129 |
| #define RESET_PWM_EF 130 |
| #define RESET_PWM_GH 131 |
| #define RESET_PWM_IJ 132 |
| /* 133-137 */ |
| #define RESET_UART_A 138 |
| #define RESET_UART_B 139 |
| #define RESET_UART_C 140 |
| #define RESET_UART_D 141 |
| #define RESET_UART_E 142 |
| #define RESET_UART_F 143 |
| #define RESET_I2C_S_A 144 |
| #define RESET_I2C_M_A 145 |
| #define RESET_I2C_M_B 146 |
| #define RESET_I2C_M_C 147 |
| #define RESET_I2C_M_D 148 |
| #define RESET_I2C_M_E 149 |
| #define RESET_I2C_M_F 150 |
| #define RESET_I2C_M_G 151 |
| #define RESET_I2C_M_H 152 |
| #define RESET_SD_EMMC_A 153 |
| #define RESET_SD_EMMC_C 154 |
| #define RESET_I2C_M_I 155 |
| #define RESET_I2C_M_J 156 |
| #define RESET_TS_NNA 157 |
| #define RESET_I2C_M_K 158 |
| /* 159 */ |
| |
| /* RESET5 */ |
| #define RESET_BRG_NOC_DDR_DMC3 160 |
| #define RESET_BRG_NOC_DDR_DMC2 161 |
| #define RESET_BRG_NOC_DDR_DMC1 162 |
| #define RESET_BRG_NOC_DDR_DMC0 163 |
| #define RESET_BRG_NOC_DDR_CPU 164 |
| #define RESET_BRG_NOC_DDR_MAIN 165 |
| #define RESET_BRG_NOC_DDR_ALL 166 |
| /* 167-181 */ |
| #define RESET_BRG_NICSYS_PCIE 182 |
| #define RESET_BRG_NICSYS_EMMC 183 |
| #define RESET_BRG_NICSYS_SYSCPU 184 |
| #define RESET_BRG_NICSYS_SYS 185 |
| #define RESET_BRG_NICSYS_M4 186 |
| #define RESET_BRG_NICSYS_DSPB 187 |
| #define RESET_BRG_NICSYS_DSPA 188 |
| #define RESET_BRG_NICSYS_VAPB 189 |
| #define RESET_BRG_NICSYS_MAIL 190 |
| #define RESET_BRG_NICSYS_ALL 191 |
| |
| /* RESET6 */ |
| #define RESET_AHB_PIPE_NICNNA1 192 |
| #define RESET_AHB_PIPE_NICNNA0 193 |
| #define RESET_AHB_PIPE_NICISP 194 |
| #define RESET_AHB_PIPE_NICVFE 195 |
| #define RESET_AHB_PIPE_NICFDLE 196 |
| #define RESET_AHB_PIPE_NICSYS 197 |
| /* 198-199 */ |
| #define RESET_AXI_PIPE_NNA1TOMMU 200 |
| #define RESET_AXI_PIPE_NNA0TOMMU 201 |
| #define RESET_AXI_PIPE_NNA1TOSYS 202 |
| #define RESET_AXI_PIPE_NNA0TOSYS 203 |
| #define RESET_AXI_PIPE_NICISP 204 |
| #define RESET_AXI_PIPE_NICFDLE 205 |
| #define RESET_AXI_PIPE_NICVFE 206 |
| #define RESET_AXI_PIPE_NICEMMCC 207 |
| #define RESET_APB_PIPE_NNA 208 |
| #define RESET_APB_PIPE_FDLETOP 209 |
| #define RESET_APB_PIPE_NOCDMC 210 |
| #define RESET_APB_PIPE_DDR0 211 |
| #define RESET_APB_PIPE_DDR1 212 |
| #define RESET_APB_PIPE_GE2D 213 |
| /* 214-217 */ |
| #define RESET_BRG_AMPIPE_NAND 218 |
| #define RESET_BRG_AMPIPE_ETH 219 |
| /* 220 */ |
| #define RESET_BRG_AM2AXI0 221 |
| #define RESET_BRG_AM2AXI1 222 |
| #define RESET_BRG_AM2AXI2 223 |
| |
| /* RESET7 */ |
| /* 224-234 */ |
| #define RESET_BRG_NICVFE_SYS 235 |
| #define RESET_BRG_NICVFE_VFE1 236 |
| #define RESET_BRG_NICVFE_VFE0 237 |
| #define RESET_BRG_NICVFE_GE2D 238 |
| #define RESET_BRG_NICVFE_DEWARPC 239 |
| #define RESET_BRG_NICVFE_DEWARPB 240 |
| #define RESET_BRG_NICVFE_DEWARPA 241 |
| #define RESET_BRG_NICVFE_MAIN 242 |
| #define RESET_BRG_NICVFE_ALL 243 |
| /* 244 */ |
| #define RESET_BRG_NICFDLE_SYS 245 |
| #define RESET_BRG_NICFDLE_MOPB 246 |
| #define RESET_BRG_NICFDLE_MOPA 247 |
| #define RESET_BRG_NICFDLE_DEPB 248 |
| #define RESET_BRG_NICFDLE_DEPA 249 |
| #define RESET_BRG_NICFDLE_MAIL 250 |
| #define RESET_BRG_NICFDLE_ALL 251 |
| /* 252 */ |
| #define RESET_BRG_NICISP_SYS 253 |
| #define RESET_BRG_NICISP_MAIN 254 |
| #define RESET_BRG_NICISP_ALL 255 |
| |
| #endif |
