| /* |
| * Amlogic GXBB Platform gpu |
| * |
| * Copyright (c) 2015-2015 Amlogic Ltd |
| * |
| * This file is licensed under a dual GPLv2 or BSD license. |
| * |
| */ |
| |
| / { |
| gpu:mali@d00c0000{ |
| #cooling-cells = <2>; /* min followed by max */ |
| compatible = "arm,mali-450"; |
| interrupt-parent = <&gic>; |
| reg = <0xd00c0000 0x40000>, /*mali APB bus base address*/ |
| <0xc1104440 0x01000>, /*reset register*/ |
| <0xc8100000 0x01000>, /*aobus for gpu pmu domain*/ |
| <0xc883c000 0x01000>, /*hiubus for gpu clk cntl*/ |
| <0xc1104440 0x01000>; |
| interrupts = <0 160 4>, <0 161 4>, <0 162 4>, <0 163 4>, |
| <0 164 4>, <0 165 4>, <0 166 4>, <0 167 4>, |
| <0 168 4>, <0 169 4>; |
| interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP", "IRQPMU", |
| "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1", |
| "IRQPP2", "IRQPPMMU2"; |
| pmu_domain_config = <0x1 0x2 0x4 0x4 0x0 0x0 |
| 0x0 0x0 0x0 0x1 0x2 0x0>; |
| pmu_switch_delay = <0xffff> ; |
| num_of_pp = <3> ; |
| def_clk = <4> ; |
| sc_mpp = <3>;/* number of pp used most of time.*/ |
| tbl = <&clk125_cfg |
| &clk285_cfg |
| &clk400_cfg |
| &clk500_cfg |
| &clk666_cfg |
| &clk800_cfg>; |
| |
| clocks = <&clkc CLKID_GPU_MUX &clkc CLKID_GP0_PLL>; |
| clock-names = "gpu_mux","gp0_pll"; |
| |
| /*control_interval x keep_count == 900 - 1000ms */ |
| control_interval = <200>; |
| |
| clk125_cfg:clk125_cfg { |
| clk_freq = <125000000>; |
| clk_parent = "fclk_div4"; |
| clkp_freq = <500000000>; |
| voltage = <1150>; |
| keep_count = <5>; |
| threshold = <30 250>; |
| }; |
| |
| clk250_cfg:clk250_cfg { |
| clk_freq = <250000000>; |
| clk_parent = "fclk_div4"; |
| clkp_freq = <500000000>; |
| voltage = <1150>; |
| keep_count = <5>; |
| threshold = <115 250>; |
| /*125 = 250*(125/250), 50= 60-10*/ |
| }; |
| |
| clk285_cfg:clk285_cfg { |
| clk_freq = <285714285>; |
| clk_parent = "fclk_div7"; |
| clkp_freq = <285714285>; |
| voltage = <1150>; |
| keep_count = <5>; |
| threshold = <100 250>; |
| /*109 = 250*(125/285)*/ |
| }; |
| |
| clk400_cfg:clk400_cfg { |
| clk_freq = <400000000>; |
| clk_parent = "fclk_div5"; |
| clkp_freq = <400000000>; |
| voltage = <1150>; |
| keep_count = <3>; |
| threshold = <168 250>; |
| /*178 = 250*(285/400)*/ |
| }; |
| |
| clk500_cfg:clk500_cfg { |
| clk_freq = <500000000>; |
| clk_parent = "fclk_div4"; |
| clkp_freq = <500000000>; |
| voltage = <1150>; |
| keep_count = <2>; |
| threshold = <190 250>; |
| /*200=250*(400/500)*/ |
| }; |
| |
| clk666_cfg:clk666_cfg { |
| clk_freq = <666666666>; |
| clk_parent = "fclk_div3"; |
| clkp_freq = <666666666>; |
| voltage = <1150>; |
| keep_count = <1>; |
| threshold = <177 250>; |
| /*187.5=250*(500/666.6)*/ |
| }; |
| |
| clk750_cfg:clk750_cfg { |
| clk_freq = <744000000>; |
| clk_parent = "gp0_pll"; |
| clkp_freq = <744000000>; |
| voltage = <1150>; |
| keep_count = <1>; |
| threshold = <213 255>; |
| /*223=250*(666.0/744.0), 223+7=230*/ |
| }; |
| |
| clk800_cfg:clk800_cfg { |
| clk_freq = <792000000>; |
| clk_parent = "gp0_pll"; |
| clkp_freq = <792000000>; |
| voltage = <1150>; |
| keep_count = <1>; |
| threshold = <230 255>; |
| }; |
| |
| }; |
| };/* end of / */ |
