| /* |
| * Amlogic GXTVBB Platform gpu |
| * |
| * Copyright (c) 2015-2017 Amlogic Ltd |
| * |
| * This file is licensed under a dual GPLv2 or BSD license. |
| * |
| */ |
| |
| / { |
| t83x_gpu:t83x@d00c0000{ |
| compatible = "arm,malit602", "arm,malit60x", |
| "arm,malit6xx", "arm,mali-midgard"; |
| #cooling-cells = <2>; /* min followed by max */ |
| reg = <0xd00c0000 0x100000>, |
| <0xc1104440 0x001000>, |
| <0xc8100000 0x001000>, |
| <0xc883c000 0x001000>, /* hiubus for gpu clk cntl*/ |
| <0xc1104440 0x001000>; |
| interrupt-parent = <&gic>; |
| interrupts = <0 160 4>, <0 161 4>, <0 162 4>; |
| interrupt-names = "GPU", "MMU", "JOB"; |
| num_of_pp = <2>; |
| sc_mpp = <1>; /* number of shader cores used most of time. */ |
| /* mali-supply = <&vdd_mali>; */ |
| operating-points = < |
| /* KHz uV */ |
| 666666 1000000 |
| 500000 1000000 |
| 400000 1000000 |
| 285714 1000000 |
| 250000 1000000 |
| 125000 1000000 |
| >; |
| |
| tbl = <&dvfs125_cfg |
| &dvfs285_cfg |
| &dvfs400_cfg |
| &dvfs500_cfg |
| &dvfs666_cfg |
| &dvfs666_cfg>; |
| |
| clocks = <&clkc CLKID_GPU_MUX &clkc CLKID_GP0_PLL>; |
| clock-names = "gpu_mux","gp0_pll"; |
| |
| dvfs125_cfg:clk125_cfg { |
| clk_freq = <125000000>; |
| clk_parent = "fclk_div4"; |
| clkp_freq = <500000000>; |
| voltage = <1150>; |
| keep_count = <5>; |
| threshold = <30 120>; |
| }; |
| |
| dvfs250_cfg:dvfs250_cfg { |
| clk_freq = <250000000>; |
| clk_parent = "fclk_div4"; |
| clkp_freq = <500000000>; |
| voltage = <1150>; |
| keep_count = <5>; |
| threshold = <80 170>; |
| }; |
| |
| dvfs285_cfg:dvfs285_cfg { |
| clk_freq = <285714000>; |
| clk_parent = "fclk_div7"; |
| clkp_freq = <285714285>; |
| voltage = <1150>; |
| keep_count = <5>; |
| threshold = <100 190>; |
| }; |
| |
| dvfs400_cfg:dvfs400_cfg { |
| clk_freq = <400000000>; |
| clk_parent = "fclk_div5"; |
| clkp_freq = <400000000>; |
| voltage = <1150>; |
| keep_count = <5>; |
| threshold = <152 207>; |
| }; |
| |
| dvfs500_cfg:dvfs500_cfg { |
| clk_freq = <500000000>; |
| clk_parent = "fclk_div4"; |
| clkp_freq = <500000000>; |
| voltage = <1150>; |
| keep_count = <5>; |
| threshold = <180 220>; |
| }; |
| |
| dvfs666_cfg:dvfs666_cfg { |
| clk_freq = <666666666>; |
| clk_parent = "fclk_div3"; |
| clkp_freq = <666666666>; |
| voltage = <1150>; |
| keep_count = <5>; |
| threshold = <210 236>; |
| }; |
| |
| dvfs750_cfg:dvfs750_cfg { |
| clk_freq = <744000000>; |
| clk_parent = "gp0_pll"; |
| clkp_freq = <744000000>; |
| voltage = <1150>; |
| keep_count = <5>; |
| threshold = <230 255>; |
| }; |
| }; |
| |
| };/* end of / */ |
