blob: 0a6a0f7a270ac9115997ae9412fe3e5eb9f5b8e0 [file] [log] [blame]
/*
* drivers/amlogic/media/vout/lcd/lcd_extern/mipi_P070ACB.c
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/amlogic/i2c-amlogic.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/amlogic/media/vout/lcd/lcd_extern.h>
#include "lcd_extern.h"
#define LCD_EXTERN_NAME "mipi_P070ACB_FT"
/* ******************** mipi command ********************
* format: data_type, num, data....
* special: data_type=0xff, num<0xff means delay ms, num=0xff means ending.
*/
static unsigned char mipi_init_on_table[] = {
0x23,2,0xE0,0x00, /* Page 0 */
0x23,2,0xE1,0x93, /* PASSWORD */
0x23,2,0xE2,0x65,
0x23,2,0xE3,0xF8,
0x23,2,0x80,0x03, /* DSI 4 lane */
0x23,2,0xE0,0x01, /* Page 01 */
0x23,2,0x0C,0x74, /* Set PWRIC */
0x23,2,0x17,0x00, /* Set Gamma Power */
0x23,2,0x18,0xEF, /* VGMP=5.1V */
0x23,2,0x19,0x00, /* VGSP=0V */
0x23,2,0x1A,0x00,
0x23,2,0x1B,0xEF, /* VGMN=-5.1V */
0x23,2,0x1C,0x00, /* VGSN=0V */
0x23,2,0x1F,0x70, /* VGH_REG=16.2V */
0x23,2,0x20,0x2D, /* VGL_REG=-12V */
0x23,2,0x21,0x2D, /* VGL_REG2=-12V */
0x23,2,0x22,0x7E, /* VGH_REG short to VGH VGL_REG short to VGL */
0x23,2,0x26,0xF3, /* VDDD from IOVCC/VCI */
0x23,2,0x37,0x09, /* SS=1 BGR=1 */
0x23,2,0x38,0x04, /* JDT=100 column inversion */
0x23,2,0x39,0x00, /* Source EQ Setting EQ1 */
0x23,2,0x3A,0x01, /* Source EQ Setting EQ2 */
0x23,2,0x3C,0x90, /* Source EQ Setting EQ3 */
0x23,2,0x3D,0xFF, /* SET Source OP on time */
0x23,2,0x3E,0xFF, /* SET Source OP off time */
0x23,2,0x3F,0xFF, /* SET Source OP off time */
0x23,2,0x40,0x02, /* RSO=640 RGB */
0x23,2,0x41,0x80, /* LN=512->1024 line */
0x23,2,0x42,0x99, /* SLT internal line period */
0x23,2,0x43,0x14, /* VFP */
0x23,2,0x44,0x19, /* VBP */
0x23,2,0x45,0x5A, /* HBP */
0x23,2,0x4B,0x04,
0x23,2,0x55,0x02, /* DCDCM=0010 FP7721BX2 */
0x23,2,0x56,0x01, /* No auto Ratio function */
0x23,2,0x57,0x69, /* VGH_RT=3'b011 2*AVDD-AVEE VGL_RT=3'b010=AVEE+VCL-AVDD VCL_RT=2'b00 0.5*VCIP */
0x23,2,0x58,0x0A, /* AVDD_S */
0x23,2,0x59,0x0A, /* VCL = -2.5V */
0x23,2,0x5A,0x2E, /* VGH = 16.2V */
0x23,2,0x5B,0x19, /* VGL = -12V */
0x23,2,0x5C,0x15, /* pump clk */
0x23,2,0x5D,0x71, /* Gamma */
0x23,2,0x5E,0x58,
0x23,2,0x5F,0x4B,
0x23,2,0x60,0x3F,
0x23,2,0x61,0x3C,
0x23,2,0x62,0x2F,
0x23,2,0x63,0x36,
0x23,2,0x64,0x23,
0x23,2,0x65,0x3E,
0x23,2,0x66,0x3E,
0x23,2,0x67,0x40,
0x23,2,0x68,0x5D,
0x23,2,0x69,0x4B,
0x23,2,0x6A,0x55,
0x23,2,0x6B,0x4A,
0x23,2,0x6C,0x4C,
0x23,2,0x6D,0x43,
0x23,2,0x6E,0x33,
0x23,2,0x6F,0x23,
0x23,2,0x70,0x71,
0x23,2,0x71,0x3F,
0x23,2,0x72,0x32,
0x23,2,0x73,0x26,
0x23,2,0x74,0x23,
0x23,2,0x75,0x16,
0x23,2,0x76,0x1E,
0x23,2,0x77,0x0A,
0x23,2,0x78,0x25,
0x23,2,0x79,0x26,
0x23,2,0x7A,0x27,
0x23,2,0x7B,0x44,
0x23,2,0x7C,0x32,
0x23,2,0x7D,0x3D,
0x23,2,0x7E,0x32,
0x23,2,0x7F,0x33,
0x23,2,0x80,0x2A,
0x23,2,0x81,0x1A,
0x23,2,0x82,0x0B,
0x23,2,0xE0,0x02, /* Page2 */
0x23,2,0x00,0x53, /* GIP_L Pin mapping RESET_EVEN */
0x23,2,0x01,0x55, /* VSSG_EVEN */
0x23,2,0x02,0x55, /* VSSA_EVEN */
0x23,2,0x03,0x51, /* STV2_EVEN */
0x23,2,0x04,0x77, /* VDD2_EVEN */
0x23,2,0x05,0x57, /* VDD1_EVEN */
0x23,2,0x06,0x1F, /* VGL */
0x23,2,0x07,0x4F, /* CK12 */
0x23,2,0x08,0x4D, /* CK10 */
0x23,2,0x09,0x1F, /* VGL */
0x23,2,0x0A,0x4B, /* CK8 */
0x23,2,0x0B,0x49, /* CK6 */
0x23,2,0x0C,0x1F, /* VGL */
0x23,2,0x0D,0x47, /* CK4 */
0x23,2,0x0E,0x45, /* CK2 */
0x23,2,0x0F,0x41, /* STV1_EVEN */
0x23,2,0x10,0x1F, /* VGL */
0x23,2,0x11,0x1F, /* VGL */
0x23,2,0x12,0x1F, /* VGL */
0x23,2,0x13,0x55, /* VGG */
0x23,2,0x14,0x1F, /* VGL */
0x23,2,0x15,0x1F, /* VGL */
0x23,2,0x16,0x52, /* GIP_R Pin mapping RESET_ODD */
0x23,2,0x17,0x55, /* VSSG_ODD */
0x23,2,0x18,0x55, /* VSSA_ODD */
0x23,2,0x19,0x50, /* STV2_ODD */
0x23,2,0x1A,0x77, /* VDD2_ODD */
0x23,2,0x1B,0x57, /* VDD1_ODD */
0x23,2,0x1C,0x1F, /* VGL */
0x23,2,0x1D,0x4E, /* CK11 */
0x23,2,0x1E,0x4C, /* CK9 */
0x23,2,0x1F,0x1F, /* VGL */
0x23,2,0x20,0x4A, /* CK7 */
0x23,2,0x21,0x48, /* CK5 */
0x23,2,0x22,0x1F, /* VGL */
0x23,2,0x23,0x46, /* CK3 */
0x23,2,0x24,0x44, /* CK1 */
0x23,2,0x25,0x40, /* STV1_ODD */
0x23,2,0x26,0x1F, /* VGL */
0x23,2,0x27,0x1F, /* VGL */
0x23,2,0x28,0x1F, /* VGL */
0x23,2,0x29,0x1F, /* VGL */
0x23,2,0x2A,0x1F, /* VGL */
0x23,2,0x2B,0x55, /* VGG */
0x23,2,0x2C,0x12, /* GIP_L_GS Pin mapping RESET_EVEN */
0x23,2,0x2D,0x15, /* VSSG_EVEN */
0x23,2,0x2E,0x15, /* VSSA_EVEN */
0x23,2,0x2F,0x00, /* STV2_EVEN */
0x23,2,0x30,0x17, /* VDD2_EVEN */
0x23,2,0x31,0x17, /* VDD1_EVEN */
0x23,2,0x32,0x1F, /* VGL */
0x23,2,0x33,0x08, /* CK12 */
0x23,2,0x34,0x0A, /* CK10 */
0x23,2,0x35,0x1F, /* VGL */
0x23,2,0x36,0x0C, /* CK8 */
0x23,2,0x37,0x0E, /* CK6 */
0x23,2,0x38,0x1F, /* VGL */
0x23,2,0x39,0x04, /* CK4 */
0x23,2,0x3A,0x06, /* CK2 */
0x23,2,0x3B,0x10, /* STV1_EVEN */
0x23,2,0x3C,0x1F, /* VGL */
0x23,2,0x3D,0x1F, /* VGL */
0x23,2,0x3E,0x1F, /* VGL */
0x23,2,0x3F,0x15, /* VGG */
0x23,2,0x40,0x1F, /* VGL */
0x23,2,0x41,0x1F, /* VGL */
0x23,2,0x42,0x13, /* GIP_R_GS Pin mapping RESET_ODD */
0x23,2,0x43,0x15, /* VSSG_ODD */
0x23,2,0x44,0x15, /* VSSA_ODD */
0x23,2,0x45,0x01, /* STV2_ODD */
0x23,2,0x46,0x37, /* VDD2_ODD */
0x23,2,0x47,0x17, /* VDD1_ODD */
0x23,2,0x48,0x1F, /* VGL */
0x23,2,0x49,0x09, /* CK11 */
0x23,2,0x4A,0x0B, /* CK9 */
0x23,2,0x4B,0x1F, /* VGL */
0x23,2,0x4C,0x0D, /* CK7 */
0x23,2,0x4D,0x0F, /* CK5 */
0x23,2,0x4E,0x1F, /* VGL */
0x23,2,0x4F,0x05, /* CK3 */
0x23,2,0x50,0x07, /* CK1 */
0x23,2,0x51,0x11, /* STV1_ODD */
0x23,2,0x52,0x1F, /* VGL */
0x23,2,0x53,0x1F, /* VGL */
0x23,2,0x54,0x1F, /* VGL */
0x23,2,0x55,0x1F, /* VGL */
0x23,2,0x56,0x1F, /* VGL */
0x23,2,0x57,0x15, /* VGG */
0x23,2,0x58,0x40, /* GAS OPT=1 for abnormal power off */
0x23,2,0x59,0x00, /* INIT_W */
0x23,2,0x5A,0x00, /* INIT[7:0] */
0x23,2,0x5B,0x10, /* STV_NUM STV_S0[10:8] */
0x23,2,0x5C,0x14, /* STV_S0[7:0] */
0x23,2,0x5D,0x40, /* STV_W STV_S1 */
0x23,2,0x5E,0x01, /* STV_S2 */
0x23,2,0x5F,0x02, /* STV_S3 */
0x23,2,0x60,0x40, /* ETV_W ETV_S1 */
0x23,2,0x61,0x03, /* ETV_S2 */
0x23,2,0x62,0x04, /* ETV_S3 */
0x23,2,0x63,0x7A, /* SETV_ON for STV/ETV on time */
0x23,2,0x64,0x7A, /* SETV_OFF for STV/ETV off time */
0x23,2,0x65,0x74, /* ETV_EN ETV_NUM ETV_S0 */
0x23,2,0x66,0x16, /* ETV_S0 */
0x23,2,0x67,0xB4, /* CKV0_NUM CKV0_W */
0x23,2,0x68,0x16, /* CKV0_S0 */
0x23,2,0x69,0x7A, /* CKV0_on */
0x23,2,0x6A,0x7A, /* CKV0_off time */
0x23,2,0x6B,0x0C, /* CKV0_DUM */
0x23,2,0x6C,0x00, /* GIP Line EQ option */
0x23,2,0x6D,0x04, /* GIP rising EQ */
0x23,2,0x6E,0x04, /* GIP fallig EQ */
0x23,2,0x6F,0x88, /* GIP_DR CKV0_CON CKV1_CON */
0x23,2,0x70,0x00, /* CKV1_NUM CKV0_W */
0x23,2,0x71,0x00, /* CKV1_S0 */
0x23,2,0x72,0x06, /* CKV1_on */
0x23,2,0x73,0x7B, /* CKV1_off time */
0x23,2,0x74,0x00, /* CKV1_DUM */
0x23,2,0x75,0xBC, /* FLM_EN FLM_W */
0x23,2,0x76,0x00, /* FLM on time */
0x23,2,0x77,0x04, /* VEN_EN VEN_W FLM_NUM FLM_OFF */
0x23,2,0x78,0x2C, /* FLM_OFF */
0x23,2,0x79,0x00, /* VEN_W */
0x23,2,0x7A,0x00, /* VEN_S0 */
0x23,2,0x7B,0x00, /* VEN_S1 */
0x23,2,0x7C,0x00, /* VEN_DUM */
0x23,2,0x7D,0x03, /* VEN on time */
0x23,2,0x7E,0x7B, /* VEN off time */
0x23,2,0xE0,0x03, /* Page3 */
0x23,2,0xAF,0x20, /* Set CABC */
0x23,2,0xE0,0x04, /* Page4 */
0x23,2,0x09,0x11, /* Source level at blanking period */
0x23,2,0x0E,0x48, /* Source EQ option */
0x23,2,0x2B,0x2B, /* ESD Protect */
0x23,2,0x2E,0x44, /* Special Packet disable */
0x23,2,0x41,0xFF, /* Set CABC */
0x23,2,0xE0,0x00, /* Page0 */
0x23,2,0xE6,0x02, /* Enable Watch Dog */
0x23,2,0xE7,0x0C, /* Watch Dog timer setting */
0x23,2,0x51,0x80, /* CABC Option 0x80=50% duty 0xFF=100% */
0x23,2,0x53,0x2C,
0x23,2,0x55,0x00,
0x05,1,0x11, /* Sleep Out */
0xfd,1,120,
0x05,1,0x29, /* Display on */
0x05,1,0x35,
0xfd,1,20, /* Delay(ms) */
0xFF,0, /* Ending */
};
static unsigned char mipi_init_off_table[] = {
0xff, 5, /* delay 5ms */
0x05, 1, 0x28, /* display off */
0xff, 60, /* delay 10ms */
0x05, 1, 0x10, /* sleep in */
0xff, 150, /* delay 150ms */
0xff, 0xff, /* ending flag */
};
static int lcd_extern_driver_update(struct aml_lcd_extern_driver_s *ext_drv)
{
int ret = 0;
if (ext_drv) {
ext_drv->config.table_init_on = &mipi_init_on_table[0];
ext_drv->config.table_init_off = &mipi_init_off_table[0];
} else {
EXTERR("%s driver is null\n", LCD_EXTERN_NAME);
ret = -1;
}
return ret;
}
int aml_lcd_extern_mipi_p070acb_ft_probe(struct aml_lcd_extern_driver_s *ext_drv)
{
int ret = 0;
ret = lcd_extern_driver_update(ext_drv);
if (lcd_debug_print_flag)
EXTPR("%s: %d\n", __func__, ret);
return ret;
}