sound/soc/codecs/tas5805m_config.h

#ifndef _TAS5805M_CONFIG_H_
#define _TAS5805M_CONFIG_H_

typedef unsigned char cfg_u8;

typedef struct {
    cfg_u8 offset;   /* command */
    cfg_u8 value;    /* param   */
}cfg_reg;

#define CFG_META_SWITCH (255)
#define CFG_META_DELAY  (254)
#define CFG_META_BURST  (253)

static cfg_reg tas5805m_init_sequence1[] =
{
    { 0x00, 0x00 },
    { 0x7f, 0x00 },  // Go to Book 0, Page 0
    { 0x03, 0x02 },  // HI-Z
    { 0x01, 0x11 },  // Reset Control Port Registers and Full Digital Core
    { 0x00, 0x00 },
    { 0x7f, 0x00 },  // Go to Book 0, Page 0
    { 0x03, 0x02 },  // HI-Z
};

// Delay here for at least 5ms

static cfg_reg tas5805m_init_sequence2[] =
{
    { 0x00, 0x00 },
    { 0x7f, 0x00 },  // Go to Book 0, Page 0
    { 0x03, 0x00 },  // Deep Sleep
    { 0x00, 0x00 },
    { 0x7f, 0x00 },  // Go to Book 0, Page 0
    { 0x46, 0x01 },  // 96kHz process flow

    { 0x00, 0x00 },
    { 0x7f, 0x00 },  // Go to Book 0, Page 0
    { 0x03, 0x02 },  // HI-Z
    { 0x00, 0x00 },
    { 0x7f, 0x00 },
    { 0x78, 0x80 },  // Fault clear (Not required, but recommended)

    { 0x00, 0x00 },
    { 0x7f, 0x00 },  // Go to Book 0, Page 0
    { 0x61, 0x0b },  // Change to fault detection after boot
    { 0x60, 0x01 },  // Change to fault detection after boot

    { 0x00, 0x00 },  // Go to Page 0
    { 0x02, 0x05 },  // 1SPW, 768k PBTL
    { 0x53, 0x60 },  // BW: 175k
    { 0x54, 0x0a },  // Amp Peak Output Voltage: 16.5V
    { 0x6B, 0x00 },  // Spread Spectrum: Ensure SSM Off
    { 0x6C, 0x05 },  // Spread Spectrum: 48k, 10%, No Random/Dither
    { 0x6D, 0x50 },  // Spread Spectrum: Ensure Value is 0x50

    { 0x33, 0x03 },  // 32-bit I2S word
    { 0x3a, 0xf8 },  // DRBOOST Disabled
    { 0x50, 0x00 },  // Automute Disabled
    { 0x5f, 0x1e },  // Analog Gain Ramp

    { 0x00, 0x00 },
    { 0x7f, 0x00 },  // Go to Book 0,Page 0
    { 0x66, 0x87 },  // bypass DRC, EQ, 128 Tap FIR

    { 0x00, 0x00 },
    { 0x7f, 0x8c }, 
    { 0x00, 0x29 },  // Book 8C Page 29
    { 0x18, 0x00 },  // Input mixer set to left channel only
    { 0x19, 0x80 },
    { 0x1a, 0x00 },
    { 0x1b, 0x00 },
    { 0x1c, 0x00 },
    { 0x1d, 0x00 },
    { 0x1e, 0x00 },
    { 0x1f, 0x00 },
    { 0x20, 0x00 },
    { 0x21, 0x00 },
    { 0x22, 0x00 },
    { 0x23, 0x00 },
    { 0x24, 0x00 },
    { 0x25, 0x00 },
    { 0x26, 0x00 },
    { 0x27, 0x00 }, 

    { 0x00, 0x2a }, // page 2A
    { 0x24, 0x00 }, // volume control -- 0x24 and 0x28 are default
    { 0x25, 0x80 },
    { 0x26, 0x00 },
    { 0x27, 0x00 },
    { 0x28, 0x00 },
    { 0x29, 0x80 },
    { 0x2a, 0x00 },
    { 0x2b, 0x00 },
    { 0x30, 0x00 }, // Went from 1.5ms to 3ms
    { 0x31, 0x71 },
    { 0x32, 0x94 },
    { 0x33, 0x9a },


    { 0x00, 0x00 },
    { 0x7f, 0x8c }, // Book 8C, page 2C
    { 0x00, 0x2c }, // AGL Section
    { 0x5c, 0x00 }, // Set Release to 0.001
    { 0x5d, 0x00 },
    { 0x5e, 0x57 },
    { 0x5f, 0x62 },
    { 0x60, 0x00 }, // Set Attack to 0.3
    { 0x61, 0xcd },
    { 0x62, 0x7b },
    { 0x63, 0x90 },
    { 0x64, 0x05 }, // Set AGL Threshold to -3dB
    { 0x65, 0xb7 },
    { 0x66, 0xb1 },
    { 0x67, 0x5b },
    { 0x68, 0x40 }, // Disable AGL (at boot)
    { 0x69, 0x00 },
    { 0x6a, 0x00 },
    { 0x6b, 0x00 },
    { 0x6c, 0x08 }, // Set Alpha to 0.15ms
    { 0x6d, 0x96 },
    { 0x6e, 0x57 },
    { 0x6f, 0x44 },

    { 0x74, 0x7F }, // Thermal foldback is enabled when AGL is enabled
    { 0x75, 0xFF }, // The temp scale setting here effectively disables it
    { 0x76, 0xFF },
    { 0x77, 0xFF },


    { 0x00, 0x2d },  // Page 2D
    { 0x18, 0x77 },  // AGL Omega to correspond with setting AGL Alpha to 0.15ms
    { 0x19, 0x69 },
    { 0x1a, 0xa8 },
    { 0x1b, 0xbc },


    { 0x00, 0x00 },
    { 0x7f, 0x00 },  // Go to Book 0, Page 0
    { 0x30, 0x00 },  // SDOUT set to postDSP
    { 0x4c, 0x30 },  // digital volume 0dB
    { 0x03, 0x03 },  // Set to PLAY

     // WARNING: nothing should be after this except clearing faults
    { 0x00, 0x00 },  // Go to Book 0, Page 0
    { 0x7f, 0x00 },
    { 0x78, 0x80 },  // Clear faults
};

#endif