| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright (c) 2019 Amlogic, Inc. All rights reserved. |
| */ |
| |
| #include <linux/clk.h> |
| #include <linux/clk-provider.h> |
| #include <linux/init.h> |
| #include <linux/of_device.h> |
| #include <linux/mfd/syscon.h> |
| #include <linux/platform_device.h> |
| #include <linux/regmap.h> |
| #include <linux/slab.h> |
| |
| #include "clkc.h" |
| #include "g12a.h" |
| |
| static DEFINE_SPINLOCK(meson_clk_lock); |
| |
| static struct clk_regmap g12a_fixed_pll_dco = { |
| .data = &(struct meson_clk_pll_data){ |
| .en = { |
| .reg_off = HHI_FIX_PLL_CNTL0, |
| .shift = 28, |
| .width = 1, |
| }, |
| .m = { |
| .reg_off = HHI_FIX_PLL_CNTL0, |
| .shift = 0, |
| .width = 8, |
| }, |
| .n = { |
| .reg_off = HHI_FIX_PLL_CNTL0, |
| .shift = 10, |
| .width = 5, |
| }, |
| .frac = { |
| .reg_off = HHI_FIX_PLL_CNTL1, |
| .shift = 0, |
| .width = 19, |
| }, |
| .l = { |
| .reg_off = HHI_FIX_PLL_CNTL0, |
| .shift = 31, |
| .width = 1, |
| }, |
| .rst = { |
| .reg_off = HHI_FIX_PLL_CNTL0, |
| .shift = 29, |
| .width = 1, |
| }, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "fixed_pll_dco", |
| .ops = &meson_clk_pll_ro_ops, |
| .parent_names = (const char *[]){ "g12a_ee_core" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_fixed_pll = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_FIX_PLL_CNTL0, |
| .shift = 16, |
| .width = 2, |
| .flags = CLK_DIVIDER_POWER_OF_TWO, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "fixed_pll", |
| .ops = &clk_regmap_divider_ro_ops, |
| .parent_names = (const char *[]){ "fixed_pll_dco" }, |
| .num_parents = 1, |
| /* |
| * This clock won't ever change at runtime so |
| * CLK_SET_RATE_PARENT is not required |
| */ |
| }, |
| }; |
| |
| /* |
| * Internal sys pll emulation configuration parameters |
| */ |
| static const struct reg_sequence g12a_sys_init_regs[] = { |
| { .reg = HHI_SYS_PLL_CNTL1, .def = 0x00000000 }, |
| { .reg = HHI_SYS_PLL_CNTL2, .def = 0x00000000 }, |
| { .reg = HHI_SYS_PLL_CNTL3, .def = 0x48681c00 }, |
| { .reg = HHI_SYS_PLL_CNTL4, .def = 0x88770290 }, |
| { .reg = HHI_SYS_PLL_CNTL5, .def = 0x39272000 }, |
| { .reg = HHI_SYS_PLL_CNTL6, .def = 0x56540000, .delay_us = 10 }, |
| }; |
| |
| static const struct clk_ops meson_pll_clk_no_ops = {}; |
| |
| /* |
| * the sys pll DCO value should be 3G~6G, |
| * otherwise the sys pll can not lock. |
| * od is for 32 bit. |
| */ |
| |
| #ifdef CONFIG_ARM |
| static const struct pll_params_table g12a_sys_pll_params_table[] = { |
| PLL_PARAMS(128, 1, 7), /*DCO=3072M OD=24M*/ |
| PLL_PARAMS(128, 1, 6), /*DCO=3072M OD=48M*/ |
| PLL_PARAMS(128, 1, 5), /*DCO=3072M OD=96M*/ |
| PLL_PARAMS(128, 1, 4), /*DCO=3072M OD=192M*/ |
| PLL_PARAMS(208, 1, 4), /*DCO=4992M OD=312M*/ |
| PLL_PARAMS(136, 1, 3), /*DCO=3264M OD=408M*/ |
| PLL_PARAMS(200, 1, 3), /*DCO=4800M OD=600M*/ |
| PLL_PARAMS(232, 1, 3), /*DCO=5568M OD=696M*/ |
| PLL_PARAMS(132, 1, 2), /*DCO=3168M OD=792M*/ |
| PLL_PARAMS(141, 1, 2), /*DCO=3384M OD=846M*/ |
| PLL_PARAMS(142, 1, 2), /*DCO=3408M OD=852M*/ |
| PLL_PARAMS(149, 1, 2), /*DCO=3576M OD=894M*/ |
| PLL_PARAMS(152, 1, 2), /*DCO=3648M OD=912M*/ |
| PLL_PARAMS(168, 1, 2), /*DCO=4032M OD=1008M*/ |
| PLL_PARAMS(184, 1, 2), /*DCO=4416M OD=1104M*/ |
| PLL_PARAMS(200, 1, 2), /*DCO=4800M OD=1200M*/ |
| PLL_PARAMS(216, 1, 2), /*DCO=5184M OD=1296M*/ |
| PLL_PARAMS(233, 1, 2), /*DCO=5592M OD=1398M*/ |
| PLL_PARAMS(249, 1, 2), /*DCO=5976M OD=1494M*/ |
| PLL_PARAMS(126, 1, 1), /*DCO=3024M OD=1512M*/ |
| PLL_PARAMS(134, 1, 1), /*DCO=3216M OD=1608M*/ |
| PLL_PARAMS(142, 1, 1), /*DCO=3408M OD=1704M*/ |
| PLL_PARAMS(150, 1, 1), /*DCO=3600M OD=1800M*/ |
| PLL_PARAMS(158, 1, 1), /*DCO=3792M OD=1896M*/ |
| PLL_PARAMS(159, 1, 1), /*DCO=3816M OD=1908*/ |
| PLL_PARAMS(160, 1, 1), /*DCO=3840M OD=1920M*/ |
| PLL_PARAMS(168, 1, 1), /*DCO=4032M OD=2016M*/ |
| /* |
| * The highest freq is 1.9G for cpu freq. |
| * For better efficiency, delete the unused table. |
| * Add it if necessary in the future. |
| */ |
| #ifdef CONFIG_UNUSED |
| PLL_PARAMS(175, 1, 1), /*DCO=4200M OD=2100M*/ |
| PLL_PARAMS(183, 1, 1), /*DCO=4392M OD=2196M*/ |
| PLL_PARAMS(191, 1, 1), /*DCO=4584M OD=2292M*/ |
| PLL_PARAMS(200, 1, 1), /*DCO=4800M OD=2400M*/ |
| PLL_PARAMS(208, 1, 1), /*DCO=4992M OD=2496M*/ |
| PLL_PARAMS(216, 1, 1), /*DCO=5184M OD=2592M*/ |
| PLL_PARAMS(225, 1, 1), /*DCO=5400M OD=2700M*/ |
| PLL_PARAMS(233, 1, 1), /*DCO=5592M OD=2796M*/ |
| PLL_PARAMS(241, 1, 1), /*DCO=5784M OD=2892M*/ |
| PLL_PARAMS(125, 1, 0), /*DCO=3000M OD=3000M*/ |
| PLL_PARAMS(129, 1, 0), /*DCO=3096M OD=3096M*/ |
| PLL_PARAMS(133, 1, 0), /*DCO=3192M OD=3192M*/ |
| PLL_PARAMS(137, 1, 0), /*DCO=3288M OD=3288M*/ |
| PLL_PARAMS(142, 1, 0), /*DCO=3408M OD=3408M*/ |
| PLL_PARAMS(146, 1, 0), /*DCO=3504M OD=3504M*/ |
| PLL_PARAMS(150, 1, 0), /*DCO=3600M OD=3600M*/ |
| PLL_PARAMS(154, 1, 0), /*DCO=3696M OD=3696M*/ |
| PLL_PARAMS(158, 1, 0), /*DCO=3792M OD=3792M*/ |
| PLL_PARAMS(162, 1, 0), /*DCO=3888M OD=3888M*/ |
| PLL_PARAMS(167, 1, 0), /*DCO=4008M OD=4008M*/ |
| PLL_PARAMS(171, 1, 0), /*DCO=4104M OD=4104M*/ |
| PLL_PARAMS(175, 1, 0), /*DCO=4200M OD=4200M*/ |
| PLL_PARAMS(179, 1, 0), /*DCO=4296M OD=4296M*/ |
| PLL_PARAMS(183, 1, 0), /*DCO=4392M OD=4392M*/ |
| PLL_PARAMS(187, 1, 0), /*DCO=4488M OD=4488M*/ |
| PLL_PARAMS(192, 1, 0), /*DCO=4608M OD=4608M*/ |
| PLL_PARAMS(196, 1, 0), /*DCO=4704M OD=4704M*/ |
| PLL_PARAMS(200, 1, 0), /*DCO=4800M OD=4800M*/ |
| PLL_PARAMS(204, 1, 0), /*DCO=4896M OD=4896M*/ |
| PLL_PARAMS(208, 1, 0), /*DCO=4992M OD=4992M*/ |
| PLL_PARAMS(212, 1, 0), /*DCO=5088M OD=5088M*/ |
| PLL_PARAMS(217, 1, 0), /*DCO=5208M OD=5208M*/ |
| PLL_PARAMS(221, 1, 0), /*DCO=5304M OD=5304M*/ |
| PLL_PARAMS(225, 1, 0), /*DCO=5400M OD=5400M*/ |
| PLL_PARAMS(229, 1, 0), /*DCO=5496M OD=5496M*/ |
| PLL_PARAMS(233, 1, 0), /*DCO=5592M OD=5592M*/ |
| PLL_PARAMS(237, 1, 0), /*DCO=5688M OD=5688M*/ |
| PLL_PARAMS(242, 1, 0), /*DCO=5808M OD=5808M*/ |
| PLL_PARAMS(246, 1, 0), /*DCO=5904M OD=5904M*/ |
| PLL_PARAMS(250, 1, 0), /*DCO=6000M OD=6000M*/ |
| #endif |
| { /* sentinel */ }, |
| }; |
| #else |
| static const struct pll_params_table g12a_sys_pll_params_table[] = { |
| PLL_PARAMS(128, 1), /*DCO=3072M OD=24M*/ |
| PLL_PARAMS(128, 1), /*DCO=3072M OD=48M*/ |
| PLL_PARAMS(128, 1), /*DCO=3072M OD=96M*/ |
| PLL_PARAMS(128, 1), /*DCO=3072M OD=192M*/ |
| PLL_PARAMS(208, 1), /*DCO=4992M OD=312M*/ |
| PLL_PARAMS(136, 1), /*DCO=3264M OD=408M*/ |
| PLL_PARAMS(200, 1), /*DCO=4800M OD=600M*/ |
| PLL_PARAMS(232, 1), /*DCO=5568M OD=696M*/ |
| PLL_PARAMS(132, 1), /*DCO=3168M OD=792M*/ |
| PLL_PARAMS(141, 1), /*DCO=3384M OD=846M*/ |
| PLL_PARAMS(142, 1), /*DCO=3408M OD=852M*/ |
| PLL_PARAMS(149, 1), /*DCO=3576M OD=894M*/ |
| PLL_PARAMS(152, 1), /*DCO=3648M OD=912M*/ |
| PLL_PARAMS(168, 1), /*DCO=4032M OD=1008M*/ |
| PLL_PARAMS(184, 1), /*DCO=4416M OD=1104M*/ |
| PLL_PARAMS(200, 1), /*DCO=4800M OD=1200M*/ |
| PLL_PARAMS(216, 1), /*DCO=5184M OD=1296M*/ |
| PLL_PARAMS(233, 1), /*DCO=5592M OD=1398M*/ |
| PLL_PARAMS(249, 1), /*DCO=5976M OD=1494M*/ |
| PLL_PARAMS(126, 1), /*DCO=3024M OD=1512M*/ |
| PLL_PARAMS(134, 1), /*DCO=3216M OD=1608M*/ |
| PLL_PARAMS(142, 1), /*DCO=3408M OD=1704M*/ |
| PLL_PARAMS(150, 1), /*DCO=3600M OD=1800M*/ |
| PLL_PARAMS(158, 1), /*DCO=3792M OD=1896M*/ |
| PLL_PARAMS(159, 1), /*DCO=3816M OD=1908*/ |
| PLL_PARAMS(160, 1), /*DCO=3840M OD=1920M*/ |
| PLL_PARAMS(168, 1), /*DCO=4032M OD=2016M*/ |
| { /* sentinel */ }, |
| }; |
| #endif |
| |
| static struct clk_regmap g12a_sys_pll_dco = { |
| .data = &(struct meson_clk_pll_data){ |
| .en = { |
| .reg_off = HHI_SYS_PLL_CNTL0, |
| .shift = 28, |
| .width = 1, |
| }, |
| .m = { |
| .reg_off = HHI_SYS_PLL_CNTL0, |
| .shift = 0, |
| .width = 8, |
| }, |
| .n = { |
| .reg_off = HHI_SYS_PLL_CNTL0, |
| .shift = 10, |
| .width = 5, |
| }, |
| /* od for 32bit */ |
| .od = { |
| .reg_off = HHI_SYS_PLL_CNTL0, |
| .shift = 16, |
| .width = 3, |
| }, |
| .l = { |
| .reg_off = HHI_SYS_PLL_CNTL0, |
| .shift = 31, |
| .width = 1, |
| }, |
| .rst = { |
| .reg_off = HHI_SYS_PLL_CNTL0, |
| .shift = 29, |
| .width = 1, |
| }, |
| .init_en = 0, |
| .init_regs = g12a_sys_init_regs, |
| .init_count = ARRAY_SIZE(g12a_sys_init_regs), |
| .table = g12a_sys_pll_params_table, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "sys_pll_dco", |
| .ops = &meson_clk_pll_ops, |
| .parent_names = (const char *[]){ "g12a_ee_core" }, |
| .num_parents = 1, |
| /* |
| * sys pll is used by cpu clock , it is initialized |
| * to 1200M in bl2, CLK_IGNORE_UNUSED is needed to |
| * prevent the system hang up which will be called |
| * by clk_disable_unused |
| */ |
| .flags = CLK_IGNORE_UNUSED, |
| }, |
| }; |
| |
| #ifdef CONFIG_ARM |
| /* |
| * If DCO frequency is greater than 2.1G in 32bit,it will |
| * overflow due to the callback .round_rate returns |
| * long (-2147483648 ~ +2147483647). |
| * The OD output value is under 2G, For 32bit, the dco and |
| * od should be described together to avoid overflow. |
| * Beside, I have tried another methods but failed. |
| * 1) change the freq unit to kHZ, it will crash (fixed xtal |
| * = 24000) and it will influences clock users. |
| * 2) change the return value for .round_rate, a greater many |
| * code will be modified, related to whole CCF. |
| * 3) dco pll using kHZ, other clock using HZ, when calculate pll |
| * it will be a lot of mass because of unit deferentces. |
| * |
| * Keep Consistent with 64bit, creat a Virtual clock for sys pll |
| */ |
| static struct clk_regmap g12a_sys_pll = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "sys_pll", |
| .ops = &meson_pll_clk_no_ops, |
| .parent_names = (const char *[]){ "sys_pll_dco" }, |
| .num_parents = 1, |
| /* |
| * sys pll is used by cpu clock , it is initialized |
| * to 1200M in bl2, CLK_IGNORE_UNUSED is needed to |
| * prevent the system hang up which will be called |
| * by clk_disable_unused |
| */ |
| .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, |
| }, |
| }; |
| #else |
| static struct clk_regmap g12a_sys_pll = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_SYS_PLL_CNTL0, |
| .shift = 16, |
| .width = 3, |
| .flags = CLK_DIVIDER_POWER_OF_TWO, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "sys_pll", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "sys_pll_dco" }, |
| .num_parents = 1, |
| /* |
| * sys pll is used by cpu clock , it is initialized |
| * to 1200M in bl2, CLK_IGNORE_UNUSED is needed to |
| * prevent the system hang up which will be called |
| * by clk_disable_unused |
| */ |
| .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, |
| }, |
| }; |
| #endif |
| |
| #ifdef CONFIG_ARM |
| static const struct pll_params_table g12a_gp0_pll_params_table[] = { |
| /* set od 0 default */ |
| PLL_PARAMS(128, 1, 7), /*DCO=3072M OD=24M*/ |
| PLL_PARAMS(128, 1, 6), /*DCO=3072M OD=48M*/ |
| PLL_PARAMS(128, 1, 5), /*DCO=3072M OD=96M*/ |
| PLL_PARAMS(128, 1, 4), /*DCO=3072M OD=192M*/ |
| PLL_PARAMS(208, 1, 4), /*DCO=4992M OD=312M*/ |
| PLL_PARAMS(136, 1, 3), /*DCO=3264M OD=408M*/ |
| PLL_PARAMS(200, 1, 3), /*DCO=4800M OD=600M*/ |
| PLL_PARAMS(232, 1, 3), /*DCO=5568M OD=696M*/ |
| PLL_PARAMS(132, 1, 2), /*DCO=3168M OD=792M*/ |
| PLL_PARAMS(141, 1, 2), /*DCO=3384M OD=846M*/ |
| PLL_PARAMS(142, 1, 2), /*DCO=3408M OD=852M*/ |
| PLL_PARAMS(149, 1, 2), /*DCO=3576M OD=894M*/ |
| PLL_PARAMS(152, 1, 2), /*DCO=3648M OD=912M*/ |
| PLL_PARAMS(168, 1, 2), /*DCO=4032M OD=1008M*/ |
| PLL_PARAMS(184, 1, 2), /*DCO=4416M OD=1104M*/ |
| PLL_PARAMS(200, 1, 2), /*DCO=4800M OD=1200M*/ |
| PLL_PARAMS(216, 1, 2), /*DCO=5184M OD=1296M*/ |
| PLL_PARAMS(233, 1, 2), /*DCO=5592M OD=1398M*/ |
| PLL_PARAMS(249, 1, 2), /*DCO=5976M OD=1494M*/ |
| PLL_PARAMS(126, 1, 1), /*DCO=3024M OD=1512M*/ |
| { /* sentinel */ }, |
| }; |
| #else |
| static const struct pll_params_table g12a_gp0_pll_params_table[] = { |
| PLL_PARAMS(128, 1), /*DCO=3072M */ |
| PLL_PARAMS(128, 1), /*DCO=3072M */ |
| PLL_PARAMS(128, 1), /*DCO=3072M */ |
| PLL_PARAMS(128, 1), /*DCO=3072M */ |
| PLL_PARAMS(208, 1), /*DCO=4992M */ |
| PLL_PARAMS(136, 1), /*DCO=3264M */ |
| PLL_PARAMS(200, 1), /*DCO=4800M */ |
| PLL_PARAMS(232, 1), /*DCO=5568M */ |
| PLL_PARAMS(132, 1), /*DCO=3168M */ |
| PLL_PARAMS(141, 1), /*DCO=3384M */ |
| PLL_PARAMS(142, 1), /*DCO=3408M */ |
| PLL_PARAMS(149, 1), /*DCO=3576M */ |
| PLL_PARAMS(152, 1), /*DCO=3648M */ |
| PLL_PARAMS(168, 1), /*DCO=4032M */ |
| PLL_PARAMS(184, 1), /*DCO=4416M */ |
| PLL_PARAMS(200, 1), /*DCO=4800M */ |
| PLL_PARAMS(216, 1), /*DCO=5184M */ |
| PLL_PARAMS(233, 1), /*DCO=5592M */ |
| PLL_PARAMS(249, 1), /*DCO=5976M */ |
| PLL_PARAMS(126, 1), /*DCO=3024M */ |
| PLL_PARAMS(134, 1), /*DCO=3216M */ |
| PLL_PARAMS(142, 1), /*DCO=3408M */ |
| PLL_PARAMS(150, 1), /*DCO=3600M */ |
| PLL_PARAMS(158, 1), /*DCO=3792M */ |
| PLL_PARAMS(159, 1), /*DCO=3816M */ |
| PLL_PARAMS(160, 1), /*DCO=3840M */ |
| PLL_PARAMS(168, 1), /*DCO=4032M */ |
| { /* sentinel */ }, |
| }; |
| #endif |
| |
| /* |
| * Internal gp0 pll emulation configuration parameters |
| */ |
| static const struct reg_sequence g12a_gp0_init_regs[] = { |
| { .reg = HHI_GP0_PLL_CNTL1, .def = 0x00000000 }, |
| { .reg = HHI_GP0_PLL_CNTL2, .def = 0x00000000 }, |
| { .reg = HHI_GP0_PLL_CNTL3, .def = 0x48681c00 }, |
| { .reg = HHI_GP0_PLL_CNTL4, .def = 0x33771290 }, |
| { .reg = HHI_GP0_PLL_CNTL5, .def = 0x39272000 }, |
| { .reg = HHI_GP0_PLL_CNTL6, .def = 0x56540000, .delay_us = 10 }, |
| }; |
| |
| static struct clk_regmap g12a_gp0_pll_dco = { |
| .data = &(struct meson_clk_pll_data){ |
| .en = { |
| .reg_off = HHI_GP0_PLL_CNTL0, |
| .shift = 28, |
| .width = 1, |
| }, |
| .m = { |
| .reg_off = HHI_GP0_PLL_CNTL0, |
| .shift = 0, |
| .width = 8, |
| }, |
| .n = { |
| .reg_off = HHI_GP0_PLL_CNTL0, |
| .shift = 10, |
| .width = 5, |
| }, |
| /* for 32bit */ |
| .od = { |
| .reg_off = HHI_GP0_PLL_CNTL0, |
| .shift = 16, |
| .width = 3, |
| }, |
| .frac = { |
| .reg_off = HHI_GP0_PLL_CNTL1, |
| .shift = 0, |
| .width = 19, |
| }, |
| .l = { |
| .reg_off = HHI_GP0_PLL_CNTL0, |
| .shift = 31, |
| .width = 1, |
| }, |
| .rst = { |
| .reg_off = HHI_GP0_PLL_CNTL0, |
| .shift = 29, |
| .width = 1, |
| }, |
| .init_en = 0, |
| .table = g12a_gp0_pll_params_table, |
| .init_regs = g12a_gp0_init_regs, |
| .init_count = ARRAY_SIZE(g12a_gp0_init_regs), |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "gp0_pll_dco", |
| .ops = &meson_clk_pll_ops, |
| .parent_names = (const char *[]){ "g12a_ee_core" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| #ifdef CONFIG_ARM |
| static struct clk_regmap g12a_gp0_pll = { |
| .hw.init = &(struct clk_init_data){ |
| .name = "gp0_pll", |
| .ops = &meson_pll_clk_no_ops, |
| .parent_names = (const char *[]){ "gp0_pll_dco" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| #else |
| static struct clk_regmap g12a_gp0_pll = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_GP0_PLL_CNTL0, |
| .shift = 16, |
| .width = 3, |
| .flags = CLK_DIVIDER_POWER_OF_TWO, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "gp0_pll", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "gp0_pll_dco" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| #endif |
| /* |
| * Internal hifi pll emulation configuration parameters |
| */ |
| static const struct reg_sequence g12a_hifi_init_regs[] = { |
| { .reg = HHI_HIFI_PLL_CNTL1, .def = 0x00000000 }, |
| { .reg = HHI_HIFI_PLL_CNTL2, .def = 0x00000000 }, |
| { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x6a285c00 }, |
| { .reg = HHI_HIFI_PLL_CNTL4, .def = 0x65771290 }, |
| { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x39272000 }, |
| { .reg = HHI_HIFI_PLL_CNTL6, .def = 0x56540000 }, |
| }; |
| |
| static struct clk_regmap g12a_hifi_pll_dco = { |
| .data = &(struct meson_clk_pll_data){ |
| .en = { |
| .reg_off = HHI_HIFI_PLL_CNTL0, |
| .shift = 28, |
| .width = 1, |
| }, |
| .m = { |
| .reg_off = HHI_HIFI_PLL_CNTL0, |
| .shift = 0, |
| .width = 8, |
| }, |
| .n = { |
| .reg_off = HHI_HIFI_PLL_CNTL0, |
| .shift = 10, |
| .width = 5, |
| }, |
| .frac = { |
| .reg_off = HHI_HIFI_PLL_CNTL1, |
| .shift = 0, |
| .width = 19, |
| }, |
| .l = { |
| .reg_off = HHI_HIFI_PLL_CNTL0, |
| .shift = 31, |
| .width = 1, |
| }, |
| .rst = { |
| .reg_off = HHI_HIFI_PLL_CNTL0, |
| .shift = 29, |
| .width = 1, |
| }, |
| .table = g12a_gp0_pll_params_table, |
| .init_regs = g12a_hifi_init_regs, |
| .init_count = ARRAY_SIZE(g12a_hifi_init_regs), |
| .flags = CLK_MESON_PLL_ROUND_CLOSEST, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "hifi_pll_dco", |
| .ops = &meson_clk_pll_ops, |
| .parent_names = (const char *[]){ "g12a_ee_core" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_hifi_pll = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_HIFI_PLL_CNTL0, |
| .shift = 16, |
| .width = 2, |
| .flags = CLK_DIVIDER_POWER_OF_TWO, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "hifi_pll", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "hifi_pll_dco" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| #ifdef CONFIG_ARM64 |
| static const struct pll_params_table g12a_hdmi_params_table[] = { |
| PLL_PARAMS(123, 1), /* DCO=2952M */ |
| PLL_PARAMS(135, 1), /* DCO=3240M */ |
| PLL_PARAMS(143, 1), /* DCO=3432M */ |
| PLL_PARAMS(154, 1), /* DCO=3696M */ |
| PLL_PARAMS(154, 1), /* DCO=3696M */ |
| PLL_PARAMS(180, 1), /* DCO=4320M */ |
| PLL_PARAMS(185, 1), /* DCO=4440M */ |
| PLL_PARAMS(204, 1), /* DCO=4896M */ |
| PLL_PARAMS(225, 1), /* DCO=5400M */ |
| PLL_PARAMS(247, 1), /* DCO=5928M */ |
| { /* sentinel */ }, |
| }; |
| #else |
| static const struct pll_params_table g12a_hdmi_params_table[] = { |
| PLL_PARAMS(123, 1, 0), /* DCO=2952M */ |
| PLL_PARAMS(135, 1, 0), /* DCO=3240M */ |
| PLL_PARAMS(143, 1, 0), /* DCO=3432M */ |
| PLL_PARAMS(154, 1, 0), /* DCO=3696M */ |
| PLL_PARAMS(154, 1, 0), /* DCO=3696M */ |
| PLL_PARAMS(180, 1, 0), /* DCO=4320M */ |
| PLL_PARAMS(185, 1, 0), /* DCO=4440M */ |
| PLL_PARAMS(204, 1, 0), /* DCO=4896M */ |
| PLL_PARAMS(225, 1, 0), /* DCO=5400M */ |
| PLL_PARAMS(247, 1, 0), /* DCO=5928M */ |
| { /* sentinel */ }, |
| }; |
| #endif |
| |
| #ifdef CONFIG_ARM64 |
| static const struct reg_sequence g12a_hdmi_5940000k_regs[] = { |
| { .reg = HHI_HDMI_PLL_CNTL2, .def = 0x0 }, |
| { .reg = HHI_HDMI_PLL_CNTL3, .def = 0x6a68dc00 }, |
| { .reg = HHI_HDMI_PLL_CNTL4, .def = 0x65771290 }, |
| { .reg = HHI_HDMI_PLL_CNTL5, .def = 0x39272000 }, |
| { .reg = HHI_HDMI_PLL_CNTL6, .def = 0x56540000 }, |
| }; |
| |
| static const struct reg_sequence g12a_hdmi_5405400k_regs[] = { |
| { .reg = HHI_HDMI_PLL_CNTL2, .def = 0x0 }, |
| { .reg = HHI_HDMI_PLL_CNTL3, .def = 0x0a691c00 }, |
| { .reg = HHI_HDMI_PLL_CNTL4, .def = 0x33771290 }, |
| { .reg = HHI_HDMI_PLL_CNTL5, .def = 0x39270000 }, |
| { .reg = HHI_HDMI_PLL_CNTL6, .def = 0x50540000 }, |
| }; |
| |
| static const struct reg_sequence g12a_hdmi_4897000k_regs[] = { |
| { .reg = HHI_HDMI_PLL_CNTL2, .def = 0x0 }, |
| { .reg = HHI_HDMI_PLL_CNTL3, .def = 0x6a685c00 }, |
| { .reg = HHI_HDMI_PLL_CNTL4, .def = 0x43231290 }, |
| { .reg = HHI_HDMI_PLL_CNTL5, .def = 0x29272000 }, |
| { .reg = HHI_HDMI_PLL_CNTL6, .def = 0x56540028 }, |
| }; |
| |
| static const struct reg_sequence g12a_hdmi_4455000k_regs[] = { |
| { .reg = HHI_HDMI_PLL_CNTL2, .def = 0x0 }, |
| { .reg = HHI_HDMI_PLL_CNTL3, .def = 0x6a685c00 }, |
| { .reg = HHI_HDMI_PLL_CNTL4, .def = 0x43231290 }, |
| { .reg = HHI_HDMI_PLL_CNTL5, .def = 0x29272000 }, |
| { .reg = HHI_HDMI_PLL_CNTL6, .def = 0x56540028 }, |
| }; |
| |
| static const struct reg_sequence g12a_hdmi_4324320k_regs[] = { |
| { .reg = HHI_HDMI_PLL_CNTL2, .def = 0x0 }, |
| { .reg = HHI_HDMI_PLL_CNTL3, .def = 0x0a691c00 }, |
| { .reg = HHI_HDMI_PLL_CNTL4, .def = 0x33771290 }, |
| { .reg = HHI_HDMI_PLL_CNTL5, .def = 0x39270000 }, |
| { .reg = HHI_HDMI_PLL_CNTL6, .def = 0x50540000 }, |
| }; |
| |
| static const struct reg_sequence g12a_hdmi_3712500k_regs[] = { |
| { .reg = HHI_HDMI_PLL_CNTL2, .def = 0x0 }, |
| { .reg = HHI_HDMI_PLL_CNTL3, .def = 0x6a685c00 }, |
| { .reg = HHI_HDMI_PLL_CNTL4, .def = 0x43231290 }, |
| { .reg = HHI_HDMI_PLL_CNTL5, .def = 0x39270000 }, |
| { .reg = HHI_HDMI_PLL_CNTL6, .def = 0x56540028 }, |
| }; |
| |
| static const struct reg_sequence g12a_hdmi_common_regs[] = { |
| { .reg = HHI_HDMI_PLL_CNTL2, .def = 0x0 }, |
| { .reg = HHI_HDMI_PLL_CNTL3, .def = 0x0a691c00 }, |
| { .reg = HHI_HDMI_PLL_CNTL4, .def = 0x33771290 }, |
| { .reg = HHI_HDMI_PLL_CNTL5, .def = 0x39270000 }, |
| { .reg = HHI_HDMI_PLL_CNTL6, .def = 0x50540000 }, |
| }; |
| |
| static const struct pravite_pll_parm g12a_hdmi_rate_parm_table[] = { |
| { .rate = 5940000000, .rate_regs = g12a_hdmi_5940000k_regs, |
| .regs_count = ARRAY_SIZE(g12a_hdmi_5940000k_regs) }, |
| { .rate = 5405400000, .rate_regs = g12a_hdmi_5405400k_regs, |
| .regs_count = ARRAY_SIZE(g12a_hdmi_5405400k_regs) }, |
| { .rate = 4897000000, .rate_regs = g12a_hdmi_4897000k_regs, |
| .regs_count = ARRAY_SIZE(g12a_hdmi_4897000k_regs) }, |
| { .rate = 4455000000, .rate_regs = g12a_hdmi_4455000k_regs, |
| .regs_count = ARRAY_SIZE(g12a_hdmi_4455000k_regs) }, |
| { .rate = 4324320000, .rate_regs = g12a_hdmi_4324320k_regs, |
| .regs_count = ARRAY_SIZE(g12a_hdmi_4324320k_regs) }, |
| { .rate = 3712500000, .rate_regs = g12a_hdmi_3712500k_regs, |
| .regs_count = ARRAY_SIZE(g12a_hdmi_3712500k_regs) }, |
| { .rate = 3450000000, .rate_regs = g12a_hdmi_common_regs, |
| .regs_count = ARRAY_SIZE(g12a_hdmi_common_regs) }, |
| { .rate = 3243240000, .rate_regs = g12a_hdmi_common_regs, |
| .regs_count = ARRAY_SIZE(g12a_hdmi_common_regs) }, |
| { .rate = 2970000000, .rate_regs = g12a_hdmi_common_regs, |
| .regs_count = ARRAY_SIZE(g12a_hdmi_common_regs)}, |
| }; |
| #else |
| static const struct pravite_pll_parm g12a_hdmi_rate_parm_table[] = { |
| }; |
| #endif |
| |
| static struct clk_regmap g12a_hdmi_pll_dco = { |
| .data = &(struct meson_clk_pll_data){ |
| .en = { |
| .reg_off = HHI_HDMI_PLL_CNTL0, |
| .shift = 28, |
| .width = 1, |
| }, |
| .m = { |
| .reg_off = HHI_HDMI_PLL_CNTL0, |
| .shift = 0, |
| .width = 8, |
| }, |
| .n = { |
| .reg_off = HHI_HDMI_PLL_CNTL0, |
| .shift = 10, |
| .width = 5, |
| }, |
| .frac = { |
| .reg_off = HHI_HDMI_PLL_CNTL1, |
| .shift = 0, |
| .width = 19, |
| }, |
| .l = { |
| .reg_off = HHI_HDMI_PLL_CNTL0, |
| .shift = 31, |
| .width = 1, |
| }, |
| .rst = { |
| .reg_off = HHI_HDMI_PLL_CNTL0, |
| .shift = 29, |
| .width = 1, |
| }, |
| .init_en = 0, |
| .init_count = 0, |
| .table = g12a_hdmi_params_table, |
| .pri_table = g12a_hdmi_rate_parm_table, |
| .pri_table_count = ARRAY_SIZE(g12a_hdmi_rate_parm_table), |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "hdmi_pll_dco", |
| .ops = &meson_clk_pll_ops, |
| .parent_names = (const char *[]){ "g12a_ee_core" }, |
| .num_parents = 1, |
| /* |
| * 1.Display directly handle hdmi pll registers ATM, we need |
| * NOCACHE to keep our view of the clock as accurate as possible |
| * 2.hdmi pll dco has been used in u-boot, add CLK_IGNORE_UNUSED |
| * to avoid disabled it which may couse exception. |
| */ |
| .flags = CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_hdmi_pll_od = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_HDMI_PLL_CNTL0, |
| .shift = 16, |
| .width = 2, |
| .flags = CLK_DIVIDER_POWER_OF_TWO, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "hdmi_pll_od", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "hdmi_pll_dco" }, |
| .num_parents = 1, |
| /* |
| * vid pll and hdmi phy share the same dco, drop |
| * CLK_SET_RATE_PARENT here, set hdmi pll dco separately. |
| */ |
| .flags = CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_hdmi_pll_od2 = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_HDMI_PLL_CNTL0, |
| .shift = 18, |
| .width = 2, |
| .flags = CLK_DIVIDER_POWER_OF_TWO, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "hdmi_pll_od2", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "hdmi_pll_od" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_hdmi_pll = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_HDMI_PLL_CNTL0, |
| .shift = 20, |
| .width = 2, |
| .flags = CLK_DIVIDER_POWER_OF_TWO, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "hdmi_pll", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "hdmi_pll_od2" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_fixed_factor g12a_fclk_div2_div = { |
| .mult = 1, |
| .div = 2, |
| .hw.init = &(struct clk_init_data){ |
| .name = "fclk_div2_div", |
| .ops = &clk_fixed_factor_ops, |
| .parent_names = (const char *[]){ "fixed_pll" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_fclk_div2 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_FIX_PLL_CNTL1, |
| .bit_idx = 24, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "fclk_div2", |
| /* |
| * Fixed clock gate should be read only, |
| * if select clk_regmap_gate_ops, the cpu clock |
| * switch to fixed clock failed due to disabling |
| * by clk_disable_unused. The same to fclk_div3, |
| * fclk_div4 and so on. |
| */ |
| .ops = &clk_regmap_gate_ro_ops, |
| .parent_names = (const char *[]){ "fclk_div2_div" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static struct clk_fixed_factor g12a_fclk_div3_div = { |
| .mult = 1, |
| .div = 3, |
| .hw.init = &(struct clk_init_data){ |
| .name = "fclk_div3_div", |
| .ops = &clk_fixed_factor_ops, |
| .parent_names = (const char *[]){ "fixed_pll" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_fclk_div3 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_FIX_PLL_CNTL1, |
| .bit_idx = 20, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "fclk_div3", |
| .ops = &clk_regmap_gate_ro_ops, |
| .parent_names = (const char *[]){ "fclk_div3_div" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static struct clk_fixed_factor g12a_fclk_div4_div = { |
| .mult = 1, |
| .div = 4, |
| .hw.init = &(struct clk_init_data){ |
| .name = "fclk_div4_div", |
| .ops = &clk_fixed_factor_ops, |
| .parent_names = (const char *[]){ "fixed_pll" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_fclk_div4 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_FIX_PLL_CNTL1, |
| .bit_idx = 21, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "fclk_div4", |
| .ops = &clk_regmap_gate_ro_ops, |
| .parent_names = (const char *[]){ "fclk_div4_div" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static struct clk_fixed_factor g12a_fclk_div5_div = { |
| .mult = 1, |
| .div = 5, |
| .hw.init = &(struct clk_init_data){ |
| .name = "fclk_div5_div", |
| .ops = &clk_fixed_factor_ops, |
| .parent_names = (const char *[]){ "fixed_pll" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_fclk_div5 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_FIX_PLL_CNTL1, |
| .bit_idx = 22, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "fclk_div5", |
| .ops = &clk_regmap_gate_ro_ops, |
| .parent_names = (const char *[]){ "fclk_div5_div" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static struct clk_fixed_factor g12a_fclk_div7_div = { |
| .mult = 1, |
| .div = 7, |
| .hw.init = &(struct clk_init_data){ |
| .name = "fclk_div7_div", |
| .ops = &clk_fixed_factor_ops, |
| .parent_names = (const char *[]){ "fixed_pll" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_fclk_div7 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_FIX_PLL_CNTL1, |
| .bit_idx = 23, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "fclk_div7", |
| .ops = &clk_regmap_gate_ro_ops, |
| .parent_names = (const char *[]){ "fclk_div7_div" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static struct clk_fixed_factor g12a_fclk_div2p5_div = { |
| .mult = 2, |
| .div = 5, |
| .hw.init = &(struct clk_init_data){ |
| .name = "fclk_div2p5_div", |
| .ops = &clk_fixed_factor_ops, |
| .parent_names = (const char *[]){ "fixed_pll" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_fclk_div2p5 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_FIX_PLL_CNTL1, |
| .bit_idx = 25, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "fclk_div2p5", |
| .ops = &clk_regmap_gate_ro_ops, |
| .parent_names = (const char *[]){ "fclk_div2p5_div" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static struct clk_fixed_factor g12a_fclk_50m_div = { |
| .mult = 1, |
| .div = 40, |
| .hw.init = &(struct clk_init_data){ |
| .name = "fclk_50m_div", |
| .ops = &clk_fixed_factor_ops, |
| .parent_names = (const char *[]){ "fixed_pll" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| /* |
| * In HHI_FIX_PLL_CNTL3 register |
| * bit5 = 0 , mpll_clk_50m = 24M |
| * bit5 = 1, mpll_clk_50m = 50M |
| * so g12a_fclk_50m should be a mux clock, |
| * not a gate clock, even though it loots like |
| * a gate clock in HIU registers Doc. |
| */ |
| static struct clk_regmap g12a_fclk_50m = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_FIX_PLL_CNTL3, |
| .mask = 0x1, |
| .shift = 5, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "fclk_50m", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = (const char *[]){ "g12a_ee_core", |
| "fclk_50m_div" }, |
| .num_parents = 2, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_mpll0_div = { |
| .data = &(struct meson_clk_mpll_data){ |
| .sdm = { |
| .reg_off = HHI_MPLL_CNTL1, |
| .shift = 0, |
| .width = 14, |
| }, |
| .sdm_en = { |
| .reg_off = HHI_MPLL_CNTL1, |
| .shift = 30, |
| .width = 1, |
| }, |
| .n2 = { |
| .reg_off = HHI_MPLL_CNTL1, |
| .shift = 20, |
| .width = 9, |
| }, |
| .ssen = { |
| .reg_off = HHI_MPLL_CNTL1, |
| .shift = 29, |
| .width = 1, |
| }, |
| .lock = &meson_clk_lock, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "mpll0_div", |
| .ops = &meson_clk_mpll_ops, |
| .parent_names = (const char *[]){ "fixed_pll" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_mpll0 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_MPLL_CNTL1, |
| .bit_idx = 31, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "mpll0", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "mpll0_div" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_mpll1_div = { |
| .data = &(struct meson_clk_mpll_data){ |
| .sdm = { |
| .reg_off = HHI_MPLL_CNTL3, |
| .shift = 0, |
| .width = 14, |
| }, |
| .sdm_en = { |
| .reg_off = HHI_MPLL_CNTL3, |
| .shift = 30, |
| .width = 1, |
| }, |
| .n2 = { |
| .reg_off = HHI_MPLL_CNTL3, |
| .shift = 20, |
| .width = 9, |
| }, |
| .ssen = { |
| .reg_off = HHI_MPLL_CNTL3, |
| .shift = 29, |
| .width = 1, |
| }, |
| .lock = &meson_clk_lock, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "mpll1_div", |
| .ops = &meson_clk_mpll_ops, |
| .parent_names = (const char *[]){ "fixed_pll" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_mpll1 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_MPLL_CNTL3, |
| .bit_idx = 31, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "mpll1", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "mpll1_div" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_mpll2_div = { |
| .data = &(struct meson_clk_mpll_data){ |
| .sdm = { |
| .reg_off = HHI_MPLL_CNTL5, |
| .shift = 0, |
| .width = 14, |
| }, |
| .sdm_en = { |
| .reg_off = HHI_MPLL_CNTL5, |
| .shift = 30, |
| .width = 1, |
| }, |
| .n2 = { |
| .reg_off = HHI_MPLL_CNTL5, |
| .shift = 20, |
| .width = 9, |
| }, |
| .ssen = { |
| .reg_off = HHI_MPLL_CNTL5, |
| .shift = 29, |
| .width = 1, |
| }, |
| .lock = &meson_clk_lock, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "mpll2_div", |
| .ops = &meson_clk_mpll_ops, |
| .parent_names = (const char *[]){ "fixed_pll" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_mpll2 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_MPLL_CNTL5, |
| .bit_idx = 31, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "mpll2", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "mpll2_div" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_mpll3_div = { |
| .data = &(struct meson_clk_mpll_data){ |
| .sdm = { |
| .reg_off = HHI_MPLL_CNTL7, |
| .shift = 0, |
| .width = 14, |
| }, |
| .sdm_en = { |
| .reg_off = HHI_MPLL_CNTL7, |
| .shift = 30, |
| .width = 1, |
| }, |
| .n2 = { |
| .reg_off = HHI_MPLL_CNTL7, |
| .shift = 20, |
| .width = 9, |
| }, |
| .ssen = { |
| .reg_off = HHI_MPLL_CNTL7, |
| .shift = 29, |
| .width = 1, |
| }, |
| .lock = &meson_clk_lock, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "mpll3_div", |
| .ops = &meson_clk_mpll_ops, |
| .parent_names = (const char *[]){ "fixed_pll" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_mpll3 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_MPLL_CNTL7, |
| .bit_idx = 31, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "mpll3", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "mpll3_div" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static const struct reg_sequence g12a_pcie_init_regs[] = { |
| { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x20090496, .delay_us = 0 }, |
| { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x30090496, .delay_us = 0 }, |
| { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x00000000, .delay_us = 0 }, |
| { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001100, .delay_us = 0 }, |
| { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x10058e00, .delay_us = 0 }, |
| { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x000100c0, .delay_us = 0 }, |
| { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000048, .delay_us = 0 }, |
| { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000068, .delay_us = 20 }, |
| { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x008100c0, .delay_us = 10 }, |
| { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x34090496, .delay_us = 0 }, |
| { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x14090496, .delay_us = 10 }, |
| { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001000, .delay_us = 0 }, |
| }; |
| |
| static int meson_clk_pcie_pll_enable(struct clk_hw *hw) |
| { |
| struct clk_regmap *clk = to_clk_regmap(hw); |
| struct meson_clk_pll_data *pll = (struct meson_clk_pll_data *)clk->data; |
| |
| if (pll->init_count) { |
| meson_parm_write(clk->map, &pll->rst, 1); |
| regmap_multi_reg_write(clk->map, pll->init_regs, |
| pll->init_count); |
| meson_parm_write(clk->map, &pll->rst, 0); |
| } |
| |
| return 0; |
| } |
| |
| static void meson_clk_pcie_pll_disable(struct clk_hw *hw) |
| { |
| struct clk_regmap *clk = to_clk_regmap(hw); |
| struct meson_clk_pll_data *pll = (struct meson_clk_pll_data *)clk->data; |
| |
| /* Put the pll is in reset */ |
| meson_parm_write(clk->map, &pll->rst, 1); |
| /* Disable the pll */ |
| meson_parm_write(clk->map, &pll->en, 0); |
| } |
| |
| const struct clk_ops meson_pcie_pll_ops = { |
| .enable = meson_clk_pcie_pll_enable, |
| .disable = meson_clk_pcie_pll_disable, |
| }; |
| |
| static struct clk_regmap g12a_pcie_pll = { |
| .data = &(struct meson_clk_pll_data){ |
| .rst = { |
| .reg_off = HHI_PCIE_PLL_CNTL0, |
| .shift = 29, |
| .width = 1, |
| }, |
| .en = { |
| .reg_off = HHI_PCIE_PLL_CNTL0, |
| .shift = 28, |
| .width = 1, |
| }, |
| .init_regs = g12a_pcie_init_regs, |
| .init_count = ARRAY_SIZE(g12a_pcie_init_regs), |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "pcie_pll", |
| .ops = &meson_pcie_pll_ops, |
| .parent_names = (const char *[]){ "g12a_ee_core" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; |
| static const char * const clk81_parent_names[] = { |
| "g12a_ee_core", "fclk_div7", "mpll1", "mpll2", "fclk_div4", |
| "fclk_div3", "fclk_div5" |
| }; |
| |
| static struct clk_regmap g12a_mpeg_clk_sel = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_MPEG_CLK_CNTL, |
| .mask = 0x7, |
| .shift = 12, |
| .table = mux_table_clk81, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "mpeg_clk_sel", |
| .ops = &clk_regmap_mux_ro_ops, |
| .parent_names = clk81_parent_names, |
| .num_parents = ARRAY_SIZE(clk81_parent_names), |
| .flags = CLK_SET_RATE_NO_REPARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_mpeg_clk_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_MPEG_CLK_CNTL, |
| .shift = 0, |
| .width = 7, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "mpeg_clk_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "mpeg_clk_sel" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_clk81 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_MPEG_CLK_CNTL, |
| .bit_idx = 7, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "clk81", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "mpeg_clk_div" }, |
| .num_parents = 1, |
| .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), |
| }, |
| }; |
| |
| static const char * const g12a_sd_emmc_clk0_parent_names[] = { |
| "g12a_ee_core", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div2p5", |
| |
| /* |
| * Following these parent clocks, we should also have had mpll2, mpll3 |
| * and gp0_pll but these clocks are too precious to be used here. All |
| * the necessary rates for MMC and NAND operation can be acheived using |
| * g12a_ee_core or fclk_div clocks |
| */ |
| }; |
| |
| /* SDIO clock */ |
| static struct clk_regmap g12a_sd_emmc_a_clk0_sel = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_SD_EMMC_CLK_CNTL, |
| .mask = 0x7, |
| .shift = 9, |
| .flags = CLK_MUX_ROUND_CLOSEST, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "sd_emmc_a_clk0_sel", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = g12a_sd_emmc_clk0_parent_names, |
| .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names), |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_sd_emmc_a_clk0_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_SD_EMMC_CLK_CNTL, |
| .shift = 0, |
| .width = 7, |
| .flags = CLK_DIVIDER_ROUND_CLOSEST, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "sd_emmc_a_clk0_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_sd_emmc_a_clk0 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_SD_EMMC_CLK_CNTL, |
| .bit_idx = 7, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "sd_emmc_a_clk0", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| /* SDcard clock */ |
| static struct clk_regmap g12a_sd_emmc_b_clk0_sel = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_SD_EMMC_CLK_CNTL, |
| .mask = 0x7, |
| .shift = 25, |
| .flags = CLK_MUX_ROUND_CLOSEST, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "sd_emmc_b_clk0_sel", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = g12a_sd_emmc_clk0_parent_names, |
| .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names), |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_sd_emmc_b_clk0_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_SD_EMMC_CLK_CNTL, |
| .shift = 16, |
| .width = 7, |
| .flags = CLK_DIVIDER_ROUND_CLOSEST, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "sd_emmc_b_clk0_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_sd_emmc_b_clk0 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_SD_EMMC_CLK_CNTL, |
| .bit_idx = 23, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "sd_emmc_b_clk0", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| /* EMMC/NAND clock */ |
| static struct clk_regmap g12a_sd_emmc_c_clk0_sel = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_NAND_CLK_CNTL, |
| .mask = 0x7, |
| .shift = 9, |
| .flags = CLK_MUX_ROUND_CLOSEST, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "sd_emmc_c_clk0_sel", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = g12a_sd_emmc_clk0_parent_names, |
| .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names), |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_sd_emmc_c_clk0_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_NAND_CLK_CNTL, |
| .shift = 0, |
| .width = 7, |
| .flags = CLK_DIVIDER_ROUND_CLOSEST, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "sd_emmc_c_clk0_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_sd_emmc_c_clk0 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_NAND_CLK_CNTL, |
| .bit_idx = 7, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "sd_emmc_c_clk0", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| /* temperature sensor clock */ |
| static struct clk_regmap g12a_ts_clk_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_TS_CLK_CNTL, |
| .shift = 0, |
| .width = 8, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "ts_clk_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "g12a_ee_core" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_ts_clk = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_TS_CLK_CNTL, |
| .bit_idx = 8, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "ts_clk", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "ts_clk_div" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| /* spicc0/spicc1 clock */ |
| static const char * const spicc_parent_names[] = { "g12a_ee_core", |
| "clk81", "fclk_div4", "fclk_div3", "fclk_div2", "fclk_div5", |
| "fclk_div7", "gp0_pll" }; |
| |
| static struct clk_regmap g12a_spicc0_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_SPICC_CLK_CNTL, |
| .mask = 0x7, |
| .shift = 7, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "spicc0_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = spicc_parent_names, |
| .num_parents = ARRAY_SIZE(spicc_parent_names), |
| .flags = CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_spicc0_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_SPICC_CLK_CNTL, |
| .shift = 0, |
| .width = 6, |
| .flags = CLK_DIVIDER_ROUND_CLOSEST, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "spicc0_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "spicc0_mux" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_spicc0_gate = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_SPICC_CLK_CNTL, |
| .bit_idx = 6, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "spicc0_gate", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "spicc0_div" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_spicc1_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_SPICC_CLK_CNTL, |
| .mask = 0x7, |
| .shift = 23, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "spicc1_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = spicc_parent_names, |
| .num_parents = ARRAY_SIZE(spicc_parent_names), |
| .flags = CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_spicc1_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_SPICC_CLK_CNTL, |
| .shift = 16, |
| .width = 6, |
| .flags = CLK_DIVIDER_ROUND_CLOSEST, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "spicc1_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "spicc1_mux" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_spicc1_gate = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_SPICC_CLK_CNTL, |
| .bit_idx = 22, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "spicc1_gate", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "spicc1_div" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| /* gpu clocks */ |
| const char *g12a_gpu_parent_names[] = { "xtal", "gp0_pll", "hifi_pll", |
| "fclk_div2p5", "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7"}; |
| |
| static struct clk_regmap g12a_gpu_p0_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_MALI_CLK_CNTL, |
| .mask = 0x7, |
| .shift = 9, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "gpu_p0_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = g12a_gpu_parent_names, |
| .num_parents = ARRAY_SIZE(g12a_gpu_parent_names), |
| .flags = CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_gpu_p0_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_MALI_CLK_CNTL, |
| .shift = 0, |
| .width = 7, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "gpu_p0_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "gpu_p0_mux" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_gpu_p0_gate = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_MALI_CLK_CNTL, |
| .bit_idx = 8, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "gpu_p0_gate", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "gpu_p0_div" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_gpu_p1_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_MALI_CLK_CNTL, |
| .mask = 0x7, |
| .shift = 25, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "gpu_p1_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = g12a_gpu_parent_names, |
| .num_parents = ARRAY_SIZE(g12a_gpu_parent_names), |
| .flags = CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_gpu_p1_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_MALI_CLK_CNTL, |
| .shift = 16, |
| .width = 7, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "gpu_p1_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "gpu_p1_mux" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_gpu_p1_gate = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_MALI_CLK_CNTL, |
| .bit_idx = 24, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "gpu_p1_gate", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "gpu_p1_div" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_gpu_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_MALI_CLK_CNTL, |
| .mask = 0x1, |
| .shift = 31, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "gpu_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = (const char *[]){ "gpu_p0_gate", |
| "gpu_p1_gate"}, |
| .num_parents = 2, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_UNGATE | |
| CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| /* |
| * media clocks |
| */ |
| /* vdin_meas_clk */ |
| const char *g12a_meas_parent_names[] = { "g12a_ee_core", "fclk_div4", |
| "fclk_div3", "fclk_div5", "vid_pll", "gp0_pll", "fclk_div2", "fclk_div7" }; |
| static struct clk_regmap g12a_dsi_meas_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VDIN_MEAS_CLK_CNTL, |
| .mask = 0x7, |
| .shift = 21, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "dsi_meas_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = g12a_meas_parent_names, |
| .num_parents = ARRAY_SIZE(g12a_meas_parent_names), |
| .flags = CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_dsi_meas_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_VDIN_MEAS_CLK_CNTL, |
| .shift = 12, |
| .width = 7, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "dsi_meas_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "dsi_meas_mux" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_dsi_meas = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VDIN_MEAS_CLK_CNTL, |
| .bit_idx = 20, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "dsi_meas", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "dsi_meas_div" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| /* cts_vdec_clk */ |
| const char *g12a_dec_parent_names[] = { "fclk_div2p5", "fclk_div3", |
| "fclk_div4", "fclk_div5", "fclk_div7", "hifi_pll", "gp0_pll", "xtal"}; |
| |
| static struct clk_regmap g12a_vdec_p0_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VDEC_CLK_CNTL, |
| .mask = 0x7, |
| .shift = 9, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vdec_p0_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = g12a_dec_parent_names, |
| .num_parents = ARRAY_SIZE(g12a_dec_parent_names), |
| .flags = CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vdec_p0_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_VDEC_CLK_CNTL, |
| .shift = 0, |
| .width = 7, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vdec_p0_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "vdec_p0_mux" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vdec_p0 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VDEC_CLK_CNTL, |
| .bit_idx = 8, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "vdec_p0", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "vdec_p0_div" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vdec_p1_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VDEC3_CLK_CNTL, |
| .mask = 0x7, |
| .shift = 9, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vdec_p1_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = g12a_dec_parent_names, |
| .num_parents = ARRAY_SIZE(g12a_dec_parent_names), |
| .flags = CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vdec_p1_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_VDEC3_CLK_CNTL, |
| .shift = 0, |
| .width = 7, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vdec_p1_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "vdec_p1_mux" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vdec_p1 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VDEC3_CLK_CNTL, |
| .bit_idx = 8, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "vdec_p1", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "vdec_p1_div" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vdec_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VDEC3_CLK_CNTL, |
| .mask = 0x1, |
| .shift = 15, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vdec_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = (const char *[]){ "vdec_p0", |
| "vdec_p1"}, |
| .num_parents = 2, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| /* cts_hcodec_clk */ |
| static struct clk_regmap g12a_hcodec_p0_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VDEC_CLK_CNTL, |
| .mask = 0x7, |
| .shift = 25, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "hcodec_p0_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = g12a_dec_parent_names, |
| .num_parents = ARRAY_SIZE(g12a_dec_parent_names), |
| .flags = CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_hcodec_p0_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_VDEC_CLK_CNTL, |
| .shift = 16, |
| .width = 7, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "hcodec_p0_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "hcodec_p0_mux" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_hcodec_p0 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VDEC_CLK_CNTL, |
| .bit_idx = 24, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "hcodec_p0", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "hcodec_p0_div" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_hcodec_p1_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VDEC3_CLK_CNTL, |
| .mask = 0x7, |
| .shift = 25, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "hcodec_p1_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = g12a_dec_parent_names, |
| .num_parents = ARRAY_SIZE(g12a_dec_parent_names), |
| .flags = CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_hcodec_p1_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_VDEC3_CLK_CNTL, |
| .shift = 16, |
| .width = 7, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "hcodec_p1_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "hcodec_p1_mux" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_hcodec_p1 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VDEC3_CLK_CNTL, |
| .bit_idx = 24, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "hcodec_p1", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "hcodec_p1_div" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_hcodec_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VDEC3_CLK_CNTL, |
| .mask = 0x1, |
| .shift = 31, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "hcodec_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = (const char *[]){ "hcodec_p0", |
| "hcodec_p1"}, |
| .num_parents = 2, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| /* cts_hevcb_clk */ |
| static struct clk_regmap g12a_hevc_p0_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VDEC2_CLK_CNTL, |
| .mask = 0x7, |
| .shift = 25, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "hevc_p0_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = g12a_dec_parent_names, |
| .num_parents = ARRAY_SIZE(g12a_dec_parent_names), |
| .flags = CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_hevc_p0_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_VDEC2_CLK_CNTL, |
| .shift = 16, |
| .width = 7, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "hevc_p0_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "hevc_p0_mux" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_hevc_p0 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VDEC2_CLK_CNTL, |
| .bit_idx = 24, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "hevc_p0", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "hevc_p0_div" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_hevc_p1_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VDEC4_CLK_CNTL, |
| .mask = 0x7, |
| .shift = 25, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "hevc_p1_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = g12a_dec_parent_names, |
| .num_parents = ARRAY_SIZE(g12a_dec_parent_names), |
| .flags = CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_hevc_p1_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_VDEC4_CLK_CNTL, |
| .shift = 16, |
| .width = 7, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "hevc_p1_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "hevc_p1_mux" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_hevc_p1 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VDEC4_CLK_CNTL, |
| .bit_idx = 24, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "hevc_p1", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "hevc_p1_div" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_hevc_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VDEC4_CLK_CNTL, |
| .mask = 0x1, |
| .shift = 31, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "hevc_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = (const char *[]){ "hevc_p0", |
| "hevc_p1"}, |
| .num_parents = 2, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| /* cts_hevcf_clk */ |
| static struct clk_regmap g12a_hevcf_p0_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VDEC2_CLK_CNTL, |
| .mask = 0x7, |
| .shift = 9, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "hevcf_p0_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = g12a_dec_parent_names, |
| .num_parents = ARRAY_SIZE(g12a_dec_parent_names), |
| .flags = CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_hevcf_p0_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_VDEC2_CLK_CNTL, |
| .shift = 0, |
| .width = 7, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "hevcf_p0_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "hevcf_p0_mux" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_hevcf_p0 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VDEC2_CLK_CNTL, |
| .bit_idx = 8, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "hevcf_p0", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "hevcf_p0_div" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_hevcf_p1_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VDEC4_CLK_CNTL, |
| .mask = 0x7, |
| .shift = 9, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "hevcf_p1_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = g12a_dec_parent_names, |
| .num_parents = ARRAY_SIZE(g12a_dec_parent_names), |
| .flags = CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_hevcf_p1_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_VDEC4_CLK_CNTL, |
| .shift = 0, |
| .width = 7, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "hevcf_p1_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "hevcf_p1_mux" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_hevcf_p1 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VDEC4_CLK_CNTL, |
| .bit_idx = 8, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "hevcf_p1", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "hevcf_p1_div" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_hevcf_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VDEC4_CLK_CNTL, |
| .mask = 0x1, |
| .shift = 15, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "hevcf_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = (const char *[]){ "hevcf_p0", |
| "hevcf_p1"}, |
| .num_parents = 2, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| /* cts_vpu_clk */ |
| static const char * const vpu_parent_names[] = { "fclk_div3", |
| "fclk_div4", "fclk_div5", "fclk_div7", "mp1l0", "vid_pll", |
| "hifi_pll", "gp0_pll"}; |
| |
| static struct clk_regmap g12a_vpu_p0_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VPU_CLK_CNTL, |
| .mask = 0x7, |
| .shift = 9, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vpu_p0_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = vpu_parent_names, |
| .num_parents = ARRAY_SIZE(vpu_parent_names), |
| .flags = CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vpu_p0_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_VPU_CLK_CNTL, |
| .shift = 0, |
| .width = 7, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vpu_p0_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "vpu_p0_mux" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vpu_p0 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VPU_CLK_CNTL, |
| .bit_idx = 8, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "vpu_p0", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "vpu_p0_div" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vpu_p1_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VPU_CLK_CNTL, |
| .mask = 0x7, |
| .shift = 25, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vpu_p1_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = vpu_parent_names, |
| .num_parents = ARRAY_SIZE(vpu_parent_names), |
| .flags = CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vpu_p1_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_VPU_CLK_CNTL, |
| .shift = 16, |
| .width = 7, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vpu_p1_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "vpu_p1_mux" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vpu_p1 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VPU_CLK_CNTL, |
| .bit_idx = 24, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "vpu_p1", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "vpu_p1_div" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vpu_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VPU_CLK_CNTL, |
| .mask = 0x1, |
| .shift = 31, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vpu_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = (const char *[]){ "vpu_p0", "vpu_p1" }, |
| .num_parents = 2, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| /* cts_vapbclk */ |
| static const char * const vapb_parent_names[] = { "fclk_div4", |
| "fclk_div3", "fclk_div5", "fclk_div7", "mpll1", "vid_pll", |
| "mpll2", "fclk_div2p5"}; |
| |
| static struct clk_regmap g12a_vapb_p0_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VAPBCLK_CNTL, |
| .mask = 0x7, |
| .shift = 9, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vapb_p0_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = vapb_parent_names, |
| .num_parents = ARRAY_SIZE(vapb_parent_names), |
| .flags = CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vapb_p0_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_VAPBCLK_CNTL, |
| .shift = 0, |
| .width = 7, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vpu_vapb_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "vpu_vapb_mux" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vapb_p0 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VAPBCLK_CNTL, |
| .bit_idx = 8, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "vapb_p0", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "vapb_p0_div" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vapb_p1_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VAPBCLK_CNTL, |
| .mask = 0x7, |
| .shift = 25, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vapb_p1_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = vpu_parent_names, |
| .num_parents = ARRAY_SIZE(vpu_parent_names), |
| .flags = CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vapb_p1_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_VAPBCLK_CNTL, |
| .shift = 16, |
| .width = 7, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vapb_p1_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "vapb_p1_mux" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vapb_p1 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VAPBCLK_CNTL, |
| .bit_idx = 24, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "vapb_p1", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "vapb_p1_div" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vapb_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VAPBCLK_CNTL, |
| .mask = 0x1, |
| .shift = 31, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vapb_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = (const char *[]){ "vapb_p0", "vapb_p1" }, |
| .num_parents = 2, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_ge2d_gate = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VAPBCLK_CNTL, |
| .bit_idx = 30, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "ge2d_gate", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "vapb_mux" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| /* vpu_clkb_tmp */ |
| static const char * const vpu_clkb_tmp_parent_names[] = { "vpu_mux", |
| "fclk_div4", "fclk_div5", "fclk_div7"}; |
| |
| static struct clk_regmap g12a_vpu_clkb_tmp_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VPU_CLKB_CNTL, |
| .mask = 0x3, |
| .shift = 20, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vpu_clkb_tmp_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = vpu_clkb_tmp_parent_names, |
| .num_parents = ARRAY_SIZE(vpu_clkb_tmp_parent_names), |
| .flags = CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vpu_clkb_tmp_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_VPU_CLKB_CNTL, |
| .shift = 16, |
| .width = 4, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vpu_clkb_tmp_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "vpu_clkb_tmp_mux" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vpu_clkb_tmp = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VPU_CLKB_CNTL, |
| .bit_idx = 24, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "vpu_clkb_tmp", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "vpu_clkb_tmp_div" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vpu_clkb_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_VPU_CLKB_CNTL, |
| .shift = 0, |
| .width = 8, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vpu_clkb_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "vpu_clkb_tmp" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vpu_clkb = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VPU_CLKB_CNTL, |
| .bit_idx = 8, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "vpu_clkb", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "vpu_clkb_div" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| /* cts_vpu_clkc */ |
| static const char * const vpu_clkc_parent_names[] = { "fclk_div4", |
| "fclk_div3", "fclk_div5", "fclk_div7", "mpll1", "vid_pll", |
| "mpll2", "gp0_pll"}; |
| |
| static struct clk_regmap g12a_vpu_clkc_p0_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VPU_CLKC_CNTL, |
| .mask = 0x7, |
| .shift = 9, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vpu_clkc_p0_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = vpu_clkc_parent_names, |
| .num_parents = ARRAY_SIZE(vpu_clkc_parent_names), |
| .flags = CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vpu_clkc_p0_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_VPU_CLKC_CNTL, |
| .shift = 0, |
| .width = 7, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vpu_clkc_p0_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "vpu_clkc_p0_mux" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vpu_clkc_p0 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VPU_CLKC_CNTL, |
| .bit_idx = 8, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "vpu_clkc_p0", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "vpu_clkc_p0_div" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vpu_clkc_p1_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VPU_CLKC_CNTL, |
| .mask = 0x7, |
| .shift = 25, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vpu_clkc_p1_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = vpu_parent_names, |
| .num_parents = ARRAY_SIZE(vpu_parent_names), |
| .flags = CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vpu_clkc_p1_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_VPU_CLKC_CNTL, |
| .shift = 16, |
| .width = 7, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vpu_clkc_p1_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "vpu_clkc_p1_mux" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vpu_clkc_p1 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VPU_CLKC_CNTL, |
| .bit_idx = 24, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "vpu_clkc_p1", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "vpu_clkc_p1_div" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vpu_clkc_mux = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VPU_CLKC_CNTL, |
| .mask = 0x1, |
| .shift = 31, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vpu_clkc_mux", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = (const char *[]){ "vpu_clkc_p0", |
| "vpu_clkc_p1" }, |
| .num_parents = 2, |
| .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static u32 cpu_fixed_source_sel_table[] = { 0, 1, 2 }; |
| static const char * const cpu_fixed_source_sel_parent_names[] = { |
| "g12a_ee_core", "fclk_div2", "fclk_div3" |
| }; |
| |
| /* cpu_fixed_sel0 */ |
| static struct clk_regmap g12a_cpu_fixed_source_sel0 = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_SYS_CPU_CLK_CNTL0, |
| .mask = 0x3, |
| .shift = 0, |
| .table = cpu_fixed_source_sel_table, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "cpu_fixed_source_sel0", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = cpu_fixed_source_sel_parent_names, |
| .num_parents = ARRAY_SIZE(cpu_fixed_source_sel_parent_names), |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_cpu_fixed_source_div0 = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_SYS_CPU_CLK_CNTL0, |
| .shift = 4, |
| .width = 6, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "cpu_fixed_source_div0", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "cpu_fixed_source_sel0" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_cpu_fixed_sel0 = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_SYS_CPU_CLK_CNTL0, |
| .mask = 0x1, |
| .shift = 2, |
| .table = cpu_fixed_source_sel_table, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "cpu_fixed_sel0", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = (const char *[]){ "cpu_fixed_source_sel0", |
| "cpu_fixed_source_div0" }, |
| .num_parents = 2, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| /* cpu_fixed_sel1 */ |
| static struct clk_regmap g12a_cpu_fixed_source_sel1 = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_SYS_CPU_CLK_CNTL0, |
| .mask = 0x3, |
| .shift = 16, |
| .table = cpu_fixed_source_sel_table, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "cpu_fixed_source_sel1", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = cpu_fixed_source_sel_parent_names, |
| .num_parents = ARRAY_SIZE(cpu_fixed_source_sel_parent_names), |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_cpu_fixed_source_div1 = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_SYS_CPU_CLK_CNTL0, |
| .shift = 20, |
| .width = 6, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "cpu_fixed_source_div1", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "cpu_fixed_source_sel1" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_cpu_fixed_sel1 = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_SYS_CPU_CLK_CNTL0, |
| .mask = 0x1, |
| .shift = 18, |
| .table = cpu_fixed_source_sel_table, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "cpu_fixed_sel1", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = (const char *[]){ "cpu_fixed_source_sel1", |
| "cpu_fixed_source_div1" }, |
| .num_parents = 2, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| /* cpu_fixed_clk */ |
| static struct clk_regmap g12a_cpu_fixed_clk = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_SYS_CPU_CLK_CNTL0, |
| .mask = 0x1, |
| .shift = 10, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "cpu_fixed_clk", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = (const char *[]){ "cpu_fixed_sel0", |
| "cpu_fixed_sel1" }, |
| .num_parents = 2, |
| .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, |
| }, |
| }; |
| |
| /* cpu clocks */ |
| /* cpu_fixed_clk |\ |
| *---------------| \ cts_cpu_clk |
| * sys_pll | |-------- |
| *---------------| / |
| * |/ |
| */ |
| |
| static struct clk_regmap g12a_cpu_clk = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_SYS_CPU_CLK_CNTL0, |
| .mask = 0x1, |
| .shift = 11, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "cpu_clk", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = (const char *[]){ "cpu_fixed_clk", "sys_pll" }, |
| .num_parents = 2, |
| .flags = CLK_SET_RATE_PARENT, |
| }, |
| }; |
| |
| /* Video Clocks */ |
| |
| static struct clk_regmap g12a_vid_pll_div = { |
| .data = &(struct meson_vid_pll_div_data){ |
| .val = { |
| .reg_off = HHI_VID_PLL_CLK_DIV, |
| .shift = 0, |
| .width = 15, |
| }, |
| .sel = { |
| .reg_off = HHI_VID_PLL_CLK_DIV, |
| .shift = 16, |
| .width = 2, |
| }, |
| .set = { |
| .reg_off = HHI_VID_PLL_CLK_DIV, |
| .shift = 15, |
| .width = 1, |
| }, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vid_pll_div", |
| .ops = &meson_vid_pll_div_ops, |
| .parent_names = (const char *[]){ "hdmi_pll" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static const char * const g12a_vid_pll_parent_names[] = { "vid_pll_div", |
| "hdmi_pll" }; |
| |
| static struct clk_regmap g12a_vid_pll_sel = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VID_PLL_CLK_DIV, |
| .mask = 0x1, |
| .shift = 18, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "vid_pll_sel", |
| .ops = &clk_regmap_mux_ops, |
| /* |
| * bit 18 selects from 2 possible parents: |
| * vid_pll_div or hdmi_pll |
| */ |
| .parent_names = g12a_vid_pll_parent_names, |
| .num_parents = ARRAY_SIZE(g12a_vid_pll_parent_names), |
| .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vid_pll = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VID_PLL_CLK_DIV, |
| .bit_idx = 19, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vid_pll", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "vid_pll_sel" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, |
| }, |
| }; |
| |
| static const char * const g12a_vclk_parent_names[] = { |
| "vid_pll", "gp0_pll", "hifi_pll", "mpll1", "fclk_div3", "fclk_div4", |
| "fclk_div5", "fclk_div7" |
| }; |
| |
| static struct clk_regmap g12a_vclk_sel = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VID_CLK_CNTL, |
| .mask = 0x7, |
| .shift = 16, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "vclk_sel", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = g12a_vclk_parent_names, |
| .num_parents = ARRAY_SIZE(g12a_vclk_parent_names), |
| .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vclk2_sel = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VIID_CLK_CNTL, |
| .mask = 0x7, |
| .shift = 16, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "vclk2_sel", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = g12a_vclk_parent_names, |
| .num_parents = ARRAY_SIZE(g12a_vclk_parent_names), |
| .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vclk_input = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VID_CLK_DIV, |
| .bit_idx = 16, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vclk_input", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "vclk_sel" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vclk2_input = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VIID_CLK_DIV, |
| .bit_idx = 16, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vclk2_input", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "vclk2_sel" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vclk_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_VID_CLK_DIV, |
| .shift = 0, |
| .width = 8, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "vclk_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "vclk_input" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vclk2_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_VIID_CLK_DIV, |
| .shift = 0, |
| .width = 8, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "vclk2_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "vclk2_input" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vclk = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VID_CLK_CNTL, |
| .bit_idx = 19, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vclk", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "vclk_div" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vclk2 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VIID_CLK_CNTL, |
| .bit_idx = 19, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vclk2", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "vclk2_div" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vclk_div1 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VID_CLK_CNTL, |
| .bit_idx = 0, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vclk_div1", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "vclk" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vclk_div2_en = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VID_CLK_CNTL, |
| .bit_idx = 1, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vclk_div2_en", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "vclk" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vclk_div4_en = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VID_CLK_CNTL, |
| .bit_idx = 2, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vclk_div4_en", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "vclk" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vclk_div6_en = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VID_CLK_CNTL, |
| .bit_idx = 3, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vclk_div6_en", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "vclk" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vclk_div12_en = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VID_CLK_CNTL, |
| .bit_idx = 4, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vclk_div12_en", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "vclk" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vclk2_div1 = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VIID_CLK_CNTL, |
| .bit_idx = 0, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vclk2_div1", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "vclk2" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vclk2_div2_en = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VIID_CLK_CNTL, |
| .bit_idx = 1, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vclk2_div2_en", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "vclk2" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vclk2_div4_en = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VIID_CLK_CNTL, |
| .bit_idx = 2, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vclk2_div4_en", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "vclk2" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vclk2_div6_en = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VIID_CLK_CNTL, |
| .bit_idx = 3, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vclk2_div6_en", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "vclk2" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_vclk2_div12_en = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VIID_CLK_CNTL, |
| .bit_idx = 4, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "vclk2_div12_en", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "vclk2" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, |
| }, |
| }; |
| |
| static struct clk_fixed_factor g12a_vclk_div2 = { |
| .mult = 1, |
| .div = 2, |
| .hw.init = &(struct clk_init_data){ |
| .name = "vclk_div2", |
| .ops = &clk_fixed_factor_ops, |
| .parent_names = (const char *[]){ "vclk_div2_en" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static struct clk_fixed_factor g12a_vclk_div4 = { |
| .mult = 1, |
| .div = 4, |
| .hw.init = &(struct clk_init_data){ |
| .name = "vclk_div4", |
| .ops = &clk_fixed_factor_ops, |
| .parent_names = (const char *[]){ "vclk_div4_en" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static struct clk_fixed_factor g12a_vclk_div6 = { |
| .mult = 1, |
| .div = 6, |
| .hw.init = &(struct clk_init_data){ |
| .name = "vclk_div6", |
| .ops = &clk_fixed_factor_ops, |
| .parent_names = (const char *[]){ "vclk_div6_en" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static struct clk_fixed_factor g12a_vclk_div12 = { |
| .mult = 1, |
| .div = 12, |
| .hw.init = &(struct clk_init_data){ |
| .name = "vclk_div12", |
| .ops = &clk_fixed_factor_ops, |
| .parent_names = (const char *[]){ "vclk_div12_en" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static struct clk_fixed_factor g12a_vclk2_div2 = { |
| .mult = 1, |
| .div = 2, |
| .hw.init = &(struct clk_init_data){ |
| .name = "vclk2_div2", |
| .ops = &clk_fixed_factor_ops, |
| .parent_names = (const char *[]){ "vclk2_div2_en" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static struct clk_fixed_factor g12a_vclk2_div4 = { |
| .mult = 1, |
| .div = 4, |
| .hw.init = &(struct clk_init_data){ |
| .name = "vclk2_div4", |
| .ops = &clk_fixed_factor_ops, |
| .parent_names = (const char *[]){ "vclk2_div4_en" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static struct clk_fixed_factor g12a_vclk2_div6 = { |
| .mult = 1, |
| .div = 6, |
| .hw.init = &(struct clk_init_data){ |
| .name = "vclk2_div6", |
| .ops = &clk_fixed_factor_ops, |
| .parent_names = (const char *[]){ "vclk2_div6_en" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static struct clk_fixed_factor g12a_vclk2_div12 = { |
| .mult = 1, |
| .div = 12, |
| .hw.init = &(struct clk_init_data){ |
| .name = "vclk2_div12", |
| .ops = &clk_fixed_factor_ops, |
| .parent_names = (const char *[]){ "vclk2_div12_en" }, |
| .num_parents = 1, |
| }, |
| }; |
| |
| static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; |
| static const char * const g12a_cts_parent_names[] = { |
| "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6", |
| "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4", |
| "vclk2_div6", "vclk2_div12" |
| }; |
| |
| static struct clk_regmap g12a_cts_enci_sel = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VID_CLK_DIV, |
| .mask = 0xf, |
| .shift = 28, |
| .table = mux_table_cts_sel, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "cts_enci_sel", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = g12a_cts_parent_names, |
| .num_parents = ARRAY_SIZE(g12a_cts_parent_names), |
| .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_cts_encl_sel = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VIID_CLK_DIV, |
| .mask = 0xf, |
| .shift = 12, |
| .table = mux_table_cts_sel, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "cts_encl_sel", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = g12a_cts_parent_names, |
| .num_parents = ARRAY_SIZE(g12a_cts_parent_names), |
| .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_cts_encp_sel = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VID_CLK_DIV, |
| .mask = 0xf, |
| .shift = 20, |
| .table = mux_table_cts_sel, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "cts_encp_sel", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = g12a_cts_parent_names, |
| .num_parents = ARRAY_SIZE(g12a_cts_parent_names), |
| .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_cts_vdac_sel = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_VIID_CLK_DIV, |
| .mask = 0xf, |
| .shift = 28, |
| .table = mux_table_cts_sel, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "cts_vdac_sel", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = g12a_cts_parent_names, |
| .num_parents = ARRAY_SIZE(g12a_cts_parent_names), |
| .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| /* TOFIX: add support for cts_tcon */ |
| static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; |
| static const char * const g12a_cts_hdmi_tx_parent_names[] = { |
| "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6", |
| "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4", |
| "vclk2_div6", "vclk2_div12" |
| }; |
| |
| static struct clk_regmap g12a_hdmi_tx_sel = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_HDMI_CLK_CNTL, |
| .mask = 0xf, |
| .shift = 16, |
| .table = mux_table_hdmi_tx_sel, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "hdmi_tx_sel", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = g12a_cts_hdmi_tx_parent_names, |
| .num_parents = ARRAY_SIZE(g12a_cts_hdmi_tx_parent_names), |
| .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_cts_enci = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VID_CLK_CNTL2, |
| .bit_idx = 0, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "cts_enci", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "cts_enci_sel" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_cts_encl = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VID_CLK_CNTL2, |
| .bit_idx = 3, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "cts_encl", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "cts_encl_sel" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_cts_encp = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VID_CLK_CNTL2, |
| .bit_idx = 2, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "cts_encp", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "cts_encp_sel" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_cts_vdac = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VID_CLK_CNTL2, |
| .bit_idx = 4, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "cts_vdac", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "cts_vdac_sel" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_hdmi_tx = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_VID_CLK_CNTL2, |
| .bit_idx = 5, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "hdmi_tx", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "hdmi_tx_sel" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, |
| }, |
| }; |
| |
| /* HDMI Clocks */ |
| |
| static const char * const g12a_hdmi_parent_names[] = { |
| "g12a_ee_core", "fclk_div4", "fclk_div3", "fclk_div5" |
| }; |
| |
| static struct clk_regmap g12a_hdmi_sel = { |
| .data = &(struct clk_regmap_mux_data){ |
| .offset = HHI_HDMI_CLK_CNTL, |
| .mask = 0x3, |
| .shift = 9, |
| .flags = CLK_MUX_ROUND_CLOSEST, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "hdmi_sel", |
| .ops = &clk_regmap_mux_ops, |
| .parent_names = g12a_hdmi_parent_names, |
| .num_parents = ARRAY_SIZE(g12a_hdmi_parent_names), |
| .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_hdmi_div = { |
| .data = &(struct clk_regmap_div_data){ |
| .offset = HHI_HDMI_CLK_CNTL, |
| .shift = 0, |
| .width = 7, |
| }, |
| .hw.init = &(struct clk_init_data){ |
| .name = "hdmi_div", |
| .ops = &clk_regmap_divider_ops, |
| .parent_names = (const char *[]){ "hdmi_sel" }, |
| .num_parents = 1, |
| .flags = CLK_GET_RATE_NOCACHE, |
| }, |
| }; |
| |
| static struct clk_regmap g12a_hdmi = { |
| .data = &(struct clk_regmap_gate_data){ |
| .offset = HHI_HDMI_CLK_CNTL, |
| .bit_idx = 8, |
| }, |
| .hw.init = &(struct clk_init_data) { |
| .name = "hdmi", |
| .ops = &clk_regmap_gate_ops, |
| .parent_names = (const char *[]){ "hdmi_div" }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, |
| }, |
| }; |
| |
| /* Everything Else (EE) domain gates */ |
| static MESON_GATE(g12a_ddr, HHI_GCLK_MPEG0, 0); |
| static MESON_GATE(g12a_dos, HHI_GCLK_MPEG0, 1); |
| static MESON_GATE(g12a_audio_locker, HHI_GCLK_MPEG0, 2); |
| static MESON_GATE(g12a_mipi_dsi_host, HHI_GCLK_MPEG0, 3); |
| static MESON_GATE(g12a_eth_phy, HHI_GCLK_MPEG0, 4); |
| static MESON_GATE(g12a_isa, HHI_GCLK_MPEG0, 5); |
| static MESON_GATE(g12a_pl301, HHI_GCLK_MPEG0, 6); |
| static MESON_GATE(g12a_periphs, HHI_GCLK_MPEG0, 7); |
| static MESON_GATE(g12a_spicc_0, HHI_GCLK_MPEG0, 8); |
| static MESON_GATE(g12a_i2c, HHI_GCLK_MPEG0, 9); |
| static MESON_GATE(g12a_sana, HHI_GCLK_MPEG0, 10); |
| static MESON_GATE(g12a_sd, HHI_GCLK_MPEG0, 11); |
| static MESON_GATE(g12a_rng0, HHI_GCLK_MPEG0, 12); |
| static MESON_GATE(g12a_uart0, HHI_GCLK_MPEG0, 13); |
| static MESON_GATE(g12a_spicc_1, HHI_GCLK_MPEG0, 14); |
| static MESON_GATE(g12a_hiu_reg, HHI_GCLK_MPEG0, 19); |
| static MESON_GATE(g12a_mipi_dsi_phy, HHI_GCLK_MPEG0, 20); |
| static MESON_GATE(g12a_assist_misc, HHI_GCLK_MPEG0, 23); |
| static MESON_GATE(g12a_emmc_a, HHI_GCLK_MPEG0, 4); |
| static MESON_GATE(g12a_emmc_b, HHI_GCLK_MPEG0, 25); |
| static MESON_GATE(g12a_emmc_c, HHI_GCLK_MPEG0, 26); |
| static MESON_GATE(g12a_audio_codec, HHI_GCLK_MPEG0, 28); |
| |
| static MESON_GATE(g12a_audio, HHI_GCLK_MPEG1, 0); |
| static MESON_GATE(g12a_eth_core, HHI_GCLK_MPEG1, 3); |
| static MESON_GATE(g12a_demux, HHI_GCLK_MPEG1, 4); |
| static MESON_GATE(g12a_audio_ififo, HHI_GCLK_MPEG1, 11); |
| static MESON_GATE(g12a_adc, HHI_GCLK_MPEG1, 13); |
| static MESON_GATE(g12a_uart1, HHI_GCLK_MPEG1, 16); |
| static MESON_GATE(g12a_g2d, HHI_GCLK_MPEG1, 20); |
| static MESON_GATE(g12a_reset, HHI_GCLK_MPEG1, 23); |
| static MESON_GATE(g12a_pcie_comb, HHI_GCLK_MPEG1, 24); |
| static MESON_GATE(g12a_parser, HHI_GCLK_MPEG1, 25); |
| static MESON_GATE(g12a_usb_general, HHI_GCLK_MPEG1, 26); |
| static MESON_GATE(g12a_pcie_phy, HHI_GCLK_MPEG1, 27); |
| static MESON_GATE(g12a_ahb_arb0, HHI_GCLK_MPEG1, 29); |
| |
| static MESON_GATE(g12a_ahb_data_bus, HHI_GCLK_MPEG2, 1); |
| static MESON_GATE(g12a_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); |
| static MESON_GATE(g12a_htx_hdcp22, HHI_GCLK_MPEG2, 3); |
| static MESON_GATE(g12a_htx_pclk, HHI_GCLK_MPEG2, 4); |
| static MESON_GATE(g12a_bt656, HHI_GCLK_MPEG2, 6); |
| static MESON_GATE(g12a_usb1_to_ddr, HHI_GCLK_MPEG2, 8); |
| static MESON_GATE(g12a_mmc_pclk, HHI_GCLK_MPEG2, 11); |
| static MESON_GATE(g12a_uart2, HHI_GCLK_MPEG2, 15); |
| static MESON_GATE(g12a_vpu_intr, HHI_GCLK_MPEG2, 25); |
| static MESON_GATE(g12a_gic, HHI_GCLK_MPEG2, 30); |
| |
| static MESON_GATE(g12a_vclk2_venci0, HHI_GCLK_OTHER, 1); |
| static MESON_GATE(g12a_vclk2_venci1, HHI_GCLK_OTHER, 2); |
| static MESON_GATE(g12a_vclk2_vencp0, HHI_GCLK_OTHER, 3); |
| static MESON_GATE(g12a_vclk2_vencp1, HHI_GCLK_OTHER, 4); |
| static MESON_GATE(g12a_vclk2_venct0, HHI_GCLK_OTHER, 5); |
| static MESON_GATE(g12a_vclk2_venct1, HHI_GCLK_OTHER, 6); |
| static MESON_GATE(g12a_vclk2_other, HHI_GCLK_OTHER, 7); |
| static MESON_GATE(g12a_vclk2_enci, HHI_GCLK_OTHER, 8); |
| static MESON_GATE(g12a_vclk2_encp, HHI_GCLK_OTHER, 9); |
| static MESON_GATE(g12a_dac_clk, HHI_GCLK_OTHER, 10); |
| static MESON_GATE(g12a_aoclk_gate, HHI_GCLK_OTHER, 14); |
| static MESON_GATE(g12a_iec958_gate, HHI_GCLK_OTHER, 16); |
| static MESON_GATE(g12a_enc480p, HHI_GCLK_OTHER, 20); |
| static MESON_GATE(g12a_rng1, HHI_GCLK_OTHER, 21); |
| static MESON_GATE(g12a_vclk2_enct, HHI_GCLK_OTHER, 22); |
| static MESON_GATE(g12a_vclk2_encl, HHI_GCLK_OTHER, 23); |
| static MESON_GATE(g12a_vclk2_venclmmc, HHI_GCLK_OTHER, 24); |
| static MESON_GATE(g12a_vclk2_vencl, HHI_GCLK_OTHER, 25); |
| static MESON_GATE(g12a_vclk2_other1, HHI_GCLK_OTHER, 26); |
| |
| /* Array of all clocks provided by this provider */ |
| static struct clk_hw_onecell_data g12a_hw_onecell_data = { |
| .hws = { |
| [CLKID_SYS_PLL] = &g12a_sys_pll.hw, |
| [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw, |
| [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw, |
| [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw, |
| [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw, |
| [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw, |
| [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw, |
| [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw, |
| [CLKID_GP0_PLL] = &g12a_gp0_pll.hw, |
| [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw, |
| [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw, |
| [CLKID_CLK81] = &g12a_clk81.hw, |
| [CLKID_MPLL0] = &g12a_mpll0.hw, |
| [CLKID_MPLL1] = &g12a_mpll1.hw, |
| [CLKID_MPLL2] = &g12a_mpll2.hw, |
| [CLKID_MPLL3] = &g12a_mpll3.hw, |
| [CLKID_DDR] = &g12a_ddr.hw, |
| [CLKID_DOS] = &g12a_dos.hw, |
| [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw, |
| [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw, |
| [CLKID_ETH_PHY] = &g12a_eth_phy.hw, |
| [CLKID_ISA] = &g12a_isa.hw, |
| [CLKID_PL301] = &g12a_pl301.hw, |
| [CLKID_PERIPHS] = &g12a_periphs.hw, |
| [CLKID_SPICC0] = &g12a_spicc_0.hw, |
| [CLKID_I2C] = &g12a_i2c.hw, |
| [CLKID_SANA] = &g12a_sana.hw, |
| [CLKID_SD] = &g12a_sd.hw, |
| [CLKID_RNG0] = &g12a_rng0.hw, |
| [CLKID_UART0] = &g12a_uart0.hw, |
| [CLKID_SPICC1] = &g12a_spicc_1.hw, |
| [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw, |
| [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw, |
| [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw, |
| [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw, |
| [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw, |
| [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw, |
| [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw, |
| [CLKID_AUDIO] = &g12a_audio.hw, |
| [CLKID_ETH] = &g12a_eth_core.hw, |
| [CLKID_DEMUX] = &g12a_demux.hw, |
| [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw, |
| [CLKID_ADC] = &g12a_adc.hw, |
| [CLKID_UART1] = &g12a_uart1.hw, |
| [CLKID_G2D] = &g12a_g2d.hw, |
| [CLKID_RESET] = &g12a_reset.hw, |
| [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw, |
| [CLKID_PARSER] = &g12a_parser.hw, |
| [CLKID_USB] = &g12a_usb_general.hw, |
| [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw, |
| [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw, |
| [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw, |
| [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw, |
| [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw, |
| [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw, |
| [CLKID_BT656] = &g12a_bt656.hw, |
| [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw, |
| [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw, |
| [CLKID_UART2] = &g12a_uart2.hw, |
| [CLKID_VPU_INTR] = &g12a_vpu_intr.hw, |
| [CLKID_GIC] = &g12a_gic.hw, |
| [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw, |
| [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw, |
| [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw, |
| [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw, |
| [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw, |
| [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw, |
| [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw, |
| [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw, |
| [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw, |
| [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw, |
| [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw, |
| [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw, |
| [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw, |
| [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw, |
| [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw, |
| [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw, |
| [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw, |
| [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw, |
| [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw, |
| [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw, |
| [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw, |
| [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw, |
| [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw, |
| [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw, |
| [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw, |
| [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw, |
| [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw, |
| [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw, |
| [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw, |
| [CLKID_DAC_CLK] = &g12a_dac_clk.hw, |
| [CLKID_AOCLK] = &g12a_aoclk_gate.hw, |
| [CLKID_IEC958] = &g12a_iec958_gate.hw, |
| [CLKID_ENC480P] = &g12a_enc480p.hw, |
| [CLKID_RNG1] = &g12a_rng1.hw, |
| [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw, |
| [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw, |
| [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw, |
| [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw, |
| [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw, |
| [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw, |
| [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw, |
| [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw, |
| [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw, |
| [CLKID_TS_CLK_DIV] = &g12a_ts_clk_div.hw, |
| [CLKID_TS_CLK] = &g12a_ts_clk.hw, |
| [CLKID_SPICC0_MUX] = &g12a_spicc0_mux.hw, |
| [CLKID_SPICC0_DIV] = &g12a_spicc0_div.hw, |
| [CLKID_SPICC0_GATE] = &g12a_spicc0_gate.hw, |
| [CLKID_SPICC1_MUX] = &g12a_spicc1_mux.hw, |
| [CLKID_SPICC1_DIV] = &g12a_spicc1_div.hw, |
| [CLKID_SPICC1_GATE] = &g12a_spicc1_gate.hw, |
| [CLKID_GPU_P0_MUX] = &g12a_gpu_p0_mux.hw, |
| [CLKID_GPU_P0_DIV] = &g12a_gpu_p0_div.hw, |
| [CLKID_GPU_P0_GATE] = &g12a_gpu_p0_gate.hw, |
| [CLKID_GPU_P1_MUX] = &g12a_gpu_p1_mux.hw, |
| [CLKID_GPU_P1_DIV] = &g12a_gpu_p1_div.hw, |
| [CLKID_GPU_P1_GATE] = &g12a_gpu_p1_gate.hw, |
| [CLKID_GPU_MUX] = &g12a_gpu_mux.hw, |
| [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw, |
| [CLKID_DSI_MEAS_MUX] = &g12a_dsi_meas_mux.hw, |
| [CLKID_DSI_MEAS_DIV] = &g12a_dsi_meas_div.hw, |
| [CLKID_DSI_MEAS] = &g12a_dsi_meas.hw, |
| [CLKID_VDEC_P0_MUX] = &g12a_vdec_p0_mux.hw, |
| [CLKID_VDEC_P0_DIV] = &g12a_vdec_p0_div.hw, |
| [CLKID_VDEC_P0] = &g12a_vdec_p0.hw, |
| [CLKID_VDEC_P1_MUX] = &g12a_vdec_p1_mux.hw, |
| [CLKID_VDEC_P1_DIV] = &g12a_vdec_p1_div.hw, |
| [CLKID_VDEC_P1] = &g12a_vdec_p1.hw, |
| [CLKID_VDEC_MUX] = &g12a_vdec_mux.hw, |
| [CLKID_HCODEC_P0_MUX] = &g12a_hcodec_p0_mux.hw, |
| [CLKID_HCODEC_P0_DIV] = &g12a_hcodec_p0_div.hw, |
| [CLKID_HCODEC_P0] = &g12a_hcodec_p0.hw, |
| [CLKID_HCODEC_P1_MUX] = &g12a_hcodec_p1_mux.hw, |
| [CLKID_HCODEC_P1_DIV] = &g12a_hcodec_p1_div.hw, |
| [CLKID_HCODEC_P1] = &g12a_hcodec_p1.hw, |
| [CLKID_HCODEC_MUX] = &g12a_hcodec_mux.hw, |
| [CLKID_HEVC_P0_MUX] = &g12a_hevc_p0_mux.hw, |
| [CLKID_HEVC_P0_DIV] = &g12a_hevc_p0_div.hw, |
| [CLKID_HEVC_P0] = &g12a_hevc_p0.hw, |
| [CLKID_HEVC_P1_MUX] = &g12a_hevc_p1_mux.hw, |
| [CLKID_HEVC_P1_DIV] = &g12a_hevc_p1_div.hw, |
| [CLKID_HEVC_P1] = &g12a_hevc_p1.hw, |
| [CLKID_HEVC_MUX] = &g12a_hevc_mux.hw, |
| [CLKID_HEVCF_P0_MUX] = &g12a_hevcf_p0_mux.hw, |
| [CLKID_HEVCF_P0_DIV] = &g12a_hevcf_p0_div.hw, |
| [CLKID_HEVCF_P0] = &g12a_hevcf_p0.hw, |
| [CLKID_HEVCF_P1_MUX] = &g12a_hevcf_p1_mux.hw, |
| [CLKID_HEVCF_P1_DIV] = &g12a_hevcf_p1_div.hw, |
| [CLKID_HEVCF_P1] = &g12a_hevcf_p1.hw, |
| [CLKID_HEVCF_MUX] = &g12a_hevcf_mux.hw, |
| [CLKID_VPU_P0_MUX] = &g12a_vpu_p0_mux.hw, |
| [CLKID_VPU_P0_DIV] = &g12a_vpu_p0_div.hw, |
| [CLKID_VPU_P0] = &g12a_vpu_p0.hw, |
| [CLKID_VPU_P1_MUX] = &g12a_vpu_p1_mux.hw, |
| [CLKID_VPU_P1_DIV] = &g12a_vpu_p1_div.hw, |
| [CLKID_VPU_P1] = &g12a_vpu_p1.hw, |
| [CLKID_VPU_MUX] = &g12a_vpu_mux.hw, |
| [CLKID_VAPB_P0_MUX] = &g12a_vapb_p0_mux.hw, |
| [CLKID_VAPB_P0_DIV] = &g12a_vapb_p0_div.hw, |
| [CLKID_VAPB_P0] = &g12a_vapb_p0.hw, |
| [CLKID_VAPB_P1_MUX] = &g12a_vapb_p1_mux.hw, |
| [CLKID_VAPB_P1_DIV] = &g12a_vapb_p1_div.hw, |
| [CLKID_VAPB_P1] = &g12a_vapb_p1.hw, |
| [CLKID_VAPB_MUX] = &g12a_vapb_mux.hw, |
| [CLKID_GE2D_GATE] = &g12a_ge2d_gate.hw, |
| [CLKID_VPU_CLKB_TMP_MUX] = &g12a_vpu_clkb_tmp_mux.hw, |
| [CLKID_VPU_CLKB_TMP_DIV] = &g12a_vpu_clkb_tmp_div.hw, |
| [CLKID_VPU_CLKB_TMP] = &g12a_vpu_clkb_tmp.hw, |
| [CLKID_VPU_CLKB_DIV] = &g12a_vpu_clkb_div.hw, |
| [CLKID_VPU_CLKB] = &g12a_vpu_clkb.hw, |
| [CLKID_VPU_CLKC_P0_MUX] = &g12a_vpu_clkc_p0_mux.hw, |
| [CLKID_VPU_CLKC_P0_DIV] = &g12a_vpu_clkc_p0_div.hw, |
| [CLKID_VPU_CLKC_P0] = &g12a_vpu_clkc_p0.hw, |
| [CLKID_VPU_CLKC_P1_MUX] = &g12a_vpu_clkc_p1_mux.hw, |
| [CLKID_VPU_CLKC_P1_DIV] = &g12a_vpu_clkc_p1_div.hw, |
| [CLKID_VPU_CLKC_P1] = &g12a_vpu_clkc_p1.hw, |
| [CLKID_VPU_CLKC_MUX] = &g12a_vpu_clkc_mux.hw, |
| [CLKID_CPU_CLK] = &g12a_cpu_clk.hw, |
| [CLKID_CPU_FCLK] = &g12a_cpu_fixed_clk.hw, |
| [CLKID_CPU_FSOURCE_SEL0] = |
| &g12a_cpu_fixed_source_sel0.hw, |
| [CLKID_CPU_FSOURCE_DIV0] = |
| &g12a_cpu_fixed_source_div0.hw, |
| [CLKID_CPU_FSEL0] = &g12a_cpu_fixed_sel0.hw, |
| [CLKID_CPU_FSOURCE_SEL1] = |
| &g12a_cpu_fixed_source_sel1.hw, |
| [CLKID_CPU_FSOURCE_DIV1] = |
| &g12a_cpu_fixed_source_div1.hw, |
| [CLKID_CPU_FSEL1] = &g12a_cpu_fixed_sel1.hw, |
| [CLKID_FCLK_50M_DIV] = &g12a_fclk_50m_div.hw, |
| [CLKID_FCLK_50M] = &g12a_fclk_50m.hw, |
| [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw, |
| [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw, |
| [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw, |
| [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw, |
| [CLKID_VID_PLL_DIV] = &g12a_vid_pll_div.hw, |
| [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw, |
| [CLKID_VID_PLL] = &g12a_vid_pll.hw, |
| [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw, |
| [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw, |
| [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw, |
| [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw, |
| [CLKID_VCLK_DIV] = &g12a_vclk_div.hw, |
| [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw, |
| [CLKID_VCLK] = &g12a_vclk.hw, |
| [CLKID_VCLK2] = &g12a_vclk2.hw, |
| [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw, |
| [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw, |
| [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw, |
| [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw, |
| [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw, |
| [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw, |
| [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw, |
| [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw, |
| [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw, |
| [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw, |
| [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw, |
| [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw, |
| [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw, |
| [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw, |
| [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw, |
| [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw, |
| [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw, |
| [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw, |
| [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw, |
| [CLKID_CTS_ENCL_SEL] = &g12a_cts_encl_sel.hw, |
| [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw, |
| [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw, |
| [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw, |
| [CLKID_CTS_ENCI] = &g12a_cts_enci.hw, |
| [CLKID_CTS_ENCL] = &g12a_cts_encl.hw, |
| [CLKID_CTS_ENCP] = &g12a_cts_encp.hw, |
| [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw, |
| [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw, |
| [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw, |
| [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw, |
| [CLKID_HDMI] = &g12a_hdmi.hw, |
| |
| [NR_CLKS] = NULL, |
| }, |
| .num = NR_CLKS, |
| }; |
| |
| /* Convenience table to populate regmap in .probe */ |
| static struct clk_regmap *const g12a_clk_regmaps[] = { |
| &g12a_clk81, |
| &g12a_dos, |
| &g12a_ddr, |
| &g12a_audio_locker, |
| &g12a_mipi_dsi_host, |
| &g12a_eth_phy, |
| &g12a_isa, |
| &g12a_pl301, |
| &g12a_periphs, |
| &g12a_spicc_0, |
| &g12a_i2c, |
| &g12a_sana, |
| &g12a_sd, |
| &g12a_rng0, |
| &g12a_uart0, |
| &g12a_spicc_1, |
| &g12a_hiu_reg, |
| &g12a_mipi_dsi_phy, |
| &g12a_assist_misc, |
| &g12a_emmc_a, |
| &g12a_emmc_b, |
| &g12a_emmc_c, |
| &g12a_audio_codec, |
| &g12a_audio, |
| &g12a_eth_core, |
| &g12a_demux, |
| &g12a_audio_ififo, |
| &g12a_adc, |
| &g12a_uart1, |
| &g12a_g2d, |
| &g12a_reset, |
| &g12a_pcie_comb, |
| &g12a_parser, |
| &g12a_usb_general, |
| &g12a_pcie_phy, |
| &g12a_ahb_arb0, |
| &g12a_ahb_data_bus, |
| &g12a_ahb_ctrl_bus, |
| &g12a_htx_hdcp22, |
| &g12a_htx_pclk, |
| &g12a_bt656, |
| &g12a_usb1_to_ddr, |
| &g12a_mmc_pclk, |
| &g12a_vpu_intr, |
| &g12a_gic, |
| &g12a_sd_emmc_b_clk0, |
| &g12a_sd_emmc_c_clk0, |
| &g12a_mpeg_clk_div, |
| &g12a_sd_emmc_b_clk0_div, |
| &g12a_sd_emmc_c_clk0_div, |
| &g12a_mpeg_clk_sel, |
| &g12a_sd_emmc_b_clk0_sel, |
| &g12a_sd_emmc_c_clk0_sel, |
| &g12a_sd_emmc_a_clk0_sel, |
| &g12a_sd_emmc_a_clk0_div, |
| &g12a_sd_emmc_a_clk0, |
| &g12a_mpll0, |
| &g12a_mpll1, |
| &g12a_mpll2, |
| &g12a_mpll3, |
| &g12a_mpll0_div, |
| &g12a_mpll1_div, |
| &g12a_mpll2_div, |
| &g12a_mpll3_div, |
| &g12a_fixed_pll, |
| &g12a_sys_pll, |
| &g12a_gp0_pll, |
| &g12a_hifi_pll, |
| &g12a_vclk2_venci0, |
| &g12a_vclk2_venci1, |
| &g12a_vclk2_vencp0, |
| &g12a_vclk2_vencp1, |
| &g12a_vclk2_venct0, |
| &g12a_vclk2_venct1, |
| &g12a_vclk2_other, |
| &g12a_vclk2_enci, |
| &g12a_vclk2_encp, |
| &g12a_dac_clk, |
| &g12a_aoclk_gate, |
| &g12a_iec958_gate, |
| &g12a_enc480p, |
| &g12a_rng1, |
| &g12a_vclk2_enct, |
| &g12a_vclk2_encl, |
| &g12a_vclk2_venclmmc, |
| &g12a_vclk2_vencl, |
| &g12a_vclk2_other1, |
| &g12a_fixed_pll_dco, |
| &g12a_sys_pll_dco, |
| &g12a_gp0_pll_dco, |
| &g12a_hifi_pll_dco, |
| &g12a_fclk_div2, |
| &g12a_fclk_div3, |
| &g12a_fclk_div4, |
| &g12a_fclk_div5, |
| &g12a_fclk_div7, |
| &g12a_fclk_div2p5, |
| &g12a_ts_clk_div, |
| &g12a_ts_clk, |
| &g12a_spicc0_mux, |
| &g12a_spicc0_div, |
| &g12a_spicc0_gate, |
| &g12a_spicc1_mux, |
| &g12a_spicc1_div, |
| &g12a_spicc1_gate, |
| &g12a_gpu_p0_mux, |
| &g12a_gpu_p0_div, |
| &g12a_gpu_p0_gate, |
| &g12a_gpu_p1_mux, |
| &g12a_gpu_p1_div, |
| &g12a_gpu_p1_gate, |
| &g12a_gpu_mux, |
| &g12a_pcie_pll, |
| &g12a_dsi_meas_mux, |
| &g12a_dsi_meas_div, |
| &g12a_dsi_meas, |
| &g12a_vdec_p0_mux, |
| &g12a_vdec_p0_div, |
| &g12a_vdec_p0, |
| &g12a_vdec_p1_mux, |
| &g12a_vdec_p1_div, |
| &g12a_vdec_p1, |
| &g12a_vdec_mux, |
| &g12a_hcodec_p0_mux, |
| &g12a_hcodec_p0_div, |
| &g12a_hcodec_p0, |
| &g12a_hcodec_p1_mux, |
| &g12a_hcodec_p1_div, |
| &g12a_hcodec_p1, |
| &g12a_hcodec_mux, |
| &g12a_hevc_p0_mux, |
| &g12a_hevc_p0_div, |
| &g12a_hevc_p0, |
| &g12a_hevc_p1_mux, |
| &g12a_hevc_p1_div, |
| &g12a_hevc_p1, |
| &g12a_hevc_mux, |
| &g12a_hevcf_p0_mux, |
| &g12a_hevcf_p0_div, |
| &g12a_hevcf_p0, |
| &g12a_hevcf_p1_mux, |
| &g12a_hevcf_p1_div, |
| &g12a_hevcf_p1, |
| &g12a_hevcf_mux, |
| &g12a_vpu_p0_mux, |
| &g12a_vpu_p0_div, |
| &g12a_vpu_p0, |
| &g12a_vpu_p1_mux, |
| &g12a_vpu_p1_div, |
| &g12a_vpu_p1, |
| &g12a_vpu_mux, |
| &g12a_vapb_p0_mux, |
| &g12a_vapb_p0_div, |
| &g12a_vapb_p0, |
| &g12a_vapb_p1_mux, |
| &g12a_vapb_p1_div, |
| &g12a_vapb_p1, |
| &g12a_vapb_mux, |
| &g12a_ge2d_gate, |
| &g12a_vpu_clkb_tmp_mux, |
| &g12a_vpu_clkb_tmp_div, |
| &g12a_vpu_clkb_tmp, |
| &g12a_vpu_clkb_div, |
| &g12a_vpu_clkb, |
| &g12a_vpu_clkc_p0_mux, |
| &g12a_vpu_clkc_p0_div, |
| &g12a_vpu_clkc_p0, |
| &g12a_vpu_clkc_p1_mux, |
| &g12a_vpu_clkc_p1_div, |
| &g12a_vpu_clkc_p1, |
| &g12a_vpu_clkc_mux, |
| &g12a_cpu_clk, |
| &g12a_cpu_fixed_clk, |
| &g12a_cpu_fixed_source_sel0, |
| &g12a_cpu_fixed_source_div0, |
| &g12a_cpu_fixed_sel0, |
| &g12a_cpu_fixed_source_sel1, |
| &g12a_cpu_fixed_source_div1, |
| &g12a_cpu_fixed_sel1, |
| &g12a_fclk_50m, |
| &g12a_hdmi_pll_dco, |
| &g12a_hdmi_pll_od, |
| &g12a_hdmi_pll_od2, |
| &g12a_hdmi_pll, |
| &g12a_vid_pll_div, |
| &g12a_vid_pll_sel, |
| &g12a_vid_pll, |
| &g12a_vclk_sel, |
| &g12a_vclk2_sel, |
| &g12a_vclk_input, |
| &g12a_vclk2_input, |
| &g12a_vclk_div, |
| &g12a_vclk2_div, |
| &g12a_vclk, |
| &g12a_vclk2, |
| &g12a_vclk_div1, |
| &g12a_vclk_div2_en, |
| &g12a_vclk_div4_en, |
| &g12a_vclk_div6_en, |
| &g12a_vclk_div12_en, |
| &g12a_vclk2_div1, |
| &g12a_vclk2_div2_en, |
| &g12a_vclk2_div4_en, |
| &g12a_vclk2_div6_en, |
| &g12a_vclk2_div12_en, |
| &g12a_cts_enci_sel, |
| &g12a_cts_encl_sel, |
| &g12a_cts_encp_sel, |
| &g12a_cts_vdac_sel, |
| &g12a_hdmi_tx_sel, |
| &g12a_cts_enci, |
| &g12a_cts_encl, |
| &g12a_cts_encp, |
| &g12a_cts_vdac, |
| &g12a_hdmi_tx, |
| &g12a_hdmi_sel, |
| &g12a_hdmi_div, |
| &g12a_hdmi, |
| }; |
| |
| struct g12a_nb_data { |
| struct notifier_block nb; |
| struct clk_hw_onecell_data *onecell_data; |
| }; |
| |
| static int g12a_cpu_clk_notifier_cb(struct notifier_block *nb, |
| unsigned long event, void *data) |
| { |
| struct g12a_nb_data *nb_data = |
| container_of(nb, struct g12a_nb_data, nb); |
| struct clk_hw **hws = nb_data->onecell_data->hws; |
| struct clk_hw *cpu_clk_hw, *parent_clk_hw; |
| struct clk *cpu_clk, *parent_clk; |
| int ret; |
| |
| switch (event) { |
| case PRE_RATE_CHANGE: |
| parent_clk_hw = hws[CLKID_CPU_FCLK]; |
| break; |
| case POST_RATE_CHANGE: |
| parent_clk_hw = hws[CLKID_SYS_PLL]; |
| break; |
| default: |
| return NOTIFY_DONE; |
| } |
| |
| cpu_clk_hw = hws[CLKID_CPU_CLK]; |
| cpu_clk = __clk_lookup(clk_hw_get_name(cpu_clk_hw)); |
| parent_clk = __clk_lookup(clk_hw_get_name(parent_clk_hw)); |
| |
| ret = clk_set_parent(cpu_clk, parent_clk); |
| if (ret) |
| return notifier_from_errno(ret); |
| |
| udelay(80); |
| |
| return NOTIFY_OK; |
| } |
| |
| static int g12a_cpu_fixed_clk_notifier_cb(struct notifier_block *nb, |
| unsigned long event, void *data) |
| { |
| struct clk_notifier_data *ndata = data; |
| struct clk *cpu_fixed_clk, *parent_clk; |
| int ret; |
| |
| switch (event) { |
| case PRE_RATE_CHANGE: |
| parent_clk = g12a_cpu_fixed_sel1.hw.clk; |
| ret = clk_set_rate(parent_clk, ndata->new_rate); |
| if (ret) |
| pr_err("set fixed sel1 to new rate failed\n"); |
| break; |
| case POST_RATE_CHANGE: |
| parent_clk = g12a_cpu_fixed_sel0.hw.clk; |
| break; |
| default: |
| return NOTIFY_DONE; |
| } |
| |
| cpu_fixed_clk = g12a_cpu_fixed_clk.hw.clk; |
| ret = clk_set_parent(cpu_fixed_clk, parent_clk); |
| if (ret) |
| return notifier_from_errno(ret); |
| |
| return NOTIFY_OK; |
| } |
| |
| static struct g12a_nb_data g12a_cpu_nb_data = { |
| .nb.notifier_call = g12a_cpu_clk_notifier_cb, |
| .onecell_data = &g12a_hw_onecell_data, |
| }; |
| |
| static struct g12a_nb_data g12a_cpu_fixed_nb_data = { |
| .nb.notifier_call = g12a_cpu_fixed_clk_notifier_cb, |
| .onecell_data = &g12a_hw_onecell_data, |
| }; |
| |
| static const struct of_device_id clkc_match_table[] = { |
| { .compatible = "amlogic,g12a-clkc" }, |
| { .compatible = "amlogic,sm1-clkc" }, |
| {} |
| }; |
| |
| static int g12a_clkc_probe(struct platform_device *pdev) |
| { |
| struct device *dev = &pdev->dev; |
| struct regmap *map; |
| struct clk_hw *hw; |
| int ret, i; |
| |
| /* Get the hhi system controller node */ |
| map = syscon_node_to_regmap(of_get_parent(dev->of_node)); |
| if (IS_ERR(map)) { |
| dev_err(dev, |
| "failed to get HHI regmap\n"); |
| return PTR_ERR(map); |
| } |
| |
| hw = meson_clk_hw_register_input(dev, "core", "g12a_ee_core", 0); |
| if (IS_ERR(hw)) |
| return PTR_ERR(hw); |
| |
| g12a_hw_onecell_data.hws[CLKID_EE_CORE] = hw; |
| |
| /* Populate regmap for the regmap backed clocks */ |
| for (i = 0; i < ARRAY_SIZE(g12a_clk_regmaps); i++) |
| g12a_clk_regmaps[i]->map = map; |
| |
| for (i = 1; i < g12a_hw_onecell_data.num; i++) { |
| /* array might be sparse */ |
| if (!g12a_hw_onecell_data.hws[i]) |
| continue; |
| |
| ret = devm_clk_hw_register(dev, g12a_hw_onecell_data.hws[i]); |
| if (ret) { |
| dev_err(dev, "Clock registration failed\n"); |
| return ret; |
| } |
| } |
| /* |
| * FIXME we shouldn't program the muxes in notifier handlers. The |
| * tricky programming sequence will be handled by the forthcoming |
| * coordinated clock rates mechanism once that feature is released. |
| */ |
| ret = clk_notifier_register(g12a_sys_pll.hw.clk, &g12a_cpu_nb_data.nb); |
| if (ret) { |
| pr_err("%s: failed to register the CPU clock notifier\n", |
| __func__); |
| return ret; |
| } |
| ret = clk_notifier_register(g12a_cpu_fixed_sel0.hw.clk, |
| &g12a_cpu_fixed_nb_data.nb); |
| if (ret) { |
| pr_err("%s: failed to register the fixed cpu clock notifier\n", |
| __func__); |
| return ret; |
| } |
| |
| /* |
| * keep cpu_fixed_clk's parent as cpu_fixed_sel0 clock |
| */ |
| ret = clk_set_parent(g12a_cpu_fixed_clk.hw.clk, |
| g12a_cpu_fixed_sel0.hw.clk); |
| if (ret) { |
| pr_err("%s: failed to set cpu_fixed_sel1 as cpu fixed clk's parent\n", |
| __func__); |
| return ret; |
| } |
| |
| return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, |
| &g12a_hw_onecell_data); |
| } |
| |
| static struct platform_driver g12a_driver = { |
| .probe = g12a_clkc_probe, |
| .driver = { |
| .name = "g12a-clkc", |
| .of_match_table = clkc_match_table, |
| }, |
| }; |
| |
| static int g12a_clkc_init(void) |
| { |
| return platform_driver_register(&g12a_driver); |
| } |
| arch_initcall_sync(g12a_clkc_init); |
