| /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ |
| /* |
| * Meson-G12A clock tree IDs |
| * |
| * Copyright (c) 2018 Amlogic, Inc. All rights reserved. |
| */ |
| |
| #ifndef __G12A_CLKC_H |
| #define __G12A_CLKC_H |
| |
| #define CLKID_EE_CORE 0 |
| #define CLKID_SYS_PLL 1 |
| #define CLKID_FIXED_PLL 2 |
| #define CLKID_FCLK_DIV2 3 |
| #define CLKID_FCLK_DIV3 4 |
| #define CLKID_FCLK_DIV4 5 |
| #define CLKID_FCLK_DIV5 6 |
| #define CLKID_FCLK_DIV7 7 |
| #define CLKID_GP0_PLL 8 |
| #define CLKID_FCLK_DIV2P5 11 |
| #define CLKID_CLK81 12 |
| #define CLKID_MPLL0 13 |
| #define CLKID_MPLL1 14 |
| #define CLKID_MPLL2 15 |
| #define CLKID_MPLL3 16 |
| #define CLKID_HIFI_PLL 17 |
| #define CLKID_PCIE_PLL 18 |
| #define CLKID_CPU_CLK 19 |
| #define CLKID_CPU_FCLK 20 |
| #define CLKID_FCLK_50M_DIV 21 |
| #define CLKID_FCLK_50M 22 |
| #define CLKID_HDMI_PLL_DCO 23 |
| #define CLKID_HDMI_PLL_OD 24 |
| #define CLKID_HDMI_PLL_OD2 25 |
| #define CLKID_HDMI_PLL 26 |
| #define CLKID_VID_PLL 27 |
| |
| /* HHI_GCLK_MPEG0 clk81 gates*/ |
| #define GATE_BASE0 28 |
| #define CLKID_DDR (GATE_BASE0 + 0) |
| #define CLKID_DOS (GATE_BASE0 + 1) |
| #define CLKID_AUDIO_LOCKER (GATE_BASE0 + 2) |
| #define CLKID_MIPI_DSI_HOST (GATE_BASE0 + 3) |
| #define CLKID_ETH_PHY (GATE_BASE0 + 4) |
| #define CLKID_ISA (GATE_BASE0 + 5) |
| #define CLKID_PL301 (GATE_BASE0 + 6) |
| #define CLKID_PERIPHS (GATE_BASE0 + 7) |
| #define CLKID_SPICC0 (GATE_BASE0 + 8) |
| #define CLKID_I2C (GATE_BASE0 + 9) |
| #define CLKID_SANA (GATE_BASE0 + 10) |
| #define CLKID_SD (GATE_BASE0 + 11) |
| #define CLKID_RNG0 (GATE_BASE0 + 12) |
| #define CLKID_UART0 (GATE_BASE0 + 13) |
| #define CLKID_SPICC1 (GATE_BASE0 + 14) |
| #define CLKID_HIU_IFACE (GATE_BASE0 + 15) |
| #define CLKID_MIPI_DSI_PHY (GATE_BASE0 + 16) |
| #define CLKID_ASSIST_MISC (GATE_BASE0 + 17) |
| #define CLKID_SD_EMMC_A (GATE_BASE0 + 18) |
| #define CLKID_SD_EMMC_B (GATE_BASE0 + 19) |
| #define CLKID_SD_EMMC_C (GATE_BASE0 + 20) |
| #define CLKID_AUDIO_CODEC (GATE_BASE0 + 21) |
| /* HHI_GCLK_MPEG1: clk81 gates*/ |
| #define GATE_BASE1 (GATE_BASE0 + 22) |
| #define CLKID_AUDIO (GATE_BASE1 + 0) |
| #define CLKID_ETH (GATE_BASE1 + 1) |
| #define CLKID_DEMUX (GATE_BASE1 + 2) |
| #define CLKID_AUDIO_IFIFO (GATE_BASE1 + 3) |
| #define CLKID_ADC (GATE_BASE1 + 4) |
| #define CLKID_UART1 (GATE_BASE1 + 5) |
| #define CLKID_G2D (GATE_BASE1 + 6) |
| #define CLKID_RESET (GATE_BASE1 + 7) |
| #define CLKID_PCIE_COMB (GATE_BASE1 + 8) |
| #define CLKID_PARSER (GATE_BASE1 + 9) |
| #define CLKID_USB (GATE_BASE1 + 10) |
| #define CLKID_PCIE_PHY (GATE_BASE1 + 11) |
| #define CLKID_AHB_ARB0 (GATE_BASE1 + 12) |
| /* HHI_GCLK_MPEG2: clk81 gates */ |
| #define GATE_BASE2 (GATE_BASE1 + 13) |
| #define CLKID_AHB_DATA_BUS (GATE_BASE2 + 0) |
| #define CLKID_AHB_CTRL_BUS (GATE_BASE2 + 1) |
| #define CLKID_HTX_HDCP22 (GATE_BASE2 + 2) |
| #define CLKID_HTX_PCLK (GATE_BASE2 + 3) |
| #define CLKID_BT656 (GATE_BASE2 + 4) |
| #define CLKID_USB1_DDR_BRIDGE (GATE_BASE2 + 5) |
| #define CLKID_MMC_PCLK (GATE_BASE2 + 6) |
| #define CLKID_UART2 (GATE_BASE2 + 7) |
| #define CLKID_VPU_INTR (GATE_BASE2 + 8) |
| #define CLKID_GIC (GATE_BASE2 + 9) |
| /* HHI_GCLK_OTHER: clk81 gates */ |
| #define GATE_BASE3 (GATE_BASE2 + 10) |
| #define CLKID_VCLK2_VENCI0 (GATE_BASE3 + 0) |
| #define CLKID_VCLK2_VENCI1 (GATE_BASE3 + 1) |
| #define CLKID_VCLK2_VENCP0 (GATE_BASE3 + 2) |
| #define CLKID_VCLK2_VENCP1 (GATE_BASE3 + 3) |
| #define CLKID_VCLK2_VENCT0 (GATE_BASE3 + 4) |
| #define CLKID_VCLK2_VENCT1 (GATE_BASE3 + 5) |
| #define CLKID_VCLK2_OTHER (GATE_BASE3 + 6) |
| #define CLKID_VCLK2_ENCI (GATE_BASE3 + 7) |
| #define CLKID_VCLK2_ENCP (GATE_BASE3 + 8) |
| #define CLKID_DAC_CLK (GATE_BASE3 + 9) |
| #define CLKID_AOCLK (GATE_BASE3 + 10) |
| #define CLKID_IEC958 (GATE_BASE3 + 11) |
| #define CLKID_ENC480P (GATE_BASE3 + 12) |
| #define CLKID_RNG1 (GATE_BASE3 + 13) |
| #define CLKID_VCLK2_ENCT (GATE_BASE3 + 14) |
| #define CLKID_VCLK2_ENCL (GATE_BASE3 + 15) |
| #define CLKID_VCLK2_VENCLMMC (GATE_BASE3 + 16) |
| #define CLKID_VCLK2_VENCL (GATE_BASE3 + 17) |
| #define CLKID_VCLK2_OTHER1 (GATE_BASE3 + 18) |
| /* HHI_GCLK_SP_MPEG: clk81 gates */ |
| #define GATE_BASE4 (GATE_BASE3 + 19) |
| #define CLKID_EFUSE (GATE_BASE4 + 0) |
| #define MISC_BASE (GATE_BASE4 + 1) |
| #define CLKID_TS_CLK_DIV (MISC_BASE + 0) |
| #define CLKID_TS_CLK (MISC_BASE + 1) |
| #define CLKID_SPICC0_MUX (MISC_BASE + 2) |
| #define CLKID_SPICC0_DIV (MISC_BASE + 3) |
| #define CLKID_SPICC0_GATE (MISC_BASE + 4) |
| #define CLKID_SPICC1_MUX (MISC_BASE + 5) |
| #define CLKID_SPICC1_DIV (MISC_BASE + 6) |
| #define CLKID_SPICC1_GATE (MISC_BASE + 7) |
| #define CLKID_GPU_P0_MUX (MISC_BASE + 8) |
| #define CLKID_GPU_P0_DIV (MISC_BASE + 9) |
| #define CLKID_GPU_P0_GATE (MISC_BASE + 10) |
| #define CLKID_GPU_P1_MUX (MISC_BASE + 11) |
| #define CLKID_GPU_P1_DIV (MISC_BASE + 12) |
| #define CLKID_GPU_P1_GATE (MISC_BASE + 13) |
| #define CLKID_GPU_MUX (MISC_BASE + 14) |
| /* Video clocks */ |
| #define VIDEO_BASE (MISC_BASE + 15) |
| #define CLKID_VCLK_SEL (VIDEO_BASE + 0) |
| #define CLKID_VCLK2_SEL (VIDEO_BASE + 1) |
| #define CLKID_VCLK_INPUT (VIDEO_BASE + 2) |
| #define CLKID_VCLK2_INPUT (VIDEO_BASE + 3) |
| #define CLKID_VCLK_DIV (VIDEO_BASE + 4) |
| #define CLKID_VCLK2_DIV (VIDEO_BASE + 5) |
| #define CLKID_VCLK (VIDEO_BASE + 6) |
| #define CLKID_VCLK2 (VIDEO_BASE + 7) |
| #define CLKID_VCLK_DIV1 (VIDEO_BASE + 8) |
| #define CLKID_VCLK_DIV2_EN (VIDEO_BASE + 9) |
| #define CLKID_VCLK_DIV4_EN (VIDEO_BASE + 10) |
| #define CLKID_VCLK_DIV6_EN (VIDEO_BASE + 11) |
| #define CLKID_VCLK_DIV12_EN (VIDEO_BASE + 12) |
| #define CLKID_VCLK2_DIV1 (VIDEO_BASE + 13) |
| #define CLKID_VCLK2_DIV2_EN (VIDEO_BASE + 14) |
| #define CLKID_VCLK2_DIV4_EN (VIDEO_BASE + 15) |
| #define CLKID_VCLK2_DIV6_EN (VIDEO_BASE + 16) |
| #define CLKID_VCLK2_DIV12_EN (VIDEO_BASE + 17) |
| #define CLKID_VCLK_DIV2 (VIDEO_BASE + 18) |
| #define CLKID_VCLK_DIV4 (VIDEO_BASE + 19) |
| #define CLKID_VCLK_DIV6 (VIDEO_BASE + 20) |
| #define CLKID_VCLK_DIV12 (VIDEO_BASE + 21) |
| #define CLKID_VCLK2_DIV2 (VIDEO_BASE + 22) |
| #define CLKID_VCLK2_DIV4 (VIDEO_BASE + 23) |
| #define CLKID_VCLK2_DIV6 (VIDEO_BASE + 24) |
| #define CLKID_VCLK2_DIV12 (VIDEO_BASE + 25) |
| #define CLKID_CTS_ENCI_SEL (VIDEO_BASE + 26) |
| #define CLKID_CTS_ENCL_SEL (VIDEO_BASE + 27) |
| #define CLKID_CTS_ENCP_SEL (VIDEO_BASE + 28) |
| #define CLKID_CTS_VDAC_SEL (VIDEO_BASE + 29) |
| #define CLKID_HDMI_TX_SEL (VIDEO_BASE + 30) |
| #define CLKID_CTS_ENCI (VIDEO_BASE + 31) |
| #define CLKID_CTS_ENCL (VIDEO_BASE + 32) |
| #define CLKID_CTS_ENCP (VIDEO_BASE + 33) |
| #define CLKID_CTS_VDAC (VIDEO_BASE + 34) |
| #define CLKID_HDMI_TX (VIDEO_BASE + 35) |
| #define CLKID_HDMI_SEL (VIDEO_BASE + 36) |
| #define CLKID_HDMI_DIV (VIDEO_BASE + 37) |
| #define CLKID_HDMI (VIDEO_BASE + 38) |
| /* Media clocks */ |
| #define MEDIA_BASE (VIDEO_BASE + 39) |
| #define CLKID_DSI_MEAS_MUX (MEDIA_BASE + 0) |
| #define CLKID_DSI_MEAS_DIV (MEDIA_BASE + 1) |
| #define CLKID_DSI_MEAS (MEDIA_BASE + 2) |
| #define CLKID_VDEC_P0_MUX (MEDIA_BASE + 3) |
| #define CLKID_VDEC_P0_DIV (MEDIA_BASE + 4) |
| #define CLKID_VDEC_P0 (MEDIA_BASE + 5) |
| #define CLKID_VDEC_P1_MUX (MEDIA_BASE + 6) |
| #define CLKID_VDEC_P1_DIV (MEDIA_BASE + 7) |
| #define CLKID_VDEC_P1 (MEDIA_BASE + 8) |
| #define CLKID_VDEC_MUX (MEDIA_BASE + 9) |
| #define CLKID_HCODEC_P0_MUX (MEDIA_BASE + 10) |
| #define CLKID_HCODEC_P0_DIV (MEDIA_BASE + 11) |
| #define CLKID_HCODEC_P0 (MEDIA_BASE + 12) |
| #define CLKID_HCODEC_P1_MUX (MEDIA_BASE + 13) |
| #define CLKID_HCODEC_P1_DIV (MEDIA_BASE + 14) |
| #define CLKID_HCODEC_P1 (MEDIA_BASE + 15) |
| #define CLKID_HCODEC_MUX (MEDIA_BASE + 16) |
| #define CLKID_HEVC_P0_MUX (MEDIA_BASE + 17) |
| #define CLKID_HEVC_P0_DIV (MEDIA_BASE + 18) |
| #define CLKID_HEVC_P0 (MEDIA_BASE + 19) |
| #define CLKID_HEVC_P1_MUX (MEDIA_BASE + 20) |
| #define CLKID_HEVC_P1_DIV (MEDIA_BASE + 21) |
| #define CLKID_HEVC_P1 (MEDIA_BASE + 22) |
| #define CLKID_HEVC_MUX (MEDIA_BASE + 23) |
| #define CLKID_HEVCF_P0_MUX (MEDIA_BASE + 24) |
| #define CLKID_HEVCF_P0_DIV (MEDIA_BASE + 25) |
| #define CLKID_HEVCF_P0 (MEDIA_BASE + 26) |
| #define CLKID_HEVCF_P1_MUX (MEDIA_BASE + 27) |
| #define CLKID_HEVCF_P1_DIV (MEDIA_BASE + 28) |
| #define CLKID_HEVCF_P1 (MEDIA_BASE + 29) |
| #define CLKID_HEVCF_MUX (MEDIA_BASE + 30) |
| #define CLKID_VPU_P0_MUX (MEDIA_BASE + 31) |
| #define CLKID_VPU_P0_DIV (MEDIA_BASE + 32) |
| #define CLKID_VPU_P0 (MEDIA_BASE + 33) |
| #define CLKID_VPU_P1_MUX (MEDIA_BASE + 34) |
| #define CLKID_VPU_P1_DIV (MEDIA_BASE + 35) |
| #define CLKID_VPU_P1 (MEDIA_BASE + 36) |
| #define CLKID_VPU_MUX (MEDIA_BASE + 37) |
| #define CLKID_VAPB_P0_MUX (MEDIA_BASE + 38) |
| #define CLKID_VAPB_P0_DIV (MEDIA_BASE + 39) |
| #define CLKID_VAPB_P0 (MEDIA_BASE + 40) |
| #define CLKID_VAPB_P1_MUX (MEDIA_BASE + 41) |
| #define CLKID_VAPB_P1_DIV (MEDIA_BASE + 42) |
| #define CLKID_VAPB_P1 (MEDIA_BASE + 43) |
| #define CLKID_VAPB_MUX (MEDIA_BASE + 44) |
| #define CLKID_GE2D_GATE (MEDIA_BASE + 45) |
| #define CLKID_VPU_CLKB_TMP_MUX (MEDIA_BASE + 46) |
| #define CLKID_VPU_CLKB_TMP_DIV (MEDIA_BASE + 47) |
| #define CLKID_VPU_CLKB_TMP (MEDIA_BASE + 48) |
| #define CLKID_VPU_CLKB_DIV (MEDIA_BASE + 49) |
| #define CLKID_VPU_CLKB (MEDIA_BASE + 50) |
| #define CLKID_VPU_CLKC_P0_MUX (MEDIA_BASE + 51) |
| #define CLKID_VPU_CLKC_P0_DIV (MEDIA_BASE + 52) |
| #define CLKID_VPU_CLKC_P0 (MEDIA_BASE + 53) |
| #define CLKID_VPU_CLKC_P1_MUX (MEDIA_BASE + 54) |
| #define CLKID_VPU_CLKC_P1_DIV (MEDIA_BASE + 55) |
| #define CLKID_VPU_CLKC_P1 (MEDIA_BASE + 56) |
| #define CLKID_VPU_CLKC_MUX (MEDIA_BASE + 57) |
| #define SD_EMMC_BASE (MEDIA_BASE + 58) |
| #define CLKID_SD_EMMC_B_CLK0 (SD_EMMC_BASE + 0) |
| #define CLKID_SD_EMMC_C_CLK0 (SD_EMMC_BASE + 1) |
| #define CLKID_SD_EMMC_A_CLK0 (SD_EMMC_BASE + 2) |
| #define CLKID_SD_EMMC_B_CLK0_SEL (SD_EMMC_BASE + 3) |
| #define CLKID_SD_EMMC_B_CLK0_DIV (SD_EMMC_BASE + 4) |
| #define CLKID_SD_EMMC_C_CLK0_SEL (SD_EMMC_BASE + 5) |
| #define CLKID_SD_EMMC_C_CLK0_DIV (SD_EMMC_BASE + 6) |
| #define CLKID_SD_EMMC_A_CLK0_SEL (SD_EMMC_BASE + 7) |
| #define CLKID_SD_EMMC_A_CLK0_DIV (SD_EMMC_BASE + 8) |
| |
| #endif /* __G12A_CLKC_H */ |
