| // SPDX-License-Identifier: ISC |
| /* |
| * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. |
| */ |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/qcom,gcc-ipq5018.h> |
| #include <dt-bindings/reset/qcom,gcc-ipq5018.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/clock/qca,apss-ipq5018.h> |
| #include "ipq5018-memory.dtsi" |
| |
| |
| / { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| interrupt-parent = <&intc>; |
| |
| #ifdef ENABLE_QSEECOM |
| qseecom { |
| compatible = "ipq5018-qseecom"; |
| mem-start = <0x4a400000>; |
| mem-size = <0x200000>; |
| memory-region = <&tzapp_data>; |
| status = "ok"; |
| }; |
| #endif |
| clocks { |
| sleep_clk: sleep-clk { |
| compatible = "fixed-clock"; |
| clock-frequency = <32000>; |
| #clock-cells = <0>; |
| }; |
| |
| xo: xo { |
| compatible = "fixed-clock"; |
| clock-frequency = <24000000>; |
| #clock-cells = <0>; |
| }; |
| }; |
| |
| cpus: cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| CPU0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x0>; |
| enable-method = "psci"; |
| qcom,acc = <&acc0>; |
| next-level-cache = <&L2_0>; |
| clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; |
| clock-names = "cpu"; |
| operating-points = < |
| /* kHz uV (fixed) */ |
| 800000 1100000 |
| 1008000 1100000 |
| >; |
| clock-latency = <200000>; |
| }; |
| |
| CPU1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| enable-method = "psci"; |
| reg = <0x1>; |
| qcom,acc = <&acc1>; |
| next-level-cache = <&L2_0>; |
| clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; |
| clock-names = "cpu"; |
| operating-points = < |
| /* kHz uV (fixed) */ |
| 800000 1100000 |
| 1008000 1100000 |
| >; |
| clock-latency = <200000>; |
| }; |
| |
| L2_0: l2-cache { |
| compatible = "cache"; |
| cache-level = <0x2>; |
| }; |
| }; |
| |
| pmuv8: pmu { |
| compatible = "arm,cortex-a53-pmu"; |
| interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | |
| IRQ_TYPE_LEVEL_HIGH)>; |
| }; |
| |
| psci: psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| firmware { |
| scm { |
| compatible = "qcom,scm"; |
| qcom,dload-mode = <&tcsr 0x6100>; |
| }; |
| |
| qfprom_sec { |
| compatible = "qcom,qfprom-sec"; |
| fuse-blow-size-required = <1>; |
| }; |
| }; |
| |
| tcsr_mutex: hwlock { |
| compatible = "qcom,tcsr-mutex"; |
| syscon = <&tcsr_mutex_regs 0 0x80>; |
| #hwlock-cells = <1>; |
| }; |
| |
| smem { |
| compatible = "qcom,smem"; |
| memory-region = <&smem_region>; |
| hwlocks = <&tcsr_mutex 0>; |
| }; |
| |
| qti,tzlog { |
| compatible = "qti,tzlog"; |
| interrupts = <GIC_SPI 267 IRQ_TYPE_EDGE_RISING>; |
| qti,tz-diag-buf-size = <0x2000>; |
| qti,tz-ring-off = <7>; |
| qti,tz-log-pos-info-off = <455>; |
| }; |
| |
| soc: soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0 0xffffffff>; |
| dma-ranges; |
| compatible = "simple-bus"; |
| |
| hs_m31phy_0: hs_m31phy@5b000 { |
| compatible = "qca,m31-usb-hsphy"; |
| reg = <0x05b000 0x120>, |
| <0x08af8800 0x400>; |
| reg-names = "m31usb_phy_base", |
| "qscratch_base"; |
| phy_type= "utmi"; |
| |
| resets = <&gcc GCC_QUSB2_0_PHY_BCR>; |
| reset-names = "usb2_phy_reset"; |
| |
| status = "ok"; |
| }; |
| |
| ssuniphy_0: ssuniphy@5d000 { |
| compatible = "qca,ipq5018-uni-ssphy"; |
| reg = <0x5d000 0x800>; |
| clocks = <&gcc GCC_USB0_PIPE_CLK>, |
| <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; |
| |
| clock-names = "pipe_clk", "phy_cfg_ahb_clk"; |
| |
| resets = <&gcc GCC_USB0_PHY_BCR>; |
| reset-names = "por_rst"; |
| #phy-cells = <0>; |
| status = "ok"; |
| }; |
| mdio0: mdio@88000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "qcom,qca-mdio", "qcom,ipq40xx-mdio"; |
| reg = <0x88000 0x64>; |
| status = "disabled"; |
| resets = <&gcc GCC_GEPHY_MDC_SW_ARES>; |
| reset-names = "gephy_mdc_rst"; |
| }; |
| |
| mdio1: mdio@90000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "qcom,qca-mdio"; |
| reg = <0x90000 0x64>; |
| status = "disabled"; |
| }; |
| |
| ess_instance: ess-instance { |
| ess-switch@0x39c00000 { |
| compatible = "qcom,ess-switch-ipq50xx"; |
| reg = <0x39c00000 0x200000>; |
| switch_access_mode = "local bus"; |
| clocks = <&gcc GCC_CMN_BLK_AHB_CLK>, |
| <&gcc GCC_CMN_BLK_SYS_CLK>, |
| <&gcc GCC_UNIPHY_AHB_CLK>, |
| <&gcc GCC_UNIPHY_SYS_CLK>, |
| <&gcc GCC_MDIO0_AHB_CLK>, |
| <&gcc GCC_MDIO1_AHB_CLK>, |
| <&gcc GCC_GMAC0_CFG_CLK>, |
| <&gcc GCC_GMAC0_SYS_CLK>, |
| <&gcc GCC_GMAC1_CFG_CLK>, |
| <&gcc GCC_GMAC1_SYS_CLK>, |
| <&gcc GCC_GEPHY_RX_CLK>, |
| <&gcc GCC_GEPHY_TX_CLK>, |
| <&gcc GCC_UNIPHY_RX_CLK>, |
| <&gcc GCC_UNIPHY_TX_CLK>, |
| <&gcc GCC_GMAC0_RX_CLK>, |
| <&gcc GCC_GMAC0_TX_CLK>, |
| <&gcc GCC_GMAC1_RX_CLK>, |
| <&gcc GCC_GMAC1_TX_CLK>, |
| <&gcc GCC_SNOC_GMAC0_AHB_CLK>, |
| <&gcc GCC_SNOC_GMAC1_AHB_CLK>, |
| <&gcc GCC_GMAC0_PTP_CLK>, |
| <&gcc GCC_GMAC1_PTP_CLK>; |
| clock-names = "cmn_ahb_clk", "cmn_sys_clk", |
| "uniphy_ahb_clk", "uniphy_sys_clk", |
| "gcc_mdio0_ahb_clk", |
| "gcc_mdio1_ahb_clk", |
| "gcc_gmac0_cfg_clk", |
| "gcc_gmac0_sys_clk", |
| "gcc_gmac1_cfg_clk", |
| "gcc_gmac1_sys_clk", |
| "uniphy0_port1_rx_clk", |
| "uniphy0_port1_tx_clk", |
| "uniphy1_port5_rx_clk", |
| "uniphy1_port5_tx_clk", |
| "nss_port1_rx_clk", "nss_port1_tx_clk", |
| "nss_port2_rx_clk", "nss_port2_tx_clk", |
| "gcc_snoc_gmac0_ahb_clk", |
| "gcc_snoc_gmac1_ahb_clk", |
| "gcc_gmac0_ptp_clk", |
| "gcc_gmac1_ptp_clk"; |
| resets = <&gcc GCC_GEPHY_BCR>, <&gcc GCC_UNIPHY_BCR>, |
| <&gcc GCC_GMAC0_BCR>, <&gcc GCC_GMAC1_BCR>, |
| <&gcc GCC_UNIPHY_SOFT_RESET>, |
| <&gcc GCC_GEPHY_MISC_ARES>; |
| reset-names = "gephy_bcr_rst", "uniphy_bcr_rst", |
| "gmac0_bcr_rst", "gmac1_bcr_rst", |
| "uniphy1_soft_rst", |
| "gephy_misc_rst"; |
| }; |
| }; |
| |
| ess-uniphy@98000 { |
| compatible = "qcom,ess-uniphy"; |
| reg = <0x98000 0x800>; |
| uniphy_access_mode = "local bus"; |
| }; |
| |
| pcie_x2phy: phy@86000{ |
| compatible = "qca,uni-pcie-phy-gen2"; |
| reg = <0x86000 0x1000>; |
| phy-type = "gen2"; |
| #phy-cells = <0>; |
| clocks = <&gcc GCC_PCIE0_PIPE_CLK>; |
| clock-names = "pipe_clk"; |
| |
| resets = <&gcc GCC_PCIE0_PHY_BCR>, |
| <&gcc GCC_PCIE0PHY_PHY_BCR>; |
| reset-names = "phy", |
| "phy_phy"; |
| mode_fixed = <1>; |
| status = "disabled"; |
| }; |
| |
| tlmm: pinctrl@1000000 { |
| compatible = "qcom,ipq5018-pinctrl"; |
| reg = <0x01000000 0x300000>; |
| interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&tlmm 0 0 80>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| tcsr_mutex_regs: syscon@1905000 { |
| compatible = "syscon"; |
| reg = <0x01905000 0x8000>; |
| }; |
| |
| gcc: gcc@1800000 { |
| compatible = "qcom,gcc-ipq5018"; |
| reg = <0x01800000 0x80000>; |
| clocks = <&xo>, <&sleep_clk>; |
| clock-names = "xo", "sleep_clk"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| tcsr_q6_block: syscon@1945000 { |
| compatible = "syscon"; |
| reg = <0x1945000 0xE000>; |
| }; |
| |
| sdhc_1: sdhci@7804000 { |
| compatible = "qcom,sdhci-msm-v5"; |
| reg = <0x7804000 0x1000>; |
| reg-names = "hc_mem"; |
| |
| interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "hc_irq", "pwr_irq"; |
| |
| qcom,bus-width = <4>; |
| qcom,max_clk = <192000000>; |
| qcom,dedicated-io = <1>; |
| |
| /* device core power supply */ |
| qcom,vdd-voltage-level = <2900000 2900000>; |
| qcom,vdd-current-level = <200 570000>; |
| |
| /* device communication power supply */ |
| qcom,vdd-io-lpm-sup; |
| qcom,vdd-io-voltage-level = <1800000 1800000>; |
| qcom,vdd-io-current-level = <200 325000>; |
| qcom,vdd-io-always-on; |
| |
| qcom,cpu-dma-latency-us = <701>; |
| qcom,msm-bus,name = "sdhc1"; |
| qcom,msm-bus,num-cases = <9>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ |
| <78 512 1046 3200>, /* 400 KB/s*/ |
| <78 512 52286 160000>, /* 20 MB/s */ |
| <78 512 65360 200000>, /* 25 MB/s */ |
| <78 512 130718 400000>, /* 50 MB/s */ |
| <78 512 261438 800000>, /* 100 MB/s */ |
| <78 512 261438 800000>, /* 200 MB/s */ |
| <78 512 261438 800000>, /* 400 MB/s */ |
| <78 512 1338562 4096000>; /* Max. bandwidth */ |
| qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 \ |
| 50000000 100000000 200000000 \ |
| 400000000 4294967295>; |
| |
| clocks = <&gcc GCC_SDCC1_AHB_CLK>, |
| <&gcc GCC_SDCC1_APPS_CLK>; |
| clock-names = "iface", "core"; |
| qcom,large-address-bus; |
| qcom,disable-aggressive-pm; |
| status = "ok"; |
| }; |
| |
| blsp_dma: dma@7884000 { |
| compatible = "qcom,bam-v1.7.0"; |
| reg = <0x07884000 0x1d000>; |
| interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "bam_clk"; |
| #dma-cells = <1>; |
| qcom,ee = <0>; |
| }; |
| |
| spi_0: spi@78b5000 { /* BLSP1 QUP0 */ |
| compatible = "qcom,spi-qup-v2.2.1"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x78b5000 0x600>; |
| interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; |
| spi-max-frequency = <50000000>; |
| clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, |
| <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| dmas = <&blsp_dma 4>, <&blsp_dma 5>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| i2c_0: i2c@78b7000 { |
| compatible = "qcom,i2c-qup-v2.2.1"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x78b7000 0x600>; |
| interrupts = <GIC_SPI 97 0x4>; |
| clocks = <&gcc GCC_BLSP1_AHB_CLK>, |
| <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; |
| clock-names = "iface", "core"; |
| clock-frequency = <400000>; |
| dmas = <&blsp_dma 9>, <&blsp_dma 8>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| qpic_bam: dma@7984000 { |
| compatible = "qcom,bam-v1.7.0"; |
| reg = <0x7984000 0x1c000>; |
| interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_QPIC_AHB_CLK>; |
| clock-names = "bam_clk"; |
| #dma-cells = <1>; |
| qcom,ee = <0>; |
| status = "disabled"; |
| }; |
| |
| nand: qpic-nand@79b0000 { |
| compatible = "qcom,ebi2-nandc-bam-v2.1.1"; |
| reg = <0x79b0000 0x10000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QPIC_CLK>, |
| <&gcc GCC_QPIC_AHB_CLK>, |
| <&gcc GCC_QPIC_IO_MACRO_CLK>; |
| clock-names = "core", "aon", "io_macro"; |
| |
| dmas = <&qpic_bam 0>, |
| <&qpic_bam 1>, |
| <&qpic_bam 2>, |
| <&qpic_bam 3>; |
| dma-names = "tx", "rx", "cmd", "status"; |
| |
| qpic,io_macro_clk_rates = <24000000 100000000 200000000 320000000>; |
| status = "disabled"; |
| |
| nandcs@0 { |
| compatible = "qcom,nandcs"; |
| reg = <0>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| nand-ecc-strength = <4>; |
| nand-ecc-step-size = <512>; |
| nand-bus-width = <8>; |
| }; |
| }; |
| |
| nss-dp-common { |
| compatible = "qcom,nss-dp-common"; |
| qcom,tcsr-base = <0x01937000>; |
| }; |
| |
| nss_crypto: qcom,nss_crypto { |
| compatible = "qcom,nss-crypto"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| qcom,max-contexts = <64>; |
| qcom,max-context-size = <144>; |
| ranges; |
| ce5_node { |
| compatible = "qcom,ce5"; |
| reg-names = "crypto_pbase", "bam_base"; |
| reg = <0x0073a000 0x6000>, |
| <0x00704000 0x20000>; |
| qcom,dma-mask = <0x0c>; |
| qcom,transform-enabled; |
| qcom,aes128-cbc; |
| qcom,aes256-cbc; |
| qcom,aes128-ctr; |
| qcom,aes256-ctr; |
| qcom,aes128-ecb; |
| qcom,aes256-ecb; |
| qcom,3des-cbc; |
| qcom,sha160-hash; |
| qcom,sha256-hash; |
| qcom,sha160-hmac; |
| qcom,sha256-hmac; |
| qcom,aes128-cbc-sha160-hmac; |
| qcom,aes256-cbc-sha160-hmac; |
| qcom,aes128-ctr-sha160-hmac; |
| qcom,aes256-ctr-sha160-hmac; |
| qcom,3des-cbc-sha160-hmac; |
| qcom,3des-cbc-sha256-hmac; |
| qcom,aes128-cbc-sha256-hmac; |
| qcom,aes256-cbc-sha256-hmac; |
| qcom,aes128-ctr-sha256-hmac; |
| qcom,aes256-ctr-sha256-hmac; |
| engine0 { |
| qcom,ee = <2 3>; |
| }; |
| }; |
| }; |
| |
| blsp1_uart1: serial@78af000 { |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| reg = <0x078af000 0x200>; |
| interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, |
| <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| status = "disabled"; |
| }; |
| |
| usb3: usb3@8A00000 { |
| compatible = "qcom,ipq5018-dwc3"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| reg = <0x8AF8800 0x100>, |
| <0x8A00000 0xe000>; |
| reg-names = "qscratch_base", "dwc3_base"; |
| clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, |
| <&gcc GCC_USB0_MASTER_CLK>, |
| <&gcc GCC_USB0_SLEEP_CLK>, |
| <&gcc GCC_USB0_MOCK_UTMI_CLK>, |
| <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, |
| <&gcc GCC_USB0_AUX_CLK>, |
| <&gcc GCC_USB0_LFPS_CLK>, |
| <&gcc GCC_USB0_PIPE_CLK>; |
| clock-names = "sys_noc_axi", |
| "master", |
| "sleep", |
| "mock_utmi", |
| "cfg_ahb_clk", |
| "aux_clk", |
| "lfps_clk", |
| "pipe_clk"; |
| assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, |
| <&gcc GCC_USB0_MASTER_CLK>, |
| <&gcc GCC_USB0_MOCK_UTMI_CLK>; |
| assigned-clock-rates = <133330000>, |
| <133330000>, |
| <60000000>; |
| resets = <&gcc GCC_USB0_BCR>; |
| reset-names = "usb30_mstr_rst"; |
| qca,host = <1>; |
| status = "ok"; |
| qcom,multiplexed-phy; |
| qcom,phy-mux-regs = <&tcsr_q6_block 0x2540>; |
| |
| dwc_0: dwc3@8A00000 { |
| compatible = "snps,dwc3"; |
| reg = <0x8A00000 0xe000>; |
| interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
| usb-phy = <&hs_m31phy_0>; |
| #phy-cells = <0>; |
| phys = <&ssuniphy_0>; |
| phy-names = "usb3-phy"; |
| snps,dis_ep_cache_eviction; |
| tx-fifo-resize; |
| snps,usb3-u1u2-disable; |
| snps,nominal-elastic-buffer; |
| snps,is-utmi-l1-suspend; |
| snps,hird-threshold = /bits/ 8 <0x0>; |
| snps,dis_u2_susphy_quirk; |
| snps,dis_u3_susphy_quirk; |
| snps,quirk-ref-clock-adjustment = <0x49459>; |
| snps,quirk-ref-clock-period = <0x10>; |
| snps,quirk-30m-sb-sel = <0x0>; |
| dr_mode = "host"; |
| }; |
| }; |
| |
| intc: interrupt-controller@b000000 { |
| compatible = "qcom,msm-qgic2"; |
| interrupt-controller; |
| #interrupt-cells = <0x3>; |
| reg = <0x0b000000 0x1000>, /*GICD*/ |
| <0x0b002000 0x1000>, /*GICC*/ |
| <0x0b001000 0x1000>, /*GICH*/ |
| <0x0b004000 0x1000>; /*GICV*/ |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| ranges = <0x0 0xb00a000 0x1ffa>; |
| |
| v2m0: v2m@0 { |
| compatible = "arm,gic-v2m-frame"; |
| msi-controller; |
| reg = <0x0 0xffd>; |
| }; |
| |
| v2m1: v2m@1000 { |
| compatible = "arm,gic-v2m-frame"; |
| msi-controller; |
| reg = <0x1000 0xffd>; |
| }; |
| }; |
| |
| watchdog@b017000 { |
| compatible = "qcom,kpss-wdt"; |
| interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; |
| reg = <0x0b017000 0x40>; |
| clocks = <&sleep_clk>; |
| max-timeout-sec = <32>; |
| }; |
| |
| apcs_glb: mailbox@b111000 { |
| compatible = "qcom,ipq5018-apcs-apps-global"; |
| reg = <0x0b111000 0x6000>; |
| #clock-cells = <1>; |
| #mbox-cells = <1>; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| clock-frequency = <24000000>; |
| always-on; |
| }; |
| |
| timer@b120000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| compatible = "arm,armv7-timer-mem"; |
| reg = <0x0b120000 0x1000>; |
| clock-frequency = <19200000>; |
| |
| frame@b120000 { |
| frame-number = <0>; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x0b121000 0x1000>, |
| <0x0b122000 0x1000>; |
| }; |
| |
| frame@b123000 { |
| frame-number = <1>; |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0xb123000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@b124000 { |
| frame-number = <2>; |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x0b124000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@b125000 { |
| frame-number = <3>; |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x0b125000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@b126000 { |
| frame-number = <4>; |
| interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x0b126000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@b127000 { |
| frame-number = <5>; |
| interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x0b127000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@b128000 { |
| frame-number = <6>; |
| interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x0b128000 0x1000>; |
| status = "disabled"; |
| }; |
| }; |
| |
| pcie_x2: pci@a0000000 { |
| compatible = "qcom,pcie-ipq5018"; |
| reg = <0xa0000000 0xf1d |
| 0xa0000F20 0xa8 |
| 0xa0001000 0x1000 |
| 0x80000 0x3000 |
| 0xa0100000 0x1000>; |
| reg-names = "dbi", "elbi", "atu", "parf", "config"; |
| device_type = "pci"; |
| linux,pci-domain = <1>; |
| bus-range = <0x00 0xff>; |
| num-lanes = <2>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| |
| phys = <&pcie_x2phy>; |
| phy-names ="pciephy"; |
| force_gen2 = <1>; |
| |
| ranges = <0x81000000 0 0xa0200000 0xa0200000 |
| 0 0x00100000 /* downstream I/O */ |
| 0x82000000 0 0xa0300000 0xa0300000 |
| 0 0x10000000>; /* non-prefetchable memory */ |
| |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 0x7>; |
| interrupt-map = <0 0 0 1 &intc 0 75 |
| IRQ_TYPE_LEVEL_HIGH>, /* int_a */ |
| <0 0 0 2 &intc 0 78 |
| IRQ_TYPE_LEVEL_HIGH>, /* int_b */ |
| <0 0 0 3 &intc 0 79 |
| IRQ_TYPE_LEVEL_HIGH>, /* int_c */ |
| <0 0 0 4 &intc 0 83 |
| IRQ_TYPE_LEVEL_HIGH>; /* int_d */ |
| |
| clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, |
| <&gcc GCC_PCIE0_AXI_M_CLK>, |
| <&gcc GCC_PCIE0_AXI_S_CLK>, |
| <&gcc GCC_PCIE0_AHB_CLK>, |
| <&gcc GCC_PCIE0_AUX_CLK>, |
| <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>; |
| |
| clock-names = "iface", |
| "axi_m", |
| "axi_s", |
| "ahb", |
| "aux", |
| "axi_bridge"; |
| |
| resets = <&gcc GCC_PCIE0_PIPE_ARES>, |
| <&gcc GCC_PCIE0_SLEEP_ARES>, |
| <&gcc GCC_PCIE0_CORE_STICKY_ARES>, |
| <&gcc GCC_PCIE0_AXI_MASTER_ARES>, |
| <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, |
| <&gcc GCC_PCIE0_AHB_ARES>, |
| <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, |
| <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; |
| |
| reset-names = "pipe", |
| "sleep", |
| "sticky", |
| "axi_m", |
| "axi_s", |
| "ahb", |
| "axi_m_sticky", |
| "axi_s_sticky"; |
| |
| msi-parent = <&v2m0>; |
| status = "disabled"; |
| |
| pcie_x2_rp: pcie_x2_rp { |
| reg = <0 0 0 0 0>; |
| }; |
| }; |
| |
| q6v5_wcss: remoteproc@cd00000 { |
| compatible = "qcom,qcs5018-wcss-pil"; |
| reg = <0x0cd00000 0x4040>, |
| <0x004ab000 0x20>; |
| reg-names = "qdsp6", |
| "rmb"; |
| interrupts-extended = <&intc GIC_SPI 291 IRQ_TYPE_EDGE_RISING>, |
| <&wcss_smp2p_in 0 0>, |
| <&wcss_smp2p_in 1 0>, |
| <&wcss_smp2p_in 2 0>, |
| <&wcss_smp2p_in 3 0>; |
| interrupt-names = "wdog", |
| "fatal", |
| "ready", |
| "handover", |
| "stop-ack"; |
| |
| resets = <&gcc GCC_WCSSAON_RESET>, |
| <&gcc GCC_WCSS_BCR>, |
| <&gcc GCC_WCSS_Q6_BCR>, |
| <&gcc GCC_CE_BCR>; |
| |
| reset-names = "wcss_aon_reset", |
| "wcss_reset", |
| "wcss_q6_reset", |
| "ce_reset"; |
| |
| |
| clocks = <&gcc GCC_Q6_AXIS_CLK>, |
| <&gcc GCC_WCSS_AHB_S_CLK>, |
| <&gcc GCC_WCSS_ECAHB_CLK>, |
| <&gcc GCC_WCSS_ACMT_CLK>, |
| <&gcc GCC_WCSS_AXI_M_CLK>, |
| <&gcc GCC_Q6_AXIM_CLK>, |
| <&gcc GCC_Q6_AXIM2_CLK>, |
| <&gcc GCC_Q6_AHB_CLK>, |
| <&gcc GCC_Q6_AHB_S_CLK>, |
| <&gcc GCC_WCSS_AXI_S_CLK>; |
| clock-names = "gcc_q6_axis_clk", |
| "gcc_wcss_ahb_s_clk", |
| "gcc_wcss_ecahb_clk", |
| "gcc_wcss_acmt_clk", |
| "gcc_wcss_axi_m_clk", |
| "gcc_q6_axim_clk", |
| "gcc_q6_axim2_clk", |
| "gcc_q6_ahb_clk", |
| "gcc_q6_ahb_s_clk", |
| "gcc_wcss_axi_s_clk"; |
| |
| qcom,halt-regs = <&tcsr_q6_block 0xa000 0xd000 0x0>; |
| |
| qcom,smem-states = <&wcss_smp2p_out 0>, |
| <&wcss_smp2p_out 1>; |
| qcom,smem-state-names = "shutdown", |
| "stop"; |
| |
| glink-edge { |
| interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; |
| qcom,remote-pid = <1>; |
| mboxes = <&apcs_glb 8>; |
| |
| qrtr_requests { |
| qcom,glink-channels = "IPCRTR"; |
| }; |
| }; |
| }; |
| |
| wifi0: wifi@c000000 { |
| compatible = "qcom,cnss-qca5018", "qcom,ipq5018-wifi"; |
| reg = <0xc000000 0x1000000>; |
| #ifdef __IPQ_MEM_PROFILE_256_MB__ |
| qcom,tgt-mem-mode = <2>; |
| #else |
| qcom,tgt-mem-mode = <1>; |
| #endif |
| qcom,rproc = <&q6v5_wcss>; |
| interrupts = <0 288 1>, /* o_wcss_apps_intr[0] = */ |
| <0 289 1>, |
| <0 290 1>, |
| <0 292 1>, |
| <0 293 1>, |
| <0 294 1>, |
| <0 295 1>, |
| <0 296 1>, |
| <0 297 1>, |
| <0 298 1>, |
| <0 299 1>, |
| <0 300 1>, |
| <0 301 1>, |
| <0 302 1>, |
| <0 303 1>, |
| <0 304 1>, |
| <0 305 1>, |
| <0 306 1>, |
| <0 307 1>, |
| <0 308 1>, |
| <0 309 1>, |
| <0 310 1>, |
| <0 311 1>, |
| <0 334 1>, |
| <0 313 1>, /* o_wcss_apps_intr[25] */ |
| |
| <0 314 1>, |
| <0 315 1>, |
| <0 316 1>, |
| <0 317 1>, |
| <0 318 1>, |
| <0 319 1>, |
| <0 320 1>, |
| <0 321 1>, |
| <0 322 1>, |
| <0 323 1>, |
| <0 324 1>, |
| <0 325 1>, |
| |
| <0 326 1>, |
| |
| <0 327 1>, |
| <0 328 1>, |
| <0 329 1>, |
| <0 330 1>, |
| <0 331 1>, |
| <0 332 1>, |
| |
| <0 333 1>, |
| <0 312 1>, |
| <0 335 1>, |
| <0 336 1>, |
| <0 337 1>, |
| <0 338 1>, |
| <0 339 1>; /* o_wcss_apps_intr[51] */ |
| |
| interrupt-names = "misc-pulse1", |
| "misc-latch", |
| "sw-exception", |
| "ce0", |
| "ce1", |
| "ce2", |
| "ce3", |
| "ce4", |
| "ce5", |
| "ce6", |
| "ce7", |
| "ce8", |
| "ce9", |
| "ce10", |
| "ce11", |
| "host2wbm-desc-feed", |
| "host2reo-re-injection", |
| "host2reo-command", |
| "host2rxdma-monitor-ring3", |
| "host2rxdma-monitor-ring2", |
| "host2rxdma-monitor-ring1", |
| "reo2ost-exception", |
| "wbm2host-rx-release", |
| "reo2host-status", |
| "reo2host-destination-ring4", |
| "reo2host-destination-ring3", |
| "reo2host-destination-ring2", |
| "reo2host-destination-ring1", |
| "rxdma2host-monitor-destination-mac3", |
| "rxdma2host-monitor-destination-mac2", |
| "rxdma2host-monitor-destination-mac1", |
| "ppdu-end-interrupts-mac3", |
| "ppdu-end-interrupts-mac2", |
| "ppdu-end-interrupts-mac1", |
| "rxdma2host-monitor-status-ring-mac3", |
| "rxdma2host-monitor-status-ring-mac2", |
| "rxdma2host-monitor-status-ring-mac1", |
| "host2rxdma-host-buf-ring-mac3", |
| "host2rxdma-host-buf-ring-mac2", |
| "host2rxdma-host-buf-ring-mac1", |
| "rxdma2host-destination-ring-mac3", |
| "rxdma2host-destination-ring-mac2", |
| "rxdma2host-destination-ring-mac1", |
| "host2tcl-input-ring4", |
| "host2tcl-input-ring3", |
| "host2tcl-input-ring2", |
| "host2tcl-input-ring1", |
| "wbm2host-tx-completions-ring3", |
| "wbm2host-tx-completions-ring2", |
| "wbm2host-tx-completions-ring1", |
| "tcl2host-status-ring"; |
| status = "disabled"; |
| }; |
| |
| wifi1: wifi1@c000000 { |
| compatible = "qcom,cnss-qcn6122", "qcom,qcn6122-wifi"; |
| msi-parent = <&v2m0>; |
| interrupts = <0 416 1>; |
| status = "disabled"; |
| }; |
| |
| wifi2: wifi2@c000000 { |
| compatible = "qcom,cnss-qcn6122", "qcom,qcn6122-wifi"; |
| msi-parent = <&v2m0>; |
| interrupts = <0 448 1>; |
| status = "disabled"; |
| }; |
| |
| wifi3: wifi3@f00000 { |
| compatible = "qcom,cnss-qcn9000"; |
| qcom,wlan-ramdump-dynamic = <0x400000>; |
| qrtr_node_id = <0x20>; |
| qca,auto-restart; |
| status = "disabled"; |
| }; |
| |
| wcss: wcss-smp2p { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <435>, <428>; |
| |
| interrupt-parent = <&intc>; |
| interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>; |
| |
| mboxes = <&apcs_glb 9>; |
| |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <1>; |
| |
| wcss_smp2p_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| qcom,smp2p-feature-ssr-ack; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| wcss_smp2p_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| nss-common { |
| compatible = "qcom,nss-common"; |
| reg = <0x01868010 0x01>; |
| reg-names = "nss-misc-reset"; |
| }; |
| |
| nss0: nss@40000000 { |
| compatible = "qcom,nss"; |
| interrupts = <0 402 0x1>, <0 401 0x1>, <0 400 0x1>, |
| <0 399 0x1>, <0 398 0x1>, <0 397 0x1>, |
| <0 396 0x1>, <0 395 0x1>; |
| reg = <0x07a00000 0x100>, <0x0b111000 0x1000>; |
| reg-names = "nphys", "qgic-phys"; |
| clocks = <&gcc GCC_UBI0_CFG_CLK>, |
| <&gcc GCC_UBI0_DBG_CLK>, |
| <&gcc GCC_UBI0_CORE_CLK>, |
| <&gcc GCC_UBI0_UTCM_CLK>, |
| <&gcc GCC_UBI0_AXI_CLK>, |
| <&gcc GCC_SNOC_UBI0_AXI_CLK>, |
| <&gcc GCC_UBI0_NC_AXI_CLK>; |
| clock-names = "nss-cfg-clk", "nss-dbg-clk", |
| "nss-core-clk", "nss-utcm-clk", |
| "nss-axi-clk", |
| "nss-snoc-axi-clk", |
| "nss-nc-axi-clk"; |
| qcom,id = <0>; |
| qcom,num-queue = <4>; |
| qcom,num-irq = <8>; |
| qcom,num-pri = <4>; |
| qcom,load-addr = <0x40000000>; |
| qcom,low-frequency = <850000000>; |
| qcom,mid-frequency = <850000000>; |
| qcom,max-frequency = <1000000000>; |
| qcom,ipv4-enabled; |
| qcom,ipv4-reasm-enabled; |
| qcom,ipv6-enabled; |
| qcom,ipv6-reasm-enabled; |
| qcom,tun6rd-enabled; |
| qcom,l2tpv2-enabled; |
| qcom,gre-enabled; |
| qcom,map-t-enabled; |
| qcom,pppoe-enabled; |
| qcom,pptp-enabled; |
| qcom,tunipip6-enabled; |
| qcom,shaping-enabled; |
| qcom,clmap-enabled; |
| qcom,vxlan-enabled; |
| qcom,match-enabled; |
| qcom,mirror-enabled; |
| qcom,crypto-enabled; |
| qcom,ipsec-enabled; |
| qcom,wlanredirect-enabled; |
| qcom,gre-redir-enabled; |
| qcom,gre-redir-mark-enabled; |
| qcom,portid-enabled; |
| qcom,wlan-dataplane-offload-enabled; |
| qcom,pvxlan-enabled; |
| qcom,udp-st-enabled; |
| }; |
| |
| scm_restart_reason: scm_restart_reason { |
| compatible = "qti,scm_restart_reason"; |
| dload_status = <0>; |
| dload_warm_status = <0>; |
| }; |
| |
| apcs: syscon@b111000 { |
| compatible = "syscon"; |
| reg = <0x0B111000 0x1000>; |
| }; |
| |
| bt: bt@7000000 { |
| compatible = "qcom,bt"; |
| firmware = "IPQ5018/bt_fw_patch.mdt"; |
| |
| reg = <0x01943008 0x8>; |
| reg-names = "bt_warm_rst"; |
| |
| qcom,ipc = <&apcs 8 23>; |
| interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>; |
| |
| resets = <&gcc GCC_BTSS_BCR>; |
| reset-names = "btss_reset"; |
| |
| clocks = <&gcc GCC_BTSS_LPO_CLK>; |
| clock-names = "lpo_clk"; |
| |
| memory-region = <&bt_region>; |
| status = "ok"; |
| }; |
| |
| apss_clk: qcom,apss_clk@b111000 { |
| compatible = "qcom,apss-ipq5018"; |
| reg = <0xb111000 0x6000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| acc0:clock-controller@b188000 { |
| compatible = "qcom,arm-cortex-acc"; |
| reg = <0x0b188000 0x1000>; |
| }; |
| |
| acc1:clock-controller@b198000 { |
| compatible = "qcom,arm-cortex-acc"; |
| reg = <0x0b198000 0x1000>; |
| }; |
| |
| qcom_rng: qrng@e1000 { |
| compatible = "qcom,msm-rng"; |
| reg = <0xe3000 0x1000>; |
| clocks = <&gcc GCC_PRNG_AHB_CLK>; |
| clock-names = "km_clk_src"; |
| qcom,no-qrng-config; |
| qcom,no-clock-support; |
| status = "ok"; |
| }; |
| |
| tcsr: syscon@1937000 { |
| reg = <0x1937000 0x30000>; |
| }; |
| }; |
| |
| qcom,test@0 { |
| compatible = "qcom,testmhi"; |
| qcom,wlan-ramdump-dynamic = <0x400000>; |
| status = "disabled"; |
| }; |
| |
| ctx_save: ctx-save { |
| compatible = "qti,ctxt-save-ipq5018"; |
| }; |
| |
| qti,sps { |
| compatible = "qti,msm-sps-4k"; |
| qti,pipe-attr-ee; |
| }; |
| }; |
| |
| #include "ipq5018-coresight.dtsi" |
| #include "ipq5018-thermal.dtsi" |
