drivers/net/wireless/ath/ath11k/core.h

/* SPDX-License-Identifier: BSD-3-Clause-Clear */
/*
 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
 */

#ifndef ATH11K_CORE_H
#define ATH11K_CORE_H

#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/bitfield.h>
#include <linux/average.h>
#include "qmi.h"
#include "htc.h"
#include "pktlog.h"
#include "wmi.h"
#include "hal.h"
#include "dp.h"
#include "ce.h"
#include "mac.h"
#include "hw.h"
#include "hal_rx.h"
#include "reg.h"
#include "thermal.h"
#include "dbring.h"
#include "spectral.h"
#include "vendor.h"
#include "rx_desc.h"
#include "nss.h"
#include "cfr.h"
#include "smart_ant.h"
#include "peer.h"

extern unsigned int ath11k_skip_radio;
extern wait_queue_head_t ath11k_radio_prb_wq;
extern bool dev_init_progress;
extern struct mutex dev_init_lock;
extern unsigned int ath11k_afc_test_enabled;

#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)

#define ATH11K_TX_MGMT_NUM_PENDING_MAX	512

#define ATH11K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64

#define ATH11K_SCAN_CHANNEL_SWITCH_WMI_EVT_OVERHEAD 10 /* msec */

/* Pending management packets threshold for dropping probe responses */
#define ATH11K_PRB_RSP_DROP_THRESHOLD ((ATH11K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4)

#define ATH11K_RESET_TIMEOUT_HZ (10 * HZ)
#define ATH11K_CONNECTION_LOSS_HZ (3 * HZ)
#define ATH11K_INVALID_HW_MAC_ID	0xFF
#define ATH11K_RX_RATE_TABLE_NUM 320
#define ATH11K_RX_RATE_TABLE_11AX_NUM 576

extern unsigned int ath11k_frame_mode;

#define ATH11K_MON_TIMER_INTERVAL  10
#define ATH11K_AHB_PROBE_SEQ_TIMEOUT  (2 * HZ)

/* Shift value to set the dest rings hash map to the dest control register */
#define HAL_REO_DEST_RING_CTRL_HASH_RING_SHIFT			8
#define HAL_IPQ5018_REO_DEST_RING_CTRL_HASH_RING_SHIFT		0

enum ath11k_supported_bw {
	ATH11K_BW_20	= 0,
	ATH11K_BW_40	= 1,
	ATH11K_BW_80	= 2,
	ATH11K_BW_160	= 3,
};

enum wme_ac {
	WME_AC_BE,
	WME_AC_BK,
	WME_AC_VI,
	WME_AC_VO,
	WME_NUM_AC
};

#define ATH11K_HT_MCS_MAX	7
#define ATH11K_VHT_MCS_MAX	9
#define ATH11K_HE_MCS_MAX	11
#define ATH11K_TID_MAX 8

enum ath11k_crypt_mode {
	/* Only use hardware crypto engine */
	ATH11K_CRYPT_MODE_HW,
	/* Only use software crypto */
	ATH11K_CRYPT_MODE_SW,
};

#define ATH11K_GROUP_KEYS_NUM_MAX	128
#define ATH11K_FREE_GROUP_IDX_MAP_BITS	32
#define ATH11K_FREE_GROUP_IDX_MAP_MAX	(ATH11K_GROUP_KEYS_NUM_MAX /	\
					 ATH11K_FREE_GROUP_IDX_MAP_BITS)
#define ATH11K_MAX_RETRY_COUNT         30

static inline enum wme_ac ath11k_tid_to_ac(u32 tid)
{
	return (((tid == 0) || (tid == 3)) ? WME_AC_BE :
		((tid == 1) || (tid == 2)) ? WME_AC_BK :
		((tid == 4) || (tid == 5)) ? WME_AC_VI :
		WME_AC_VO);
}

enum ath11k_skb_flags {
	ATH11K_SKB_HW_80211_ENCAP = BIT(0),
	ATH11K_SKB_CIPHER_SET = BIT(1),
	ATH11K_SKB_TX_STATUS = BIT(2),
	ATH11K_SKB_F_NOACK_TID = BIT(3),
};

struct ath11k_skb_cb {
	dma_addr_t paddr;
	u8 eid;
	u8 flags;
	u32 cipher;
	struct ath11k *ar;
	struct ieee80211_vif *vif;
} __packed;

struct ath11k_skb_rxcb {
	dma_addr_t paddr;
	bool is_first_msdu;
	bool is_last_msdu;
	bool is_continuation;
	bool is_mcbc;
	bool is_eapol_tkip;
	struct hal_rx_desc *rx_desc;
	u8 err_rel_src;
	u8 err_code;
	u8 mac_id;
	u8 unmapped;
	u8 is_frag;
	u8 tid;
	u16 peer_id;
	u16 seq_no;
	u16 msdu_len;
	struct napi_struct *napi;
};

enum ath11k_hw_rev {
	ATH11K_HW_IPQ8074,
	ATH11K_HW_QCA6390_HW20,
	ATH11K_HW_IPQ6018_HW10,
	ATH11K_HW_QCN9074_HW10,
	ATH11K_HW_IPQ5018,
	ATH11K_HW_QCN6122,
};

enum ath11k_firmware_mode {
	/* the default mode, standard 802.11 functionality */
	ATH11K_FIRMWARE_MODE_NORMAL,

	/* factory tests etc */
	ATH11K_FIRMWARE_MODE_FTM,

	/* Cold boot calibration */
	ATH11K_FIRMWARE_MODE_COLD_BOOT = 7,
};

extern bool ath11k_cold_boot_cal;

#define ATH11K_IRQ_NUM_MAX 52
#define ATH11K_EXT_IRQ_NUM_MAX	16

struct ath11k_ext_irq_grp {
	struct ath11k_base *ab;
	u32 irqs[ATH11K_EXT_IRQ_NUM_MAX];
	u32 num_irq;
	u32 grp_id;
	u64 timestamp;
	struct napi_struct napi;
	struct net_device napi_ndev;
};

#define HEHANDLE_CAP_PHYINFO_SIZE       3
#define HECAP_PHYINFO_SIZE              9
#define HECAP_MACINFO_SIZE              5
#define HECAP_TXRX_MCS_NSS_SIZE         2
#define HECAP_PPET16_PPET8_MAX_SIZE     25

#define HE_PPET16_PPET8_SIZE            8

/* 802.11ax PPE (PPDU packet Extension) threshold */
struct he_ppe_threshold {
	u32 numss_m1;
	u32 ru_mask;
	u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE];
};

struct ath11k_he {
	u8 hecap_macinfo[HECAP_MACINFO_SIZE];
	u32 hecap_rxmcsnssmap;
	u32 hecap_txmcsnssmap;
	u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE];
	struct he_ppe_threshold   hecap_ppet;
	u32 heop_param;
};

#define MAX_RADIOS 3

enum {
	WMI_HOST_TP_SCALE_MAX   = 0,
	WMI_HOST_TP_SCALE_50    = 1,
	WMI_HOST_TP_SCALE_25    = 2,
	WMI_HOST_TP_SCALE_12    = 3,
	WMI_HOST_TP_SCALE_MIN   = 4,
	WMI_HOST_TP_SCALE_SIZE   = 5,
};

enum ath11k_scan_state {
	ATH11K_SCAN_IDLE,
	ATH11K_SCAN_STARTING,
	ATH11K_SCAN_RUNNING,
	ATH11K_SCAN_ABORTING,
};

enum ath11k_dev_flags {
	ATH11K_CAC_RUNNING,
	ATH11K_FLAG_CORE_REGISTERED,
	ATH11K_FLAG_CRASH_FLUSH,
	ATH11K_FLAG_RAW_MODE,
	ATH11K_FLAG_HW_CRYPTO_DISABLED,
	ATH11K_FLAG_BTCOEX,
	ATH11K_FLAG_RECOVERY,
	ATH11K_FLAG_UNREGISTERING,
	ATH11K_FLAG_REGISTERED,
	ATH11K_FLAG_QMI_FAIL,
	ATH11K_FLAG_HTC_SUSPEND_COMPLETE,
	ATH11K_FLAG_FW_RESTART_FOR_HOST,
};

#define ATH11K_STATS_MGMT_FRM_TYPE_MAX 16

struct ath11k_mgmt_frame_stats {
	u32 tx_succ_cnt[ATH11K_STATS_MGMT_FRM_TYPE_MAX];
	u32 tx_fail_cnt[ATH11K_STATS_MGMT_FRM_TYPE_MAX];
	u32 rx_cnt[ATH11K_STATS_MGMT_FRM_TYPE_MAX];
	u32 tx_compl_succ[ATH11K_STATS_MGMT_FRM_TYPE_MAX];
	u32 tx_compl_fail[ATH11K_STATS_MGMT_FRM_TYPE_MAX];
};

struct ath11k_mac_filter {
	struct list_head list;
	u8 peer_mac[ETH_ALEN];
};

struct ath11k_tid_qos_config {
	int noack;
	int retry_long;
	int aggr_ctrl;
	int amsdu_count;
	int ampdu_count;
	u8 rate_ctrl;
	u32 rate_code;
	int rtscts;
	int ext_tid_cfg_bitmap;
};

/**
 * struct chan_power_info - TPE containing power info per channel chunk
 * @chan_cfreq: channel center freq (MHz)
 * e.g.
 * channel 37/20MHz,  it is 6135
 * channel 37/40MHz,  it is 6125
 * channel 37/80MHz,  it is 6145
 * channel 37/160MHz, it is 6185
 * @tx_power: transmit power (dBm)
 */
struct chan_power_info {
	u16 chan_cfreq;
	s8 tx_power;
};

/**
 * struct reg_tpc_power_info - regulatory TPC power info
 * @is_psd_power: is PSD power or not
 * @eirp_power: Maximum EIRP power (dBm), valid only if power is PSD
 * @power_type_6g: type of power (SP/LPI/VLP)
 * @num_pwr_levels: number of power levels
 * @reg_max: Array of maximum TX power (dBm) per PSD value
 * @ap_constraint_power: AP constraint power (dBm)
 * @tpe: TPE values processed from TPE IE
 * @chan_power_info: power info to send to FW
 */
struct ath11k_reg_tpc_power_info {
	bool is_psd_power;
	u8 eirp_power;
	enum wmi_reg_6g_ap_type power_type_6g;
	u8 num_pwr_levels;
	u8 reg_max[IEEE80211_MAX_NUM_PWR_LEVEL];
	u8 ap_constraint_power;
	s8 tpe[IEEE80211_MAX_NUM_PWR_LEVEL];
	struct chan_power_info chan_power_info[IEEE80211_MAX_NUM_PWR_LEVEL];
};

struct ath11k_vif {
	u32 vdev_id;
	enum wmi_vdev_type vdev_type;
	enum wmi_vdev_subtype vdev_subtype;
	u32 beacon_interval;
	u32 dtim_period;
	u16 ast_hash;
	u16 ast_idx;
	u16 tcl_metadata;
	u8 hal_addr_search_flags;
	u8 search_type;

	struct ath11k *ar;
	struct ieee80211_vif *vif;

	u16 tx_seq_no;
	struct wmi_wmm_params_all_arg wmm_params;
	struct list_head list;
	union {
		struct {
			u32 uapsd;
		} sta;
		struct {
			/* 127 stations; wmi limit */
			u8 tim_bitmap[16];
			u8 tim_len;
			u32 ssid_len;
			u8 ssid[IEEE80211_MAX_SSID_LEN];
			bool hidden_ssid;
			/* P2P_IE with NoA attribute for P2P_GO case */
			u32 noa_len;
			u8 *noa_data;
		} ap;
	} u;

	bool is_started;
	bool is_up;
	bool ftm_responder;
	bool spectral_enabled;
	u32 aid;
	u8 bssid[ETH_ALEN];
	struct cfg80211_bitrate_mask bitrate_mask;
	struct delayed_work connection_loss_work;
	int num_legacy_stations;
	int rtscts_prot_mode;
	int txpower;
	bool rsnie_present;
	bool wpaie_present;
	bool bcca_zero_sent;
	bool do_not_send_tmpl;
	u32 vht_cap;
	struct ieee80211_chanctx_conf chanctx;
	struct ath11k_reg_tpc_power_info reg_tpc_info;
	struct dentry *debugfs_twt;
	struct ath11k_mgmt_frame_stats mgmt_stats;
	/* protected by conf_mutex */
	struct list_head mac_filters;
	u32 mac_filter_count;
	u64 wbm_tx_comp_stats[HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX];
	struct arvif_nss nss;
	struct list_head ap_vlan_arvifs;
	/* VLAN keyidx map required for Dynamic VLAN */
	u16 *vlan_keyid_map;
	u32 tid_conf_changed[ATH11K_TID_MAX];
	struct ath11k_tid_qos_config tid_cfg[ATH11K_TID_MAX];
	u32 tids_rst;
	u64 tbtt_offset;
	struct work_struct update_bcn_template_work;
	DECLARE_BITMAP(free_groupidx_map, ATH11K_GROUP_KEYS_NUM_MAX);
};

struct ath11k_vif_iter {
	u32 vdev_id;
	struct ath11k_vif *arvif;
};

struct ath11k_rx_peer_rate_stats {
	u64 ht_mcs_count[HAL_RX_MAX_MCS_HT + 1];
	u64 vht_mcs_count[HAL_RX_MAX_MCS_VHT + 1];
	u64 he_mcs_count[HAL_RX_MAX_MCS_HE + 1];
	u64 nss_count[HAL_RX_MAX_NSS];
	u64 bw_count[HAL_RX_BW_MAX];
	u64 gi_count[HAL_RX_GI_MAX];
	u64 legacy_count[HAL_RX_MAX_NUM_LEGACY_RATES];
	u64 rx_rate[ATH11K_RX_RATE_TABLE_11AX_NUM];
};

struct ath11k_rx_peer_stats {
	u64 num_msdu;
	u64 num_mpdu_fcs_ok;
	u64 num_mpdu_fcs_err;
	u64 tcp_msdu_count;
	u64 udp_msdu_count;
	u64 other_msdu_count;
	u64 ampdu_msdu_count;
	u64 non_ampdu_msdu_count;
	u64 stbc_count;
	u64 beamformed_count;
	u64 coding_count[HAL_RX_SU_MU_CODING_MAX];
	u64 tid_count[IEEE80211_NUM_TIDS + 1];
	u64 pream_cnt[HAL_RX_PREAMBLE_MAX];
	u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX];
	u64 rx_duration;
	u64 dcm_count;
	u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX];
	struct ath11k_rx_peer_rate_stats pkt_stats;
	struct ath11k_rx_peer_rate_stats byte_stats;
};

#define ATH11K_HE_MCS_NUM       12
#define ATH11K_VHT_MCS_NUM      10
#define ATH11K_BW_NUM           4
#define ATH11K_NSS_NUM          4
#define ATH11K_LEGACY_NUM       12
#define ATH11K_GI_NUM           4
#define ATH11K_HT_MCS_NUM       32

enum ath11k_pkt_rx_err {
	ATH11K_PKT_RX_ERR_FCS,
	ATH11K_PKT_RX_ERR_TKIP,
	ATH11K_PKT_RX_ERR_CRYPT,
	ATH11K_PKT_RX_ERR_PEER_IDX_INVAL,
	ATH11K_PKT_RX_ERR_MAX,
};

enum ath11k_ampdu_subfrm_num {
	ATH11K_AMPDU_SUBFRM_NUM_10,
	ATH11K_AMPDU_SUBFRM_NUM_20,
	ATH11K_AMPDU_SUBFRM_NUM_30,
	ATH11K_AMPDU_SUBFRM_NUM_40,
	ATH11K_AMPDU_SUBFRM_NUM_50,
	ATH11K_AMPDU_SUBFRM_NUM_60,
	ATH11K_AMPDU_SUBFRM_NUM_MORE,
	ATH11K_AMPDU_SUBFRM_NUM_MAX,
};

enum ath11k_amsdu_subfrm_num {
	ATH11K_AMSDU_SUBFRM_NUM_1,
	ATH11K_AMSDU_SUBFRM_NUM_2,
	ATH11K_AMSDU_SUBFRM_NUM_3,
	ATH11K_AMSDU_SUBFRM_NUM_4,
	ATH11K_AMSDU_SUBFRM_NUM_MORE,
	ATH11K_AMSDU_SUBFRM_NUM_MAX,
};

enum ath11k_counter_type {
	ATH11K_COUNTER_TYPE_BYTES,
	ATH11K_COUNTER_TYPE_PKTS,
	ATH11K_COUNTER_TYPE_MAX,
};

enum ath11k_stats_type {
	ATH11K_STATS_TYPE_SUCC,
	ATH11K_STATS_TYPE_FAIL,
	ATH11K_STATS_TYPE_RETRY,
	ATH11K_STATS_TYPE_AMPDU,
	ATH11K_STATS_TYPE_MAX,
};

struct ath11k_htt_data_stats {
	u64 legacy[ATH11K_COUNTER_TYPE_MAX][ATH11K_LEGACY_NUM];
	u64 ht[ATH11K_COUNTER_TYPE_MAX][ATH11K_HT_MCS_NUM];
	u64 vht[ATH11K_COUNTER_TYPE_MAX][ATH11K_VHT_MCS_NUM];
	u64 he[ATH11K_COUNTER_TYPE_MAX][ATH11K_HE_MCS_NUM];
	u64 bw[ATH11K_COUNTER_TYPE_MAX][ATH11K_BW_NUM];
	u64 nss[ATH11K_COUNTER_TYPE_MAX][ATH11K_NSS_NUM];
	u64 gi[ATH11K_COUNTER_TYPE_MAX][ATH11K_GI_NUM];
	u64 transmit_type[ATH11K_COUNTER_TYPE_MAX][HAL_RX_RECEPTION_TYPE_MAX];
	u64 ru_loc[ATH11K_COUNTER_TYPE_MAX][HAL_RX_RU_ALLOC_TYPE_MAX];
};

struct ath11k_wbm_tx_stats {
	u64 wbm_tx_comp_stats[HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX];
};

struct ath11k_htt_tx_stats {
	struct ath11k_htt_data_stats stats[ATH11K_STATS_TYPE_MAX];
	u64 tx_duration;
	u64 ba_fails;
	u64 ack_fails;
	u16 ru_start;
	u16 ru_tones;
	u32 mu_group[MAX_MU_GROUP_ID];
};

struct ath11k_per_peer_cfr_capture {
	u32 cfr_enable;
	u32 cfr_period;
	u32 cfr_bandwidth;
	u32 cfr_method;
};

struct ath11k_per_ppdu_tx_stats {
	u16 succ_pkts;
	u16 failed_pkts;
	u16 retry_pkts;
	u32 succ_bytes;
	u32 failed_bytes;
	u32 retry_bytes;
};

struct ath11k_driver_tx_pkts_flow {
	atomic_t pkts_in;
	atomic_t pkts_out;
};

struct ath11k_driver_rx_pkts_flow {
	atomic_t pkts_frm_hw;
	atomic_t pkts_out;
	atomic_t pkts_out_to_netif;
};

DECLARE_EWMA(sta_per, 8, 16)
DECLARE_EWMA(sta_ber, 8, 16)
DECLARE_EWMA(avg_rssi, 10, 8)

struct ath11k_sta {
	struct ath11k_vif *arvif;

	/* the following are protected by ar->data_lock */
	u32 changed; /* IEEE80211_RC_* */
	u32 bw;
	u32 nss;
	u32 smps;
	enum hal_pn_type pn_type;

	struct work_struct update_wk;
	struct work_struct use_4addr_wk;
	struct rate_info txrate;
	struct rate_info last_txrate;
	u64 rx_duration;
	u64 tx_duration;
	u32 tx_rts_retry_count;
	u8 rssi_comb;
	u32 tx_retry_count;
	struct ewma_avg_rssi avg_rssi;
	struct ath11k_htt_tx_stats *tx_stats;
	struct ath11k_rx_peer_stats *rx_stats;

#ifdef CONFIG_MAC80211_DEBUGFS
	/* protected by conf_mutex */
	bool aggr_mode;
#endif

	bool use_4addr_set;
#ifdef CONFIG_ATH11K_NSS_SUPPORT
	struct ath11k_nss_sta_stats *nss_stats;
#endif
	struct ath11k_driver_tx_pkts_flow drv_tx_pkts;
	struct ath11k_driver_rx_pkts_flow drv_rx_pkts;
	u16 tcl_metadata;
	/* Protected with ar->data_lock */
	u32 peer_ps_state;
	u32 ps_start_time;
	u32 ps_start_jiffies;
	u8 peer_current_ps_valid;
	u32 ps_total_duration;
	u8 num_spatial_strm_mask;
	u8 tx_pwr_multiplier;
	u8 chain_enable_bits;
	u8 ampdu_subframe_count;
	u32 tx_pwr[HTT_PPDU_STATS_USER_CMN_TX_PWR_ARR_SIZE];
	struct ewma_sta_per per;
	u64 fail_pkts;
	u64 succ_pkts;
	u64 drop_pkts;
	u64 msdu_cnt[ATH11K_TID_MAX];
	u64 mpdu_cnt[ATH11K_TID_MAX];
	u64 ppdu_cnt[ATH11K_TID_MAX];
	/* pkt count for packet error rate computation*/
	u32 per_fail_pkts;
	u32 per_succ_pkts;
	struct ewma_sta_ber ber;
	u64 succ_bytes;
	u64 fail_bytes;
	u64 drop_bytes;
	/*bytes count for bit error rate computation*/
	u32 ber_succ_bytes;
	u32 ber_fail_bytes;
	u32 last_tx_pkt_bw;

	u8 sta_kickout;
	unsigned long sta_kickout_timeout;

	struct work_struct tid_config_wk;
	struct ath11k_tid_qos_config tid_cfg[ATH11K_TID_MAX];
	struct ath11k_wbm_tx_stats *wbm_tx_stats;
#ifdef CONFIG_ATH11K_CFR
	struct ath11k_per_peer_cfr_capture cfr_capture;
#endif
	struct ath11k_smart_ant_sta *smart_ant_sta;
	struct completion disassoc_comp;
	bool tx_disassoc;
	u32 bw_last;
};

#define ATH11K_HALF_20MHZ_BW 10
#define ATH11K_5G_MIN_CENTER 4900
#define ATH11K_5G_MAX_CENTER 5920
#define ATH11K_6G_MIN_CENTER 5935
#define ATH11K_6G_MAX_CENTER 7115
#define ATH11K_MIN_5G_FREQ (ATH11K_5G_MIN_CENTER - ATH11K_HALF_20MHZ_BW)
#define ATH11K_MAX_5G_FREQ (ATH11K_5G_MAX_CENTER + ATH11K_HALF_20MHZ_BW)
#define ATH11K_MIN_6G_FREQ (ATH11K_6G_MIN_CENTER - ATH11K_HALF_20MHZ_BW)
#define ATH11K_MAX_6G_FREQ (ATH11K_6G_MAX_CENTER + ATH11K_HALF_20MHZ_BW)
#define ATH11K_NUM_CHANS 102
#define ATH11K_MAX_5G_CHAN 177

enum ath11k_state {
	ATH11K_STATE_OFF,
	ATH11K_STATE_ON,
	ATH11K_STATE_RESTARTING,
	ATH11K_STATE_RESTARTED,
	ATH11K_STATE_WEDGED,
	ATH11K_STATE_TM,
	/* Add other states as required */
};

/* Antenna noise floor */
#define ATH11K_DEFAULT_NOISE_FLOOR -95

struct ath11k_ftm_event_obj {
	u32 data_pos;
	u32 expected_seq;
	u8 *eventdata;
};

struct ath11k_fw_stats {
	struct dentry *debugfs_fwstats;
	u32 pdev_id;
	u32 stats_id;
	struct list_head pdevs;
	struct list_head vdevs;
	struct list_head bcn;
};

struct ath11k_dbg_htt_stats {
	u8 type;
	u8 reset;
	struct debug_htt_stats_req *stats_req;
	/* protects shared stats req buffer */
	spinlock_t lock;
};

#define ATH11K_MAX_COEX_PRIORITY_LEVEL       3
#define ATH11K_FTMR_MAX_NUM_VDEVS 		20

#define ATH11K_DELAY_STATS_SCALED_BINS		20
#define ATH11K_TX_DELAY_STATS_MAX_BINS		(ATH11K_DELAY_STATS_SCALED_BINS + 1)
struct ath11k_tx_delay_stats {
	/* histogram of tx delay with 21 bins. The bucket size scales
	 * exponentially, from 1ms to 1024ms. Each power-of-two bucket that
	 * spans greater than 1ms is subdivided into two bins (e.g. the range
	 * [2, 4) is broken into bins [2, 3) and [3, 4), while the range
	 * [32, 64) is broken into bins [32, 48) and [48, 64), etc.).
	 * Each bin is a counter of tx packet with delay in that range.
	 */
	u32 counts[ATH11K_TX_DELAY_STATS_MAX_BINS];
};

struct ath11k_debug {
	struct dentry *debugfs_pdev;
	struct ath11k_dbg_htt_stats htt_stats;
	u32 extd_tx_stats;
	struct ath11k_fw_stats fw_stats;
	struct ath11k_tx_delay_stats *tx_delay_stats[IEEE80211_NUM_TIDS];

	/* debug tx_work */
	u64 num_tx_work;
	u64 num_tx_wmi_mgmt;

	u32 extd_rx_stats;
	u32 pktlog_filter;
	u32 pktlog_mode;
	u32 pktlog_peer_valid;
	u8 pktlog_peer_addr[ETH_ALEN];
#ifdef CONFIG_ATH11K_PKTLOG
	struct dentry *debugfs_pktlog;
	struct ath_pktlog pktlog;
	bool is_pkt_logging;
#endif
	u32 rx_filter;
	bool enable_m3_dump;
	bool burst_enabled;
	u32 mem_addr;
	struct list_head wmi_list;
	struct completion wmi_ctrl_path_stats_rcvd;
	u32 wmi_ctrl_path_stats_tagid;
	struct ath11k_db_module_debug *module_debug[WMI_DIRECT_BUF_MAX];
	bool disable_dynamic_bw;
	struct dentry *debugfs_smartant;
	u32 coex_priority_level[ATH11K_MAX_COEX_PRIORITY_LEVEL];
	u32 burst_dur[4];
	int ftmr_enabled[ATH11K_FTMR_MAX_NUM_VDEVS];
};

struct ath11k_per_peer_tx_stats {
	u32 succ_bytes;
	u32 retry_bytes;
	u32 failed_bytes;
	u32 duration;
	u16 succ_pkts;
	u16 mpdu_cnt;
	u16 retry_pkts;
	u16 failed_pkts;
	u16 ru_start;
	u16 ru_tones;
	u8 ba_fails;
	u8 ppdu_type;
	u32 mu_grpid;
	u32 mu_pos;
	bool is_ampdu;
};

#define ATH11K_FLUSH_TIMEOUT (5 * HZ)
#define ATH11K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ)

struct ath11k_coex_info {
	bool coex_support;
	u32 pta_num;
	u32 coex_mode;
	u32 bt_active_time_slot;
	u32 bt_priority_time_slot;
	u32 coex_algo_type;
	u32 pta_priority;
	u32 wlan_prio_mask;
	u32 wlan_weight;
	u32 duty_cycle;
	u32 wlan_duration;
};

enum ath11k_ap_ps_state {
	ATH11K_AP_PS_STATE_OFF,
	ATH11K_AP_PS_STATE_ON,
};

enum coex_algo {
	COEX_ALGO_UNCONS_FREERUN = 0,
	COEX_ALGO_FREERUN,
	COEX_ALGO_OCS,
	COEX_ALGO_MAX_SUPPORTED,
};

struct ath11k_rx_buf_id {
	struct list_head list;
	int used_buf_id;
};

enum ath11k_afc_event_state {
	ATH11K_AFC_EVENT_POWER_INFO   = 1,
	ATH11K_AFC_EVENT_TIMER_EXPIRY = 2,
};

enum ath11k_afc_expiry_event_subtype {
	REG_AFC_EXPIRY_EVENT_START = 1,
	REG_AFC_EXPIRY_EVENT_RENEW = 2,
	REG_AFC_EXPIRY_EVENT_SWITCH_TO_LPI = 3,
};

enum ath11k_afc_power_event_status_code {
	REG_FW_AFC_POWER_EVENT_SUCCESS = 0,
	REG_FW_AFC_POWER_EVENT_RESP_NOT_RECEIVED = 1,
	REG_FW_AFC_POWER_EVENT_RESP_PARSING_FAILURE = 2,
	REG_FW_AFC_POWER_EVENT_FAILURE = 3,
};

enum ath11k_serv_resp_code {
	REG_AFC_SERV_RESP_GENERAL_FAILURE = -1,
	REG_AFC_SERV_RESP_SUCCESS = 0,
	REG_AFC_SERV_RESP_VERSION_NOT_SUPPORTED = 100,
	REG_AFC_SERV_RESP_DEVICE_UNALLOWED = 101,
	REG_AFC_SERV_RESP_MISSING_PARAM = 102,
	REG_AFC_SERV_RESP_INVALID_VALUE = 103,
	REG_AFC_SERV_RESP_UNEXPECTED_PARAM = 106,
	REG_AFC_SERV_RESP_UNSUPPORTED_SPECTRUM = 300,
};

struct ath11k_afc_freq_obj {
	u32 low_freq;
	u32 high_freq;
	s16 max_psd;
};

struct ath11k_chan_eirp_obj {
	u8 cfi;
	u16 eirp_power;
};

struct ath11k_afc_chan_obj {
	u8 global_opclass;
	u8 num_chans;
	struct ath11k_chan_eirp_obj *chan_eirp_info;
};

struct ath11k_afc_sp_reg_info {
	u32 resp_id;
	enum ath11k_afc_power_event_status_code fw_status_code;
	enum ath11k_serv_resp_code serv_resp_code;
	u32 afc_wfa_version;
	u32 avail_exp_time_d;
	u32 avail_exp_time_t;
	u8 num_freq_objs;
	u8 num_chan_objs;
	struct ath11k_afc_freq_obj *afc_freq_info;
	struct ath11k_afc_chan_obj *afc_chan_info;
};

struct ath11k_afc_info {
	enum ath11k_afc_event_state event_type;
	u32 request_id;
	enum ath11k_afc_expiry_event_subtype event_subtype;
	u32 afc_wfa_version;
	bool is_6g_afc_expiry_event_received;
	bool is_6g_afc_power_event_received;
	bool switch_to_lpi_indication_received;
	struct ath11k_afc_sp_reg_info *afc_reg_info;
	bool afc_regdom_configured;
};

enum mon_status_buf_done {
	MON_STATUS_BUF_DONE = 0,
	MON_STATUS_NO_BUF_DONE = 1,
	MON_STATUS_BUF_DONE_NEXT = 2,
};

struct ath11k {
	struct ath11k_base *ab;
	struct ath11k_pdev *pdev;
	struct ieee80211_hw *hw;
	struct ieee80211_ops *ops;
	struct ath11k_pdev_wmi *wmi;
	struct ath11k_nss nss;
	struct ath11k_peer *bss_peer;
	struct ath11k_pdev_dp dp;
	u8 mac_addr[ETH_ALEN];
	u32 ht_cap_info;
	u32 vht_cap_info;
	struct ath11k_he ar_he;
	enum ath11k_state state;
	bool supports_6ghz;
	struct {
		struct completion started;
		struct completion completed;
		struct completion on_channel;
		struct delayed_work timeout;
		enum ath11k_scan_state state;
		bool is_roc;
		int vdev_id;
		int roc_freq;
		bool roc_notify;
	} scan;

	struct {
		struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
		struct ieee80211_sband_iftype_data
			iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];
	} mac;

	unsigned long dev_flags;
	unsigned int filter_flags;
	u32 min_tx_power;
	u32 max_tx_power;
	u32 txpower_limit_2g;
	u32 txpower_limit_5g;
	u32 txpower_limit_6g;
	u32 txpower_scale;
	u32 power_scale;
	u32 chan_tx_pwr;
	s32 chan_noise_floor;
	u32 num_stations;
	u32 max_num_stations;
	bool monitor_conf_enabled;
	bool monitor_started;
	/* To synchronize concurrent synchronous mac80211 callback operations,
	 * concurrent debugfs configuration and concurrent FW statistics events.
	 */
	struct mutex conf_mutex;
	/* protects the radio specific data like debug stats, ppdu_stats_info stats,
	 * vdev_stop_status info, scan data, ath11k_sta info, ath11k_vif info,
	 * channel context data, survey info, test mode data.
	 */
	spinlock_t data_lock;

	struct list_head arvifs;
	/* should never be NULL; needed for regular htt rx */
	struct ieee80211_channel *rx_channel;

	/* valid during scan; needed for mgmt rx during scan */
	struct ieee80211_channel *scan_channel;

	u8 cfg_tx_chainmask;
	u8 cfg_rx_chainmask;
	u8 num_rx_chains;
	u8 num_tx_chains;
	/* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */
	u8 pdev_idx;
	u8 lmac_id;

	struct completion peer_assoc_done;
	struct completion peer_delete_done;

	int install_key_status;
	struct completion install_key_done;

	int last_wmi_vdev_start_status;
	struct completion vdev_setup_done;
	struct completion vdev_delete_done;

	int num_peers;
	int max_num_peers;
	u32 num_started_vdevs;
	u32 num_created_vdevs;
	u32 num_mesh_vdevs;
	unsigned long long allocated_vdev_map;

	struct idr txmgmt_idr;
	/* protects txmgmt_idr data */
	spinlock_t txmgmt_idr_lock;
	atomic_t num_pending_mgmt_tx;

	/* cycle count is reported twice for each visited channel during scan.
	 * access protected by data_lock
	 */
	u32 survey_last_rx_clear_count;
	u32 survey_last_cycle_count;

	/* Channel info events are expected to come in pairs without and with
	 * COMPLETE flag set respectively for each channel visit during scan.
	 *
	 * However there are deviations from this rule. This flag is used to
	 * avoid reporting garbage data.
	 */
	bool ch_info_can_report_survey;
	struct survey_info survey[ATH11K_NUM_CHANS];
	struct completion bss_survey_done;

	struct work_struct regd_update_work;

	struct work_struct wmi_mgmt_tx_work;
	struct sk_buff_head wmi_mgmt_tx_queue;

	struct ath11k_per_peer_tx_stats peer_tx_stats;
	struct list_head ppdu_stats_info;
	u32 ppdu_stat_list_depth;

	struct ath11k_per_peer_tx_stats cached_stats;
	u32 last_ppdu_id;
	u32 cached_ppdu_id;
	int monitor_vdev_id;

	struct ath11k_coex_info coex;
	u8 tpc_stats_type;
	/* tpc_stats ptr is protected by data lock */
	struct wmi_tpc_stats_event *tpc_stats;
	struct completion tpc_complete;
	bool tpc_request;
#ifdef CONFIG_ATH11K_DEBUGFS
	struct ath11k_debug debug;
#endif
#ifdef CONFIG_ATH11K_SPECTRAL
	struct ath11k_spectral spectral;
#endif
	bool dfs_block_radar_events;
	struct ath11k_thermal thermal;
	s8 max_allowed_tx_power;
	struct completion fw_mode_reset;
	u8 ftm_msgref;
	int ap_ps_enabled;
	enum ath11k_ap_ps_state ap_ps_state;

	bool monitor_vdev_created;

	int cookie_pdev_id;

	/* protected by conf_mutex */
	u8 ps_state_enable;
	u8 ps_timekeeper_enable;
	u8 reset_ps_duration;
#ifdef CONFIG_ATH11K_CFR
	struct ath11k_cfr cfr;
#endif
	u8 cfr_enabled;
	bool ani_enabled;
	enum wmi_phy_mode cfr_phymode;
	struct ath11k_afc_info afc;
	struct ath11k_smart_ant_info smart_ant_info;
	u32 rx_antenna;
	u32 aggr_sw_retry_thold;
	u32 non_aggr_sw_retry_thold;
	struct cfg80211_chan_def awgn_chandef;
	u32 chan_bw_interference_bitmap;
	bool awgn_intf_handling_in_prog;
	struct ath11k_rx_buf_id rx_buf_id;
	u8 mgmt_retry_limit;

	/* fw pdev_stats can be requested by get_txpower mac ops too */
	struct list_head fw_stats_pdevs;
	struct completion fw_stats_complete;
	bool fw_stats_done;
	u16 rts_threshold[NUM_NL80211_IFTYPES];
	struct completion ani_status_event;
	bool mon_status_skb_zero;
	enum mon_status_buf_done mon_status_no_buf_done;
};

struct ath11k_band_cap {
	u32 phy_id;
	u32 max_bw_supported;
	u32 ht_cap_info;
	u32 he_cap_info[2];
	u32 he_mcs;
	u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE];
	struct ath11k_ppe_threshold he_ppet;
	u16 he_6ghz_capa;
};

struct ath11k_pdev_cap {
	u32 supported_bands;
	u32 ampdu_density;
	u32 vht_cap;
	u32 vht_mcs;
	u32 he_mcs;
	u32 tx_chain_mask;
	u32 rx_chain_mask;
	u32 tx_chain_mask_shift;
	u32 rx_chain_mask_shift;
	struct ath11k_band_cap band[NUM_NL80211_BANDS];
	bool nss_ratio_enabled;
	u8 nss_ratio_info;
};

struct ath11k_pdev {
	struct ath11k *ar;
	u32 pdev_id;
	struct ath11k_pdev_cap cap;
	u8 mac_addr[ETH_ALEN];
};

struct ath11k_board_data {
	const struct firmware *fw;
	const void *data;
	size_t len;
};

struct ath11k_bus_params {
	bool mhi_support;
	bool m3_fw_support;
	bool fixed_bdf_addr;
	bool fixed_mem_region;
	bool static_window_map;
};

/* IPQ8074 HW channel counters frequency value in hertz */
#define IPQ8074_CC_FREQ_HERTZ 320000

struct ath11k_bp_stats {
	/* Head Pointer reported by the last HTT Backpressure event for the ring */
	u16 hp;

	/* Tail Pointer reported by the last HTT Backpressure event for the ring */
	u16 tp;

	/* Number of Backpressure events received for the ring */
	u32 count;

	/* Last recorded event timestamp */
	unsigned long jiffies;
};

struct ath11k_dp_ring_bp_stats {
	struct ath11k_bp_stats umac_ring_bp_stats[HTT_SW_UMAC_RING_IDX_MAX];
	struct ath11k_bp_stats lmac_ring_bp_stats[HTT_SW_LMAC_RING_IDX_MAX][MAX_RADIOS];
};

struct ath11k_soc_dp_tx_err_stats {
	/* TCL Ring Descriptor unavailable */
	u32 desc_na[DP_TCL_NUM_RING_MAX];
	/* TCL Ring IDR unavailable */
	u32 idr_na[DP_TCL_NUM_RING_MAX];

	/* Other failures during dp_tx due to mem allocation failure
	 * idr unavailable etc.
	 */
	atomic_t misc_fail;
	atomic_t max_fail;
};

struct ath11k_soc_dp_stats {
	u32 err_ring_pkts;
	u32 invalid_rbm;
	u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX];
	u32 rxdma_error_drop[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX];
	u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX];
	u32 reo_error_drop[HAL_REO_DEST_RING_ERROR_CODE_MAX];
	u32 hal_reo_error[DP_REO_DST_RING_MAX];
	struct ath11k_soc_dp_tx_err_stats tx_err;
	struct ath11k_dp_ring_bp_stats bp_stats;
};

struct ath11k_num_vdevs_peers {
	u32 num_vdevs;
	u32 num_peers;
};

struct ath11k_internal_pci {
	int qgicm_id;
	const struct ath11k_msi_config *msi_cfg;
	bool gic_enabled;
	wait_queue_head_t gic_msi_waitq;
	u32 address_lo;
	u32 address_hi;
	u32 dp_msi_data[ATH11K_EXT_IRQ_GRP_NUM_MAX];
	u32 ce_msi_data[ATH11K_QCN6122_CE_COUNT];
	u32 gic_ep_base_data;
	u32 dp_irq_num[8];
};

struct ath11k_memory_stats {
	/* Account kzalloc and valloc */
	atomic_t malloc_size;
	/* Account dma_alloc in dp.c & hal.c */
	atomic_t dma_alloc;
	/* Account memory used in ce rings */
	atomic_t ce_ring_alloc;
	/* Account memory used in htc_send */
	atomic_t htc_skb_alloc;
	/* Account memory used in wmi tx skb alloc */
	atomic_t wmi_tx_skb_alloc;
	/* Account memory consumed for peer object */
	atomic_t per_peer_object;
	/* Account memory used in ce rx pipe */
	atomic_t ce_rx_pipe;
};

struct ath11k_6g_sp_reg_rule {
	int num_6g_sp_rule;
	struct ieee80211_reg_rule sp_reg_rule[];
};

struct ath11k_reg_rule {
	u32 start_freq;
	u32 end_freq;
};

/* Master structure to hold the hw data which may be used in core module */
struct ath11k_base {
	enum ath11k_hw_rev hw_rev;
	enum ath11k_firmware_mode fw_mode;
	struct platform_device *pdev;
	struct device *dev;
	struct ath11k_qmi qmi;
	struct ath11k_wmi_base wmi_ab;
	struct completion fw_ready;
	int num_radios;
	/* HW channel counters frequency value in hertz common to all MACs */
	u32 cc_freq_hz;

	struct ath11k_htc htc;

	struct ath11k_dp dp;
	struct ath11k_soc_nss nss;

	void __iomem *mem;
	void __iomem *mem_ce;
	dma_addr_t mem_pa;
	unsigned long mem_len;

	struct {
		enum ath11k_bus bus;
		const struct ath11k_hif_ops *ops;
	} hif;

	struct {
		struct completion wakeup_completed;
	} wow;

	struct ath11k_ce ce;
	struct timer_list rx_replenish_retry;
	struct ath11k_hal hal;
	/* To synchronize core_start/core_stop */
	struct mutex core_lock;
	/* Protects data like peers */
	spinlock_t base_lock;
	struct ath11k_pdev pdevs[MAX_RADIOS];
	struct ath11k_pdev __rcu *pdevs_active[MAX_RADIOS];
	struct ath11k_hal_reg_capabilities_ext hal_reg_cap[MAX_RADIOS];
	unsigned long long free_vdev_map;

	/*
	 * The rhashtable containing struct ath11k_peer keyed by mac addr
	 * protected under ab->base_lock spin lock
	 */
	struct rhashtable *rhead_peer_addr;
	struct rhashtable_params rhash_peer_addr_param;

	/* The rhashtable containing struct ath11k_peer keyed by id  */
	struct rhashtable *rhead_peer_id;
	struct rhashtable_params rhash_peer_id_param;

	struct list_head peers;
	wait_queue_head_t peer_mapping_wq;
	u8 mac_addr[ETH_ALEN];
	bool wmi_ready;
	u32 wlan_init_status;
	int irq_num[ATH11K_IRQ_NUM_MAX];
	struct ath11k_ext_irq_grp ext_irq_grp[ATH11K_EXT_IRQ_GRP_NUM_MAX];
	struct napi_struct *napi;
	struct ath11k_targ_cap target_caps;
	u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE];
	bool pdevs_macaddr_valid;
	bool enable_cold_boot_cal;
	int bd_api;

	struct ath11k_hw_params hw_params;
	struct ath11k_bus_params bus_params;
	bool is_qdss_tracing;

	const struct firmware *cal_file;

	/* Below regd's are protected by ab->data_lock */
	/* This is the regd set for every radio
	 * by the firmware during initializatin
	 */
	struct ieee80211_regdomain *default_regd[MAX_RADIOS];
	/* This regd is set during dynamic country setting
	 * This may or may not be used during the runtime
	 */
	struct ieee80211_regdomain *new_regd[MAX_RADIOS];

	/* 6G standard power rules from cc ext event are saved here
	 * as it should not be updated to cfg unless we have a afc
	 * response
	 */
	struct ath11k_6g_sp_reg_rule *sp_rule;
	/* Current DFS Regulatory */
	enum ath11k_dfs_region dfs_region;
	struct ath11k_reg_rule reg_rule_2g;
	struct ath11k_reg_rule reg_rule_5g;
	struct ath11k_reg_rule reg_rule_6g;
#ifdef CONFIG_ATH11K_DEBUGFS
	struct dentry *debugfs_soc;
	struct ath11k_memory_stats memory_stats;
#endif
	struct ath11k_soc_dp_stats soc_stats;

	unsigned long dev_flags;
	struct completion driver_recovery;
	struct workqueue_struct *workqueue;
	struct work_struct restart_work;
	struct workqueue_struct *workqueue_aux;
	struct work_struct reset_work;
	atomic_t reset_count;
	bool is_reset;
	struct completion reset_complete;
	struct {
		/* protected by data_lock */
		u32 fw_crash_counter;
	} stats;
	bool ftm_segment_handler;
	struct ath11k_ftm_event_obj ftm_event_obj;

	u32 max_ast_index;
	u32 pktlog_defs_checksum;

	u32 num_ast_entries;

	struct ath11k_dbring_cap *db_caps;
	u32 num_db_cap;

	struct timer_list mon_reap_timer;

	struct completion htc_suspend;

	bool fw_recovery_support;
	bool ce_remap;
	bool ce_latency_stats_enable;
	u32 ce_remap_base_addr;
	atomic_t num_max_allowed;
	int userpd_id;
	struct ath11k_internal_pci ipci;
	bool enable_memory_stats;
	u32 fw_dbglog_param;
	u64 fw_dbglog_val;

	u32 rx_hash;
	bool stats_disable;

	u32 ani_poll_period;
	u32 ani_listen_period;
	int ani_ofdm_level;
	int ani_cck_level;
	struct completion ani_ofdm_event;
	struct completion ani_cck_event;
	struct mutex base_ast_lock;
	struct work_struct wmi_ast_work;
	struct list_head wmi_ast_list;
	u32 napi_poll_budget;
	bool gro_support_enabled;

	/* must be last */
	u8 drv_priv[0] __aligned(sizeof(void *));
};

struct ath11k_fw_stats_pdev {
	struct list_head list;

	/* PDEV stats */
	s32 ch_noise_floor;
	/* Cycles spent transmitting frames */
	u32 tx_frame_count;
	/* Cycles spent receiving frames */
	u32 rx_frame_count;
	/* Total channel busy time, evidently */
	u32 rx_clear_count;
	/* Total on-channel time */
	u32 cycle_count;
	u32 phy_err_count;
	u32 chan_tx_power;
	u32 ack_rx_bad;
	u32 rts_bad;
	u32 rts_good;
	u32 fcs_bad;
	u32 no_beacons;
	u32 mib_int_count;

	/* PDEV TX stats */
	/* Num HTT cookies queued to dispatch list */
	s32 comp_queued;
	/* Num HTT cookies dispatched */
	s32 comp_delivered;
	/* Num MSDU queued to WAL */
	s32 msdu_enqued;
	/* Num MPDU queue to WAL */
	s32 mpdu_enqued;
	/* Num MSDUs dropped by WMM limit */
	s32 wmm_drop;
	/* Num Local frames queued */
	s32 local_enqued;
	/* Num Local frames done */
	s32 local_freed;
	/* Num queued to HW */
	s32 hw_queued;
	/* Num PPDU reaped from HW */
	s32 hw_reaped;
	/* Num underruns */
	s32 underrun;
	/* Num hw paused */
	u32 hw_paused;
	/* Num PPDUs cleaned up in TX abort */
	s32 tx_abort;
	/* Num MPDUs requed by SW */
	s32 mpdus_requed;
	/* excessive retries */
	u32 tx_ko;
	u32 tx_xretry;
	/* data hw rate code */
	u32 data_rc;
	/* Scheduler self triggers */
	u32 self_triggers;
	/* frames dropped due to excessive sw retries */
	u32 sw_retry_failure;
	/* illegal rate phy errors	*/
	u32 illgl_rate_phy_err;
	/* wal pdev continuous xretry */
	u32 pdev_cont_xretry;
	/* wal pdev tx timeouts */
	u32 pdev_tx_timeout;
	/* wal pdev resets */
	u32 pdev_resets;
	/* frames dropped due to non-availability of stateless TIDs */
	u32 stateless_tid_alloc_failure;
	/* PhY/BB underrun */
	u32 phy_underrun;
	/* MPDU is more than txop limit */
	u32 txop_ovf;
	/* Num sequences posted */
	u32 seq_posted;
	/* Num sequences failed in queueing */
	u32 seq_failed_queing;
	/* Num sequences completed */
	u32 seq_completed;
	/* Num sequences restarted */
	u32 seq_restarted;
	/* Num of MU sequences posted */
	u32 mu_seq_posted;
	/* Num MPDUs flushed by SW, HWPAUSED, SW TXABORT
	 * (Reset,channel change)
	 */
	s32 mpdus_sw_flush;
	/* Num MPDUs filtered by HW, all filter condition (TTL expired) */
	s32 mpdus_hw_filter;
	/* Num MPDUs truncated by PDG (TXOP, TBTT,
	 * PPDU_duration based on rate, dyn_bw)
	 */
	s32 mpdus_truncated;
	/* Num MPDUs that was tried but didn't receive ACK or BA */
	s32 mpdus_ack_failed;
	/* Num MPDUs that was dropped du to expiry. */
	s32 mpdus_expired;
	/* Num mc drops */
	u32 mc_drop;

	/* PDEV RX stats */
	/* Cnts any change in ring routing mid-ppdu */
	s32 mid_ppdu_route_change;
	/* Total number of statuses processed */
	s32 status_rcvd;
	/* Extra frags on rings 0-3 */
	s32 r0_frags;
	s32 r1_frags;
	s32 r2_frags;
	s32 r3_frags;
	/* MSDUs / MPDUs delivered to HTT */
	s32 htt_msdus;
	s32 htt_mpdus;
	/* MSDUs / MPDUs delivered to local stack */
	s32 loc_msdus;
	s32 loc_mpdus;
	/* AMSDUs that have more MSDUs than the status ring size */
	s32 oversize_amsdu;
	/* Number of PHY errors */
	s32 phy_errs;
	/* Number of PHY errors drops */
	s32 phy_err_drop;
	/* Number of mpdu errors - FCS, MIC, ENC etc. */
	s32 mpdu_errs;
	/* Inactivity timeouts */
	u32 pdev_rx_timeout;
	/* Num overflow errors */
	s32 rx_ovf_err;
};

struct ath11k_fw_stats_vdev {
	struct list_head list;

	u32 vdev_id;
	u32 beacon_snr;
	u32 data_snr;
	u32 num_tx_frames[WLAN_MAX_AC];
	u32 num_rx_frames;
	u32 num_tx_frames_retries[WLAN_MAX_AC];
	u32 num_tx_frames_failures[WLAN_MAX_AC];
	u32 num_rts_fail;
	u32 num_rts_success;
	u32 num_rx_err;
	u32 num_rx_discard;
	u32 num_tx_not_acked;
	u32 tx_rate_history[MAX_TX_RATE_VALUES];
	u32 beacon_rssi_history[MAX_TX_RATE_VALUES];
};

struct ath11k_fw_stats_bcn {
	struct list_head list;

	u32 vdev_id;
	u32 tx_bcn_succ_cnt;
	u32 tx_bcn_outage_cnt;
};

enum ath11k_fw_recovery_option {
	ATH11K_FW_RECOVERY_DISABLE = 0,
	ATH11K_FW_RECOVERY_ENABLE_AUTO, /* Automatically recover after FW assert */
	/* Enable only recovery. Send MPD SSR WMI */
	/* command to unlink UserPD assert from RootPD */
	ATH11K_FW_RECOVERY_ENABLE_SSR_ONLY,
};

void ath11k_fw_stats_init(struct ath11k *ar);
void ath11k_fw_stats_pdevs_free(struct list_head *head);
void ath11k_fw_stats_bcn_free(struct list_head *head);
void ath11k_fw_stats_reset(struct ath11k *ar);
void ath11k_fw_stats_free(struct ath11k_fw_stats *stats);

extern bool ath11k_enable_smart_antenna;

static inline bool ath11k_smart_ant_enabled(struct ath11k *ar)
{
	if (!test_bit(WMI_TLV_SERVICE_SMART_ANTENNA_SW_SUPPORT,
	    ar->ab->wmi_ab.svc_map))
		return false;

	if (!test_bit(WMI_TLV_SERVICE_SMART_ANTENNA_HW_SUPPORT,
	    ar->ab->wmi_ab.svc_map))
		return false;

	if (!ath11k_enable_smart_antenna)
		return false;

	return true;
}

extern const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq8074[];
extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq8074[];
extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq6018[];

extern const struct ce_pipe_config ath11k_target_ce_config_wlan_qca6390[];
extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qca6390[];

extern const struct ce_pipe_config ath11k_target_ce_config_wlan_qcn9074[];
extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qcn9074[];
extern const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq5018[];
extern const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq5018[];

int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab);
int ath11k_core_pre_init(struct ath11k_base *ab);
int ath11k_core_init(struct ath11k_base *ath11k);
void ath11k_core_deinit(struct ath11k_base *ath11k);
struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size,
				      enum ath11k_bus bus,
				      const struct ath11k_bus_params *bus_params);
void ath11k_core_free(struct ath11k_base *ath11k);
int ath11k_core_fetch_bdf(struct ath11k_base *ath11k,
			  struct ath11k_board_data *bd);
int ath11k_config_qdss(struct ath11k_base *ab);
void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd);
int ath11k_core_check_dt(struct ath11k_base *ath11k);

void ath11k_core_halt(struct ath11k *ar);
int ath11k_core_resume(struct ath11k_base *ab);
int ath11k_core_suspend(struct ath11k_base *ab);

void ath11k_core_dump_bp_stats(struct ath11k_base *ab);
void ath11k_coredump_qdss_dump(struct ath11k_base *ab,
			       struct ath11k_qmi_event_qdss_trace_save_data *event_data);
const struct firmware *ath11k_core_firmware_request(struct ath11k_base *ab,
						    const char *filename);

static inline const char *ath11k_scan_state_str(enum ath11k_scan_state state)
{
	switch (state) {
	case ATH11K_SCAN_IDLE:
		return "idle";
	case ATH11K_SCAN_STARTING:
		return "starting";
	case ATH11K_SCAN_RUNNING:
		return "running";
	case ATH11K_SCAN_ABORTING:
		return "aborting";
	}

	return "unknown";
}

static inline struct ath11k_skb_cb *ATH11K_SKB_CB(struct sk_buff *skb)
{
	BUILD_BUG_ON(sizeof(struct ath11k_skb_cb) >
		     IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
	return (struct ath11k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
}

static inline struct ath11k_skb_rxcb *ATH11K_SKB_RXCB(struct sk_buff *skb)
{
	BUILD_BUG_ON(sizeof(struct ath11k_skb_rxcb) > sizeof(skb->cb));
	return (struct ath11k_skb_rxcb *)skb->cb;
}

static inline struct ath11k_vif *ath11k_vif_to_arvif(struct ieee80211_vif *vif)
{
	return (struct ath11k_vif *)vif->drv_priv;
}

static inline struct ath11k *ath11k_ab_to_ar(struct ath11k_base *ab,
					     int mac_id)
{
	return ab->pdevs[ath11k_hw_mac_id_to_pdev_id(&ab->hw_params, mac_id)].ar;
}

static inline void ath11k_core_create_firmware_path(struct ath11k_base *ab,
						    const char *filename,
						    void *buf, size_t buf_len)
{
	snprintf(buf, buf_len, "%s/%s/%s", ATH11K_FW_DIR,
		 ab->hw_params.fw.dir, filename);
}

static inline const char *ath11k_bus_str(enum ath11k_bus bus)
{
	switch (bus) {
	case ATH11K_BUS_PCI:
		return "pci";
	case ATH11K_BUS_AHB:
		return "ahb";
	}

	return "unknown";
}

#endif /* _CORE_H_ */