| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright (c) 2019 Amlogic, Inc. All rights reserved. |
| */ |
| |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| |
| / { |
| compatible = "amlogic,g12b"; |
| |
| interrupt-parent = <&gic>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| ppmgr { |
| compatible = "amlogic, ppmgr"; |
| dev_name = "ppmgr"; |
| status = "okay"; |
| }; |
| |
| ionvideo { |
| compatible = "amlogic, ionvideo"; |
| dev_name = "ionvideo"; |
| status = "okay"; |
| }; |
| |
| amlvideo { |
| compatible = "amlogic, amlvideo"; |
| dev_name = "amlvideo"; |
| status = "okay"; |
| }; |
| |
| videosync { |
| compatible = "amlogic, videosync"; |
| dev_name = "videosync"; |
| status = "okay"; |
| }; |
| |
| cpus { |
| #address-cells = <0x1>; |
| #size-cells = <0x0>; |
| |
| cpu-map { |
| cluster0:cluster0 { |
| core0 { |
| cpu = <&CPU0>; |
| }; |
| core1 { |
| cpu = <&CPU1>; |
| }; |
| }; |
| cluster1:cluster1 { |
| core0 { |
| cpu = <&CPU2>; |
| }; |
| core1 { |
| cpu = <&CPU3>; |
| }; |
| core2 { |
| cpu = <&CPU4>; |
| }; |
| core3 { |
| cpu = <&CPU5>; |
| }; |
| }; |
| }; |
| |
| CPU0:cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53","arm,armv8"; |
| reg = <0x0>; |
| enable-method = "psci"; |
| }; |
| |
| CPU1:cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53","arm,armv8"; |
| reg = <0x1>; |
| enable-method = "psci"; |
| }; |
| |
| CPU2:cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a73","arm,armv8"; |
| reg = <0x100>; |
| enable-method = "psci"; |
| }; |
| |
| CPU3:cpu@101 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a73","arm,armv8"; |
| reg = <0x101>; |
| enable-method = "psci"; |
| }; |
| |
| CPU4:cpu@102 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a73","arm,armv8"; |
| reg = <0x102>; |
| enable-method = "psci"; |
| }; |
| |
| CPU5:cpu@103 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a73","arm,armv8"; |
| reg = <0x103>; |
| enable-method = "psci"; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| arm_pmu { |
| compatible = "arm,cortex-a15-pmu"; |
| clusterb-enabled; |
| interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0xff634680 0x4>, |
| <0xff6347c0 0x04>; |
| cpumasks = <0x3 0x3C>; |
| /* default 10ms */ |
| relax-timer-ns = <10000000>; |
| /* default 10000us */ |
| max-wait-cnt = <10000>; |
| }; |
| |
| ram-dump { |
| compatible = "amlogic, ram_dump"; |
| status = "okay"; |
| reg = <0xFF6345E0 4>; |
| reg-names = "PREG_STICKY_REG8"; |
| store_device = "data"; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| periphs: periphs@ff634000 { |
| compatible = "simple-bus"; |
| reg = <0xff634000 0x2000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xff634000 0x2000>; |
| |
| pinctrl_periphs: pinctrl@6c0 { |
| compatible = |
| "amlogic,meson-g12a-periphs-pinctrl"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| }; |
| }; |
| |
| hiubus: bus@ff63c000 { |
| compatible = "simple-bus"; |
| reg = <0xff63c000 0x1c00>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xff63c000 0x1c00>; |
| |
| }; |
| |
| aml_dma: aml_dma@ff63e000 { |
| compatible = "amlogic,aml_txlx_dma"; |
| reg = <0xff63e000 0x48>; |
| interrupts = <0 180 1>; |
| |
| }; |
| |
| aobus: bus@ff800000 { |
| compatible = "simple-bus"; |
| reg = <0xff800000 0x100000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xff800000 0x100000>; |
| |
| uart_AO: serial@3000 { |
| compatible = "amlogic,meson-uart"; |
| reg = <0x3000 0x18>; |
| interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; |
| status = "disabled"; |
| clocks = <&xtal>; |
| clock-names = "clk_uart"; |
| xtal_tick_en = <0>; |
| fifosize = < 64 >; |
| pinctrl-names = "default"; |
| /*pinctrl-0 = <&ao_uart_pins>;*/ |
| }; |
| |
| }; |
| |
| gic: interrupt-controller@ffc01000 { |
| compatible = "arm,gic-400"; |
| reg = <0xffc01000 0x1000>, |
| <0xffc02000 0x2000>, |
| <0xffc04000 0x2000>, |
| <0xffc06000 0x2000>; |
| interrupt-controller; |
| interrupts = <GIC_PPI 9 |
| (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; |
| #interrupt-cells = <3>; |
| #address-cells = <0>; |
| }; |
| |
| cbus: bus@ffd00000 { |
| compatible = "simple-bus"; |
| reg = <0xffd00000 0x25000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xffd00000 0x25000>; |
| |
| }; |
| |
| apb: apb@ffe00000 { |
| compatible = "simple-bus"; |
| reg = <0xffe00000 0x200000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xffe00000 0x200000>; |
| }; |
| |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 |
| (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 |
| (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 |
| (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 |
| (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| |
| timer_bc { |
| compatible = "amlogic,bc-timer"; |
| reg= <0xffd0f190 0x8>; |
| timer_name = "Meson TimerF"; |
| clockevent-rating=<300>; |
| clockevent-shift=<20>; |
| clockevent-features=<0x23>; |
| interrupts = <0 60 1>; |
| bit_enable=<16>; |
| bit_mode=<12>; |
| bit_resolution=<0>; |
| }; |
| |
| xtal: xtal-clk { |
| compatible = "fixed-clock"; |
| clock-frequency = <24000000>; |
| clock-output-names = "xtal"; |
| #clock-cells = <0>; |
| }; |
| |
| secmon { |
| compatible = "amlogic,meson-gxbb-sm"; |
| memory-region = <&secmon_reserved>; |
| reserve_mem_size = <0x00300000>; |
| }; |
| |
| ion_dev { |
| compatible = "amlogic, ion_dev"; |
| memory-region = <&ion_cma_reserved>; |
| }; |
| |
| mailbox: mhu@ff63c400 { |
| compatible = "amlogic, meson_mhu"; |
| reg = <0xff63c400 0x4c>, /* MHU registers */ |
| <0xfffe7000 0x800>; /* Payload area */ |
| interrupts = <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, /* low isr*/ |
| <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; /* high isr*/ |
| #mbox-cells = <1>; |
| mbox-names = "cpu_to_scp_low", "cpu_to_scp_high"; |
| mboxes = <&mailbox 0 &mailbox 1>; |
| }; |
| }; |
| |
| &pinctrl_periphs { |
| pwm_a_pins: pwm_a { |
| mux { |
| groups = "pwm_a"; |
| function = "pwm_a"; |
| }; |
| }; |
| |
| pwm_b_pins1: pwm_b_pins1 { |
| mux { |
| groups = "pwm_b_x7"; |
| function = "pwm_b"; |
| }; |
| }; |
| |
| pwm_b_pins2: pwm_b_pins2 { |
| mux { |
| groups = "pwm_b_x19"; |
| function = "pwm_b"; |
| }; |
| }; |
| |
| pwm_c_pins1: pwm_c_pins1 { |
| mux { |
| groups = "pwm_c_c"; |
| function = "pwm_c"; |
| }; |
| }; |
| |
| pwm_c_pins2: pwm_c_pins2 { |
| mux { |
| groups = "pwm_c_x5"; |
| function = "pwm_c"; |
| }; |
| }; |
| |
| pwm_c_pins3: pwm_c_pins3 { |
| mux { |
| groups = "pwm_c_x8"; |
| function = "pwm_c"; |
| }; |
| }; |
| |
| pwm_d_pins1: pwm_d_pins1 { |
| mux { |
| groups = "pwm_d_x3"; |
| function = "pwm_d"; |
| }; |
| }; |
| |
| pwm_d_pins2: pwm_d_pins2 { |
| mux { |
| groups = "pwm_d_x6"; |
| function = "pwm_d"; |
| }; |
| }; |
| |
| pwm_e_pins: pwm_e { |
| mux { |
| groups = "pwm_e"; |
| function = "pwm_e"; |
| }; |
| }; |
| |
| pwm_f_pins1: pwm_f_pins1 { |
| mux { |
| groups = "pwm_f_x"; |
| function = "pwm_f"; |
| }; |
| }; |
| |
| pwm_f_pins2: pwm_f_pins2 { |
| mux { |
| groups = "pwm_f_h"; |
| function = "pwm_f"; |
| }; |
| }; |
| |
| i2c0_master_pins1:i2c0_pins1 { |
| mux { |
| groups = "i2c0_sda_c", |
| "i2c0_sck_c"; |
| function = "i2c0"; |
| bias-pull-up; |
| drive-strength = <2>; |
| }; |
| }; |
| |
| i2c0_master_pins2:i2c0_pins2 { |
| mux { |
| groups = "i2c0_sda_z0", |
| "i2c0_sck_z1"; |
| function = "i2c0"; |
| bias-pull-up; |
| drive-strength = <2>; |
| }; |
| }; |
| |
| i2c0_master_pins3:i2c0_pins3 { |
| mux { |
| groups = "i2c0_sda_z7", |
| "i2c0_sck_z8"; |
| function = "i2c0"; |
| bias-pull-up; |
| drive-strength = <2>; |
| }; |
| }; |
| |
| i2c1_master_pins1:i2c1_pins1 { |
| mux { |
| groups = "i2c1_sda_x", |
| "i2c1_sck_x"; |
| function = "i2c1"; |
| bias-pull-up; |
| drive-strength = <2>; |
| }; |
| }; |
| |
| i2c1_master_pins2:i2c1_pins2 { |
| mux { |
| groups = "i2c1_sda_h2", |
| "i2c1_sck_h3"; |
| function = "i2c1"; |
| bias-pull-up; |
| drive-strength = <2>; |
| }; |
| }; |
| |
| i2c1_master_pins3:i2c1_pins3 { |
| mux { |
| groups = "i2c1_sda_h6", |
| "i2c1_sck_h7"; |
| function = "i2c1"; |
| bias-pull-up; |
| drive-strength = <2>; |
| }; |
| }; |
| |
| i2c2_master_pins1:i2c2_pins1 { |
| mux { |
| groups = "i2c2_sda_x", |
| "i2c2_sck_x"; |
| function = "i2c2"; |
| bias-pull-up; |
| drive-strength = <2>; |
| }; |
| }; |
| |
| i2c2_master_pins2:i2c2_pins2 { |
| mux { |
| groups = "i2c2_sda_z", |
| "i2c2_sck_z"; |
| function = "i2c2"; |
| bias-pull-up; |
| drive-strength = <2>; |
| }; |
| }; |
| |
| i2c3_master_pins1:i2c3_pins1 { |
| mux { |
| groups = "i2c3_sda_h", |
| "i2c3_sck_h"; |
| function = "i2c3"; |
| bias-pull-up; |
| drive-strength = <2>; |
| }; |
| }; |
| |
| i2c3_master_pins2:i2c3_pins2 { |
| mux { |
| groups = "i2c3_sda_a", |
| "i2c3_sck_a"; |
| function = "i2c3"; |
| bias-pull-up; |
| drive-strength = <2>; |
| }; |
| }; |
| |
| internal_eth_pins: internal_eth_pins { |
| mux { |
| groups = "eth_link_led", |
| "eth_act_led"; |
| function = "eth"; |
| }; |
| }; |
| |
| internal_gpio_pins: internal_gpio_pins { |
| mux { |
| groups = "GPIOZ_14", |
| "GPIOZ_15"; |
| function = "gpio_periphs"; |
| bias-disable; |
| input-enable; |
| }; |
| }; |
| |
| external_eth_pins: external_eth_pins { |
| mux { |
| groups = "eth_mdio", |
| "eth_mdc", |
| "eth_rgmii_rx_clk", |
| "eth_rx_dv", |
| "eth_rxd0", |
| "eth_rxd1", |
| "eth_rxd2_rgmii", |
| "eth_rxd3_rgmii", |
| "eth_rgmii_tx_clk", |
| "eth_txen", |
| "eth_txd0", |
| "eth_txd1", |
| "eth_txd2_rgmii", |
| "eth_txd3_rgmii"; |
| function = "eth"; |
| drive-strength = <3>; |
| }; |
| }; |
| |
| spicc0_pins_x: spicc0_pins_x { |
| mux { |
| groups = "spi0_mosi_x", |
| "spi0_miso_x", |
| "spi0_clk_x"; |
| function = "spi0"; |
| drive-strength = <2>; |
| }; |
| }; |
| |
| spicc0_pins_c: spicc0_pins_c { |
| mux { |
| groups = "spi0_mosi_c", |
| "spi0_miso_c", |
| "spi0_clk_c"; |
| function = "spi0"; |
| drive-strength = <2>; |
| }; |
| }; |
| |
| spicc1_pins: spicc1_pins { |
| mux { |
| groups = "spi1_mosi", |
| "spi1_miso", |
| "spi1_clk"; |
| function = "spi1"; |
| drive-strength = <2>; |
| }; |
| }; |
| |
| all_nand_pins: all_nand_pins { |
| mux { |
| groups = "emmc_nand_d0", |
| "emmc_nand_d1", |
| "emmc_nand_d2", |
| "emmc_nand_d3", |
| "emmc_nand_d4", |
| "emmc_nand_d5", |
| "emmc_nand_d6", |
| "emmc_nand_d7", |
| "nand_ce0", |
| "nand_ale", |
| "nand_cle", |
| "nand_wen_clk", |
| "nand_ren_wr", |
| "nand_rb0"; |
| function = "nand"; |
| input-enable; |
| }; |
| }; |
| |
| nand_cs_pins: nand_cs { |
| mux { |
| groups = "nand_ce0"; |
| function = "nand"; |
| }; |
| }; |
| |
| a_uart_pins:a_uart { |
| mux { |
| groups = "uart_a_tx", |
| "uart_a_rx", |
| "uart_a_cts", |
| "uart_a_rts"; |
| function = "uart_a"; |
| }; |
| }; |
| |
| b_uart_pins:b_uart { |
| mux { |
| groups = "uart_b_tx", |
| "uart_b_rx"; |
| function = "uart_b"; |
| }; |
| }; |
| |
| c_uart_pins:c_uart { |
| mux { |
| groups = "uart_c_rx", |
| "uart_c_tx"; |
| function = "uart_c"; |
| }; |
| }; |
| |
| hdmitx_hpd: hdmitx_hpd { |
| mux { |
| groups = "hdmitx_hpd_in"; |
| function = "hdmitx"; |
| bias-disable; |
| }; |
| }; |
| |
| hdmitx_hpd_gpio: hdmitx_hpd_gpio { |
| mux { |
| groups = "GPIOH_1"; |
| function = "gpio_periphs"; |
| bias-disable; |
| }; |
| }; |
| |
| hdmitx_ddc: hdmitx_ddc { |
| mux { |
| groups = "hdmitx_sda", |
| "hdmitx_sck"; |
| function = "hdmitx"; |
| bias-disable; |
| drive-strength = <3>; |
| }; |
| }; |
| }; |
| |
