| /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ |
| /* |
| * Copyright (c) 2019 Amlogic, Inc. All rights reserved. |
| */ |
| |
| #ifndef __G12A_H |
| #define __G12A_H |
| |
| /* |
| * Clock controller register offsets |
| * |
| * Register offsets from the data sheet must be multiplied by 4 before |
| * adding them to the base address to get the right value. |
| */ |
| #define HHI_MIPI_CNTL0 0x000 |
| #define HHI_MIPI_CNTL1 0x004 |
| #define HHI_MIPI_CNTL2 0x008 |
| #define HHI_MIPI_STS 0x00C |
| #define HHI_GP0_PLL_CNTL0 0x040 |
| #define HHI_GP0_PLL_CNTL1 0x044 |
| #define HHI_GP0_PLL_CNTL2 0x048 |
| #define HHI_GP0_PLL_CNTL3 0x04C |
| #define HHI_GP0_PLL_CNTL4 0x050 |
| #define HHI_GP0_PLL_CNTL5 0x054 |
| #define HHI_GP0_PLL_CNTL6 0x058 |
| #define HHI_GP0_PLL_STS 0x05C |
| #define HHI_PCIE_PLL_CNTL0 0x098 |
| #define HHI_PCIE_PLL_CNTL1 0x09C |
| #define HHI_PCIE_PLL_CNTL2 0x0A0 |
| #define HHI_PCIE_PLL_CNTL3 0x0A4 |
| #define HHI_PCIE_PLL_CNTL4 0x0A8 |
| #define HHI_PCIE_PLL_CNTL5 0x0AC |
| #define HHI_PCIE_PLL_STS 0x0B8 |
| #define HHI_HIFI_PLL_CNTL0 0x0D8 |
| #define HHI_HIFI_PLL_CNTL1 0x0DC |
| #define HHI_HIFI_PLL_CNTL2 0x0E0 |
| #define HHI_HIFI_PLL_CNTL3 0x0E4 |
| #define HHI_HIFI_PLL_CNTL4 0x0E8 |
| #define HHI_HIFI_PLL_CNTL5 0x0EC |
| #define HHI_HIFI_PLL_CNTL6 0x0F0 |
| #define HHI_VIID_CLK_DIV 0x128 |
| #define HHI_VIID_CLK_CNTL 0x12C |
| #define HHI_GCLK_MPEG0 0x140 |
| #define HHI_GCLK_MPEG1 0x144 |
| #define HHI_GCLK_MPEG2 0x148 |
| #define HHI_GCLK_OTHER 0x150 |
| #define HHI_VID_CLK_DIV 0x164 |
| #define HHI_MPEG_CLK_CNTL 0x174 |
| #define HHI_AUD_CLK_CNTL 0x178 |
| #define HHI_VID_CLK_CNTL 0x17c |
| #define HHI_TS_CLK_CNTL 0x190 |
| #define HHI_VID_CLK_CNTL2 0x194 |
| #define HHI_SYS_CPU_CLK_CNTL0 0x19c |
| #define HHI_VID_PLL_CLK_DIV 0x1a0 |
| #define HHI_MALI_CLK_CNTL 0x1b0 |
| #define HHI_VPU_CLKC_CNTL 0x1b4 |
| #define HHI_VPU_CLK_CNTL 0x1bC |
| #define HHI_HDMI_CLK_CNTL 0x1CC |
| #define HHI_VDEC_CLK_CNTL 0x1E0 |
| #define HHI_VDEC2_CLK_CNTL 0x1E4 |
| #define HHI_VDEC3_CLK_CNTL 0x1E8 |
| #define HHI_VDEC4_CLK_CNTL 0x1EC |
| #define HHI_HDCP22_CLK_CNTL 0x1F0 |
| #define HHI_VAPBCLK_CNTL 0x1F4 |
| #define HHI_VPU_CLKB_CNTL 0x20C |
| #define HHI_GEN_CLK_CNTL 0x228 |
| #define HHI_VDIN_MEAS_CLK_CNTL 0x250 |
| #define HHI_MIPIDSI_PHY_CLK_CNTL 0x254 |
| #define HHI_NAND_CLK_CNTL 0x25C |
| #define HHI_SD_EMMC_CLK_CNTL 0x264 |
| #define HHI_MPLL_CNTL0 0x278 |
| #define HHI_MPLL_CNTL1 0x27C |
| #define HHI_MPLL_CNTL2 0x280 |
| #define HHI_MPLL_CNTL3 0x284 |
| #define HHI_MPLL_CNTL4 0x288 |
| #define HHI_MPLL_CNTL5 0x28c |
| #define HHI_MPLL_CNTL6 0x290 |
| #define HHI_MPLL_CNTL7 0x294 |
| #define HHI_MPLL_CNTL8 0x298 |
| #define HHI_FIX_PLL_CNTL0 0x2A0 |
| #define HHI_FIX_PLL_CNTL1 0x2A4 |
| #define HHI_FIX_PLL_CNTL2 0x2A8 |
| #define HHI_FIX_PLL_CNTL3 0x2AC |
| #define HHI_FIX_PLL_CNTL4 0x2B0 |
| #define HHI_FIX_PLL_CNTL5 0x2B4 |
| #define HHI_FIX_PLL_CNTL6 0x2B8 |
| #define HHI_SYS_PLL_CNTL0 0x2f4 |
| #define HHI_SYS_PLL_CNTL1 0x2f8 |
| #define HHI_SYS_PLL_CNTL2 0x2fc |
| #define HHI_SYS_PLL_CNTL3 0x300 |
| #define HHI_SYS_PLL_CNTL4 0x304 |
| #define HHI_SYS_PLL_CNTL5 0x308 |
| #define HHI_SYS_PLL_CNTL6 0x30c |
| #define HHI_HDMI_PLL_CNTL0 0x320 |
| #define HHI_HDMI_PLL_CNTL1 0x324 |
| #define HHI_HDMI_PLL_CNTL2 0x328 |
| #define HHI_HDMI_PLL_CNTL3 0x32c |
| #define HHI_HDMI_PLL_CNTL4 0x330 |
| #define HHI_HDMI_PLL_CNTL5 0x334 |
| #define HHI_HDMI_PLL_CNTL6 0x338 |
| #define HHI_HDMI_PLL_STS 0x33c |
| #define HHI_SPICC_CLK_CNTL 0x3dc |
| |
| /* include the CLKIDs that have been made part of the DT binding */ |
| #include <dt-bindings/clock/g12a-clkc.h> |
| /* |
| * CLKID index values |
| * |
| * These indices are entirely contrived and do not map onto the hardware. |
| * It has now been decided to expose everything by default in the DT header: |
| * include/dt-bindings/clock/g12a-clkc.h. Only the clocks ids we don't want |
| * to expose, such as the internal muxes and dividers of composite clocks, |
| * will remain defined here. |
| */ |
| #define CLKID_MPEG_SEL 9 |
| #define CLKID_MPEG_DIV 10 |
| |
| /* pll div clock, are not exposed to user,just used by g12a clock driver*/ |
| #define CLKID_CPU_BASE (SD_EMMC_BASE + 9) |
| #define CLKID_CPU_FSOURCE_SEL0 (CLKID_CPU_BASE + 0) |
| #define CLKID_CPU_FSOURCE_DIV0 (CLKID_CPU_BASE + 1) |
| #define CLKID_CPU_FSEL0 (CLKID_CPU_BASE + 2) |
| #define CLKID_CPU_FSOURCE_SEL1 (CLKID_CPU_BASE + 3) |
| #define CLKID_CPU_FSOURCE_DIV1 (CLKID_CPU_BASE + 4) |
| #define CLKID_CPU_FSEL1 (CLKID_CPU_BASE + 5) |
| |
| #define PLL_DIV_BASE (CLKID_CPU_BASE + 6) |
| #define CLKID_MPLL0_DIV (PLL_DIV_BASE + 0) |
| #define CLKID_MPLL1_DIV (PLL_DIV_BASE + 1) |
| #define CLKID_MPLL2_DIV (PLL_DIV_BASE + 2) |
| #define CLKID_MPLL3_DIV (PLL_DIV_BASE + 3) |
| #define CLKID_MPLL_PREDIV (PLL_DIV_BASE + 4) |
| #define CLKID_FCLK_DIV2_DIV (PLL_DIV_BASE + 5) |
| #define CLKID_FCLK_DIV3_DIV (PLL_DIV_BASE + 6) |
| #define CLKID_FCLK_DIV4_DIV (PLL_DIV_BASE + 7) |
| #define CLKID_FCLK_DIV5_DIV (PLL_DIV_BASE + 8) |
| #define CLKID_FCLK_DIV7_DIV (PLL_DIV_BASE + 9) |
| #define CLKID_FCLK_DIV2P5_DIV (PLL_DIV_BASE + 10) |
| #define CLKID_FIXED_PLL_DCO (PLL_DIV_BASE + 11) |
| #define CLKID_SYS_PLL_DCO (PLL_DIV_BASE + 12) |
| #define CLKID_GP0_PLL_DCO (PLL_DIV_BASE + 13) |
| #define CLKID_HIFI_PLL_DCO (PLL_DIV_BASE + 14) |
| #define CLKID_VID_PLL_DIV (PLL_DIV_BASE + 15) |
| #define CLKID_VID_PLL_SEL (PLL_DIV_BASE + 16) |
| |
| #define NR_CLKS (PLL_DIV_BASE + 17) |
| |
| #endif /* __G12A_H */ |
