| /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| * |
| * Copyright (c) 2016 BayLibre, SAS. |
| * Author: Neil Armstrong <narmstrong@baylibre.com> |
| * |
| * Copyright (c) 2017 Amlogic, inc. |
| * Author: Yixun Lan <yixun.lan@amlogic.com> |
| * |
| * Copyright (c) 2018 Amlogic, inc. |
| * Author: Jian Hu <jian.hu@amlogic.com> |
| * |
| */ |
| |
| #ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H |
| #define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H |
| |
| /* RESET0 */ |
| #define RESET_HIU 0 |
| #define RESET_DOS 2 |
| #define RESET_VIU 5 |
| #define RESET_AFIFO 6 |
| #define RESET_VID_PLL 7 |
| #define RESET_VENC 10 |
| #define RESET_ASSIST 11 |
| #define RESET_PCIE_A 12 |
| #define RESET_VCBUS 13 |
| #define RESET_PCIE_PHY 14 |
| #define RESET_PCIE_APB 15 |
| #define RESET_GIC 16 |
| #define RESET_CAPB3_DECODE 17 |
| #define RESET_HDMI_CAPB3 19 |
| #define RESET_MALI_CAPB3 20 |
| #define RESET_DOS_CAPB3 21 |
| #define RESET_CBUS_CAPB3 23 |
| #define RESET_AHB_CNTL 24 |
| #define RESET_AHB_DATA 25 |
| #define RESET_VCBUS_CLK81 26 |
| /* RESET1 */ |
| #define RESET_DEMUX 33 |
| #define RESET_USB 34 |
| #define RESET_DDR 35 |
| #define RESET_BT656 37 |
| #define RESET_AHB_SRAM 38 |
| #define RESET_PARSER 40 |
| #define RESET_ISA 42 |
| #define RESET_ETHERNET 43 |
| #define RESET_SD_EMMC_A 44 |
| #define RESET_SD_EMMC_B 45 |
| #define RESET_SD_EMMC_C 46 |
| #define RESET_ACODEC 61 |
| /* RESET2 */ |
| #define RESET_AUDIO 65 |
| #define RESET_HDMITX_PHY 66 |
| #define RESET_MIPI_HOST 68 |
| #define RESET_ALOCKER 69 |
| #define RESET_GE2D 70 |
| #define RESET_PARSER_REG 71 |
| #define RESET_PARSER_FETCH 72 |
| #define RESET_PARSER_CTL 73 |
| #define RESET_PARSER_TOP 74 |
| #define RESET_PARSER_MALI 78 |
| #define RESET_HDMITX 79 |
| /* RESET3 */ |
| #define RESET_DEMUX_TOP 105 |
| #define RESET_DEMUX_DES_PL 106 |
| #define RESET_DEMUX_S2P0 107 |
| #define RESET_DEMUX_S2P1 108 |
| #define RESET_DEMUX0 109 |
| #define RESET_DEMUX1 110 |
| #define RESET_DEMUX2 111 |
| /* RESET4 */ |
| #define RESET_MIPI_PHY 130 |
| #define RESET_RDMA 133 |
| #define RESET_VENCI 134 |
| #define RESET_VENCP 135 |
| #define RESET_VDAC 137 |
| #define RESET_VDI6 140 |
| #define RESET_VENCL 141 |
| #define RESET_I2C_MASTER_1 142 |
| #define RESET_I2C_MASTER_2 143 |
| /* RESET5 */ |
| /* RESET6 */ |
| #define RESET_GEN 192 |
| #define RESET_SPICC0 193 |
| #define RESET_SC 194 |
| #define RESET_SANA_3 195 |
| #define RESET_I2C_MASTER_0 196 |
| #define RESET_TS_PLL 197 |
| #define RESET_SPICC1 198 |
| #define RESET_STREAM 199 |
| #define RESET_TS_CPU 200 |
| #define RESET_UART0 201 |
| #define RESET_UART1_2 202 |
| #define RESET_ASYNC0 203 |
| #define RESET_ASYNC1 204 |
| #define RESET_SPIFC 205 |
| #define RESET_I2C_MASTER_3 206 |
| /* RESET7*/ |
| #define RESET_USB_DDR_0 224 |
| #define RESET_USB_DDR_1 225 |
| #define RESET_USB_DDR_2 226 |
| #define RESET_USB_DDR_3 227 |
| #define RESRT_TS_GPU 228 |
| #define RESET_DEVICE_MMC_ARB 229 |
| #define RESET_MALI_DMC_PIPL 230 |
| #define RESET_VID_LOCK 231 |
| #define RESET_MIC_DMC_PIPL 232 |
| #define RESET_VPU_DMC_PIPL 233 |
| #define RESET_GE2D_DMC_PIPL 234 |
| #define RESET_HCODEC_DMC_PIPL 235 |
| #define RESET_WAVE420_DMC_PIPL 236 |
| #define RESET_HEVCF_DMC_PIPL 237 |
| |
| #endif |
