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| Secondary CPU enable-method "nuvoton,npcm750-smp" binding | |
| ========================================================= | |
| To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be | |
| defined in the "cpus" node. | |
| Enable method name: "nuvoton,npcm750-smp" | |
| Compatible machines: "nuvoton,npcm750" | |
| Compatible CPUs: "arm,cortex-a9" | |
| Related properties: (none) | |
| Note: | |
| This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and | |
| "nuvoton,npcm750-gcr". | |
| Example: | |
| cpus { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| enable-method = "nuvoton,npcm750-smp"; | |
| cpu@0 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a9"; | |
| clocks = <&clk NPCM7XX_CLK_CPU>; | |
| clock-names = "clk_cpu"; | |
| reg = <0>; | |
| next-level-cache = <&L2>; | |
| }; | |
| cpu@1 { | |
| device_type = "cpu"; | |
| compatible = "arm,cortex-a9"; | |
| clocks = <&clk NPCM7XX_CLK_CPU>; | |
| clock-names = "clk_cpu"; | |
| reg = <1>; | |
| next-level-cache = <&L2>; | |
| }; | |
| }; | |