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Googler9398cc32022-12-02 17:21:52 +08001// SPDX-License-Identifier: GPL-2.0
2//
3// flexcan.c - FLEXCAN CAN controller driver
4//
5// Copyright (c) 2005-2006 Varma Electronics Oy
6// Copyright (c) 2009 Sascha Hauer, Pengutronix
7// Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
8// Copyright (c) 2014 David Jander, Protonic Holland
9//
10// Based on code originally by Andrey Volkov <avolkov@varma-el.com>
Googleraf606d22022-10-26 21:40:12 -070011
12#include <linux/netdevice.h>
13#include <linux/can.h>
14#include <linux/can/dev.h>
15#include <linux/can/error.h>
16#include <linux/can/led.h>
Googler9398cc32022-12-02 17:21:52 +080017#include <linux/can/rx-offload.h>
Googleraf606d22022-10-26 21:40:12 -070018#include <linux/clk.h>
19#include <linux/delay.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
Googler9398cc32022-12-02 17:21:52 +080022#include <linux/mfd/syscon.h>
Googleraf606d22022-10-26 21:40:12 -070023#include <linux/module.h>
24#include <linux/of.h>
25#include <linux/of_device.h>
26#include <linux/platform_device.h>
Googler9398cc32022-12-02 17:21:52 +080027#include <linux/pm_runtime.h>
Googleraf606d22022-10-26 21:40:12 -070028#include <linux/regulator/consumer.h>
Googler9398cc32022-12-02 17:21:52 +080029#include <linux/regmap.h>
Googleraf606d22022-10-26 21:40:12 -070030
31#define DRV_NAME "flexcan"
32
33/* 8 for RX fifo and 2 error handling */
34#define FLEXCAN_NAPI_WEIGHT (8 + 2)
35
36/* FLEXCAN module configuration register (CANMCR) bits */
37#define FLEXCAN_MCR_MDIS BIT(31)
38#define FLEXCAN_MCR_FRZ BIT(30)
39#define FLEXCAN_MCR_FEN BIT(29)
40#define FLEXCAN_MCR_HALT BIT(28)
41#define FLEXCAN_MCR_NOT_RDY BIT(27)
42#define FLEXCAN_MCR_WAK_MSK BIT(26)
43#define FLEXCAN_MCR_SOFTRST BIT(25)
44#define FLEXCAN_MCR_FRZ_ACK BIT(24)
45#define FLEXCAN_MCR_SUPV BIT(23)
46#define FLEXCAN_MCR_SLF_WAK BIT(22)
47#define FLEXCAN_MCR_WRN_EN BIT(21)
48#define FLEXCAN_MCR_LPM_ACK BIT(20)
49#define FLEXCAN_MCR_WAK_SRC BIT(19)
50#define FLEXCAN_MCR_DOZE BIT(18)
51#define FLEXCAN_MCR_SRX_DIS BIT(17)
Googler9398cc32022-12-02 17:21:52 +080052#define FLEXCAN_MCR_IRMQ BIT(16)
Googleraf606d22022-10-26 21:40:12 -070053#define FLEXCAN_MCR_LPRIO_EN BIT(13)
54#define FLEXCAN_MCR_AEN BIT(12)
Googler9398cc32022-12-02 17:21:52 +080055/* MCR_MAXMB: maximum used MBs is MAXMB + 1 */
Googleraf606d22022-10-26 21:40:12 -070056#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
57#define FLEXCAN_MCR_IDAM_A (0x0 << 8)
58#define FLEXCAN_MCR_IDAM_B (0x1 << 8)
59#define FLEXCAN_MCR_IDAM_C (0x2 << 8)
60#define FLEXCAN_MCR_IDAM_D (0x3 << 8)
61
62/* FLEXCAN control register (CANCTRL) bits */
63#define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
64#define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
65#define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
66#define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
67#define FLEXCAN_CTRL_BOFF_MSK BIT(15)
68#define FLEXCAN_CTRL_ERR_MSK BIT(14)
69#define FLEXCAN_CTRL_CLK_SRC BIT(13)
70#define FLEXCAN_CTRL_LPB BIT(12)
71#define FLEXCAN_CTRL_TWRN_MSK BIT(11)
72#define FLEXCAN_CTRL_RWRN_MSK BIT(10)
73#define FLEXCAN_CTRL_SMP BIT(7)
74#define FLEXCAN_CTRL_BOFF_REC BIT(6)
75#define FLEXCAN_CTRL_TSYN BIT(5)
76#define FLEXCAN_CTRL_LBUF BIT(4)
77#define FLEXCAN_CTRL_LOM BIT(3)
78#define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
79#define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
80#define FLEXCAN_CTRL_ERR_STATE \
81 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
82 FLEXCAN_CTRL_BOFF_MSK)
83#define FLEXCAN_CTRL_ERR_ALL \
84 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
85
86/* FLEXCAN control register 2 (CTRL2) bits */
87#define FLEXCAN_CTRL2_ECRWRE BIT(29)
88#define FLEXCAN_CTRL2_WRMFRZ BIT(28)
89#define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
90#define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
91#define FLEXCAN_CTRL2_MRP BIT(18)
92#define FLEXCAN_CTRL2_RRS BIT(17)
93#define FLEXCAN_CTRL2_EACEN BIT(16)
94
95/* FLEXCAN memory error control register (MECR) bits */
96#define FLEXCAN_MECR_ECRWRDIS BIT(31)
97#define FLEXCAN_MECR_HANCEI_MSK BIT(19)
98#define FLEXCAN_MECR_FANCEI_MSK BIT(18)
99#define FLEXCAN_MECR_CEI_MSK BIT(16)
100#define FLEXCAN_MECR_HAERRIE BIT(15)
101#define FLEXCAN_MECR_FAERRIE BIT(14)
102#define FLEXCAN_MECR_EXTERRIE BIT(13)
103#define FLEXCAN_MECR_RERRDIS BIT(9)
104#define FLEXCAN_MECR_ECCDIS BIT(8)
105#define FLEXCAN_MECR_NCEFAFRZ BIT(7)
106
107/* FLEXCAN error and status register (ESR) bits */
108#define FLEXCAN_ESR_TWRN_INT BIT(17)
109#define FLEXCAN_ESR_RWRN_INT BIT(16)
110#define FLEXCAN_ESR_BIT1_ERR BIT(15)
111#define FLEXCAN_ESR_BIT0_ERR BIT(14)
112#define FLEXCAN_ESR_ACK_ERR BIT(13)
113#define FLEXCAN_ESR_CRC_ERR BIT(12)
114#define FLEXCAN_ESR_FRM_ERR BIT(11)
115#define FLEXCAN_ESR_STF_ERR BIT(10)
116#define FLEXCAN_ESR_TX_WRN BIT(9)
117#define FLEXCAN_ESR_RX_WRN BIT(8)
118#define FLEXCAN_ESR_IDLE BIT(7)
119#define FLEXCAN_ESR_TXRX BIT(6)
120#define FLEXCAN_EST_FLT_CONF_SHIFT (4)
121#define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
122#define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
123#define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
124#define FLEXCAN_ESR_BOFF_INT BIT(2)
125#define FLEXCAN_ESR_ERR_INT BIT(1)
126#define FLEXCAN_ESR_WAK_INT BIT(0)
127#define FLEXCAN_ESR_ERR_BUS \
128 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
129 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
130 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
131#define FLEXCAN_ESR_ERR_STATE \
132 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
133#define FLEXCAN_ESR_ERR_ALL \
134 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
135#define FLEXCAN_ESR_ALL_INT \
136 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
Googler9398cc32022-12-02 17:21:52 +0800137 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT | \
138 FLEXCAN_ESR_WAK_INT)
Googleraf606d22022-10-26 21:40:12 -0700139
140/* FLEXCAN interrupt flag register (IFLAG) bits */
141/* Errata ERR005829 step7: Reserve first valid MB */
Googler9398cc32022-12-02 17:21:52 +0800142#define FLEXCAN_TX_MB_RESERVED_OFF_FIFO 8
143#define FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP 0
144#define FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST (FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP + 1)
145#define FLEXCAN_IFLAG_MB(x) BIT((x) & 0x1f)
Googleraf606d22022-10-26 21:40:12 -0700146#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
147#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
148#define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
Googleraf606d22022-10-26 21:40:12 -0700149
150/* FLEXCAN message buffers */
Googler9398cc32022-12-02 17:21:52 +0800151#define FLEXCAN_MB_CODE_MASK (0xf << 24)
152#define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24)
Googleraf606d22022-10-26 21:40:12 -0700153#define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
154#define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
155#define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
156#define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
157#define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
158
159#define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
160#define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
161#define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
162#define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
163
164#define FLEXCAN_MB_CNT_SRR BIT(22)
165#define FLEXCAN_MB_CNT_IDE BIT(21)
166#define FLEXCAN_MB_CNT_RTR BIT(20)
167#define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
168#define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
169
170#define FLEXCAN_TIMEOUT_US (250)
171
172/* FLEXCAN hardware feature flags
173 *
174 * Below is some version info we got:
Googler9398cc32022-12-02 17:21:52 +0800175 * SOC Version IP-Version Glitch- [TR]WRN_INT IRQ Err Memory err RTR re-
176 * Filter? connected? Passive detection ception in MB
177 * MX25 FlexCAN2 03.00.00.00 no no no no no
178 * MX28 FlexCAN2 03.00.04.00 yes yes no no no
179 * MX35 FlexCAN2 03.00.00.00 no no no no no
180 * MX53 FlexCAN2 03.00.00.00 yes no no no no
181 * MX6s FlexCAN3 10.00.12.00 yes yes no no yes
182 * VF610 FlexCAN3 ? no yes no yes yes?
183 * LS1021A FlexCAN2 03.00.04.00 no yes no no yes
Googleraf606d22022-10-26 21:40:12 -0700184 *
185 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
186 */
Googler9398cc32022-12-02 17:21:52 +0800187#define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1) /* [TR]WRN_INT not connected */
Googleraf606d22022-10-26 21:40:12 -0700188#define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2) /* Disable RX FIFO Global mask */
Googler9398cc32022-12-02 17:21:52 +0800189#define FLEXCAN_QUIRK_ENABLE_EACEN_RRS BIT(3) /* Enable EACEN and RRS bit in ctrl2 */
190#define FLEXCAN_QUIRK_DISABLE_MECR BIT(4) /* Disable Memory error detection */
191#define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5) /* Use timestamp based offloading */
192#define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6) /* No interrupt for error passive */
193#define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN BIT(7) /* default to BE register access */
194#define FLEXCAN_QUIRK_SETUP_STOP_MODE BIT(8) /* Setup stop mode to support wakeup */
Googleraf606d22022-10-26 21:40:12 -0700195
196/* Structure of the message buffer */
197struct flexcan_mb {
198 u32 can_ctrl;
199 u32 can_id;
Googler9398cc32022-12-02 17:21:52 +0800200 u32 data[];
Googleraf606d22022-10-26 21:40:12 -0700201};
202
203/* Structure of the hardware registers */
204struct flexcan_regs {
205 u32 mcr; /* 0x00 */
206 u32 ctrl; /* 0x04 */
207 u32 timer; /* 0x08 */
208 u32 _reserved1; /* 0x0c */
209 u32 rxgmask; /* 0x10 */
210 u32 rx14mask; /* 0x14 */
211 u32 rx15mask; /* 0x18 */
212 u32 ecr; /* 0x1c */
213 u32 esr; /* 0x20 */
214 u32 imask2; /* 0x24 */
215 u32 imask1; /* 0x28 */
216 u32 iflag2; /* 0x2c */
217 u32 iflag1; /* 0x30 */
Googler9398cc32022-12-02 17:21:52 +0800218 union { /* 0x34 */
219 u32 gfwr_mx28; /* MX28, MX53 */
220 u32 ctrl2; /* MX6, VF610 */
221 };
Googleraf606d22022-10-26 21:40:12 -0700222 u32 esr2; /* 0x38 */
223 u32 imeur; /* 0x3c */
224 u32 lrfr; /* 0x40 */
225 u32 crcr; /* 0x44 */
226 u32 rxfgmask; /* 0x48 */
227 u32 rxfir; /* 0x4c */
228 u32 _reserved3[12]; /* 0x50 */
Googler9398cc32022-12-02 17:21:52 +0800229 u8 mb[2][512]; /* 0x80 */
Googleraf606d22022-10-26 21:40:12 -0700230 /* FIFO-mode:
231 * MB
232 * 0x080...0x08f 0 RX message buffer
233 * 0x090...0x0df 1-5 reserverd
234 * 0x0e0...0x0ff 6-7 8 entry ID table
235 * (mx25, mx28, mx35, mx53)
236 * 0x0e0...0x2df 6-7..37 8..128 entry ID table
237 * size conf'ed via ctrl2::RFFN
238 * (mx6, vf610)
239 */
Googler9398cc32022-12-02 17:21:52 +0800240 u32 _reserved4[256]; /* 0x480 */
241 u32 rximr[64]; /* 0x880 */
242 u32 _reserved5[24]; /* 0x980 */
243 u32 gfwr_mx6; /* 0x9e0 - MX6 */
244 u32 _reserved6[63]; /* 0x9e4 */
Googleraf606d22022-10-26 21:40:12 -0700245 u32 mecr; /* 0xae0 */
246 u32 erriar; /* 0xae4 */
247 u32 erridpr; /* 0xae8 */
248 u32 errippr; /* 0xaec */
249 u32 rerrar; /* 0xaf0 */
250 u32 rerrdr; /* 0xaf4 */
251 u32 rerrsynr; /* 0xaf8 */
252 u32 errsr; /* 0xafc */
253};
254
255struct flexcan_devtype_data {
256 u32 quirks; /* quirks needed for different IP cores */
257};
258
Googler9398cc32022-12-02 17:21:52 +0800259struct flexcan_stop_mode {
260 struct regmap *gpr;
261 u8 req_gpr;
262 u8 req_bit;
263 u8 ack_gpr;
264 u8 ack_bit;
265};
266
Googleraf606d22022-10-26 21:40:12 -0700267struct flexcan_priv {
268 struct can_priv can;
Googler9398cc32022-12-02 17:21:52 +0800269 struct can_rx_offload offload;
270 struct device *dev;
Googleraf606d22022-10-26 21:40:12 -0700271
272 struct flexcan_regs __iomem *regs;
Googler9398cc32022-12-02 17:21:52 +0800273 struct flexcan_mb __iomem *tx_mb;
274 struct flexcan_mb __iomem *tx_mb_reserved;
275 u8 tx_mb_idx;
276 u8 mb_count;
277 u8 mb_size;
278 u8 clk_src; /* clock source of CAN Protocol Engine */
279
Googleraf606d22022-10-26 21:40:12 -0700280 u32 reg_ctrl_default;
Googler9398cc32022-12-02 17:21:52 +0800281 u32 reg_imask1_default;
282 u32 reg_imask2_default;
Googleraf606d22022-10-26 21:40:12 -0700283
284 struct clk *clk_ipg;
285 struct clk *clk_per;
Googleraf606d22022-10-26 21:40:12 -0700286 const struct flexcan_devtype_data *devtype_data;
287 struct regulator *reg_xceiver;
Googler9398cc32022-12-02 17:21:52 +0800288 struct flexcan_stop_mode stm;
289
290 /* Read and Write APIs */
291 u32 (*read)(void __iomem *addr);
292 void (*write)(u32 val, void __iomem *addr);
Googleraf606d22022-10-26 21:40:12 -0700293};
294
Googler9398cc32022-12-02 17:21:52 +0800295static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
296 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
297 FLEXCAN_QUIRK_BROKEN_PERR_STATE |
298 FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN,
Googleraf606d22022-10-26 21:40:12 -0700299};
300
Googler9398cc32022-12-02 17:21:52 +0800301static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
302 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
303 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
Googleraf606d22022-10-26 21:40:12 -0700304};
305
Googler9398cc32022-12-02 17:21:52 +0800306static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
307 .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
308};
309
310static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
311 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
312 FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
313 FLEXCAN_QUIRK_SETUP_STOP_MODE,
314};
315
316static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
317 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
318 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP |
319 FLEXCAN_QUIRK_BROKEN_PERR_STATE,
320};
321
322static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
323 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
324 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
Googleraf606d22022-10-26 21:40:12 -0700325};
326
327static const struct can_bittiming_const flexcan_bittiming_const = {
328 .name = DRV_NAME,
329 .tseg1_min = 4,
330 .tseg1_max = 16,
331 .tseg2_min = 2,
332 .tseg2_max = 8,
333 .sjw_max = 4,
334 .brp_min = 1,
335 .brp_max = 256,
336 .brp_inc = 1,
337};
338
Googler9398cc32022-12-02 17:21:52 +0800339/* FlexCAN module is essentially modelled as a little-endian IP in most
340 * SoCs, i.e the registers as well as the message buffer areas are
341 * implemented in a little-endian fashion.
342 *
343 * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
344 * module in a big-endian fashion (i.e the registers as well as the
345 * message buffer areas are implemented in a big-endian way).
346 *
347 * In addition, the FlexCAN module can be found on SoCs having ARM or
348 * PPC cores. So, we need to abstract off the register read/write
349 * functions, ensuring that these cater to all the combinations of module
350 * endianness and underlying CPU endianness.
Googleraf606d22022-10-26 21:40:12 -0700351 */
Googler9398cc32022-12-02 17:21:52 +0800352static inline u32 flexcan_read_be(void __iomem *addr)
Googleraf606d22022-10-26 21:40:12 -0700353{
Googler9398cc32022-12-02 17:21:52 +0800354 return ioread32be(addr);
Googleraf606d22022-10-26 21:40:12 -0700355}
356
Googler9398cc32022-12-02 17:21:52 +0800357static inline void flexcan_write_be(u32 val, void __iomem *addr)
Googleraf606d22022-10-26 21:40:12 -0700358{
Googler9398cc32022-12-02 17:21:52 +0800359 iowrite32be(val, addr);
Googleraf606d22022-10-26 21:40:12 -0700360}
361
Googler9398cc32022-12-02 17:21:52 +0800362static inline u32 flexcan_read_le(void __iomem *addr)
Googleraf606d22022-10-26 21:40:12 -0700363{
Googler9398cc32022-12-02 17:21:52 +0800364 return ioread32(addr);
Googleraf606d22022-10-26 21:40:12 -0700365}
Googler9398cc32022-12-02 17:21:52 +0800366
367static inline void flexcan_write_le(u32 val, void __iomem *addr)
368{
369 iowrite32(val, addr);
370}
371
372static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv,
373 u8 mb_index)
374{
375 u8 bank_size;
376 bool bank;
377
378 if (WARN_ON(mb_index >= priv->mb_count))
379 return NULL;
380
381 bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size;
382
383 bank = mb_index >= bank_size;
384 if (bank)
385 mb_index -= bank_size;
386
387 return (struct flexcan_mb __iomem *)
388 (&priv->regs->mb[bank][priv->mb_size * mb_index]);
389}
390
391static int flexcan_low_power_enter_ack(struct flexcan_priv *priv)
392{
393 struct flexcan_regs __iomem *regs = priv->regs;
394 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
395
396 while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
397 udelay(10);
398
399 if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
400 return -ETIMEDOUT;
401
402 return 0;
403}
404
405static int flexcan_low_power_exit_ack(struct flexcan_priv *priv)
406{
407 struct flexcan_regs __iomem *regs = priv->regs;
408 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
409
410 while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK))
411 udelay(10);
412
413 if (priv->read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)
414 return -ETIMEDOUT;
415
416 return 0;
417}
418
419static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable)
420{
421 struct flexcan_regs __iomem *regs = priv->regs;
422 u32 reg_mcr;
423
424 reg_mcr = priv->read(&regs->mcr);
425
426 if (enable)
427 reg_mcr |= FLEXCAN_MCR_WAK_MSK;
428 else
429 reg_mcr &= ~FLEXCAN_MCR_WAK_MSK;
430
431 priv->write(reg_mcr, &regs->mcr);
432}
433
434static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv)
435{
436 struct flexcan_regs __iomem *regs = priv->regs;
437 u32 reg_mcr;
438
439 reg_mcr = priv->read(&regs->mcr);
440 reg_mcr |= FLEXCAN_MCR_SLF_WAK;
441 priv->write(reg_mcr, &regs->mcr);
442
443 /* enable stop request */
444 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
445 1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
446
447 return flexcan_low_power_enter_ack(priv);
448}
449
450static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv)
451{
452 struct flexcan_regs __iomem *regs = priv->regs;
453 u32 reg_mcr;
454
455 /* remove stop request */
456 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
457 1 << priv->stm.req_bit, 0);
458
459
460 reg_mcr = priv->read(&regs->mcr);
461 reg_mcr &= ~FLEXCAN_MCR_SLF_WAK;
462 priv->write(reg_mcr, &regs->mcr);
463
464 return flexcan_low_power_exit_ack(priv);
465}
466
467static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
468{
469 struct flexcan_regs __iomem *regs = priv->regs;
470 u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
471
472 priv->write(reg_ctrl, &regs->ctrl);
473}
474
475static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
476{
477 struct flexcan_regs __iomem *regs = priv->regs;
478 u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
479
480 priv->write(reg_ctrl, &regs->ctrl);
481}
482
483static int flexcan_clks_enable(const struct flexcan_priv *priv)
484{
485 int err;
486
487 err = clk_prepare_enable(priv->clk_ipg);
488 if (err)
489 return err;
490
491 err = clk_prepare_enable(priv->clk_per);
492 if (err)
493 clk_disable_unprepare(priv->clk_ipg);
494
495 return err;
496}
497
498static void flexcan_clks_disable(const struct flexcan_priv *priv)
499{
500 clk_disable_unprepare(priv->clk_per);
501 clk_disable_unprepare(priv->clk_ipg);
502}
Googleraf606d22022-10-26 21:40:12 -0700503
504static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
505{
506 if (!priv->reg_xceiver)
507 return 0;
508
509 return regulator_enable(priv->reg_xceiver);
510}
511
512static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
513{
514 if (!priv->reg_xceiver)
515 return 0;
516
517 return regulator_disable(priv->reg_xceiver);
518}
519
Googleraf606d22022-10-26 21:40:12 -0700520static int flexcan_chip_enable(struct flexcan_priv *priv)
521{
522 struct flexcan_regs __iomem *regs = priv->regs;
Googleraf606d22022-10-26 21:40:12 -0700523 u32 reg;
524
Googler9398cc32022-12-02 17:21:52 +0800525 reg = priv->read(&regs->mcr);
Googleraf606d22022-10-26 21:40:12 -0700526 reg &= ~FLEXCAN_MCR_MDIS;
Googler9398cc32022-12-02 17:21:52 +0800527 priv->write(reg, &regs->mcr);
Googleraf606d22022-10-26 21:40:12 -0700528
Googler9398cc32022-12-02 17:21:52 +0800529 return flexcan_low_power_exit_ack(priv);
Googleraf606d22022-10-26 21:40:12 -0700530}
531
532static int flexcan_chip_disable(struct flexcan_priv *priv)
533{
534 struct flexcan_regs __iomem *regs = priv->regs;
Googleraf606d22022-10-26 21:40:12 -0700535 u32 reg;
536
Googler9398cc32022-12-02 17:21:52 +0800537 reg = priv->read(&regs->mcr);
Googleraf606d22022-10-26 21:40:12 -0700538 reg |= FLEXCAN_MCR_MDIS;
Googler9398cc32022-12-02 17:21:52 +0800539 priv->write(reg, &regs->mcr);
Googleraf606d22022-10-26 21:40:12 -0700540
Googler9398cc32022-12-02 17:21:52 +0800541 return flexcan_low_power_enter_ack(priv);
Googleraf606d22022-10-26 21:40:12 -0700542}
543
544static int flexcan_chip_freeze(struct flexcan_priv *priv)
545{
546 struct flexcan_regs __iomem *regs = priv->regs;
Googlerb48fa912023-03-17 12:40:29 +0530547 unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
Googleraf606d22022-10-26 21:40:12 -0700548 u32 reg;
549
Googler9398cc32022-12-02 17:21:52 +0800550 reg = priv->read(&regs->mcr);
Googlerb48fa912023-03-17 12:40:29 +0530551 reg |= FLEXCAN_MCR_HALT;
Googler9398cc32022-12-02 17:21:52 +0800552 priv->write(reg, &regs->mcr);
Googler38bda472022-08-19 10:07:08 -0700553
Googler9398cc32022-12-02 17:21:52 +0800554 while (timeout-- && !(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
Googleraf606d22022-10-26 21:40:12 -0700555 udelay(100);
556
Googler9398cc32022-12-02 17:21:52 +0800557 if (!(priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
Googleraf606d22022-10-26 21:40:12 -0700558 return -ETIMEDOUT;
559
560 return 0;
561}
562
563static int flexcan_chip_unfreeze(struct flexcan_priv *priv)
564{
565 struct flexcan_regs __iomem *regs = priv->regs;
566 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
567 u32 reg;
568
Googler9398cc32022-12-02 17:21:52 +0800569 reg = priv->read(&regs->mcr);
Googleraf606d22022-10-26 21:40:12 -0700570 reg &= ~FLEXCAN_MCR_HALT;
Googler9398cc32022-12-02 17:21:52 +0800571 priv->write(reg, &regs->mcr);
Googleraf606d22022-10-26 21:40:12 -0700572
Googler9398cc32022-12-02 17:21:52 +0800573 while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK))
Googleraf606d22022-10-26 21:40:12 -0700574 udelay(10);
575
Googler9398cc32022-12-02 17:21:52 +0800576 if (priv->read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)
Googleraf606d22022-10-26 21:40:12 -0700577 return -ETIMEDOUT;
578
579 return 0;
580}
581
582static int flexcan_chip_softreset(struct flexcan_priv *priv)
583{
584 struct flexcan_regs __iomem *regs = priv->regs;
585 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
586
Googler9398cc32022-12-02 17:21:52 +0800587 priv->write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
588 while (timeout-- && (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST))
Googleraf606d22022-10-26 21:40:12 -0700589 udelay(10);
590
Googler9398cc32022-12-02 17:21:52 +0800591 if (priv->read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)
Googleraf606d22022-10-26 21:40:12 -0700592 return -ETIMEDOUT;
593
594 return 0;
595}
596
597static int __flexcan_get_berr_counter(const struct net_device *dev,
598 struct can_berr_counter *bec)
599{
600 const struct flexcan_priv *priv = netdev_priv(dev);
601 struct flexcan_regs __iomem *regs = priv->regs;
Googler9398cc32022-12-02 17:21:52 +0800602 u32 reg = priv->read(&regs->ecr);
Googleraf606d22022-10-26 21:40:12 -0700603
604 bec->txerr = (reg >> 0) & 0xff;
605 bec->rxerr = (reg >> 8) & 0xff;
606
607 return 0;
608}
609
610static int flexcan_get_berr_counter(const struct net_device *dev,
611 struct can_berr_counter *bec)
612{
613 const struct flexcan_priv *priv = netdev_priv(dev);
614 int err;
615
Googler9398cc32022-12-02 17:21:52 +0800616 err = pm_runtime_get_sync(priv->dev);
617 if (err < 0) {
618 pm_runtime_put_noidle(priv->dev);
Googleraf606d22022-10-26 21:40:12 -0700619 return err;
Googler9398cc32022-12-02 17:21:52 +0800620 }
Googleraf606d22022-10-26 21:40:12 -0700621
622 err = __flexcan_get_berr_counter(dev, bec);
623
Googler9398cc32022-12-02 17:21:52 +0800624 pm_runtime_put(priv->dev);
Googleraf606d22022-10-26 21:40:12 -0700625
626 return err;
627}
628
Googler9398cc32022-12-02 17:21:52 +0800629static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
Googleraf606d22022-10-26 21:40:12 -0700630{
631 const struct flexcan_priv *priv = netdev_priv(dev);
Googleraf606d22022-10-26 21:40:12 -0700632 struct can_frame *cf = (struct can_frame *)skb->data;
633 u32 can_id;
634 u32 data;
635 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | (cf->can_dlc << 16);
Googler9398cc32022-12-02 17:21:52 +0800636 int i;
Googleraf606d22022-10-26 21:40:12 -0700637
638 if (can_dropped_invalid_skb(dev, skb))
639 return NETDEV_TX_OK;
640
641 netif_stop_queue(dev);
642
643 if (cf->can_id & CAN_EFF_FLAG) {
644 can_id = cf->can_id & CAN_EFF_MASK;
645 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
646 } else {
647 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
648 }
649
650 if (cf->can_id & CAN_RTR_FLAG)
651 ctrl |= FLEXCAN_MB_CNT_RTR;
652
Googler9398cc32022-12-02 17:21:52 +0800653 for (i = 0; i < cf->can_dlc; i += sizeof(u32)) {
654 data = be32_to_cpup((__be32 *)&cf->data[i]);
655 priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]);
Googleraf606d22022-10-26 21:40:12 -0700656 }
657
658 can_put_echo_skb(skb, dev, 0);
659
Googler9398cc32022-12-02 17:21:52 +0800660 priv->write(can_id, &priv->tx_mb->can_id);
661 priv->write(ctrl, &priv->tx_mb->can_ctrl);
Googleraf606d22022-10-26 21:40:12 -0700662
663 /* Errata ERR005829 step8:
664 * Write twice INACTIVE(0x8) code to first MB.
665 */
Googler9398cc32022-12-02 17:21:52 +0800666 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
667 &priv->tx_mb_reserved->can_ctrl);
668 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
669 &priv->tx_mb_reserved->can_ctrl);
Googleraf606d22022-10-26 21:40:12 -0700670
671 return NETDEV_TX_OK;
672}
673
Googler9398cc32022-12-02 17:21:52 +0800674static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr)
Googleraf606d22022-10-26 21:40:12 -0700675{
676 struct flexcan_priv *priv = netdev_priv(dev);
Googler9398cc32022-12-02 17:21:52 +0800677 struct flexcan_regs __iomem *regs = priv->regs;
678 struct sk_buff *skb;
679 struct can_frame *cf;
680 bool rx_errors = false, tx_errors = false;
681 u32 timestamp;
682 int err;
683
684 timestamp = priv->read(&regs->timer) << 16;
685
686 skb = alloc_can_err_skb(dev, &cf);
687 if (unlikely(!skb))
688 return;
Googleraf606d22022-10-26 21:40:12 -0700689
690 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
691
692 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
693 netdev_dbg(dev, "BIT1_ERR irq\n");
694 cf->data[2] |= CAN_ERR_PROT_BIT1;
Googler9398cc32022-12-02 17:21:52 +0800695 tx_errors = true;
Googleraf606d22022-10-26 21:40:12 -0700696 }
697 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
698 netdev_dbg(dev, "BIT0_ERR irq\n");
699 cf->data[2] |= CAN_ERR_PROT_BIT0;
Googler9398cc32022-12-02 17:21:52 +0800700 tx_errors = true;
Googleraf606d22022-10-26 21:40:12 -0700701 }
702 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
703 netdev_dbg(dev, "ACK_ERR irq\n");
704 cf->can_id |= CAN_ERR_ACK;
705 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
Googler9398cc32022-12-02 17:21:52 +0800706 tx_errors = true;
Googleraf606d22022-10-26 21:40:12 -0700707 }
708 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
709 netdev_dbg(dev, "CRC_ERR irq\n");
710 cf->data[2] |= CAN_ERR_PROT_BIT;
711 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
Googler9398cc32022-12-02 17:21:52 +0800712 rx_errors = true;
Googleraf606d22022-10-26 21:40:12 -0700713 }
714 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
715 netdev_dbg(dev, "FRM_ERR irq\n");
716 cf->data[2] |= CAN_ERR_PROT_FORM;
Googler9398cc32022-12-02 17:21:52 +0800717 rx_errors = true;
Googleraf606d22022-10-26 21:40:12 -0700718 }
719 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
720 netdev_dbg(dev, "STF_ERR irq\n");
721 cf->data[2] |= CAN_ERR_PROT_STUFF;
Googler9398cc32022-12-02 17:21:52 +0800722 rx_errors = true;
Googleraf606d22022-10-26 21:40:12 -0700723 }
724
725 priv->can.can_stats.bus_error++;
726 if (rx_errors)
727 dev->stats.rx_errors++;
728 if (tx_errors)
729 dev->stats.tx_errors++;
Googler9398cc32022-12-02 17:21:52 +0800730
731 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
732 if (err)
733 dev->stats.rx_fifo_errors++;
Googleraf606d22022-10-26 21:40:12 -0700734}
735
Googler9398cc32022-12-02 17:21:52 +0800736static void flexcan_irq_state(struct net_device *dev, u32 reg_esr)
Googler9726be62022-12-14 05:53:31 +0000737{
738 struct flexcan_priv *priv = netdev_priv(dev);
Googler9398cc32022-12-02 17:21:52 +0800739 struct flexcan_regs __iomem *regs = priv->regs;
Googler9726be62022-12-14 05:53:31 +0000740 struct sk_buff *skb;
741 struct can_frame *cf;
Googler9398cc32022-12-02 17:21:52 +0800742 enum can_state new_state, rx_state, tx_state;
Googleraf606d22022-10-26 21:40:12 -0700743 int flt;
744 struct can_berr_counter bec;
Googler9398cc32022-12-02 17:21:52 +0800745 u32 timestamp;
746 int err;
747
748 timestamp = priv->read(&regs->timer) << 16;
Googleraf606d22022-10-26 21:40:12 -0700749
750 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
751 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
752 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ?
753 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
754 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ?
755 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE;
756 new_state = max(tx_state, rx_state);
757 } else {
758 __flexcan_get_berr_counter(dev, &bec);
759 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ?
760 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF;
761 rx_state = bec.rxerr >= bec.txerr ? new_state : 0;
762 tx_state = bec.rxerr <= bec.txerr ? new_state : 0;
763 }
764
765 /* state hasn't changed */
766 if (likely(new_state == priv->can.state))
Googler9398cc32022-12-02 17:21:52 +0800767 return;
Googleraf606d22022-10-26 21:40:12 -0700768
769 skb = alloc_can_err_skb(dev, &cf);
770 if (unlikely(!skb))
Googler9398cc32022-12-02 17:21:52 +0800771 return;
Googleraf606d22022-10-26 21:40:12 -0700772
773 can_change_state(dev, cf, tx_state, rx_state);
774
775 if (unlikely(new_state == CAN_STATE_BUS_OFF))
776 can_bus_off(dev);
777
Googler9398cc32022-12-02 17:21:52 +0800778 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp);
779 if (err)
780 dev->stats.rx_fifo_errors++;
Googleraf606d22022-10-26 21:40:12 -0700781}
782
Googler9398cc32022-12-02 17:21:52 +0800783static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload)
Googleraf606d22022-10-26 21:40:12 -0700784{
Googler9398cc32022-12-02 17:21:52 +0800785 return container_of(offload, struct flexcan_priv, offload);
786}
Googler0109c452022-10-13 17:50:39 +0800787
Googler9398cc32022-12-02 17:21:52 +0800788static unsigned int flexcan_mailbox_read(struct can_rx_offload *offload,
789 struct can_frame *cf,
790 u32 *timestamp, unsigned int n)
791{
792 struct flexcan_priv *priv = rx_offload_to_priv(offload);
793 struct flexcan_regs __iomem *regs = priv->regs;
794 struct flexcan_mb __iomem *mb;
795 u32 reg_ctrl, reg_id, reg_iflag1;
796 int i;
797
798 mb = flexcan_get_mb(priv, n);
799
800 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
801 u32 code;
802
803 do {
804 reg_ctrl = priv->read(&mb->can_ctrl);
805 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
806
807 /* is this MB empty? */
808 code = reg_ctrl & FLEXCAN_MB_CODE_MASK;
809 if ((code != FLEXCAN_MB_CODE_RX_FULL) &&
810 (code != FLEXCAN_MB_CODE_RX_OVERRUN))
811 return 0;
812
813 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) {
814 /* This MB was overrun, we lost data */
815 offload->dev->stats.rx_over_errors++;
816 offload->dev->stats.rx_errors++;
817 }
818 } else {
819 reg_iflag1 = priv->read(&regs->iflag1);
820 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
821 return 0;
822
823 reg_ctrl = priv->read(&mb->can_ctrl);
824 }
825
826 /* increase timstamp to full 32 bit */
827 *timestamp = reg_ctrl << 16;
828
829 reg_id = priv->read(&mb->can_id);
Googleraf606d22022-10-26 21:40:12 -0700830 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
831 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
832 else
833 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
834
835 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
836 cf->can_id |= CAN_RTR_FLAG;
837 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
838
Googler9398cc32022-12-02 17:21:52 +0800839 for (i = 0; i < cf->can_dlc; i += sizeof(u32)) {
840 __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)]));
841 *(__be32 *)(cf->data + i) = data;
Googler38bda472022-08-19 10:07:08 -0700842 }
Googler4f18c0c2022-09-20 17:23:36 +0800843
Googler9398cc32022-12-02 17:21:52 +0800844 /* mark as read */
845 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
846 /* Clear IRQ */
847 if (n < 32)
848 priv->write(BIT(n), &regs->iflag1);
849 else
850 priv->write(BIT(n - 32), &regs->iflag2);
851 } else {
852 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
853 }
Googler9726be62022-12-14 05:53:31 +0000854
Googler9398cc32022-12-02 17:21:52 +0800855 /* Read the Free Running Timer. It is optional but recommended
856 * to unlock Mailbox as soon as possible and make it available
857 * for reception.
858 */
859 priv->read(&regs->timer);
Googleraf606d22022-10-26 21:40:12 -0700860
861 return 1;
862}
863
Googler9398cc32022-12-02 17:21:52 +0800864
865static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv)
Googleraf606d22022-10-26 21:40:12 -0700866{
Googleraf606d22022-10-26 21:40:12 -0700867 struct flexcan_regs __iomem *regs = priv->regs;
Googler9398cc32022-12-02 17:21:52 +0800868 u32 iflag1, iflag2;
Googleraf606d22022-10-26 21:40:12 -0700869
Googler9398cc32022-12-02 17:21:52 +0800870 iflag2 = priv->read(&regs->iflag2) & priv->reg_imask2_default &
871 ~FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
872 iflag1 = priv->read(&regs->iflag1) & priv->reg_imask1_default;
Googleraf606d22022-10-26 21:40:12 -0700873
Googler9398cc32022-12-02 17:21:52 +0800874 return (u64)iflag2 << 32 | iflag1;
Googleraf606d22022-10-26 21:40:12 -0700875}
876
877static irqreturn_t flexcan_irq(int irq, void *dev_id)
878{
879 struct net_device *dev = dev_id;
880 struct net_device_stats *stats = &dev->stats;
881 struct flexcan_priv *priv = netdev_priv(dev);
882 struct flexcan_regs __iomem *regs = priv->regs;
Googler9398cc32022-12-02 17:21:52 +0800883 irqreturn_t handled = IRQ_NONE;
884 u32 reg_iflag2, reg_esr;
885 enum can_state last_state = priv->can.state;
Googleraf606d22022-10-26 21:40:12 -0700886
Googler9398cc32022-12-02 17:21:52 +0800887 /* reception interrupt */
888 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
889 u64 reg_iflag;
890 int ret;
Googleraf606d22022-10-26 21:40:12 -0700891
Googler9398cc32022-12-02 17:21:52 +0800892 while ((reg_iflag = flexcan_read_reg_iflag_rx(priv))) {
893 handled = IRQ_HANDLED;
894 ret = can_rx_offload_irq_offload_timestamp(&priv->offload,
895 reg_iflag);
896 if (!ret)
897 break;
898 }
899 } else {
900 u32 reg_iflag1;
Googleraf606d22022-10-26 21:40:12 -0700901
Googler9398cc32022-12-02 17:21:52 +0800902 reg_iflag1 = priv->read(&regs->iflag1);
903 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) {
904 handled = IRQ_HANDLED;
905 can_rx_offload_irq_offload_fifo(&priv->offload);
906 }
907
908 /* FIFO overflow interrupt */
909 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
910 handled = IRQ_HANDLED;
911 priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
912 &regs->iflag1);
913 dev->stats.rx_over_errors++;
914 dev->stats.rx_errors++;
915 }
Googleraf606d22022-10-26 21:40:12 -0700916 }
917
Googler9398cc32022-12-02 17:21:52 +0800918 reg_iflag2 = priv->read(&regs->iflag2);
Googleraf606d22022-10-26 21:40:12 -0700919
920 /* transmission complete interrupt */
Googler9398cc32022-12-02 17:21:52 +0800921 if (reg_iflag2 & FLEXCAN_IFLAG_MB(priv->tx_mb_idx)) {
922 u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl);
923
924 handled = IRQ_HANDLED;
925 stats->tx_bytes += can_rx_offload_get_echo_skb(&priv->offload,
926 0, reg_ctrl << 16);
Googleraf606d22022-10-26 21:40:12 -0700927 stats->tx_packets++;
928 can_led_event(dev, CAN_LED_EVENT_TX);
929
930 /* after sending a RTR frame MB is in RX mode */
Googler9398cc32022-12-02 17:21:52 +0800931 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
932 &priv->tx_mb->can_ctrl);
933 priv->write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), &regs->iflag2);
Googleraf606d22022-10-26 21:40:12 -0700934 netif_wake_queue(dev);
935 }
936
Googler9398cc32022-12-02 17:21:52 +0800937 reg_esr = priv->read(&regs->esr);
938
939 /* ACK all bus error and state change IRQ sources */
940 if (reg_esr & FLEXCAN_ESR_ALL_INT) {
941 handled = IRQ_HANDLED;
942 priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
943 }
944
945 /* state change interrupt or broken error state quirk fix is enabled */
946 if ((reg_esr & FLEXCAN_ESR_ERR_STATE) ||
947 (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE |
948 FLEXCAN_QUIRK_BROKEN_PERR_STATE)))
949 flexcan_irq_state(dev, reg_esr);
950
951 /* bus error IRQ - handle if bus error reporting is activated */
952 if ((reg_esr & FLEXCAN_ESR_ERR_BUS) &&
953 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
954 flexcan_irq_bus_err(dev, reg_esr);
955
956 /* availability of error interrupt among state transitions in case
957 * bus error reporting is de-activated and
958 * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled:
959 * +--------------------------------------------------------------+
960 * | +----------------------------------------------+ [stopped / |
961 * | | | sleeping] -+
962 * +-+-> active <-> warning <-> passive -> bus off -+
963 * ___________^^^^^^^^^^^^_______________________________
964 * disabled(1) enabled disabled
965 *
966 * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled
967 */
968 if ((last_state != priv->can.state) &&
969 (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) &&
970 !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
971 switch (priv->can.state) {
972 case CAN_STATE_ERROR_ACTIVE:
973 if (priv->devtype_data->quirks &
974 FLEXCAN_QUIRK_BROKEN_WERR_STATE)
975 flexcan_error_irq_enable(priv);
976 else
977 flexcan_error_irq_disable(priv);
978 break;
979
980 case CAN_STATE_ERROR_WARNING:
981 flexcan_error_irq_enable(priv);
982 break;
983
984 case CAN_STATE_ERROR_PASSIVE:
985 case CAN_STATE_BUS_OFF:
986 flexcan_error_irq_disable(priv);
987 break;
988
989 default:
990 break;
991 }
992 }
993
994 return handled;
Googleraf606d22022-10-26 21:40:12 -0700995}
996
997static void flexcan_set_bittiming(struct net_device *dev)
998{
999 const struct flexcan_priv *priv = netdev_priv(dev);
1000 const struct can_bittiming *bt = &priv->can.bittiming;
1001 struct flexcan_regs __iomem *regs = priv->regs;
1002 u32 reg;
1003
Googler9398cc32022-12-02 17:21:52 +08001004 reg = priv->read(&regs->ctrl);
Googleraf606d22022-10-26 21:40:12 -07001005 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
1006 FLEXCAN_CTRL_RJW(0x3) |
1007 FLEXCAN_CTRL_PSEG1(0x7) |
1008 FLEXCAN_CTRL_PSEG2(0x7) |
1009 FLEXCAN_CTRL_PROPSEG(0x7) |
1010 FLEXCAN_CTRL_LPB |
1011 FLEXCAN_CTRL_SMP |
1012 FLEXCAN_CTRL_LOM);
1013
1014 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
1015 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
1016 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
1017 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
1018 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
1019
1020 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1021 reg |= FLEXCAN_CTRL_LPB;
1022 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1023 reg |= FLEXCAN_CTRL_LOM;
1024 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
1025 reg |= FLEXCAN_CTRL_SMP;
1026
1027 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
Googler9398cc32022-12-02 17:21:52 +08001028 priv->write(reg, &regs->ctrl);
Googleraf606d22022-10-26 21:40:12 -07001029
1030 /* print chip status */
1031 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
Googler9398cc32022-12-02 17:21:52 +08001032 priv->read(&regs->mcr), priv->read(&regs->ctrl));
Googleraf606d22022-10-26 21:40:12 -07001033}
1034
1035/* flexcan_chip_start
1036 *
1037 * this functions is entered with clocks enabled
1038 *
1039 */
1040static int flexcan_chip_start(struct net_device *dev)
1041{
1042 struct flexcan_priv *priv = netdev_priv(dev);
1043 struct flexcan_regs __iomem *regs = priv->regs;
1044 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
1045 int err, i;
Googler9398cc32022-12-02 17:21:52 +08001046 struct flexcan_mb __iomem *mb;
Googleraf606d22022-10-26 21:40:12 -07001047
1048 /* enable module */
1049 err = flexcan_chip_enable(priv);
1050 if (err)
1051 return err;
1052
1053 /* soft reset */
1054 err = flexcan_chip_softreset(priv);
1055 if (err)
1056 goto out_chip_disable;
1057
1058 flexcan_set_bittiming(dev);
1059
Googleraf606d22022-10-26 21:40:12 -07001060 /* MCR
1061 *
Googlerb48fa912023-03-17 12:40:29 +05301062 * enable freeze
1063 * halt now
Googleraf606d22022-10-26 21:40:12 -07001064 * only supervisor access
1065 * enable warning int
Googler9398cc32022-12-02 17:21:52 +08001066 * enable individual RX masking
Googleraf606d22022-10-26 21:40:12 -07001067 * choose format C
1068 * set max mailbox number
1069 */
Googler9398cc32022-12-02 17:21:52 +08001070 reg_mcr = priv->read(&regs->mcr);
Googleraf606d22022-10-26 21:40:12 -07001071 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
Googlerb48fa912023-03-17 12:40:29 +05301072 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
1073 FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ | FLEXCAN_MCR_IDAM_C |
1074 FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
Googler9398cc32022-12-02 17:21:52 +08001075
1076 /* MCR
1077 *
1078 * FIFO:
1079 * - disable for timestamp mode
1080 * - enable for FIFO mode
1081 */
1082 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1083 reg_mcr &= ~FLEXCAN_MCR_FEN;
1084 else
1085 reg_mcr |= FLEXCAN_MCR_FEN;
1086
1087 /* MCR
1088 *
1089 * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be
1090 * asserted because this will impede the self reception
1091 * of a transmitted message. This is not documented in
1092 * earlier versions of flexcan block guide.
1093 *
1094 * Self Reception:
1095 * - enable Self Reception for loopback mode
1096 * (by clearing "Self Reception Disable" bit)
1097 * - disable for normal operation
1098 */
1099 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
1100 reg_mcr &= ~FLEXCAN_MCR_SRX_DIS;
1101 else
1102 reg_mcr |= FLEXCAN_MCR_SRX_DIS;
1103
Googleraf606d22022-10-26 21:40:12 -07001104 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
Googler9398cc32022-12-02 17:21:52 +08001105 priv->write(reg_mcr, &regs->mcr);
Googleraf606d22022-10-26 21:40:12 -07001106
1107 /* CTRL
1108 *
1109 * disable timer sync feature
1110 *
1111 * disable auto busoff recovery
1112 * transmit lowest buffer first
1113 *
1114 * enable tx and rx warning interrupt
1115 * enable bus off interrupt
1116 * (== FLEXCAN_CTRL_ERR_STATE)
1117 */
Googler9398cc32022-12-02 17:21:52 +08001118 reg_ctrl = priv->read(&regs->ctrl);
Googleraf606d22022-10-26 21:40:12 -07001119 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
1120 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
1121 FLEXCAN_CTRL_ERR_STATE;
1122
1123 /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
1124 * on most Flexcan cores, too. Otherwise we don't get
1125 * any error warning or passive interrupts.
1126 */
Googler9398cc32022-12-02 17:21:52 +08001127 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE ||
Googleraf606d22022-10-26 21:40:12 -07001128 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
1129 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
1130 else
1131 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK;
1132
1133 /* save for later use */
1134 priv->reg_ctrl_default = reg_ctrl;
1135 /* leave interrupts disabled for now */
1136 reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
1137 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
Googler9398cc32022-12-02 17:21:52 +08001138 priv->write(reg_ctrl, &regs->ctrl);
Googleraf606d22022-10-26 21:40:12 -07001139
Googler9398cc32022-12-02 17:21:52 +08001140 if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
1141 reg_ctrl2 = priv->read(&regs->ctrl2);
1142 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
1143 priv->write(reg_ctrl2, &regs->ctrl2);
1144 }
1145
1146 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1147 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) {
1148 mb = flexcan_get_mb(priv, i);
1149 priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
1150 &mb->can_ctrl);
1151 }
1152 } else {
1153 /* clear and invalidate unused mailboxes first */
1154 for (i = FLEXCAN_TX_MB_RESERVED_OFF_FIFO; i < priv->mb_count; i++) {
1155 mb = flexcan_get_mb(priv, i);
1156 priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
1157 &mb->can_ctrl);
1158 }
Googleraf606d22022-10-26 21:40:12 -07001159 }
1160
1161 /* Errata ERR005829: mark first TX mailbox as INACTIVE */
Googler9398cc32022-12-02 17:21:52 +08001162 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1163 &priv->tx_mb_reserved->can_ctrl);
Googleraf606d22022-10-26 21:40:12 -07001164
1165 /* mark TX mailbox as INACTIVE */
Googler9398cc32022-12-02 17:21:52 +08001166 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
1167 &priv->tx_mb->can_ctrl);
Googleraf606d22022-10-26 21:40:12 -07001168
1169 /* acceptance mask/acceptance code (accept everything) */
Googler9398cc32022-12-02 17:21:52 +08001170 priv->write(0x0, &regs->rxgmask);
1171 priv->write(0x0, &regs->rx14mask);
1172 priv->write(0x0, &regs->rx15mask);
Googleraf606d22022-10-26 21:40:12 -07001173
1174 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
Googler9398cc32022-12-02 17:21:52 +08001175 priv->write(0x0, &regs->rxfgmask);
1176
1177 /* clear acceptance filters */
1178 for (i = 0; i < priv->mb_count; i++)
1179 priv->write(0, &regs->rximr[i]);
Googleraf606d22022-10-26 21:40:12 -07001180
1181 /* On Vybrid, disable memory error detection interrupts
1182 * and freeze mode.
1183 * This also works around errata e5295 which generates
1184 * false positive memory errors and put the device in
1185 * freeze mode.
1186 */
1187 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
1188 /* Follow the protocol as described in "Detection
1189 * and Correction of Memory Errors" to write to
1190 * MECR register
1191 */
Googler9398cc32022-12-02 17:21:52 +08001192 reg_ctrl2 = priv->read(&regs->ctrl2);
Googleraf606d22022-10-26 21:40:12 -07001193 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
Googler9398cc32022-12-02 17:21:52 +08001194 priv->write(reg_ctrl2, &regs->ctrl2);
Googleraf606d22022-10-26 21:40:12 -07001195
Googler9398cc32022-12-02 17:21:52 +08001196 reg_mecr = priv->read(&regs->mecr);
Googleraf606d22022-10-26 21:40:12 -07001197 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
Googler9398cc32022-12-02 17:21:52 +08001198 priv->write(reg_mecr, &regs->mecr);
Googleraf606d22022-10-26 21:40:12 -07001199 reg_mecr |= FLEXCAN_MECR_ECCDIS;
1200 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
1201 FLEXCAN_MECR_FANCEI_MSK);
Googler9398cc32022-12-02 17:21:52 +08001202 priv->write(reg_mecr, &regs->mecr);
Googleraf606d22022-10-26 21:40:12 -07001203 }
1204
Googleraf606d22022-10-26 21:40:12 -07001205 /* synchronize with the can bus */
1206 err = flexcan_chip_unfreeze(priv);
1207 if (err)
Googler9398cc32022-12-02 17:21:52 +08001208 goto out_chip_disable;
Googleraf606d22022-10-26 21:40:12 -07001209
1210 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1211
1212 /* enable interrupts atomically */
1213 disable_irq(dev->irq);
Googler9398cc32022-12-02 17:21:52 +08001214 priv->write(priv->reg_ctrl_default, &regs->ctrl);
1215 priv->write(priv->reg_imask1_default, &regs->imask1);
1216 priv->write(priv->reg_imask2_default, &regs->imask2);
Googleraf606d22022-10-26 21:40:12 -07001217 enable_irq(dev->irq);
1218
1219 /* print chip status */
1220 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
Googler9398cc32022-12-02 17:21:52 +08001221 priv->read(&regs->mcr), priv->read(&regs->ctrl));
Googleraf606d22022-10-26 21:40:12 -07001222
1223 return 0;
1224
Googleraf606d22022-10-26 21:40:12 -07001225 out_chip_disable:
1226 flexcan_chip_disable(priv);
1227 return err;
1228}
1229
Googler9398cc32022-12-02 17:21:52 +08001230/* __flexcan_chip_stop
Googleraf606d22022-10-26 21:40:12 -07001231 *
Googler9398cc32022-12-02 17:21:52 +08001232 * this function is entered with clocks enabled
Googleraf606d22022-10-26 21:40:12 -07001233 */
Googler9398cc32022-12-02 17:21:52 +08001234static int __flexcan_chip_stop(struct net_device *dev, bool disable_on_error)
Googleraf606d22022-10-26 21:40:12 -07001235{
1236 struct flexcan_priv *priv = netdev_priv(dev);
1237 struct flexcan_regs __iomem *regs = priv->regs;
Googler9398cc32022-12-02 17:21:52 +08001238 int err;
Googleraf606d22022-10-26 21:40:12 -07001239
1240 /* freeze + disable module */
Googler9398cc32022-12-02 17:21:52 +08001241 err = flexcan_chip_freeze(priv);
1242 if (err && !disable_on_error)
1243 return err;
1244 err = flexcan_chip_disable(priv);
1245 if (err && !disable_on_error)
1246 goto out_chip_unfreeze;
Googleraf606d22022-10-26 21:40:12 -07001247
1248 /* Disable all interrupts */
Googler9398cc32022-12-02 17:21:52 +08001249 priv->write(0, &regs->imask2);
1250 priv->write(0, &regs->imask1);
1251 priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
1252 &regs->ctrl);
Googleraf606d22022-10-26 21:40:12 -07001253
Googleraf606d22022-10-26 21:40:12 -07001254 priv->can.state = CAN_STATE_STOPPED;
Googler9398cc32022-12-02 17:21:52 +08001255
1256 return 0;
1257
1258 out_chip_unfreeze:
1259 flexcan_chip_unfreeze(priv);
1260
1261 return err;
1262}
1263
1264static inline int flexcan_chip_stop_disable_on_error(struct net_device *dev)
1265{
1266 return __flexcan_chip_stop(dev, true);
1267}
1268
1269static inline int flexcan_chip_stop(struct net_device *dev)
1270{
1271 return __flexcan_chip_stop(dev, false);
Googleraf606d22022-10-26 21:40:12 -07001272}
1273
1274static int flexcan_open(struct net_device *dev)
1275{
1276 struct flexcan_priv *priv = netdev_priv(dev);
1277 int err;
1278
Googler9398cc32022-12-02 17:21:52 +08001279 err = pm_runtime_get_sync(priv->dev);
1280 if (err < 0) {
1281 pm_runtime_put_noidle(priv->dev);
Googleraf606d22022-10-26 21:40:12 -07001282 return err;
Googler9398cc32022-12-02 17:21:52 +08001283 }
Googleraf606d22022-10-26 21:40:12 -07001284
1285 err = open_candev(dev);
1286 if (err)
Googler9398cc32022-12-02 17:21:52 +08001287 goto out_runtime_put;
1288
1289 err = flexcan_transceiver_enable(priv);
1290 if (err)
1291 goto out_close;
Googleraf606d22022-10-26 21:40:12 -07001292
1293 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
1294 if (err)
Googler9398cc32022-12-02 17:21:52 +08001295 goto out_transceiver_disable;
1296
1297 priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN;
1298 priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) +
1299 (sizeof(priv->regs->mb[1]) / priv->mb_size);
1300
1301 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)
1302 priv->tx_mb_reserved =
1303 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_TIMESTAMP);
1304 else
1305 priv->tx_mb_reserved =
1306 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_OFF_FIFO);
1307 priv->tx_mb_idx = priv->mb_count - 1;
1308 priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx);
1309
1310 priv->reg_imask1_default = 0;
1311 priv->reg_imask2_default = FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
1312
1313 priv->offload.mailbox_read = flexcan_mailbox_read;
1314
1315 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
1316 u64 imask;
1317
1318 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST;
1319 priv->offload.mb_last = priv->mb_count - 2;
1320
1321 imask = GENMASK_ULL(priv->offload.mb_last,
1322 priv->offload.mb_first);
1323 priv->reg_imask1_default |= imask;
1324 priv->reg_imask2_default |= imask >> 32;
1325
1326 err = can_rx_offload_add_timestamp(dev, &priv->offload);
1327 } else {
1328 priv->reg_imask1_default |= FLEXCAN_IFLAG_RX_FIFO_OVERFLOW |
1329 FLEXCAN_IFLAG_RX_FIFO_AVAILABLE;
1330 err = can_rx_offload_add_fifo(dev, &priv->offload,
1331 FLEXCAN_NAPI_WEIGHT);
1332 }
1333 if (err)
1334 goto out_free_irq;
Googleraf606d22022-10-26 21:40:12 -07001335
1336 /* start chip and queuing */
1337 err = flexcan_chip_start(dev);
1338 if (err)
Googler9398cc32022-12-02 17:21:52 +08001339 goto out_offload_del;
Googleraf606d22022-10-26 21:40:12 -07001340
1341 can_led_event(dev, CAN_LED_EVENT_OPEN);
1342
Googler9398cc32022-12-02 17:21:52 +08001343 can_rx_offload_enable(&priv->offload);
Googleraf606d22022-10-26 21:40:12 -07001344 netif_start_queue(dev);
1345
1346 return 0;
1347
Googler9398cc32022-12-02 17:21:52 +08001348 out_offload_del:
1349 can_rx_offload_del(&priv->offload);
Googleraf606d22022-10-26 21:40:12 -07001350 out_free_irq:
1351 free_irq(dev->irq, dev);
Googler9398cc32022-12-02 17:21:52 +08001352 out_transceiver_disable:
1353 flexcan_transceiver_disable(priv);
Googleraf606d22022-10-26 21:40:12 -07001354 out_close:
1355 close_candev(dev);
Googler9398cc32022-12-02 17:21:52 +08001356 out_runtime_put:
1357 pm_runtime_put(priv->dev);
Googleraf606d22022-10-26 21:40:12 -07001358
1359 return err;
1360}
1361
1362static int flexcan_close(struct net_device *dev)
1363{
1364 struct flexcan_priv *priv = netdev_priv(dev);
1365
1366 netif_stop_queue(dev);
Googler9398cc32022-12-02 17:21:52 +08001367 can_rx_offload_disable(&priv->offload);
1368 flexcan_chip_stop_disable_on_error(dev);
Googleraf606d22022-10-26 21:40:12 -07001369
Googler9398cc32022-12-02 17:21:52 +08001370 can_rx_offload_del(&priv->offload);
Googleraf606d22022-10-26 21:40:12 -07001371 free_irq(dev->irq, dev);
Googler9398cc32022-12-02 17:21:52 +08001372 flexcan_transceiver_disable(priv);
Googleraf606d22022-10-26 21:40:12 -07001373
1374 close_candev(dev);
Googler9398cc32022-12-02 17:21:52 +08001375 pm_runtime_put(priv->dev);
Googleraf606d22022-10-26 21:40:12 -07001376
1377 can_led_event(dev, CAN_LED_EVENT_STOP);
1378
1379 return 0;
1380}
1381
1382static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
1383{
1384 int err;
1385
1386 switch (mode) {
1387 case CAN_MODE_START:
1388 err = flexcan_chip_start(dev);
1389 if (err)
1390 return err;
1391
1392 netif_wake_queue(dev);
1393 break;
1394
1395 default:
1396 return -EOPNOTSUPP;
1397 }
1398
1399 return 0;
1400}
1401
1402static const struct net_device_ops flexcan_netdev_ops = {
1403 .ndo_open = flexcan_open,
1404 .ndo_stop = flexcan_close,
1405 .ndo_start_xmit = flexcan_start_xmit,
1406 .ndo_change_mtu = can_change_mtu,
1407};
1408
1409static int register_flexcandev(struct net_device *dev)
1410{
1411 struct flexcan_priv *priv = netdev_priv(dev);
1412 struct flexcan_regs __iomem *regs = priv->regs;
1413 u32 reg, err;
1414
Googler9398cc32022-12-02 17:21:52 +08001415 err = flexcan_clks_enable(priv);
Googleraf606d22022-10-26 21:40:12 -07001416 if (err)
1417 return err;
1418
Googleraf606d22022-10-26 21:40:12 -07001419 /* select "bus clock", chip must be disabled */
1420 err = flexcan_chip_disable(priv);
1421 if (err)
Googler9398cc32022-12-02 17:21:52 +08001422 goto out_clks_disable;
1423
1424 reg = priv->read(&regs->ctrl);
1425 if (priv->clk_src)
1426 reg |= FLEXCAN_CTRL_CLK_SRC;
1427 else
1428 reg &= ~FLEXCAN_CTRL_CLK_SRC;
1429 priv->write(reg, &regs->ctrl);
Googleraf606d22022-10-26 21:40:12 -07001430
1431 err = flexcan_chip_enable(priv);
1432 if (err)
1433 goto out_chip_disable;
1434
Googlerb48fa912023-03-17 12:40:29 +05301435 /* set freeze, halt and activate FIFO, restrict register access */
Googler9398cc32022-12-02 17:21:52 +08001436 reg = priv->read(&regs->mcr);
Googlerb48fa912023-03-17 12:40:29 +05301437 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
1438 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
Googler9398cc32022-12-02 17:21:52 +08001439 priv->write(reg, &regs->mcr);
Googleraf606d22022-10-26 21:40:12 -07001440
1441 /* Currently we only support newer versions of this core
Googler9398cc32022-12-02 17:21:52 +08001442 * featuring a RX hardware FIFO (although this driver doesn't
1443 * make use of it on some cores). Older cores, found on some
1444 * Coldfire derivates are not tested.
Googleraf606d22022-10-26 21:40:12 -07001445 */
Googler9398cc32022-12-02 17:21:52 +08001446 reg = priv->read(&regs->mcr);
Googleraf606d22022-10-26 21:40:12 -07001447 if (!(reg & FLEXCAN_MCR_FEN)) {
1448 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
1449 err = -ENODEV;
1450 goto out_chip_disable;
1451 }
1452
1453 err = register_candev(dev);
Googler9398cc32022-12-02 17:21:52 +08001454 if (err)
1455 goto out_chip_disable;
Googleraf606d22022-10-26 21:40:12 -07001456
Googler9398cc32022-12-02 17:21:52 +08001457 /* Disable core and let pm_runtime_put() disable the clocks.
1458 * If CONFIG_PM is not enabled, the clocks will stay powered.
1459 */
1460 flexcan_chip_disable(priv);
1461 pm_runtime_put(priv->dev);
1462
1463 return 0;
1464
Googleraf606d22022-10-26 21:40:12 -07001465 out_chip_disable:
1466 flexcan_chip_disable(priv);
Googler9398cc32022-12-02 17:21:52 +08001467 out_clks_disable:
1468 flexcan_clks_disable(priv);
Googleraf606d22022-10-26 21:40:12 -07001469 return err;
1470}
1471
1472static void unregister_flexcandev(struct net_device *dev)
1473{
1474 unregister_candev(dev);
1475}
1476
Googler9398cc32022-12-02 17:21:52 +08001477static int flexcan_setup_stop_mode(struct platform_device *pdev)
1478{
1479 struct net_device *dev = platform_get_drvdata(pdev);
1480 struct device_node *np = pdev->dev.of_node;
1481 struct device_node *gpr_np;
1482 struct flexcan_priv *priv;
1483 phandle phandle;
1484 u32 out_val[5];
1485 int ret;
1486
1487 if (!np)
1488 return -EINVAL;
1489
1490 /* stop mode property format is:
1491 * <&gpr req_gpr req_bit ack_gpr ack_bit>.
1492 */
1493 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
1494 ARRAY_SIZE(out_val));
1495 if (ret) {
1496 dev_dbg(&pdev->dev, "no stop-mode property\n");
1497 return ret;
1498 }
1499 phandle = *out_val;
1500
1501 gpr_np = of_find_node_by_phandle(phandle);
1502 if (!gpr_np) {
1503 dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
1504 return -ENODEV;
1505 }
1506
1507 priv = netdev_priv(dev);
1508 priv->stm.gpr = syscon_node_to_regmap(gpr_np);
1509 if (IS_ERR(priv->stm.gpr)) {
1510 dev_dbg(&pdev->dev, "could not find gpr regmap\n");
1511 ret = PTR_ERR(priv->stm.gpr);
1512 goto out_put_node;
1513 }
1514
1515 priv->stm.req_gpr = out_val[1];
1516 priv->stm.req_bit = out_val[2];
1517 priv->stm.ack_gpr = out_val[3];
1518 priv->stm.ack_bit = out_val[4];
1519
1520 dev_dbg(&pdev->dev,
1521 "gpr %s req_gpr=0x02%x req_bit=%u ack_gpr=0x02%x ack_bit=%u\n",
1522 gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit,
1523 priv->stm.ack_gpr, priv->stm.ack_bit);
1524
1525 device_set_wakeup_capable(&pdev->dev, true);
1526
1527 if (of_property_read_bool(np, "wakeup-source"))
1528 device_set_wakeup_enable(&pdev->dev, true);
1529
1530 return 0;
1531
1532out_put_node:
1533 of_node_put(gpr_np);
1534 return ret;
1535}
1536
Googleraf606d22022-10-26 21:40:12 -07001537static const struct of_device_id flexcan_of_match[] = {
1538 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1539 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
Googler9398cc32022-12-02 17:21:52 +08001540 { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
1541 { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
1542 { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
Googleraf606d22022-10-26 21:40:12 -07001543 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1544 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
Googler9398cc32022-12-02 17:21:52 +08001545 { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
Googleraf606d22022-10-26 21:40:12 -07001546 { /* sentinel */ },
1547};
1548MODULE_DEVICE_TABLE(of, flexcan_of_match);
1549
1550static const struct platform_device_id flexcan_id_table[] = {
1551 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1552 { /* sentinel */ },
1553};
1554MODULE_DEVICE_TABLE(platform, flexcan_id_table);
1555
1556static int flexcan_probe(struct platform_device *pdev)
1557{
1558 const struct of_device_id *of_id;
1559 const struct flexcan_devtype_data *devtype_data;
1560 struct net_device *dev;
1561 struct flexcan_priv *priv;
1562 struct regulator *reg_xceiver;
1563 struct resource *mem;
1564 struct clk *clk_ipg = NULL, *clk_per = NULL;
1565 struct flexcan_regs __iomem *regs;
1566 int err, irq;
Googler9398cc32022-12-02 17:21:52 +08001567 u8 clk_src = 1;
Googleraf606d22022-10-26 21:40:12 -07001568 u32 clock_freq = 0;
1569
1570 reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
1571 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
1572 return -EPROBE_DEFER;
1573 else if (IS_ERR(reg_xceiver))
1574 reg_xceiver = NULL;
1575
Googler9398cc32022-12-02 17:21:52 +08001576 if (pdev->dev.of_node) {
Googleraf606d22022-10-26 21:40:12 -07001577 of_property_read_u32(pdev->dev.of_node,
1578 "clock-frequency", &clock_freq);
Googler9398cc32022-12-02 17:21:52 +08001579 of_property_read_u8(pdev->dev.of_node,
1580 "fsl,clk-source", &clk_src);
1581 }
Googleraf606d22022-10-26 21:40:12 -07001582
1583 if (!clock_freq) {
1584 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1585 if (IS_ERR(clk_ipg)) {
1586 dev_err(&pdev->dev, "no ipg clock defined\n");
1587 return PTR_ERR(clk_ipg);
1588 }
1589
1590 clk_per = devm_clk_get(&pdev->dev, "per");
1591 if (IS_ERR(clk_per)) {
1592 dev_err(&pdev->dev, "no per clock defined\n");
1593 return PTR_ERR(clk_per);
1594 }
1595 clock_freq = clk_get_rate(clk_per);
1596 }
1597
1598 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1599 irq = platform_get_irq(pdev, 0);
1600 if (irq <= 0)
1601 return -ENODEV;
1602
1603 regs = devm_ioremap_resource(&pdev->dev, mem);
1604 if (IS_ERR(regs))
1605 return PTR_ERR(regs);
1606
1607 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1608 if (of_id) {
1609 devtype_data = of_id->data;
1610 } else if (platform_get_device_id(pdev)->driver_data) {
1611 devtype_data = (struct flexcan_devtype_data *)
1612 platform_get_device_id(pdev)->driver_data;
1613 } else {
1614 return -ENODEV;
1615 }
1616
1617 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1618 if (!dev)
1619 return -ENOMEM;
1620
Googler9398cc32022-12-02 17:21:52 +08001621 platform_set_drvdata(pdev, dev);
1622 SET_NETDEV_DEV(dev, &pdev->dev);
1623
Googleraf606d22022-10-26 21:40:12 -07001624 dev->netdev_ops = &flexcan_netdev_ops;
1625 dev->irq = irq;
1626 dev->flags |= IFF_ECHO;
1627
1628 priv = netdev_priv(dev);
Googler9398cc32022-12-02 17:21:52 +08001629
1630 if (of_property_read_bool(pdev->dev.of_node, "big-endian") ||
1631 devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) {
1632 priv->read = flexcan_read_be;
1633 priv->write = flexcan_write_be;
1634 } else {
1635 priv->read = flexcan_read_le;
1636 priv->write = flexcan_write_le;
1637 }
1638
1639 priv->dev = &pdev->dev;
Googleraf606d22022-10-26 21:40:12 -07001640 priv->can.clock.freq = clock_freq;
1641 priv->can.bittiming_const = &flexcan_bittiming_const;
1642 priv->can.do_set_mode = flexcan_set_mode;
1643 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1644 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1645 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1646 CAN_CTRLMODE_BERR_REPORTING;
1647 priv->regs = regs;
1648 priv->clk_ipg = clk_ipg;
1649 priv->clk_per = clk_per;
Googler9398cc32022-12-02 17:21:52 +08001650 priv->clk_src = clk_src;
Googleraf606d22022-10-26 21:40:12 -07001651 priv->devtype_data = devtype_data;
1652 priv->reg_xceiver = reg_xceiver;
1653
Googler9398cc32022-12-02 17:21:52 +08001654 pm_runtime_get_noresume(&pdev->dev);
1655 pm_runtime_set_active(&pdev->dev);
1656 pm_runtime_enable(&pdev->dev);
Googleraf606d22022-10-26 21:40:12 -07001657
1658 err = register_flexcandev(dev);
1659 if (err) {
1660 dev_err(&pdev->dev, "registering netdev failed\n");
1661 goto failed_register;
1662 }
1663
1664 devm_can_led_init(dev);
1665
Googler9398cc32022-12-02 17:21:52 +08001666 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE) {
1667 err = flexcan_setup_stop_mode(pdev);
1668 if (err)
1669 dev_dbg(&pdev->dev, "failed to setup stop-mode\n");
1670 }
Googleraf606d22022-10-26 21:40:12 -07001671
1672 return 0;
1673
1674 failed_register:
1675 free_candev(dev);
1676 return err;
1677}
1678
1679static int flexcan_remove(struct platform_device *pdev)
1680{
1681 struct net_device *dev = platform_get_drvdata(pdev);
Googleraf606d22022-10-26 21:40:12 -07001682
Googler9398cc32022-12-02 17:21:52 +08001683 device_set_wakeup_enable(&pdev->dev, false);
1684 device_set_wakeup_capable(&pdev->dev, false);
Googleraf606d22022-10-26 21:40:12 -07001685 unregister_flexcandev(dev);
Googler9398cc32022-12-02 17:21:52 +08001686 pm_runtime_disable(&pdev->dev);
Googleraf606d22022-10-26 21:40:12 -07001687 free_candev(dev);
1688
1689 return 0;
1690}
1691
1692static int __maybe_unused flexcan_suspend(struct device *device)
1693{
1694 struct net_device *dev = dev_get_drvdata(device);
1695 struct flexcan_priv *priv = netdev_priv(dev);
Googler9398cc32022-12-02 17:21:52 +08001696 int err = 0;
Googleraf606d22022-10-26 21:40:12 -07001697
1698 if (netif_running(dev)) {
Googler9398cc32022-12-02 17:21:52 +08001699 /* if wakeup is enabled, enter stop mode
1700 * else enter disabled mode.
1701 */
1702 if (device_may_wakeup(device)) {
1703 enable_irq_wake(dev->irq);
1704 err = flexcan_enter_stop_mode(priv);
1705 if (err)
1706 return err;
1707 } else {
1708 err = flexcan_chip_disable(priv);
1709 if (err)
1710 return err;
1711 }
Googleraf606d22022-10-26 21:40:12 -07001712 netif_stop_queue(dev);
1713 netif_device_detach(dev);
1714 }
1715 priv->can.state = CAN_STATE_SLEEPING;
1716
Googler9398cc32022-12-02 17:21:52 +08001717 return err;
Googleraf606d22022-10-26 21:40:12 -07001718}
1719
1720static int __maybe_unused flexcan_resume(struct device *device)
1721{
1722 struct net_device *dev = dev_get_drvdata(device);
1723 struct flexcan_priv *priv = netdev_priv(dev);
Googler9398cc32022-12-02 17:21:52 +08001724 int err = 0;
Googleraf606d22022-10-26 21:40:12 -07001725
1726 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1727 if (netif_running(dev)) {
1728 netif_device_attach(dev);
1729 netif_start_queue(dev);
Googler9398cc32022-12-02 17:21:52 +08001730 if (device_may_wakeup(device)) {
1731 disable_irq_wake(dev->irq);
1732 err = flexcan_exit_stop_mode(priv);
1733 if (err)
1734 return err;
1735 } else {
1736 err = flexcan_chip_enable(priv);
1737 }
Googler38bda472022-08-19 10:07:08 -07001738 }
Googler9398cc32022-12-02 17:21:52 +08001739
1740 return err;
1741}
1742
1743static int __maybe_unused flexcan_runtime_suspend(struct device *device)
1744{
1745 struct net_device *dev = dev_get_drvdata(device);
1746 struct flexcan_priv *priv = netdev_priv(dev);
1747
1748 flexcan_clks_disable(priv);
1749
Googler38bda472022-08-19 10:07:08 -07001750 return 0;
1751}
1752
Googler9398cc32022-12-02 17:21:52 +08001753static int __maybe_unused flexcan_runtime_resume(struct device *device)
1754{
1755 struct net_device *dev = dev_get_drvdata(device);
1756 struct flexcan_priv *priv = netdev_priv(dev);
1757
1758 return flexcan_clks_enable(priv);
1759}
1760
1761static int __maybe_unused flexcan_noirq_suspend(struct device *device)
1762{
1763 struct net_device *dev = dev_get_drvdata(device);
1764 struct flexcan_priv *priv = netdev_priv(dev);
1765
1766 if (netif_running(dev)) {
1767 int err;
1768
1769 if (device_may_wakeup(device))
1770 flexcan_enable_wakeup_irq(priv, true);
1771
1772 err = pm_runtime_force_suspend(device);
1773 if (err)
1774 return err;
1775 }
1776
1777 return 0;
1778}
1779
1780static int __maybe_unused flexcan_noirq_resume(struct device *device)
1781{
1782 struct net_device *dev = dev_get_drvdata(device);
1783 struct flexcan_priv *priv = netdev_priv(dev);
1784
1785 if (netif_running(dev)) {
1786 int err;
1787
1788 err = pm_runtime_force_resume(device);
1789 if (err)
1790 return err;
1791
1792 if (device_may_wakeup(device))
1793 flexcan_enable_wakeup_irq(priv, false);
1794 }
1795
1796 return 0;
1797}
1798
1799static const struct dev_pm_ops flexcan_pm_ops = {
1800 SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume)
1801 SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL)
1802 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume)
1803};
Googleraf606d22022-10-26 21:40:12 -07001804
1805static struct platform_driver flexcan_driver = {
1806 .driver = {
1807 .name = DRV_NAME,
1808 .pm = &flexcan_pm_ops,
1809 .of_match_table = flexcan_of_match,
1810 },
1811 .probe = flexcan_probe,
1812 .remove = flexcan_remove,
1813 .id_table = flexcan_id_table,
1814};
1815
1816module_platform_driver(flexcan_driver);
1817
1818MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1819 "Marc Kleine-Budde <kernel@pengutronix.de>");
1820MODULE_LICENSE("GPL v2");
1821MODULE_DESCRIPTION("CAN port driver for flexcan based chip");