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Googler9398cc32022-12-02 17:21:52 +08001// SPDX-License-Identifier: GPL-2.0
2// CAN bus driver for Bosch M_CAN controller
3// Copyright (C) 2014 Freescale Semiconductor, Inc.
4// Dong Aisheng <b29396@freescale.com>
5// Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/
6
7/* Bosch M_CAN user manual can be obtained from:
Googleraf606d22022-10-26 21:40:12 -07008 * http://www.bosch-semiconductors.de/media/pdf_1/ipmodules_1/m_can/
9 * mcan_users_manual_v302.pdf
10 */
11
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/netdevice.h>
17#include <linux/of.h>
18#include <linux/of_device.h>
19#include <linux/platform_device.h>
Googler9398cc32022-12-02 17:21:52 +080020#include <linux/pm_runtime.h>
21#include <linux/iopoll.h>
Googler012a81c2022-09-15 14:55:24 +080022#include <linux/can/dev.h>
Googler9398cc32022-12-02 17:21:52 +080023#include <linux/pinctrl/consumer.h>
Googler012a81c2022-09-15 14:55:24 +080024
Googler9398cc32022-12-02 17:21:52 +080025#include "m_can.h"
Googleraf606d22022-10-26 21:40:12 -070026
27/* registers definition */
28enum m_can_reg {
29 M_CAN_CREL = 0x0,
30 M_CAN_ENDN = 0x4,
31 M_CAN_CUST = 0x8,
Googler9398cc32022-12-02 17:21:52 +080032 M_CAN_DBTP = 0xc,
Googleraf606d22022-10-26 21:40:12 -070033 M_CAN_TEST = 0x10,
34 M_CAN_RWD = 0x14,
35 M_CAN_CCCR = 0x18,
Googler9398cc32022-12-02 17:21:52 +080036 M_CAN_NBTP = 0x1c,
Googleraf606d22022-10-26 21:40:12 -070037 M_CAN_TSCC = 0x20,
38 M_CAN_TSCV = 0x24,
39 M_CAN_TOCC = 0x28,
40 M_CAN_TOCV = 0x2c,
41 M_CAN_ECR = 0x40,
42 M_CAN_PSR = 0x44,
Googler9398cc32022-12-02 17:21:52 +080043/* TDCR Register only available for version >=3.1.x */
44 M_CAN_TDCR = 0x48,
Googleraf606d22022-10-26 21:40:12 -070045 M_CAN_IR = 0x50,
46 M_CAN_IE = 0x54,
47 M_CAN_ILS = 0x58,
48 M_CAN_ILE = 0x5c,
49 M_CAN_GFC = 0x80,
50 M_CAN_SIDFC = 0x84,
51 M_CAN_XIDFC = 0x88,
52 M_CAN_XIDAM = 0x90,
53 M_CAN_HPMS = 0x94,
54 M_CAN_NDAT1 = 0x98,
55 M_CAN_NDAT2 = 0x9c,
56 M_CAN_RXF0C = 0xa0,
57 M_CAN_RXF0S = 0xa4,
58 M_CAN_RXF0A = 0xa8,
59 M_CAN_RXBC = 0xac,
60 M_CAN_RXF1C = 0xb0,
61 M_CAN_RXF1S = 0xb4,
62 M_CAN_RXF1A = 0xb8,
63 M_CAN_RXESC = 0xbc,
64 M_CAN_TXBC = 0xc0,
65 M_CAN_TXFQS = 0xc4,
66 M_CAN_TXESC = 0xc8,
67 M_CAN_TXBRP = 0xcc,
68 M_CAN_TXBAR = 0xd0,
69 M_CAN_TXBCR = 0xd4,
70 M_CAN_TXBTO = 0xd8,
71 M_CAN_TXBCF = 0xdc,
72 M_CAN_TXBTIE = 0xe0,
73 M_CAN_TXBCIE = 0xe4,
74 M_CAN_TXEFC = 0xf0,
75 M_CAN_TXEFS = 0xf4,
76 M_CAN_TXEFA = 0xf8,
77};
78
Googler9398cc32022-12-02 17:21:52 +080079/* napi related */
80#define M_CAN_NAPI_WEIGHT 64
Googleraf606d22022-10-26 21:40:12 -070081
Googler9398cc32022-12-02 17:21:52 +080082/* message ram configuration data length */
83#define MRAM_CFG_LEN 8
Googleraf606d22022-10-26 21:40:12 -070084
Googler9398cc32022-12-02 17:21:52 +080085/* Core Release Register (CREL) */
86#define CREL_REL_SHIFT 28
87#define CREL_REL_MASK (0xF << CREL_REL_SHIFT)
88#define CREL_STEP_SHIFT 24
89#define CREL_STEP_MASK (0xF << CREL_STEP_SHIFT)
90#define CREL_SUBSTEP_SHIFT 20
91#define CREL_SUBSTEP_MASK (0xF << CREL_SUBSTEP_SHIFT)
92
93/* Data Bit Timing & Prescaler Register (DBTP) */
94#define DBTP_TDC BIT(23)
95#define DBTP_DBRP_SHIFT 16
96#define DBTP_DBRP_MASK (0x1f << DBTP_DBRP_SHIFT)
97#define DBTP_DTSEG1_SHIFT 8
98#define DBTP_DTSEG1_MASK (0x1f << DBTP_DTSEG1_SHIFT)
99#define DBTP_DTSEG2_SHIFT 4
100#define DBTP_DTSEG2_MASK (0xf << DBTP_DTSEG2_SHIFT)
101#define DBTP_DSJW_SHIFT 0
102#define DBTP_DSJW_MASK (0xf << DBTP_DSJW_SHIFT)
103
104/* Transmitter Delay Compensation Register (TDCR) */
105#define TDCR_TDCO_SHIFT 8
106#define TDCR_TDCO_MASK (0x7F << TDCR_TDCO_SHIFT)
107#define TDCR_TDCF_SHIFT 0
108#define TDCR_TDCF_MASK (0x7F << TDCR_TDCF_SHIFT)
Googleraf606d22022-10-26 21:40:12 -0700109
110/* Test Register (TEST) */
Googler9398cc32022-12-02 17:21:52 +0800111#define TEST_LBCK BIT(4)
Googleraf606d22022-10-26 21:40:12 -0700112
113/* CC Control Register(CCCR) */
114#define CCCR_CMR_MASK 0x3
115#define CCCR_CMR_SHIFT 10
116#define CCCR_CMR_CANFD 0x1
117#define CCCR_CMR_CANFD_BRS 0x2
118#define CCCR_CMR_CAN 0x3
119#define CCCR_CME_MASK 0x3
120#define CCCR_CME_SHIFT 8
121#define CCCR_CME_CAN 0
122#define CCCR_CME_CANFD 0x1
123#define CCCR_CME_CANFD_BRS 0x2
Googler9398cc32022-12-02 17:21:52 +0800124#define CCCR_TXP BIT(14)
Googleraf606d22022-10-26 21:40:12 -0700125#define CCCR_TEST BIT(7)
126#define CCCR_MON BIT(5)
Googler9398cc32022-12-02 17:21:52 +0800127#define CCCR_CSR BIT(4)
128#define CCCR_CSA BIT(3)
129#define CCCR_ASM BIT(2)
Googleraf606d22022-10-26 21:40:12 -0700130#define CCCR_CCE BIT(1)
131#define CCCR_INIT BIT(0)
132#define CCCR_CANFD 0x10
Googler9398cc32022-12-02 17:21:52 +0800133/* for version >=3.1.x */
134#define CCCR_EFBI BIT(13)
135#define CCCR_PXHD BIT(12)
136#define CCCR_BRSE BIT(9)
137#define CCCR_FDOE BIT(8)
138/* only for version >=3.2.x */
139#define CCCR_NISO BIT(15)
Googleraf606d22022-10-26 21:40:12 -0700140
Googler9398cc32022-12-02 17:21:52 +0800141/* Nominal Bit Timing & Prescaler Register (NBTP) */
142#define NBTP_NSJW_SHIFT 25
143#define NBTP_NSJW_MASK (0x7f << NBTP_NSJW_SHIFT)
144#define NBTP_NBRP_SHIFT 16
145#define NBTP_NBRP_MASK (0x1ff << NBTP_NBRP_SHIFT)
146#define NBTP_NTSEG1_SHIFT 8
147#define NBTP_NTSEG1_MASK (0xff << NBTP_NTSEG1_SHIFT)
148#define NBTP_NTSEG2_SHIFT 0
149#define NBTP_NTSEG2_MASK (0x7f << NBTP_NTSEG2_SHIFT)
Googleraf606d22022-10-26 21:40:12 -0700150
151/* Error Counter Register(ECR) */
152#define ECR_RP BIT(15)
153#define ECR_REC_SHIFT 8
154#define ECR_REC_MASK (0x7f << ECR_REC_SHIFT)
155#define ECR_TEC_SHIFT 0
156#define ECR_TEC_MASK 0xff
157
158/* Protocol Status Register(PSR) */
159#define PSR_BO BIT(7)
160#define PSR_EW BIT(6)
161#define PSR_EP BIT(5)
162#define PSR_LEC_MASK 0x7
163
164/* Interrupt Register(IR) */
165#define IR_ALL_INT 0xffffffff
Googler9398cc32022-12-02 17:21:52 +0800166
167/* Renamed bits for versions > 3.1.x */
168#define IR_ARA BIT(29)
169#define IR_PED BIT(28)
170#define IR_PEA BIT(27)
171
172/* Bits for version 3.0.x */
Googleraf606d22022-10-26 21:40:12 -0700173#define IR_STE BIT(31)
174#define IR_FOE BIT(30)
175#define IR_ACKE BIT(29)
176#define IR_BE BIT(28)
177#define IR_CRCE BIT(27)
178#define IR_WDI BIT(26)
179#define IR_BO BIT(25)
180#define IR_EW BIT(24)
181#define IR_EP BIT(23)
182#define IR_ELO BIT(22)
183#define IR_BEU BIT(21)
184#define IR_BEC BIT(20)
185#define IR_DRX BIT(19)
186#define IR_TOO BIT(18)
187#define IR_MRAF BIT(17)
188#define IR_TSW BIT(16)
189#define IR_TEFL BIT(15)
190#define IR_TEFF BIT(14)
191#define IR_TEFW BIT(13)
192#define IR_TEFN BIT(12)
193#define IR_TFE BIT(11)
194#define IR_TCF BIT(10)
195#define IR_TC BIT(9)
196#define IR_HPM BIT(8)
197#define IR_RF1L BIT(7)
198#define IR_RF1F BIT(6)
199#define IR_RF1W BIT(5)
200#define IR_RF1N BIT(4)
201#define IR_RF0L BIT(3)
202#define IR_RF0F BIT(2)
203#define IR_RF0W BIT(1)
204#define IR_RF0N BIT(0)
205#define IR_ERR_STATE (IR_BO | IR_EW | IR_EP)
Googler9398cc32022-12-02 17:21:52 +0800206
207/* Interrupts for version 3.0.x */
208#define IR_ERR_LEC_30X (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE)
Googlerb48fa912023-03-17 12:40:29 +0530209#define IR_ERR_BUS_30X (IR_ERR_LEC_30X | IR_WDI | IR_ELO | IR_BEU | \
210 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \
211 IR_RF1L | IR_RF0L)
Googler9398cc32022-12-02 17:21:52 +0800212#define IR_ERR_ALL_30X (IR_ERR_STATE | IR_ERR_BUS_30X)
213/* Interrupts for version >= 3.1.x */
214#define IR_ERR_LEC_31X (IR_PED | IR_PEA)
Googlerb48fa912023-03-17 12:40:29 +0530215#define IR_ERR_BUS_31X (IR_ERR_LEC_31X | IR_WDI | IR_ELO | IR_BEU | \
216 IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \
217 IR_RF1L | IR_RF0L)
Googler9398cc32022-12-02 17:21:52 +0800218#define IR_ERR_ALL_31X (IR_ERR_STATE | IR_ERR_BUS_31X)
Googleraf606d22022-10-26 21:40:12 -0700219
220/* Interrupt Line Select (ILS) */
221#define ILS_ALL_INT0 0x0
222#define ILS_ALL_INT1 0xFFFFFFFF
223
224/* Interrupt Line Enable (ILE) */
Googler9726be62022-12-14 05:53:31 +0000225#define ILE_EINT1 BIT(1)
Googler9398cc32022-12-02 17:21:52 +0800226#define ILE_EINT0 BIT(0)
Googleraf606d22022-10-26 21:40:12 -0700227
228/* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */
Googler9398cc32022-12-02 17:21:52 +0800229#define RXFC_FWM_SHIFT 24
230#define RXFC_FWM_MASK (0x7f << RXFC_FWM_SHIFT)
231#define RXFC_FS_SHIFT 16
232#define RXFC_FS_MASK (0x7f << RXFC_FS_SHIFT)
Googleraf606d22022-10-26 21:40:12 -0700233
234/* Rx FIFO 0/1 Status (RXF0S/RXF1S) */
235#define RXFS_RFL BIT(25)
236#define RXFS_FF BIT(24)
Googler9398cc32022-12-02 17:21:52 +0800237#define RXFS_FPI_SHIFT 16
Googleraf606d22022-10-26 21:40:12 -0700238#define RXFS_FPI_MASK 0x3f0000
Googler9398cc32022-12-02 17:21:52 +0800239#define RXFS_FGI_SHIFT 8
Googleraf606d22022-10-26 21:40:12 -0700240#define RXFS_FGI_MASK 0x3f00
241#define RXFS_FFL_MASK 0x7f
242
243/* Rx Buffer / FIFO Element Size Configuration (RXESC) */
244#define M_CAN_RXESC_8BYTES 0x0
245#define M_CAN_RXESC_64BYTES 0x777
246
247/* Tx Buffer Configuration(TXBC) */
Googler9398cc32022-12-02 17:21:52 +0800248#define TXBC_NDTB_SHIFT 16
249#define TXBC_NDTB_MASK (0x3f << TXBC_NDTB_SHIFT)
250#define TXBC_TFQS_SHIFT 24
251#define TXBC_TFQS_MASK (0x3f << TXBC_TFQS_SHIFT)
252
253/* Tx FIFO/Queue Status (TXFQS) */
254#define TXFQS_TFQF BIT(21)
255#define TXFQS_TFQPI_SHIFT 16
256#define TXFQS_TFQPI_MASK (0x1f << TXFQS_TFQPI_SHIFT)
257#define TXFQS_TFGI_SHIFT 8
258#define TXFQS_TFGI_MASK (0x1f << TXFQS_TFGI_SHIFT)
259#define TXFQS_TFFL_SHIFT 0
260#define TXFQS_TFFL_MASK (0x3f << TXFQS_TFFL_SHIFT)
Googleraf606d22022-10-26 21:40:12 -0700261
262/* Tx Buffer Element Size Configuration(TXESC) */
263#define TXESC_TBDS_8BYTES 0x0
264#define TXESC_TBDS_64BYTES 0x7
265
Googler9398cc32022-12-02 17:21:52 +0800266/* Tx Event FIFO Configuration (TXEFC) */
267#define TXEFC_EFS_SHIFT 16
268#define TXEFC_EFS_MASK (0x3f << TXEFC_EFS_SHIFT)
269
270/* Tx Event FIFO Status (TXEFS) */
271#define TXEFS_TEFL BIT(25)
272#define TXEFS_EFF BIT(24)
273#define TXEFS_EFGI_SHIFT 8
274#define TXEFS_EFGI_MASK (0x1f << TXEFS_EFGI_SHIFT)
275#define TXEFS_EFFL_SHIFT 0
276#define TXEFS_EFFL_MASK (0x3f << TXEFS_EFFL_SHIFT)
277
278/* Tx Event FIFO Acknowledge (TXEFA) */
279#define TXEFA_EFAI_SHIFT 0
280#define TXEFA_EFAI_MASK (0x1f << TXEFA_EFAI_SHIFT)
Googleraf606d22022-10-26 21:40:12 -0700281
282/* Message RAM Configuration (in bytes) */
283#define SIDF_ELEMENT_SIZE 4
284#define XIDF_ELEMENT_SIZE 8
285#define RXF0_ELEMENT_SIZE 72
286#define RXF1_ELEMENT_SIZE 72
Googler9398cc32022-12-02 17:21:52 +0800287#define RXB_ELEMENT_SIZE 72
Googleraf606d22022-10-26 21:40:12 -0700288#define TXE_ELEMENT_SIZE 8
289#define TXB_ELEMENT_SIZE 72
290
291/* Message RAM Elements */
292#define M_CAN_FIFO_ID 0x0
293#define M_CAN_FIFO_DLC 0x4
294#define M_CAN_FIFO_DATA(n) (0x8 + ((n) << 2))
295
296/* Rx Buffer Element */
297/* R0 */
298#define RX_BUF_ESI BIT(31)
299#define RX_BUF_XTD BIT(30)
300#define RX_BUF_RTR BIT(29)
301/* R1 */
302#define RX_BUF_ANMF BIT(31)
Googler9398cc32022-12-02 17:21:52 +0800303#define RX_BUF_FDF BIT(21)
Googleraf606d22022-10-26 21:40:12 -0700304#define RX_BUF_BRS BIT(20)
305
306/* Tx Buffer Element */
Googler9398cc32022-12-02 17:21:52 +0800307/* T0 */
308#define TX_BUF_ESI BIT(31)
Googleraf606d22022-10-26 21:40:12 -0700309#define TX_BUF_XTD BIT(30)
310#define TX_BUF_RTR BIT(29)
Googler9398cc32022-12-02 17:21:52 +0800311/* T1 */
312#define TX_BUF_EFC BIT(23)
313#define TX_BUF_FDF BIT(21)
314#define TX_BUF_BRS BIT(20)
315#define TX_BUF_MM_SHIFT 24
316#define TX_BUF_MM_MASK (0xff << TX_BUF_MM_SHIFT)
Googleraf606d22022-10-26 21:40:12 -0700317
Googler9398cc32022-12-02 17:21:52 +0800318/* Tx event FIFO Element */
319/* E1 */
320#define TX_EVENT_MM_SHIFT TX_BUF_MM_SHIFT
321#define TX_EVENT_MM_MASK (0xff << TX_EVENT_MM_SHIFT)
Googleraf606d22022-10-26 21:40:12 -0700322
Googler9398cc32022-12-02 17:21:52 +0800323static inline u32 m_can_read(struct m_can_classdev *cdev, enum m_can_reg reg)
Googleraf606d22022-10-26 21:40:12 -0700324{
Googler9398cc32022-12-02 17:21:52 +0800325 return cdev->ops->read_reg(cdev, reg);
Googleraf606d22022-10-26 21:40:12 -0700326}
327
Googler9398cc32022-12-02 17:21:52 +0800328static inline void m_can_write(struct m_can_classdev *cdev, enum m_can_reg reg,
329 u32 val)
Googleraf606d22022-10-26 21:40:12 -0700330{
Googler9398cc32022-12-02 17:21:52 +0800331 cdev->ops->write_reg(cdev, reg, val);
Googleraf606d22022-10-26 21:40:12 -0700332}
333
Googler9398cc32022-12-02 17:21:52 +0800334static u32 m_can_fifo_read(struct m_can_classdev *cdev,
335 u32 fgi, unsigned int offset)
Googleraf606d22022-10-26 21:40:12 -0700336{
Googler9398cc32022-12-02 17:21:52 +0800337 u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE +
338 offset;
339
340 return cdev->ops->read_fifo(cdev, addr_offset);
Googleraf606d22022-10-26 21:40:12 -0700341}
342
Googler9398cc32022-12-02 17:21:52 +0800343static void m_can_fifo_write(struct m_can_classdev *cdev,
344 u32 fpi, unsigned int offset, u32 val)
Googleraf606d22022-10-26 21:40:12 -0700345{
Googler9398cc32022-12-02 17:21:52 +0800346 u32 addr_offset = cdev->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE +
347 offset;
348
349 cdev->ops->write_fifo(cdev, addr_offset, val);
Googleraf606d22022-10-26 21:40:12 -0700350}
351
Googler9398cc32022-12-02 17:21:52 +0800352static inline void m_can_fifo_write_no_off(struct m_can_classdev *cdev,
353 u32 fpi, u32 val)
Googleraf606d22022-10-26 21:40:12 -0700354{
Googler9398cc32022-12-02 17:21:52 +0800355 cdev->ops->write_fifo(cdev, fpi, val);
356}
357
358static u32 m_can_txe_fifo_read(struct m_can_classdev *cdev, u32 fgi, u32 offset)
359{
360 u32 addr_offset = cdev->mcfg[MRAM_TXE].off + fgi * TXE_ELEMENT_SIZE +
361 offset;
362
363 return cdev->ops->read_fifo(cdev, addr_offset);
364}
365
366static inline bool m_can_tx_fifo_full(struct m_can_classdev *cdev)
367{
368 return !!(m_can_read(cdev, M_CAN_TXFQS) & TXFQS_TFQF);
369}
370
371void m_can_config_endisable(struct m_can_classdev *cdev, bool enable)
372{
373 u32 cccr = m_can_read(cdev, M_CAN_CCCR);
Googleraf606d22022-10-26 21:40:12 -0700374 u32 timeout = 10;
375 u32 val = 0;
376
Googler9398cc32022-12-02 17:21:52 +0800377 /* Clear the Clock stop request if it was set */
378 if (cccr & CCCR_CSR)
379 cccr &= ~CCCR_CSR;
380
Googleraf606d22022-10-26 21:40:12 -0700381 if (enable) {
382 /* enable m_can configuration */
Googler9398cc32022-12-02 17:21:52 +0800383 m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT);
Googleraf606d22022-10-26 21:40:12 -0700384 udelay(5);
385 /* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */
Googler9398cc32022-12-02 17:21:52 +0800386 m_can_write(cdev, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE);
Googleraf606d22022-10-26 21:40:12 -0700387 } else {
Googler9398cc32022-12-02 17:21:52 +0800388 m_can_write(cdev, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE));
Googleraf606d22022-10-26 21:40:12 -0700389 }
390
391 /* there's a delay for module initialization */
392 if (enable)
393 val = CCCR_INIT | CCCR_CCE;
394
Googler9398cc32022-12-02 17:21:52 +0800395 while ((m_can_read(cdev, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) {
Googleraf606d22022-10-26 21:40:12 -0700396 if (timeout == 0) {
Googler9398cc32022-12-02 17:21:52 +0800397 netdev_warn(cdev->net, "Failed to init module\n");
Googleraf606d22022-10-26 21:40:12 -0700398 return;
399 }
400 timeout--;
401 udelay(1);
402 }
403}
404
Googler9398cc32022-12-02 17:21:52 +0800405static inline void m_can_enable_all_interrupts(struct m_can_classdev *cdev)
Googleraf606d22022-10-26 21:40:12 -0700406{
Googler9398cc32022-12-02 17:21:52 +0800407 /* Only interrupt line 0 is used in this driver */
408 m_can_write(cdev, M_CAN_ILE, ILE_EINT0);
Googleraf606d22022-10-26 21:40:12 -0700409}
410
Googler9398cc32022-12-02 17:21:52 +0800411static inline void m_can_disable_all_interrupts(struct m_can_classdev *cdev)
Googleraf606d22022-10-26 21:40:12 -0700412{
Googler9398cc32022-12-02 17:21:52 +0800413 m_can_write(cdev, M_CAN_ILE, 0x0);
414}
415
416static void m_can_clean(struct net_device *net)
417{
418 struct m_can_classdev *cdev = netdev_priv(net);
419
420 if (cdev->tx_skb) {
421 int putidx = 0;
422
423 net->stats.tx_errors++;
424 if (cdev->version > 30)
425 putidx = ((m_can_read(cdev, M_CAN_TXFQS) &
426 TXFQS_TFQPI_MASK) >> TXFQS_TFQPI_SHIFT);
427
428 can_free_echo_skb(cdev->net, putidx);
429 cdev->tx_skb = NULL;
430 }
Googleraf606d22022-10-26 21:40:12 -0700431}
432
433static void m_can_read_fifo(struct net_device *dev, u32 rxfs)
434{
435 struct net_device_stats *stats = &dev->stats;
Googler9398cc32022-12-02 17:21:52 +0800436 struct m_can_classdev *cdev = netdev_priv(dev);
Googleraf606d22022-10-26 21:40:12 -0700437 struct canfd_frame *cf;
438 struct sk_buff *skb;
439 u32 id, fgi, dlc;
440 int i;
441
442 /* calculate the fifo get index for where to read data */
Googler9398cc32022-12-02 17:21:52 +0800443 fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_SHIFT;
444 dlc = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_DLC);
445 if (dlc & RX_BUF_FDF)
Googleraf606d22022-10-26 21:40:12 -0700446 skb = alloc_canfd_skb(dev, &cf);
447 else
448 skb = alloc_can_skb(dev, (struct can_frame **)&cf);
449 if (!skb) {
450 stats->rx_dropped++;
451 return;
452 }
453
Googler9398cc32022-12-02 17:21:52 +0800454 if (dlc & RX_BUF_FDF)
Googleraf606d22022-10-26 21:40:12 -0700455 cf->len = can_dlc2len((dlc >> 16) & 0x0F);
456 else
457 cf->len = get_can_dlc((dlc >> 16) & 0x0F);
458
Googler9398cc32022-12-02 17:21:52 +0800459 id = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_ID);
Googleraf606d22022-10-26 21:40:12 -0700460 if (id & RX_BUF_XTD)
461 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
462 else
463 cf->can_id = (id >> 18) & CAN_SFF_MASK;
464
465 if (id & RX_BUF_ESI) {
466 cf->flags |= CANFD_ESI;
467 netdev_dbg(dev, "ESI Error\n");
468 }
469
Googler9398cc32022-12-02 17:21:52 +0800470 if (!(dlc & RX_BUF_FDF) && (id & RX_BUF_RTR)) {
Googleraf606d22022-10-26 21:40:12 -0700471 cf->can_id |= CAN_RTR_FLAG;
472 } else {
473 if (dlc & RX_BUF_BRS)
474 cf->flags |= CANFD_BRS;
475
476 for (i = 0; i < cf->len; i += 4)
477 *(u32 *)(cf->data + i) =
Googler9398cc32022-12-02 17:21:52 +0800478 m_can_fifo_read(cdev, fgi,
Googleraf606d22022-10-26 21:40:12 -0700479 M_CAN_FIFO_DATA(i / 4));
480 }
481
482 /* acknowledge rx fifo 0 */
Googler9398cc32022-12-02 17:21:52 +0800483 m_can_write(cdev, M_CAN_RXF0A, fgi);
Googleraf606d22022-10-26 21:40:12 -0700484
485 stats->rx_packets++;
486 stats->rx_bytes += cf->len;
487
488 netif_receive_skb(skb);
489}
490
491static int m_can_do_rx_poll(struct net_device *dev, int quota)
492{
Googler9398cc32022-12-02 17:21:52 +0800493 struct m_can_classdev *cdev = netdev_priv(dev);
Googleraf606d22022-10-26 21:40:12 -0700494 u32 pkts = 0;
495 u32 rxfs;
496
Googler9398cc32022-12-02 17:21:52 +0800497 rxfs = m_can_read(cdev, M_CAN_RXF0S);
Googleraf606d22022-10-26 21:40:12 -0700498 if (!(rxfs & RXFS_FFL_MASK)) {
499 netdev_dbg(dev, "no messages in fifo0\n");
500 return 0;
501 }
502
503 while ((rxfs & RXFS_FFL_MASK) && (quota > 0)) {
Googlerb48fa912023-03-17 12:40:29 +0530504 if (rxfs & RXFS_RFL)
505 netdev_warn(dev, "Rx FIFO 0 Message Lost\n");
506
Googleraf606d22022-10-26 21:40:12 -0700507 m_can_read_fifo(dev, rxfs);
508
509 quota--;
510 pkts++;
Googler9398cc32022-12-02 17:21:52 +0800511 rxfs = m_can_read(cdev, M_CAN_RXF0S);
Googleraf606d22022-10-26 21:40:12 -0700512 }
513
514 if (pkts)
515 can_led_event(dev, CAN_LED_EVENT_RX);
516
517 return pkts;
518}
519
520static int m_can_handle_lost_msg(struct net_device *dev)
521{
522 struct net_device_stats *stats = &dev->stats;
523 struct sk_buff *skb;
524 struct can_frame *frame;
525
526 netdev_err(dev, "msg lost in rxf0\n");
527
528 stats->rx_errors++;
529 stats->rx_over_errors++;
530
531 skb = alloc_can_err_skb(dev, &frame);
532 if (unlikely(!skb))
533 return 0;
534
535 frame->can_id |= CAN_ERR_CRTL;
536 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
537
538 netif_receive_skb(skb);
539
540 return 1;
541}
542
543static int m_can_handle_lec_err(struct net_device *dev,
544 enum m_can_lec_type lec_type)
545{
Googler9398cc32022-12-02 17:21:52 +0800546 struct m_can_classdev *cdev = netdev_priv(dev);
Googleraf606d22022-10-26 21:40:12 -0700547 struct net_device_stats *stats = &dev->stats;
548 struct can_frame *cf;
549 struct sk_buff *skb;
550
Googler9398cc32022-12-02 17:21:52 +0800551 cdev->can.can_stats.bus_error++;
Googleraf606d22022-10-26 21:40:12 -0700552 stats->rx_errors++;
553
554 /* propagate the error condition to the CAN stack */
555 skb = alloc_can_err_skb(dev, &cf);
556 if (unlikely(!skb))
557 return 0;
558
559 /* check for 'last error code' which tells us the
560 * type of the last error to occur on the CAN bus
561 */
562 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
563
564 switch (lec_type) {
565 case LEC_STUFF_ERROR:
566 netdev_dbg(dev, "stuff error\n");
567 cf->data[2] |= CAN_ERR_PROT_STUFF;
568 break;
569 case LEC_FORM_ERROR:
570 netdev_dbg(dev, "form error\n");
571 cf->data[2] |= CAN_ERR_PROT_FORM;
572 break;
573 case LEC_ACK_ERROR:
574 netdev_dbg(dev, "ack error\n");
575 cf->data[3] = CAN_ERR_PROT_LOC_ACK;
576 break;
577 case LEC_BIT1_ERROR:
578 netdev_dbg(dev, "bit1 error\n");
579 cf->data[2] |= CAN_ERR_PROT_BIT1;
580 break;
581 case LEC_BIT0_ERROR:
582 netdev_dbg(dev, "bit0 error\n");
583 cf->data[2] |= CAN_ERR_PROT_BIT0;
584 break;
585 case LEC_CRC_ERROR:
586 netdev_dbg(dev, "CRC error\n");
587 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
588 break;
589 default:
590 break;
591 }
592
593 stats->rx_packets++;
594 stats->rx_bytes += cf->can_dlc;
595 netif_receive_skb(skb);
596
597 return 1;
598}
599
600static int __m_can_get_berr_counter(const struct net_device *dev,
601 struct can_berr_counter *bec)
602{
Googler9398cc32022-12-02 17:21:52 +0800603 struct m_can_classdev *cdev = netdev_priv(dev);
Googleraf606d22022-10-26 21:40:12 -0700604 unsigned int ecr;
605
Googler9398cc32022-12-02 17:21:52 +0800606 ecr = m_can_read(cdev, M_CAN_ECR);
Googleraf606d22022-10-26 21:40:12 -0700607 bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT;
Googler9398cc32022-12-02 17:21:52 +0800608 bec->txerr = (ecr & ECR_TEC_MASK) >> ECR_TEC_SHIFT;
Googleraf606d22022-10-26 21:40:12 -0700609
610 return 0;
611}
612
Googler9398cc32022-12-02 17:21:52 +0800613static int m_can_clk_start(struct m_can_classdev *cdev)
614{
615 int err;
616
617 if (cdev->pm_clock_support == 0)
618 return 0;
619
620 err = pm_runtime_get_sync(cdev->dev);
621 if (err < 0) {
622 pm_runtime_put_noidle(cdev->dev);
623 return err;
624 }
625
626 return 0;
627}
628
629static void m_can_clk_stop(struct m_can_classdev *cdev)
630{
631 if (cdev->pm_clock_support)
632 pm_runtime_put_sync(cdev->dev);
633}
634
Googleraf606d22022-10-26 21:40:12 -0700635static int m_can_get_berr_counter(const struct net_device *dev,
636 struct can_berr_counter *bec)
637{
Googler9398cc32022-12-02 17:21:52 +0800638 struct m_can_classdev *cdev = netdev_priv(dev);
Googleraf606d22022-10-26 21:40:12 -0700639 int err;
640
Googler9398cc32022-12-02 17:21:52 +0800641 err = m_can_clk_start(cdev);
Googleraf606d22022-10-26 21:40:12 -0700642 if (err)
643 return err;
644
645 __m_can_get_berr_counter(dev, bec);
646
Googler9398cc32022-12-02 17:21:52 +0800647 m_can_clk_stop(cdev);
Googleraf606d22022-10-26 21:40:12 -0700648
649 return 0;
650}
651
652static int m_can_handle_state_change(struct net_device *dev,
653 enum can_state new_state)
654{
Googler9398cc32022-12-02 17:21:52 +0800655 struct m_can_classdev *cdev = netdev_priv(dev);
Googleraf606d22022-10-26 21:40:12 -0700656 struct net_device_stats *stats = &dev->stats;
657 struct can_frame *cf;
658 struct sk_buff *skb;
659 struct can_berr_counter bec;
660 unsigned int ecr;
661
662 switch (new_state) {
Googler38bda472022-08-19 10:07:08 -0700663 case CAN_STATE_ERROR_WARNING:
Googleraf606d22022-10-26 21:40:12 -0700664 /* error warning state */
Googler9398cc32022-12-02 17:21:52 +0800665 cdev->can.can_stats.error_warning++;
666 cdev->can.state = CAN_STATE_ERROR_WARNING;
Googleraf606d22022-10-26 21:40:12 -0700667 break;
668 case CAN_STATE_ERROR_PASSIVE:
669 /* error passive state */
Googler9398cc32022-12-02 17:21:52 +0800670 cdev->can.can_stats.error_passive++;
671 cdev->can.state = CAN_STATE_ERROR_PASSIVE;
Googleraf606d22022-10-26 21:40:12 -0700672 break;
673 case CAN_STATE_BUS_OFF:
674 /* bus-off state */
Googler9398cc32022-12-02 17:21:52 +0800675 cdev->can.state = CAN_STATE_BUS_OFF;
676 m_can_disable_all_interrupts(cdev);
677 cdev->can.can_stats.bus_off++;
Googleraf606d22022-10-26 21:40:12 -0700678 can_bus_off(dev);
679 break;
680 default:
681 break;
682 }
683
684 /* propagate the error condition to the CAN stack */
685 skb = alloc_can_err_skb(dev, &cf);
686 if (unlikely(!skb))
687 return 0;
688
689 __m_can_get_berr_counter(dev, &bec);
690
691 switch (new_state) {
Googler38bda472022-08-19 10:07:08 -0700692 case CAN_STATE_ERROR_WARNING:
Googleraf606d22022-10-26 21:40:12 -0700693 /* error warning state */
694 cf->can_id |= CAN_ERR_CRTL;
695 cf->data[1] = (bec.txerr > bec.rxerr) ?
696 CAN_ERR_CRTL_TX_WARNING :
697 CAN_ERR_CRTL_RX_WARNING;
698 cf->data[6] = bec.txerr;
699 cf->data[7] = bec.rxerr;
700 break;
701 case CAN_STATE_ERROR_PASSIVE:
702 /* error passive state */
703 cf->can_id |= CAN_ERR_CRTL;
Googler9398cc32022-12-02 17:21:52 +0800704 ecr = m_can_read(cdev, M_CAN_ECR);
Googleraf606d22022-10-26 21:40:12 -0700705 if (ecr & ECR_RP)
706 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
707 if (bec.txerr > 127)
708 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
709 cf->data[6] = bec.txerr;
710 cf->data[7] = bec.rxerr;
711 break;
712 case CAN_STATE_BUS_OFF:
713 /* bus-off state */
714 cf->can_id |= CAN_ERR_BUSOFF;
715 break;
716 default:
717 break;
718 }
719
720 stats->rx_packets++;
721 stats->rx_bytes += cf->can_dlc;
722 netif_receive_skb(skb);
723
724 return 1;
725}
726
727static int m_can_handle_state_errors(struct net_device *dev, u32 psr)
728{
Googler9398cc32022-12-02 17:21:52 +0800729 struct m_can_classdev *cdev = netdev_priv(dev);
Googleraf606d22022-10-26 21:40:12 -0700730 int work_done = 0;
731
Googler9398cc32022-12-02 17:21:52 +0800732 if (psr & PSR_EW && cdev->can.state != CAN_STATE_ERROR_WARNING) {
Googleraf606d22022-10-26 21:40:12 -0700733 netdev_dbg(dev, "entered error warning state\n");
734 work_done += m_can_handle_state_change(dev,
735 CAN_STATE_ERROR_WARNING);
736 }
737
Googler9398cc32022-12-02 17:21:52 +0800738 if (psr & PSR_EP && cdev->can.state != CAN_STATE_ERROR_PASSIVE) {
Googleraf606d22022-10-26 21:40:12 -0700739 netdev_dbg(dev, "entered error passive state\n");
740 work_done += m_can_handle_state_change(dev,
741 CAN_STATE_ERROR_PASSIVE);
742 }
743
Googler9398cc32022-12-02 17:21:52 +0800744 if (psr & PSR_BO && cdev->can.state != CAN_STATE_BUS_OFF) {
Googleraf606d22022-10-26 21:40:12 -0700745 netdev_dbg(dev, "entered error bus off state\n");
746 work_done += m_can_handle_state_change(dev,
747 CAN_STATE_BUS_OFF);
748 }
749
750 return work_done;
751}
752
753static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus)
754{
755 if (irqstatus & IR_WDI)
756 netdev_err(dev, "Message RAM Watchdog event due to missing READY\n");
Googlerb48fa912023-03-17 12:40:29 +0530757 if (irqstatus & IR_ELO)
758 netdev_err(dev, "Error Logging Overflow\n");
Googleraf606d22022-10-26 21:40:12 -0700759 if (irqstatus & IR_BEU)
760 netdev_err(dev, "Bit Error Uncorrected\n");
761 if (irqstatus & IR_BEC)
762 netdev_err(dev, "Bit Error Corrected\n");
763 if (irqstatus & IR_TOO)
764 netdev_err(dev, "Timeout reached\n");
765 if (irqstatus & IR_MRAF)
766 netdev_err(dev, "Message RAM access failure occurred\n");
767}
768
769static inline bool is_lec_err(u32 psr)
770{
771 psr &= LEC_UNUSED;
772
773 return psr && (psr != LEC_UNUSED);
774}
775
776static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus,
777 u32 psr)
778{
Googler9398cc32022-12-02 17:21:52 +0800779 struct m_can_classdev *cdev = netdev_priv(dev);
Googleraf606d22022-10-26 21:40:12 -0700780 int work_done = 0;
781
782 if (irqstatus & IR_RF0L)
783 work_done += m_can_handle_lost_msg(dev);
784
785 /* handle lec errors on the bus */
Googler9398cc32022-12-02 17:21:52 +0800786 if ((cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
Googleraf606d22022-10-26 21:40:12 -0700787 is_lec_err(psr))
788 work_done += m_can_handle_lec_err(dev, psr & LEC_UNUSED);
789
790 /* other unproccessed error interrupts */
791 m_can_handle_other_err(dev, irqstatus);
792
793 return work_done;
794}
795
Googler9398cc32022-12-02 17:21:52 +0800796static int m_can_rx_handler(struct net_device *dev, int quota)
Googleraf606d22022-10-26 21:40:12 -0700797{
Googler9398cc32022-12-02 17:21:52 +0800798 struct m_can_classdev *cdev = netdev_priv(dev);
Googleraf606d22022-10-26 21:40:12 -0700799 int work_done = 0;
800 u32 irqstatus, psr;
801
Googler9398cc32022-12-02 17:21:52 +0800802 irqstatus = cdev->irqstatus | m_can_read(cdev, M_CAN_IR);
Googleraf606d22022-10-26 21:40:12 -0700803 if (!irqstatus)
804 goto end;
805
Googler9398cc32022-12-02 17:21:52 +0800806 /* Errata workaround for issue "Needless activation of MRAF irq"
807 * During frame reception while the MCAN is in Error Passive state
808 * and the Receive Error Counter has the value MCAN_ECR.REC = 127,
809 * it may happen that MCAN_IR.MRAF is set although there was no
810 * Message RAM access failure.
811 * If MCAN_IR.MRAF is enabled, an interrupt to the Host CPU is generated
812 * The Message RAM Access Failure interrupt routine needs to check
813 * whether MCAN_ECR.RP = ’1’ and MCAN_ECR.REC = 127.
814 * In this case, reset MCAN_IR.MRAF. No further action is required.
815 */
816 if (cdev->version <= 31 && irqstatus & IR_MRAF &&
817 m_can_read(cdev, M_CAN_ECR) & ECR_RP) {
818 struct can_berr_counter bec;
819
820 __m_can_get_berr_counter(dev, &bec);
821 if (bec.rxerr == 127) {
822 m_can_write(cdev, M_CAN_IR, IR_MRAF);
823 irqstatus &= ~IR_MRAF;
824 }
825 }
826
827 psr = m_can_read(cdev, M_CAN_PSR);
828
Googleraf606d22022-10-26 21:40:12 -0700829 if (irqstatus & IR_ERR_STATE)
830 work_done += m_can_handle_state_errors(dev, psr);
831
Googler9398cc32022-12-02 17:21:52 +0800832 if (irqstatus & IR_ERR_BUS_30X)
Googleraf606d22022-10-26 21:40:12 -0700833 work_done += m_can_handle_bus_errors(dev, irqstatus, psr);
834
835 if (irqstatus & IR_RF0N)
836 work_done += m_can_do_rx_poll(dev, (quota - work_done));
837end:
838 return work_done;
839}
840
Googler9398cc32022-12-02 17:21:52 +0800841static int m_can_rx_peripheral(struct net_device *dev)
842{
843 struct m_can_classdev *cdev = netdev_priv(dev);
844
Googlerb48fa912023-03-17 12:40:29 +0530845 m_can_rx_handler(dev, 1);
Googler9398cc32022-12-02 17:21:52 +0800846
847 m_can_enable_all_interrupts(cdev);
848
849 return 0;
850}
851
852static int m_can_poll(struct napi_struct *napi, int quota)
853{
854 struct net_device *dev = napi->dev;
855 struct m_can_classdev *cdev = netdev_priv(dev);
856 int work_done;
857
858 work_done = m_can_rx_handler(dev, quota);
859 if (work_done < quota) {
860 napi_complete_done(napi, work_done);
861 m_can_enable_all_interrupts(cdev);
862 }
863
864 return work_done;
865}
866
867static void m_can_echo_tx_event(struct net_device *dev)
868{
869 u32 txe_count = 0;
870 u32 m_can_txefs;
871 u32 fgi = 0;
872 int i = 0;
873 unsigned int msg_mark;
874
875 struct m_can_classdev *cdev = netdev_priv(dev);
876 struct net_device_stats *stats = &dev->stats;
877
878 /* read tx event fifo status */
879 m_can_txefs = m_can_read(cdev, M_CAN_TXEFS);
880
881 /* Get Tx Event fifo element count */
882 txe_count = (m_can_txefs & TXEFS_EFFL_MASK)
883 >> TXEFS_EFFL_SHIFT;
884
885 /* Get and process all sent elements */
886 for (i = 0; i < txe_count; i++) {
887 /* retrieve get index */
888 fgi = (m_can_read(cdev, M_CAN_TXEFS) & TXEFS_EFGI_MASK)
889 >> TXEFS_EFGI_SHIFT;
890
891 /* get message marker */
892 msg_mark = (m_can_txe_fifo_read(cdev, fgi, 4) &
893 TX_EVENT_MM_MASK) >> TX_EVENT_MM_SHIFT;
894
895 /* ack txe element */
896 m_can_write(cdev, M_CAN_TXEFA, (TXEFA_EFAI_MASK &
897 (fgi << TXEFA_EFAI_SHIFT)));
898
899 /* update stats */
900 stats->tx_bytes += can_get_echo_skb(dev, msg_mark);
901 stats->tx_packets++;
902 }
903}
904
Googleraf606d22022-10-26 21:40:12 -0700905static irqreturn_t m_can_isr(int irq, void *dev_id)
906{
907 struct net_device *dev = (struct net_device *)dev_id;
Googler9398cc32022-12-02 17:21:52 +0800908 struct m_can_classdev *cdev = netdev_priv(dev);
Googleraf606d22022-10-26 21:40:12 -0700909 struct net_device_stats *stats = &dev->stats;
910 u32 ir;
911
Googler9398cc32022-12-02 17:21:52 +0800912 if (pm_runtime_suspended(cdev->dev))
913 return IRQ_NONE;
914 ir = m_can_read(cdev, M_CAN_IR);
Googleraf606d22022-10-26 21:40:12 -0700915 if (!ir)
916 return IRQ_NONE;
917
918 /* ACK all irqs */
919 if (ir & IR_ALL_INT)
Googler9398cc32022-12-02 17:21:52 +0800920 m_can_write(cdev, M_CAN_IR, ir);
921
922 if (cdev->ops->clear_interrupts)
923 cdev->ops->clear_interrupts(cdev);
Googleraf606d22022-10-26 21:40:12 -0700924
925 /* schedule NAPI in case of
926 * - rx IRQ
927 * - state change IRQ
928 * - bus error IRQ and bus error reporting
929 */
Googler9398cc32022-12-02 17:21:52 +0800930 if ((ir & IR_RF0N) || (ir & IR_ERR_ALL_30X)) {
931 cdev->irqstatus = ir;
932 m_can_disable_all_interrupts(cdev);
933 if (!cdev->is_peripheral)
934 napi_schedule(&cdev->napi);
935 else
936 m_can_rx_peripheral(dev);
Googleraf606d22022-10-26 21:40:12 -0700937 }
938
Googler9398cc32022-12-02 17:21:52 +0800939 if (cdev->version == 30) {
940 if (ir & IR_TC) {
941 /* Transmission Complete Interrupt*/
942 stats->tx_bytes += can_get_echo_skb(dev, 0);
943 stats->tx_packets++;
944 can_led_event(dev, CAN_LED_EVENT_TX);
945 netif_wake_queue(dev);
946 }
947 } else {
948 if (ir & IR_TEFN) {
949 /* New TX FIFO Element arrived */
950 m_can_echo_tx_event(dev);
951 can_led_event(dev, CAN_LED_EVENT_TX);
952 if (netif_queue_stopped(dev) &&
953 !m_can_tx_fifo_full(cdev))
954 netif_wake_queue(dev);
955 }
Googleraf606d22022-10-26 21:40:12 -0700956 }
957
958 return IRQ_HANDLED;
959}
960
Googler9398cc32022-12-02 17:21:52 +0800961static const struct can_bittiming_const m_can_bittiming_const_30X = {
Googleraf606d22022-10-26 21:40:12 -0700962 .name = KBUILD_MODNAME,
963 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
964 .tseg1_max = 64,
965 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
966 .tseg2_max = 16,
967 .sjw_max = 16,
968 .brp_min = 1,
969 .brp_max = 1024,
970 .brp_inc = 1,
971};
972
Googler9398cc32022-12-02 17:21:52 +0800973static const struct can_bittiming_const m_can_data_bittiming_const_30X = {
Googleraf606d22022-10-26 21:40:12 -0700974 .name = KBUILD_MODNAME,
975 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
976 .tseg1_max = 16,
977 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
978 .tseg2_max = 8,
979 .sjw_max = 4,
980 .brp_min = 1,
981 .brp_max = 32,
982 .brp_inc = 1,
983};
984
Googler9398cc32022-12-02 17:21:52 +0800985static const struct can_bittiming_const m_can_bittiming_const_31X = {
986 .name = KBUILD_MODNAME,
987 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
988 .tseg1_max = 256,
989 .tseg2_min = 2, /* Time segment 2 = phase_seg2 */
990 .tseg2_max = 128,
991 .sjw_max = 128,
992 .brp_min = 1,
993 .brp_max = 512,
994 .brp_inc = 1,
995};
996
997static const struct can_bittiming_const m_can_data_bittiming_const_31X = {
998 .name = KBUILD_MODNAME,
999 .tseg1_min = 1, /* Time segment 1 = prop_seg + phase_seg1 */
1000 .tseg1_max = 32,
1001 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
1002 .tseg2_max = 16,
1003 .sjw_max = 16,
1004 .brp_min = 1,
1005 .brp_max = 32,
1006 .brp_inc = 1,
1007};
1008
Googleraf606d22022-10-26 21:40:12 -07001009static int m_can_set_bittiming(struct net_device *dev)
1010{
Googler9398cc32022-12-02 17:21:52 +08001011 struct m_can_classdev *cdev = netdev_priv(dev);
1012 const struct can_bittiming *bt = &cdev->can.bittiming;
1013 const struct can_bittiming *dbt = &cdev->can.data_bittiming;
Googleraf606d22022-10-26 21:40:12 -07001014 u16 brp, sjw, tseg1, tseg2;
1015 u32 reg_btp;
1016
1017 brp = bt->brp - 1;
1018 sjw = bt->sjw - 1;
1019 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
1020 tseg2 = bt->phase_seg2 - 1;
Googler9398cc32022-12-02 17:21:52 +08001021 reg_btp = (brp << NBTP_NBRP_SHIFT) | (sjw << NBTP_NSJW_SHIFT) |
1022 (tseg1 << NBTP_NTSEG1_SHIFT) | (tseg2 << NBTP_NTSEG2_SHIFT);
1023 m_can_write(cdev, M_CAN_NBTP, reg_btp);
Googleraf606d22022-10-26 21:40:12 -07001024
Googler9398cc32022-12-02 17:21:52 +08001025 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) {
1026 reg_btp = 0;
Googleraf606d22022-10-26 21:40:12 -07001027 brp = dbt->brp - 1;
1028 sjw = dbt->sjw - 1;
1029 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
1030 tseg2 = dbt->phase_seg2 - 1;
Googler9398cc32022-12-02 17:21:52 +08001031
1032 /* TDC is only needed for bitrates beyond 2.5 MBit/s.
1033 * This is mentioned in the "Bit Time Requirements for CAN FD"
1034 * paper presented at the International CAN Conference 2013
1035 */
1036 if (dbt->bitrate > 2500000) {
1037 u32 tdco, ssp;
1038
1039 /* Use the same value of secondary sampling point
1040 * as the data sampling point
1041 */
1042 ssp = dbt->sample_point;
1043
1044 /* Equation based on Bosch's M_CAN User Manual's
1045 * Transmitter Delay Compensation Section
1046 */
1047 tdco = (cdev->can.clock.freq / 1000) *
1048 ssp / dbt->bitrate;
1049
1050 /* Max valid TDCO value is 127 */
1051 if (tdco > 127) {
1052 netdev_warn(dev, "TDCO value of %u is beyond maximum. Using maximum possible value\n",
1053 tdco);
1054 tdco = 127;
1055 }
1056
1057 reg_btp |= DBTP_TDC;
1058 m_can_write(cdev, M_CAN_TDCR,
1059 tdco << TDCR_TDCO_SHIFT);
1060 }
1061
1062 reg_btp |= (brp << DBTP_DBRP_SHIFT) |
1063 (sjw << DBTP_DSJW_SHIFT) |
1064 (tseg1 << DBTP_DTSEG1_SHIFT) |
1065 (tseg2 << DBTP_DTSEG2_SHIFT);
1066
1067 m_can_write(cdev, M_CAN_DBTP, reg_btp);
Googleraf606d22022-10-26 21:40:12 -07001068 }
1069
1070 return 0;
1071}
1072
1073/* Configure M_CAN chip:
1074 * - set rx buffer/fifo element size
1075 * - configure rx fifo
1076 * - accept non-matching frame into fifo 0
1077 * - configure tx buffer
Googler9398cc32022-12-02 17:21:52 +08001078 * - >= v3.1.x: TX FIFO is used
Googleraf606d22022-10-26 21:40:12 -07001079 * - configure mode
1080 * - setup bittiming
1081 */
1082static void m_can_chip_config(struct net_device *dev)
1083{
Googler9398cc32022-12-02 17:21:52 +08001084 struct m_can_classdev *cdev = netdev_priv(dev);
Googleraf606d22022-10-26 21:40:12 -07001085 u32 cccr, test;
1086
Googler9398cc32022-12-02 17:21:52 +08001087 m_can_config_endisable(cdev, true);
Googleraf606d22022-10-26 21:40:12 -07001088
1089 /* RX Buffer/FIFO Element Size 64 bytes data field */
Googler9398cc32022-12-02 17:21:52 +08001090 m_can_write(cdev, M_CAN_RXESC, M_CAN_RXESC_64BYTES);
Googleraf606d22022-10-26 21:40:12 -07001091
1092 /* Accept Non-matching Frames Into FIFO 0 */
Googler9398cc32022-12-02 17:21:52 +08001093 m_can_write(cdev, M_CAN_GFC, 0x0);
Googleraf606d22022-10-26 21:40:12 -07001094
Googler9398cc32022-12-02 17:21:52 +08001095 if (cdev->version == 30) {
1096 /* only support one Tx Buffer currently */
1097 m_can_write(cdev, M_CAN_TXBC, (1 << TXBC_NDTB_SHIFT) |
1098 cdev->mcfg[MRAM_TXB].off);
1099 } else {
1100 /* TX FIFO is used for newer IP Core versions */
1101 m_can_write(cdev, M_CAN_TXBC,
1102 (cdev->mcfg[MRAM_TXB].num << TXBC_TFQS_SHIFT) |
1103 (cdev->mcfg[MRAM_TXB].off));
1104 }
Googleraf606d22022-10-26 21:40:12 -07001105
1106 /* support 64 bytes payload */
Googler9398cc32022-12-02 17:21:52 +08001107 m_can_write(cdev, M_CAN_TXESC, TXESC_TBDS_64BYTES);
Googleraf606d22022-10-26 21:40:12 -07001108
Googler9398cc32022-12-02 17:21:52 +08001109 /* TX Event FIFO */
1110 if (cdev->version == 30) {
1111 m_can_write(cdev, M_CAN_TXEFC, (1 << TXEFC_EFS_SHIFT) |
1112 cdev->mcfg[MRAM_TXE].off);
1113 } else {
1114 /* Full TX Event FIFO is used */
1115 m_can_write(cdev, M_CAN_TXEFC,
1116 ((cdev->mcfg[MRAM_TXE].num << TXEFC_EFS_SHIFT)
1117 & TXEFC_EFS_MASK) |
1118 cdev->mcfg[MRAM_TXE].off);
1119 }
Googleraf606d22022-10-26 21:40:12 -07001120
1121 /* rx fifo configuration, blocking mode, fifo size 1 */
Googler9398cc32022-12-02 17:21:52 +08001122 m_can_write(cdev, M_CAN_RXF0C,
1123 (cdev->mcfg[MRAM_RXF0].num << RXFC_FS_SHIFT) |
1124 cdev->mcfg[MRAM_RXF0].off);
Googleraf606d22022-10-26 21:40:12 -07001125
Googler9398cc32022-12-02 17:21:52 +08001126 m_can_write(cdev, M_CAN_RXF1C,
1127 (cdev->mcfg[MRAM_RXF1].num << RXFC_FS_SHIFT) |
1128 cdev->mcfg[MRAM_RXF1].off);
Googleraf606d22022-10-26 21:40:12 -07001129
Googler9398cc32022-12-02 17:21:52 +08001130 cccr = m_can_read(cdev, M_CAN_CCCR);
1131 test = m_can_read(cdev, M_CAN_TEST);
Googleraf606d22022-10-26 21:40:12 -07001132 test &= ~TEST_LBCK;
Googler9398cc32022-12-02 17:21:52 +08001133 if (cdev->version == 30) {
1134 /* Version 3.0.x */
Googleraf606d22022-10-26 21:40:12 -07001135
Googler9398cc32022-12-02 17:21:52 +08001136 cccr &= ~(CCCR_TEST | CCCR_MON |
1137 (CCCR_CMR_MASK << CCCR_CMR_SHIFT) |
1138 (CCCR_CME_MASK << CCCR_CME_SHIFT));
Googleraf606d22022-10-26 21:40:12 -07001139
Googler9398cc32022-12-02 17:21:52 +08001140 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD)
1141 cccr |= CCCR_CME_CANFD_BRS << CCCR_CME_SHIFT;
1142
1143 } else {
1144 /* Version 3.1.x or 3.2.x */
1145 cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_BRSE | CCCR_FDOE |
1146 CCCR_NISO);
1147
1148 /* Only 3.2.x has NISO Bit implemented */
1149 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)
1150 cccr |= CCCR_NISO;
1151
1152 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD)
1153 cccr |= (CCCR_BRSE | CCCR_FDOE);
1154 }
1155
1156 /* Loopback Mode */
1157 if (cdev->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
1158 cccr |= CCCR_TEST | CCCR_MON;
Googler9726be62022-12-14 05:53:31 +00001159 test |= TEST_LBCK;
1160 }
1161
Googler9398cc32022-12-02 17:21:52 +08001162 /* Enable Monitoring (all versions) */
1163 if (cdev->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1164 cccr |= CCCR_MON;
Googler9726be62022-12-14 05:53:31 +00001165
Googler9398cc32022-12-02 17:21:52 +08001166 /* Write config */
1167 m_can_write(cdev, M_CAN_CCCR, cccr);
1168 m_can_write(cdev, M_CAN_TEST, test);
Googleraf606d22022-10-26 21:40:12 -07001169
Googler9398cc32022-12-02 17:21:52 +08001170 /* Enable interrupts */
1171 m_can_write(cdev, M_CAN_IR, IR_ALL_INT);
1172 if (!(cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
1173 if (cdev->version == 30)
1174 m_can_write(cdev, M_CAN_IE, IR_ALL_INT &
1175 ~(IR_ERR_LEC_30X));
1176 else
1177 m_can_write(cdev, M_CAN_IE, IR_ALL_INT &
1178 ~(IR_ERR_LEC_31X));
Googleraf606d22022-10-26 21:40:12 -07001179 else
Googler9398cc32022-12-02 17:21:52 +08001180 m_can_write(cdev, M_CAN_IE, IR_ALL_INT);
Googleraf606d22022-10-26 21:40:12 -07001181
1182 /* route all interrupts to INT0 */
Googler9398cc32022-12-02 17:21:52 +08001183 m_can_write(cdev, M_CAN_ILS, ILS_ALL_INT0);
Googleraf606d22022-10-26 21:40:12 -07001184
1185 /* set bittiming params */
1186 m_can_set_bittiming(dev);
1187
Googler9398cc32022-12-02 17:21:52 +08001188 m_can_config_endisable(cdev, false);
1189
1190 if (cdev->ops->init)
1191 cdev->ops->init(cdev);
Googleraf606d22022-10-26 21:40:12 -07001192}
1193
1194static void m_can_start(struct net_device *dev)
1195{
Googler9398cc32022-12-02 17:21:52 +08001196 struct m_can_classdev *cdev = netdev_priv(dev);
Googleraf606d22022-10-26 21:40:12 -07001197
1198 /* basic m_can configuration */
1199 m_can_chip_config(dev);
1200
Googler9398cc32022-12-02 17:21:52 +08001201 cdev->can.state = CAN_STATE_ERROR_ACTIVE;
Googleraf606d22022-10-26 21:40:12 -07001202
Googler9398cc32022-12-02 17:21:52 +08001203 m_can_enable_all_interrupts(cdev);
Googleraf606d22022-10-26 21:40:12 -07001204}
1205
1206static int m_can_set_mode(struct net_device *dev, enum can_mode mode)
1207{
1208 switch (mode) {
1209 case CAN_MODE_START:
Googler9398cc32022-12-02 17:21:52 +08001210 m_can_clean(dev);
Googleraf606d22022-10-26 21:40:12 -07001211 m_can_start(dev);
1212 netif_wake_queue(dev);
1213 break;
1214 default:
1215 return -EOPNOTSUPP;
1216 }
1217
1218 return 0;
1219}
1220
Googler9398cc32022-12-02 17:21:52 +08001221/* Checks core release number of M_CAN
1222 * returns 0 if an unsupported device is detected
1223 * else it returns the release and step coded as:
1224 * return value = 10 * <release> + 1 * <step>
1225 */
1226static int m_can_check_core_release(struct m_can_classdev *cdev)
Googleraf606d22022-10-26 21:40:12 -07001227{
Googler9398cc32022-12-02 17:21:52 +08001228 u32 crel_reg;
1229 u8 rel;
1230 u8 step;
1231 int res;
1232
1233 /* Read Core Release Version and split into version number
1234 * Example: Version 3.2.1 => rel = 3; step = 2; substep = 1;
1235 */
1236 crel_reg = m_can_read(cdev, M_CAN_CREL);
1237 rel = (u8)((crel_reg & CREL_REL_MASK) >> CREL_REL_SHIFT);
1238 step = (u8)((crel_reg & CREL_STEP_MASK) >> CREL_STEP_SHIFT);
1239
1240 if (rel == 3) {
1241 /* M_CAN v3.x.y: create return value */
1242 res = 30 + step;
1243 } else {
1244 /* Unsupported M_CAN version */
1245 res = 0;
1246 }
1247
1248 return res;
Googleraf606d22022-10-26 21:40:12 -07001249}
1250
Googler9398cc32022-12-02 17:21:52 +08001251/* Selectable Non ISO support only in version 3.2.x
1252 * This function checks if the bit is writable.
1253 */
1254static bool m_can_niso_supported(struct m_can_classdev *cdev)
Googleraf606d22022-10-26 21:40:12 -07001255{
Googler9398cc32022-12-02 17:21:52 +08001256 u32 cccr_reg, cccr_poll = 0;
1257 int niso_timeout = -ETIMEDOUT;
1258 int i;
Googler0109c452022-10-13 17:50:39 +08001259
Googler9398cc32022-12-02 17:21:52 +08001260 m_can_config_endisable(cdev, true);
1261 cccr_reg = m_can_read(cdev, M_CAN_CCCR);
1262 cccr_reg |= CCCR_NISO;
1263 m_can_write(cdev, M_CAN_CCCR, cccr_reg);
Googleraf606d22022-10-26 21:40:12 -07001264
Googler9398cc32022-12-02 17:21:52 +08001265 for (i = 0; i <= 10; i++) {
1266 cccr_poll = m_can_read(cdev, M_CAN_CCCR);
1267 if (cccr_poll == cccr_reg) {
1268 niso_timeout = 0;
1269 break;
1270 }
Googleraf606d22022-10-26 21:40:12 -07001271
Googler9398cc32022-12-02 17:21:52 +08001272 usleep_range(1, 5);
1273 }
Googleraf606d22022-10-26 21:40:12 -07001274
Googler9398cc32022-12-02 17:21:52 +08001275 /* Clear NISO */
1276 cccr_reg &= ~(CCCR_NISO);
1277 m_can_write(cdev, M_CAN_CCCR, cccr_reg);
Googler9726be62022-12-14 05:53:31 +00001278
Googler9398cc32022-12-02 17:21:52 +08001279 m_can_config_endisable(cdev, false);
1280
1281 /* return false if time out (-ETIMEDOUT), else return true */
1282 return !niso_timeout;
1283}
1284
1285static int m_can_dev_setup(struct m_can_classdev *m_can_dev)
1286{
1287 struct net_device *dev = m_can_dev->net;
1288 int m_can_version;
1289
1290 m_can_version = m_can_check_core_release(m_can_dev);
1291 /* return if unsupported version */
1292 if (!m_can_version) {
1293 dev_err(m_can_dev->dev, "Unsupported version number: %2d",
1294 m_can_version);
1295 return -EINVAL;
1296 }
1297
1298 if (!m_can_dev->is_peripheral)
1299 netif_napi_add(dev, &m_can_dev->napi,
1300 m_can_poll, M_CAN_NAPI_WEIGHT);
1301
1302 /* Shared properties of all M_CAN versions */
1303 m_can_dev->version = m_can_version;
1304 m_can_dev->can.do_set_mode = m_can_set_mode;
1305 m_can_dev->can.do_get_berr_counter = m_can_get_berr_counter;
1306
1307 /* Set M_CAN supported operations */
1308 m_can_dev->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
Googleraf606d22022-10-26 21:40:12 -07001309 CAN_CTRLMODE_LISTENONLY |
1310 CAN_CTRLMODE_BERR_REPORTING |
1311 CAN_CTRLMODE_FD;
1312
Googler9398cc32022-12-02 17:21:52 +08001313 /* Set properties depending on M_CAN version */
1314 switch (m_can_dev->version) {
1315 case 30:
1316 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */
1317 can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
1318 m_can_dev->can.bittiming_const = m_can_dev->bit_timing ?
1319 m_can_dev->bit_timing : &m_can_bittiming_const_30X;
Googleraf606d22022-10-26 21:40:12 -07001320
Googler9398cc32022-12-02 17:21:52 +08001321 m_can_dev->can.data_bittiming_const = m_can_dev->data_timing ?
1322 m_can_dev->data_timing :
1323 &m_can_data_bittiming_const_30X;
1324 break;
1325 case 31:
1326 /* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */
1327 can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
1328 m_can_dev->can.bittiming_const = m_can_dev->bit_timing ?
1329 m_can_dev->bit_timing : &m_can_bittiming_const_31X;
Googleraf606d22022-10-26 21:40:12 -07001330
Googler9398cc32022-12-02 17:21:52 +08001331 m_can_dev->can.data_bittiming_const = m_can_dev->data_timing ?
1332 m_can_dev->data_timing :
1333 &m_can_data_bittiming_const_31X;
1334 break;
1335 case 32:
1336 case 33:
1337 /* Support both MCAN version v3.2.x and v3.3.0 */
1338 m_can_dev->can.bittiming_const = m_can_dev->bit_timing ?
1339 m_can_dev->bit_timing : &m_can_bittiming_const_31X;
Googleraf606d22022-10-26 21:40:12 -07001340
Googler9398cc32022-12-02 17:21:52 +08001341 m_can_dev->can.data_bittiming_const = m_can_dev->data_timing ?
1342 m_can_dev->data_timing :
1343 &m_can_data_bittiming_const_31X;
Googler9726be62022-12-14 05:53:31 +00001344
Googler9398cc32022-12-02 17:21:52 +08001345 m_can_dev->can.ctrlmode_supported |=
1346 (m_can_niso_supported(m_can_dev)
1347 ? CAN_CTRLMODE_FD_NON_ISO
1348 : 0);
1349 break;
1350 default:
1351 dev_err(m_can_dev->dev, "Unsupported version number: %2d",
1352 m_can_dev->version);
1353 return -EINVAL;
Googleraf606d22022-10-26 21:40:12 -07001354 }
1355
Googler9398cc32022-12-02 17:21:52 +08001356 if (m_can_dev->ops->init)
1357 m_can_dev->ops->init(m_can_dev);
Googleraf606d22022-10-26 21:40:12 -07001358
1359 return 0;
1360}
1361
1362static void m_can_stop(struct net_device *dev)
1363{
Googler9398cc32022-12-02 17:21:52 +08001364 struct m_can_classdev *cdev = netdev_priv(dev);
Googleraf606d22022-10-26 21:40:12 -07001365
1366 /* disable all interrupts */
Googler9398cc32022-12-02 17:21:52 +08001367 m_can_disable_all_interrupts(cdev);
Googleraf606d22022-10-26 21:40:12 -07001368
Googler9398cc32022-12-02 17:21:52 +08001369 /* Set init mode to disengage from the network */
1370 m_can_config_endisable(cdev, true);
Googler9726be62022-12-14 05:53:31 +00001371
Googleraf606d22022-10-26 21:40:12 -07001372 /* set the state as STOPPED */
Googler9398cc32022-12-02 17:21:52 +08001373 cdev->can.state = CAN_STATE_STOPPED;
Googleraf606d22022-10-26 21:40:12 -07001374}
1375
1376static int m_can_close(struct net_device *dev)
1377{
Googler9398cc32022-12-02 17:21:52 +08001378 struct m_can_classdev *cdev = netdev_priv(dev);
Googleraf606d22022-10-26 21:40:12 -07001379
1380 netif_stop_queue(dev);
Googler9398cc32022-12-02 17:21:52 +08001381
1382 if (!cdev->is_peripheral)
1383 napi_disable(&cdev->napi);
1384
Googleraf606d22022-10-26 21:40:12 -07001385 m_can_stop(dev);
Googler9398cc32022-12-02 17:21:52 +08001386 m_can_clk_stop(cdev);
Googleraf606d22022-10-26 21:40:12 -07001387 free_irq(dev->irq, dev);
Googler9398cc32022-12-02 17:21:52 +08001388
1389 if (cdev->is_peripheral) {
1390 cdev->tx_skb = NULL;
1391 destroy_workqueue(cdev->tx_wq);
1392 cdev->tx_wq = NULL;
1393 }
1394
Googleraf606d22022-10-26 21:40:12 -07001395 close_candev(dev);
1396 can_led_event(dev, CAN_LED_EVENT_STOP);
1397
1398 return 0;
1399}
1400
Googler9398cc32022-12-02 17:21:52 +08001401static int m_can_next_echo_skb_occupied(struct net_device *dev, int putidx)
Googleraf606d22022-10-26 21:40:12 -07001402{
Googler9398cc32022-12-02 17:21:52 +08001403 struct m_can_classdev *cdev = netdev_priv(dev);
1404 /*get wrap around for loopback skb index */
1405 unsigned int wrap = cdev->can.echo_skb_max;
1406 int next_idx;
1407
1408 /* calculate next index */
1409 next_idx = (++putidx >= wrap ? 0 : putidx);
1410
1411 /* check if occupied */
1412 return !!cdev->can.echo_skb[next_idx];
1413}
1414
1415static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev)
1416{
1417 struct canfd_frame *cf = (struct canfd_frame *)cdev->tx_skb->data;
1418 struct net_device *dev = cdev->net;
1419 struct sk_buff *skb = cdev->tx_skb;
1420 u32 id, cccr, fdflags;
Googleraf606d22022-10-26 21:40:12 -07001421 int i;
Googler9398cc32022-12-02 17:21:52 +08001422 int putidx;
Googleraf606d22022-10-26 21:40:12 -07001423
Googler9398cc32022-12-02 17:21:52 +08001424 /* Generate ID field for TX buffer Element */
1425 /* Common to all supported M_CAN versions */
Googleraf606d22022-10-26 21:40:12 -07001426 if (cf->can_id & CAN_EFF_FLAG) {
1427 id = cf->can_id & CAN_EFF_MASK;
1428 id |= TX_BUF_XTD;
1429 } else {
1430 id = ((cf->can_id & CAN_SFF_MASK) << 18);
1431 }
1432
1433 if (cf->can_id & CAN_RTR_FLAG)
1434 id |= TX_BUF_RTR;
1435
Googler9398cc32022-12-02 17:21:52 +08001436 if (cdev->version == 30) {
1437 netif_stop_queue(dev);
Googleraf606d22022-10-26 21:40:12 -07001438
Googler9398cc32022-12-02 17:21:52 +08001439 /* message ram configuration */
1440 m_can_fifo_write(cdev, 0, M_CAN_FIFO_ID, id);
1441 m_can_fifo_write(cdev, 0, M_CAN_FIFO_DLC,
1442 can_len2dlc(cf->len) << 16);
Googleraf606d22022-10-26 21:40:12 -07001443
Googler9398cc32022-12-02 17:21:52 +08001444 for (i = 0; i < cf->len; i += 4)
1445 m_can_fifo_write(cdev, 0,
1446 M_CAN_FIFO_DATA(i / 4),
1447 *(u32 *)(cf->data + i));
Googleraf606d22022-10-26 21:40:12 -07001448
Googlerb48fa912023-03-17 12:40:29 +05301449 can_put_echo_skb(skb, dev, 0);
1450
Googler9398cc32022-12-02 17:21:52 +08001451 if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) {
1452 cccr = m_can_read(cdev, M_CAN_CCCR);
1453 cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT);
1454 if (can_is_canfd_skb(skb)) {
1455 if (cf->flags & CANFD_BRS)
1456 cccr |= CCCR_CMR_CANFD_BRS <<
1457 CCCR_CMR_SHIFT;
1458 else
1459 cccr |= CCCR_CMR_CANFD <<
1460 CCCR_CMR_SHIFT;
1461 } else {
1462 cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT;
1463 }
1464 m_can_write(cdev, M_CAN_CCCR, cccr);
Googler0109c452022-10-13 17:50:39 +08001465 }
Googler9398cc32022-12-02 17:21:52 +08001466 m_can_write(cdev, M_CAN_TXBTIE, 0x1);
Googler9398cc32022-12-02 17:21:52 +08001467 m_can_write(cdev, M_CAN_TXBAR, 0x1);
1468 /* End of xmit function for version 3.0.x */
1469 } else {
1470 /* Transmit routine for version >= v3.1.x */
1471
1472 /* Check if FIFO full */
1473 if (m_can_tx_fifo_full(cdev)) {
1474 /* This shouldn't happen */
1475 netif_stop_queue(dev);
1476 netdev_warn(dev,
1477 "TX queue active although FIFO is full.");
1478
1479 if (cdev->is_peripheral) {
1480 kfree_skb(skb);
1481 dev->stats.tx_dropped++;
1482 return NETDEV_TX_OK;
1483 } else {
1484 return NETDEV_TX_BUSY;
1485 }
1486 }
1487
1488 /* get put index for frame */
1489 putidx = ((m_can_read(cdev, M_CAN_TXFQS) & TXFQS_TFQPI_MASK)
1490 >> TXFQS_TFQPI_SHIFT);
1491 /* Write ID Field to FIFO Element */
1492 m_can_fifo_write(cdev, putidx, M_CAN_FIFO_ID, id);
1493
1494 /* get CAN FD configuration of frame */
1495 fdflags = 0;
1496 if (can_is_canfd_skb(skb)) {
1497 fdflags |= TX_BUF_FDF;
1498 if (cf->flags & CANFD_BRS)
1499 fdflags |= TX_BUF_BRS;
1500 }
1501
1502 /* Construct DLC Field. Also contains CAN-FD configuration
1503 * use put index of fifo as message marker
1504 * it is used in TX interrupt for
1505 * sending the correct echo frame
1506 */
1507 m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DLC,
1508 ((putidx << TX_BUF_MM_SHIFT) &
1509 TX_BUF_MM_MASK) |
1510 (can_len2dlc(cf->len) << 16) |
1511 fdflags | TX_BUF_EFC);
1512
1513 for (i = 0; i < cf->len; i += 4)
1514 m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DATA(i / 4),
1515 *(u32 *)(cf->data + i));
1516
1517 /* Push loopback echo.
1518 * Will be looped back on TX interrupt based on message marker
1519 */
1520 can_put_echo_skb(skb, dev, putidx);
1521
1522 /* Enable TX FIFO element to start transfer */
1523 m_can_write(cdev, M_CAN_TXBAR, (1 << putidx));
1524
1525 /* stop network queue if fifo full */
1526 if (m_can_tx_fifo_full(cdev) ||
1527 m_can_next_echo_skb_occupied(dev, putidx))
1528 netif_stop_queue(dev);
Googler0109c452022-10-13 17:50:39 +08001529 }
Googler012a81c2022-09-15 14:55:24 +08001530
Googler9398cc32022-12-02 17:21:52 +08001531 return NETDEV_TX_OK;
1532}
1533
1534static void m_can_tx_work_queue(struct work_struct *ws)
1535{
1536 struct m_can_classdev *cdev = container_of(ws, struct m_can_classdev,
1537 tx_work);
1538
1539 m_can_tx_handler(cdev);
Googlerb48fa912023-03-17 12:40:29 +05301540 cdev->tx_skb = NULL;
Googler9398cc32022-12-02 17:21:52 +08001541}
1542
1543static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
1544 struct net_device *dev)
1545{
1546 struct m_can_classdev *cdev = netdev_priv(dev);
1547
1548 if (can_dropped_invalid_skb(dev, skb))
1549 return NETDEV_TX_OK;
1550
1551 if (cdev->is_peripheral) {
1552 if (cdev->tx_skb) {
1553 netdev_err(dev, "hard_xmit called while tx busy\n");
1554 return NETDEV_TX_BUSY;
1555 }
1556
1557 if (cdev->can.state == CAN_STATE_BUS_OFF) {
1558 m_can_clean(dev);
1559 } else {
1560 /* Need to stop the queue to avoid numerous requests
1561 * from being sent. Suggested improvement is to create
1562 * a queueing mechanism that will queue the skbs and
1563 * process them in order.
1564 */
1565 cdev->tx_skb = skb;
1566 netif_stop_queue(cdev->net);
1567 queue_work(cdev->tx_wq, &cdev->tx_work);
1568 }
1569 } else {
1570 cdev->tx_skb = skb;
1571 return m_can_tx_handler(cdev);
1572 }
Googler9726be62022-12-14 05:53:31 +00001573
Googleraf606d22022-10-26 21:40:12 -07001574 return NETDEV_TX_OK;
1575}
1576
Googler9398cc32022-12-02 17:21:52 +08001577static int m_can_open(struct net_device *dev)
1578{
1579 struct m_can_classdev *cdev = netdev_priv(dev);
1580 int err;
1581
1582 err = m_can_clk_start(cdev);
1583 if (err)
1584 return err;
1585
1586 /* open the can device */
1587 err = open_candev(dev);
1588 if (err) {
1589 netdev_err(dev, "failed to open can device\n");
1590 goto exit_disable_clks;
1591 }
1592
1593 /* register interrupt handler */
1594 if (cdev->is_peripheral) {
1595 cdev->tx_skb = NULL;
1596 cdev->tx_wq = alloc_workqueue("mcan_wq",
1597 WQ_FREEZABLE | WQ_MEM_RECLAIM, 0);
1598 if (!cdev->tx_wq) {
1599 err = -ENOMEM;
1600 goto out_wq_fail;
1601 }
1602
1603 INIT_WORK(&cdev->tx_work, m_can_tx_work_queue);
1604
1605 err = request_threaded_irq(dev->irq, NULL, m_can_isr,
1606 IRQF_ONESHOT,
1607 dev->name, dev);
1608 } else {
1609 err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name,
1610 dev);
1611 }
1612
1613 if (err < 0) {
1614 netdev_err(dev, "failed to request interrupt\n");
1615 goto exit_irq_fail;
1616 }
1617
1618 /* start the m_can controller */
1619 m_can_start(dev);
1620
1621 can_led_event(dev, CAN_LED_EVENT_OPEN);
1622
1623 if (!cdev->is_peripheral)
1624 napi_enable(&cdev->napi);
1625
1626 netif_start_queue(dev);
1627
1628 return 0;
1629
1630exit_irq_fail:
1631 if (cdev->is_peripheral)
1632 destroy_workqueue(cdev->tx_wq);
1633out_wq_fail:
1634 close_candev(dev);
1635exit_disable_clks:
1636 m_can_clk_stop(cdev);
1637 return err;
1638}
1639
Googleraf606d22022-10-26 21:40:12 -07001640static const struct net_device_ops m_can_netdev_ops = {
1641 .ndo_open = m_can_open,
1642 .ndo_stop = m_can_close,
1643 .ndo_start_xmit = m_can_start_xmit,
1644 .ndo_change_mtu = can_change_mtu,
1645};
1646
1647static int register_m_can_dev(struct net_device *dev)
1648{
1649 dev->flags |= IFF_ECHO; /* we support local echo */
1650 dev->netdev_ops = &m_can_netdev_ops;
1651
1652 return register_candev(dev);
1653}
1654
Googler9398cc32022-12-02 17:21:52 +08001655static void m_can_of_parse_mram(struct m_can_classdev *cdev,
1656 const u32 *mram_config_vals)
Googleraf606d22022-10-26 21:40:12 -07001657{
Googler9398cc32022-12-02 17:21:52 +08001658 cdev->mcfg[MRAM_SIDF].off = mram_config_vals[0];
1659 cdev->mcfg[MRAM_SIDF].num = mram_config_vals[1];
1660 cdev->mcfg[MRAM_XIDF].off = cdev->mcfg[MRAM_SIDF].off +
1661 cdev->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE;
1662 cdev->mcfg[MRAM_XIDF].num = mram_config_vals[2];
1663 cdev->mcfg[MRAM_RXF0].off = cdev->mcfg[MRAM_XIDF].off +
1664 cdev->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE;
1665 cdev->mcfg[MRAM_RXF0].num = mram_config_vals[3] &
1666 (RXFC_FS_MASK >> RXFC_FS_SHIFT);
1667 cdev->mcfg[MRAM_RXF1].off = cdev->mcfg[MRAM_RXF0].off +
1668 cdev->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE;
1669 cdev->mcfg[MRAM_RXF1].num = mram_config_vals[4] &
1670 (RXFC_FS_MASK >> RXFC_FS_SHIFT);
1671 cdev->mcfg[MRAM_RXB].off = cdev->mcfg[MRAM_RXF1].off +
1672 cdev->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE;
1673 cdev->mcfg[MRAM_RXB].num = mram_config_vals[5];
1674 cdev->mcfg[MRAM_TXE].off = cdev->mcfg[MRAM_RXB].off +
1675 cdev->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE;
1676 cdev->mcfg[MRAM_TXE].num = mram_config_vals[6];
1677 cdev->mcfg[MRAM_TXB].off = cdev->mcfg[MRAM_TXE].off +
1678 cdev->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE;
1679 cdev->mcfg[MRAM_TXB].num = mram_config_vals[7] &
1680 (TXBC_NDTB_MASK >> TXBC_NDTB_SHIFT);
Googleraf606d22022-10-26 21:40:12 -07001681
Googler9398cc32022-12-02 17:21:52 +08001682 dev_dbg(cdev->dev,
1683 "sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n",
1684 cdev->mcfg[MRAM_SIDF].off, cdev->mcfg[MRAM_SIDF].num,
1685 cdev->mcfg[MRAM_XIDF].off, cdev->mcfg[MRAM_XIDF].num,
1686 cdev->mcfg[MRAM_RXF0].off, cdev->mcfg[MRAM_RXF0].num,
1687 cdev->mcfg[MRAM_RXF1].off, cdev->mcfg[MRAM_RXF1].num,
1688 cdev->mcfg[MRAM_RXB].off, cdev->mcfg[MRAM_RXB].num,
1689 cdev->mcfg[MRAM_TXE].off, cdev->mcfg[MRAM_TXE].num,
1690 cdev->mcfg[MRAM_TXB].off, cdev->mcfg[MRAM_TXB].num);
1691}
Googler012a81c2022-09-15 14:55:24 +08001692
Googler9398cc32022-12-02 17:21:52 +08001693void m_can_init_ram(struct m_can_classdev *cdev)
1694{
1695 int end, i, start;
Googler0109c452022-10-13 17:50:39 +08001696
Googler9726be62022-12-14 05:53:31 +00001697 /* initialize the entire Message RAM in use to avoid possible
1698 * ECC/parity checksum errors when reading an uninitialized buffer
1699 */
Googler9398cc32022-12-02 17:21:52 +08001700 start = cdev->mcfg[MRAM_SIDF].off;
1701 end = cdev->mcfg[MRAM_TXB].off +
1702 cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE;
1703
Googler9726be62022-12-14 05:53:31 +00001704 for (i = start; i < end; i += 4)
Googler9398cc32022-12-02 17:21:52 +08001705 m_can_fifo_write_no_off(cdev, i, 0x0);
Googleraf606d22022-10-26 21:40:12 -07001706}
Googler9398cc32022-12-02 17:21:52 +08001707EXPORT_SYMBOL_GPL(m_can_init_ram);
Googleraf606d22022-10-26 21:40:12 -07001708
Googler9398cc32022-12-02 17:21:52 +08001709int m_can_class_get_clocks(struct m_can_classdev *m_can_dev)
Googleraf606d22022-10-26 21:40:12 -07001710{
Googler9398cc32022-12-02 17:21:52 +08001711 int ret = 0;
Googleraf606d22022-10-26 21:40:12 -07001712
Googler9398cc32022-12-02 17:21:52 +08001713 m_can_dev->hclk = devm_clk_get(m_can_dev->dev, "hclk");
1714 m_can_dev->cclk = devm_clk_get(m_can_dev->dev, "cclk");
1715
1716 if (IS_ERR(m_can_dev->cclk)) {
1717 dev_err(m_can_dev->dev, "no clock found\n");
1718 ret = -ENODEV;
Googleraf606d22022-10-26 21:40:12 -07001719 }
1720
Googler38bda472022-08-19 10:07:08 -07001721 return ret;
1722}
Googler9398cc32022-12-02 17:21:52 +08001723EXPORT_SYMBOL_GPL(m_can_class_get_clocks);
Googler38bda472022-08-19 10:07:08 -07001724
Googler9398cc32022-12-02 17:21:52 +08001725struct m_can_classdev *m_can_class_allocate_dev(struct device *dev)
1726{
1727 struct m_can_classdev *class_dev = NULL;
1728 u32 mram_config_vals[MRAM_CFG_LEN];
1729 struct net_device *net_dev;
1730 u32 tx_fifo_size;
1731 int ret;
1732
1733 ret = fwnode_property_read_u32_array(dev_fwnode(dev),
1734 "bosch,mram-cfg",
1735 mram_config_vals,
1736 sizeof(mram_config_vals) / 4);
1737 if (ret) {
1738 dev_err(dev, "Could not get Message RAM configuration.");
1739 goto out;
1740 }
1741
1742 /* Get TX FIFO size
1743 * Defines the total amount of echo buffers for loopback
1744 */
1745 tx_fifo_size = mram_config_vals[7];
1746
1747 /* allocate the m_can device */
1748 net_dev = alloc_candev(sizeof(*class_dev), tx_fifo_size);
1749 if (!net_dev) {
1750 dev_err(dev, "Failed to allocate CAN device");
1751 goto out;
1752 }
1753
1754 class_dev = netdev_priv(net_dev);
1755 if (!class_dev) {
1756 dev_err(dev, "Failed to init netdev cdevate");
1757 goto out;
1758 }
1759
1760 class_dev->net = net_dev;
1761 class_dev->dev = dev;
1762 SET_NETDEV_DEV(net_dev, dev);
1763
1764 m_can_of_parse_mram(class_dev, mram_config_vals);
1765out:
1766 return class_dev;
1767}
1768EXPORT_SYMBOL_GPL(m_can_class_allocate_dev);
1769
1770void m_can_class_free_dev(struct net_device *net)
1771{
1772 free_candev(net);
1773}
1774EXPORT_SYMBOL_GPL(m_can_class_free_dev);
1775
1776int m_can_class_register(struct m_can_classdev *m_can_dev)
1777{
1778 int ret;
1779
1780 if (m_can_dev->pm_clock_support) {
1781 pm_runtime_enable(m_can_dev->dev);
1782 ret = m_can_clk_start(m_can_dev);
1783 if (ret)
1784 goto pm_runtime_fail;
1785 }
1786
1787 ret = m_can_dev_setup(m_can_dev);
1788 if (ret)
1789 goto clk_disable;
1790
1791 ret = register_m_can_dev(m_can_dev->net);
1792 if (ret) {
1793 dev_err(m_can_dev->dev, "registering %s failed (err=%d)\n",
1794 m_can_dev->net->name, ret);
1795 goto clk_disable;
1796 }
1797
1798 devm_can_led_init(m_can_dev->net);
1799
1800 of_can_transceiver(m_can_dev->net);
1801
1802 dev_info(m_can_dev->dev, "%s device registered (irq=%d, version=%d)\n",
1803 KBUILD_MODNAME, m_can_dev->net->irq, m_can_dev->version);
1804
1805 /* Probe finished
1806 * Stop clocks. They will be reactivated once the M_CAN device is opened
1807 */
1808clk_disable:
1809 m_can_clk_stop(m_can_dev);
1810pm_runtime_fail:
1811 if (ret) {
1812 if (m_can_dev->pm_clock_support)
1813 pm_runtime_disable(m_can_dev->dev);
1814 free_candev(m_can_dev->net);
1815 }
1816
1817 return ret;
1818}
1819EXPORT_SYMBOL_GPL(m_can_class_register);
1820
1821int m_can_class_suspend(struct device *dev)
Googleraf606d22022-10-26 21:40:12 -07001822{
1823 struct net_device *ndev = dev_get_drvdata(dev);
Googler9398cc32022-12-02 17:21:52 +08001824 struct m_can_classdev *cdev = netdev_priv(ndev);
Googleraf606d22022-10-26 21:40:12 -07001825
1826 if (netif_running(ndev)) {
1827 netif_stop_queue(ndev);
1828 netif_device_detach(ndev);
Googler9398cc32022-12-02 17:21:52 +08001829 m_can_stop(ndev);
1830 m_can_clk_stop(cdev);
Googleraf606d22022-10-26 21:40:12 -07001831 }
1832
Googler9398cc32022-12-02 17:21:52 +08001833 pinctrl_pm_select_sleep_state(dev);
Googleraf606d22022-10-26 21:40:12 -07001834
Googler9398cc32022-12-02 17:21:52 +08001835 cdev->can.state = CAN_STATE_SLEEPING;
Googleraf606d22022-10-26 21:40:12 -07001836
1837 return 0;
1838}
Googler9398cc32022-12-02 17:21:52 +08001839EXPORT_SYMBOL_GPL(m_can_class_suspend);
Googleraf606d22022-10-26 21:40:12 -07001840
Googler9398cc32022-12-02 17:21:52 +08001841int m_can_class_resume(struct device *dev)
Googleraf606d22022-10-26 21:40:12 -07001842{
1843 struct net_device *ndev = dev_get_drvdata(dev);
Googler9398cc32022-12-02 17:21:52 +08001844 struct m_can_classdev *cdev = netdev_priv(ndev);
Googleraf606d22022-10-26 21:40:12 -07001845
Googler9398cc32022-12-02 17:21:52 +08001846 pinctrl_pm_select_default_state(dev);
Googleraf606d22022-10-26 21:40:12 -07001847
Googler9398cc32022-12-02 17:21:52 +08001848 cdev->can.state = CAN_STATE_ERROR_ACTIVE;
Googleraf606d22022-10-26 21:40:12 -07001849
1850 if (netif_running(ndev)) {
Googler9398cc32022-12-02 17:21:52 +08001851 int ret;
1852
1853 ret = m_can_clk_start(cdev);
1854 if (ret)
1855 return ret;
1856
1857 m_can_init_ram(cdev);
1858 m_can_start(ndev);
Googleraf606d22022-10-26 21:40:12 -07001859 netif_device_attach(ndev);
1860 netif_start_queue(ndev);
1861 }
1862
1863 return 0;
1864}
Googler9398cc32022-12-02 17:21:52 +08001865EXPORT_SYMBOL_GPL(m_can_class_resume);
Googleraf606d22022-10-26 21:40:12 -07001866
Googler9398cc32022-12-02 17:21:52 +08001867void m_can_class_unregister(struct m_can_classdev *m_can_dev)
Googleraf606d22022-10-26 21:40:12 -07001868{
Googler9398cc32022-12-02 17:21:52 +08001869 unregister_candev(m_can_dev->net);
1870
Googlerb48fa912023-03-17 12:40:29 +05301871 m_can_clk_stop(m_can_dev);
1872
Googler9398cc32022-12-02 17:21:52 +08001873 free_candev(m_can_dev->net);
Googleraf606d22022-10-26 21:40:12 -07001874}
Googler9398cc32022-12-02 17:21:52 +08001875EXPORT_SYMBOL_GPL(m_can_class_unregister);
Googleraf606d22022-10-26 21:40:12 -07001876
1877MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>");
Googler9398cc32022-12-02 17:21:52 +08001878MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
Googleraf606d22022-10-26 21:40:12 -07001879MODULE_LICENSE("GPL v2");
1880MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller");