Googler | b48fa91 | 2023-03-17 12:40:29 +0530 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: BSD-3-Clause-Clear */ |
| 2 | /* |
| 3 | * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. |
| 4 | */ |
| 5 | #include "core.h" |
| 6 | |
| 7 | #ifndef ATH11K_HAL_DESC_H |
| 8 | #define ATH11K_HAL_DESC_H |
| 9 | |
| 10 | #define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0) |
| 11 | |
| 12 | #define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0) |
| 13 | #define BUFFER_ADDR_INFO1_RET_BUF_MGR GENMASK(10, 8) |
| 14 | #define BUFFER_ADDR_INFO1_SW_COOKIE GENMASK(31, 11) |
| 15 | |
| 16 | struct ath11k_buffer_addr { |
| 17 | u32 info0; |
| 18 | u32 info1; |
| 19 | } __packed; |
| 20 | |
| 21 | /* ath11k_buffer_addr |
| 22 | * |
| 23 | * info0 |
| 24 | * Address (lower 32 bits) of the msdu buffer or msdu extension |
| 25 | * descriptor or Link descriptor |
| 26 | * |
| 27 | * addr |
| 28 | * Address (upper 8 bits) of the msdu buffer or msdu extension |
| 29 | * descriptor or Link descriptor |
| 30 | * |
| 31 | * return_buffer_manager (RBM) |
| 32 | * Consumer: WBM |
| 33 | * Producer: SW/FW |
| 34 | * Indicates to which buffer manager the buffer or MSDU_EXTENSION |
| 35 | * descriptor or link descriptor that is being pointed to shall be |
| 36 | * returned after the frame has been processed. It is used by WBM |
| 37 | * for routing purposes. |
| 38 | * |
| 39 | * Values are defined in enum %HAL_RX_BUF_RBM_ |
| 40 | * |
| 41 | * sw_buffer_cookie |
| 42 | * Cookie field exclusively used by SW. HW ignores the contents, |
| 43 | * accept that it passes the programmed value on to other |
| 44 | * descriptors together with the physical address. |
| 45 | * |
| 46 | * Field can be used by SW to for example associate the buffers |
| 47 | * physical address with the virtual address. |
| 48 | */ |
| 49 | |
| 50 | enum hal_tlv_tag { |
| 51 | HAL_MACTX_CBF_START = 0 /* 0x0 */, |
| 52 | HAL_PHYRX_DATA = 1 /* 0x1 */, |
| 53 | HAL_PHYRX_CBF_DATA_RESP = 2 /* 0x2 */, |
| 54 | HAL_PHYRX_ABORT_REQUEST = 3 /* 0x3 */, |
| 55 | HAL_PHYRX_USER_ABORT_NOTIFICATION = 4 /* 0x4 */, |
| 56 | HAL_MACTX_DATA_RESP = 5 /* 0x5 */, |
| 57 | HAL_MACTX_CBF_DATA = 6 /* 0x6 */, |
| 58 | HAL_MACTX_CBF_DONE = 7 /* 0x7 */, |
| 59 | HAL_MACRX_CBF_READ_REQUEST = 8 /* 0x8 */, |
| 60 | HAL_MACRX_CBF_DATA_REQUEST = 9 /* 0x9 */, |
| 61 | HAL_MACRX_EXPECT_NDP_RECEPTION = 10 /* 0xa */, |
| 62 | HAL_MACRX_FREEZE_CAPTURE_CHANNEL = 11 /* 0xb */, |
| 63 | HAL_MACRX_NDP_TIMEOUT = 12 /* 0xc */, |
| 64 | HAL_MACRX_ABORT_ACK = 13 /* 0xd */, |
| 65 | HAL_MACRX_REQ_IMPLICIT_FB = 14 /* 0xe */, |
| 66 | HAL_MACRX_CHAIN_MASK = 15 /* 0xf */, |
| 67 | HAL_MACRX_NAP_USER = 16 /* 0x10 */, |
| 68 | HAL_MACRX_ABORT_REQUEST = 17 /* 0x11 */, |
| 69 | HAL_PHYTX_OTHER_TRANSMIT_INFO16 = 18 /* 0x12 */, |
| 70 | HAL_PHYTX_ABORT_ACK = 19 /* 0x13 */, |
| 71 | HAL_PHYTX_ABORT_REQUEST = 20 /* 0x14 */, |
| 72 | HAL_PHYTX_PKT_END = 21 /* 0x15 */, |
| 73 | HAL_PHYTX_PPDU_HEADER_INFO_REQUEST = 22 /* 0x16 */, |
| 74 | HAL_PHYTX_REQUEST_CTRL_INFO = 23 /* 0x17 */, |
| 75 | HAL_PHYTX_DATA_REQUEST = 24 /* 0x18 */, |
| 76 | HAL_PHYTX_BF_CV_LOADING_DONE = 25 /* 0x19 */, |
| 77 | HAL_PHYTX_NAP_ACK = 26 /* 0x1a */, |
| 78 | HAL_PHYTX_NAP_DONE = 27 /* 0x1b */, |
| 79 | HAL_PHYTX_OFF_ACK = 28 /* 0x1c */, |
| 80 | HAL_PHYTX_ON_ACK = 29 /* 0x1d */, |
| 81 | HAL_PHYTX_SYNTH_OFF_ACK = 30 /* 0x1e */, |
| 82 | HAL_PHYTX_DEBUG16 = 31 /* 0x1f */, |
| 83 | HAL_MACTX_ABORT_REQUEST = 32 /* 0x20 */, |
| 84 | HAL_MACTX_ABORT_ACK = 33 /* 0x21 */, |
| 85 | HAL_MACTX_PKT_END = 34 /* 0x22 */, |
| 86 | HAL_MACTX_PRE_PHY_DESC = 35 /* 0x23 */, |
| 87 | HAL_MACTX_BF_PARAMS_COMMON = 36 /* 0x24 */, |
| 88 | HAL_MACTX_BF_PARAMS_PER_USER = 37 /* 0x25 */, |
| 89 | HAL_MACTX_PREFETCH_CV = 38 /* 0x26 */, |
| 90 | HAL_MACTX_USER_DESC_COMMON = 39 /* 0x27 */, |
| 91 | HAL_MACTX_USER_DESC_PER_USER = 40 /* 0x28 */, |
| 92 | HAL_EXAMPLE_USER_TLV_16 = 41 /* 0x29 */, |
| 93 | HAL_EXAMPLE_TLV_16 = 42 /* 0x2a */, |
| 94 | HAL_MACTX_PHY_OFF = 43 /* 0x2b */, |
| 95 | HAL_MACTX_PHY_ON = 44 /* 0x2c */, |
| 96 | HAL_MACTX_SYNTH_OFF = 45 /* 0x2d */, |
| 97 | HAL_MACTX_EXPECT_CBF_COMMON = 46 /* 0x2e */, |
| 98 | HAL_MACTX_EXPECT_CBF_PER_USER = 47 /* 0x2f */, |
| 99 | HAL_MACTX_PHY_DESC = 48 /* 0x30 */, |
| 100 | HAL_MACTX_L_SIG_A = 49 /* 0x31 */, |
| 101 | HAL_MACTX_L_SIG_B = 50 /* 0x32 */, |
| 102 | HAL_MACTX_HT_SIG = 51 /* 0x33 */, |
| 103 | HAL_MACTX_VHT_SIG_A = 52 /* 0x34 */, |
| 104 | HAL_MACTX_VHT_SIG_B_SU20 = 53 /* 0x35 */, |
| 105 | HAL_MACTX_VHT_SIG_B_SU40 = 54 /* 0x36 */, |
| 106 | HAL_MACTX_VHT_SIG_B_SU80 = 55 /* 0x37 */, |
| 107 | HAL_MACTX_VHT_SIG_B_SU160 = 56 /* 0x38 */, |
| 108 | HAL_MACTX_VHT_SIG_B_MU20 = 57 /* 0x39 */, |
| 109 | HAL_MACTX_VHT_SIG_B_MU40 = 58 /* 0x3a */, |
| 110 | HAL_MACTX_VHT_SIG_B_MU80 = 59 /* 0x3b */, |
| 111 | HAL_MACTX_VHT_SIG_B_MU160 = 60 /* 0x3c */, |
| 112 | HAL_MACTX_SERVICE = 61 /* 0x3d */, |
| 113 | HAL_MACTX_HE_SIG_A_SU = 62 /* 0x3e */, |
| 114 | HAL_MACTX_HE_SIG_A_MU_DL = 63 /* 0x3f */, |
| 115 | HAL_MACTX_HE_SIG_A_MU_UL = 64 /* 0x40 */, |
| 116 | HAL_MACTX_HE_SIG_B1_MU = 65 /* 0x41 */, |
| 117 | HAL_MACTX_HE_SIG_B2_MU = 66 /* 0x42 */, |
| 118 | HAL_MACTX_HE_SIG_B2_OFDMA = 67 /* 0x43 */, |
| 119 | HAL_MACTX_DELETE_CV = 68 /* 0x44 */, |
| 120 | HAL_MACTX_MU_UPLINK_COMMON = 69 /* 0x45 */, |
| 121 | HAL_MACTX_MU_UPLINK_USER_SETUP = 70 /* 0x46 */, |
| 122 | HAL_MACTX_OTHER_TRANSMIT_INFO = 71 /* 0x47 */, |
| 123 | HAL_MACTX_PHY_NAP = 72 /* 0x48 */, |
| 124 | HAL_MACTX_DEBUG = 73 /* 0x49 */, |
| 125 | HAL_PHYRX_ABORT_ACK = 74 /* 0x4a */, |
| 126 | HAL_PHYRX_GENERATED_CBF_DETAILS = 75 /* 0x4b */, |
| 127 | HAL_PHYRX_RSSI_LEGACY = 76 /* 0x4c */, |
| 128 | HAL_PHYRX_RSSI_HT = 77 /* 0x4d */, |
| 129 | HAL_PHYRX_USER_INFO = 78 /* 0x4e */, |
| 130 | HAL_PHYRX_PKT_END = 79 /* 0x4f */, |
| 131 | HAL_PHYRX_DEBUG = 80 /* 0x50 */, |
| 132 | HAL_PHYRX_CBF_TRANSFER_DONE = 81 /* 0x51 */, |
| 133 | HAL_PHYRX_CBF_TRANSFER_ABORT = 82 /* 0x52 */, |
| 134 | HAL_PHYRX_L_SIG_A = 83 /* 0x53 */, |
| 135 | HAL_PHYRX_L_SIG_B = 84 /* 0x54 */, |
| 136 | HAL_PHYRX_HT_SIG = 85 /* 0x55 */, |
| 137 | HAL_PHYRX_VHT_SIG_A = 86 /* 0x56 */, |
| 138 | HAL_PHYRX_VHT_SIG_B_SU20 = 87 /* 0x57 */, |
| 139 | HAL_PHYRX_VHT_SIG_B_SU40 = 88 /* 0x58 */, |
| 140 | HAL_PHYRX_VHT_SIG_B_SU80 = 89 /* 0x59 */, |
| 141 | HAL_PHYRX_VHT_SIG_B_SU160 = 90 /* 0x5a */, |
| 142 | HAL_PHYRX_VHT_SIG_B_MU20 = 91 /* 0x5b */, |
| 143 | HAL_PHYRX_VHT_SIG_B_MU40 = 92 /* 0x5c */, |
| 144 | HAL_PHYRX_VHT_SIG_B_MU80 = 93 /* 0x5d */, |
| 145 | HAL_PHYRX_VHT_SIG_B_MU160 = 94 /* 0x5e */, |
| 146 | HAL_PHYRX_HE_SIG_A_SU = 95 /* 0x5f */, |
| 147 | HAL_PHYRX_HE_SIG_A_MU_DL = 96 /* 0x60 */, |
| 148 | HAL_PHYRX_HE_SIG_A_MU_UL = 97 /* 0x61 */, |
| 149 | HAL_PHYRX_HE_SIG_B1_MU = 98 /* 0x62 */, |
| 150 | HAL_PHYRX_HE_SIG_B2_MU = 99 /* 0x63 */, |
| 151 | HAL_PHYRX_HE_SIG_B2_OFDMA = 100 /* 0x64 */, |
| 152 | HAL_PHYRX_OTHER_RECEIVE_INFO = 101 /* 0x65 */, |
| 153 | HAL_PHYRX_COMMON_USER_INFO = 102 /* 0x66 */, |
| 154 | HAL_PHYRX_DATA_DONE = 103 /* 0x67 */, |
| 155 | HAL_RECEIVE_RSSI_INFO = 104 /* 0x68 */, |
| 156 | HAL_RECEIVE_USER_INFO = 105 /* 0x69 */, |
| 157 | HAL_MIMO_CONTROL_INFO = 106 /* 0x6a */, |
| 158 | HAL_RX_LOCATION_INFO = 107 /* 0x6b */, |
| 159 | HAL_COEX_TX_REQ = 108 /* 0x6c */, |
| 160 | HAL_DUMMY = 109 /* 0x6d */, |
| 161 | HAL_RX_TIMING_OFFSET_INFO = 110 /* 0x6e */, |
| 162 | HAL_EXAMPLE_TLV_32_NAME = 111 /* 0x6f */, |
| 163 | HAL_MPDU_LIMIT = 112 /* 0x70 */, |
| 164 | HAL_NA_LENGTH_END = 113 /* 0x71 */, |
| 165 | HAL_OLE_BUF_STATUS = 114 /* 0x72 */, |
| 166 | HAL_PCU_PPDU_SETUP_DONE = 115 /* 0x73 */, |
| 167 | HAL_PCU_PPDU_SETUP_END = 116 /* 0x74 */, |
| 168 | HAL_PCU_PPDU_SETUP_INIT = 117 /* 0x75 */, |
| 169 | HAL_PCU_PPDU_SETUP_START = 118 /* 0x76 */, |
| 170 | HAL_PDG_FES_SETUP = 119 /* 0x77 */, |
| 171 | HAL_PDG_RESPONSE = 120 /* 0x78 */, |
| 172 | HAL_PDG_TX_REQ = 121 /* 0x79 */, |
| 173 | HAL_SCH_WAIT_INSTR = 122 /* 0x7a */, |
| 174 | HAL_SCHEDULER_TLV = 123 /* 0x7b */, |
| 175 | HAL_TQM_FLOW_EMPTY_STATUS = 124 /* 0x7c */, |
| 176 | HAL_TQM_FLOW_NOT_EMPTY_STATUS = 125 /* 0x7d */, |
| 177 | HAL_TQM_GEN_MPDU_LENGTH_LIST = 126 /* 0x7e */, |
| 178 | HAL_TQM_GEN_MPDU_LENGTH_LIST_STATUS = 127 /* 0x7f */, |
| 179 | HAL_TQM_GEN_MPDUS = 128 /* 0x80 */, |
| 180 | HAL_TQM_GEN_MPDUS_STATUS = 129 /* 0x81 */, |
| 181 | HAL_TQM_REMOVE_MPDU = 130 /* 0x82 */, |
| 182 | HAL_TQM_REMOVE_MPDU_STATUS = 131 /* 0x83 */, |
| 183 | HAL_TQM_REMOVE_MSDU = 132 /* 0x84 */, |
| 184 | HAL_TQM_REMOVE_MSDU_STATUS = 133 /* 0x85 */, |
| 185 | HAL_TQM_UPDATE_TX_MPDU_COUNT = 134 /* 0x86 */, |
| 186 | HAL_TQM_WRITE_CMD = 135 /* 0x87 */, |
| 187 | HAL_OFDMA_TRIGGER_DETAILS = 136 /* 0x88 */, |
| 188 | HAL_TX_DATA = 137 /* 0x89 */, |
| 189 | HAL_TX_FES_SETUP = 138 /* 0x8a */, |
| 190 | HAL_RX_PACKET = 139 /* 0x8b */, |
| 191 | HAL_EXPECTED_RESPONSE = 140 /* 0x8c */, |
| 192 | HAL_TX_MPDU_END = 141 /* 0x8d */, |
| 193 | HAL_TX_MPDU_START = 142 /* 0x8e */, |
| 194 | HAL_TX_MSDU_END = 143 /* 0x8f */, |
| 195 | HAL_TX_MSDU_START = 144 /* 0x90 */, |
| 196 | HAL_TX_SW_MODE_SETUP = 145 /* 0x91 */, |
| 197 | HAL_TXPCU_BUFFER_STATUS = 146 /* 0x92 */, |
| 198 | HAL_TXPCU_USER_BUFFER_STATUS = 147 /* 0x93 */, |
| 199 | HAL_DATA_TO_TIME_CONFIG = 148 /* 0x94 */, |
| 200 | HAL_EXAMPLE_USER_TLV_32 = 149 /* 0x95 */, |
| 201 | HAL_MPDU_INFO = 150 /* 0x96 */, |
| 202 | HAL_PDG_USER_SETUP = 151 /* 0x97 */, |
| 203 | HAL_TX_11AH_SETUP = 152 /* 0x98 */, |
| 204 | HAL_REO_UPDATE_RX_REO_QUEUE_STATUS = 153 /* 0x99 */, |
| 205 | HAL_TX_PEER_ENTRY = 154 /* 0x9a */, |
| 206 | HAL_TX_RAW_OR_NATIVE_FRAME_SETUP = 155 /* 0x9b */, |
| 207 | HAL_EXAMPLE_STRUCT_NAME = 156 /* 0x9c */, |
| 208 | HAL_PCU_PPDU_SETUP_END_INFO = 157 /* 0x9d */, |
| 209 | HAL_PPDU_RATE_SETTING = 158 /* 0x9e */, |
| 210 | HAL_PROT_RATE_SETTING = 159 /* 0x9f */, |
| 211 | HAL_RX_MPDU_DETAILS = 160 /* 0xa0 */, |
| 212 | HAL_EXAMPLE_USER_TLV_42 = 161 /* 0xa1 */, |
| 213 | HAL_RX_MSDU_LINK = 162 /* 0xa2 */, |
| 214 | HAL_RX_REO_QUEUE = 163 /* 0xa3 */, |
| 215 | HAL_ADDR_SEARCH_ENTRY = 164 /* 0xa4 */, |
| 216 | HAL_SCHEDULER_CMD = 165 /* 0xa5 */, |
| 217 | HAL_TX_FLUSH = 166 /* 0xa6 */, |
| 218 | HAL_TQM_ENTRANCE_RING = 167 /* 0xa7 */, |
| 219 | HAL_TX_DATA_WORD = 168 /* 0xa8 */, |
| 220 | HAL_TX_MPDU_DETAILS = 169 /* 0xa9 */, |
| 221 | HAL_TX_MPDU_LINK = 170 /* 0xaa */, |
| 222 | HAL_TX_MPDU_LINK_PTR = 171 /* 0xab */, |
| 223 | HAL_TX_MPDU_QUEUE_HEAD = 172 /* 0xac */, |
| 224 | HAL_TX_MPDU_QUEUE_EXT = 173 /* 0xad */, |
| 225 | HAL_TX_MPDU_QUEUE_EXT_PTR = 174 /* 0xae */, |
| 226 | HAL_TX_MSDU_DETAILS = 175 /* 0xaf */, |
| 227 | HAL_TX_MSDU_EXTENSION = 176 /* 0xb0 */, |
| 228 | HAL_TX_MSDU_FLOW = 177 /* 0xb1 */, |
| 229 | HAL_TX_MSDU_LINK = 178 /* 0xb2 */, |
| 230 | HAL_TX_MSDU_LINK_ENTRY_PTR = 179 /* 0xb3 */, |
| 231 | HAL_RESPONSE_RATE_SETTING = 180 /* 0xb4 */, |
| 232 | HAL_TXPCU_BUFFER_BASICS = 181 /* 0xb5 */, |
| 233 | HAL_UNIFORM_DESCRIPTOR_HEADER = 182 /* 0xb6 */, |
| 234 | HAL_UNIFORM_TQM_CMD_HEADER = 183 /* 0xb7 */, |
| 235 | HAL_UNIFORM_TQM_STATUS_HEADER = 184 /* 0xb8 */, |
| 236 | HAL_USER_RATE_SETTING = 185 /* 0xb9 */, |
| 237 | HAL_WBM_BUFFER_RING = 186 /* 0xba */, |
| 238 | HAL_WBM_LINK_DESCRIPTOR_RING = 187 /* 0xbb */, |
| 239 | HAL_WBM_RELEASE_RING = 188 /* 0xbc */, |
| 240 | HAL_TX_FLUSH_REQ = 189 /* 0xbd */, |
| 241 | HAL_RX_MSDU_DETAILS = 190 /* 0xbe */, |
| 242 | HAL_TQM_WRITE_CMD_STATUS = 191 /* 0xbf */, |
| 243 | HAL_TQM_GET_MPDU_QUEUE_STATS = 192 /* 0xc0 */, |
| 244 | HAL_TQM_GET_MSDU_FLOW_STATS = 193 /* 0xc1 */, |
| 245 | HAL_EXAMPLE_USER_CTLV_32 = 194 /* 0xc2 */, |
| 246 | HAL_TX_FES_STATUS_START = 195 /* 0xc3 */, |
| 247 | HAL_TX_FES_STATUS_USER_PPDU = 196 /* 0xc4 */, |
| 248 | HAL_TX_FES_STATUS_USER_RESPONSE = 197 /* 0xc5 */, |
| 249 | HAL_TX_FES_STATUS_END = 198 /* 0xc6 */, |
| 250 | HAL_RX_TRIG_INFO = 199 /* 0xc7 */, |
| 251 | HAL_RXPCU_TX_SETUP_CLEAR = 200 /* 0xc8 */, |
| 252 | HAL_RX_FRAME_BITMAP_REQ = 201 /* 0xc9 */, |
| 253 | HAL_RX_FRAME_BITMAP_ACK = 202 /* 0xca */, |
| 254 | HAL_COEX_RX_STATUS = 203 /* 0xcb */, |
| 255 | HAL_RX_START_PARAM = 204 /* 0xcc */, |
| 256 | HAL_RX_PPDU_START = 205 /* 0xcd */, |
| 257 | HAL_RX_PPDU_END = 206 /* 0xce */, |
| 258 | HAL_RX_MPDU_START = 207 /* 0xcf */, |
| 259 | HAL_RX_MPDU_END = 208 /* 0xd0 */, |
| 260 | HAL_RX_MSDU_START = 209 /* 0xd1 */, |
| 261 | HAL_RX_MSDU_END = 210 /* 0xd2 */, |
| 262 | HAL_RX_ATTENTION = 211 /* 0xd3 */, |
| 263 | HAL_RECEIVED_RESPONSE_INFO = 212 /* 0xd4 */, |
| 264 | HAL_RX_PHY_SLEEP = 213 /* 0xd5 */, |
| 265 | HAL_RX_HEADER = 214 /* 0xd6 */, |
| 266 | HAL_RX_PEER_ENTRY = 215 /* 0xd7 */, |
| 267 | HAL_RX_FLUSH = 216 /* 0xd8 */, |
| 268 | HAL_RX_RESPONSE_REQUIRED_INFO = 217 /* 0xd9 */, |
| 269 | HAL_RX_FRAMELESS_BAR_DETAILS = 218 /* 0xda */, |
| 270 | HAL_TQM_GET_MPDU_QUEUE_STATS_STATUS = 219 /* 0xdb */, |
| 271 | HAL_TQM_GET_MSDU_FLOW_STATS_STATUS = 220 /* 0xdc */, |
| 272 | HAL_TX_CBF_INFO = 221 /* 0xdd */, |
| 273 | HAL_PCU_PPDU_SETUP_USER = 222 /* 0xde */, |
| 274 | HAL_RX_MPDU_PCU_START = 223 /* 0xdf */, |
| 275 | HAL_RX_PM_INFO = 224 /* 0xe0 */, |
| 276 | HAL_RX_USER_PPDU_END = 225 /* 0xe1 */, |
| 277 | HAL_RX_PRE_PPDU_START = 226 /* 0xe2 */, |
| 278 | HAL_RX_PREAMBLE = 227 /* 0xe3 */, |
| 279 | HAL_TX_FES_SETUP_COMPLETE = 228 /* 0xe4 */, |
| 280 | HAL_TX_LAST_MPDU_FETCHED = 229 /* 0xe5 */, |
| 281 | HAL_TXDMA_STOP_REQUEST = 230 /* 0xe6 */, |
| 282 | HAL_RXPCU_SETUP = 231 /* 0xe7 */, |
| 283 | HAL_RXPCU_USER_SETUP = 232 /* 0xe8 */, |
| 284 | HAL_TX_FES_STATUS_ACK_OR_BA = 233 /* 0xe9 */, |
| 285 | HAL_TQM_ACKED_MPDU = 234 /* 0xea */, |
| 286 | HAL_COEX_TX_RESP = 235 /* 0xeb */, |
| 287 | HAL_COEX_TX_STATUS = 236 /* 0xec */, |
| 288 | HAL_MACTX_COEX_PHY_CTRL = 237 /* 0xed */, |
| 289 | HAL_COEX_STATUS_BROADCAST = 238 /* 0xee */, |
| 290 | HAL_RESPONSE_START_STATUS = 239 /* 0xef */, |
| 291 | HAL_RESPONSE_END_STATUS = 240 /* 0xf0 */, |
| 292 | HAL_CRYPTO_STATUS = 241 /* 0xf1 */, |
| 293 | HAL_RECEIVED_TRIGGER_INFO = 242 /* 0xf2 */, |
| 294 | HAL_REO_ENTRANCE_RING = 243 /* 0xf3 */, |
| 295 | HAL_RX_MPDU_LINK = 244 /* 0xf4 */, |
| 296 | HAL_COEX_TX_STOP_CTRL = 245 /* 0xf5 */, |
| 297 | HAL_RX_PPDU_ACK_REPORT = 246 /* 0xf6 */, |
| 298 | HAL_RX_PPDU_NO_ACK_REPORT = 247 /* 0xf7 */, |
| 299 | HAL_SCH_COEX_STATUS = 248 /* 0xf8 */, |
| 300 | HAL_SCHEDULER_COMMAND_STATUS = 249 /* 0xf9 */, |
| 301 | HAL_SCHEDULER_RX_PPDU_NO_RESPONSE_STATUS = 250 /* 0xfa */, |
| 302 | HAL_TX_FES_STATUS_PROT = 251 /* 0xfb */, |
| 303 | HAL_TX_FES_STATUS_START_PPDU = 252 /* 0xfc */, |
| 304 | HAL_TX_FES_STATUS_START_PROT = 253 /* 0xfd */, |
| 305 | HAL_TXPCU_PHYTX_DEBUG32 = 254 /* 0xfe */, |
| 306 | HAL_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 = 255 /* 0xff */, |
| 307 | HAL_TX_MPDU_COUNT_TRANSFER_END = 256 /* 0x100 */, |
| 308 | HAL_WHO_ANCHOR_OFFSET = 257 /* 0x101 */, |
| 309 | HAL_WHO_ANCHOR_VALUE = 258 /* 0x102 */, |
| 310 | HAL_WHO_CCE_INFO = 259 /* 0x103 */, |
| 311 | HAL_WHO_COMMIT = 260 /* 0x104 */, |
| 312 | HAL_WHO_COMMIT_DONE = 261 /* 0x105 */, |
| 313 | HAL_WHO_FLUSH = 262 /* 0x106 */, |
| 314 | HAL_WHO_L2_LLC = 263 /* 0x107 */, |
| 315 | HAL_WHO_L2_PAYLOAD = 264 /* 0x108 */, |
| 316 | HAL_WHO_L3_CHECKSUM = 265 /* 0x109 */, |
| 317 | HAL_WHO_L3_INFO = 266 /* 0x10a */, |
| 318 | HAL_WHO_L4_CHECKSUM = 267 /* 0x10b */, |
| 319 | HAL_WHO_L4_INFO = 268 /* 0x10c */, |
| 320 | HAL_WHO_MSDU = 269 /* 0x10d */, |
| 321 | HAL_WHO_MSDU_MISC = 270 /* 0x10e */, |
| 322 | HAL_WHO_PACKET_DATA = 271 /* 0x10f */, |
| 323 | HAL_WHO_PACKET_HDR = 272 /* 0x110 */, |
| 324 | HAL_WHO_PPDU_END = 273 /* 0x111 */, |
| 325 | HAL_WHO_PPDU_START = 274 /* 0x112 */, |
| 326 | HAL_WHO_TSO = 275 /* 0x113 */, |
| 327 | HAL_WHO_WMAC_HEADER_PV0 = 276 /* 0x114 */, |
| 328 | HAL_WHO_WMAC_HEADER_PV1 = 277 /* 0x115 */, |
| 329 | HAL_WHO_WMAC_IV = 278 /* 0x116 */, |
| 330 | HAL_MPDU_INFO_END = 279 /* 0x117 */, |
| 331 | HAL_MPDU_INFO_BITMAP = 280 /* 0x118 */, |
| 332 | HAL_TX_QUEUE_EXTENSION = 281 /* 0x119 */, |
| 333 | HAL_RX_PEER_ENTRY_DETAILS = 282 /* 0x11a */, |
| 334 | HAL_RX_REO_QUEUE_REFERENCE = 283 /* 0x11b */, |
| 335 | HAL_RX_REO_QUEUE_EXT = 284 /* 0x11c */, |
| 336 | HAL_SCHEDULER_SELFGEN_RESPONSE_STATUS = 285 /* 0x11d */, |
| 337 | HAL_TQM_UPDATE_TX_MPDU_COUNT_STATUS = 286 /* 0x11e */, |
| 338 | HAL_TQM_ACKED_MPDU_STATUS = 287 /* 0x11f */, |
| 339 | HAL_TQM_ADD_MSDU_STATUS = 288 /* 0x120 */, |
| 340 | HAL_RX_MPDU_LINK_PTR = 289 /* 0x121 */, |
| 341 | HAL_REO_DESTINATION_RING = 290 /* 0x122 */, |
| 342 | HAL_TQM_LIST_GEN_DONE = 291 /* 0x123 */, |
| 343 | HAL_WHO_TERMINATE = 292 /* 0x124 */, |
| 344 | HAL_TX_LAST_MPDU_END = 293 /* 0x125 */, |
| 345 | HAL_TX_CV_DATA = 294 /* 0x126 */, |
| 346 | HAL_TCL_ENTRANCE_FROM_PPE_RING = 295 /* 0x127 */, |
| 347 | HAL_PPDU_TX_END = 296 /* 0x128 */, |
| 348 | HAL_PROT_TX_END = 297 /* 0x129 */, |
| 349 | HAL_PDG_RESPONSE_RATE_SETTING = 298 /* 0x12a */, |
| 350 | HAL_MPDU_INFO_GLOBAL_END = 299 /* 0x12b */, |
| 351 | HAL_TQM_SCH_INSTR_GLOBAL_END = 300 /* 0x12c */, |
| 352 | HAL_RX_PPDU_END_USER_STATS = 301 /* 0x12d */, |
| 353 | HAL_RX_PPDU_END_USER_STATS_EXT = 302 /* 0x12e */, |
| 354 | HAL_NO_ACK_REPORT = 303 /* 0x12f */, |
| 355 | HAL_ACK_REPORT = 304 /* 0x130 */, |
| 356 | HAL_UNIFORM_REO_CMD_HEADER = 305 /* 0x131 */, |
| 357 | HAL_REO_GET_QUEUE_STATS = 306 /* 0x132 */, |
| 358 | HAL_REO_FLUSH_QUEUE = 307 /* 0x133 */, |
| 359 | HAL_REO_FLUSH_CACHE = 308 /* 0x134 */, |
| 360 | HAL_REO_UNBLOCK_CACHE = 309 /* 0x135 */, |
| 361 | HAL_UNIFORM_REO_STATUS_HEADER = 310 /* 0x136 */, |
| 362 | HAL_REO_GET_QUEUE_STATS_STATUS = 311 /* 0x137 */, |
| 363 | HAL_REO_FLUSH_QUEUE_STATUS = 312 /* 0x138 */, |
| 364 | HAL_REO_FLUSH_CACHE_STATUS = 313 /* 0x139 */, |
| 365 | HAL_REO_UNBLOCK_CACHE_STATUS = 314 /* 0x13a */, |
| 366 | HAL_TQM_FLUSH_CACHE = 315 /* 0x13b */, |
| 367 | HAL_TQM_UNBLOCK_CACHE = 316 /* 0x13c */, |
| 368 | HAL_TQM_FLUSH_CACHE_STATUS = 317 /* 0x13d */, |
| 369 | HAL_TQM_UNBLOCK_CACHE_STATUS = 318 /* 0x13e */, |
| 370 | HAL_RX_PPDU_END_STATUS_DONE = 319 /* 0x13f */, |
| 371 | HAL_RX_STATUS_BUFFER_DONE = 320 /* 0x140 */, |
| 372 | HAL_BUFFER_ADDR_INFO = 321 /* 0x141 */, |
| 373 | HAL_RX_MSDU_DESC_INFO = 322 /* 0x142 */, |
| 374 | HAL_RX_MPDU_DESC_INFO = 323 /* 0x143 */, |
| 375 | HAL_TCL_DATA_CMD = 324 /* 0x144 */, |
| 376 | HAL_TCL_GSE_CMD = 325 /* 0x145 */, |
| 377 | HAL_TCL_EXIT_BASE = 326 /* 0x146 */, |
| 378 | HAL_TCL_COMPACT_EXIT_RING = 327 /* 0x147 */, |
| 379 | HAL_TCL_REGULAR_EXIT_RING = 328 /* 0x148 */, |
| 380 | HAL_TCL_EXTENDED_EXIT_RING = 329 /* 0x149 */, |
| 381 | HAL_UPLINK_COMMON_INFO = 330 /* 0x14a */, |
| 382 | HAL_UPLINK_USER_SETUP_INFO = 331 /* 0x14b */, |
| 383 | HAL_TX_DATA_SYNC = 332 /* 0x14c */, |
| 384 | HAL_PHYRX_CBF_READ_REQUEST_ACK = 333 /* 0x14d */, |
| 385 | HAL_TCL_STATUS_RING = 334 /* 0x14e */, |
| 386 | HAL_TQM_GET_MPDU_HEAD_INFO = 335 /* 0x14f */, |
| 387 | HAL_TQM_SYNC_CMD = 336 /* 0x150 */, |
| 388 | HAL_TQM_GET_MPDU_HEAD_INFO_STATUS = 337 /* 0x151 */, |
| 389 | HAL_TQM_SYNC_CMD_STATUS = 338 /* 0x152 */, |
| 390 | HAL_TQM_THRESHOLD_DROP_NOTIFICATION_STATUS = 339 /* 0x153 */, |
| 391 | HAL_TQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 340 /* 0x154 */, |
| 392 | HAL_REO_FLUSH_TIMEOUT_LIST = 341 /* 0x155 */, |
| 393 | HAL_REO_FLUSH_TIMEOUT_LIST_STATUS = 342 /* 0x156 */, |
| 394 | HAL_REO_TO_PPE_RING = 343 /* 0x157 */, |
| 395 | HAL_RX_MPDU_INFO = 344 /* 0x158 */, |
| 396 | HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 345 /* 0x159 */, |
| 397 | HAL_SCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS = 346 /* 0x15a */, |
| 398 | HAL_EXAMPLE_USER_TLV_32_NAME = 347 /* 0x15b */, |
| 399 | HAL_RX_PPDU_START_USER_INFO = 348 /* 0x15c */, |
| 400 | HAL_RX_RXPCU_CLASSIFICATION_OVERVIEW = 349 /* 0x15d */, |
| 401 | HAL_RX_RING_MASK = 350 /* 0x15e */, |
| 402 | HAL_WHO_CLASSIFY_INFO = 351 /* 0x15f */, |
| 403 | HAL_TXPT_CLASSIFY_INFO = 352 /* 0x160 */, |
| 404 | HAL_RXPT_CLASSIFY_INFO = 353 /* 0x161 */, |
| 405 | HAL_TX_FLOW_SEARCH_ENTRY = 354 /* 0x162 */, |
| 406 | HAL_RX_FLOW_SEARCH_ENTRY = 355 /* 0x163 */, |
| 407 | HAL_RECEIVED_TRIGGER_INFO_DETAILS = 356 /* 0x164 */, |
| 408 | HAL_COEX_MAC_NAP = 357 /* 0x165 */, |
| 409 | HAL_MACRX_ABORT_REQUEST_INFO = 358 /* 0x166 */, |
| 410 | HAL_MACTX_ABORT_REQUEST_INFO = 359 /* 0x167 */, |
| 411 | HAL_PHYRX_ABORT_REQUEST_INFO = 360 /* 0x168 */, |
| 412 | HAL_PHYTX_ABORT_REQUEST_INFO = 361 /* 0x169 */, |
| 413 | HAL_RXPCU_PPDU_END_INFO = 362 /* 0x16a */, |
| 414 | HAL_WHO_MESH_CONTROL = 363 /* 0x16b */, |
| 415 | HAL_L_SIG_A_INFO = 364 /* 0x16c */, |
| 416 | HAL_L_SIG_B_INFO = 365 /* 0x16d */, |
| 417 | HAL_HT_SIG_INFO = 366 /* 0x16e */, |
| 418 | HAL_VHT_SIG_A_INFO = 367 /* 0x16f */, |
| 419 | HAL_VHT_SIG_B_SU20_INFO = 368 /* 0x170 */, |
| 420 | HAL_VHT_SIG_B_SU40_INFO = 369 /* 0x171 */, |
| 421 | HAL_VHT_SIG_B_SU80_INFO = 370 /* 0x172 */, |
| 422 | HAL_VHT_SIG_B_SU160_INFO = 371 /* 0x173 */, |
| 423 | HAL_VHT_SIG_B_MU20_INFO = 372 /* 0x174 */, |
| 424 | HAL_VHT_SIG_B_MU40_INFO = 373 /* 0x175 */, |
| 425 | HAL_VHT_SIG_B_MU80_INFO = 374 /* 0x176 */, |
| 426 | HAL_VHT_SIG_B_MU160_INFO = 375 /* 0x177 */, |
| 427 | HAL_SERVICE_INFO = 376 /* 0x178 */, |
| 428 | HAL_HE_SIG_A_SU_INFO = 377 /* 0x179 */, |
| 429 | HAL_HE_SIG_A_MU_DL_INFO = 378 /* 0x17a */, |
| 430 | HAL_HE_SIG_A_MU_UL_INFO = 379 /* 0x17b */, |
| 431 | HAL_HE_SIG_B1_MU_INFO = 380 /* 0x17c */, |
| 432 | HAL_HE_SIG_B2_MU_INFO = 381 /* 0x17d */, |
| 433 | HAL_HE_SIG_B2_OFDMA_INFO = 382 /* 0x17e */, |
| 434 | HAL_PDG_SW_MODE_BW_START = 383 /* 0x17f */, |
| 435 | HAL_PDG_SW_MODE_BW_END = 384 /* 0x180 */, |
| 436 | HAL_PDG_WAIT_FOR_MAC_REQUEST = 385 /* 0x181 */, |
| 437 | HAL_PDG_WAIT_FOR_PHY_REQUEST = 386 /* 0x182 */, |
| 438 | HAL_SCHEDULER_END = 387 /* 0x183 */, |
| 439 | HAL_PEER_TABLE_ENTRY = 388 /* 0x184 */, |
| 440 | HAL_SW_PEER_INFO = 389 /* 0x185 */, |
| 441 | HAL_RXOLE_CCE_CLASSIFY_INFO = 390 /* 0x186 */, |
| 442 | HAL_TCL_CCE_CLASSIFY_INFO = 391 /* 0x187 */, |
| 443 | HAL_RXOLE_CCE_INFO = 392 /* 0x188 */, |
| 444 | HAL_TCL_CCE_INFO = 393 /* 0x189 */, |
| 445 | HAL_TCL_CCE_SUPERRULE = 394 /* 0x18a */, |
| 446 | HAL_CCE_RULE = 395 /* 0x18b */, |
| 447 | HAL_RX_PPDU_START_DROPPED = 396 /* 0x18c */, |
| 448 | HAL_RX_PPDU_END_DROPPED = 397 /* 0x18d */, |
| 449 | HAL_RX_PPDU_END_STATUS_DONE_DROPPED = 398 /* 0x18e */, |
| 450 | HAL_RX_MPDU_START_DROPPED = 399 /* 0x18f */, |
| 451 | HAL_RX_MSDU_START_DROPPED = 400 /* 0x190 */, |
| 452 | HAL_RX_MSDU_END_DROPPED = 401 /* 0x191 */, |
| 453 | HAL_RX_MPDU_END_DROPPED = 402 /* 0x192 */, |
| 454 | HAL_RX_ATTENTION_DROPPED = 403 /* 0x193 */, |
| 455 | HAL_TXPCU_USER_SETUP = 404 /* 0x194 */, |
| 456 | HAL_RXPCU_USER_SETUP_EXT = 405 /* 0x195 */, |
| 457 | HAL_CE_SRC_DESC = 406 /* 0x196 */, |
| 458 | HAL_CE_STAT_DESC = 407 /* 0x197 */, |
| 459 | HAL_RXOLE_CCE_SUPERRULE = 408 /* 0x198 */, |
| 460 | HAL_TX_RATE_STATS_INFO = 409 /* 0x199 */, |
| 461 | HAL_CMD_PART_0_END = 410 /* 0x19a */, |
| 462 | HAL_MACTX_SYNTH_ON = 411 /* 0x19b */, |
| 463 | HAL_SCH_CRITICAL_TLV_REFERENCE = 412 /* 0x19c */, |
| 464 | HAL_TQM_MPDU_GLOBAL_START = 413 /* 0x19d */, |
| 465 | HAL_EXAMPLE_TLV_32 = 414 /* 0x19e */, |
| 466 | HAL_TQM_UPDATE_TX_MSDU_FLOW = 415 /* 0x19f */, |
| 467 | HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD = 416 /* 0x1a0 */, |
| 468 | HAL_TQM_UPDATE_TX_MSDU_FLOW_STATUS = 417 /* 0x1a1 */, |
| 469 | HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS = 418 /* 0x1a2 */, |
| 470 | HAL_REO_UPDATE_RX_REO_QUEUE = 419 /* 0x1a3 */, |
| 471 | HAL_CE_DST_DESC = 420 /* 0x1a4 */, |
| 472 | HAL_RX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS = 455 /* 0x1c7 */, |
| 473 | HAL_TLV_BASE = 511 /* 0x1ff */, |
| 474 | }; |
| 475 | |
| 476 | #define HAL_TLV_HDR_TAG GENMASK(9, 1) |
| 477 | #define HAL_TLV_HDR_LEN GENMASK(25, 10) |
| 478 | #define HAL_TLV_USR_ID GENMASK(31, 26) |
| 479 | |
| 480 | #define HAL_TLV_ALIGN 4 |
| 481 | |
| 482 | struct hal_tlv_hdr { |
| 483 | u32 tl; |
| 484 | u8 value[]; |
| 485 | } __packed; |
| 486 | |
| 487 | #define RX_MPDU_DESC_INFO0_MSDU_COUNT GENMASK(7, 0) |
| 488 | #define RX_MPDU_DESC_INFO0_SEQ_NUM GENMASK(19, 8) |
| 489 | #define RX_MPDU_DESC_INFO0_FRAG_FLAG BIT(20) |
| 490 | #define RX_MPDU_DESC_INFO0_MPDU_RETRY BIT(21) |
| 491 | #define RX_MPDU_DESC_INFO0_AMPDU_FLAG BIT(22) |
| 492 | #define RX_MPDU_DESC_INFO0_BAR_FRAME BIT(23) |
| 493 | #define RX_MPDU_DESC_INFO0_VALID_PN BIT(24) |
| 494 | #define RX_MPDU_DESC_INFO0_VALID_SA BIT(25) |
| 495 | #define RX_MPDU_DESC_INFO0_SA_IDX_TIMEOUT BIT(26) |
| 496 | #define RX_MPDU_DESC_INFO0_VALID_DA BIT(27) |
| 497 | #define RX_MPDU_DESC_INFO0_DA_MCBC BIT(28) |
| 498 | #define RX_MPDU_DESC_INFO0_DA_IDX_TIMEOUT BIT(29) |
| 499 | #define RX_MPDU_DESC_INFO0_RAW_MPDU BIT(30) |
| 500 | |
| 501 | #define RX_MPDU_DESC_META_DATA_PEER_ID GENMASK(15, 0) |
| 502 | |
| 503 | struct rx_mpdu_desc { |
| 504 | u32 info0; /* %RX_MPDU_DESC_INFO */ |
| 505 | u32 meta_data; |
| 506 | } __packed; |
| 507 | |
| 508 | /* rx_mpdu_desc |
| 509 | * Producer: RXDMA |
| 510 | * Consumer: REO/SW/FW |
| 511 | * |
| 512 | * msdu_count |
| 513 | * The number of MSDUs within the MPDU |
| 514 | * |
| 515 | * mpdu_sequence_number |
| 516 | * The field can have two different meanings based on the setting |
| 517 | * of field 'bar_frame'. If 'bar_frame' is set, it means the MPDU |
| 518 | * start sequence number from the BAR frame otherwise it means |
| 519 | * the MPDU sequence number of the received frame. |
| 520 | * |
| 521 | * fragment_flag |
| 522 | * When set, this MPDU is a fragment and REO should forward this |
| 523 | * fragment MPDU to the REO destination ring without any reorder |
| 524 | * checks, pn checks or bitmap update. This implies that REO is |
| 525 | * forwarding the pointer to the MSDU link descriptor. |
| 526 | * |
| 527 | * mpdu_retry_bit |
| 528 | * The retry bit setting from the MPDU header of the received frame |
| 529 | * |
| 530 | * ampdu_flag |
| 531 | * Indicates the MPDU was received as part of an A-MPDU. |
| 532 | * |
| 533 | * bar_frame |
| 534 | * Indicates the received frame is a BAR frame. After processing, |
| 535 | * this frame shall be pushed to SW or deleted. |
| 536 | * |
| 537 | * valid_pn |
| 538 | * When not set, REO will not perform a PN sequence number check. |
| 539 | * |
| 540 | * valid_sa |
| 541 | * Indicates OLE found a valid SA entry for all MSDUs in this MPDU. |
| 542 | * |
| 543 | * sa_idx_timeout |
| 544 | * Indicates, at least 1 MSDU within the MPDU has an unsuccessful |
| 545 | * MAC source address search due to the expiration of search timer. |
| 546 | * |
| 547 | * valid_da |
| 548 | * When set, OLE found a valid DA entry for all MSDUs in this MPDU. |
| 549 | * |
| 550 | * da_mcbc |
| 551 | * Field Only valid if valid_da is set. Indicates at least one of |
| 552 | * the DA addresses is a Multicast or Broadcast address. |
| 553 | * |
| 554 | * da_idx_timeout |
| 555 | * Indicates, at least 1 MSDU within the MPDU has an unsuccessful |
| 556 | * MAC destination address search due to the expiration of search |
| 557 | * timer. |
| 558 | * |
| 559 | * raw_mpdu |
| 560 | * Field only valid when first_msdu_in_mpdu_flag is set. Indicates |
| 561 | * the contents in the MSDU buffer contains a 'RAW' MPDU. |
| 562 | */ |
| 563 | |
| 564 | enum hal_rx_msdu_desc_reo_dest_ind { |
| 565 | HAL_RX_MSDU_DESC_REO_DEST_IND_TCL, |
| 566 | HAL_RX_MSDU_DESC_REO_DEST_IND_SW1, |
| 567 | HAL_RX_MSDU_DESC_REO_DEST_IND_SW2, |
| 568 | HAL_RX_MSDU_DESC_REO_DEST_IND_SW3, |
| 569 | HAL_RX_MSDU_DESC_REO_DEST_IND_SW4, |
| 570 | HAL_RX_MSDU_DESC_REO_DEST_IND_RELEASE, |
| 571 | HAL_RX_MSDU_DESC_REO_DEST_IND_FW, |
| 572 | }; |
| 573 | |
| 574 | #define RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU BIT(0) |
| 575 | #define RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU BIT(1) |
| 576 | #define RX_MSDU_DESC_INFO0_MSDU_CONTINUATION BIT(2) |
| 577 | #define RX_MSDU_DESC_INFO0_MSDU_LENGTH GENMASK(16, 3) |
| 578 | #define RX_MSDU_DESC_INFO0_REO_DEST_IND GENMASK(21, 17) |
| 579 | #define RX_MSDU_DESC_INFO0_MSDU_DROP BIT(22) |
| 580 | #define RX_MSDU_DESC_INFO0_VALID_SA BIT(23) |
| 581 | #define RX_MSDU_DESC_INFO0_SA_IDX_TIMEOUT BIT(24) |
| 582 | #define RX_MSDU_DESC_INFO0_VALID_DA BIT(25) |
| 583 | #define RX_MSDU_DESC_INFO0_DA_MCBC BIT(26) |
| 584 | #define RX_MSDU_DESC_INFO0_DA_IDX_TIMEOUT BIT(27) |
| 585 | |
| 586 | #define HAL_RX_MSDU_PKT_LENGTH_GET(val) \ |
| 587 | (FIELD_GET(RX_MSDU_DESC_INFO0_MSDU_LENGTH, (val))) |
| 588 | |
| 589 | struct rx_msdu_desc { |
| 590 | u32 info0; |
| 591 | u32 rsvd0; |
| 592 | } __packed; |
| 593 | |
| 594 | /* rx_msdu_desc |
| 595 | * |
| 596 | * first_msdu_in_mpdu |
| 597 | * Indicates first msdu in mpdu. |
| 598 | * |
| 599 | * last_msdu_in_mpdu |
| 600 | * Indicates last msdu in mpdu. This flag can be true only when |
| 601 | * 'Msdu_continuation' set to 0. This implies that when an msdu |
| 602 | * is spread out over multiple buffers and thus msdu_continuation |
| 603 | * is set, only for the very last buffer of the msdu, can the |
| 604 | * 'last_msdu_in_mpdu' be set. |
| 605 | * |
| 606 | * When both first_msdu_in_mpdu and last_msdu_in_mpdu are set, |
| 607 | * the MPDU that this MSDU belongs to only contains a single MSDU. |
| 608 | * |
| 609 | * msdu_continuation |
| 610 | * When set, this MSDU buffer was not able to hold the entire MSDU. |
| 611 | * The next buffer will therefor contain additional information |
| 612 | * related to this MSDU. |
| 613 | * |
| 614 | * msdu_length |
| 615 | * Field is only valid in combination with the 'first_msdu_in_mpdu' |
| 616 | * being set. Full MSDU length in bytes after decapsulation. This |
| 617 | * field is still valid for MPDU frames without A-MSDU. It still |
| 618 | * represents MSDU length after decapsulation Or in case of RAW |
| 619 | * MPDUs, it indicates the length of the entire MPDU (without FCS |
| 620 | * field). |
| 621 | * |
| 622 | * reo_destination_indication |
| 623 | * The id of the reo exit ring where the msdu frame shall push |
| 624 | * after (MPDU level) reordering has finished. Values are defined |
| 625 | * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_. |
| 626 | * |
| 627 | * msdu_drop |
| 628 | * Indicates that REO shall drop this MSDU and not forward it to |
| 629 | * any other ring. |
| 630 | * |
| 631 | * valid_sa |
| 632 | * Indicates OLE found a valid SA entry for this MSDU. |
| 633 | * |
| 634 | * sa_idx_timeout |
| 635 | * Indicates, an unsuccessful MAC source address search due to |
| 636 | * the expiration of search timer for this MSDU. |
| 637 | * |
| 638 | * valid_da |
| 639 | * When set, OLE found a valid DA entry for this MSDU. |
| 640 | * |
| 641 | * da_mcbc |
| 642 | * Field Only valid if valid_da is set. Indicates the DA address |
| 643 | * is a Multicast or Broadcast address for this MSDU. |
| 644 | * |
| 645 | * da_idx_timeout |
| 646 | * Indicates, an unsuccessful MAC destination address search due |
| 647 | * to the expiration of search timer fot this MSDU. |
| 648 | */ |
| 649 | |
| 650 | enum hal_reo_dest_ring_buffer_type { |
| 651 | HAL_REO_DEST_RING_BUFFER_TYPE_MSDU, |
| 652 | HAL_REO_DEST_RING_BUFFER_TYPE_LINK_DESC, |
| 653 | }; |
| 654 | |
| 655 | enum hal_reo_dest_ring_push_reason { |
| 656 | HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED, |
| 657 | HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION, |
| 658 | }; |
| 659 | |
| 660 | enum hal_reo_dest_ring_error_code { |
| 661 | HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO, |
| 662 | HAL_REO_DEST_RING_ERROR_CODE_DESC_INVALID, |
| 663 | HAL_REO_DEST_RING_ERROR_CODE_AMPDU_IN_NON_BA, |
| 664 | HAL_REO_DEST_RING_ERROR_CODE_NON_BA_DUPLICATE, |
| 665 | HAL_REO_DEST_RING_ERROR_CODE_BA_DUPLICATE, |
| 666 | HAL_REO_DEST_RING_ERROR_CODE_FRAME_2K_JUMP, |
| 667 | HAL_REO_DEST_RING_ERROR_CODE_BAR_2K_JUMP, |
| 668 | HAL_REO_DEST_RING_ERROR_CODE_FRAME_OOR, |
| 669 | HAL_REO_DEST_RING_ERROR_CODE_BAR_OOR, |
| 670 | HAL_REO_DEST_RING_ERROR_CODE_NO_BA_SESSION, |
| 671 | HAL_REO_DEST_RING_ERROR_CODE_FRAME_SN_EQUALS_SSN, |
| 672 | HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED, |
| 673 | HAL_REO_DEST_RING_ERROR_CODE_2K_ERR_FLAG_SET, |
| 674 | HAL_REO_DEST_RING_ERROR_CODE_PN_ERR_FLAG_SET, |
| 675 | HAL_REO_DEST_RING_ERROR_CODE_DESC_BLOCKED, |
| 676 | HAL_REO_DEST_RING_ERROR_CODE_MAX, |
| 677 | }; |
| 678 | |
| 679 | #define HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) |
| 680 | #define HAL_REO_DEST_RING_INFO0_BUFFER_TYPE BIT(8) |
| 681 | #define HAL_REO_DEST_RING_INFO0_PUSH_REASON GENMASK(10, 9) |
| 682 | #define HAL_REO_DEST_RING_INFO0_ERROR_CODE GENMASK(15, 11) |
| 683 | #define HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM GENMASK(31, 16) |
| 684 | |
| 685 | #define HAL_REO_DEST_RING_INFO1_REORDER_INFO_VALID BIT(0) |
| 686 | #define HAL_REO_DEST_RING_INFO1_REORDER_OPCODE GENMASK(4, 1) |
| 687 | #define HAL_REO_DEST_RING_INFO1_REORDER_SLOT_IDX GENMASK(12, 5) |
| 688 | |
| 689 | #define HAL_REO_DEST_RING_INFO2_RING_ID GENMASK(27, 20) |
| 690 | #define HAL_REO_DEST_RING_INFO2_LOOPING_COUNT GENMASK(31, 28) |
| 691 | |
| 692 | struct hal_reo_dest_ring { |
| 693 | struct ath11k_buffer_addr buf_addr_info; |
| 694 | struct rx_mpdu_desc rx_mpdu_info; |
| 695 | struct rx_msdu_desc rx_msdu_info; |
| 696 | u32 queue_addr_lo; |
| 697 | u32 info0; /* %HAL_REO_DEST_RING_INFO0_ */ |
| 698 | u32 info1; /* %HAL_REO_DEST_RING_INFO1_ */ |
| 699 | u32 rsvd0; |
| 700 | u32 rsvd1; |
| 701 | u32 rsvd2; |
| 702 | u32 rsvd3; |
| 703 | u32 rsvd4; |
| 704 | u32 rsvd5; |
| 705 | u32 info2; /* %HAL_REO_DEST_RING_INFO2_ */ |
| 706 | } __packed; |
| 707 | |
| 708 | /* hal_reo_dest_ring |
| 709 | * |
| 710 | * Producer: RXDMA |
| 711 | * Consumer: REO/SW/FW |
| 712 | * |
| 713 | * buf_addr_info |
| 714 | * Details of the physical address of a buffer or MSDU |
| 715 | * link descriptor. |
| 716 | * |
| 717 | * rx_mpdu_info |
| 718 | * General information related to the MPDU that is passed |
| 719 | * on from REO entrance ring to the REO destination ring. |
| 720 | * |
| 721 | * rx_msdu_info |
| 722 | * General information related to the MSDU that is passed |
| 723 | * on from RXDMA all the way to the REO destination ring. |
| 724 | * |
| 725 | * queue_addr_lo |
| 726 | * Address (lower 32 bits) of the REO queue descriptor. |
| 727 | * |
| 728 | * queue_addr_hi |
| 729 | * Address (upper 8 bits) of the REO queue descriptor. |
| 730 | * |
| 731 | * buffer_type |
| 732 | * Indicates the type of address provided in the buf_addr_info. |
| 733 | * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_. |
| 734 | * |
| 735 | * push_reason |
| 736 | * Reason for pushing this frame to this exit ring. Values are |
| 737 | * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. |
| 738 | * |
| 739 | * error_code |
| 740 | * Valid only when 'push_reason' is set. All error codes are |
| 741 | * defined in enum %HAL_REO_DEST_RING_ERROR_CODE_. |
| 742 | * |
| 743 | * rx_queue_num |
| 744 | * Indicates the REO MPDU reorder queue id from which this frame |
| 745 | * originated. |
| 746 | * |
| 747 | * reorder_info_valid |
| 748 | * When set, REO has been instructed to not perform the actual |
| 749 | * re-ordering of frames for this queue, but just to insert |
| 750 | * the reorder opcodes. |
| 751 | * |
| 752 | * reorder_opcode |
| 753 | * Field is valid when 'reorder_info_valid' is set. This field is |
| 754 | * always valid for debug purpose as well. |
| 755 | * |
| 756 | * reorder_slot_idx |
| 757 | * Valid only when 'reorder_info_valid' is set. |
| 758 | * |
| 759 | * ring_id |
| 760 | * The buffer pointer ring id. |
| 761 | * 0 - Idle ring |
| 762 | * 1 - N refers to other rings. |
| 763 | * |
| 764 | * looping_count |
| 765 | * Indicates the number of times the producer of entries into |
| 766 | * this ring has looped around the ring. |
| 767 | */ |
| 768 | |
| 769 | enum hal_reo_entr_rxdma_ecode { |
| 770 | HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR, |
| 771 | HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR, |
| 772 | HAL_REO_ENTR_RING_RXDMA_ECODE_FCS_ERR, |
| 773 | HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR, |
| 774 | HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR, |
| 775 | HAL_REO_ENTR_RING_RXDMA_ECODE_UNECRYPTED_ERR, |
| 776 | HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LEN_ERR, |
| 777 | HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LIMIT_ERR, |
| 778 | HAL_REO_ENTR_RING_RXDMA_ECODE_WIFI_PARSE_ERR, |
| 779 | HAL_REO_ENTR_RING_RXDMA_ECODE_AMSDU_PARSE_ERR, |
| 780 | HAL_REO_ENTR_RING_RXDMA_ECODE_SA_TIMEOUT_ERR, |
| 781 | HAL_REO_ENTR_RING_RXDMA_ECODE_DA_TIMEOUT_ERR, |
| 782 | HAL_REO_ENTR_RING_RXDMA_ECODE_FLOW_TIMEOUT_ERR, |
| 783 | HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR, |
| 784 | HAL_REO_ENTR_RING_RXDMA_ECODE_MAX, |
| 785 | }; |
| 786 | |
| 787 | #define HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) |
| 788 | #define HAL_REO_ENTR_RING_INFO0_MPDU_BYTE_COUNT GENMASK(21, 8) |
| 789 | #define HAL_REO_ENTR_RING_INFO0_DEST_IND GENMASK(26, 22) |
| 790 | #define HAL_REO_ENTR_RING_INFO0_FRAMELESS_BAR BIT(27) |
| 791 | |
| 792 | #define HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON GENMASK(1, 0) |
| 793 | #define HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE GENMASK(6, 2) |
| 794 | |
| 795 | struct hal_reo_entrance_ring { |
| 796 | struct ath11k_buffer_addr buf_addr_info; |
| 797 | struct rx_mpdu_desc rx_mpdu_info; |
| 798 | u32 queue_addr_lo; |
| 799 | u32 info0; /* %HAL_REO_ENTR_RING_INFO0_ */ |
| 800 | u32 info1; /* %HAL_REO_ENTR_RING_INFO1_ */ |
| 801 | u32 info2; /* %HAL_REO_DEST_RING_INFO2_ */ |
| 802 | |
| 803 | } __packed; |
| 804 | |
| 805 | /* hal_reo_entrance_ring |
| 806 | * |
| 807 | * Producer: RXDMA |
| 808 | * Consumer: REO |
| 809 | * |
| 810 | * buf_addr_info |
| 811 | * Details of the physical address of a buffer or MSDU |
| 812 | * link descriptor. |
| 813 | * |
| 814 | * rx_mpdu_info |
| 815 | * General information related to the MPDU that is passed |
| 816 | * on from REO entrance ring to the REO destination ring. |
| 817 | * |
| 818 | * queue_addr_lo |
| 819 | * Address (lower 32 bits) of the REO queue descriptor. |
| 820 | * |
| 821 | * queue_addr_hi |
| 822 | * Address (upper 8 bits) of the REO queue descriptor. |
| 823 | * |
| 824 | * mpdu_byte_count |
| 825 | * An approximation of the number of bytes received in this MPDU. |
| 826 | * Used to keeps stats on the amount of data flowing |
| 827 | * through a queue. |
| 828 | * |
| 829 | * reo_destination_indication |
| 830 | * The id of the reo exit ring where the msdu frame shall push |
| 831 | * after (MPDU level) reordering has finished. Values are defined |
| 832 | * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_. |
| 833 | * |
| 834 | * frameless_bar |
| 835 | * Indicates that this REO entrance ring struct contains BAR info |
| 836 | * from a multi TID BAR frame. The original multi TID BAR frame |
| 837 | * itself contained all the REO info for the first TID, but all |
| 838 | * the subsequent TID info and their linkage to the REO descriptors |
| 839 | * is passed down as 'frameless' BAR info. |
| 840 | * |
| 841 | * The only fields valid in this descriptor when this bit is set |
| 842 | * are queue_addr_lo, queue_addr_hi, mpdu_sequence_number, |
| 843 | * bar_frame and peer_meta_data. |
| 844 | * |
| 845 | * rxdma_push_reason |
| 846 | * Reason for pushing this frame to this exit ring. Values are |
| 847 | * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. |
| 848 | * |
| 849 | * rxdma_error_code |
| 850 | * Valid only when 'push_reason' is set. All error codes are |
| 851 | * defined in enum %HAL_REO_ENTR_RING_RXDMA_ECODE_. |
| 852 | * |
| 853 | * ring_id |
| 854 | * The buffer pointer ring id. |
| 855 | * 0 - Idle ring |
| 856 | * 1 - N refers to other rings. |
| 857 | * |
| 858 | * looping_count |
| 859 | * Indicates the number of times the producer of entries into |
| 860 | * this ring has looped around the ring. |
| 861 | */ |
| 862 | |
| 863 | #define HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON GENMASK(1, 0) |
| 864 | #define HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE GENMASK(6, 2) |
| 865 | #define HAL_SW_MON_RING_INFO0_MPDU_FRAG_NUMBER GENMASK(10, 7) |
| 866 | #define HAL_SW_MON_RING_INFO0_FRAMELESS_BAR BIT(11) |
| 867 | #define HAL_SW_MON_RING_INFO0_STATUS_BUF_CNT GENMASK(15, 12) |
| 868 | #define HAL_SW_MON_RING_INFO0_END_OF_PPDU BIT(16) |
| 869 | |
| 870 | #define HAL_SW_MON_RING_INFO1_PHY_PPDU_ID GENMASK(15, 0) |
| 871 | #define HAL_SW_MON_RING_INFO1_RING_ID GENMASK(27, 20) |
| 872 | #define HAL_SW_MON_RING_INFO1_LOOPING_COUNT GENMASK(31, 28) |
| 873 | |
| 874 | struct hal_sw_monitor_ring { |
| 875 | struct ath11k_buffer_addr buf_addr_info; |
| 876 | struct rx_mpdu_desc rx_mpdu_info; |
| 877 | struct ath11k_buffer_addr status_buf_addr_info; |
| 878 | u32 info0; |
| 879 | u32 info1; |
| 880 | } __packed; |
| 881 | |
| 882 | #define HAL_REO_CMD_HDR_INFO0_CMD_NUMBER GENMASK(15, 0) |
| 883 | #define HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED BIT(16) |
| 884 | |
| 885 | struct hal_reo_cmd_hdr { |
| 886 | u32 info0; |
| 887 | } __packed; |
| 888 | |
| 889 | #define HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) |
| 890 | #define HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS BIT(8) |
| 891 | |
| 892 | struct hal_reo_get_queue_stats { |
| 893 | struct hal_reo_cmd_hdr cmd; |
| 894 | u32 queue_addr_lo; |
| 895 | u32 info0; |
| 896 | u32 rsvd0[6]; |
| 897 | } __packed; |
| 898 | |
| 899 | /* hal_reo_get_queue_stats |
| 900 | * Producer: SW |
| 901 | * Consumer: REO |
| 902 | * |
| 903 | * cmd |
| 904 | * Details for command execution tracking purposes. |
| 905 | * |
| 906 | * queue_addr_lo |
| 907 | * Address (lower 32 bits) of the REO queue descriptor. |
| 908 | * |
| 909 | * queue_addr_hi |
| 910 | * Address (upper 8 bits) of the REO queue descriptor. |
| 911 | * |
| 912 | * clear_stats |
| 913 | * Clear stats settings. When set, Clear the stats after |
| 914 | * generating the status. |
| 915 | * |
| 916 | * Following stats will be cleared. |
| 917 | * Timeout_count |
| 918 | * Forward_due_to_bar_count |
| 919 | * Duplicate_count |
| 920 | * Frames_in_order_count |
| 921 | * BAR_received_count |
| 922 | * MPDU_Frames_processed_count |
| 923 | * MSDU_Frames_processed_count |
| 924 | * Total_processed_byte_count |
| 925 | * Late_receive_MPDU_count |
| 926 | * window_jump_2k |
| 927 | * Hole_count |
| 928 | */ |
| 929 | |
| 930 | #define HAL_REO_FLUSH_QUEUE_INFO0_DESC_ADDR_HI GENMASK(7, 0) |
| 931 | #define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_DESC_ADDR BIT(8) |
| 932 | #define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_RESRC_IDX GENMASK(10, 9) |
| 933 | |
| 934 | struct hal_reo_flush_queue { |
| 935 | struct hal_reo_cmd_hdr cmd; |
| 936 | u32 desc_addr_lo; |
| 937 | u32 info0; |
| 938 | u32 rsvd0[6]; |
| 939 | } __packed; |
| 940 | |
| 941 | #define HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI GENMASK(7, 0) |
| 942 | #define HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS BIT(8) |
| 943 | #define HAL_REO_FLUSH_CACHE_INFO0_RELEASE_BLOCK_IDX BIT(9) |
| 944 | #define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX GENMASK(11, 10) |
| 945 | #define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE BIT(12) |
| 946 | #define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE BIT(13) |
| 947 | #define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL BIT(14) |
| 948 | |
| 949 | struct hal_reo_flush_cache { |
| 950 | struct hal_reo_cmd_hdr cmd; |
| 951 | u32 cache_addr_lo; |
| 952 | u32 info0; |
| 953 | u32 rsvd0[6]; |
| 954 | } __packed; |
| 955 | |
| 956 | #define TX_IP_CHECKSUM HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN | \ |
| 957 | HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN | \ |
| 958 | HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN | \ |
| 959 | HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN | \ |
| 960 | HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN |
| 961 | |
| 962 | #define HAL_TCL_DATA_CMD_INFO0_DESC_TYPE BIT(0) |
| 963 | #define HAL_TCL_DATA_CMD_INFO0_EPD BIT(1) |
| 964 | #define HAL_TCL_DATA_CMD_INFO0_ENCAP_TYPE GENMASK(3, 2) |
| 965 | #define HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE GENMASK(7, 4) |
| 966 | #define HAL_TCL_DATA_CMD_INFO0_SRC_BUF_SWAP BIT(8) |
| 967 | #define HAL_TCL_DATA_CMD_INFO0_LNK_META_SWAP BIT(9) |
| 968 | #define HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE GENMASK(13, 12) |
| 969 | #define HAL_TCL_DATA_CMD_INFO0_ADDR_EN GENMASK(15, 14) |
| 970 | #define HAL_TCL_DATA_CMD_INFO0_CMD_NUM GENMASK(31, 16) |
| 971 | |
| 972 | #define HAL_TCL_DATA_CMD_INFO1_DATA_LEN GENMASK(15, 0) |
| 973 | #define HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN BIT(16) |
| 974 | #define HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN BIT(17) |
| 975 | #define HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN BIT(18) |
| 976 | #define HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN BIT(19) |
| 977 | #define HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN BIT(20) |
| 978 | #define HAL_TCL_DATA_CMD_INFO1_TO_FW BIT(21) |
| 979 | #define HAL_TCL_DATA_CMD_INFO1_PKT_OFFSET GENMASK(31, 23) |
| 980 | |
| 981 | #define HAL_TCL_DATA_CMD_INFO2_BUF_TIMESTAMP GENMASK(18, 0) |
| 982 | #define HAL_TCL_DATA_CMD_INFO2_BUF_T_VALID BIT(19) |
| 983 | #define HAL_IPQ8074_TCL_DATA_CMD_INFO2_MESH_ENABLE BIT(20) |
| 984 | #define HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE BIT(21) |
| 985 | #define HAL_TCL_DATA_CMD_INFO2_TID GENMASK(25, 22) |
| 986 | #define HAL_TCL_DATA_CMD_INFO2_LMAC_ID GENMASK(27, 26) |
| 987 | |
| 988 | #define HAL_TCL_DATA_CMD_INFO3_DSCP_TID_TABLE_IDX GENMASK(5, 0) |
| 989 | #define HAL_TCL_DATA_CMD_INFO3_SEARCH_INDEX GENMASK(25, 6) |
| 990 | #define HAL_TCL_DATA_CMD_INFO3_CACHE_SET_NUM GENMASK(29, 26) |
| 991 | #define HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE GENMASK(31, 30) |
| 992 | |
| 993 | #define HAL_TCL_DATA_CMD_INFO4_RING_ID GENMASK(27, 20) |
| 994 | #define HAL_TCL_DATA_CMD_INFO4_LOOPING_COUNT GENMASK(31, 28) |
| 995 | |
| 996 | enum hal_encrypt_type { |
| 997 | HAL_ENCRYPT_TYPE_WEP_40, |
| 998 | HAL_ENCRYPT_TYPE_WEP_104, |
| 999 | HAL_ENCRYPT_TYPE_TKIP_NO_MIC, |
| 1000 | HAL_ENCRYPT_TYPE_WEP_128, |
| 1001 | HAL_ENCRYPT_TYPE_TKIP_MIC, |
| 1002 | HAL_ENCRYPT_TYPE_WAPI, |
| 1003 | HAL_ENCRYPT_TYPE_CCMP_128, |
| 1004 | HAL_ENCRYPT_TYPE_OPEN, |
| 1005 | HAL_ENCRYPT_TYPE_CCMP_256, |
| 1006 | HAL_ENCRYPT_TYPE_GCMP_128, |
| 1007 | HAL_ENCRYPT_TYPE_AES_GCMP_256, |
| 1008 | HAL_ENCRYPT_TYPE_WAPI_GCM_SM4, |
| 1009 | }; |
| 1010 | |
| 1011 | enum hal_tcl_encap_type { |
| 1012 | HAL_TCL_ENCAP_TYPE_RAW, |
| 1013 | HAL_TCL_ENCAP_TYPE_NATIVE_WIFI, |
| 1014 | HAL_TCL_ENCAP_TYPE_ETHERNET, |
| 1015 | HAL_TCL_ENCAP_TYPE_802_3 = 3, |
| 1016 | }; |
| 1017 | |
| 1018 | enum hal_tcl_desc_type { |
| 1019 | HAL_TCL_DESC_TYPE_BUFFER, |
| 1020 | HAL_TCL_DESC_TYPE_EXT_DESC, |
| 1021 | }; |
| 1022 | |
| 1023 | enum hal_wbm_htt_tx_comp_status { |
| 1024 | HAL_WBM_REL_HTT_TX_COMP_STATUS_OK, |
| 1025 | HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP, |
| 1026 | HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL, |
| 1027 | HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ, |
| 1028 | HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT, |
| 1029 | HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY, |
| 1030 | HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX |
| 1031 | }; |
| 1032 | |
| 1033 | struct hal_tcl_data_cmd { |
| 1034 | struct ath11k_buffer_addr buf_addr_info; |
| 1035 | u32 info0; |
| 1036 | u32 info1; |
| 1037 | u32 info2; |
| 1038 | u32 info3; |
| 1039 | u32 info4; |
| 1040 | } __packed; |
| 1041 | |
| 1042 | /* hal_tcl_data_cmd |
| 1043 | * |
| 1044 | * buf_addr_info |
| 1045 | * Details of the physical address of a buffer or MSDU |
| 1046 | * link descriptor. |
| 1047 | * |
| 1048 | * desc_type |
| 1049 | * Indicates the type of address provided in the buf_addr_info. |
| 1050 | * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_. |
| 1051 | * |
| 1052 | * epd |
| 1053 | * When this bit is set then input packet is an EPD type. |
| 1054 | * |
| 1055 | * encap_type |
| 1056 | * Indicates the encapsulation that HW will perform. Values are |
| 1057 | * defined in enum %HAL_TCL_ENCAP_TYPE_. |
| 1058 | * |
| 1059 | * encrypt_type |
| 1060 | * Field only valid for encap_type: RAW |
| 1061 | * Values are defined in enum %HAL_ENCRYPT_TYPE_. |
| 1062 | * |
| 1063 | * src_buffer_swap |
| 1064 | * Treats source memory (packet buffer) organization as big-endian. |
| 1065 | * 1'b0: Source memory is little endian |
| 1066 | * 1'b1: Source memory is big endian |
| 1067 | * |
| 1068 | * link_meta_swap |
| 1069 | * Treats link descriptor and Metadata as big-endian. |
| 1070 | * 1'b0: memory is little endian |
| 1071 | * 1'b1: memory is big endian |
| 1072 | * |
| 1073 | * search_type |
| 1074 | * Search type select |
| 1075 | * 0 - Normal search, 1 - Index based address search, |
| 1076 | * 2 - Index based flow search |
| 1077 | * |
| 1078 | * addrx_en |
| 1079 | * addry_en |
| 1080 | * Address X/Y search enable in ASE correspondingly. |
| 1081 | * 1'b0: Search disable |
| 1082 | * 1'b1: Search Enable |
| 1083 | * |
| 1084 | * cmd_num |
| 1085 | * This number can be used to match against status. |
| 1086 | * |
| 1087 | * data_length |
| 1088 | * MSDU length in case of direct descriptor. Length of link |
| 1089 | * extension descriptor in case of Link extension descriptor. |
| 1090 | * |
| 1091 | * *_checksum_en |
| 1092 | * Enable checksum replacement for ipv4, udp_over_ipv4, ipv6, |
| 1093 | * udp_over_ipv6, tcp_over_ipv4 and tcp_over_ipv6. |
| 1094 | * |
| 1095 | * to_fw |
| 1096 | * Forward packet to FW along with classification result. The |
| 1097 | * packet will not be forward to TQM when this bit is set. |
| 1098 | * 1'b0: Use classification result to forward the packet. |
| 1099 | * 1'b1: Override classification result & forward packet only to fw |
| 1100 | * |
| 1101 | * packet_offset |
| 1102 | * Packet offset from Metadata in case of direct buffer descriptor. |
| 1103 | * |
| 1104 | * buffer_timestamp |
| 1105 | * buffer_timestamp_valid |
| 1106 | * Frame system entrance timestamp. It shall be filled by first |
| 1107 | * module (SW, TCL or TQM) that sees the frames first. |
| 1108 | * |
| 1109 | * mesh_enable |
| 1110 | * For raw WiFi frames, this indicates transmission to a mesh STA, |
| 1111 | * enabling the interpretation of the 'Mesh Control Present' bit |
| 1112 | * (bit 8) of QoS Control. |
| 1113 | * For native WiFi frames, this indicates that a 'Mesh Control' |
| 1114 | * field is present between the header and the LLC. |
| 1115 | * |
| 1116 | * hlos_tid_overwrite |
| 1117 | * |
| 1118 | * When set, TCL shall ignore the IP DSCP and VLAN PCP |
| 1119 | * fields and use HLOS_TID as the final TID. Otherwise TCL |
| 1120 | * shall consider the DSCP and PCP fields as well as HLOS_TID |
| 1121 | * and choose a final TID based on the configured priority |
| 1122 | * |
| 1123 | * hlos_tid |
| 1124 | * HLOS MSDU priority |
| 1125 | * Field is used when HLOS_TID_overwrite is set. |
| 1126 | * |
| 1127 | * lmac_id |
| 1128 | * TCL uses this LMAC_ID in address search, i.e, while |
| 1129 | * finding matching entry for the packet in AST corresponding |
| 1130 | * to given LMAC_ID |
| 1131 | * |
| 1132 | * If LMAC ID is all 1s (=> value 3), it indicates wildcard |
| 1133 | * match for any MAC |
| 1134 | * |
| 1135 | * dscp_tid_table_num |
| 1136 | * DSCP to TID mapping table number that need to be used |
| 1137 | * for the MSDU. |
| 1138 | * |
| 1139 | * search_index |
| 1140 | * The index that will be used for index based address or |
| 1141 | * flow search. The field is valid when 'search_type' is 1 or 2. |
| 1142 | * |
| 1143 | * cache_set_num |
| 1144 | * |
| 1145 | * Cache set number that should be used to cache the index |
| 1146 | * based search results, for address and flow search. This |
| 1147 | * value should be equal to LSB four bits of the hash value of |
| 1148 | * match data, in case of search index points to an entry which |
| 1149 | * may be used in content based search also. The value can be |
| 1150 | * anything when the entry pointed by search index will not be |
| 1151 | * used for content based search. |
| 1152 | * |
| 1153 | * ring_id |
| 1154 | * The buffer pointer ring ID. |
| 1155 | * 0 refers to the IDLE ring |
| 1156 | * 1 - N refers to other rings |
| 1157 | * |
| 1158 | * looping_count |
| 1159 | * |
| 1160 | * A count value that indicates the number of times the |
| 1161 | * producer of entries into the Ring has looped around the |
| 1162 | * ring. |
| 1163 | * |
| 1164 | * At initialization time, this value is set to 0. On the |
| 1165 | * first loop, this value is set to 1. After the max value is |
| 1166 | * reached allowed by the number of bits for this field, the |
| 1167 | * count value continues with 0 again. |
| 1168 | * |
| 1169 | * In case SW is the consumer of the ring entries, it can |
| 1170 | * use this field to figure out up to where the producer of |
| 1171 | * entries has created new entries. This eliminates the need to |
| 1172 | * check where the head pointer' of the ring is located once |
| 1173 | * the SW starts processing an interrupt indicating that new |
| 1174 | * entries have been put into this ring... |
| 1175 | * |
| 1176 | * Also note that SW if it wants only needs to look at the |
| 1177 | * LSB bit of this count value. |
| 1178 | */ |
| 1179 | |
| 1180 | #define HAL_TCL_DESC_LEN sizeof(struct hal_tcl_data_cmd) |
| 1181 | |
| 1182 | enum hal_tcl_gse_ctrl { |
| 1183 | HAL_TCL_GSE_CTRL_RD_STAT, |
| 1184 | HAL_TCL_GSE_CTRL_SRCH_DIS, |
| 1185 | HAL_TCL_GSE_CTRL_WR_BK_SINGLE, |
| 1186 | HAL_TCL_GSE_CTRL_WR_BK_ALL, |
| 1187 | HAL_TCL_GSE_CTRL_INVAL_SINGLE, |
| 1188 | HAL_TCL_GSE_CTRL_INVAL_ALL, |
| 1189 | HAL_TCL_GSE_CTRL_WR_BK_INVAL_SINGLE, |
| 1190 | HAL_TCL_GSE_CTRL_WR_BK_INVAL_ALL, |
| 1191 | HAL_TCL_GSE_CTRL_CLR_STAT_SINGLE, |
| 1192 | }; |
| 1193 | |
| 1194 | /* hal_tcl_gse_ctrl |
| 1195 | * |
| 1196 | * rd_stat |
| 1197 | * Report or Read statistics |
| 1198 | * srch_dis |
| 1199 | * Search disable. Report only Hash. |
| 1200 | * wr_bk_single |
| 1201 | * Write Back single entry |
| 1202 | * wr_bk_all |
| 1203 | * Write Back entire cache entry |
| 1204 | * inval_single |
| 1205 | * Invalidate single cache entry |
| 1206 | * inval_all |
| 1207 | * Invalidate entire cache |
| 1208 | * wr_bk_inval_single |
| 1209 | * Write back and invalidate single entry in cache |
| 1210 | * wr_bk_inval_all |
| 1211 | * Write back and invalidate entire cache |
| 1212 | * clr_stat_single |
| 1213 | * Clear statistics for single entry |
| 1214 | */ |
| 1215 | |
| 1216 | #define HAL_TCL_GSE_CMD_INFO0_CTRL_BUF_ADDR_HI GENMASK(7, 0) |
| 1217 | #define HAL_TCL_GSE_CMD_INFO0_GSE_CTRL GENMASK(11, 8) |
| 1218 | #define HAL_TCL_GSE_CMD_INFO0_GSE_SEL BIT(12) |
| 1219 | #define HAL_TCL_GSE_CMD_INFO0_STATUS_DEST_RING_ID BIT(13) |
| 1220 | #define HAL_TCL_GSE_CMD_INFO0_SWAP BIT(14) |
| 1221 | |
| 1222 | #define HAL_TCL_GSE_CMD_INFO1_RING_ID GENMASK(27, 20) |
| 1223 | #define HAL_TCL_GSE_CMD_INFO1_LOOPING_COUNT GENMASK(31, 28) |
| 1224 | |
| 1225 | struct hal_tcl_gse_cmd { |
| 1226 | u32 ctrl_buf_addr_lo; |
| 1227 | u32 info0; |
| 1228 | u32 meta_data[2]; |
| 1229 | u32 rsvd0[2]; |
| 1230 | u32 info1; |
| 1231 | } __packed; |
| 1232 | |
| 1233 | /* hal_tcl_gse_cmd |
| 1234 | * |
| 1235 | * ctrl_buf_addr_lo, ctrl_buf_addr_hi |
| 1236 | * Address of a control buffer containing additional info needed |
| 1237 | * for this command execution. |
| 1238 | * |
| 1239 | * gse_ctrl |
| 1240 | * GSE control operations. This includes cache operations and table |
| 1241 | * entry statistics read/clear operation. Values are defined in |
| 1242 | * enum %HAL_TCL_GSE_CTRL. |
| 1243 | * |
| 1244 | * gse_sel |
| 1245 | * To select the ASE/FSE to do the operation mention by GSE_ctrl. |
| 1246 | * 0: FSE select 1: ASE select |
| 1247 | * |
| 1248 | * status_destination_ring_id |
| 1249 | * TCL status ring to which the GSE status needs to be send. |
| 1250 | * |
| 1251 | * swap |
| 1252 | * Bit to enable byte swapping of contents of buffer. |
| 1253 | * |
| 1254 | * meta_data |
| 1255 | * Meta data to be returned in the status descriptor |
| 1256 | */ |
| 1257 | |
| 1258 | enum hal_tcl_cache_op_res { |
| 1259 | HAL_TCL_CACHE_OP_RES_DONE, |
| 1260 | HAL_TCL_CACHE_OP_RES_NOT_FOUND, |
| 1261 | HAL_TCL_CACHE_OP_RES_TIMEOUT, |
| 1262 | }; |
| 1263 | |
| 1264 | #define HAL_TCL_STATUS_RING_INFO0_GSE_CTRL GENMASK(3, 0) |
| 1265 | #define HAL_TCL_STATUS_RING_INFO0_GSE_SEL BIT(4) |
| 1266 | #define HAL_TCL_STATUS_RING_INFO0_CACHE_OP_RES GENMASK(6, 5) |
| 1267 | #define HAL_TCL_STATUS_RING_INFO0_MSDU_CNT GENMASK(31, 8) |
| 1268 | |
| 1269 | #define HAL_TCL_STATUS_RING_INFO1_HASH_IDX GENMASK(19, 0) |
| 1270 | |
| 1271 | #define HAL_TCL_STATUS_RING_INFO2_RING_ID GENMASK(27, 20) |
| 1272 | #define HAL_TCL_STATUS_RING_INFO2_LOOPING_COUNT GENMASK(31, 28) |
| 1273 | |
| 1274 | struct hal_tcl_status_ring { |
| 1275 | u32 info0; |
| 1276 | u32 msdu_byte_count; |
| 1277 | u32 msdu_timestamp; |
| 1278 | u32 meta_data[2]; |
| 1279 | u32 info1; |
| 1280 | u32 rsvd0; |
| 1281 | u32 info2; |
| 1282 | } __packed; |
| 1283 | |
| 1284 | /* hal_tcl_status_ring |
| 1285 | * |
| 1286 | * gse_ctrl |
| 1287 | * GSE control operations. This includes cache operations and table |
| 1288 | * entry statistics read/clear operation. Values are defined in |
| 1289 | * enum %HAL_TCL_GSE_CTRL. |
| 1290 | * |
| 1291 | * gse_sel |
| 1292 | * To select the ASE/FSE to do the operation mention by GSE_ctrl. |
| 1293 | * 0: FSE select 1: ASE select |
| 1294 | * |
| 1295 | * cache_op_res |
| 1296 | * Cache operation result. Values are defined in enum |
| 1297 | * %HAL_TCL_CACHE_OP_RES_. |
| 1298 | * |
| 1299 | * msdu_cnt |
| 1300 | * msdu_byte_count |
| 1301 | * MSDU count of Entry and MSDU byte count for entry 1. |
| 1302 | * |
| 1303 | * hash_indx |
| 1304 | * Hash value of the entry in case of search failed or disabled. |
| 1305 | */ |
| 1306 | |
| 1307 | #define HAL_CE_SRC_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0) |
| 1308 | #define HAL_CE_SRC_DESC_ADDR_INFO_HASH_EN BIT(8) |
| 1309 | #define HAL_CE_SRC_DESC_ADDR_INFO_BYTE_SWAP BIT(9) |
| 1310 | #define HAL_CE_SRC_DESC_ADDR_INFO_DEST_SWAP BIT(10) |
| 1311 | #define HAL_CE_SRC_DESC_ADDR_INFO_GATHER BIT(11) |
| 1312 | #define HAL_CE_SRC_DESC_ADDR_INFO_LEN GENMASK(31, 16) |
| 1313 | |
| 1314 | #define HAL_CE_SRC_DESC_META_INFO_DATA GENMASK(15, 0) |
| 1315 | |
| 1316 | #define HAL_CE_SRC_DESC_FLAGS_RING_ID GENMASK(27, 20) |
| 1317 | #define HAL_CE_SRC_DESC_FLAGS_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT |
| 1318 | |
| 1319 | struct hal_ce_srng_src_desc { |
| 1320 | u32 buffer_addr_low; |
| 1321 | u32 buffer_addr_info; /* %HAL_CE_SRC_DESC_ADDR_INFO_ */ |
| 1322 | u32 meta_info; /* %HAL_CE_SRC_DESC_META_INFO_ */ |
| 1323 | u32 flags; /* %HAL_CE_SRC_DESC_FLAGS_ */ |
| 1324 | } __packed; |
| 1325 | |
| 1326 | /* |
| 1327 | * hal_ce_srng_src_desc |
| 1328 | * |
| 1329 | * buffer_addr_lo |
| 1330 | * LSB 32 bits of the 40 Bit Pointer to the source buffer |
| 1331 | * |
| 1332 | * buffer_addr_hi |
| 1333 | * MSB 8 bits of the 40 Bit Pointer to the source buffer |
| 1334 | * |
| 1335 | * toeplitz_en |
| 1336 | * Enable generation of 32-bit Toeplitz-LFSR hash for |
| 1337 | * data transfer. In case of gather field in first source |
| 1338 | * ring entry of the gather copy cycle in taken into account. |
| 1339 | * |
| 1340 | * src_swap |
| 1341 | * Treats source memory organization as big-endian. For |
| 1342 | * each dword read (4 bytes), the byte 0 is swapped with byte 3 |
| 1343 | * and byte 1 is swapped with byte 2. |
| 1344 | * In case of gather field in first source ring entry of |
| 1345 | * the gather copy cycle in taken into account. |
| 1346 | * |
| 1347 | * dest_swap |
| 1348 | * Treats destination memory organization as big-endian. |
| 1349 | * For each dword write (4 bytes), the byte 0 is swapped with |
| 1350 | * byte 3 and byte 1 is swapped with byte 2. |
| 1351 | * In case of gather field in first source ring entry of |
| 1352 | * the gather copy cycle in taken into account. |
| 1353 | * |
| 1354 | * gather |
| 1355 | * Enables gather of multiple copy engine source |
| 1356 | * descriptors to one destination. |
| 1357 | * |
| 1358 | * ce_res_0 |
| 1359 | * Reserved |
| 1360 | * |
| 1361 | * |
| 1362 | * length |
| 1363 | * Length of the buffer in units of octets of the current |
| 1364 | * descriptor |
| 1365 | * |
| 1366 | * fw_metadata |
| 1367 | * Meta data used by FW. |
| 1368 | * In case of gather field in first source ring entry of |
| 1369 | * the gather copy cycle in taken into account. |
| 1370 | * |
| 1371 | * ce_res_1 |
| 1372 | * Reserved |
| 1373 | * |
| 1374 | * ce_res_2 |
| 1375 | * Reserved |
| 1376 | * |
| 1377 | * ring_id |
| 1378 | * The buffer pointer ring ID. |
| 1379 | * 0 refers to the IDLE ring |
| 1380 | * 1 - N refers to other rings |
| 1381 | * Helps with debugging when dumping ring contents. |
| 1382 | * |
| 1383 | * looping_count |
| 1384 | * A count value that indicates the number of times the |
| 1385 | * producer of entries into the Ring has looped around the |
| 1386 | * ring. |
| 1387 | * |
| 1388 | * At initialization time, this value is set to 0. On the |
| 1389 | * first loop, this value is set to 1. After the max value is |
| 1390 | * reached allowed by the number of bits for this field, the |
| 1391 | * count value continues with 0 again. |
| 1392 | * |
| 1393 | * In case SW is the consumer of the ring entries, it can |
| 1394 | * use this field to figure out up to where the producer of |
| 1395 | * entries has created new entries. This eliminates the need to |
| 1396 | * check where the head pointer' of the ring is located once |
| 1397 | * the SW starts processing an interrupt indicating that new |
| 1398 | * entries have been put into this ring... |
| 1399 | * |
| 1400 | * Also note that SW if it wants only needs to look at the |
| 1401 | * LSB bit of this count value. |
| 1402 | */ |
| 1403 | |
| 1404 | #define HAL_CE_DEST_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0) |
| 1405 | #define HAL_CE_DEST_DESC_ADDR_INFO_RING_ID GENMASK(27, 20) |
| 1406 | #define HAL_CE_DEST_DESC_ADDR_INFO_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT |
| 1407 | |
| 1408 | struct hal_ce_srng_dest_desc { |
| 1409 | u32 buffer_addr_low; |
| 1410 | u32 buffer_addr_info; /* %HAL_CE_DEST_DESC_ADDR_INFO_ */ |
| 1411 | } __packed; |
| 1412 | |
| 1413 | /* hal_ce_srng_dest_desc |
| 1414 | * |
| 1415 | * dst_buffer_low |
| 1416 | * LSB 32 bits of the 40 Bit Pointer to the Destination |
| 1417 | * buffer |
| 1418 | * |
| 1419 | * dst_buffer_high |
| 1420 | * MSB 8 bits of the 40 Bit Pointer to the Destination |
| 1421 | * buffer |
| 1422 | * |
| 1423 | * ce_res_4 |
| 1424 | * Reserved |
| 1425 | * |
| 1426 | * ring_id |
| 1427 | * The buffer pointer ring ID. |
| 1428 | * 0 refers to the IDLE ring |
| 1429 | * 1 - N refers to other rings |
| 1430 | * Helps with debugging when dumping ring contents. |
| 1431 | * |
| 1432 | * looping_count |
| 1433 | * A count value that indicates the number of times the |
| 1434 | * producer of entries into the Ring has looped around the |
| 1435 | * ring. |
| 1436 | * |
| 1437 | * At initialization time, this value is set to 0. On the |
| 1438 | * first loop, this value is set to 1. After the max value is |
| 1439 | * reached allowed by the number of bits for this field, the |
| 1440 | * count value continues with 0 again. |
| 1441 | * |
| 1442 | * In case SW is the consumer of the ring entries, it can |
| 1443 | * use this field to figure out up to where the producer of |
| 1444 | * entries has created new entries. This eliminates the need to |
| 1445 | * check where the head pointer' of the ring is located once |
| 1446 | * the SW starts processing an interrupt indicating that new |
| 1447 | * entries have been put into this ring... |
| 1448 | * |
| 1449 | * Also note that SW if it wants only needs to look at the |
| 1450 | * LSB bit of this count value. |
| 1451 | */ |
| 1452 | |
| 1453 | #define HAL_CE_DST_STATUS_DESC_FLAGS_HASH_EN BIT(8) |
| 1454 | #define HAL_CE_DST_STATUS_DESC_FLAGS_BYTE_SWAP BIT(9) |
| 1455 | #define HAL_CE_DST_STATUS_DESC_FLAGS_DEST_SWAP BIT(10) |
| 1456 | #define HAL_CE_DST_STATUS_DESC_FLAGS_GATHER BIT(11) |
| 1457 | #define HAL_CE_DST_STATUS_DESC_FLAGS_LEN GENMASK(31, 16) |
| 1458 | |
| 1459 | #define HAL_CE_DST_STATUS_DESC_META_INFO_DATA GENMASK(15, 0) |
| 1460 | #define HAL_CE_DST_STATUS_DESC_META_INFO_RING_ID GENMASK(27, 20) |
| 1461 | #define HAL_CE_DST_STATUS_DESC_META_INFO_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT |
| 1462 | |
| 1463 | struct hal_ce_srng_dst_status_desc { |
| 1464 | u32 flags; /* %HAL_CE_DST_STATUS_DESC_FLAGS_ */ |
| 1465 | u32 toeplitz_hash0; |
| 1466 | u32 toeplitz_hash1; |
| 1467 | u32 meta_info; /* HAL_CE_DST_STATUS_DESC_META_INFO_ */ |
| 1468 | } __packed; |
| 1469 | |
| 1470 | /* hal_ce_srng_dst_status_desc |
| 1471 | * |
| 1472 | * ce_res_5 |
| 1473 | * Reserved |
| 1474 | * |
| 1475 | * toeplitz_en |
| 1476 | * |
| 1477 | * src_swap |
| 1478 | * Source memory buffer swapped |
| 1479 | * |
| 1480 | * dest_swap |
| 1481 | * Destination memory buffer swapped |
| 1482 | * |
| 1483 | * gather |
| 1484 | * Gather of multiple copy engine source descriptors to one |
| 1485 | * destination enabled |
| 1486 | * |
| 1487 | * ce_res_6 |
| 1488 | * Reserved |
| 1489 | * |
| 1490 | * length |
| 1491 | * Sum of all the Lengths of the source descriptor in the |
| 1492 | * gather chain |
| 1493 | * |
| 1494 | * toeplitz_hash_0 |
| 1495 | * 32 LS bits of 64 bit Toeplitz LFSR hash result |
| 1496 | * |
| 1497 | * toeplitz_hash_1 |
| 1498 | * 32 MS bits of 64 bit Toeplitz LFSR hash result |
| 1499 | * |
| 1500 | * fw_metadata |
| 1501 | * Meta data used by FW |
| 1502 | * In case of gather field in first source ring entry of |
| 1503 | * the gather copy cycle in taken into account. |
| 1504 | * |
| 1505 | * ce_res_7 |
| 1506 | * Reserved |
| 1507 | * |
| 1508 | * ring_id |
| 1509 | * The buffer pointer ring ID. |
| 1510 | * 0 refers to the IDLE ring |
| 1511 | * 1 - N refers to other rings |
| 1512 | * Helps with debugging when dumping ring contents. |
| 1513 | * |
| 1514 | * looping_count |
| 1515 | * A count value that indicates the number of times the |
| 1516 | * producer of entries into the Ring has looped around the |
| 1517 | * ring. |
| 1518 | * |
| 1519 | * At initialization time, this value is set to 0. On the |
| 1520 | * first loop, this value is set to 1. After the max value is |
| 1521 | * reached allowed by the number of bits for this field, the |
| 1522 | * count value continues with 0 again. |
| 1523 | * |
| 1524 | * In case SW is the consumer of the ring entries, it can |
| 1525 | * use this field to figure out up to where the producer of |
| 1526 | * entries has created new entries. This eliminates the need to |
| 1527 | * check where the head pointer' of the ring is located once |
| 1528 | * the SW starts processing an interrupt indicating that new |
| 1529 | * entries have been put into this ring... |
| 1530 | * |
| 1531 | * Also note that SW if it wants only needs to look at the |
| 1532 | * LSB bit of this count value. |
| 1533 | */ |
| 1534 | |
| 1535 | #define HAL_TX_RATE_STATS_INFO0_VALID BIT(0) |
| 1536 | #define HAL_TX_RATE_STATS_INFO0_BW GENMASK(2, 1) |
| 1537 | #define HAL_TX_RATE_STATS_INFO0_PKT_TYPE GENMASK(6, 3) |
| 1538 | #define HAL_TX_RATE_STATS_INFO0_STBC BIT(7) |
| 1539 | #define HAL_TX_RATE_STATS_INFO0_LDPC BIT(8) |
| 1540 | #define HAL_TX_RATE_STATS_INFO0_SGI GENMASK(10, 9) |
| 1541 | #define HAL_TX_RATE_STATS_INFO0_MCS GENMASK(14, 11) |
| 1542 | #define HAL_TX_RATE_STATS_INFO0_OFDMA_TX BIT(15) |
| 1543 | #define HAL_TX_RATE_STATS_INFO0_TONES_IN_RU GENMASK(27, 16) |
| 1544 | |
| 1545 | enum hal_tx_rate_stats_bw { |
| 1546 | HAL_TX_RATE_STATS_BW_20, |
| 1547 | HAL_TX_RATE_STATS_BW_40, |
| 1548 | HAL_TX_RATE_STATS_BW_80, |
| 1549 | HAL_TX_RATE_STATS_BW_160, |
| 1550 | }; |
| 1551 | |
| 1552 | enum hal_tx_rate_stats_pkt_type { |
| 1553 | HAL_TX_RATE_STATS_PKT_TYPE_11A, |
| 1554 | HAL_TX_RATE_STATS_PKT_TYPE_11B, |
| 1555 | HAL_TX_RATE_STATS_PKT_TYPE_11N, |
| 1556 | HAL_TX_RATE_STATS_PKT_TYPE_11AC, |
| 1557 | HAL_TX_RATE_STATS_PKT_TYPE_11AX, |
| 1558 | }; |
| 1559 | |
| 1560 | enum hal_tx_rate_stats_sgi { |
| 1561 | HAL_TX_RATE_STATS_SGI_08US, |
| 1562 | HAL_TX_RATE_STATS_SGI_04US, |
| 1563 | HAL_TX_RATE_STATS_SGI_16US, |
| 1564 | HAL_TX_RATE_STATS_SGI_32US, |
| 1565 | }; |
| 1566 | |
| 1567 | struct hal_tx_rate_stats { |
| 1568 | u32 info0; |
| 1569 | u32 tsf; |
| 1570 | } __packed; |
| 1571 | |
| 1572 | struct hal_wbm_link_desc { |
| 1573 | struct ath11k_buffer_addr buf_addr_info; |
| 1574 | } __packed; |
| 1575 | |
| 1576 | /* hal_wbm_link_desc |
| 1577 | * |
| 1578 | * Producer: WBM |
| 1579 | * Consumer: WBM |
| 1580 | * |
| 1581 | * buf_addr_info |
| 1582 | * Details of the physical address of a buffer or MSDU |
| 1583 | * link descriptor. |
| 1584 | */ |
| 1585 | |
| 1586 | enum hal_wbm_rel_src_module { |
| 1587 | HAL_WBM_REL_SRC_MODULE_TQM, |
| 1588 | HAL_WBM_REL_SRC_MODULE_RXDMA, |
| 1589 | HAL_WBM_REL_SRC_MODULE_REO, |
| 1590 | HAL_WBM_REL_SRC_MODULE_FW, |
| 1591 | HAL_WBM_REL_SRC_MODULE_SW, |
| 1592 | }; |
| 1593 | |
| 1594 | enum hal_wbm_rel_desc_type { |
| 1595 | HAL_WBM_REL_DESC_TYPE_REL_MSDU, |
| 1596 | HAL_WBM_REL_DESC_TYPE_MSDU_LINK, |
| 1597 | HAL_WBM_REL_DESC_TYPE_MPDU_LINK, |
| 1598 | HAL_WBM_REL_DESC_TYPE_MSDU_EXT, |
| 1599 | HAL_WBM_REL_DESC_TYPE_QUEUE_EXT, |
| 1600 | }; |
| 1601 | |
| 1602 | /* hal_wbm_rel_desc_type |
| 1603 | * |
| 1604 | * msdu_buffer |
| 1605 | * The address points to an MSDU buffer |
| 1606 | * |
| 1607 | * msdu_link_descriptor |
| 1608 | * The address points to an Tx MSDU link descriptor |
| 1609 | * |
| 1610 | * mpdu_link_descriptor |
| 1611 | * The address points to an MPDU link descriptor |
| 1612 | * |
| 1613 | * msdu_ext_descriptor |
| 1614 | * The address points to an MSDU extension descriptor |
| 1615 | * |
| 1616 | * queue_ext_descriptor |
| 1617 | * The address points to an TQM queue extension descriptor. WBM should |
| 1618 | * treat this is the same way as a link descriptor. |
| 1619 | */ |
| 1620 | |
| 1621 | enum hal_wbm_rel_bm_act { |
| 1622 | HAL_WBM_REL_BM_ACT_PUT_IN_IDLE, |
| 1623 | HAL_WBM_REL_BM_ACT_REL_MSDU, |
| 1624 | }; |
| 1625 | |
| 1626 | /* hal_wbm_rel_bm_act |
| 1627 | * |
| 1628 | * put_in_idle_list |
| 1629 | * Put the buffer or descriptor back in the idle list. In case of MSDU or |
| 1630 | * MDPU link descriptor, BM does not need to check to release any |
| 1631 | * individual MSDU buffers. |
| 1632 | * |
| 1633 | * release_msdu_list |
| 1634 | * This BM action can only be used in combination with desc_type being |
| 1635 | * msdu_link_descriptor. Field first_msdu_index points out which MSDU |
| 1636 | * pointer in the MSDU link descriptor is the first of an MPDU that is |
| 1637 | * released. BM shall release all the MSDU buffers linked to this first |
| 1638 | * MSDU buffer pointer. All related MSDU buffer pointer entries shall be |
| 1639 | * set to value 0, which represents the 'NULL' pointer. When all MSDU |
| 1640 | * buffer pointers in the MSDU link descriptor are 'NULL', the MSDU link |
| 1641 | * descriptor itself shall also be released. |
| 1642 | */ |
| 1643 | |
| 1644 | #define HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE GENMASK(2, 0) |
| 1645 | #define HAL_WBM_RELEASE_INFO0_BM_ACTION GENMASK(5, 3) |
| 1646 | #define HAL_WBM_RELEASE_INFO0_DESC_TYPE GENMASK(8, 6) |
| 1647 | #define HAL_WBM_RELEASE_INFO0_FIRST_MSDU_IDX GENMASK(12, 9) |
| 1648 | #define HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON GENMASK(16, 13) |
| 1649 | #define HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17) |
| 1650 | #define HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19) |
| 1651 | #define HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON GENMASK(25, 24) |
| 1652 | #define HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE GENMASK(30, 26) |
| 1653 | #define HAL_WBM_RELEASE_INFO0_WBM_INTERNAL_ERROR BIT(31) |
| 1654 | |
| 1655 | #define HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER GENMASK(23, 0) |
| 1656 | #define HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT GENMASK(30, 24) |
| 1657 | |
| 1658 | #define HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI GENMASK(7, 0) |
| 1659 | #define HAL_WBM_RELEASE_INFO2_SW_REL_DETAILS_VALID BIT(8) |
| 1660 | #define HAL_WBM_RELEASE_INFO2_FIRST_MSDU BIT(9) |
| 1661 | #define HAL_WBM_RELEASE_INFO2_LAST_MSDU BIT(10) |
| 1662 | #define HAL_WBM_RELEASE_INFO2_MSDU_IN_AMSDU BIT(11) |
| 1663 | #define HAL_WBM_RELEASE_INFO2_FW_TX_NOTIF_FRAME BIT(12) |
| 1664 | #define HAL_WBM_RELEASE_INFO2_BUFFER_TIMESTAMP GENMASK(31, 13) |
| 1665 | |
| 1666 | #define HAL_WBM_RELEASE_INFO3_PEER_ID GENMASK(15, 0) |
| 1667 | #define HAL_WBM_RELEASE_INFO3_TID GENMASK(19, 16) |
| 1668 | #define HAL_WBM_RELEASE_INFO3_RING_ID GENMASK(27, 20) |
| 1669 | #define HAL_WBM_RELEASE_INFO3_LOOPING_COUNT GENMASK(31, 28) |
| 1670 | |
| 1671 | #define HAL_WBM_REL_HTT_TX_COMP_INFO0_STATUS GENMASK(12, 9) |
| 1672 | #define HAL_WBM_REL_HTT_TX_COMP_INFO0_REINJ_REASON GENMASK(16, 13) |
| 1673 | #define HAL_WBM_REL_HTT_TX_COMP_INFO0_EXP_FRAME BIT(17) |
| 1674 | |
| 1675 | struct hal_wbm_release_ring { |
| 1676 | struct ath11k_buffer_addr buf_addr_info; |
| 1677 | u32 info0; |
| 1678 | u32 info1; |
| 1679 | u32 info2; |
| 1680 | struct hal_tx_rate_stats rate_stats; |
| 1681 | u32 info3; |
| 1682 | } __packed; |
| 1683 | |
| 1684 | /* hal_wbm_release_ring |
| 1685 | * |
| 1686 | * Producer: SW/TQM/RXDMA/REO/SWITCH |
| 1687 | * Consumer: WBM/SW/FW |
| 1688 | * |
| 1689 | * HTT tx status is overlayed on wbm_release ring on 4-byte words 2, 3, 4 and 5 |
| 1690 | * for software based completions. |
| 1691 | * |
| 1692 | * buf_addr_info |
| 1693 | * Details of the physical address of the buffer or link descriptor. |
| 1694 | * |
| 1695 | * release_source_module |
| 1696 | * Indicates which module initiated the release of this buffer/descriptor. |
| 1697 | * Values are defined in enum %HAL_WBM_REL_SRC_MODULE_. |
| 1698 | * |
| 1699 | * bm_action |
| 1700 | * Field only valid when the field return_buffer_manager in |
| 1701 | * Released_buff_or_desc_addr_info indicates: |
| 1702 | * WBM_IDLE_BUF_LIST / WBM_IDLE_DESC_LIST |
| 1703 | * Values are defined in enum %HAL_WBM_REL_BM_ACT_. |
| 1704 | * |
| 1705 | * buffer_or_desc_type |
| 1706 | * Field only valid when WBM is marked as the return_buffer_manager in |
| 1707 | * the Released_Buffer_address_info. Indicates that type of buffer or |
| 1708 | * descriptor is being released. Values are in enum %HAL_WBM_REL_DESC_TYPE. |
| 1709 | * |
| 1710 | * first_msdu_index |
| 1711 | * Field only valid for the bm_action release_msdu_list. The index of the |
| 1712 | * first MSDU in an MSDU link descriptor all belonging to the same MPDU. |
| 1713 | * |
| 1714 | * tqm_release_reason |
| 1715 | * Field only valid when Release_source_module is set to release_source_TQM |
| 1716 | * Release reasons are defined in enum %HAL_WBM_TQM_REL_REASON_. |
| 1717 | * |
| 1718 | * rxdma_push_reason |
| 1719 | * reo_push_reason |
| 1720 | * Indicates why rxdma/reo pushed the frame to this ring and values are |
| 1721 | * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. |
| 1722 | * |
| 1723 | * rxdma_error_code |
| 1724 | * Field only valid when 'rxdma_push_reason' set to 'error_detected'. |
| 1725 | * Values are defined in enum %HAL_REO_ENTR_RING_RXDMA_ECODE_. |
| 1726 | * |
| 1727 | * reo_error_code |
| 1728 | * Field only valid when 'reo_push_reason' set to 'error_detected'. Values |
| 1729 | * are defined in enum %HAL_REO_DEST_RING_ERROR_CODE_. |
| 1730 | * |
| 1731 | * wbm_internal_error |
| 1732 | * Is set when WBM got a buffer pointer but the action was to push it to |
| 1733 | * the idle link descriptor ring or do link related activity OR |
| 1734 | * Is set when WBM got a link buffer pointer but the action was to push it |
| 1735 | * to the buffer descriptor ring. |
| 1736 | * |
| 1737 | * tqm_status_number |
| 1738 | * The value in this field is equal to tqm_cmd_number in TQM command. It is |
| 1739 | * used to correlate the statu with TQM commands. Only valid when |
| 1740 | * release_source_module is TQM. |
| 1741 | * |
| 1742 | * transmit_count |
| 1743 | * The number of times the frame has been transmitted, valid only when |
| 1744 | * release source in TQM. |
| 1745 | * |
| 1746 | * ack_frame_rssi |
| 1747 | * This field is only valid when the source is TQM. If this frame is |
| 1748 | * removed as the result of the reception of an ACK or BA, this field |
| 1749 | * indicates the RSSI of the received ACK or BA frame. |
| 1750 | * |
| 1751 | * sw_release_details_valid |
| 1752 | * This is set when WMB got a 'release_msdu_list' command from TQM and |
| 1753 | * return buffer manager is not WMB. WBM will then de-aggregate all MSDUs |
| 1754 | * and pass them one at a time on to the 'buffer owner'. |
| 1755 | * |
| 1756 | * first_msdu |
| 1757 | * Field only valid when SW_release_details_valid is set. |
| 1758 | * When set, this MSDU is the first MSDU pointed to in the |
| 1759 | * 'release_msdu_list' command. |
| 1760 | * |
| 1761 | * last_msdu |
| 1762 | * Field only valid when SW_release_details_valid is set. |
| 1763 | * When set, this MSDU is the last MSDU pointed to in the |
| 1764 | * 'release_msdu_list' command. |
| 1765 | * |
| 1766 | * msdu_part_of_amsdu |
| 1767 | * Field only valid when SW_release_details_valid is set. |
| 1768 | * When set, this MSDU was part of an A-MSDU in MPDU |
| 1769 | * |
| 1770 | * fw_tx_notify_frame |
| 1771 | * Field only valid when SW_release_details_valid is set. |
| 1772 | * |
| 1773 | * buffer_timestamp |
| 1774 | * Field only valid when SW_release_details_valid is set. |
| 1775 | * This is the Buffer_timestamp field from the |
| 1776 | * Timestamp in units of 1024 us |
| 1777 | * |
| 1778 | * struct hal_tx_rate_stats rate_stats |
| 1779 | * Details for command execution tracking purposes. |
| 1780 | * |
| 1781 | * sw_peer_id |
| 1782 | * tid |
| 1783 | * Field only valid when Release_source_module is set to |
| 1784 | * release_source_TQM |
| 1785 | * |
| 1786 | * 1) Release of msdu buffer due to drop_frame = 1. Flow is |
| 1787 | * not fetched and hence sw_peer_id and tid = 0 |
| 1788 | * |
| 1789 | * buffer_or_desc_type = e_num 0 |
| 1790 | * MSDU_rel_buffertqm_release_reason = e_num 1 |
| 1791 | * tqm_rr_rem_cmd_rem |
| 1792 | * |
| 1793 | * 2) Release of msdu buffer due to Flow is not fetched and |
| 1794 | * hence sw_peer_id and tid = 0 |
| 1795 | * |
| 1796 | * buffer_or_desc_type = e_num 0 |
| 1797 | * MSDU_rel_buffertqm_release_reason = e_num 1 |
| 1798 | * tqm_rr_rem_cmd_rem |
| 1799 | * |
| 1800 | * 3) Release of msdu link due to remove_mpdu or acked_mpdu |
| 1801 | * command. |
| 1802 | * |
| 1803 | * buffer_or_desc_type = e_num1 |
| 1804 | * msdu_link_descriptortqm_release_reason can be:e_num 1 |
| 1805 | * tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx |
| 1806 | * e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged |
| 1807 | * |
| 1808 | * This field represents the TID from the TX_MSDU_FLOW |
| 1809 | * descriptor or TX_MPDU_QUEUE descriptor |
| 1810 | * |
| 1811 | * rind_id |
| 1812 | * For debugging. |
| 1813 | * This field is filled in by the SRNG module. |
| 1814 | * It help to identify the ring that is being looked |
| 1815 | * |
| 1816 | * looping_count |
| 1817 | * A count value that indicates the number of times the |
| 1818 | * producer of entries into the Buffer Manager Ring has looped |
| 1819 | * around the ring. |
| 1820 | * |
| 1821 | * At initialization time, this value is set to 0. On the |
| 1822 | * first loop, this value is set to 1. After the max value is |
| 1823 | * reached allowed by the number of bits for this field, the |
| 1824 | * count value continues with 0 again. |
| 1825 | * |
| 1826 | * In case SW is the consumer of the ring entries, it can |
| 1827 | * use this field to figure out up to where the producer of |
| 1828 | * entries has created new entries. This eliminates the need to |
| 1829 | * check where the head pointer' of the ring is located once |
| 1830 | * the SW starts processing an interrupt indicating that new |
| 1831 | * entries have been put into this ring... |
| 1832 | * |
| 1833 | * Also note that SW if it wants only needs to look at the |
| 1834 | * LSB bit of this count value. |
| 1835 | */ |
| 1836 | |
| 1837 | /** |
| 1838 | * enum hal_wbm_tqm_rel_reason - TQM release reason code |
| 1839 | * @HAL_WBM_TQM_REL_REASON_FRAME_ACKED: ACK or BACK received for the frame |
| 1840 | * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU: Command remove_mpdus initiated by SW |
| 1841 | * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX: Command remove transmitted_mpdus |
| 1842 | * initiated by sw. |
| 1843 | * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX: Command remove untransmitted_mpdus |
| 1844 | * initiated by sw. |
| 1845 | * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES: Command remove aged msdus or |
| 1846 | * mpdus. |
| 1847 | * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1: Remove command initiated by |
| 1848 | * fw with fw_reason1. |
| 1849 | * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2: Remove command initiated by |
| 1850 | * fw with fw_reason2. |
| 1851 | * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3: Remove command initiated by |
| 1852 | * fw with fw_reason3. |
| 1853 | */ |
| 1854 | enum hal_wbm_tqm_rel_reason { |
| 1855 | HAL_WBM_TQM_REL_REASON_FRAME_ACKED, |
| 1856 | HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU, |
| 1857 | HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX, |
| 1858 | HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX, |
| 1859 | HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES, |
| 1860 | HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1, |
| 1861 | HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2, |
| 1862 | HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3, |
| 1863 | }; |
| 1864 | |
| 1865 | struct hal_wbm_buffer_ring { |
| 1866 | struct ath11k_buffer_addr buf_addr_info; |
| 1867 | }; |
| 1868 | |
| 1869 | enum hal_desc_owner { |
| 1870 | HAL_DESC_OWNER_WBM, |
| 1871 | HAL_DESC_OWNER_SW, |
| 1872 | HAL_DESC_OWNER_TQM, |
| 1873 | HAL_DESC_OWNER_RXDMA, |
| 1874 | HAL_DESC_OWNER_REO, |
| 1875 | HAL_DESC_OWNER_SWITCH, |
| 1876 | }; |
| 1877 | |
| 1878 | enum hal_desc_buf_type { |
| 1879 | HAL_DESC_BUF_TYPE_TX_MSDU_LINK, |
| 1880 | HAL_DESC_BUF_TYPE_TX_MPDU_LINK, |
| 1881 | HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_HEAD, |
| 1882 | HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_EXT, |
| 1883 | HAL_DESC_BUF_TYPE_TX_FLOW, |
| 1884 | HAL_DESC_BUF_TYPE_TX_BUFFER, |
| 1885 | HAL_DESC_BUF_TYPE_RX_MSDU_LINK, |
| 1886 | HAL_DESC_BUF_TYPE_RX_MPDU_LINK, |
| 1887 | HAL_DESC_BUF_TYPE_RX_REO_QUEUE, |
| 1888 | HAL_DESC_BUF_TYPE_RX_REO_QUEUE_EXT, |
| 1889 | HAL_DESC_BUF_TYPE_RX_BUFFER, |
| 1890 | HAL_DESC_BUF_TYPE_IDLE_LINK, |
| 1891 | }; |
| 1892 | |
| 1893 | #define HAL_DESC_REO_OWNED 4 |
| 1894 | #define HAL_DESC_REO_QUEUE_DESC 8 |
| 1895 | #define HAL_DESC_REO_QUEUE_EXT_DESC 9 |
| 1896 | #define HAL_DESC_REO_NON_QOS_TID 16 |
| 1897 | |
| 1898 | #define HAL_DESC_HDR_INFO0_OWNER GENMASK(3, 0) |
| 1899 | #define HAL_DESC_HDR_INFO0_BUF_TYPE GENMASK(7, 4) |
| 1900 | #define HAL_DESC_HDR_INFO0_DBG_RESERVED GENMASK(31, 8) |
| 1901 | |
| 1902 | struct hal_desc_header { |
| 1903 | u32 info0; |
| 1904 | } __packed; |
| 1905 | |
| 1906 | struct hal_rx_mpdu_link_ptr { |
| 1907 | struct ath11k_buffer_addr addr_info; |
| 1908 | } __packed; |
| 1909 | |
| 1910 | struct hal_rx_msdu_details { |
| 1911 | struct ath11k_buffer_addr buf_addr_info; |
| 1912 | struct rx_msdu_desc rx_msdu_info; |
| 1913 | } __packed; |
| 1914 | |
| 1915 | #define HAL_RX_MSDU_LNK_INFO0_RX_QUEUE_NUMBER GENMASK(15, 0) |
| 1916 | #define HAL_RX_MSDU_LNK_INFO0_FIRST_MSDU_LNK BIT(16) |
| 1917 | |
| 1918 | struct hal_rx_msdu_link { |
| 1919 | struct hal_desc_header desc_hdr; |
| 1920 | struct ath11k_buffer_addr buf_addr_info; |
| 1921 | u32 info0; |
| 1922 | u32 pn[4]; |
| 1923 | struct hal_rx_msdu_details msdu_link[6]; |
| 1924 | } __packed; |
| 1925 | |
| 1926 | struct hal_rx_reo_queue_ext { |
| 1927 | struct hal_desc_header desc_hdr; |
| 1928 | u32 rsvd; |
| 1929 | struct hal_rx_mpdu_link_ptr mpdu_link[15]; |
| 1930 | } __packed; |
| 1931 | |
| 1932 | /* hal_rx_reo_queue_ext |
| 1933 | * Consumer: REO |
| 1934 | * Producer: REO |
| 1935 | * |
| 1936 | * descriptor_header |
| 1937 | * Details about which module owns this struct. |
| 1938 | * |
| 1939 | * mpdu_link |
| 1940 | * Pointer to the next MPDU_link descriptor in the MPDU queue. |
| 1941 | */ |
| 1942 | |
| 1943 | enum hal_rx_reo_queue_pn_size { |
| 1944 | HAL_RX_REO_QUEUE_PN_SIZE_24, |
| 1945 | HAL_RX_REO_QUEUE_PN_SIZE_48, |
| 1946 | HAL_RX_REO_QUEUE_PN_SIZE_128, |
| 1947 | }; |
| 1948 | |
| 1949 | #define HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER GENMASK(15, 0) |
| 1950 | |
| 1951 | #define HAL_RX_REO_QUEUE_INFO0_VLD BIT(0) |
| 1952 | #define HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER GENMASK(2, 1) |
| 1953 | #define HAL_RX_REO_QUEUE_INFO0_DIS_DUP_DETECTION BIT(3) |
| 1954 | #define HAL_RX_REO_QUEUE_INFO0_SOFT_REORDER_EN BIT(4) |
| 1955 | #define HAL_RX_REO_QUEUE_INFO0_AC GENMASK(6, 5) |
| 1956 | #define HAL_RX_REO_QUEUE_INFO0_BAR BIT(7) |
| 1957 | #define HAL_RX_REO_QUEUE_INFO0_RETRY BIT(8) |
| 1958 | #define HAL_RX_REO_QUEUE_INFO0_CHECK_2K_MODE BIT(9) |
| 1959 | #define HAL_RX_REO_QUEUE_INFO0_OOR_MODE BIT(10) |
| 1960 | #define HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE GENMASK(18, 11) |
| 1961 | #define HAL_RX_REO_QUEUE_INFO0_PN_CHECK BIT(19) |
| 1962 | #define HAL_RX_REO_QUEUE_INFO0_EVEN_PN BIT(20) |
| 1963 | #define HAL_RX_REO_QUEUE_INFO0_UNEVEN_PN BIT(21) |
| 1964 | #define HAL_RX_REO_QUEUE_INFO0_PN_HANDLE_ENABLE BIT(22) |
| 1965 | #define HAL_RX_REO_QUEUE_INFO0_PN_SIZE GENMASK(24, 23) |
| 1966 | #define HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG BIT(25) |
| 1967 | |
| 1968 | #define HAL_RX_REO_QUEUE_INFO1_SVLD BIT(0) |
| 1969 | #define HAL_RX_REO_QUEUE_INFO1_SSN GENMASK(12, 1) |
| 1970 | #define HAL_RX_REO_QUEUE_INFO1_CURRENT_IDX GENMASK(20, 13) |
| 1971 | #define HAL_RX_REO_QUEUE_INFO1_SEQ_2K_ERR BIT(21) |
| 1972 | #define HAL_RX_REO_QUEUE_INFO1_PN_ERR BIT(22) |
| 1973 | #define HAL_RX_REO_QUEUE_INFO1_PN_VALID BIT(31) |
| 1974 | |
| 1975 | #define HAL_RX_REO_QUEUE_INFO2_MPDU_COUNT GENMASK(6, 0) |
| 1976 | #define HAL_RX_REO_QUEUE_INFO2_MSDU_COUNT (31, 7) |
| 1977 | |
| 1978 | #define HAL_RX_REO_QUEUE_INFO3_TIMEOUT_COUNT GENMASK(9, 4) |
| 1979 | #define HAL_RX_REO_QUEUE_INFO3_FWD_DUE_TO_BAR_CNT GENMASK(15, 10) |
| 1980 | #define HAL_RX_REO_QUEUE_INFO3_DUPLICATE_COUNT GENMASK(31, 16) |
| 1981 | |
| 1982 | #define HAL_RX_REO_QUEUE_INFO4_FRAME_IN_ORD_COUNT GENMASK(23, 0) |
| 1983 | #define HAL_RX_REO_QUEUE_INFO4_BAR_RECVD_COUNT GENMASK(31, 24) |
| 1984 | |
| 1985 | #define HAL_RX_REO_QUEUE_INFO5_LATE_RX_MPDU_COUNT GENMASK(11, 0) |
| 1986 | #define HAL_RX_REO_QUEUE_INFO5_WINDOW_JUMP_2K GENMASK(15, 12) |
| 1987 | #define HAL_RX_REO_QUEUE_INFO5_HOLE_COUNT GENMASK(31, 16) |
| 1988 | |
| 1989 | struct hal_rx_reo_queue { |
| 1990 | struct hal_desc_header desc_hdr; |
| 1991 | u32 rx_queue_num; |
| 1992 | u32 info0; |
| 1993 | u32 info1; |
| 1994 | u32 pn[4]; |
| 1995 | u32 last_rx_enqueue_timestamp; |
| 1996 | u32 last_rx_dequeue_timestamp; |
| 1997 | u32 next_aging_queue[2]; |
| 1998 | u32 prev_aging_queue[2]; |
| 1999 | u32 rx_bitmap[8]; |
| 2000 | u32 info2; |
| 2001 | u32 info3; |
| 2002 | u32 info4; |
| 2003 | u32 processed_mpdus; |
| 2004 | u32 processed_msdus; |
| 2005 | u32 processed_total_bytes; |
| 2006 | u32 info5; |
| 2007 | u32 rsvd[3]; |
| 2008 | struct hal_rx_reo_queue_ext ext_desc[]; |
| 2009 | } __packed; |
| 2010 | |
| 2011 | /* hal_rx_reo_queue |
| 2012 | * |
| 2013 | * descriptor_header |
| 2014 | * Details about which module owns this struct. Note that sub field |
| 2015 | * Buffer_type shall be set to receive_reo_queue_descriptor. |
| 2016 | * |
| 2017 | * receive_queue_number |
| 2018 | * Indicates the MPDU queue ID to which this MPDU link descriptor belongs. |
| 2019 | * |
| 2020 | * vld |
| 2021 | * Valid bit indicating a session is established and the queue descriptor |
| 2022 | * is valid. |
| 2023 | * associated_link_descriptor_counter |
| 2024 | * Indicates which of the 3 link descriptor counters shall be incremented |
| 2025 | * or decremented when link descriptors are added or removed from this |
| 2026 | * flow queue. |
| 2027 | * disable_duplicate_detection |
| 2028 | * When set, do not perform any duplicate detection. |
| 2029 | * soft_reorder_enable |
| 2030 | * When set, REO has been instructed to not perform the actual re-ordering |
| 2031 | * of frames for this queue, but just to insert the reorder opcodes. |
| 2032 | * ac |
| 2033 | * Indicates the access category of the queue descriptor. |
| 2034 | * bar |
| 2035 | * Indicates if BAR has been received. |
| 2036 | * retry |
| 2037 | * Retry bit is checked if this bit is set. |
| 2038 | * chk_2k_mode |
| 2039 | * Indicates what type of operation is expected from Reo when the received |
| 2040 | * frame SN falls within the 2K window. |
| 2041 | * oor_mode |
| 2042 | * Indicates what type of operation is expected when the received frame |
| 2043 | * falls within the OOR window. |
| 2044 | * ba_window_size |
| 2045 | * Indicates the negotiated (window size + 1). Max of 256 bits. |
| 2046 | * |
| 2047 | * A value 255 means 256 bitmap, 63 means 64 bitmap, 0 (means non-BA |
| 2048 | * session, with window size of 0). The 3 values here are the main values |
| 2049 | * validated, but other values should work as well. |
| 2050 | * |
| 2051 | * A BA window size of 0 (=> one frame entry bitmat), means that there is |
| 2052 | * no additional rx_reo_queue_ext desc. following rx_reo_queue in memory. |
| 2053 | * A BA window size of 1 - 105, means that there is 1 rx_reo_queue_ext. |
| 2054 | * A BA window size of 106 - 210, means that there are 2 rx_reo_queue_ext. |
| 2055 | * A BA window size of 211 - 256, means that there are 3 rx_reo_queue_ext. |
| 2056 | * pn_check_needed, pn_shall_be_even, pn_shall_be_uneven, pn_handling_enable, |
| 2057 | * pn_size |
| 2058 | * REO shall perform the PN increment check, even number check, uneven |
| 2059 | * number check, PN error check and size of the PN field check. |
| 2060 | * ignore_ampdu_flag |
| 2061 | * REO shall ignore the ampdu_flag on entrance descriptor for this queue. |
| 2062 | * |
| 2063 | * svld |
| 2064 | * Sequence number in next field is valid one. |
| 2065 | * ssn |
| 2066 | * Starting Sequence number of the session. |
| 2067 | * current_index |
| 2068 | * Points to last forwarded packet |
| 2069 | * seq_2k_error_detected_flag |
| 2070 | * REO has detected a 2k error jump in the sequence number and from that |
| 2071 | * moment forward, all new frames are forwarded directly to FW, without |
| 2072 | * duplicate detect, reordering, etc. |
| 2073 | * pn_error_detected_flag |
| 2074 | * REO has detected a PN error. |
| 2075 | */ |
| 2076 | |
| 2077 | #define HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) |
| 2078 | #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM BIT(8) |
| 2079 | #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD BIT(9) |
| 2080 | #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT BIT(10) |
| 2081 | #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION BIT(11) |
| 2082 | #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN BIT(12) |
| 2083 | #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC BIT(13) |
| 2084 | #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR BIT(14) |
| 2085 | #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY BIT(15) |
| 2086 | #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE BIT(16) |
| 2087 | #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE BIT(17) |
| 2088 | #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE BIT(18) |
| 2089 | #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK BIT(19) |
| 2090 | #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN BIT(20) |
| 2091 | #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN BIT(21) |
| 2092 | #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE BIT(22) |
| 2093 | #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE BIT(23) |
| 2094 | #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG BIT(24) |
| 2095 | #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD BIT(25) |
| 2096 | #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN BIT(26) |
| 2097 | #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR BIT(27) |
| 2098 | #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_ERR BIT(28) |
| 2099 | #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID BIT(29) |
| 2100 | #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN BIT(30) |
| 2101 | |
| 2102 | #define HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER GENMASK(15, 0) |
| 2103 | #define HAL_REO_UPD_RX_QUEUE_INFO1_VLD BIT(16) |
| 2104 | #define HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER GENMASK(18, 17) |
| 2105 | #define HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION BIT(19) |
| 2106 | #define HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN BIT(20) |
| 2107 | #define HAL_REO_UPD_RX_QUEUE_INFO1_AC GENMASK(22, 21) |
| 2108 | #define HAL_REO_UPD_RX_QUEUE_INFO1_BAR BIT(23) |
| 2109 | #define HAL_REO_UPD_RX_QUEUE_INFO1_RETRY BIT(24) |
| 2110 | #define HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE BIT(25) |
| 2111 | #define HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE BIT(26) |
| 2112 | #define HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK BIT(27) |
| 2113 | #define HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN BIT(28) |
| 2114 | #define HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN BIT(29) |
| 2115 | #define HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE BIT(30) |
| 2116 | #define HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG BIT(31) |
| 2117 | |
| 2118 | #define HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE GENMASK(7, 0) |
| 2119 | #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE GENMASK(9, 8) |
| 2120 | #define HAL_REO_UPD_RX_QUEUE_INFO2_SVLD BIT(10) |
| 2121 | #define HAL_REO_UPD_RX_QUEUE_INFO2_SSN GENMASK(22, 11) |
| 2122 | #define HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR BIT(23) |
| 2123 | #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR BIT(24) |
| 2124 | #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_VALID BIT(25) |
| 2125 | |
| 2126 | struct hal_reo_update_rx_queue { |
| 2127 | struct hal_reo_cmd_hdr cmd; |
| 2128 | u32 queue_addr_lo; |
| 2129 | u32 info0; |
| 2130 | u32 info1; |
| 2131 | u32 info2; |
| 2132 | u32 pn[4]; |
| 2133 | } __packed; |
| 2134 | |
| 2135 | #define HAL_REO_UNBLOCK_CACHE_INFO0_UNBLK_CACHE BIT(0) |
| 2136 | #define HAL_REO_UNBLOCK_CACHE_INFO0_RESOURCE_IDX GENMASK(2, 1) |
| 2137 | |
| 2138 | struct hal_reo_unblock_cache { |
| 2139 | struct hal_reo_cmd_hdr cmd; |
| 2140 | u32 info0; |
| 2141 | u32 rsvd[7]; |
| 2142 | } __packed; |
| 2143 | |
| 2144 | enum hal_reo_exec_status { |
| 2145 | HAL_REO_EXEC_STATUS_SUCCESS, |
| 2146 | HAL_REO_EXEC_STATUS_BLOCKED, |
| 2147 | HAL_REO_EXEC_STATUS_FAILED, |
| 2148 | HAL_REO_EXEC_STATUS_RESOURCE_BLOCKED, |
| 2149 | }; |
| 2150 | |
| 2151 | #define HAL_REO_STATUS_HDR_INFO0_STATUS_NUM GENMASK(15, 0) |
| 2152 | #define HAL_REO_STATUS_HDR_INFO0_EXEC_TIME GENMASK(25, 16) |
| 2153 | #define HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS GENMASK(27, 26) |
| 2154 | |
| 2155 | struct hal_reo_status_hdr { |
| 2156 | u32 info0; |
| 2157 | u32 timestamp; |
| 2158 | } __packed; |
| 2159 | |
| 2160 | /* hal_reo_status_hdr |
| 2161 | * Producer: REO |
| 2162 | * Consumer: SW |
| 2163 | * |
| 2164 | * status_num |
| 2165 | * The value in this field is equal to value of the reo command |
| 2166 | * number. This field helps to correlate the statuses with the REO |
| 2167 | * commands. |
| 2168 | * |
| 2169 | * execution_time (in us) |
| 2170 | * The amount of time REO took to excecute the command. Note that |
| 2171 | * this time does not include the duration of the command waiting |
| 2172 | * in the command ring, before the execution started. |
| 2173 | * |
| 2174 | * execution_status |
| 2175 | * Execution status of the command. Values are defined in |
| 2176 | * enum %HAL_REO_EXEC_STATUS_. |
| 2177 | */ |
| 2178 | #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN GENMASK(11, 0) |
| 2179 | #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX GENMASK(19, 12) |
| 2180 | |
| 2181 | #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT GENMASK(6, 0) |
| 2182 | #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT GENMASK(31, 7) |
| 2183 | |
| 2184 | #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT GENMASK(9, 4) |
| 2185 | #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT GENMASK(15, 10) |
| 2186 | #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT GENMASK(31, 16) |
| 2187 | |
| 2188 | #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT GENMASK(23, 0) |
| 2189 | #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT GENMASK(31, 24) |
| 2190 | |
| 2191 | #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU GENMASK(11, 0) |
| 2192 | #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_WINDOW_JMP2K GENMASK(15, 12) |
| 2193 | #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT GENMASK(31, 16) |
| 2194 | |
| 2195 | #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT GENMASK(31, 28) |
| 2196 | |
| 2197 | struct hal_reo_get_queue_stats_status { |
| 2198 | struct hal_reo_status_hdr hdr; |
| 2199 | u32 info0; |
| 2200 | u32 pn[4]; |
| 2201 | u32 last_rx_enqueue_timestamp; |
| 2202 | u32 last_rx_dequeue_timestamp; |
| 2203 | u32 rx_bitmap[8]; |
| 2204 | u32 info1; |
| 2205 | u32 info2; |
| 2206 | u32 info3; |
| 2207 | u32 num_mpdu_frames; |
| 2208 | u32 num_msdu_frames; |
| 2209 | u32 total_bytes; |
| 2210 | u32 info4; |
| 2211 | u32 info5; |
| 2212 | } __packed; |
| 2213 | |
| 2214 | /* hal_reo_get_queue_stats_status |
| 2215 | * Producer: REO |
| 2216 | * Consumer: SW |
| 2217 | * |
| 2218 | * status_hdr |
| 2219 | * Details that can link this status with the original command. It |
| 2220 | * also contains info on how long REO took to execute this command. |
| 2221 | * |
| 2222 | * ssn |
| 2223 | * Starting Sequence number of the session, this changes whenever |
| 2224 | * window moves (can be filled by SW then maintained by REO). |
| 2225 | * |
| 2226 | * current_index |
| 2227 | * Points to last forwarded packet. |
| 2228 | * |
| 2229 | * pn |
| 2230 | * Bits of the PN number. |
| 2231 | * |
| 2232 | * last_rx_enqueue_timestamp |
| 2233 | * last_rx_dequeue_timestamp |
| 2234 | * Timestamp of arrival of the last MPDU for this queue and |
| 2235 | * Timestamp of forwarding an MPDU accordingly. |
| 2236 | * |
| 2237 | * rx_bitmap |
| 2238 | * When a bit is set, the corresponding frame is currently held |
| 2239 | * in the re-order queue. The bitmap is Fully managed by HW. |
| 2240 | * |
| 2241 | * current_mpdu_count |
| 2242 | * current_msdu_count |
| 2243 | * The number of MPDUs and MSDUs in the queue. |
| 2244 | * |
| 2245 | * timeout_count |
| 2246 | * The number of times REO started forwarding frames even though |
| 2247 | * there is a hole in the bitmap. Forwarding reason is timeout. |
| 2248 | * |
| 2249 | * forward_due_to_bar_count |
| 2250 | * The number of times REO started forwarding frames even though |
| 2251 | * there is a hole in the bitmap. Fwd reason is reception of BAR. |
| 2252 | * |
| 2253 | * duplicate_count |
| 2254 | * The number of duplicate frames that have been detected. |
| 2255 | * |
| 2256 | * frames_in_order_count |
| 2257 | * The number of frames that have been received in order (without |
| 2258 | * a hole that prevented them from being forwarded immediately). |
| 2259 | * |
| 2260 | * bar_received_count |
| 2261 | * The number of times a BAR frame is received. |
| 2262 | * |
| 2263 | * mpdu_frames_processed_count |
| 2264 | * msdu_frames_processed_count |
| 2265 | * The total number of MPDU/MSDU frames that have been processed. |
| 2266 | * |
| 2267 | * total_bytes |
| 2268 | * An approximation of the number of bytes received for this queue. |
| 2269 | * |
| 2270 | * late_receive_mpdu_count |
| 2271 | * The number of MPDUs received after the window had already moved |
| 2272 | * on. The 'late' sequence window is defined as |
| 2273 | * (Window SSN - 256) - (Window SSN - 1). |
| 2274 | * |
| 2275 | * window_jump_2k |
| 2276 | * The number of times the window moved more than 2K |
| 2277 | * |
| 2278 | * hole_count |
| 2279 | * The number of times a hole was created in the receive bitmap. |
| 2280 | * |
| 2281 | * looping_count |
| 2282 | * A count value that indicates the number of times the producer of |
| 2283 | * entries into this Ring has looped around the ring. |
| 2284 | */ |
| 2285 | |
| 2286 | #define HAL_REO_STATUS_LOOP_CNT GENMASK(31, 28) |
| 2287 | |
| 2288 | #define HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED BIT(0) |
| 2289 | #define HAL_REO_FLUSH_QUEUE_INFO0_RSVD GENMASK(31, 1) |
| 2290 | #define HAL_REO_FLUSH_QUEUE_INFO1_RSVD GENMASK(27, 0) |
| 2291 | |
| 2292 | struct hal_reo_flush_queue_status { |
| 2293 | struct hal_reo_status_hdr hdr; |
| 2294 | u32 info0; |
| 2295 | u32 rsvd0[21]; |
| 2296 | u32 info1; |
| 2297 | } __packed; |
| 2298 | |
| 2299 | /* hal_reo_flush_queue_status |
| 2300 | * Producer: REO |
| 2301 | * Consumer: SW |
| 2302 | * |
| 2303 | * status_hdr |
| 2304 | * Details that can link this status with the original command. It |
| 2305 | * also contains info on how long REO took to execute this command. |
| 2306 | * |
| 2307 | * error_detected |
| 2308 | * Status of blocking resource |
| 2309 | * |
| 2310 | * 0 - No error has been detected while executing this command |
| 2311 | * 1 - Error detected. The resource to be used for blocking was |
| 2312 | * already in use. |
| 2313 | * |
| 2314 | * looping_count |
| 2315 | * A count value that indicates the number of times the producer of |
| 2316 | * entries into this Ring has looped around the ring. |
| 2317 | */ |
| 2318 | |
| 2319 | #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR BIT(0) |
| 2320 | #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE GENMASK(2, 1) |
| 2321 | #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT BIT(8) |
| 2322 | #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE GENMASK(11, 9) |
| 2323 | #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID GENMASK(15, 12) |
| 2324 | #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR GENMASK(17, 16) |
| 2325 | #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT GENMASK(25, 18) |
| 2326 | |
| 2327 | struct hal_reo_flush_cache_status { |
| 2328 | struct hal_reo_status_hdr hdr; |
| 2329 | u32 info0; |
| 2330 | u32 rsvd0[21]; |
| 2331 | u32 info1; |
| 2332 | } __packed; |
| 2333 | |
| 2334 | /* hal_reo_flush_cache_status |
| 2335 | * Producer: REO |
| 2336 | * Consumer: SW |
| 2337 | * |
| 2338 | * status_hdr |
| 2339 | * Details that can link this status with the original command. It |
| 2340 | * also contains info on how long REO took to execute this command. |
| 2341 | * |
| 2342 | * error_detected |
| 2343 | * Status for blocking resource handling |
| 2344 | * |
| 2345 | * 0 - No error has been detected while executing this command |
| 2346 | * 1 - An error in the blocking resource management was detected |
| 2347 | * |
| 2348 | * block_error_details |
| 2349 | * only valid when error_detected is set |
| 2350 | * |
| 2351 | * 0 - No blocking related errors found |
| 2352 | * 1 - Blocking resource is already in use |
| 2353 | * 2 - Resource requested to be unblocked, was not blocked |
| 2354 | * |
| 2355 | * cache_controller_flush_status_hit |
| 2356 | * The status that the cache controller returned on executing the |
| 2357 | * flush command. |
| 2358 | * |
| 2359 | * 0 - miss; 1 - hit |
| 2360 | * |
| 2361 | * cache_controller_flush_status_desc_type |
| 2362 | * Flush descriptor type |
| 2363 | * |
| 2364 | * cache_controller_flush_status_client_id |
| 2365 | * Module who made the flush request |
| 2366 | * |
| 2367 | * In REO, this is always 0 |
| 2368 | * |
| 2369 | * cache_controller_flush_status_error |
| 2370 | * Error condition |
| 2371 | * |
| 2372 | * 0 - No error found |
| 2373 | * 1 - HW interface is still busy |
| 2374 | * 2 - Line currently locked. Used for one line flush command |
| 2375 | * 3 - At least one line is still locked. |
| 2376 | * Used for cache flush command. |
| 2377 | * |
| 2378 | * cache_controller_flush_count |
| 2379 | * The number of lines that were actually flushed out |
| 2380 | * |
| 2381 | * looping_count |
| 2382 | * A count value that indicates the number of times the producer of |
| 2383 | * entries into this Ring has looped around the ring. |
| 2384 | */ |
| 2385 | |
| 2386 | #define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR BIT(0) |
| 2387 | #define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE BIT(1) |
| 2388 | |
| 2389 | struct hal_reo_unblock_cache_status { |
| 2390 | struct hal_reo_status_hdr hdr; |
| 2391 | u32 info0; |
| 2392 | u32 rsvd0[21]; |
| 2393 | u32 info1; |
| 2394 | } __packed; |
| 2395 | |
| 2396 | /* hal_reo_unblock_cache_status |
| 2397 | * Producer: REO |
| 2398 | * Consumer: SW |
| 2399 | * |
| 2400 | * status_hdr |
| 2401 | * Details that can link this status with the original command. It |
| 2402 | * also contains info on how long REO took to execute this command. |
| 2403 | * |
| 2404 | * error_detected |
| 2405 | * 0 - No error has been detected while executing this command |
| 2406 | * 1 - The blocking resource was not in use, and therefore it could |
| 2407 | * not be unblocked. |
| 2408 | * |
| 2409 | * unblock_type |
| 2410 | * Reference to the type of unblock command |
| 2411 | * 0 - Unblock a blocking resource |
| 2412 | * 1 - The entire cache usage is unblock |
| 2413 | * |
| 2414 | * looping_count |
| 2415 | * A count value that indicates the number of times the producer of |
| 2416 | * entries into this Ring has looped around the ring. |
| 2417 | */ |
| 2418 | |
| 2419 | #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR BIT(0) |
| 2420 | #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY BIT(1) |
| 2421 | |
| 2422 | #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT GENMASK(15, 0) |
| 2423 | #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT GENMASK(31, 16) |
| 2424 | |
| 2425 | struct hal_reo_flush_timeout_list_status { |
| 2426 | struct hal_reo_status_hdr hdr; |
| 2427 | u32 info0; |
| 2428 | u32 info1; |
| 2429 | u32 rsvd0[20]; |
| 2430 | u32 info2; |
| 2431 | } __packed; |
| 2432 | |
| 2433 | /* hal_reo_flush_timeout_list_status |
| 2434 | * Producer: REO |
| 2435 | * Consumer: SW |
| 2436 | * |
| 2437 | * status_hdr |
| 2438 | * Details that can link this status with the original command. It |
| 2439 | * also contains info on how long REO took to execute this command. |
| 2440 | * |
| 2441 | * error_detected |
| 2442 | * 0 - No error has been detected while executing this command |
| 2443 | * 1 - Command not properly executed and returned with error |
| 2444 | * |
| 2445 | * timeout_list_empty |
| 2446 | * When set, REO has depleted the timeout list and all entries are |
| 2447 | * gone. |
| 2448 | * |
| 2449 | * release_desc_count |
| 2450 | * Producer: SW; Consumer: REO |
| 2451 | * The number of link descriptor released |
| 2452 | * |
| 2453 | * forward_buf_count |
| 2454 | * Producer: SW; Consumer: REO |
| 2455 | * The number of buffers forwarded to the REO destination rings |
| 2456 | * |
| 2457 | * looping_count |
| 2458 | * A count value that indicates the number of times the producer of |
| 2459 | * entries into this Ring has looped around the ring. |
| 2460 | */ |
| 2461 | |
| 2462 | #define HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX GENMASK(1, 0) |
| 2463 | #define HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0 GENMASK(23, 0) |
| 2464 | #define HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1 GENMASK(23, 0) |
| 2465 | #define HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2 GENMASK(23, 0) |
| 2466 | #define HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM GENMASK(25, 0) |
| 2467 | |
| 2468 | struct hal_reo_desc_thresh_reached_status { |
| 2469 | struct hal_reo_status_hdr hdr; |
| 2470 | u32 info0; |
| 2471 | u32 info1; |
| 2472 | u32 info2; |
| 2473 | u32 info3; |
| 2474 | u32 info4; |
| 2475 | u32 rsvd0[17]; |
| 2476 | u32 info5; |
| 2477 | } __packed; |
| 2478 | |
| 2479 | /* hal_reo_desc_thresh_reached_status |
| 2480 | * Producer: REO |
| 2481 | * Consumer: SW |
| 2482 | * |
| 2483 | * status_hdr |
| 2484 | * Details that can link this status with the original command. It |
| 2485 | * also contains info on how long REO took to execute this command. |
| 2486 | * |
| 2487 | * threshold_index |
| 2488 | * The index of the threshold register whose value got reached |
| 2489 | * |
| 2490 | * link_descriptor_counter0 |
| 2491 | * link_descriptor_counter1 |
| 2492 | * link_descriptor_counter2 |
| 2493 | * link_descriptor_counter_sum |
| 2494 | * Value of the respective counters at generation of this message |
| 2495 | * |
| 2496 | * looping_count |
| 2497 | * A count value that indicates the number of times the producer of |
| 2498 | * entries into this Ring has looped around the ring. |
| 2499 | */ |
| 2500 | |
| 2501 | #endif /* ATH11K_HAL_DESC_H */ |