| /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ |
| /* |
| * Copyright (c) 2021 MediaTek Inc. |
| * |
| */ |
| |
| #ifndef _DT_BINDINGS_GCE_MT6983_H |
| #define _DT_BINDINGS_GCE_MT6983_H |
| |
| /* assign timeout 0 also means default */ |
| #define CMDQ_NO_TIMEOUT 0xffffffff |
| #define CMDQ_TIMEOUT_DEFAULT 1000 |
| |
| /* GCE thread priority */ |
| #define CMDQ_THR_PRIO_LOWEST 0 |
| #define CMDQ_THR_PRIO_1 1 |
| #define CMDQ_THR_PRIO_2 2 |
| #define CMDQ_THR_PRIO_3 3 |
| #define CMDQ_THR_PRIO_4 4 |
| #define CMDQ_THR_PRIO_5 5 |
| #define CMDQ_THR_PRIO_6 6 |
| #define CMDQ_THR_PRIO_HIGHEST 7 |
| |
| /* CPR count in 32bit register */ |
| #define GCE_CPR_COUNT 1312 |
| |
| /* GCE subsys table */ |
| #define SUBSYS_1300XXXX 0 |
| #define SUBSYS_1400XXXX 1 |
| #define SUBSYS_1401XXXX 2 |
| #define SUBSYS_1402XXXX 3 |
| #define SUBSYS_1502XXXX 4 |
| #define SUBSYS_1880XXXX 5 |
| #define SUBSYS_1881XXXX 6 |
| #define SUBSYS_1882XXXX 7 |
| #define SUBSYS_1883XXXX 8 |
| #define SUBSYS_1884XXXX 9 |
| #define SUBSYS_1000XXXX 10 |
| #define SUBSYS_1001XXXX 11 |
| #define SUBSYS_1002XXXX 12 |
| #define SUBSYS_1003XXXX 13 |
| #define SUBSYS_1004XXXX 14 |
| #define SUBSYS_1005XXXX 15 |
| #define SUBSYS_1020XXXX 16 |
| #define SUBSYS_1028XXXX 17 |
| #define SUBSYS_1700XXXX 18 |
| #define SUBSYS_1701XXXX 19 |
| #define SUBSYS_1702XXXX 20 |
| #define SUBSYS_1703XXXX 21 |
| #define SUBSYS_1800XXXX 22 |
| #define SUBSYS_1801XXXX 23 |
| #define SUBSYS_1802XXXX 24 |
| #define SUBSYS_1804XXXX 25 |
| #define SUBSYS_1805XXXX 26 |
| #define SUBSYS_1808XXXX 27 |
| #define SUBSYS_180aXXXX 28 |
| #define SUBSYS_180bXXXX 29 |
| #define SUBSYS_NO_SUPPORT 99 |
| |
| /* GCE General Purpose Register (GPR) support |
| * Leave note for scenario usage here |
| */ |
| /* GCE: write mask */ |
| #define GCE_GPR_R00 0x00 |
| #define GCE_GPR_R01 0x01 |
| /* MDP: P1: JPEG dest */ |
| #define GCE_GPR_R02 0x02 |
| #define GCE_GPR_R03 0x03 |
| /* MDP: PQ color */ |
| #define GCE_GPR_R04 0x04 |
| /* MDP: 2D sharpness */ |
| #define GCE_GPR_R05 0x05 |
| /* DISP: poll esd */ |
| #define GCE_GPR_R06 0x06 |
| #define GCE_GPR_R07 0x07 |
| /* MDP: P4: 2D sharpness dst */ |
| #define GCE_GPR_R08 0x08 |
| #define GCE_GPR_R09 0x09 |
| /* VCU: poll with timeout for GPR timer */ |
| #define GCE_GPR_R10 0x0A |
| #define GCE_GPR_R11 0x0B |
| /* CMDQ: debug */ |
| #define GCE_GPR_R12 0x0C |
| #define GCE_GPR_R13 0x0D |
| /* CMDQ: P7: debug */ |
| #define GCE_GPR_R14 0x0E |
| #define GCE_GPR_R15 0x0F |
| |
| /* GCE-D hardware events */ |
| #define CMDQ_EVENT_MDPSYS1_MDP_RDMA0_SOF 0 |
| #define CMDQ_EVENT_MDPSYS1_MDP_RDMA1_SOF 1 |
| #define CMDQ_EVENT_MDPSYS1_MDP_TDSHP0_SOF 2 |
| #define CMDQ_EVENT_MDPSYS1_MDP_TDSHP1_SOF 3 |
| #define CMDQ_EVENT_MDPSYS1_MDP_COLOR0_SOF 4 |
| #define CMDQ_EVENT_MDPSYS1_MDP_COLOR1_SOF 5 |
| #define CMDQ_EVENT_MDPSYS1_MDP_WROT0_SOF 6 |
| #define CMDQ_EVENT_MDPSYS1_MDP_WROT1_SOF 7 |
| #define CMDQ_EVENT_MDPSYS1_MDP_FG0_SOF 8 |
| #define CMDQ_EVENT_MDPSYS1_MDP_FG1_SOF 9 |
| #define CMDQ_EVENT_MDPSYS1_MDP_DLI_ASYNC0_SOF 10 |
| #define CMDQ_EVENT_MDPSYS1_MDP_DLI_ASYNC1_SOF 11 |
| #define CMDQ_EVENT_MDPSYS1_MDP_DLO_ASYNC0_SOF 12 |
| #define CMDQ_EVENT_MDPSYS1_MDP_DLO_ASYNC1_SOF 13 |
| #define CMDQ_EVENT_MDPSYS1_MDP_RSZ2_SOF 14 |
| #define CMDQ_EVENT_MDPSYS1_MDP_RSZ3_SOF 15 |
| #define CMDQ_EVENT_MDPSYS1_MDP_WROT2_SOF 16 |
| #define CMDQ_EVENT_MDPSYS1_MDP_WROT3_SOF 17 |
| #define CMDQ_EVENT_MDPSYS1_MDP_WROT3_FRAME_DONE 18 |
| #define CMDQ_EVENT_MDPSYS1_MDP_WROT2_FRAME_DONE 19 |
| #define CMDQ_EVENT_MDPSYS1_MDP_WROT1_FRAME_DONE 20 |
| #define CMDQ_EVENT_MDPSYS1_MDP_WROT0_FRAME_DONE 21 |
| #define CMDQ_EVENT_MDPSYS1_MDP_TDSHP1_FRAME_DONE 22 |
| #define CMDQ_EVENT_MDPSYS1_MDP_TDSHP0_FRAME_DONE 23 |
| #define CMDQ_EVENT_MDPSYS1_MDP_RSZ3_FRAME_DONE 24 |
| #define CMDQ_EVENT_MDPSYS1_MDP_RSZ2_FRAME_DONE 25 |
| #define CMDQ_EVENT_MDPSYS1_MDP_RSZ1_FRAME_DONE 26 |
| #define CMDQ_EVENT_MDPSYS1_MDP_RSZ0_FRAME_DONE 27 |
| #define CMDQ_EVENT_MDPSYS1_MDP_RDMA1_FRAME_DONE 28 |
| #define CMDQ_EVENT_MDPSYS1_MDP_RDMA0_FRAME_DONE 29 |
| #define CMDQ_EVENT_MDPSYS1_MDP_HDR1_FRAME_DONE 30 |
| #define CMDQ_EVENT_MDPSYS1_MDP_HDR0_FRAME_DONE 31 |
| #define CMDQ_EVENT_MDPSYS1_MDP_FG1_FRAME_DONE 32 |
| #define CMDQ_EVENT_MDPSYS1_MDP_FG0_FRAME_DONE 33 |
| #define CMDQ_EVENT_MDPSYS1_MDP_COLOR1_FRAME_DONE 34 |
| #define CMDQ_EVENT_MDPSYS1_MDP_COLOR0_FRAME_DONE 35 |
| #define CMDQ_EVENT_MDPSYS1_MDP_AAL1_FRAME_DONE 36 |
| #define CMDQ_EVENT_MDPSYS1_MDP_AAL0_FRAME_DONE 37 |
| #define CMDQ_EVENT_MDPSYS1_STREAM_DONE_ENG_EVENT_0 38 |
| #define CMDQ_EVENT_MDPSYS1_STREAM_DONE_ENG_EVENT_1 39 |
| #define CMDQ_EVENT_MDPSYS1_STREAM_DONE_ENG_EVENT_2 40 |
| #define CMDQ_EVENT_MDPSYS1_STREAM_DONE_ENG_EVENT_3 41 |
| #define CMDQ_EVENT_MDPSYS1_STREAM_DONE_ENG_EVENT_4 42 |
| #define CMDQ_EVENT_MDPSYS1_STREAM_DONE_ENG_EVENT_5 43 |
| #define CMDQ_EVENT_MDPSYS1_STREAM_DONE_ENG_EVENT_6 44 |
| #define CMDQ_EVENT_MDPSYS1_STREAM_DONE_ENG_EVENT_7 45 |
| #define CMDQ_EVENT_MDPSYS1_STREAM_DONE_ENG_EVENT_8 46 |
| #define CMDQ_EVENT_MDPSYS1_STREAM_DONE_ENG_EVENT_9 47 |
| #define CMDQ_EVENT_MDPSYS1_STREAM_DONE_ENG_EVENT_10 48 |
| #define CMDQ_EVENT_MDPSYS1_STREAM_DONE_ENG_EVENT_11 49 |
| #define CMDQ_EVENT_MDPSYS1_STREAM_DONE_ENG_EVENT_12 50 |
| #define CMDQ_EVENT_MDPSYS1_STREAM_DONE_ENG_EVENT_13 51 |
| #define CMDQ_EVENT_MDPSYS1_STREAM_DONE_ENG_EVENT_14 52 |
| #define CMDQ_EVENT_MDPSYS1_STREAM_DONE_ENG_EVENT_15 53 |
| #define CMDQ_EVENT_MDPSYS1_MDP_WROT3_SW_RST_DONE_ENG_EVENT 54 |
| #define CMDQ_EVENT_MDPSYS1_MDP_WROT2_SW_RST_DONE_ENG_EVENT 55 |
| #define CMDQ_EVENT_MDPSYS1_MDP_WROT1_SW_RST_DONE_ENG_EVENT 56 |
| #define CMDQ_EVENT_MDPSYS1_MDP_WROT0_SW_RST_DONE_ENG_EVENT 57 |
| #define CMDQ_EVENT_MDPSYS1_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 58 |
| #define CMDQ_EVENT_MDPSYS1_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 59 |
| #define CMDQ_EVENT_MDPSYS1_BUF_UNDERRUN_ENG_EVENT_0 60 |
| #define CMDQ_EVENT_MDPSYS1_BUF_UNDERRUN_ENG_EVENT_1 61 |
| #define CMDQ_EVENT_MDPSYS1_BUF_UNDERRUN_ENG_EVENT_2 62 |
| #define CMDQ_EVENT_MDPSYS1_BUF_UNDERRUN_ENG_EVENT_3 63 |
| |
| #define CMDQ_EVENT_MDPSYS0_MDP_RDMA0_SOF 64 |
| #define CMDQ_EVENT_MDPSYS0_MDP_RDMA1_SOF 65 |
| #define CMDQ_EVENT_MDPSYS0_MDP_TDSHP0_SOF 66 |
| #define CMDQ_EVENT_MDPSYS0_MDP_TDSHP1_SOF 67 |
| #define CMDQ_EVENT_MDPSYS0_MDP_COLOR0_SOF 68 |
| #define CMDQ_EVENT_MDPSYS0_MDP_COLOR1_SOF 69 |
| #define CMDQ_EVENT_MDPSYS0_MDP_WROT0_SOF 70 |
| #define CMDQ_EVENT_MDPSYS0_MDP_WROT1_SOF 71 |
| #define CMDQ_EVENT_MDPSYS0_MDP_FG0_SOF 72 |
| #define CMDQ_EVENT_MDPSYS0_MDP_FG1_SOF 73 |
| #define CMDQ_EVENT_MDPSYS0_MDP_DLI_ASYNC0_SOF 74 |
| #define CMDQ_EVENT_MDPSYS0_MDP_DLI_ASYNC1_SOF 75 |
| #define CMDQ_EVENT_MDPSYS0_MDP_DLO_ASYNC0_SOF 76 |
| #define CMDQ_EVENT_MDPSYS0_MDP_DLO_ASYNC1_SOF 77 |
| #define CMDQ_EVENT_MDPSYS0_MDP_RSZ2_SOF 78 |
| #define CMDQ_EVENT_MDPSYS0_MDP_RSZ3_SOF 79 |
| #define CMDQ_EVENT_MDPSYS0_MDP_WROT2_SOF 80 |
| #define CMDQ_EVENT_MDPSYS0_MDP_WROT3_SOF 81 |
| #define CMDQ_EVENT_MDPSYS0_MDP_WROT3_FRAME_DONE 82 |
| #define CMDQ_EVENT_MDPSYS0_MDP_WROT2_FRAME_DONE 83 |
| #define CMDQ_EVENT_MDPSYS0_MDP_WROT1_FRAME_DONE 84 |
| #define CMDQ_EVENT_MDPSYS0_MDP_WROT0_FRAME_DONE 85 |
| #define CMDQ_EVENT_MDPSYS0_MDP_TDSHP1_FRAME_DONE 86 |
| #define CMDQ_EVENT_MDPSYS0_MDP_TDSHP0_FRAME_DONE 87 |
| #define CMDQ_EVENT_MDPSYS0_MDP_RSZ3_FRAME_DONE 88 |
| #define CMDQ_EVENT_MDPSYS0_MDP_RSZ2_FRAME_DONE 89 |
| #define CMDQ_EVENT_MDPSYS0_MDP_RSZ1_FRAME_DONE 90 |
| #define CMDQ_EVENT_MDPSYS0_MDP_RSZ0_FRAME_DONE 91 |
| #define CMDQ_EVENT_MDPSYS0_MDP_RDMA1_FRAME_DONE 92 |
| #define CMDQ_EVENT_MDPSYS0_MDP_RDMA0_FRAME_DONE 93 |
| #define CMDQ_EVENT_MDPSYS0_MDP_HDR1_FRAME_DONE 94 |
| #define CMDQ_EVENT_MDPSYS0_MDP_HDR0_FRAME_DONE 95 |
| #define CMDQ_EVENT_MDPSYS0_MDP_FG1_FRAME_DONE 96 |
| #define CMDQ_EVENT_MDPSYS0_MDP_FG0_FRAME_DONE 97 |
| #define CMDQ_EVENT_MDPSYS0_MDP_COLOR1_FRAME_DONE 98 |
| #define CMDQ_EVENT_MDPSYS0_MDP_COLOR0_FRAME_DONE 99 |
| #define CMDQ_EVENT_MDPSYS0_MDP_AAL1_FRAME_DONE 100 |
| #define CMDQ_EVENT_MDPSYS0_MDP_AAL0_FRAME_DONE 101 |
| #define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_0 102 |
| #define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_1 103 |
| #define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_2 104 |
| #define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_3 105 |
| #define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_4 106 |
| #define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_5 107 |
| #define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_6 108 |
| #define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_7 109 |
| #define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_8 110 |
| #define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_9 111 |
| #define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_10 112 |
| #define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_11 113 |
| #define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_12 114 |
| #define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_13 115 |
| #define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_14 116 |
| #define CMDQ_EVENT_MDPSYS0_STREAM_DONE_ENG_EVENT_15 117 |
| #define CMDQ_EVENT_MDPSYS0_MDP_WROT3_SW_RST_DONE_ENG_EVENT 118 |
| #define CMDQ_EVENT_MDPSYS0_MDP_WROT2_SW_RST_DONE_ENG_EVENT 119 |
| #define CMDQ_EVENT_MDPSYS0_MDP_WROT1_SW_RST_DONE_ENG_EVENT 120 |
| #define CMDQ_EVENT_MDPSYS0_MDP_WROT0_SW_RST_DONE_ENG_EVENT 121 |
| #define CMDQ_EVENT_MDPSYS0_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 122 |
| #define CMDQ_EVENT_MDPSYS0_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 123 |
| #define CMDQ_EVENT_MDPSYS0_BUF_UNDERRUN_ENG_EVENT_0 124 |
| #define CMDQ_EVENT_MDPSYS0_BUF_UNDERRUN_ENG_EVENT_1 125 |
| #define CMDQ_EVENT_MDPSYS0_BUF_UNDERRUN_ENG_EVENT_2 126 |
| #define CMDQ_EVENT_MDPSYS0_BUF_UNDERRUN_ENG_EVENT_3 127 |
| #define CMDQ_EVENT_DPTX_IRQ_OUT_GCE_0 130 |
| #define CMDQ_EVENT_DPTX_IRQ_OUT_GCE_1 131 |
| |
| #define CMDQ_EVENT_MMSYS_DISP_OVL0_SOF 256 |
| #define CMDQ_EVENT_MMSYS_DISP_OVL0_2L_SOF 257 |
| #define CMDQ_EVENT_MMSYS_DISP_OVL1_2L_SOF 258 |
| #define CMDQ_EVENT_MMSYS_DISP_RSZ0_SOF 259 |
| #define CMDQ_EVENT_MMSYS_DISP_RDMA0_SOF 260 |
| #define CMDQ_EVENT_MMSYS_DISP_TDSHP0_SOF 261 |
| #define CMDQ_EVENT_MMSYS_DISP_C3D0_SOF 262 |
| #define CMDQ_EVENT_MMSYS_DISP_COLOR0_SOF 263 |
| #define CMDQ_EVENT_MMSYS_DISP_CCORR0_SOF 264 |
| #define CMDQ_EVENT_MMSYS_DISP_CCORR1_SOF 265 |
| #define CMDQ_EVENT_MMSYS_DISP_MDP_AAL0_SOF 266 |
| #define CMDQ_EVENT_MMSYS_DISP_AAL0_SOF 267 |
| #define CMDQ_EVENT_MMSYS_DSI0_TARGET_LINE 268 |
| #define CMDQ_EVENT_MMSYS_DISP_POSTMASK0_SOF 269 |
| #define CMDQ_EVENT_MMSYS_DISP_DITHER0_SOF 270 |
| #define CMDQ_EVENT_MMSYS_DISP_CHIST0_SOF 271 |
| #define CMDQ_EVENT_MMSYS_DISP_CHIST1_SOF 272 |
| #define CMDQ_EVENT_MMSYS_DISP_CM0_SOF 273 |
| #define CMDQ_EVENT_MMSYS_DISP_SPR0_SOF 274 |
| #define CMDQ_EVENT_MMSYS_DISP_DSC_WRAP0_CORE0_SOF 275 |
| #define CMDQ_EVENT_MMSYS_DISP_DSC_WRAP0_CORE1_SOF 276 |
| #define CMDQ_EVENT_MMSYS_DISP_MERGE0_SOF 277 |
| #define CMDQ_EVENT_MMSYS_DISP_DSI0_SOF 278 |
| #define CMDQ_EVENT_MMSYS_DISP_WDMA0_SOF 279 |
| #define CMDQ_EVENT_MMSYS_DISP_UFBC_WDMA0_SOF 280 |
| #define CMDQ_EVENT_MMSYS_DISP_OVL0_2L_NWCG_SOF 281 |
| #define CMDQ_EVENT_MMSYS_DISP_OVL1_2L_NWCG_SOF 282 |
| #define CMDQ_EVENT_MMSYS_DISP_RDMA1_SOF 283 |
| #define CMDQ_EVENT_MMSYS_DISP_DP_INTF0_SOF 284 |
| #define CMDQ_EVENT_MMSYS_DISP_DPI0_SOF 285 |
| #define CMDQ_EVENT_MMSYS_DISP_WDMA1_SOF 286 |
| #define CMDQ_EVENT_MMSYS_DISP_Y2R0_SOF 287 |
| #define CMDQ_EVENT_MMSYS_INLINEROT0_SOF 288 |
| #define CMDQ_EVENT_MMSYS_DISP_DLI_ASYNC0_SOF 289 |
| #define CMDQ_EVENT_MMSYS_DISP_DLI_ASYNC1_SOF 290 |
| #define CMDQ_EVENT_MMSYS_DISP_DLI_ASYNC2_SOF 291 |
| #define CMDQ_EVENT_MMSYS_DISP_DLI_ASYNC3_SOF 292 |
| #define CMDQ_EVENT_MMSYS_DISP_DLO_ASYNC0_SOF 293 |
| #define CMDQ_EVENT_MMSYS_DISP_DLO_ASYNC1_SOF 294 |
| #define CMDQ_EVENT_MMSYS_DISP_DLO_ASYNC2_SOF 295 |
| #define CMDQ_EVENT_MMSYS_DISP_DLO_ASYNC3_SOF 296 |
| #define CMDQ_EVENT_MMSYS_DISP_PWM0_SOF 297 |
| #define CMDQ_EVENT_MMSYS_PMSR_MOD_FRAME_DONE_0 301 |
| #define CMDQ_EVENT_MMSYS_PMSR_MOD_FRAME_DONE_1 302 |
| #define CMDQ_EVENT_MMSYS_PMSR_MOD_FRAME_DONE_2 303 |
| #define CMDQ_EVENT_MMSYS_PMSR_MOD_FRAME_DONE_3 304 |
| #define CMDQ_EVENT_MMSYS_PMSR_MOD_FRAME_DONE_4 305 |
| #define CMDQ_EVENT_MMSYS_PMSR_MOD_FRAME_DONE_5 306 |
| #define CMDQ_EVENT_MMSYS_PMSR_MOD_FRAME_DONE_6 307 |
| #define CMDQ_EVENT_MMSYS_PMSR_MOD_FRAME_DONE_7 308 |
| #define CMDQ_EVENT_MMSYS_PMSR_MOD_FRAME_DONE_8 309 |
| #define CMDQ_EVENT_MMSYS_PMSR_MOD_FRAME_DONE_9 310 |
| #define CMDQ_EVENT_MMSYS_PMSR_MOD_FRAME_DONE_10 311 |
| #define CMDQ_EVENT_MMSYS_PMSR_MOD_FRAME_DONE_11 312 |
| #define CMDQ_EVENT_MMSYS_DSI0_FRAME_DONE 313 |
| #define CMDQ_EVENT_MMSYS_DP_INTF0_FRAME_DONE 314 |
| #define CMDQ_EVENT_MMSYS_DISP_WDMA1_FRAME_DONE 315 |
| #define CMDQ_EVENT_MMSYS_DISP_WDMA0_FRAME_DONE 316 |
| #define CMDQ_EVENT_MMSYS_DISP_UFBC_WDMA0_FRAME_DONE 317 |
| #define CMDQ_EVENT_MMSYS_DISP_TDSHP0_FRAME_DONE 318 |
| #define CMDQ_EVENT_MMSYS_DISP_SPR0_FRAME_DONE 319 |
| #define CMDQ_EVENT_MMSYS_DISP_RSZ0_FRAME_DONE 320 |
| #define CMDQ_EVENT_MMSYS_DISP_RDMA1_FRAME_DONE 321 |
| #define CMDQ_EVENT_MMSYS_DISP_RDMA0_FRAME_DONE 322 |
| #define CMDQ_EVENT_MMSYS_DISP_POSTMASK0_FRAME_DONE 323 |
| #define CMDQ_EVENT_MMSYS_DISP_OVL1_2L_NWCG_FRAME_DONE 324 |
| #define CMDQ_EVENT_MMSYS_DISP_OVL1_2L_FRAME_DONE 325 |
| #define CMDQ_EVENT_MMSYS_DISP_OVL0_FRAME_DONE 326 |
| #define CMDQ_EVENT_MMSYS_DISP_OVL0_2L_NWCG_FRAME_DONE 327 |
| #define CMDQ_EVENT_MMSYS_DISP_OVL0_2L_FRAME_DONE 328 |
| #define CMDQ_EVENT_MMSYS_DISP_MERGE0_FRAME_DONE 329 |
| #define CMDQ_EVENT_MMSYS_DISP_MDP_AAL0_FRAME_DONE 330 |
| #define CMDQ_EVENT_MMSYS_DISP_GAMMA0_FRAME_DONE 331 |
| #define CMDQ_EVENT_MMSYS_DISP_DSC_WRAP0_CORE1_FRAME_DONE 332 |
| #define CMDQ_EVENT_MMSYS_DISP_DSC_WRAP0_CORE0_FRAME_DONE 333 |
| #define CMDQ_EVENT_MMSYS_DISP_DPI0_FRAME_DONE 334 |
| #define CMDQ_EVENT_MMSYS_DISP_DITHER0_FRAME_DONE 335 |
| #define CMDQ_EVENT_MMSYS_DISP_COLOR0_FRAME_DONE 336 |
| #define CMDQ_EVENT_MMSYS_DISP_CM0_FRAME_DONE 337 |
| #define CMDQ_EVENT_MMSYS_DISP_CHIST1_FRAME_DONE 338 |
| #define CMDQ_EVENT_MMSYS_DISP_CHIST0_FRAME_DONE 339 |
| #define CMDQ_EVENT_MMSYS_DISP_CCORR1_FRAME_DONE 340 |
| #define CMDQ_EVENT_MMSYS_DISP_CCORR0_FRAME_DONE 341 |
| #define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_0 342 |
| #define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_1 343 |
| #define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_2 344 |
| #define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_3 345 |
| #define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_4 346 |
| #define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_5 347 |
| #define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_6 348 |
| #define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_7 349 |
| #define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_8 350 |
| #define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_9 351 |
| #define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_10 352 |
| #define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_11 353 |
| #define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_12 354 |
| #define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_13 355 |
| #define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_14 356 |
| #define CMDQ_EVENT_MMSYS_STREAM_DONE_ENG_EVENT_15 357 |
| #define CMDQ_EVENT_MMSYS_DSI0_TE_ENG_EVENT 358 |
| #define CMDQ_EVENT_MMSYS_DSI0_IRQ_ENG_EVENT 359 |
| #define CMDQ_EVENT_MMSYS_DSI0_DONE_ENG_EVENT 360 |
| #define CMDQ_EVENT_MMSYS_DP_VSYNC_START_ENG_EVENT 361 |
| #define CMDQ_EVENT_MMSYS_DP_VSYNC_END_ENG_EVENT 362 |
| #define CMDQ_EVENT_MMSYS_DP_VDE_START_ENG_EVENT 363 |
| #define CMDQ_EVENT_MMSYS_DP_VDE_END_ENG_EVENT 364 |
| #define CMDQ_EVENT_MMSYS_DP_TARGET_LINE_ENG_EVENT 365 |
| #define CMDQ_EVENT_MMSYS_DISP_WDMA1_SW_RST_DONE_ENG_EVENT 366 |
| #define CMDQ_EVENT_MMSYS_DISP_WDMA0_SW_RST_DONE_ENG_EVENT 367 |
| #define CMDQ_EVENT_MMSYS_DISP_RDMA1_TARGET_LINE_ENG_EVENT 368 |
| #define CMDQ_EVENT_MMSYS_DISP_RDMA0_TARGET_LINE_ENG_EVENT 369 |
| #define CMDQ_EVENT_MMSYS_DISP_POSTMASK0_RST_DONE_ENG_EVENT 370 |
| #define CMDQ_EVENT_MMSYS_DISP_OVL1_2L_RST_DONE_ENG_EVENT 371 |
| #define CMDQ_EVENT_MMSYS_DISP_OVL1_2L_NWCG_RST_DONE_ENG_EVENT 372 |
| #define CMDQ_EVENT_MMSYS_DISP_OVL0_RST_DONE_ENG_EVENT 373 |
| #define CMDQ_EVENT_MMSYS_DISP_OVL0_2L_RST_DONE_ENG_EVENT 374 |
| #define CMDQ_EVENT_MMSYS_DISP_OVL0_2L_NWCG_RST_DONE_ENG_EVENT 375 |
| #define CMDQ_EVENT_MMSYS_BUF_UNDERRUN_ENG_EVENT_0 376 |
| #define CMDQ_EVENT_MMSYS_BUF_UNDERRUN_ENG_EVENT_1 377 |
| #define CMDQ_EVENT_MMSYS_BUF_UNDERRUN_ENG_EVENT_2 378 |
| #define CMDQ_EVENT_MMSYS_BUF_UNDERRUN_ENG_EVENT_3 379 |
| #define CMDQ_EVENT_MMSYS_BUF_UNDERRUN_ENG_EVENT_4 380 |
| #define CMDQ_EVENT_MMSYS_BUF_UNDERRUN_ENG_EVENT_5 381 |
| #define CMDQ_EVENT_MMSYS_BUF_UNDERRUN_ENG_EVENT_6 382 |
| #define CMDQ_EVENT_MMSYS_BUF_UNDERRUN_ENG_EVENT_7 383 |
| #define CMDQ_EVENT_MMSYS1_DISP_OVL0_SOF 384 |
| #define CMDQ_EVENT_MMSYS1_DISP_OVL0_2L_SOF 385 |
| #define CMDQ_EVENT_MMSYS1_DISP_OVL1_2L_SOF 386 |
| #define CMDQ_EVENT_MMSYS1_DISP_RSZ0_SOF 387 |
| #define CMDQ_EVENT_MMSYS1_DISP_RDMA0_SOF 388 |
| #define CMDQ_EVENT_MMSYS1_DISP_TDSHP0_SOF 389 |
| #define CMDQ_EVENT_MMSYS1_DISP_C3D0_SOF 390 |
| #define CMDQ_EVENT_MMSYS1_DISP_COLOR0_SOF 391 |
| #define CMDQ_EVENT_MMSYS1_DISP_CCORR0_SOF 392 |
| #define CMDQ_EVENT_MMSYS1_DISP_CCORR1_SOF 393 |
| #define CMDQ_EVENT_MMSYS1_DISP_MDP_AAL0_SOF 394 |
| #define CMDQ_EVENT_MMSYS1_DISP_AAL0_SOF 395 |
| #define CMDQ_EVENT_MMSYS1_DSI0_TARGET_LINE 396 |
| #define CMDQ_EVENT_MMSYS1_DISP_POSTMASK0_SOF 397 |
| #define CMDQ_EVENT_MMSYS1_DISP_DITHER0_SOF 398 |
| #define CMDQ_EVENT_MMSYS1_DISP_CHIST0_SOF 399 |
| #define CMDQ_EVENT_MMSYS1_DISP_CHIST1_SOF 400 |
| #define CMDQ_EVENT_MMSYS1_DISP_CM0_SOF 401 |
| #define CMDQ_EVENT_MMSYS1_DISP_SPR0_SOF 402 |
| #define CMDQ_EVENT_MMSYS1_DISP_DSC_WRAP0_CORE0_SOF 403 |
| #define CMDQ_EVENT_MMSYS1_DISP_DSC_WRAP0_CORE1_SOF 404 |
| #define CMDQ_EVENT_MMSYS1_DISP_MERGE0_SOF 405 |
| #define CMDQ_EVENT_MMSYS1_DISP_DSI0_SOF 406 |
| #define CMDQ_EVENT_MMSYS1_DISP_WDMA0_SOF 407 |
| #define CMDQ_EVENT_MMSYS1_DISP_UFBC_WDMA0_SOF 408 |
| #define CMDQ_EVENT_MMSYS1_DISP_OVL0_2L_NWCG_SOF 409 |
| #define CMDQ_EVENT_MMSYS1_DISP_OVL1_2L_NWCG_SOF 410 |
| #define CMDQ_EVENT_MMSYS1_DISP_RDMA1_SOF 411 |
| #define CMDQ_EVENT_MMSYS1_DISP_DP_INTF0_SOF 412 |
| #define CMDQ_EVENT_MMSYS1_DISP_DPI0_SOF 413 |
| #define CMDQ_EVENT_MMSYS1_DISP_WDMA1_SOF 414 |
| #define CMDQ_EVENT_MMSYS1_DISP_Y2R0_SOF 415 |
| #define CMDQ_EVENT_MMSYS1_INLINEROT0_SOF 416 |
| #define CMDQ_EVENT_MMSYS1_DISP_DLI_ASYNC0_SOF 417 |
| #define CMDQ_EVENT_MMSYS1_DISP_DLI_ASYNC1_SOF 418 |
| #define CMDQ_EVENT_MMSYS1_DISP_DLI_ASYNC2_SOF 419 |
| #define CMDQ_EVENT_MMSYS1_DISP_DLI_ASYNC3_SOF 420 |
| #define CMDQ_EVENT_MMSYS1_DISP_DLO_ASYNC0_SOF 421 |
| #define CMDQ_EVENT_MMSYS1_DISP_DLO_ASYNC1_SOF 422 |
| #define CMDQ_EVENT_MMSYS1_DISP_DLO_ASYNC2_SOF 423 |
| #define CMDQ_EVENT_MMSYS1_DISP_DLO_ASYNC3_SOF 424 |
| #define CMDQ_EVENT_MMSYS1_DISP_PWM0_SOF 425 |
| #define CMDQ_EVENT_MMSYS1_PMSR_MOD_FRAME_DONE_0 429 |
| #define CMDQ_EVENT_MMSYS1_PMSR_MOD_FRAME_DONE_1 430 |
| #define CMDQ_EVENT_MMSYS1_PMSR_MOD_FRAME_DONE_2 431 |
| #define CMDQ_EVENT_MMSYS1_PMSR_MOD_FRAME_DONE_3 432 |
| #define CMDQ_EVENT_MMSYS1_PMSR_MOD_FRAME_DONE_4 433 |
| #define CMDQ_EVENT_MMSYS1_PMSR_MOD_FRAME_DONE_5 434 |
| #define CMDQ_EVENT_MMSYS1_PMSR_MOD_FRAME_DONE_6 435 |
| #define CMDQ_EVENT_MMSYS1_PMSR_MOD_FRAME_DONE_7 436 |
| #define CMDQ_EVENT_MMSYS1_PMSR_MOD_FRAME_DONE_8 437 |
| #define CMDQ_EVENT_MMSYS1_PMSR_MOD_FRAME_DONE_9 438 |
| #define CMDQ_EVENT_MMSYS1_PMSR_MOD_FRAME_DONE_10 439 |
| #define CMDQ_EVENT_MMSYS1_PMSR_MOD_FRAME_DONE_11 440 |
| #define CMDQ_EVENT_MMSYS1_DSI0_FRAME_DONE 441 |
| #define CMDQ_EVENT_MMSYS1_DP_INTF0_FRAME_DONE 442 |
| #define CMDQ_EVENT_MMSYS1_DISP_WDMA1_FRAME_DONE 443 |
| #define CMDQ_EVENT_MMSYS1_DISP_WDMA0_FRAME_DONE 444 |
| #define CMDQ_EVENT_MMSYS1_DISP_UFBC_WDMA0_FRAME_DONE 445 |
| #define CMDQ_EVENT_MMSYS1_DISP_TDSHP0_FRAME_DONE 446 |
| #define CMDQ_EVENT_MMSYS1_DISP_SPR0_FRAME_DONE 447 |
| #define CMDQ_EVENT_MMSYS1_DISP_RSZ0_FRAME_DONE 448 |
| #define CMDQ_EVENT_MMSYS1_DISP_RDMA1_FRAME_DONE 449 |
| #define CMDQ_EVENT_MMSYS1_DISP_RDMA0_FRAME_DONE 450 |
| #define CMDQ_EVENT_MMSYS1_DISP_POSTMASK0_FRAME_DONE 451 |
| #define CMDQ_EVENT_MMSYS1_DISP_OVL1_2L_NWCG_FRAME_DONE 452 |
| #define CMDQ_EVENT_MMSYS1_DISP_OVL1_2L_FRAME_DONE 453 |
| #define CMDQ_EVENT_MMSYS1_DISP_OVL0_FRAME_DONE 454 |
| #define CMDQ_EVENT_MMSYS1_DISP_OVL0_2L_NWCG_FRAME_DONE 455 |
| #define CMDQ_EVENT_MMSYS1_DISP_OVL0_2L_FRAME_DONE 456 |
| #define CMDQ_EVENT_MMSYS1_DISP_MERGE0_FRAME_DONE 457 |
| #define CMDQ_EVENT_MMSYS1_DISP_MDP_AAL0_FRAME_DONE 458 |
| #define CMDQ_EVENT_MMSYS1_DISP_GAMMA0_FRAME_DONE 459 |
| #define CMDQ_EVENT_MMSYS1_DISP_DSC_WRAP0_CORE1_FRAME_DONE 460 |
| #define CMDQ_EVENT_MMSYS1_DISP_DSC_WRAP0_CORE0_FRAME_DONE 461 |
| #define CMDQ_EVENT_MMSYS1_DISP_DPI0_FRAME_DONE 462 |
| #define CMDQ_EVENT_MMSYS1_DISP_DITHER0_FRAME_DONE 463 |
| #define CMDQ_EVENT_MMSYS1_DISP_COLOR0_FRAME_DONE 464 |
| #define CMDQ_EVENT_MMSYS1_DISP_CM0_FRAME_DONE 465 |
| #define CMDQ_EVENT_MMSYS1_DISP_CHIST1_FRAME_DONE 466 |
| #define CMDQ_EVENT_MMSYS1_DISP_CHIST0_FRAME_DONE 467 |
| #define CMDQ_EVENT_MMSYS1_DISP_CCORR1_FRAME_DONE 468 |
| #define CMDQ_EVENT_MMSYS1_DISP_CCORR0_FRAME_DONE 469 |
| #define CMDQ_EVENT_MMSYS1_STREAM_DONE_ENG_EVENT_0 470 |
| #define CMDQ_EVENT_MMSYS1_STREAM_DONE_ENG_EVENT_1 471 |
| #define CMDQ_EVENT_MMSYS1_STREAM_DONE_ENG_EVENT_2 472 |
| #define CMDQ_EVENT_MMSYS1_STREAM_DONE_ENG_EVENT_3 473 |
| #define CMDQ_EVENT_MMSYS1_STREAM_DONE_ENG_EVENT_4 474 |
| #define CMDQ_EVENT_MMSYS1_STREAM_DONE_ENG_EVENT_5 475 |
| #define CMDQ_EVENT_MMSYS1_STREAM_DONE_ENG_EVENT_6 476 |
| #define CMDQ_EVENT_MMSYS1_STREAM_DONE_ENG_EVENT_7 477 |
| #define CMDQ_EVENT_MMSYS1_STREAM_DONE_ENG_EVENT_8 478 |
| #define CMDQ_EVENT_MMSYS1_STREAM_DONE_ENG_EVENT_9 479 |
| #define CMDQ_EVENT_MMSYS1_STREAM_DONE_ENG_EVENT_10 480 |
| #define CMDQ_EVENT_MMSYS1_STREAM_DONE_ENG_EVENT_11 481 |
| #define CMDQ_EVENT_MMSYS1_STREAM_DONE_ENG_EVENT_12 482 |
| #define CMDQ_EVENT_MMSYS1_STREAM_DONE_ENG_EVENT_13 483 |
| #define CMDQ_EVENT_MMSYS1_STREAM_DONE_ENG_EVENT_14 484 |
| #define CMDQ_EVENT_MMSYS1_STREAM_DONE_ENG_EVENT_15 485 |
| #define CMDQ_EVENT_MMSYS1_DSI0_TE_ENG_EVENT 486 |
| #define CMDQ_EVENT_MMSYS1_DSI0_IRQ_ENG_EVENT 487 |
| #define CMDQ_EVENT_MMSYS1_DSI0_DONE_ENG_EVENT 488 |
| #define CMDQ_EVENT_MMSYS1_DP_VSYNC_START_ENG_EVENT 489 |
| #define CMDQ_EVENT_MMSYS1_DP_VSYNC_END_ENG_EVENT 490 |
| #define CMDQ_EVENT_MMSYS1_DP_VDE_START_ENG_EVENT 491 |
| #define CMDQ_EVENT_MMSYS1_DP_VDE_END_ENG_EVENT 492 |
| #define CMDQ_EVENT_MMSYS1_DP_TARGET_LINE_ENG_EVENT 493 |
| #define CMDQ_EVENT_MMSYS1_DISP_WDMA1_SW_RST_DONE_ENG_EVENT 494 |
| #define CMDQ_EVENT_MMSYS1_DISP_WDMA0_SW_RST_DONE_ENG_EVENT 495 |
| #define CMDQ_EVENT_MMSYS1_DISP_RDMA1_TARGET_LINE_ENG_EVENT 496 |
| #define CMDQ_EVENT_MMSYS1_DISP_RDMA0_TARGET_LINE_ENG_EVENT 497 |
| #define CMDQ_EVENT_MMSYS1_DISP_POSTMASK0_RST_DONE_ENG_EVENT 498 |
| #define CMDQ_EVENT_MMSYS1_DISP_OVL1_2L_RST_DONE_ENG_EVENT 499 |
| #define CMDQ_EVENT_MMSYS1_DISP_OVL1_2L_NWCG_RST_DONE_ENG_EVENT 500 |
| #define CMDQ_EVENT_MMSYS1_DISP_OVL0_RST_DONE_ENG_EVENT 501 |
| #define CMDQ_EVENT_MMSYS1_DISP_OVL0_2L_RST_DONE_ENG_EVENT 502 |
| #define CMDQ_EVENT_MMSYS1_DISP_OVL0_2L_NWCG_RST_DONE_ENG_EVENT 503 |
| #define CMDQ_EVENT_MMSYS1_BUF_UNDERRUN_ENG_EVENT_0 504 |
| #define CMDQ_EVENT_MMSYS1_BUF_UNDERRUN_ENG_EVENT_1 505 |
| #define CMDQ_EVENT_MMSYS1_BUF_UNDERRUN_ENG_EVENT_2 506 |
| #define CMDQ_EVENT_MMSYS1_BUF_UNDERRUN_ENG_EVENT_3 507 |
| #define CMDQ_EVENT_MMSYS1_BUF_UNDERRUN_ENG_EVENT_4 508 |
| #define CMDQ_EVENT_MMSYS1_BUF_UNDERRUN_ENG_EVENT_5 509 |
| #define CMDQ_EVENT_MMSYS1_BUF_UNDERRUN_ENG_EVENT_6 510 |
| #define CMDQ_EVENT_MMSYS1_BUF_UNDERRUN_ENG_EVENT_7 511 |
| #define CMDQ_EVENT_GCE_EVENT_DSI0_TE_I 898 |
| #define CMDQ_EVENT_GCE_EVENT_DSI1_TE_I 899 |
| |
| /* GCE-M hardware events */ |
| #define CMDQ_EVENT_VENC2_EVENT_0 0 |
| #define CMDQ_EVENT_VENC2_EVENT_1 1 |
| #define CMDQ_EVENT_VENC2_EVENT_2 2 |
| #define CMDQ_EVENT_VENC2_EVENT_3 3 |
| #define CMDQ_EVENT_VENC2_EVENT_4 4 |
| #define CMDQ_EVENT_VENC2_EVENT_5 5 |
| #define CMDQ_EVENT_VENC2_EVENT_6 6 |
| #define CMDQ_EVENT_VENC2_EVENT_7 7 |
| #define CMDQ_EVENT_VENC2_EVENT_8 8 |
| #define CMDQ_EVENT_VENC2_EVENT_9 9 |
| #define CMDQ_EVENT_VENC2_EVENT_10 10 |
| #define CMDQ_EVENT_VENC2_EVENT_11 11 |
| #define CMDQ_EVENT_VENC2_EVENT_12 12 |
| #define CMDQ_EVENT_VENC2_EVENT_13 13 |
| #define CMDQ_EVENT_VENC2_EVENT_14 14 |
| #define CMDQ_EVENT_VENC2_EVENT_15 15 |
| #define CMDQ_EVENT_VENC2_EVENT_16 16 |
| #define CMDQ_EVENT_VENC1_EVENT_0 32 |
| #define CMDQ_EVENT_VENC1_EVENT_1 33 |
| #define CMDQ_EVENT_VENC1_EVENT_2 34 |
| #define CMDQ_EVENT_VENC1_EVENT_3 35 |
| #define CMDQ_EVENT_VENC1_EVENT_4 36 |
| #define CMDQ_EVENT_VENC1_EVENT_5 37 |
| #define CMDQ_EVENT_VENC1_EVENT_6 38 |
| #define CMDQ_EVENT_VENC1_EVENT_7 39 |
| #define CMDQ_EVENT_VENC1_EVENT_8 40 |
| #define CMDQ_EVENT_VENC1_EVENT_9 41 |
| #define CMDQ_EVENT_VENC1_EVENT_10 42 |
| #define CMDQ_EVENT_VENC1_EVENT_11 43 |
| #define CMDQ_EVENT_VENC1_EVENT_12 44 |
| #define CMDQ_EVENT_VENC1_EVENT_13 45 |
| #define CMDQ_EVENT_VENC1_EVENT_14 46 |
| #define CMDQ_EVENT_VENC1_EVENT_15 47 |
| #define CMDQ_EVENT_VENC1_EVENT_16 48 |
| |
| #define CMDQ_EVENT_VDEC2_EVENT_0 64 |
| #define CMDQ_EVENT_VDEC2_EVENT_1 65 |
| #define CMDQ_EVENT_VDEC2_EVENT_2 66 |
| #define CMDQ_EVENT_VDEC2_EVENT_3 67 |
| #define CMDQ_EVENT_VDEC2_EVENT_4 68 |
| #define CMDQ_EVENT_VDEC2_EVENT_5 69 |
| #define CMDQ_EVENT_VDEC2_EVENT_6 70 |
| #define CMDQ_EVENT_VDEC2_EVENT_7 71 |
| #define CMDQ_EVENT_VDEC2_EVENT_8 72 |
| #define CMDQ_EVENT_VDEC2_EVENT_9 73 |
| #define CMDQ_EVENT_VDEC2_EVENT_10 74 |
| #define CMDQ_EVENT_VDEC2_EVENT_11 75 |
| #define CMDQ_EVENT_VDEC2_EVENT_12 76 |
| #define CMDQ_EVENT_VDEC2_EVENT_13 77 |
| #define CMDQ_EVENT_VDEC2_EVENT_14 78 |
| #define CMDQ_EVENT_VDEC2_EVENT_15 79 |
| #define CMDQ_EVENT_VDEC1_EVENT_0 96 |
| #define CMDQ_EVENT_VDEC1_EVENT_1 97 |
| #define CMDQ_EVENT_VDEC1_EVENT_2 98 |
| #define CMDQ_EVENT_VDEC1_EVENT_3 99 |
| #define CMDQ_EVENT_VDEC1_EVENT_4 100 |
| #define CMDQ_EVENT_VDEC1_EVENT_5 101 |
| #define CMDQ_EVENT_VDEC1_EVENT_6 102 |
| #define CMDQ_EVENT_VDEC1_EVENT_7 103 |
| #define CMDQ_EVENT_VDEC1_EVENT_8 104 |
| #define CMDQ_EVENT_VDEC1_EVENT_9 105 |
| #define CMDQ_EVENT_VDEC1_EVENT_10 106 |
| #define CMDQ_EVENT_VDEC1_EVENT_11 107 |
| #define CMDQ_EVENT_VDEC1_EVENT_12 108 |
| #define CMDQ_EVENT_VDEC1_EVENT_13 109 |
| #define CMDQ_EVENT_VDEC1_EVENT_14 110 |
| #define CMDQ_EVENT_VDEC1_EVENT_15 111 |
| #define CMDQ_EVENT_VDEC1_EVENT_16 112 |
| #define CMDQ_EVENT_VDEC1_EVENT_17 113 |
| #define CMDQ_EVENT_VDEC1_EVENT_18 114 |
| #define CMDQ_EVENT_VDEC1_EVENT_19 115 |
| #define CMDQ_EVENT_VDEC1_EVENT_20 116 |
| #define CMDQ_EVENT_VDEC1_EVENT_21 117 |
| #define CMDQ_EVENT_VDEC1_EVENT_22 118 |
| #define CMDQ_EVENT_VDEC1_EVENT_23 119 |
| #define CMDQ_EVENT_VDEC1_EVENT_24 120 |
| #define CMDQ_EVENT_VDEC1_EVENT_25 121 |
| #define CMDQ_EVENT_VDEC1_EVENT_26 122 |
| #define CMDQ_EVENT_VDEC1_EVENT_27 123 |
| #define CMDQ_EVENT_VDEC1_EVENT_28 124 |
| #define CMDQ_EVENT_VDEC1_EVENT_29 125 |
| #define CMDQ_EVENT_VDEC1_EVENT_30 126 |
| #define CMDQ_EVENT_VDEC1_EVENT_31 127 |
| |
| #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_0 129 |
| #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_1 130 |
| #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_2 131 |
| #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_3 132 |
| #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_4 133 |
| #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_5 134 |
| #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_6 135 |
| #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_7 136 |
| #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_8 137 |
| #define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_TRAW0_9 138 |
| #define CMDQ_EVENT_IMG_TRAW0_DIP_DMA_ERR_EVENT 139 |
| #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_0 140 |
| #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_1 141 |
| #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_2 142 |
| #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_3 143 |
| #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_4 144 |
| #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_5 145 |
| #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_6 146 |
| #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_7 147 |
| #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_8 148 |
| #define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_TRAW0_9 149 |
| #define CMDQ_EVENT_IMG_TRAW1_DIP_DMA_ERR_EVENT 150 |
| #define CMDQ_EVENT_IMG_ADL_TILE_DONE_EVENT 151 |
| #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_0 152 |
| #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_1 153 |
| #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_2 154 |
| #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_3 155 |
| #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_4 156 |
| #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_5 157 |
| #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_6 158 |
| #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_7 159 |
| #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_8 160 |
| #define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_P2_9 161 |
| #define CMDQ_EVENT_IMG_DIP_DMA_ERR_EVENT 162 |
| #define CMDQ_EVENT_IMG_DIP_NR_DMA_ERR_EVENT 163 |
| #define CMDQ_EVENT_IMG_DIP_DUMMY_0 164 |
| #define CMDQ_EVENT_IMG_DIP_DUMMY_1 165 |
| #define CMDQ_EVENT_IMG_DIP_DUMMY_2 166 |
| #define CMDQ_EVENT_IMG_WPE_EIS_GCE_FRAME_DONE 167 |
| #define CMDQ_EVENT_IMG_WPE_EIS_DONE_SYNC_OUT 168 |
| #define CMDQ_EVENT_IMG_WOE_EIS_CQ_THR_DONE_P2_0 169 |
| #define CMDQ_EVENT_IMG_WOE_EIS_CQ_THR_DONE_P2_1 170 |
| #define CMDQ_EVENT_IMG_WOE_EIS_CQ_THR_DONE_P2_2 171 |
| #define CMDQ_EVENT_IMG_WOE_EIS_CQ_THR_DONE_P2_3 172 |
| #define CMDQ_EVENT_IMG_WOE_EIS_CQ_THR_DONE_P2_4 173 |
| #define CMDQ_EVENT_IMG_WOE_EIS_CQ_THR_DONE_P2_5 174 |
| #define CMDQ_EVENT_IMG_WOE_EIS_CQ_THR_DONE_P2_6 175 |
| #define CMDQ_EVENT_IMG_WOE_EIS_CQ_THR_DONE_P2_7 176 |
| #define CMDQ_EVENT_IMG_WOE_EIS_CQ_THR_DONE_P2_8 177 |
| #define CMDQ_EVENT_IMG_WOE_EIS_CQ_THR_DONE_P2_9 178 |
| #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_0 179 |
| #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_1 180 |
| #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_2 181 |
| #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_3 182 |
| #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_4 183 |
| #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_5 184 |
| #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_6 185 |
| #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_7 186 |
| #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_8 187 |
| #define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_P2_9 188 |
| #define CMDQ_EVENT_IMG_PQA_DMA_ERR_EVENT 189 |
| #define CMDQ_EVENT_IMG_WPE0_DUMMY_0 190 |
| #define CMDQ_EVENT_IMG_WPE0_DUMMY_1 191 |
| #define CMDQ_EVENT_IMG_WPE0_DUMMY_2 192 |
| #define CMDQ_EVENT_IMG_WPE_TNR_GCE_FRAME_DONE 193 |
| #define CMDQ_EVENT_IMG_WPE_TNR_DONE_SYNC_OUT 194 |
| #define CMDQ_EVENT_IMG_WOE_TNR_CQ_THR_DONE_P2_0 195 |
| #define CMDQ_EVENT_IMG_WOE_TNR_CQ_THR_DONE_P2_1 196 |
| #define CMDQ_EVENT_IMG_WOE_TNR_CQ_THR_DONE_P2_2 197 |
| #define CMDQ_EVENT_IMG_WOE_TNR_CQ_THR_DONE_P2_3 198 |
| #define CMDQ_EVENT_IMG_WOE_TNR_CQ_THR_DONE_P2_4 199 |
| #define CMDQ_EVENT_IMG_WOE_TNR_CQ_THR_DONE_P2_5 200 |
| #define CMDQ_EVENT_IMG_WOE_TNR_CQ_THR_DONE_P2_6 201 |
| #define CMDQ_EVENT_IMG_WOE_TNR_CQ_THR_DONE_P2_7 202 |
| #define CMDQ_EVENT_IMG_WOE_TNR_CQ_THR_DONE_P2_8 203 |
| #define CMDQ_EVENT_IMG_WOE_TNR_CQ_THR_DONE_P2_9 204 |
| #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_0 205 |
| #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_1 206 |
| #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_2 207 |
| #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_3 208 |
| #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_4 209 |
| #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_5 210 |
| #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_6 211 |
| #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_7 212 |
| #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_8 213 |
| #define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_P2_9 214 |
| #define CMDQ_EVENT_IMG_PQB_DMA_ERR_EVENT 215 |
| #define CMDQ_EVENT_IMG_WPE1_DUMMY_0 216 |
| #define CMDQ_EVENT_IMG_WPE1_DUMMY_1 217 |
| #define CMDQ_EVENT_IMG_WPE1_DUMMY_2 218 |
| #define CMDQ_EVENT_IMG_WPE_LITE_GCE_FRAME_DONE 219 |
| #define CMDQ_EVENT_IMG_WPE_LITE_DONE_SYNC_OUT 220 |
| #define CMDQ_EVENT_IMG_WOE_LITE_CQ_THR_DONE_P2_0 221 |
| #define CMDQ_EVENT_IMG_WOE_LITE_CQ_THR_DONE_P2_1 222 |
| #define CMDQ_EVENT_IMG_WOE_LITE_CQ_THR_DONE_P2_2 223 |
| #define CMDQ_EVENT_IMG_WOE_LITE_CQ_THR_DONE_P2_3 224 |
| #define CMDQ_EVENT_IMG_WOE_LITE_CQ_THR_DONE_P2_4 225 |
| #define CMDQ_EVENT_IMG_WOE_LITE_CQ_THR_DONE_P2_5 226 |
| #define CMDQ_EVENT_IMG_WOE_LITE_CQ_THR_DONE_P2_6 227 |
| #define CMDQ_EVENT_IMG_WOE_LITE_CQ_THR_DONE_P2_7 228 |
| #define CMDQ_EVENT_IMG_WOE_LITE_CQ_THR_DONE_P2_8 229 |
| #define CMDQ_EVENT_IMG_WOE_LITE_CQ_THR_DONE_P2_9 230 |
| #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_TRAW0_0 231 |
| #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_TRAW0_1 232 |
| #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_TRAW0_2 233 |
| #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_TRAW0_3 234 |
| #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_TRAW0_4 235 |
| #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_TRAW0_5 236 |
| #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_TRAW0_6 237 |
| #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_TRAW0_7 238 |
| #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_TRAW0_8 239 |
| #define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_TRAW0_9 240 |
| #define CMDQ_EVENT_IMG_XTRAW_DMA_ERR_EVENT 241 |
| #define CMDQ_EVENT_IMG_WPE2_DUMMY_0 242 |
| #define CMDQ_EVENT_IMG_WPE2_DUMMY_1 243 |
| #define CMDQ_EVENT_IMG_WPE2_DUMMY_2 244 |
| #define CMDQ_EVENT_IMG_IPE_DUMMY 245 |
| #define CMDQ_EVENT_IMG_IMGSYS_IPE_FDVT0_DONE 246 |
| #define CMDQ_EVENT_IMG_IMGSYS_IPE_ME_DONE 247 |
| #define CMDQ_EVENT_IMG_IMGSYS_IPE_DVS_DONE 248 |
| #define CMDQ_EVENT_IMG_IMGSYS_IPE_DVP_DONE 249 |
| #define CMDQ_EVENT_IMG_IMGSYS_IPE_FDVT1_DONE 250 |
| |
| #define CMDQ_EVENT_CAMSYS_CAMSUBA_SW_PASS1_DONE 385 |
| #define CMDQ_EVENT_CAMSYS_CAMSUBB_SW_PASS1_DONE 386 |
| #define CMDQ_EVENT_CAMSYS_CAMSUBC_SW_PASS1_DONE 387 |
| #define CMDQ_EVENT_CAMSYS_GCAMSV_A_1_SW_PASS1_DONE 388 |
| #define CMDQ_EVENT_CAMSYS_GCAMSV_A_2_SW_PASS1_DONE 389 |
| #define CMDQ_EVENT_CAMSYS_GCAMSV_B_1_SW_PASS1_DONE 390 |
| #define CMDQ_EVENT_CAMSYS_GCAMSV_B_2_SW_PASS1_DONE 391 |
| #define CMDQ_EVENT_CAMSYS_GCAMSV_C_1_SW_PASS1_DONE 392 |
| #define CMDQ_EVENT_CAMSYS_GCAMSV_C_2_SW_PASS1_DONE 393 |
| #define CMDQ_EVENT_CAMSYS_GCAMSV_D_1_SW_PASS1_DONE 394 |
| #define CMDQ_EVENT_CAMSYS_GCAMSV_D_2_SW_PASS1_DONE 395 |
| #define CMDQ_EVENT_CAMSYS_GCAMSV_E_1_SW_PASS1_DONE 396 |
| #define CMDQ_EVENT_CAMSYS_GCAMSV_E_2_SW_PASS1_DONE 397 |
| #define CMDQ_EVENT_CAMSYS_GCAMSV_F_1_SW_PASS1_DONE 398 |
| #define CMDQ_EVENT_CAMSYS_GCAMSV_F_2_SW_PASS1_DONE 399 |
| #define CMDQ_EVENT_CAMSYS_GCAMSV_G_1_SW_PASS1_DONE 400 |
| #define CMDQ_EVENT_CAMSYS_GCAMSV_G_2_SW_PASS1_DONE 401 |
| #define CMDQ_EVENT_CAMSYS_GCAMSV_H_1_SW_PASS1_DONE 402 |
| #define CMDQ_EVENT_CAMSYS_GCAMSV_H_2_SW_PASS1_DONE 403 |
| #define CMDQ_EVENT_CAMSYS_GCAMSV_I_1_SW_PASS1_DONE 404 |
| #define CMDQ_EVENT_CAMSYS_GCAMSV_I_2_SW_PASS1_DONE 405 |
| #define CMDQ_EVENT_CAMSYS_GCAMSV_J_1_SW_PASS1_DONE 406 |
| #define CMDQ_EVENT_CAMSYS_GCAMSV_J_2_SW_PASS1_DONE 407 |
| #define CMDQ_EVENT_CAMSYS_MRAW_0_SW_PASS1_DONE 408 |
| #define CMDQ_EVENT_CAMSYS_MRAW_1_SW_PASS1_DONE 409 |
| #define CMDQ_EVENT_CAMSYS_MRAW_2_SW_PASS1_DONE 410 |
| #define CMDQ_EVENT_CAMSYS_MRAW_3_SW_PASS1_DONE 411 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM0_FIFO_FULL 412 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM1_FIFO_FULL 413 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM2_FIFO_FULL 414 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM3_FIFO_FULL 415 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM4_FIFO_FULL 416 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM5_FIFO_FULL 417 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM6_FIFO_FULL 418 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM7_FIFO_FULL 419 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM8_FIFO_FULL 420 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM9_FIFO_FULL 421 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM10_FIFO_FULL 422 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM11_FIFO_FULL 423 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM12_FIFO_FULL 424 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM13_FIFO_FULL 425 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM14_FIFO_FULL 426 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM15_FIFO_FULL 427 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM16_FIFO_FULL 428 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM17_FIFO_FULL 429 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM18_FIFO_FULL 430 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM19_FIFO_FULL 431 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM20_FIFO_FULL 432 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM21_FIFO_FULL 433 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM22_FIFO_FULL 434 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM23_FIFO_FULL 435 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM24_FIFO_FULL 436 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM25_FIFO_FULL 437 |
| #define CMDQ_EVENT_CAMSYS_SENINF_CAM26_FIFO_FULL 438 |
| #define CMDQ_EVENT_CAMSYS_TG_OVRUN_MRAW0_INT 439 |
| #define CMDQ_EVENT_CAMSYS_TG_OVRUN_MRAW1_INT 440 |
| #define CMDQ_EVENT_CAMSYS_TG_OVRUN_MRAW2_INT 441 |
| #define CMDQ_EVENT_CAMSYS_TG_OVRUN_MRAW3_INT 442 |
| #define CMDQ_EVENT_CAMSYS_DMA_R1_ERROR_MRAW0_INT 443 |
| #define CMDQ_EVENT_CAMSYS_DMA_R1_ERROR_MRAW1_INT 444 |
| #define CMDQ_EVENT_CAMSYS_DMA_R1_ERROR_MRAW2_INT 445 |
| #define CMDQ_EVENT_CAMSYS_DMA_R1_ERROR_MRAW3_INT 446 |
| #define CMDQ_EVENT_CAMSYS_PDA0_IRQO_EVENT_DONE_D1 447 |
| #define CMDQ_EVENT_CAMSYS_PDA1_IRQO_EVENT_DONE_D1 448 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBA_TG_INT1 449 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBA_TG_INT2 450 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBA_TG_INT3 451 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBA_TG_INT4 452 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBB_TG_INT1 453 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBB_TG_INT2 454 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBB_TG_INT3 455 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBB_TG_INT4 456 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBC_TG_INT1 457 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBC_TG_INT2 458 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBC_TG_INT3 459 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBC_TG_INT4 460 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBA_IMGO_R1_LOW_LATENCY_LINE_CNT_INT 461 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBA_YUVO_R1_LOW_LATENCY_LINE_CNT_INT 462 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBA_YUVO_R3_LOW_LATENCY_LINE_CNT_INT 463 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBA_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT 464 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBB_IMGO_R1_LOW_LATENCY_LINE_CNT_INT 465 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBB_YUVO_R1_LOW_LATENCY_LINE_CNT_INT 466 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBB_YUVO_R3_LOW_LATENCY_LINE_CNT_INT 467 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBB_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT 468 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBC_IMGO_R1_LOW_LATENCY_LINE_CNT_INT 469 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBC_YUVO_R1_LOW_LATENCY_LINE_CNT_INT 470 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBC_YUVO_R3_LOW_LATENCY_LINE_CNT_INT 471 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBC_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT 472 |
| #define CMDQ_EVENT_CAMSYS_RAW_SEL_SOF_SUBA 473 |
| #define CMDQ_EVENT_CAMSYS_RAW_SEL_SOF_SUBB 474 |
| #define CMDQ_EVENT_CAMSYS_RAW_SEL_SOF_SUBC 475 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBA_RING_BUFFER_OVERFLOW_INT_IN 476 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBB_RING_BUFFER_OVERFLOW_INT_IN 477 |
| #define CMDQ_EVENT_CAMSYS_CAM_SUBC_RING_BUFFER_OVERFLOW_INT_IN 478 |
| #define CMDQ_EVENT_GCE_EVENT_0 898 |
| #define CMDQ_EVENT_GCE_EVENT_1 899 |
| #define CMDQ_EVENT_GCE_EVENT_2 900 |
| |
| /* CMDQ sw tokens |
| * Following definitions are gce sw token which may use by clients |
| * event operation API. |
| * Note that token 512 to 639 may set secure |
| */ |
| |
| /* end of hw event and begin of sw token */ |
| #define CMDQ_MAX_HW_EVENT 512 |
| |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_1 514 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_2 515 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_3 516 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_4 517 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_5 518 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_6 519 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_7 520 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_8 521 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_9 522 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_10 523 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_11 524 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_12 525 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_13 526 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_14 527 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_15 528 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_16 529 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_17 530 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_18 531 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_19 532 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_20 533 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_21 534 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_22 535 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_23 536 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_24 537 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_25 538 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_26 539 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_27 540 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_28 541 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_29 542 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_30 543 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_31 544 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_32 545 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_33 546 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_34 547 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_35 548 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_36 549 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_37 550 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_38 551 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_39 552 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_40 553 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_41 554 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_42 555 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_43 556 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_44 557 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_45 558 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_46 559 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_47 560 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_48 561 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_49 562 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_50 563 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_51 564 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_52 565 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_53 566 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_54 567 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_55 568 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_56 569 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_57 570 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_58 571 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_59 572 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_60 573 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_61 574 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_62 575 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_63 576 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_64 577 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_65 578 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_66 579 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_67 580 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_68 581 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_69 582 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_70 583 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_71 584 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_72 585 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_73 586 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_74 587 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_75 588 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_76 589 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_77 590 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_78 591 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_79 592 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_80 593 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_81 594 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_82 595 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_83 596 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_84 597 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_85 598 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_86 599 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_87 600 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_88 601 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_89 602 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_90 603 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_91 604 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_92 605 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_93 606 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_94 607 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_95 608 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_96 609 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_97 610 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_98 611 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_99 612 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_100 613 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_101 720 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_102 721 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_103 722 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_104 723 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_105 724 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_106 725 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_107 726 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_108 727 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_109 728 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_110 729 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_111 730 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_112 731 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_113 732 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_114 733 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_115 734 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_116 735 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_117 736 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_118 737 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_119 738 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_120 739 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_121 740 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_122 741 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_123 742 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_124 743 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_125 744 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_126 745 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_127 746 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_128 747 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_129 748 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_130 749 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_131 750 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_132 751 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_133 752 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_134 753 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_135 754 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_136 755 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_137 756 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_138 757 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_139 758 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_POOL_140 759 |
| |
| /* MML sw tokens */ |
| #define CMDQ_SYNC_TOKEN_MML_BUFA 630 |
| #define CMDQ_SYNC_TOKEN_MML_BUFB 631 |
| #define CMDQ_SYNC_TOKEN_MML_BUF_NEXT 632 |
| #define CMDQ_SYNC_TOKEN_MML_IR_MML_READY 633 |
| #define CMDQ_SYNC_TOKEN_MML_IR_DISP_READY 634 |
| #define CMDQ_SYNC_TOKEN_MML_MML_STOP 635 |
| #define CMDQ_SYNC_TOKEN_MML_PIPE0 636 |
| #define CMDQ_SYNC_TOKEN_MML_PIPE1 637 |
| #define CMDQ_SYNC_TOKEN_MML_PIPE1_NEXT 638 |
| |
| /* Config thread notify trigger thread */ |
| #define CMDQ_SYNC_TOKEN_CONFIG_DIRTY 640 |
| /* Trigger thread notify config thread */ |
| #define CMDQ_SYNC_TOKEN_STREAM_EOF 641 |
| /* Block Trigger thread until the ESD check finishes. */ |
| #define CMDQ_SYNC_TOKEN_ESD_EOF 642 |
| #define CMDQ_SYNC_TOKEN_STREAM_BLOCK 643 |
| /* check CABC setup finish */ |
| #define CMDQ_SYNC_TOKEN_CABC_EOF 644 |
| |
| /*VFP period token for Msync*/ |
| #define CMDQ_SYNC_TOKEN_VFP_PERIOD 645 |
| |
| /* Notify normal CMDQ there are some secure task done |
| * MUST NOT CHANGE, this token sync with secure world |
| */ |
| #define CMDQ_SYNC_SECURE_THR_EOF 647 |
| |
| /* CMDQ use sw token */ |
| #define CMDQ_SYNC_TOKEN_USER_0 649 |
| #define CMDQ_SYNC_TOKEN_USER_1 650 |
| #define CMDQ_SYNC_TOKEN_POLL_MONITOR 651 |
| #define CMDQ_SYNC_TOKEN_TPR_LOCK 652 |
| |
| /* TZMP sw token */ |
| #define CMDQ_SYNC_TOKEN_TZMP_DISP_WAIT 653 |
| #define CMDQ_SYNC_TOKEN_TZMP_DISP_SET 654 |
| #define CMDQ_SYNC_TOKEN_TZMP_ISP_WAIT 655 |
| #define CMDQ_SYNC_TOKEN_TZMP_ISP_SET 656 |
| #define CMDQ_SYNC_TOKEN_TZMP_AIE_WAIT 657 |
| #define CMDQ_SYNC_TOKEN_TZMP_AIE_SET 658 |
| #define CMDQ_SYNC_TOKEN_TZMP_ADL_WAIT 659 |
| #define CMDQ_SYNC_TOKEN_TZMP_ADL_SET 660 |
| |
| /* ISP sw token */ |
| #define CMDQ_SYNC_TOKEN_IMGSYS_WPE_EIS 665 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_WPE_TNR 666 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_WPE_LITE 667 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_TRAW 668 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_LTRAW 669 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_XTRAW 670 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_DIP 671 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_A 672 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_B 673 |
| #define CMDQ_SYNC_TOKEN_IPESYS_ME 674 |
| #define CMDQ_SYNC_TOKEN_APUSYS_APU 675 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_VSS_TRAW 676 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_VSS_LTRAW 677 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_VSS_XTRAW 678 |
| #define CMDQ_SYNC_TOKEN_IMGSYS_VSS_DIP 679 |
| |
| /* PREBUILT sw token */ |
| #define CMDQ_SYNC_TOKEN_PREBUILT_MDP_LOCK 682 |
| #define CMDQ_SYNC_TOKEN_PREBUILT_MML_LOCK 685 |
| #define CMDQ_SYNC_TOKEN_PREBUILT_VFMT_LOCK 688 |
| #define CMDQ_SYNC_TOKEN_PREBUILT_DISP_LOCK 691 |
| |
| #define CMDQ_SYNC_TOKEN_DISP_VA_START 692 |
| #define CMDQ_SYNC_TOKEN_DISP_VA_END 693 |
| |
| /* SW sync token for dual display */ |
| #define CMDQ_SYNC_TOKEN_CONFIG_DIRTY_1 694 |
| #define CMDQ_SYNC_TOKEN_STREAM_EOF_1 695 |
| #define CMDQ_SYNC_TOKEN_ESD_EOF_1 696 |
| #define CMDQ_SYNC_TOKEN_STREAM_BLOCK_1 697 |
| #define CMDQ_SYNC_TOKEN_CABC_EOF_1 698 |
| |
| /* SW sync token for dual display */ |
| #define CMDQ_SYNC_TOKEN_CONFIG_DIRTY_3 714 |
| #define CMDQ_SYNC_TOKEN_STREAM_EOF_3 715 |
| #define CMDQ_SYNC_TOKEN_ESD_EOF_3 716 |
| #define CMDQ_SYNC_TOKEN_STREAM_BLOCK_3 717 |
| #define CMDQ_SYNC_TOKEN_CABC_EOF_3 718 |
| |
| /* GPR access tokens (for HW register backup) |
| * There are 15 32-bit GPR, 3 GPR form a set |
| * (64-bit for address, 32-bit for value) |
| * MUST NOT CHANGE, these tokens sync with MDP |
| */ |
| #define CMDQ_SYNC_TOKEN_GPR_SET_0 700 |
| #define CMDQ_SYNC_TOKEN_GPR_SET_1 701 |
| #define CMDQ_SYNC_TOKEN_GPR_SET_2 702 |
| #define CMDQ_SYNC_TOKEN_GPR_SET_3 703 |
| #define CMDQ_SYNC_TOKEN_GPR_SET_4 704 |
| |
| #define CMDQ_SYNC_TOKEN_TE_0 705 |
| #define CMDQ_SYNC_TOKEN_PRETE_0 706 |
| /* Resource lock event to control resource in GCE thread */ |
| #define CMDQ_SYNC_RESOURCE_WROT0 710 |
| #define CMDQ_SYNC_RESOURCE_WROT1 711 |
| |
| /* HW TRACE sw token */ |
| #define CMDQ_SYNC_TOKEN_HW_TRACE_WAIT 712 |
| #define CMDQ_SYNC_TOKEN_HW_TRACE_LOCK 713 |
| |
| /* event for gpr timer, used in sleep and poll with timeout */ |
| #define CMDQ_TOKEN_GPR_TIMER_R0 994 |
| #define CMDQ_TOKEN_GPR_TIMER_R1 995 |
| #define CMDQ_TOKEN_GPR_TIMER_R2 996 |
| #define CMDQ_TOKEN_GPR_TIMER_R3 997 |
| #define CMDQ_TOKEN_GPR_TIMER_R4 998 |
| #define CMDQ_TOKEN_GPR_TIMER_R5 999 |
| #define CMDQ_TOKEN_GPR_TIMER_R6 1000 |
| #define CMDQ_TOKEN_GPR_TIMER_R7 1001 |
| #define CMDQ_TOKEN_GPR_TIMER_R8 1002 |
| #define CMDQ_TOKEN_GPR_TIMER_R9 1003 |
| #define CMDQ_TOKEN_GPR_TIMER_R10 1004 |
| #define CMDQ_TOKEN_GPR_TIMER_R11 1005 |
| #define CMDQ_TOKEN_GPR_TIMER_R12 1006 |
| #define CMDQ_TOKEN_GPR_TIMER_R13 1007 |
| #define CMDQ_TOKEN_GPR_TIMER_R14 1008 |
| #define CMDQ_TOKEN_GPR_TIMER_R15 1009 |
| |
| #define CMDQ_EVENT_MAX 0x3FF |
| /* CMDQ sw tokens END */ |
| |
| #endif |
