| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* |
| * Copyright (c) 2021 MediaTek Inc. |
| */ |
| |
| #ifndef __LINUX_REGULATOR_MT6363_H |
| #define __LINUX_REGULATOR_MT6363_H |
| |
| enum { |
| MT6363_ID_VS2, |
| MT6363_ID_VBUCK1, |
| MT6363_ID_VBUCK2, |
| MT6363_ID_VBUCK3, |
| MT6363_ID_VBUCK4, |
| MT6363_ID_VBUCK5, |
| MT6363_ID_VBUCK6, |
| MT6363_ID_VBUCK7, |
| MT6363_ID_VS1, |
| MT6363_ID_VS3, |
| MT6363_ID_VBUCK1_SSHUB, |
| MT6363_ID_VBUCK2_SSHUB, |
| MT6363_ID_VBUCK4_SSHUB, |
| MT6363_ID_VSRAM_DIGRF, |
| MT6363_ID_VSRAM_MDFE, |
| MT6363_ID_VSRAM_MODEM, |
| MT6363_ID_VSRAM_CPUB, |
| MT6363_ID_VSRAM_CPUM, |
| MT6363_ID_VSRAM_CPUL, |
| MT6363_ID_VSRAM_APU, |
| MT6363_ID_VEMC, |
| MT6363_ID_VCN13, |
| MT6363_ID_VTREF18, |
| MT6363_ID_VAUX18, |
| MT6363_ID_VCN15, |
| MT6363_ID_VUFS18, |
| MT6363_ID_VIO18, |
| MT6363_ID_VM18, |
| MT6363_ID_VA15, |
| MT6363_ID_VRF18, |
| MT6363_ID_VRFIO18, |
| MT6363_ID_VIO075, |
| MT6363_ID_VUFS12, |
| MT6363_ID_VA12_1, |
| MT6363_ID_VA12_2, |
| MT6363_ID_VRF12, |
| MT6363_ID_VRF13, |
| MT6363_ID_VRF09, |
| MT6363_ID_ISINK_LOAD, |
| MT6363_MAX_REGULATOR, |
| }; |
| |
| #define MTK_REGULATOR_MAX_NR MT6363_MAX_REGULATOR |
| |
| /* Register */ |
| #define MT6363_TOP_TRAP (0x36) |
| #define MT6363_TOP_TMA_KEY_L (0x39e) |
| #define MT6363_BUCK_TOP_KEY_PROT_LO (0x142a) |
| #define MT6363_BUCK_VS2_OP_EN_0 (0x148d) |
| #define MT6363_BUCK_VS2_HW_LP_MODE (0x1498) |
| #define MT6363_BUCK_VBUCK1_OP_EN_0 (0x150d) |
| #define MT6363_BUCK_VBUCK1_HW_LP_MODE (0x1518) |
| #define MT6363_BUCK_VBUCK2_OP_EN_0 (0x158d) |
| #define MT6363_BUCK_VBUCK2_HW_LP_MODE (0x1598) |
| #define MT6363_BUCK_VBUCK3_OP_EN_0 (0x160d) |
| #define MT6363_BUCK_VBUCK3_HW_LP_MODE (0x1618) |
| #define MT6363_BUCK_VBUCK4_OP_EN_0 (0x168d) |
| #define MT6363_BUCK_VBUCK4_HW_LP_MODE (0x1698) |
| #define MT6363_BUCK_VBUCK5_OP_EN_0 (0x170d) |
| #define MT6363_BUCK_VBUCK5_HW_LP_MODE (0x1718) |
| #define MT6363_BUCK_VBUCK6_OP_EN_0 (0x178d) |
| #define MT6363_BUCK_VBUCK6_HW_LP_MODE (0x1798) |
| #define MT6363_BUCK_VBUCK7_OP_EN_0 (0x180d) |
| #define MT6363_BUCK_VBUCK7_HW_LP_MODE (0x1818) |
| #define MT6363_BUCK_VS1_OP_EN_0 (0x188d) |
| #define MT6363_BUCK_VS1_HW_LP_MODE (0x1898) |
| #define MT6363_BUCK_VS3_OP_EN_0 (0x190d) |
| #define MT6363_BUCK_VS3_HW_LP_MODE (0x1918) |
| #define MT6363_LDO_VCN15_HW_LP_MODE (0x1b8b) |
| #define MT6363_LDO_VCN15_OP_EN0 (0x1b8c) |
| #define MT6363_LDO_VRF09_HW_LP_MODE (0x1b99) |
| #define MT6363_LDO_VRF09_OP_EN0 (0x1b9a) |
| #define MT6363_LDO_VRF12_HW_LP_MODE (0x1ba7) |
| #define MT6363_LDO_VRF12_OP_EN0 (0x1ba8) |
| #define MT6363_LDO_VRF13_HW_LP_MODE (0x1bb5) |
| #define MT6363_LDO_VRF13_OP_EN0 (0x1bb6) |
| #define MT6363_LDO_VRF18_HW_LP_MODE (0x1bc3) |
| #define MT6363_LDO_VRF18_OP_EN0 (0x1bc4) |
| #define MT6363_LDO_VRFIO18_HW_LP_MODE (0x1bd1) |
| #define MT6363_LDO_VRFIO18_OP_EN0 (0x1bd2) |
| #define MT6363_LDO_VTREF18_HW_LP_MODE (0x1c0b) |
| #define MT6363_LDO_VTREF18_OP_EN0 (0x1c0c) |
| #define MT6363_LDO_VAUX18_HW_LP_MODE (0x1c19) |
| #define MT6363_LDO_VAUX18_OP_EN0 (0x1c1a) |
| #define MT6363_LDO_VEMC_HW_LP_MODE (0x1c27) |
| #define MT6363_LDO_VEMC_OP_EN0 (0x1c28) |
| #define MT6363_LDO_VUFS12_HW_LP_MODE (0x1c35) |
| #define MT6363_LDO_VUFS12_OP_EN0 (0x1c36) |
| #define MT6363_LDO_VUFS18_HW_LP_MODE (0x1c43) |
| #define MT6363_LDO_VUFS18_OP_EN0 (0x1c44) |
| #define MT6363_LDO_VIO18_HW_LP_MODE (0x1c51) |
| #define MT6363_LDO_VIO18_OP_EN0 (0x1c52) |
| #define MT6363_LDO_VIO075_HW_LP_MODE (0x1c8b) |
| #define MT6363_LDO_VIO075_OP_EN0 (0x1c8c) |
| #define MT6363_LDO_VA12_1_HW_LP_MODE (0x1c99) |
| #define MT6363_LDO_VA12_1_OP_EN0 (0x1c9a) |
| #define MT6363_LDO_VA12_2_HW_LP_MODE (0x1ca7) |
| #define MT6363_LDO_VA12_2_OP_EN0 (0x1ca8) |
| #define MT6363_LDO_VA15_HW_LP_MODE (0x1cb5) |
| #define MT6363_LDO_VA15_OP_EN0 (0x1cb6) |
| #define MT6363_LDO_VM18_HW_LP_MODE (0x1cc3) |
| #define MT6363_LDO_VM18_OP_EN0 (0x1cc4) |
| #define MT6363_LDO_VCN13_HW_LP_MODE (0x1d0b) |
| #define MT6363_LDO_VCN13_OP_EN0 (0x1d14) |
| #define MT6363_LDO_VSRAM_DIGRF_HW_LP_MODE (0x1d21) |
| #define MT6363_LDO_VSRAM_DIGRF_OP_EN0 (0x1d2a) |
| #define MT6363_LDO_VSRAM_MDFE_HW_LP_MODE (0x1d8b) |
| #define MT6363_LDO_VSRAM_MDFE_OP_EN0 (0x1d94) |
| #define MT6363_LDO_VSRAM_MODEM_HW_LP_MODE (0x1da6) |
| #define MT6363_LDO_VSRAM_MODEM_OP_EN0 (0x1daf) |
| #define MT6363_LDO_VSRAM_CPUB_HW_LP_MODE (0x1e0b) |
| #define MT6363_LDO_VSRAM_CPUB_OP_EN0 (0x1e14) |
| #define MT6363_LDO_VSRAM_CPUM_HW_LP_MODE (0x1e21) |
| #define MT6363_LDO_VSRAM_CPUM_OP_EN0 (0x1e2a) |
| #define MT6363_LDO_VSRAM_CPUL_HW_LP_MODE (0x1e8b) |
| #define MT6363_LDO_VSRAM_CPUL_OP_EN0 (0x1e94) |
| #define MT6363_LDO_VSRAM_APU_HW_LP_MODE (0x1ea1) |
| #define MT6363_LDO_VSRAM_APU_OP_EN0 (0x1eaa) |
| #define MT6363_RG_BUCK_VS2_EN_ADDR (0x240) |
| #define MT6363_RG_BUCK_VS2_EN_SHIFT (0) |
| #define MT6363_RG_BUCK_VBUCK1_EN_ADDR (0x240) |
| #define MT6363_RG_BUCK_VBUCK1_EN_SHIFT (1) |
| #define MT6363_RG_BUCK_VBUCK2_EN_ADDR (0x240) |
| #define MT6363_RG_BUCK_VBUCK2_EN_SHIFT (2) |
| #define MT6363_RG_BUCK_VBUCK3_EN_ADDR (0x240) |
| #define MT6363_RG_BUCK_VBUCK3_EN_SHIFT (3) |
| #define MT6363_RG_BUCK_VBUCK4_EN_ADDR (0x240) |
| #define MT6363_RG_BUCK_VBUCK4_EN_SHIFT (4) |
| #define MT6363_RG_BUCK_VBUCK5_EN_ADDR (0x240) |
| #define MT6363_RG_BUCK_VBUCK5_EN_SHIFT (5) |
| #define MT6363_RG_BUCK_VBUCK6_EN_ADDR (0x240) |
| #define MT6363_RG_BUCK_VBUCK6_EN_SHIFT (6) |
| #define MT6363_RG_BUCK_VBUCK7_EN_ADDR (0x240) |
| #define MT6363_RG_BUCK_VBUCK7_EN_SHIFT (7) |
| #define MT6363_RG_BUCK_VS1_EN_ADDR (0x243) |
| #define MT6363_RG_BUCK_VS1_EN_SHIFT (0) |
| #define MT6363_RG_BUCK_VS3_EN_ADDR (0x243) |
| #define MT6363_RG_BUCK_VS3_EN_SHIFT (1) |
| #define MT6363_RG_LDO_VSRAM_DIGRF_EN_ADDR (0x243) |
| #define MT6363_RG_LDO_VSRAM_DIGRF_EN_SHIFT (4) |
| #define MT6363_RG_LDO_VSRAM_MDFE_EN_ADDR (0x243) |
| #define MT6363_RG_LDO_VSRAM_MDFE_EN_SHIFT (5) |
| #define MT6363_RG_LDO_VSRAM_MODEM_EN_ADDR (0x243) |
| #define MT6363_RG_LDO_VSRAM_MODEM_EN_SHIFT (6) |
| #define MT6363_RG_BUCK_VS2_LP_ADDR (0x246) |
| #define MT6363_RG_BUCK_VS2_LP_SHIFT (0) |
| #define MT6363_RG_BUCK_VBUCK1_LP_ADDR (0x246) |
| #define MT6363_RG_BUCK_VBUCK1_LP_SHIFT (1) |
| #define MT6363_RG_BUCK_VBUCK2_LP_ADDR (0x246) |
| #define MT6363_RG_BUCK_VBUCK2_LP_SHIFT (2) |
| #define MT6363_RG_BUCK_VBUCK3_LP_ADDR (0x246) |
| #define MT6363_RG_BUCK_VBUCK3_LP_SHIFT (3) |
| #define MT6363_RG_BUCK_VBUCK4_LP_ADDR (0x246) |
| #define MT6363_RG_BUCK_VBUCK4_LP_SHIFT (4) |
| #define MT6363_RG_BUCK_VBUCK5_LP_ADDR (0x246) |
| #define MT6363_RG_BUCK_VBUCK5_LP_SHIFT (5) |
| #define MT6363_RG_BUCK_VBUCK6_LP_ADDR (0x246) |
| #define MT6363_RG_BUCK_VBUCK6_LP_SHIFT (6) |
| #define MT6363_RG_BUCK_VBUCK7_LP_ADDR (0x246) |
| #define MT6363_RG_BUCK_VBUCK7_LP_SHIFT (7) |
| #define MT6363_RG_BUCK_VS1_LP_ADDR (0x249) |
| #define MT6363_RG_BUCK_VS1_LP_SHIFT (0) |
| #define MT6363_RG_BUCK_VS3_LP_ADDR (0x249) |
| #define MT6363_RG_BUCK_VS3_LP_SHIFT (1) |
| #define MT6363_RG_LDO_VSRAM_DIGRF_LP_ADDR (0x249) |
| #define MT6363_RG_LDO_VSRAM_DIGRF_LP_SHIFT (4) |
| #define MT6363_RG_LDO_VSRAM_MDFE_LP_ADDR (0x249) |
| #define MT6363_RG_LDO_VSRAM_MDFE_LP_SHIFT (5) |
| #define MT6363_RG_LDO_VSRAM_MODEM_LP_ADDR (0x249) |
| #define MT6363_RG_LDO_VSRAM_MODEM_LP_SHIFT (6) |
| #define MT6363_RG_BUCK_VS2_VOSEL_ADDR (0x24c) |
| #define MT6363_RG_BUCK_VS2_VOSEL_MASK (0xff) |
| #define MT6363_RG_BUCK_VBUCK1_VOSEL_ADDR (0x24d) |
| #define MT6363_RG_BUCK_VBUCK1_VOSEL_MASK (0xff) |
| #define MT6363_RG_BUCK_VBUCK2_VOSEL_ADDR (0x24e) |
| #define MT6363_RG_BUCK_VBUCK2_VOSEL_MASK (0xff) |
| #define MT6363_RG_BUCK_VBUCK3_VOSEL_ADDR (0x24f) |
| #define MT6363_RG_BUCK_VBUCK3_VOSEL_MASK (0xff) |
| #define MT6363_RG_BUCK_VBUCK4_VOSEL_ADDR (0x250) |
| #define MT6363_RG_BUCK_VBUCK4_VOSEL_MASK (0xff) |
| #define MT6363_RG_BUCK_VBUCK5_VOSEL_ADDR (0x251) |
| #define MT6363_RG_BUCK_VBUCK5_VOSEL_MASK (0xff) |
| #define MT6363_RG_BUCK_VBUCK6_VOSEL_ADDR (0x252) |
| #define MT6363_RG_BUCK_VBUCK6_VOSEL_MASK (0xff) |
| #define MT6363_RG_BUCK_VBUCK7_VOSEL_ADDR (0x253) |
| #define MT6363_RG_BUCK_VBUCK7_VOSEL_MASK (0xff) |
| #define MT6363_RG_BUCK_VS1_VOSEL_ADDR (0x254) |
| #define MT6363_RG_BUCK_VS1_VOSEL_MASK (0xff) |
| #define MT6363_RG_BUCK_VS3_VOSEL_ADDR (0x255) |
| #define MT6363_RG_BUCK_VS3_VOSEL_MASK (0xff) |
| #define MT6363_RG_LDO_VSRAM_DIGRF_VOSEL_ADDR (0x258) |
| #define MT6363_RG_LDO_VSRAM_DIGRF_VOSEL_MASK (0x7f) |
| #define MT6363_RG_LDO_VSRAM_MDFE_VOSEL_ADDR (0x259) |
| #define MT6363_RG_LDO_VSRAM_MDFE_VOSEL_MASK (0x7f) |
| #define MT6363_RG_LDO_VSRAM_MODEM_VOSEL_ADDR (0x25a) |
| #define MT6363_RG_LDO_VSRAM_MODEM_VOSEL_MASK (0x7f) |
| #define MT6363_BUCK_VS2_WDTDBG_VOSEL_ADDR (0x142c) |
| #define MT6363_BUCK_VBUCK1_WDTDBG_VOSEL_ADDR (0x142d) |
| #define MT6363_BUCK_VBUCK2_WDTDBG_VOSEL_ADDR (0x142e) |
| #define MT6363_BUCK_VBUCK3_WDTDBG_VOSEL_ADDR (0x142f) |
| #define MT6363_BUCK_VBUCK4_WDTDBG_VOSEL_ADDR (0x1430) |
| #define MT6363_BUCK_VBUCK5_WDTDBG_VOSEL_ADDR (0x1431) |
| #define MT6363_BUCK_VBUCK6_WDTDBG_VOSEL_ADDR (0x1432) |
| #define MT6363_BUCK_VBUCK7_WDTDBG_VOSEL_ADDR (0x1433) |
| #define MT6363_BUCK_VS1_WDTDBG_VOSEL_ADDR (0x1434) |
| #define MT6363_BUCK_VS3_WDTDBG_VOSEL_ADDR (0x1435) |
| #define MT6363_RG_BUCK_VBUCK1_SSHUB_EN_ADDR (0x151a) |
| #define MT6363_RG_BUCK_VBUCK1_SSHUB_VOSEL_ADDR (0x151b) |
| #define MT6363_RG_BUCK_VBUCK1_SSHUB_VOSEL_MASK (0xff) |
| #define MT6363_RG_BUCK_VBUCK2_SSHUB_EN_ADDR (0x159a) |
| #define MT6363_RG_BUCK_VBUCK2_SSHUB_VOSEL_ADDR (0x159b) |
| #define MT6363_RG_BUCK_VBUCK2_SSHUB_VOSEL_MASK (0xff) |
| #define MT6363_RG_BUCK_VBUCK4_SSHUB_EN_ADDR (0x169a) |
| #define MT6363_RG_BUCK_VBUCK4_SSHUB_VOSEL_ADDR (0x169b) |
| #define MT6363_RG_BUCK_VBUCK4_SSHUB_VOSEL_MASK (0xff) |
| #define MT6363_RG_VS1_FCCM_ADDR (0x1994) |
| #define MT6363_RG_VS1_FCCM_SHIFT (0) |
| #define MT6363_RG_VS3_FCCM_ADDR (0x19a3) |
| #define MT6363_RG_VS3_FCCM_SHIFT (0) |
| #define MT6363_RG_VBUCK1_FCCM_ADDR (0x1a32) |
| #define MT6363_RG_VBUCK1_FCCM_SHIFT (0) |
| #define MT6363_RG_VBUCK2_FCCM_ADDR (0x1a32) |
| #define MT6363_RG_VBUCK2_FCCM_SHIFT (1) |
| #define MT6363_RG_VBUCK3_FCCM_ADDR (0x1a32) |
| #define MT6363_RG_VBUCK3_FCCM_SHIFT (2) |
| #define MT6363_RG_VS2_FCCM_ADDR (0x1a32) |
| #define MT6363_RG_VS2_FCCM_SHIFT (3) |
| #define MT6363_RG_VBUCK4_FCCM_ADDR (0x1ab2) |
| #define MT6363_RG_VBUCK4_FCCM_SHIFT (0) |
| #define MT6363_RG_VBUCK5_FCCM_ADDR (0x1ab2) |
| #define MT6363_RG_VBUCK5_FCCM_SHIFT (1) |
| #define MT6363_RG_VBUCK6_FCCM_ADDR (0x1ab2) |
| #define MT6363_RG_VBUCK6_FCCM_SHIFT (2) |
| #define MT6363_RG_VBUCK7_FCCM_ADDR (0x1ab2) |
| #define MT6363_RG_VBUCK7_FCCM_SHIFT (3) |
| #define MT6363_RG_VCN13_VOSEL_ADDR (0x1b3f) |
| #define MT6363_RG_VCN13_VOSEL_MASK (0xf) |
| #define MT6363_RG_VEMC_VOSEL_0_ADDR (0x1b40) |
| #define MT6363_RG_VEMC_VOSEL_0_MASK (0xf) |
| #define MT6363_RG_LDO_VSRAM_CPUB_VOSEL_ADDR (0x1b44) |
| #define MT6363_RG_LDO_VSRAM_CPUB_VOSEL_MASK (0x7f) |
| #define MT6363_RG_LDO_VSRAM_CPUM_VOSEL_ADDR (0x1b45) |
| #define MT6363_RG_LDO_VSRAM_CPUM_VOSEL_MASK (0x7f) |
| #define MT6363_RG_LDO_VSRAM_CPUL_VOSEL_ADDR (0x1b46) |
| #define MT6363_RG_LDO_VSRAM_CPUL_VOSEL_MASK (0x7f) |
| #define MT6363_RG_LDO_VSRAM_APU_VOSEL_ADDR (0x1b47) |
| #define MT6363_RG_LDO_VSRAM_APU_VOSEL_MASK (0x7f) |
| #define MT6363_RG_VEMC_VOCAL_0_ADDR (0x1b4b) |
| #define MT6363_RG_VEMC_VOCAL_0_MASK (0xf) |
| #define MT6363_RG_LDO_VCN15_EN_ADDR (0x1b87) |
| #define MT6363_RG_LDO_VCN15_EN_SHIFT (0) |
| #define MT6363_RG_LDO_VCN15_LP_ADDR (0x1b87) |
| #define MT6363_RG_LDO_VCN15_LP_SHIFT (1) |
| #define MT6363_RG_LDO_VRF09_EN_ADDR (0x1b95) |
| #define MT6363_RG_LDO_VRF09_EN_SHIFT (0) |
| #define MT6363_RG_LDO_VRF09_LP_ADDR (0x1b95) |
| #define MT6363_RG_LDO_VRF09_LP_SHIFT (1) |
| #define MT6363_RG_LDO_VRF12_EN_ADDR (0x1ba3) |
| #define MT6363_RG_LDO_VRF12_EN_SHIFT (0) |
| #define MT6363_RG_LDO_VRF12_LP_ADDR (0x1ba3) |
| #define MT6363_RG_LDO_VRF12_LP_SHIFT (1) |
| #define MT6363_RG_LDO_VRF13_EN_ADDR (0x1bb1) |
| #define MT6363_RG_LDO_VRF13_EN_SHIFT (0) |
| #define MT6363_RG_LDO_VRF13_LP_ADDR (0x1bb1) |
| #define MT6363_RG_LDO_VRF13_LP_SHIFT (1) |
| #define MT6363_RG_LDO_VRF18_EN_ADDR (0x1bbf) |
| #define MT6363_RG_LDO_VRF18_EN_SHIFT (0) |
| #define MT6363_RG_LDO_VRF18_LP_ADDR (0x1bbf) |
| #define MT6363_RG_LDO_VRF18_LP_SHIFT (1) |
| #define MT6363_RG_LDO_VRFIO18_EN_ADDR (0x1bcd) |
| #define MT6363_RG_LDO_VRFIO18_EN_SHIFT (0) |
| #define MT6363_RG_LDO_VRFIO18_LP_ADDR (0x1bcd) |
| #define MT6363_RG_LDO_VRFIO18_LP_SHIFT (1) |
| #define MT6363_RG_LDO_VTREF18_EN_ADDR (0x1c07) |
| #define MT6363_RG_LDO_VTREF18_EN_SHIFT (0) |
| #define MT6363_RG_LDO_VTREF18_LP_ADDR (0x1c07) |
| #define MT6363_RG_LDO_VTREF18_LP_SHIFT (1) |
| #define MT6363_RG_LDO_VAUX18_EN_ADDR (0x1c15) |
| #define MT6363_RG_LDO_VAUX18_EN_SHIFT (0) |
| #define MT6363_RG_LDO_VAUX18_LP_ADDR (0x1c15) |
| #define MT6363_RG_LDO_VAUX18_LP_SHIFT (1) |
| #define MT6363_RG_LDO_VEMC_EN_ADDR (0x1c23) |
| #define MT6363_RG_LDO_VEMC_EN_SHIFT (0) |
| #define MT6363_RG_LDO_VEMC_LP_ADDR (0x1c23) |
| #define MT6363_RG_LDO_VEMC_LP_SHIFT (1) |
| #define MT6363_RG_LDO_VUFS12_EN_ADDR (0x1c31) |
| #define MT6363_RG_LDO_VUFS12_EN_SHIFT (0) |
| #define MT6363_RG_LDO_VUFS12_LP_ADDR (0x1c31) |
| #define MT6363_RG_LDO_VUFS12_LP_SHIFT (1) |
| #define MT6363_RG_LDO_VUFS18_EN_ADDR (0x1c3f) |
| #define MT6363_RG_LDO_VUFS18_EN_SHIFT (0) |
| #define MT6363_RG_LDO_VUFS18_LP_ADDR (0x1c3f) |
| #define MT6363_RG_LDO_VUFS18_LP_SHIFT (1) |
| #define MT6363_RG_LDO_VIO18_EN_ADDR (0x1c4d) |
| #define MT6363_RG_LDO_VIO18_EN_SHIFT (0) |
| #define MT6363_RG_LDO_VIO18_LP_ADDR (0x1c4d) |
| #define MT6363_RG_LDO_VIO18_LP_SHIFT (1) |
| #define MT6363_RG_LDO_VIO075_EN_ADDR (0x1c87) |
| #define MT6363_RG_LDO_VIO075_EN_SHIFT (0) |
| #define MT6363_RG_LDO_VIO075_LP_ADDR (0x1c87) |
| #define MT6363_RG_LDO_VIO075_LP_SHIFT (1) |
| #define MT6363_RG_LDO_VA12_1_EN_ADDR (0x1c95) |
| #define MT6363_RG_LDO_VA12_1_EN_SHIFT (0) |
| #define MT6363_RG_LDO_VA12_1_LP_ADDR (0x1c95) |
| #define MT6363_RG_LDO_VA12_1_LP_SHIFT (1) |
| #define MT6363_RG_LDO_VA12_2_EN_ADDR (0x1ca3) |
| #define MT6363_RG_LDO_VA12_2_EN_SHIFT (0) |
| #define MT6363_RG_LDO_VA12_2_LP_ADDR (0x1ca3) |
| #define MT6363_RG_LDO_VA12_2_LP_SHIFT (1) |
| #define MT6363_RG_LDO_VA15_EN_ADDR (0x1cb1) |
| #define MT6363_RG_LDO_VA15_EN_SHIFT (0) |
| #define MT6363_RG_LDO_VA15_LP_ADDR (0x1cb1) |
| #define MT6363_RG_LDO_VA15_LP_SHIFT (1) |
| #define MT6363_RG_LDO_VM18_EN_ADDR (0x1cbf) |
| #define MT6363_RG_LDO_VM18_EN_SHIFT (0) |
| #define MT6363_RG_LDO_VM18_LP_ADDR (0x1cbf) |
| #define MT6363_RG_LDO_VM18_LP_SHIFT (1) |
| #define MT6363_RG_LDO_VCN13_EN_ADDR (0x1d07) |
| #define MT6363_RG_LDO_VCN13_EN_SHIFT (0) |
| #define MT6363_RG_LDO_VCN13_LP_ADDR (0x1d07) |
| #define MT6363_RG_LDO_VCN13_LP_SHIFT (1) |
| #define MT6363_LDO_VSRAM_DIGRF_WDTDBG_VOSEL_ADDR (0x1d24) |
| #define MT6363_LDO_VSRAM_MDFE_WDTDBG_VOSEL_ADDR (0x1d8e) |
| #define MT6363_LDO_VSRAM_MODEM_WDTDBG_VOSEL_ADDR (0x1da9) |
| #define MT6363_RG_LDO_VSRAM_CPUB_EN_ADDR (0x1e07) |
| #define MT6363_RG_LDO_VSRAM_CPUB_EN_SHIFT (0) |
| #define MT6363_RG_LDO_VSRAM_CPUB_LP_ADDR (0x1e07) |
| #define MT6363_RG_LDO_VSRAM_CPUB_LP_SHIFT (1) |
| #define MT6363_LDO_VSRAM_CPUB_WDTDBG_VOSEL_ADDR (0x1e0e) |
| #define MT6363_RG_LDO_VSRAM_CPUM_EN_ADDR (0x1e1d) |
| #define MT6363_RG_LDO_VSRAM_CPUM_EN_SHIFT (0) |
| #define MT6363_RG_LDO_VSRAM_CPUM_LP_ADDR (0x1e1d) |
| #define MT6363_RG_LDO_VSRAM_CPUM_LP_SHIFT (1) |
| #define MT6363_LDO_VSRAM_CPUM_WDTDBG_VOSEL_ADDR (0x1e24) |
| #define MT6363_RG_LDO_VSRAM_CPUL_EN_ADDR (0x1e87) |
| #define MT6363_RG_LDO_VSRAM_CPUL_EN_SHIFT (0) |
| #define MT6363_RG_LDO_VSRAM_CPUL_LP_ADDR (0x1e87) |
| #define MT6363_RG_LDO_VSRAM_CPUL_LP_SHIFT (1) |
| #define MT6363_LDO_VSRAM_CPUL_WDTDBG_VOSEL_ADDR (0x1e8e) |
| #define MT6363_RG_LDO_VSRAM_APU_EN_ADDR (0x1e9d) |
| #define MT6363_RG_LDO_VSRAM_APU_EN_SHIFT (0) |
| #define MT6363_RG_LDO_VSRAM_APU_LP_ADDR (0x1e9d) |
| #define MT6363_RG_LDO_VSRAM_APU_LP_SHIFT (1) |
| #define MT6363_LDO_VSRAM_APU_WDTDBG_VOSEL_ADDR (0x1ea4) |
| #define MT6363_RG_VTREF18_VOCAL_ADDR (0x1f08) |
| #define MT6363_RG_VTREF18_VOCAL_MASK (0xf) |
| #define MT6363_RG_VTREF18_VOSEL_ADDR (0x1f09) |
| #define MT6363_RG_VTREF18_VOSEL_MASK (0xf) |
| #define MT6363_RG_VAUX18_VOCAL_ADDR (0x1f0c) |
| #define MT6363_RG_VAUX18_VOCAL_MASK (0xf) |
| #define MT6363_RG_VAUX18_VOSEL_ADDR (0x1f0d) |
| #define MT6363_RG_VAUX18_VOSEL_MASK (0xf) |
| #define MT6363_RG_VCN15_VOCAL_ADDR (0x1f13) |
| #define MT6363_RG_VCN15_VOCAL_MASK (0xf) |
| #define MT6363_RG_VCN15_VOSEL_ADDR (0x1f14) |
| #define MT6363_RG_VCN15_VOSEL_MASK (0xf) |
| #define MT6363_RG_VUFS18_VOCAL_ADDR (0x1f17) |
| #define MT6363_RG_VUFS18_VOCAL_MASK (0xf) |
| #define MT6363_RG_VUFS18_VOSEL_ADDR (0x1f18) |
| #define MT6363_RG_VUFS18_VOSEL_MASK (0xf) |
| #define MT6363_RG_VIO18_VOCAL_ADDR (0x1f1b) |
| #define MT6363_RG_VIO18_VOCAL_MASK (0xf) |
| #define MT6363_RG_VIO18_VOSEL_ADDR (0x1f1c) |
| #define MT6363_RG_VIO18_VOSEL_MASK (0xf) |
| #define MT6363_RG_VM18_VOCAL_ADDR (0x1f1f) |
| #define MT6363_RG_VM18_VOCAL_MASK (0xf) |
| #define MT6363_RG_VM18_VOSEL_ADDR (0x1f20) |
| #define MT6363_RG_VM18_VOSEL_MASK (0xf) |
| #define MT6363_RG_VA15_VOCAL_ADDR (0x1f23) |
| #define MT6363_RG_VA15_VOCAL_MASK (0xf) |
| #define MT6363_RG_VA15_VOSEL_ADDR (0x1f24) |
| #define MT6363_RG_VA15_VOSEL_MASK (0xf) |
| #define MT6363_RG_VRF18_VOCAL_ADDR (0x1f27) |
| #define MT6363_RG_VRF18_VOCAL_MASK (0xf) |
| #define MT6363_RG_VRF18_VOSEL_ADDR (0x1f28) |
| #define MT6363_RG_VRF18_VOSEL_MASK (0xf) |
| #define MT6363_RG_VRFIO18_VOCAL_ADDR (0x1f2b) |
| #define MT6363_RG_VRFIO18_VOCAL_MASK (0xf) |
| #define MT6363_RG_VRFIO18_VOSEL_ADDR (0x1f2c) |
| #define MT6363_RG_VRFIO18_VOSEL_MASK (0xf) |
| #define MT6363_RG_VIO075_VOCAL_ADDR (0x1f31) |
| #define MT6363_RG_VIO075_VOCAL_MASK (0xf) |
| #define MT6363_RG_VIO075_VOSEL_ADDR (0x1f31) |
| #define MT6363_RG_VIO075_VOSEL_MASK (0x70) |
| #define MT6363_RG_VCN13_VOCAL_ADDR (0x1f88) |
| #define MT6363_RG_VCN13_VOCAL_MASK (0xf) |
| #define MT6363_RG_VUFS12_VOCAL_ADDR (0x1f91) |
| #define MT6363_RG_VUFS12_VOCAL_MASK (0xf) |
| #define MT6363_RG_VUFS12_VOSEL_ADDR (0x1f92) |
| #define MT6363_RG_VUFS12_VOSEL_MASK (0xf) |
| #define MT6363_RG_VA12_1_VOCAL_ADDR (0x1f95) |
| #define MT6363_RG_VA12_1_VOCAL_MASK (0xf) |
| #define MT6363_RG_VA12_1_VOSEL_ADDR (0x1f96) |
| #define MT6363_RG_VA12_1_VOSEL_MASK (0xf) |
| #define MT6363_RG_VA12_2_VOCAL_ADDR (0x1f99) |
| #define MT6363_RG_VA12_2_VOCAL_MASK (0xf) |
| #define MT6363_RG_VA12_2_VOSEL_ADDR (0x1f9a) |
| #define MT6363_RG_VA12_2_VOSEL_MASK (0xf) |
| #define MT6363_RG_VRF12_VOCAL_ADDR (0x1f9d) |
| #define MT6363_RG_VRF12_VOCAL_MASK (0xf) |
| #define MT6363_RG_VRF12_VOSEL_ADDR (0x1f9e) |
| #define MT6363_RG_VRF12_VOSEL_MASK (0xf) |
| #define MT6363_RG_VRF13_VOCAL_ADDR (0x1fa1) |
| #define MT6363_RG_VRF13_VOCAL_MASK (0xf) |
| #define MT6363_RG_VRF13_VOSEL_ADDR (0x1fa2) |
| #define MT6363_RG_VRF13_VOSEL_MASK (0xf) |
| #define MT6363_RG_VRF09_VOCAL_ADDR (0x1fa8) |
| #define MT6363_RG_VRF09_VOCAL_MASK (0xf) |
| #define MT6363_RG_VRF09_VOSEL_ADDR (0x1fa9) |
| #define MT6363_RG_VRF09_VOSEL_MASK (0xf) |
| #define MT6363_ISINK_EN_CTRL0 (0x220b) |
| #define MT6363_ISINK_EN_CTRL1 (0x220c) |
| |
| |
| #endif /* __LINUX_REGULATOR_MT6363_H */ |
