| /* SPDX-License-Identifier: GPL-2.0-only */ |
| /* |
| * Copyright (c) 2021 MediaTek Inc. |
| * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> |
| */ |
| |
| #ifndef _DT_BINDINGS_POWER_MT8188_POWER_H |
| #define _DT_BINDINGS_POWER_MT8188_POWER_H |
| |
| #define MT8188_POWER_DOMAIN_MFG0 0 |
| #define MT8188_POWER_DOMAIN_MFG1 1 |
| #define MT8188_POWER_DOMAIN_MFG2 2 |
| #define MT8188_POWER_DOMAIN_MFG3 3 |
| #define MT8188_POWER_DOMAIN_MFG4 4 |
| #define MT8188_POWER_DOMAIN_PEXTP_MAC_P0 5 |
| #define MT8188_POWER_DOMAIN_PEXTP_PHY_TOP 6 |
| #define MT8188_POWER_DOMAIN_CSIRX_TOP 7 |
| #define MT8188_POWER_DOMAIN_ETHER 8 |
| #define MT8188_POWER_DOMAIN_HDMI_TX 9 |
| #define MT8188_POWER_DOMAIN_ADSP_AO 10 |
| #define MT8188_POWER_DOMAIN_ADSP_INFRA 11 |
| #define MT8188_POWER_DOMAIN_ADSP 12 |
| #define MT8188_POWER_DOMAIN_AUDIO 13 |
| #define MT8188_POWER_DOMAIN_AUDIO_ASRC 14 |
| #define MT8188_POWER_DOMAIN_VPPSYS0 15 |
| #define MT8188_POWER_DOMAIN_VDOSYS0 16 |
| #define MT8188_POWER_DOMAIN_VDOSYS1 17 |
| #define MT8188_POWER_DOMAIN_DP_TX 18 |
| #define MT8188_POWER_DOMAIN_EDP_TX 19 |
| #define MT8188_POWER_DOMAIN_VPPSYS1 20 |
| #define MT8188_POWER_DOMAIN_WPE 21 |
| #define MT8188_POWER_DOMAIN_VDEC0 22 |
| #define MT8188_POWER_DOMAIN_VDEC1 23 |
| #define MT8188_POWER_DOMAIN_VENC 24 |
| #define MT8188_POWER_DOMAIN_IMG_VCORE 25 |
| #define MT8188_POWER_DOMAIN_IMG_MAIN 26 |
| #define MT8188_POWER_DOMAIN_DIP 27 |
| #define MT8188_POWER_DOMAIN_IPE 28 |
| #define MT8188_POWER_DOMAIN_CAM_VCORE 29 |
| #define MT8188_POWER_DOMAIN_CAM_MAIN 30 |
| #define MT8188_POWER_DOMAIN_CAM_SUBA 31 |
| #define MT8188_POWER_DOMAIN_CAM_SUBB 32 |
| |
| #endif /* _DT_BINDINGS_POWER_MT8188_POWER_H */ |
