| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* |
| * Copyright (C) 2021 MediaTek Inc. |
| */ |
| #ifndef _MT6338_H_ |
| #define _MT6338_H_ |
| /*************Register Bit Define*************/ |
| #define MT6338_AUDIO_REG_COUNT 3045 |
| #define MT6338_MAX_REGISTER MT6338_ACCDET_CON40 |
| |
| #define MT6338_TOP0_ID 0x0 |
| #define MT6338_TOP0_ID_H 0x1 |
| #define MT6338_TOP0_REV0 0x2 |
| #define MT6338_TOP0_REV0_H 0x3 |
| #define MT6338_TOP0_DSN_DBI 0x4 |
| #define MT6338_TOP0_DSN_DBI_H 0x5 |
| #define MT6338_TOP0_DSN_DXI 0x6 |
| #define MT6338_TOP0_DMY 0x7 |
| #define MT6338_HWCID_L 0x8 |
| #define MT6338_HWCID_H 0x9 |
| #define MT6338_SWCID_L 0xa |
| #define MT6338_SWCID_H 0xb |
| #define MT6338_TOP_CON 0xc |
| #define MT6338_TEST_OUT 0xd |
| #define MT6338_TEST_OUT_H 0xe |
| #define MT6338_TEST_CON0 0xf |
| #define MT6338_TEST_CON1 0x10 |
| #define MT6338_TEST_CON2 0x11 |
| #define MT6338_TEST_CON3 0x12 |
| #define MT6338_TEST_CON4 0x13 |
| #define MT6338_TEST_CON5 0x14 |
| #define MT6338_TEST_CON6 0x15 |
| #define MT6338_TEST_CON7 0x16 |
| #define MT6338_TEST_CON8 0x17 |
| #define MT6338_TEST_CON9 0x18 |
| #define MT6338_TEST_CON10 0x19 |
| #define MT6338_TEST_CON11 0x1a |
| #define MT6338_TESTMODE_SW 0x1b |
| #define MT6338_TDSEL_CON0 0x1c |
| #define MT6338_TDSEL_CON1 0x1d |
| #define MT6338_RDSEL_CON 0x1e |
| #define MT6338_SMT_CON0 0x1f |
| #define MT6338_SMT_CON1 0x20 |
| #define MT6338_TOP_RSV0 0x21 |
| #define MT6338_TOP_RSV1 0x22 |
| #define MT6338_DRV_CON0 0x23 |
| #define MT6338_DRV_CON1 0x24 |
| #define MT6338_DRV_CON2 0x25 |
| #define MT6338_DRV_CON3 0x26 |
| #define MT6338_DRV_CON4 0x27 |
| #define MT6338_DRV_CON5 0x28 |
| #define MT6338_TOP_STATUS 0x29 |
| #define MT6338_TOP_STATUS_SET 0x2a |
| #define MT6338_TOP_STATUS_CLR 0x2b |
| #define MT6338_TOP_PWOFF_CON 0x2c |
| #define MT6338_TOP_TRAP 0x2d |
| #define MT6338_TMBIST_CFG00 0x2e |
| #define MT6338_TMBIST_CFG01 0x2f |
| #define MT6338_TMBIST_CFG02 0x30 |
| #define MT6338_TMBIST_CFG10 0x31 |
| #define MT6338_TMBIST_CFG11 0x32 |
| #define MT6338_TMBIST_CFG12 0x33 |
| #define MT6338_TMBIST_CFG20 0x34 |
| #define MT6338_TMBIST_CFG21 0x35 |
| #define MT6338_TMBIST_CFG22 0x36 |
| #define MT6338_TMBIST_CFG30 0x37 |
| #define MT6338_TMBIST_CFG31 0x38 |
| #define MT6338_TMBIST_CFG32 0x39 |
| #define MT6338_TOP1_ID 0x80 |
| #define MT6338_TOP1_ID_H 0x81 |
| #define MT6338_TOP1_REV0 0x82 |
| #define MT6338_TOP1_REV0_H 0x83 |
| #define MT6338_TOP1_DSN_DBI 0x84 |
| #define MT6338_TOP1_DSN_DBI_H 0x85 |
| #define MT6338_TOP1_DSN_DXI 0x86 |
| #define MT6338_GPIO_DIR0 0x87 |
| #define MT6338_GPIO_DIR0_SET 0x88 |
| #define MT6338_GPIO_DIR0_CLR 0x89 |
| #define MT6338_GPIO_DIR1 0x8a |
| #define MT6338_GPIO_DIR1_SET 0x8b |
| #define MT6338_GPIO_DIR1_CLR 0x8c |
| #define MT6338_GPIO_PULLEN0 0x8d |
| #define MT6338_GPIO_PULLEN0_SET 0x8e |
| #define MT6338_GPIO_PULLEN0_CLR 0x8f |
| #define MT6338_GPIO_PULLEN1 0x90 |
| #define MT6338_GPIO_PULLEN1_SET 0x91 |
| #define MT6338_GPIO_PULLEN1_CLR 0x92 |
| #define MT6338_GPIO_PULLSEL0 0x93 |
| #define MT6338_GPIO_PULLSEL0_SET 0x94 |
| #define MT6338_GPIO_PULLSEL0_CLR 0x95 |
| #define MT6338_GPIO_PULLSEL1 0x96 |
| #define MT6338_GPIO_PULLSEL1_SET 0x97 |
| #define MT6338_GPIO_PULLSEL1_CLR 0x98 |
| #define MT6338_GPIO_DINV0 0x99 |
| #define MT6338_GPIO_DINV0_SET 0x9a |
| #define MT6338_GPIO_DINV0_CLR 0x9b |
| #define MT6338_GPIO_DINV1 0x9c |
| #define MT6338_GPIO_DINV1_SET 0x9d |
| #define MT6338_GPIO_DINV1_CLR 0x9e |
| #define MT6338_GPIO_DOUT0 0x9f |
| #define MT6338_GPIO_DOUT0_SET 0xa0 |
| #define MT6338_GPIO_DOUT0_CLR 0xa1 |
| #define MT6338_GPIO_DOUT1 0xa2 |
| #define MT6338_GPIO_DOUT1_SET 0xa3 |
| #define MT6338_GPIO_DOUT1_CLR 0xa4 |
| #define MT6338_GPIO_PI0 0xa5 |
| #define MT6338_GPIO_PI1 0xa6 |
| #define MT6338_GPIO_POE0 0xa7 |
| #define MT6338_GPIO_POE1 0xa8 |
| #define MT6338_GPIO_MODE0 0xa9 |
| #define MT6338_GPIO_MODE0_SET 0xaa |
| #define MT6338_GPIO_MODE0_CLR 0xab |
| #define MT6338_GPIO_MODE1 0xac |
| #define MT6338_GPIO_MODE1_SET 0xad |
| #define MT6338_GPIO_MODE1_CLR 0xae |
| #define MT6338_GPIO_MODE2 0xaf |
| #define MT6338_GPIO_MODE2_SET 0xb0 |
| #define MT6338_GPIO_MODE2_CLR 0xb1 |
| #define MT6338_GPIO_MODE3 0xb2 |
| #define MT6338_GPIO_MODE3_SET 0xb3 |
| #define MT6338_GPIO_MODE3_CLR 0xb4 |
| #define MT6338_GPIO_MODE4 0xb5 |
| #define MT6338_GPIO_MODE4_SET 0xb6 |
| #define MT6338_GPIO_MODE4_CLR 0xb7 |
| #define MT6338_GPIO_MODE5 0xb8 |
| #define MT6338_GPIO_MODE5_SET 0xb9 |
| #define MT6338_GPIO_MODE5_CLR 0xba |
| #define MT6338_GPIO_MODE6 0xbb |
| #define MT6338_GPIO_MODE6_SET 0xbc |
| #define MT6338_GPIO_MODE6_CLR 0xbd |
| #define MT6338_GPIO_RSV 0xbe |
| #define MT6338_GPIO_CON 0xbf |
| #define MT6338_TOP2_ID 0x100 |
| #define MT6338_TOP2_ID_H 0x101 |
| #define MT6338_TOP2_REV0 0x102 |
| #define MT6338_TOP2_REV0_H 0x103 |
| #define MT6338_TOP2_DSN_DBI 0x104 |
| #define MT6338_TOP2_DSN_DBI_H 0x105 |
| #define MT6338_TOP2_DSN_DXI 0x106 |
| #define MT6338_TOP_PAM0 0x107 |
| #define MT6338_TOP_PAM0_H 0x108 |
| #define MT6338_TOP_PAM1 0x109 |
| #define MT6338_TOP_PAM1_H 0x10a |
| #define MT6338_TOP_CKPDN_CON0 0x10b |
| #define MT6338_TOP_CKPDN_CON0_SET 0x10c |
| #define MT6338_TOP_CKPDN_CON0_CLR 0x10d |
| #define MT6338_TOP_CKPDN_CON1 0x10e |
| #define MT6338_TOP_CKPDN_CON1_SET 0x10f |
| #define MT6338_TOP_CKPDN_CON1_CLR 0x110 |
| #define MT6338_TOP_CKSEL_CON0 0x111 |
| #define MT6338_TOP_CKSEL_CON0_SET 0x112 |
| #define MT6338_TOP_CKSEL_CON0_CLR 0x113 |
| #define MT6338_TOP_CKDIVSEL_CON0 0x114 |
| #define MT6338_TOP_CKDIVSEL_CON0_SET 0x115 |
| #define MT6338_TOP_CKDIVSEL_CON0_CLR 0x116 |
| #define MT6338_TOP_CKHWEN_CON0 0x117 |
| #define MT6338_TOP_CKHWEN_CON0_SET 0x118 |
| #define MT6338_TOP_CKHWEN_CON0_CLR 0x119 |
| #define MT6338_TOP_SMPS_OSC_DBG 0x11a |
| #define MT6338_TOP_CKTST_CON0 0x11b |
| #define MT6338_TOP_CKTST_CON1 0x11c |
| #define MT6338_TOP_CLK_CON0 0x11d |
| #define MT6338_TOP_RST_CON0 0x11e |
| #define MT6338_TOP_RST_CON0_SET 0x11f |
| #define MT6338_TOP_RST_CON0_CLR 0x120 |
| #define MT6338_TOP_RST_CON1 0x121 |
| #define MT6338_TOP_RST_CON1_SET 0x122 |
| #define MT6338_TOP_RST_CON1_CLR 0x123 |
| #define MT6338_TOP_RST_CON2 0x124 |
| #define MT6338_TOP_RST_CON3 0x125 |
| #define MT6338_TOP_RST_STATUS 0x126 |
| #define MT6338_TOP_RST_STATUS_SET 0x127 |
| #define MT6338_TOP_RST_STATUS_CLR 0x128 |
| #define MT6338_TOP_FQMTR_CON0 0x129 |
| #define MT6338_TOP_FQMTR_CON1 0x12a |
| #define MT6338_TOP_FQMTR_CON2 0x12b |
| #define MT6338_TOP_FQMTR_DAT0 0x12c |
| #define MT6338_TOP_FQMTR_DAT1 0x12d |
| #define MT6338_TOP2_ELR_NUM 0x12e |
| #define MT6338_TOP2_ELR0 0x12f |
| #define MT6338_TOP2_ELR1 0x130 |
| #define MT6338_TOP2_ELR2 0x131 |
| #define MT6338_TOP2_ELR3 0x132 |
| #define MT6338_TOP2_ELR4 0x133 |
| #define MT6338_TOP2_ELR5 0x134 |
| #define MT6338_TOP2_ELR6 0x135 |
| #define MT6338_TOP2_ELR7 0x136 |
| #define MT6338_TOP3_ID 0x180 |
| #define MT6338_TOP3_ID_H 0x181 |
| #define MT6338_TOP3_REV0 0x182 |
| #define MT6338_TOP3_REV0_H 0x183 |
| #define MT6338_TOP3_DSN_DBI 0x184 |
| #define MT6338_TOP3_DSN_DBI_H 0x185 |
| #define MT6338_TOP3_DSN_DXI 0x186 |
| #define MT6338_TOP_INT_CON0 0x187 |
| #define MT6338_TOP_INT_CON0_SET 0x188 |
| #define MT6338_TOP_INT_CON0_CLR 0x189 |
| #define MT6338_TOP_INT_MASK_CON0 0x18a |
| #define MT6338_TOP_INT_MASK_CON0_SET 0x18b |
| #define MT6338_TOP_INT_MASK_CON0_CLR 0x18c |
| #define MT6338_TOP_INT_STATUS0 0x18d |
| #define MT6338_TOP_INT_STATUS1 0x18e |
| #define MT6338_TOP_INT_RAW_STATUS0 0x18f |
| #define MT6338_TOP_INT_RAW_STATUS1 0x190 |
| #define MT6338_TOP_INT_CON1 0x191 |
| #define MT6338_PMRC_CON0 0x192 |
| #define MT6338_PMRC_CON0_SET 0x193 |
| #define MT6338_PMRC_CON0_CLR 0x194 |
| #define MT6338_PMRC_CON1 0x195 |
| #define MT6338_PMRC_CON1_SET 0x196 |
| #define MT6338_PMRC_CON1_CLR 0x197 |
| #define MT6338_VDIG18_CON0 0x198 |
| #define MT6338_VDIG18_CON1 0x199 |
| #define MT6338_SPMI_WR_ADDR_MASK 0x19a |
| #define MT6338_SPMI_WR_ADDR_MASK_H 0x19b |
| #define MT6338_SPMI_RD_ADDR 0x19c |
| #define MT6338_SPMI_RD_ADDR_H 0x19d |
| #define MT6338_SPMI_RD_ADDR_MASK 0x19e |
| #define MT6338_SPMI_RD_ADDR_MASK_H 0x19f |
| #define MT6338_SPMI_WR_DATA 0x1a0 |
| #define MT6338_SPMI_WR_DATA_MASK 0x1a1 |
| #define MT6338_SPMI_RD_DATA 0x1a2 |
| #define MT6338_SPMI_RD_DATA_MASK 0x1a3 |
| #define MT6338_SPMI_INT_STS 0x1a4 |
| #define MT6338_SPMI_INT_EN 0x1a5 |
| #define MT6338_SPMI_RCS_BUS_SEL 0x1a6 |
| #define MT6338_SPMI_RCS_CLK_SEL 0x1a7 |
| #define MT6338_DA_INTF_STTING0 0x1a8 |
| #define MT6338_DA_INTF_STTING1 0x1a9 |
| #define MT6338_DA_INTF_STTING2 0x1aa |
| #define MT6338_DA_INTF_STTING3 0x1ab |
| #define MT6338_AD_STATUS0 0x1ac |
| #define MT6338_MTC_CTL0 0x1ad |
| #define MT6338_MTC_CTL1 0x1ae |
| #define MT6338_MTC_CTL2 0x1af |
| #define MT6338_MTC_STS0 0x1b0 |
| #define MT6338_MTC_STS1 0x1b1 |
| #define MT6338_PLT0_ID_ANA_ID 0x380 |
| #define MT6338_PLT0_ID_DIG_ID 0x381 |
| #define MT6338_PLT0_REV0 0x382 |
| #define MT6338_PLT0_REV1 0x383 |
| #define MT6338_PLT0_REV2 0x384 |
| #define MT6338_PLT0_REV3 0x385 |
| #define MT6338_PLT0_DSN_DXI 0x386 |
| #define MT6338_TOP_CLK_TRIM_0 0x387 |
| #define MT6338_TOP_CLK_TRIM_1 0x388 |
| #define MT6338_TOP_CLK_TRIM_2 0x389 |
| #define MT6338_TOP_CLK_TRIM_3 0x38a |
| #define MT6338_PLT_CON0 0x38b |
| #define MT6338_PLT_CON1 0x38c |
| #define MT6338_OTP_CON0 0x38d |
| #define MT6338_OTP_CON1 0x38e |
| #define MT6338_OTP_CON3 0x38f |
| #define MT6338_OTP_CON4 0x390 |
| #define MT6338_OTP_CON5 0x391 |
| #define MT6338_OTP_CON6 0x392 |
| #define MT6338_OTP_CON7 0x393 |
| #define MT6338_OTP_CON8 0x394 |
| #define MT6338_OTP_CON9 0x395 |
| #define MT6338_OTP_CON10 0x396 |
| #define MT6338_OTP_CON11 0x397 |
| #define MT6338_OTP_CON12 0x398 |
| #define MT6338_OTP_CON13 0x399 |
| #define MT6338_OTP_CON14 0x39a |
| #define MT6338_OTP_CON15 0x39b |
| #define MT6338_OTP_CON17 0x39c |
| #define MT6338_OTP_CON18 0x39d |
| #define MT6338_OTP_CON19 0x39e |
| #define MT6338_OTP_CON20 0x39f |
| #define MT6338_OTP_CON21 0x3a0 |
| #define MT6338_TOP_TMA_KEY 0x3a1 |
| #define MT6338_TOP_TMA_KEY_H 0x3a2 |
| #define MT6338_TOP_ANA_KEY 0x3a3 |
| #define MT6338_TOP_ANA_KEY_H 0x3a4 |
| #define MT6338_TOP_MDB_CONF0 0x3a5 |
| #define MT6338_TOP_MDB_CONF0_H 0x3a6 |
| #define MT6338_TOP_MDB_CONF1 0x3a7 |
| #define MT6338_TOP_MDB_CONF1_H 0x3a8 |
| #define MT6338_TOP_MDB_CONF2 0x3a9 |
| #define MT6338_TOP_DIG_WPK 0x3aa |
| #define MT6338_TOP_DIG_WPK_H 0x3ab |
| #define MT6338_PLT0_ELR_NUM 0x3ac |
| #define MT6338_PLT0_ELR0 0x3ad |
| #define MT6338_PLT0_ELR1 0x3ae |
| #define MT6338_I2CRECORD_ID_ANA_ID 0x400 |
| #define MT6338_I2CRECORD_ID_DIG_ID 0x401 |
| #define MT6338_I2CRECORD_REV0 0x402 |
| #define MT6338_I2CRECORD_REV1 0x403 |
| #define MT6338_I2CRECORD_REV2 0x404 |
| #define MT6338_I2CRECORD_REV3 0x405 |
| #define MT6338_I2CRECORD_DSN_DXI 0x406 |
| #define MT6338_RECORD_CMD0_H 0x407 |
| #define MT6338_RECORD_CMD0_L 0x408 |
| #define MT6338_RECORD_CMD1_H 0x409 |
| #define MT6338_RECORD_CMD1_L 0x40a |
| #define MT6338_RECORD_CMD2_H 0x40b |
| #define MT6338_RECORD_CMD2_L 0x40c |
| #define MT6338_RECORD_CMD3_H 0x40d |
| #define MT6338_RECORD_CMD3_L 0x40e |
| #define MT6338_RECORD_CMD4_H 0x40f |
| #define MT6338_RECORD_CMD4_L 0x410 |
| #define MT6338_RECORD_CMD5_H 0x411 |
| #define MT6338_RECORD_CMD5_L 0x412 |
| #define MT6338_RECORD_CMD6_H 0x413 |
| #define MT6338_RECORD_CMD6_L 0x414 |
| #define MT6338_RECORD_CMD7_H 0x415 |
| #define MT6338_RECORD_CMD7_L 0x416 |
| #define MT6338_RECORD_CMD8_H 0x417 |
| #define MT6338_RECORD_CMD8_L 0x418 |
| #define MT6338_RECORD_CMD9_H 0x419 |
| #define MT6338_RECORD_CMD9_L 0x41a |
| #define MT6338_RECORD_CMD10_H 0x41b |
| #define MT6338_RECORD_CMD10_L 0x41c |
| #define MT6338_RECORD_CMD11_H 0x41d |
| #define MT6338_RECORD_CMD11_L 0x41e |
| #define MT6338_RECORD_CMD12_H 0x41f |
| #define MT6338_RECORD_CMD12_L 0x420 |
| #define MT6338_RECORD_CMD13_H 0x421 |
| #define MT6338_RECORD_CMD13_L 0x422 |
| #define MT6338_RECORD_CMD14_H 0x423 |
| #define MT6338_RECORD_CMD14_L 0x424 |
| #define MT6338_RECORD_CMD15_H 0x425 |
| #define MT6338_RECORD_CMD15_L 0x426 |
| #define MT6338_RECORD_DATA0 0x427 |
| #define MT6338_RECORD_DATA1 0x428 |
| #define MT6338_RECORD_DATA2 0x429 |
| #define MT6338_RECORD_DATA3 0x42a |
| #define MT6338_RECORD_DATA4 0x42b |
| #define MT6338_RECORD_DATA5 0x42c |
| #define MT6338_RECORD_DATA6 0x42d |
| #define MT6338_RECORD_DATA7 0x42e |
| #define MT6338_RECORD_DATA8 0x42f |
| #define MT6338_RECORD_DATA9 0x430 |
| #define MT6338_RECORD_DATA10 0x431 |
| #define MT6338_RECORD_DATA11 0x432 |
| #define MT6338_RECORD_DATA12 0x433 |
| #define MT6338_RECORD_DATA13 0x434 |
| #define MT6338_RECORD_DATA14 0x435 |
| #define MT6338_RECORD_DATA15 0x436 |
| #define MT6338_RECORD_CON0 0x437 |
| #define MT6338_RECORD_CON1 0x438 |
| #define MT6338_RECORD_CON2 0x439 |
| #define MT6338_RECORD_CON3 0x43a |
| #define MT6338_RECORD_CON4 0x43b |
| #define MT6338_RECORD_CON5 0x43c |
| #define MT6338_RECORD_CON6 0x43d |
| #define MT6338_RECORD_CON7 0x43e |
| #define MT6338_RECORD_CON8 0x43f |
| #define MT6338_RECORD_CON9 0x440 |
| #define MT6338_RECORD_CON10 0x441 |
| #define MT6338_RECORD_CON11 0x442 |
| #define MT6338_INT_CON0 0x443 |
| #define MT6338_INT_CON1 0x444 |
| #define MT6338_INT_CON2 0x445 |
| #define MT6338_INT_CON3 0x446 |
| #define MT6338_INT_CON4 0x447 |
| #define MT6338_INT_CON5 0x448 |
| #define MT6338_INT_CON6 0x449 |
| #define MT6338_INT_CON7 0x44a |
| #define MT6338_INT_CON8 0x44b |
| #define MT6338_INT_CON9 0x44c |
| #define MT6338_INT_CON10 0x44d |
| #define MT6338_INT_CON11 0x44e |
| #define MT6338_RECORD_INT_CON0 0x44f |
| #define MT6338_RECORD_INT_CON1 0x450 |
| #define MT6338_DEW_WRITE_TEST_L 0x451 |
| #define MT6338_DEW_WRITE_TEST_H 0x452 |
| #define MT6338_I2C_TEST_CON0 0x453 |
| #define MT6338_SPMI_ANA_ID 0x480 |
| #define MT6338_SPMI_DIG_ID 0x481 |
| #define MT6338_SPMI_ANA_REV0 0x482 |
| #define MT6338_SPMI_DIG_REV0 0x483 |
| #define MT6338_SPMI_REV1 0x484 |
| #define MT6338_SPMI_ESP 0x485 |
| #define MT6338_SPMI_DSN_FPI 0x486 |
| #define MT6338_SPMI_DSN_DXI 0x487 |
| #define MT6338_PLT_DIG_WPK 0x488 |
| #define MT6338_PLT_DIG_WPK_H 0x489 |
| #define MT6338_SPMI_EXT_ADDR1 0x48a |
| #define MT6338_SPMI_EXT_ADDR0 0x48b |
| #define MT6338_SPMI_EXT_ADDR0_H 0x48c |
| #define MT6338_SPMI_EXT_ADDR2 0x48d |
| #define MT6338_SPMI_EXT_ADDR2_H 0x48e |
| #define MT6338_SPMI_RCS_FUN0 0x48f |
| #define MT6338_SPMI_RCS_FUN1 0x490 |
| #define MT6338_SPMI_RCS_FUN2 0x491 |
| #define MT6338_SPMI_WR_ADDR 0x492 |
| #define MT6338_SPMI_WR_ADDR_H 0x493 |
| #define MT6338_SPMI_REG_RSV0 0x494 |
| #define MT6338_SPMI_REG_RSV1 0x495 |
| #define MT6338_SPMI_REG_RSV2 0x496 |
| #define MT6338_SPMI_DEBUG_OUT_L 0x497 |
| #define MT6338_SPMI_DEBUG_OUT_H 0x498 |
| #define MT6338_SPMI_DEBUG_SEL 0x499 |
| #define MT6338_SPMI_RSV0 0x49a |
| #define MT6338_SPMI_RSV1 0x49b |
| #define MT6338_PSC_TOP_ID_ANA 0x900 |
| #define MT6338_PSC_TOP_ID_DIG 0x901 |
| #define MT6338_PSC_TOP_REV0 0x902 |
| #define MT6338_PSC_TOP_REV1 0x903 |
| #define MT6338_PSC_TOP_DBI0 0x904 |
| #define MT6338_PSC_TOP_DBI1 0x905 |
| #define MT6338_PSC_TOP_DXI 0x906 |
| #define MT6338_PSC_CON0 0x907 |
| #define MT6338_PSC_CON1 0x908 |
| #define MT6338_PSC_CON2 0x909 |
| #define MT6338_PSC_WPK_L 0x90a |
| #define MT6338_PSC_WPK_H 0x90b |
| #define MT6338_PSC_DBG0 0x90c |
| #define MT6338_PSC_ELR_NUM 0x90d |
| #define MT6338_PSC_ELR0 0x90e |
| #define MT6338_PSC_ELR1 0x90f |
| #define MT6338_ANATOP_ANA_ID 0x980 |
| #define MT6338_ANATOP_DIG_ID 0x981 |
| #define MT6338_ANATOP_ANA_REV 0x982 |
| #define MT6338_ANATOP_DIG_REV 0x983 |
| #define MT6338_ANATOP_DBI 0x984 |
| #define MT6338_ANATOP_ESP 0x985 |
| #define MT6338_ANATOP_FPI 0x986 |
| #define MT6338_ANATOP_DXI 0x987 |
| #define MT6338_STRUP_PMU_CON0 0x988 |
| #define MT6338_STRUP_PMU_CON1 0x989 |
| #define MT6338_STRUP_PMU_CON2 0x98a |
| #define MT6338_TSBG_PMU_CON0 0x98b |
| #define MT6338_TSBG_PMU_CON1 0x98c |
| #define MT6338_IVGEN_PMU_CON0 0x98d |
| #define MT6338_IVGEN_PMU_CON1 0x98e |
| #define MT6338_CLKSQ_PMU_CON0 0x98f |
| #define MT6338_SPIOSC_PMU_CON0 0x990 |
| #define MT6338_PLL208M_PMU_CON0 0x991 |
| #define MT6338_PLL208M_PMU_CON1 0x992 |
| #define MT6338_PLL208M_PMU_CON2 0x993 |
| #define MT6338_PLL208M_PMU_CON3 0x994 |
| #define MT6338_PLL208M_PMU_CON4 0x995 |
| #define MT6338_PLL208M_PMU_CON5 0x996 |
| #define MT6338_VOWPLL_PMU_CON0 0x997 |
| #define MT6338_VOWPLL_PMU_CON1 0x998 |
| #define MT6338_VOWPLL_PMU_CON2 0x999 |
| #define MT6338_VOWPLL_PMU_CON3 0x99a |
| #define MT6338_VOWPLL_PMU_CON4 0x99b |
| #define MT6338_VOWPLL_PMU_CON5 0x99c |
| #define MT6338_VOWPLL_PMU_CON6 0x99d |
| #define MT6338_VOWPLL_PMU_CON7 0x99e |
| #define MT6338_VOWPLL_PMU_CON8 0x99f |
| #define MT6338_VOWPLL_PMU_CON9 0x9a0 |
| #define MT6338_ANATOP_ELR_NUM 0x9a1 |
| #define MT6338_STRUP_ELR_0 0x9a2 |
| #define MT6338_STRUP_ELR_1 0x9a3 |
| #define MT6338_STRUP_ELR_2 0x9a4 |
| #define MT6338_HK_TOP_DSN_ID0 0xf80 |
| #define MT6338_HK_TOP_DSN_ID1 0xf81 |
| #define MT6338_HK_TOP_REV0 0xf82 |
| #define MT6338_HK_TOP_REV1 0xf83 |
| #define MT6338_HK_TOP_DBI 0xf84 |
| #define MT6338_HK_TOP_ESP 0xf85 |
| #define MT6338_HK_TOP_DXI 0xf86 |
| #define MT6338_HK_TPM0 0xf87 |
| #define MT6338_HK_TPM1 0xf88 |
| #define MT6338_HK_TPM2 0xf89 |
| #define MT6338_HK_TPM3 0xf8a |
| #define MT6338_HK_TOP_CLK_CON0 0xf8b |
| #define MT6338_HK_TOP_CLK_CON1 0xf8c |
| #define MT6338_HK_TOP_RST_CON0 0xf8d |
| #define MT6338_HK_TOP_MON_CON0 0xf8e |
| #define MT6338_HK_TOP_MON_CON2 0xf8f |
| #define MT6338_HK_TOP_STRUP_CON0 0xf90 |
| #define MT6338_HK_TOP_STRUP_CON1 0xf91 |
| #define MT6338_HK_TOP_LDO_CON 0xf92 |
| #define MT6338_HK_TOP_LDO_STATUS 0xf93 |
| #define MT6338_HK_TOP_WKEY_L 0xf94 |
| #define MT6338_HK_TOP_WKEY_H 0xf95 |
| #define MT6338_HK_TOP_TEST_CON 0xf96 |
| #define MT6338_AUXADC_ANA_ID 0x1000 |
| #define MT6338_AUXADC_DIG_ID 0x1001 |
| #define MT6338_AUXADC_ANA_REV 0x1002 |
| #define MT6338_AUXADC_DIG_REV 0x1003 |
| #define MT6338_AUXADC_DBI 0x1004 |
| #define MT6338_AUXADC_ESP 0x1005 |
| #define MT6338_AUXADC_FPI 0x1006 |
| #define MT6338_AUXADC_PMU_CON0 0x1007 |
| #define MT6338_AUXADC_PMU_CON1 0x1008 |
| #define MT6338_AUXADC_PMU_CON2 0x1009 |
| #define MT6338_AUXADC_PMU_CON3 0x100a |
| #define MT6338_AUXADC_DIG_1_DSN_ID0 0x1080 |
| #define MT6338_AUXADC_DIG_1_DSN_ID1 0x1081 |
| #define MT6338_AUXADC_DIG_1_DSN_REV0 0x1082 |
| #define MT6338_AUXADC_DIG_1_DSN_REV1 0x1083 |
| #define MT6338_AUXADC_DIG_1_DSN_DBI 0x1084 |
| #define MT6338_AUXADC_DIG_1_DSN_ESP 0x1085 |
| #define MT6338_AUXADC_DIG_1_DSN_DXI 0x1086 |
| #define MT6338_AUXADC_ADC4_L 0x1087 |
| #define MT6338_AUXADC_ADC4_H 0x1088 |
| #define MT6338_AUXADC_ADC5_L 0x1089 |
| #define MT6338_AUXADC_ADC5_H 0x108a |
| #define MT6338_AUXADC_ADC9_L 0x108b |
| #define MT6338_AUXADC_ADC9_H 0x108c |
| #define MT6338_AUXADC_ADC10_L 0x108d |
| #define MT6338_AUXADC_ADC10_H 0x108e |
| #define MT6338_AUXADC_ADC30_L 0x108f |
| #define MT6338_AUXADC_ADC30_H 0x1090 |
| #define MT6338_AUXADC_ADC45_L 0x1091 |
| #define MT6338_AUXADC_ADC45_H 0x1092 |
| #define MT6338_AUXADC_ADC46_L 0x1093 |
| #define MT6338_AUXADC_ADC46_H 0x1094 |
| #define MT6338_AUXADC_STA0 0x1095 |
| #define MT6338_AUXADC_STA1 0x1096 |
| #define MT6338_AUXADC_STA3 0x1097 |
| #define MT6338_AUXADC_STA4 0x1098 |
| #define MT6338_AUXADC_SPL_LIST_0 0x1099 |
| #define MT6338_AUXADC_DIG_2_DSN_ID0 0x1100 |
| #define MT6338_AUXADC_DIG_2_DSN_ID1 0x1101 |
| #define MT6338_AUXADC_DIG_2_DSN_REV0 0x1102 |
| #define MT6338_AUXADC_DIG_2_DSN_REV1 0x1103 |
| #define MT6338_AUXADC_DIG_2_DSN_DBI 0x1104 |
| #define MT6338_AUXADC_DIG_2_DSN_ESP 0x1105 |
| #define MT6338_AUXADC_DIG_2_DSN_DXI 0x1106 |
| #define MT6338_AUXADC_RQST0 0x1107 |
| #define MT6338_AUXADC_DIG_3_DSN_ID0 0x1180 |
| #define MT6338_AUXADC_DIG_3_DSN_ID1 0x1181 |
| #define MT6338_AUXADC_DIG_3_DSN_REV0 0x1182 |
| #define MT6338_AUXADC_DIG_3_DSN_REV1 0x1183 |
| #define MT6338_AUXADC_DIG_3_DSN_DBI 0x1184 |
| #define MT6338_AUXADC_DIG_3_DSN_ESP 0x1185 |
| #define MT6338_AUXADC_DIG_3_DSN_DXI 0x1186 |
| #define MT6338_AUXADC_CON0 0x1187 |
| #define MT6338_AUXADC_CON1 0x1188 |
| #define MT6338_AUXADC_SPL_CON0 0x1189 |
| #define MT6338_AUXADC_SPL_CON1 0x118a |
| #define MT6338_AUXADC_SPL_CON2 0x118b |
| #define MT6338_AUXADC_SPL_CON3 0x118c |
| #define MT6338_AUXADC_SPL_CON4 0x118d |
| #define MT6338_AUXADC_SPL_CON5 0x118e |
| #define MT6338_AUXADC_SPL_CON9 0x118f |
| #define MT6338_AUXADC_AVG_CON0 0x1190 |
| #define MT6338_AUXADC_AVG_CON1 0x1191 |
| #define MT6338_AUXADC_AVG_CON2 0x1192 |
| #define MT6338_AUXADC_AVG_CON3 0x1193 |
| #define MT6338_AUXADC_AVG_CON4 0x1194 |
| #define MT6338_AUXADC_TRIM_SEL2 0x1195 |
| #define MT6338_AUXADC_CON28 0x1196 |
| #define MT6338_AUXADC_CON29 0x1197 |
| #define MT6338_AUXADC_CON30 0x1198 |
| #define MT6338_AUXADC_CON31 0x1199 |
| #define MT6338_AUXADC_CON32 0x119a |
| #define MT6338_AUXADC_CON33 0x119b |
| #define MT6338_AUXADC_CON35 0x119c |
| #define MT6338_AUXADC_CON36 0x119d |
| #define MT6338_AUXADC_CON37 0x119e |
| #define MT6338_AUXADC_CON38 0x119f |
| #define MT6338_AUXADC_CON39 0x11a0 |
| #define MT6338_AUXADC_CON40 0x11a1 |
| #define MT6338_AUXADC_CON44 0x11a2 |
| #define MT6338_AUXADC_CON45 0x11a3 |
| #define MT6338_AUXADC_AUTORPT0 0x11a4 |
| #define MT6338_AUXADC_AUTORPT1 0x11a5 |
| #define MT6338_AUXADC_AUTORPT2 0x11a6 |
| #define MT6338_AUXADC_ACCDET0 0x11a7 |
| #define MT6338_AUXADC_ACCDET1 0x11a8 |
| #define MT6338_AUXADC_DBG0 0x11a9 |
| #define MT6338_AUXADC_DBG1 0x11aa |
| #define MT6338_AUXADC_PRI_NEW 0x11ab |
| #define MT6338_AUXADC_DIG_3_ELR_NUM 0x11ac |
| #define MT6338_AUXADC_DIG_3_ELR8 0x11ad |
| #define MT6338_AUXADC_DIG_3_ELR9 0x11ae |
| #define MT6338_AUXADC_DIG_3_ELR10 0x11af |
| #define MT6338_AUXADC_DIG_3_ELR11 0x11b0 |
| #define MT6338_AUXADC_DIG_3_ELR20 0x11b1 |
| #define MT6338_AUXADC_DIG_3_ELR21 0x11b2 |
| #define MT6338_AUXADC_DIG_3_ELR22 0x11b3 |
| #define MT6338_AUXADC_DIG_3_ELR23 0x11b4 |
| #define MT6338_AUXADC_DIG_3_ELR24 0x11b5 |
| #define MT6338_AUXADC_DIG_3_ELR25 0x11b6 |
| #define MT6338_AUXADC_DIG_3_ELR26 0x11b7 |
| #define MT6338_AUXADC_DIG_3_ELR27 0x11b8 |
| #define MT6338_AUXADC_DIG_3_ELR36 0x11b9 |
| #define MT6338_AUXADC_DIG_3_ELR37 0x11ba |
| #define MT6338_AUXADC_DIG_3_ELR38 0x11bb |
| #define MT6338_AUXADC_DIG_3_ELR39 0x11bc |
| #define MT6338_AUXADC_DIG_3_ELR40 0x11bd |
| #define MT6338_AUXADC_DIG_3_ELR41 0x11be |
| #define MT6338_AUXADC_DIG_3_ELR42 0x11bf |
| #define MT6338_AUXADC_DIG_3_ELR43 0x11c0 |
| #define MT6338_AUXADC_DIG_3_ELR44 0x11c1 |
| #define MT6338_AUXADC_DIG_3_ELR45 0x11c2 |
| #define MT6338_AUXADC_DIG_3_ELR46 0x11c3 |
| #define MT6338_AUXADC_DIG_3_ELR47 0x11c4 |
| #define MT6338_AUXADC_DIG_3_ELR48 0x11c5 |
| #define MT6338_AUXADC_DIG_3_ELR49 0x11c6 |
| #define MT6338_AUXADC_DIG_3_ELR50 0x11c7 |
| #define MT6338_AUXADC_DIG_3_ELR51 0x11c8 |
| #define MT6338_AUXADC_DIG_3_ELR52 0x11c9 |
| #define MT6338_AUXADC_DIG_3_ELR53 0x11ca |
| #define MT6338_AUXADC_DIG_3_ELR54 0x11cb |
| #define MT6338_AUXADC_DIG_3_ELR55 0x11cc |
| #define MT6338_LDO_TOP_ANA_ID 0x1b00 |
| #define MT6338_LDO_TOP_DIG_ID 0x1b01 |
| #define MT6338_LDO_TOP_ANA_REV 0x1b02 |
| #define MT6338_LDO_TOP_DIG_REV 0x1b03 |
| #define MT6338_LDO_TOP_DBI 0x1b04 |
| #define MT6338_PSC_TOP_ESP 0x1b05 |
| #define MT6338_LDO_TOP_FPI 0x1b06 |
| #define MT6338_LDO_TOP_DXI 0x1b07 |
| #define MT6338_LDO_TPM0 0x1b08 |
| #define MT6338_LDO_TPM0_H 0x1b09 |
| #define MT6338_LDO_TPM1 0x1b0a |
| #define MT6338_LDO_TPM1_H 0x1b0b |
| #define MT6338_LDO_TOP_CKPDN_CON0 0x1b0c |
| #define MT6338_TOP_TOP_CKHWEN_CON0 0x1b0d |
| #define MT6338_LDO_TOP_CLK_DCM_CON0 0x1b0e |
| #define MT6338_LDO_TOP_VR_CLK_CON0 0x1b0f |
| #define MT6338_LDO_VD105_OC_CON 0x1b10 |
| #define MT6338_LDO_TEST_CON0 0x1b11 |
| #define MT6338_LDO_TEST_CON1 0x1b12 |
| #define MT6338_LDO_TOP_CON0 0x1b13 |
| #define MT6338_LDO_TOP_CON1 0x1b14 |
| #define MT6338_VAUD18_ACK 0x1b15 |
| #define MT6338_LDO_TOP_ELR_NUM 0x1b16 |
| #define MT6338_LDO_TOP_ELR 0x1b17 |
| #define MT6338_LDO_GNR0_ANA_ID 0x1b80 |
| #define MT6338_LDO_GNR0_DIG_ID 0x1b81 |
| #define MT6338_LDO_GNR0_ANA_REV 0x1b82 |
| #define MT6338_LDO_GNR0_DIG_REV 0x1b83 |
| #define MT6338_LDO_GNR0_DSN_DBI 0x1b84 |
| #define MT6338_LDO_GNR0_DSN_ESP 0x1b85 |
| #define MT6338_LDO_GNR0_DSN_DXI 0x1b86 |
| #define MT6338_LDO_VAUD18_CON0 0x1b87 |
| #define MT6338_LDO_VAUD18_CON1 0x1b88 |
| #define MT6338_LDO_VAUD18_CON2 0x1b89 |
| #define MT6338_LDO_VAUD18_MON 0x1b8a |
| #define MT6338_LDO_VAUD18_OP_EN0 0x1b8b |
| #define MT6338_LDO_VAUD18_OP_EN0_SET 0x1b8c |
| #define MT6338_LDO_VAUD18_OP_EN0_CLR 0x1b8d |
| #define MT6338_LDO_VAUD18_OP_EN1 0x1b8e |
| #define MT6338_LDO_VAUD18_OP_EN1_SET 0x1b8f |
| #define MT6338_LDO_VAUD18_OP_EN1_CLR 0x1b90 |
| #define MT6338_LDO_VAUD18_OP_CFG0 0x1b91 |
| #define MT6338_LDO_VAUD18_OP_CFG0_SET 0x1b92 |
| #define MT6338_LDO_VAUD18_OP_CFG0_CLR 0x1b93 |
| #define MT6338_LDO_VAUD18_OP_CFG1 0x1b94 |
| #define MT6338_LDO_VAUD18_OP_CFG1_SET 0x1b95 |
| #define MT6338_LDO_VAUD18_OP_CFG1_CLR 0x1b96 |
| #define MT6338_LDO_VAUD18_MULTI_SW_0 0x1b97 |
| #define MT6338_LDO_VAUD18_MULTI_SW_1 0x1b98 |
| #define MT6338_LDO_ANA0_ANA_ID 0x1c00 |
| #define MT6338_LDO_ANA0_DIG_ID 0x1c01 |
| #define MT6338_LDO_ANA0_ANA_REV 0x1c02 |
| #define MT6338_LDO_ANA0_DIG_REV 0x1c03 |
| #define MT6338_LDO_ANA0_DBI 0x1c04 |
| #define MT6338_LDO_ANA0_ESP 0x1c05 |
| #define MT6338_LDO_ANA0_FPI 0x1c06 |
| #define MT6338_LDO_ANA0_DXI 0x1c07 |
| #define MT6338_VD105_PMU_CON0 0x1c08 |
| #define MT6338_VAUD18_PMU_CON0 0x1c09 |
| #define MT6338_VAUD18_PMU_CON1 0x1c0a |
| #define MT6338_VAUD18_PMU_CON2 0x1c0b |
| #define MT6338_VPLL18_PMU_CON0 0x1c0c |
| #define MT6338_VPLL18_PMU_CON1 0x1c0d |
| #define MT6338_VPLL18_PMU_CON2 0x1c0e |
| #define MT6338_LDO_ANA0_ELR_NUM 0x1c0f |
| #define MT6338_VD105_ELR_0 0x1c10 |
| #define MT6338_AUD_TOP_ID 0x2300 |
| #define MT6338_AUD_TOP_ID_H 0x2301 |
| #define MT6338_AUD_TOP_REV0 0x2302 |
| #define MT6338_AUD_TOP_REV0_H 0x2303 |
| #define MT6338_AUD_TOP_DBI 0x2304 |
| #define MT6338_AUD_TOP_DBI_H 0x2305 |
| #define MT6338_AUD_TOP_DXI 0x2306 |
| #define MT6338_AUD_TOP_CKPDN_TPM0 0x2307 |
| #define MT6338_AUD_TOP_CKPDN_TPM0_H 0x2308 |
| #define MT6338_AUD_TOP_CKPDN_TPM1 0x2309 |
| #define MT6338_AUD_TOP_CKPDN_TPM1_H 0x230a |
| #define MT6338_AUD_TOP_CKPDN_CON0 0x230b |
| #define MT6338_AUD_TOP_CKPDN_CON0_SET 0x230c |
| #define MT6338_AUD_TOP_CKPDN_CON0_CLR 0x230d |
| #define MT6338_AUD_TOP_CKPDN_CON0_H 0x230e |
| #define MT6338_AUD_TOP_CKPDN_CON0_H_SET 0x230f |
| #define MT6338_AUD_TOP_CKPDN_CON0_H_CLR 0x2310 |
| #define MT6338_AUD_TOP_CKSEL_CON0 0x2311 |
| #define MT6338_AUD_TOP_CKSEL_CON0_SET 0x2312 |
| #define MT6338_AUD_TOP_CKSEL_CON0_CLR 0x2313 |
| #define MT6338_AUD_TOP_CKTST_CON0 0x2314 |
| #define MT6338_AUD_TOP_CKTST_CON0_H 0x2315 |
| #define MT6338_AUD_TOP_CLK_HWEN_CON0 0x2316 |
| #define MT6338_AUD_TOP_CLK_HWEN_CON0_SET 0x2317 |
| #define MT6338_AUD_TOP_CLK_HWEN_CON0_CLR 0x2318 |
| #define MT6338_AUD_TOP_RST_CON0 0x2319 |
| #define MT6338_AUD_TOP_RST_CON0_SET 0x231a |
| #define MT6338_AUD_TOP_RST_CON0_CLR 0x231b |
| #define MT6338_AUD_TOP_RST_BANK_CON0 0x231c |
| #define MT6338_AUD_TOP_INT_CON0 0x231d |
| #define MT6338_AUD_TOP_INT_CON0_SET 0x231e |
| #define MT6338_AUD_TOP_INT_CON0_CLR 0x231f |
| #define MT6338_AUD_TOP_INT_MASK_CON0 0x2320 |
| #define MT6338_AUD_TOP_INT_MASK_CON0_SET 0x2321 |
| #define MT6338_AUD_TOP_INT_MASK_CON0_CLR 0x2322 |
| #define MT6338_AUD_TOP_INT_STATUS0 0x2323 |
| #define MT6338_AUD_TOP_INT_RAW_STATUS0 0x2324 |
| #define MT6338_AUD_TOP_INT_MISC_CON0 0x2325 |
| #define MT6338_AUD_TOP_MON_CON0 0x2326 |
| #define MT6338_AUD_TOP_MON_CON0_H 0x2327 |
| #define MT6338_AUDIO_DIG_CFG 0x2328 |
| #define MT6338_AUDIO_DIG_CFG_H 0x2329 |
| #define MT6338_AUDIO_DIG_CFG1 0x232a |
| #define MT6338_AFE_AUD_PAD_TOP 0x232b |
| #define MT6338_AFE_AUD_PAD_TOP_MON 0x232c |
| #define MT6338_AFE_AUD_PAD_TOP_MON_H 0x232d |
| #define MT6338_AFE_AUD_PAD_TOP_MON1 0x232e |
| #define MT6338_AFE_AUD_PAD_TOP_MON1_H 0x232f |
| #define MT6338_AFE_AUD_PAD_TOP_MON2 0x2330 |
| #define MT6338_AUD_TOP_SRAM_CON 0x2331 |
| #define MT6338_AFE_DCCLK1_CFG0 0x2332 |
| #define MT6338_AFE_DCCLK1_CFG1 0x2333 |
| #define MT6338_AFE_DCCLK1_CFG2 0x2334 |
| #define MT6338_AFE_DCCLK2_CFG0 0x2335 |
| #define MT6338_AFE_DCCLK2_CFG1 0x2336 |
| #define MT6338_AFE_DCCLK2_CFG2 0x2337 |
| #define MT6338_AFE_DCCLK3_CFG0 0x2338 |
| #define MT6338_AFE_DCCLK3_CFG1 0x2339 |
| #define MT6338_AFE_DCCLK3_CFG2 0x233a |
| #define MT6338_AFE_DCCLK4_CFG0 0x233b |
| #define MT6338_AFE_DCCLK4_CFG1 0x233c |
| #define MT6338_AFE_DCCLK4_CFG2 0x233d |
| #define MT6338_AO_AFUNC_AUD_CON3_L 0x233e |
| #define MT6338_AO_AFUNC_AUD_CON4_H 0x233f |
| #define MT6338_AO_AFUNC_AUD_CON4_L 0x2340 |
| #define MT6338_AO_AFUNC_AUD_CON7_H 0x2341 |
| #define MT6338_AO_AFUNC_AUD_CON7_L 0x2342 |
| #define MT6338_AO_AFE_DMIC_ARRAY_CFG 0x2343 |
| #define MT6338_AO_AFE_ADC_ASYNC_FIFO_CFG 0x2344 |
| #define MT6338_AO_AUDIO_TOP_CON0 0x2345 |
| #define MT6338_AUDIO_DIG_DSN_ID 0x2380 |
| #define MT6338_AUDIO_DIG_DSN_ID_H 0x2381 |
| #define MT6338_AUDIO_DIG_DSN_REV0 0x2382 |
| #define MT6338_AUDIO_DIG_DSN_REV0_H 0x2383 |
| #define MT6338_AUDIO_DIG_DSN_DBI 0x2384 |
| #define MT6338_AUDIO_DIG_DSN_DBI_H 0x2385 |
| #define MT6338_AUDIO_DIG_DSN_DXI 0x2386 |
| #define MT6338_AUDIO_TOP_CON0 0x2387 |
| #define MT6338_AUDIO_TOP_CON1 0x2388 |
| #define MT6338_AUDIO_TOP_CON2 0x2389 |
| #define MT6338_AUDIO_TOP_CON3 0x238a |
| #define MT6338_AFE_TOP_CON0 0x238b |
| #define MT6338_AFE_MON_DEBUG0 0x238c |
| #define MT6338_AFE_MON_DEBUG1 0x238d |
| #define MT6338_AFE_MTKAIF_MUX_CFG_H 0x238e |
| #define MT6338_AFE_MTKAIF_MUX_CFG 0x238f |
| #define MT6338_AFE_SINEGEN_CON0 0x2390 |
| #define MT6338_AFE_SINEGEN_CON1 0x2391 |
| #define MT6338_AFE_SINEGEN_CON2 0x2392 |
| #define MT6338_AFE_SINEGEN_CON3 0x2393 |
| #define MT6338_AFE_SINEGEN_CON4 0x2394 |
| #define MT6338_AFE_STF_CON0 0x2395 |
| #define MT6338_AFE_STF_CON0_M 0x2396 |
| #define MT6338_AFE_STF_CON0_H 0x2397 |
| #define MT6338_AFE_STF_CON1 0x2398 |
| #define MT6338_AFE_STF_COEFF 0x2399 |
| #define MT6338_AFE_STF_COEFF_M 0x239a |
| #define MT6338_AFE_STF_COEFF_H 0x239b |
| #define MT6338_AFE_STF_GAIN 0x239c |
| #define MT6338_AFE_STF_GAIN_M 0x239d |
| #define MT6338_AFE_STF_GAIN_H 0x239e |
| #define MT6338_AFE_STF_COEFF_RD 0x239f |
| #define MT6338_AFE_STF_MON 0x23a0 |
| #define MT6338_AFE_STF_MON_M 0x23a1 |
| #define MT6338_AFE_STF_MON_H 0x23a2 |
| #define MT6338_AFE_STF_MON_H1 0x23a3 |
| #define MT6338_AFE_NCP_CFG0 0x23a4 |
| #define MT6338_AFE_NCP_CFG1 0x23a5 |
| #define MT6338_AFE_NCP_CFG2 0x23a6 |
| #define MT6338_AFE_NCP_CFG3 0x23a7 |
| #define MT6338_AFE_NCP_CFG4 0x23a8 |
| #define MT6338_AFE_TOP_DEBUG0 0x23a9 |
| #define MT6338_AFE_MTKAIF_IN_MUX_CFG 0x23aa |
| #define MT6338_AUDIO_DIG_2ND_DSN_ID 0x2400 |
| #define MT6338_AUDIO_DIG_2ND_DSN_ID_H 0x2401 |
| #define MT6338_AUDIO_DIG_2ND_DSN_REV0 0x2402 |
| #define MT6338_AUDIO_DIG_2ND_DSN_REV0_H 0x2403 |
| #define MT6338_AUDIO_DIG_2ND_DSN_DBI 0x2404 |
| #define MT6338_AUDIO_DIG_2ND_DSN_DBI_H 0x2405 |
| #define MT6338_AUDIO_DIG_2ND_DSN_DXI 0x2406 |
| #define MT6338_GENERAL_ASRC_EN_ON 0x2407 |
| #define MT6338_GASRC1_MODE 0x2408 |
| #define MT6338_GASRC2_MODE 0x2409 |
| #define MT6338_GASRC3_MODE 0x240a |
| #define MT6338_GASRC4_MODE 0x240b |
| #define MT6338_AFE_GASRC1_CON0 0x240c |
| #define MT6338_AFE_GASRC1_CON1 0x240d |
| #define MT6338_AFE_GASRC1_CON2 0x240e |
| #define MT6338_AFE_GASRC1_CON2_M 0x240f |
| #define MT6338_AFE_GASRC1_CON2_H 0x2410 |
| #define MT6338_AFE_GASRC1_CON3 0x2411 |
| #define MT6338_AFE_GASRC1_CON3_M 0x2412 |
| #define MT6338_AFE_GASRC1_CON3_H 0x2413 |
| #define MT6338_AFE_GASRC1_CON4 0x2414 |
| #define MT6338_AFE_GASRC1_CON4_M 0x2415 |
| #define MT6338_AFE_GASRC1_CON4_H 0x2416 |
| #define MT6338_AFE_GASRC1_CON5 0x2417 |
| #define MT6338_AFE_GASRC1_CON5_M 0x2418 |
| #define MT6338_AFE_GASRC1_CON5_H0 0x2419 |
| #define MT6338_AFE_GASRC1_CON5_H1 0x241a |
| #define MT6338_AFE_GASRC1_CON6 0x241b |
| #define MT6338_AFE_GASRC1_CON6_M 0x241c |
| #define MT6338_AFE_GASRC1_CON6_H 0x241d |
| #define MT6338_AFE_GASRC1_CON7 0x241e |
| #define MT6338_AFE_GASRC1_CON7_M 0x241f |
| #define MT6338_AFE_GASRC1_CON7_H 0x2420 |
| #define MT6338_AFE_GASRC1_CON8 0x2421 |
| #define MT6338_AFE_GASRC1_CON8_M 0x2422 |
| #define MT6338_AFE_GASRC1_CON8_H 0x2423 |
| #define MT6338_AFE_GASRC1_CON9 0x2424 |
| #define MT6338_AFE_GASRC1_CON9_M 0x2425 |
| #define MT6338_AFE_GASRC1_CON9_H 0x2426 |
| #define MT6338_AFE_GASRC1_CON10 0x2427 |
| #define MT6338_AFE_GASRC1_CON10_M 0x2428 |
| #define MT6338_AFE_GASRC1_CON10_H 0x2429 |
| #define MT6338_AFE_GASRC1_CON11 0x242a |
| #define MT6338_AFE_GASRC1_CON11_H 0x242b |
| #define MT6338_AFE_GASRC1_CON12 0x242c |
| #define MT6338_AFE_GASRC1_CON12_M 0x242d |
| #define MT6338_AFE_GASRC1_CON12_H 0x242e |
| #define MT6338_AFE_GASRC1_CON13 0x242f |
| #define MT6338_AFE_GASRC1_CON14 0x2430 |
| #define MT6338_AFE_GASRC1_CON14_M 0x2431 |
| #define MT6338_AFE_GASRC1_CON14_H 0x2432 |
| #define MT6338_AFE_GASRC1_CON15 0x2433 |
| #define MT6338_AFE_GASRC2_CON0 0x2434 |
| #define MT6338_AFE_GASRC2_CON1 0x2435 |
| #define MT6338_AFE_GASRC2_CON2 0x2436 |
| #define MT6338_AFE_GASRC2_CON2_M 0x2437 |
| #define MT6338_AFE_GASRC2_CON2_H 0x2438 |
| #define MT6338_AFE_GASRC2_CON3 0x2439 |
| #define MT6338_AFE_GASRC2_CON3_M 0x243a |
| #define MT6338_AFE_GASRC2_CON3_H 0x243b |
| #define MT6338_AFE_GASRC2_CON4 0x243c |
| #define MT6338_AFE_GASRC2_CON4_M 0x243d |
| #define MT6338_AFE_GASRC2_CON4_H 0x243e |
| #define MT6338_AFE_GASRC2_CON5 0x243f |
| #define MT6338_AFE_GASRC2_CON5_M 0x2440 |
| #define MT6338_AFE_GASRC2_CON5_H0 0x2441 |
| #define MT6338_AFE_GASRC2_CON5_H1 0x2442 |
| #define MT6338_AFE_GASRC2_CON6 0x2443 |
| #define MT6338_AFE_GASRC2_CON6_M 0x2444 |
| #define MT6338_AFE_GASRC2_CON6_H 0x2445 |
| #define MT6338_AFE_GASRC2_CON7 0x2446 |
| #define MT6338_AFE_GASRC2_CON7_M 0x2447 |
| #define MT6338_AFE_GASRC2_CON7_H 0x2448 |
| #define MT6338_AFE_GASRC2_CON8 0x2449 |
| #define MT6338_AFE_GASRC2_CON8_M 0x244a |
| #define MT6338_AFE_GASRC2_CON8_H 0x244b |
| #define MT6338_AFE_GASRC2_CON9 0x244c |
| #define MT6338_AFE_GASRC2_CON9_M 0x244d |
| #define MT6338_AFE_GASRC2_CON9_H 0x244e |
| #define MT6338_AFE_GASRC2_CON10 0x244f |
| #define MT6338_AFE_GASRC2_CON10_M 0x2450 |
| #define MT6338_AFE_GASRC2_CON10_H 0x2451 |
| #define MT6338_AFE_GASRC2_CON11 0x2452 |
| #define MT6338_AFE_GASRC2_CON11_H 0x2453 |
| #define MT6338_AFE_GASRC2_CON12 0x2454 |
| #define MT6338_AFE_GASRC2_CON12_M 0x2455 |
| #define MT6338_AFE_GASRC2_CON12_H 0x2456 |
| #define MT6338_AFE_GASRC2_CON13 0x2457 |
| #define MT6338_AFE_GASRC2_CON14 0x2458 |
| #define MT6338_AFE_GASRC2_CON14_M 0x2459 |
| #define MT6338_AFE_GASRC2_CON14_H 0x245a |
| #define MT6338_AFE_GASRC2_CON15 0x245b |
| #define MT6338_AFE_GASRC_CK_SEL 0x245c |
| #define MT6338_AUDIO_DIG_3RD_DSN_ID 0x2480 |
| #define MT6338_AUDIO_DIG_3RD_DSN_ID_H 0x2481 |
| #define MT6338_AUDIO_DIG_3RD_DSN_REV0 0x2482 |
| #define MT6338_AUDIO_DIG_3RD_DSN_REV0_H 0x2483 |
| #define MT6338_AUDIO_DIG_3RD_DSN_DBI 0x2484 |
| #define MT6338_AUDIO_DIG_3RD_DSN_DBI_H 0x2485 |
| #define MT6338_AUDIO_DIG_3RD_DSN_DXI 0x2486 |
| #define MT6338_AFE_GASRC3_CON0 0x2487 |
| #define MT6338_AFE_GASRC3_CON1 0x2488 |
| #define MT6338_AFE_GASRC3_CON2 0x2489 |
| #define MT6338_AFE_GASRC3_CON2_M 0x248a |
| #define MT6338_AFE_GASRC3_CON2_H 0x248b |
| #define MT6338_AFE_GASRC3_CON3 0x248c |
| #define MT6338_AFE_GASRC3_CON3_M 0x248d |
| #define MT6338_AFE_GASRC3_CON3_H 0x248e |
| #define MT6338_AFE_GASRC3_CON4 0x248f |
| #define MT6338_AFE_GASRC3_CON4_M 0x2490 |
| #define MT6338_AFE_GASRC3_CON4_H 0x2491 |
| #define MT6338_AFE_GASRC3_CON5 0x2492 |
| #define MT6338_AFE_GASRC3_CON5_M 0x2493 |
| #define MT6338_AFE_GASRC3_CON5_H0 0x2494 |
| #define MT6338_AFE_GASRC3_CON5_H1 0x2495 |
| #define MT6338_AFE_GASRC3_CON6 0x2496 |
| #define MT6338_AFE_GASRC3_CON6_M 0x2497 |
| #define MT6338_AFE_GASRC3_CON6_H 0x2498 |
| #define MT6338_AFE_GASRC3_CON7 0x2499 |
| #define MT6338_AFE_GASRC3_CON7_M 0x249a |
| #define MT6338_AFE_GASRC3_CON7_H 0x249b |
| #define MT6338_AFE_GASRC3_CON8 0x249c |
| #define MT6338_AFE_GASRC3_CON8_M 0x249d |
| #define MT6338_AFE_GASRC3_CON8_H 0x249e |
| #define MT6338_AFE_GASRC3_CON9 0x249f |
| #define MT6338_AFE_GASRC3_CON9_M 0x24a0 |
| #define MT6338_AFE_GASRC3_CON9_H 0x24a1 |
| #define MT6338_AFE_GASRC3_CON10 0x24a2 |
| #define MT6338_AFE_GASRC3_CON10_M 0x24a3 |
| #define MT6338_AFE_GASRC3_CON10_H 0x24a4 |
| #define MT6338_AFE_GASRC3_CON11 0x24a5 |
| #define MT6338_AFE_GASRC3_CON11_H 0x24a6 |
| #define MT6338_AFE_GASRC3_CON12 0x24a7 |
| #define MT6338_AFE_GASRC3_CON12_M 0x24a8 |
| #define MT6338_AFE_GASRC3_CON12_H 0x24a9 |
| #define MT6338_AFE_GASRC3_CON13 0x24aa |
| #define MT6338_AFE_GASRC3_CON14 0x24ab |
| #define MT6338_AFE_GASRC3_CON14_M 0x24ac |
| #define MT6338_AFE_GASRC3_CON14_H 0x24ad |
| #define MT6338_AFE_GASRC3_CON15 0x24ae |
| #define MT6338_AFE_GASRC4_CON0 0x24af |
| #define MT6338_AFE_GASRC4_CON1 0x24b0 |
| #define MT6338_AFE_GASRC4_CON2 0x24b1 |
| #define MT6338_AFE_GASRC4_CON2_M 0x24b2 |
| #define MT6338_AFE_GASRC4_CON2_H 0x24b3 |
| #define MT6338_AFE_GASRC4_CON3 0x24b4 |
| #define MT6338_AFE_GASRC4_CON3_M 0x24b5 |
| #define MT6338_AFE_GASRC4_CON3_H 0x24b6 |
| #define MT6338_AFE_GASRC4_CON4 0x24b7 |
| #define MT6338_AFE_GASRC4_CON4_M 0x24b8 |
| #define MT6338_AFE_GASRC4_CON4_H 0x24b9 |
| #define MT6338_AFE_GASRC4_CON5 0x24ba |
| #define MT6338_AFE_GASRC4_CON5_M 0x24bb |
| #define MT6338_AFE_GASRC4_CON5_H0 0x24bc |
| #define MT6338_AFE_GASRC4_CON5_H1 0x24bd |
| #define MT6338_AFE_GASRC4_CON6 0x24be |
| #define MT6338_AFE_GASRC4_CON6_M 0x24bf |
| #define MT6338_AFE_GASRC4_CON6_H 0x24c0 |
| #define MT6338_AFE_GASRC4_CON7 0x24c1 |
| #define MT6338_AFE_GASRC4_CON7_M 0x24c2 |
| #define MT6338_AFE_GASRC4_CON7_H 0x24c3 |
| #define MT6338_AFE_GASRC4_CON8 0x24c4 |
| #define MT6338_AFE_GASRC4_CON8_M 0x24c5 |
| #define MT6338_AFE_GASRC4_CON8_H 0x24c6 |
| #define MT6338_AFE_GASRC4_CON9 0x24c7 |
| #define MT6338_AFE_GASRC4_CON9_M 0x24c8 |
| #define MT6338_AFE_GASRC4_CON9_H 0x24c9 |
| #define MT6338_AFE_GASRC4_CON10 0x24ca |
| #define MT6338_AFE_GASRC4_CON10_M 0x24cb |
| #define MT6338_AFE_GASRC4_CON10_H 0x24cc |
| #define MT6338_AFE_GASRC4_CON11 0x24cd |
| #define MT6338_AFE_GASRC4_CON11_H 0x24ce |
| #define MT6338_AFE_GASRC4_CON12 0x24cf |
| #define MT6338_AFE_GASRC4_CON12_M 0x24d0 |
| #define MT6338_AFE_GASRC4_CON12_H 0x24d1 |
| #define MT6338_AFE_GASRC4_CON13 0x24d2 |
| #define MT6338_AFE_GASRC4_CON14 0x24d3 |
| #define MT6338_AFE_GASRC4_CON14_M 0x24d4 |
| #define MT6338_AFE_GASRC4_CON14_H 0x24d5 |
| #define MT6338_AFE_GASRC4_CON15 0x24d6 |
| #define MT6338_AUDIO_DIG_4TH_DSN_ID 0x2500 |
| #define MT6338_AUDIO_DIG_4TH_DSN_ID_H 0x2501 |
| #define MT6338_AUDIO_DIG_4TH_DSN_REV0 0x2502 |
| #define MT6338_AUDIO_DIG_4TH_DSN_REV0_H 0x2503 |
| #define MT6338_AUDIO_DIG_4TH_DSN_DBI 0x2504 |
| #define MT6338_AUDIO_DIG_4TH_DSN_DBI_H 0x2505 |
| #define MT6338_AUDIO_DIG_4TH_DSN_DXI 0x2506 |
| #define MT6338_AFE_ADDA_UL_DL_CON0_2 0x2507 |
| #define MT6338_AFE_ADDA_UL_DL_CON0_1 0x2508 |
| #define MT6338_AFE_ADDA_UL_DL_CON0_0 0x2509 |
| #define MT6338_AFE_ADDA_UL_SRC_CON0_3 0x250a |
| #define MT6338_AFE_ADDA_UL_SRC_CON0_2 0x250b |
| #define MT6338_AFE_ADDA_UL_SRC_CON0_1 0x250c |
| #define MT6338_AFE_ADDA_UL_SRC_CON0_0 0x250d |
| #define MT6338_AFE_ADDA_UL_SRC_CON1_3 0x250e |
| #define MT6338_AFE_ADDA_UL_SRC_CON1_2 0x250f |
| #define MT6338_AFE_ADDA_UL_SRC_CON1_1 0x2510 |
| #define MT6338_AFE_ADDA_UL_SRC_CON1_0 0x2511 |
| #define MT6338_AFE_ADDA_UL_SRC_CON2_3 0x2512 |
| #define MT6338_AFE_ADDA_UL_SRC_CON2_2 0x2513 |
| #define MT6338_AFE_ADDA_UL_SRC_CON2_1 0x2514 |
| #define MT6338_AFE_ADDA_UL_SRC_CON2_0 0x2515 |
| #define MT6338_AFE_ADDA_IIR_COEF_02_01_3 0x2516 |
| #define MT6338_AFE_ADDA_IIR_COEF_02_01_2 0x2517 |
| #define MT6338_AFE_ADDA_IIR_COEF_02_01_1 0x2518 |
| #define MT6338_AFE_ADDA_IIR_COEF_02_01_0 0x2519 |
| #define MT6338_AFE_ADDA_IIR_COEF_04_03_3 0x251a |
| #define MT6338_AFE_ADDA_IIR_COEF_04_03_2 0x251b |
| #define MT6338_AFE_ADDA_IIR_COEF_04_03_1 0x251c |
| #define MT6338_AFE_ADDA_IIR_COEF_04_03_0 0x251d |
| #define MT6338_AFE_ADDA_IIR_COEF_06_05_3 0x251e |
| #define MT6338_AFE_ADDA_IIR_COEF_06_05_2 0x251f |
| #define MT6338_AFE_ADDA_IIR_COEF_06_05_1 0x2520 |
| #define MT6338_AFE_ADDA_IIR_COEF_06_05_0 0x2521 |
| #define MT6338_AFE_ADDA_IIR_COEF_08_07_3 0x2522 |
| #define MT6338_AFE_ADDA_IIR_COEF_08_07_2 0x2523 |
| #define MT6338_AFE_ADDA_IIR_COEF_08_07_1 0x2524 |
| #define MT6338_AFE_ADDA_IIR_COEF_08_07_0 0x2525 |
| #define MT6338_AFE_ADDA_IIR_COEF_10_09_3 0x2526 |
| #define MT6338_AFE_ADDA_IIR_COEF_10_09_2 0x2527 |
| #define MT6338_AFE_ADDA_IIR_COEF_10_09_1 0x2528 |
| #define MT6338_AFE_ADDA_IIR_COEF_10_09_0 0x2529 |
| #define MT6338_AFE_ADDA_ULCF_CFG_02_01_3 0x252a |
| #define MT6338_AFE_ADDA_ULCF_CFG_02_01_2 0x252b |
| #define MT6338_AFE_ADDA_ULCF_CFG_02_01_1 0x252c |
| #define MT6338_AFE_ADDA_ULCF_CFG_02_01_0 0x252d |
| #define MT6338_AFE_ADDA_ULCF_CFG_04_03_3 0x252e |
| #define MT6338_AFE_ADDA_ULCF_CFG_04_03_2 0x252f |
| #define MT6338_AFE_ADDA_ULCF_CFG_04_03_1 0x2530 |
| #define MT6338_AFE_ADDA_ULCF_CFG_04_03_0 0x2531 |
| #define MT6338_AFE_ADDA_ULCF_CFG_06_05_3 0x2532 |
| #define MT6338_AFE_ADDA_ULCF_CFG_06_05_2 0x2533 |
| #define MT6338_AFE_ADDA_ULCF_CFG_06_05_1 0x2534 |
| #define MT6338_AFE_ADDA_ULCF_CFG_06_05_0 0x2535 |
| #define MT6338_AFE_ADDA_ULCF_CFG_08_07_3 0x2536 |
| #define MT6338_AFE_ADDA_ULCF_CFG_08_07_2 0x2537 |
| #define MT6338_AFE_ADDA_ULCF_CFG_08_07_1 0x2538 |
| #define MT6338_AFE_ADDA_ULCF_CFG_08_07_0 0x2539 |
| #define MT6338_AFE_ADDA_ULCF_CFG_10_09_3 0x253a |
| #define MT6338_AFE_ADDA_ULCF_CFG_10_09_2 0x253b |
| #define MT6338_AFE_ADDA_ULCF_CFG_10_09_1 0x253c |
| #define MT6338_AFE_ADDA_ULCF_CFG_10_09_0 0x253d |
| #define MT6338_AFE_ADDA_ULCF_CFG_12_11_3 0x253e |
| #define MT6338_AFE_ADDA_ULCF_CFG_12_11_2 0x253f |
| #define MT6338_AFE_ADDA_ULCF_CFG_12_11_1 0x2540 |
| #define MT6338_AFE_ADDA_ULCF_CFG_12_11_0 0x2541 |
| #define MT6338_AFE_ADDA_ULCF_CFG_14_13_3 0x2542 |
| #define MT6338_AFE_ADDA_ULCF_CFG_14_13_2 0x2543 |
| #define MT6338_AFE_ADDA_ULCF_CFG_14_13_1 0x2544 |
| #define MT6338_AFE_ADDA_ULCF_CFG_14_13_0 0x2545 |
| #define MT6338_AFE_ADDA_ULCF_CFG_16_15_3 0x2546 |
| #define MT6338_AFE_ADDA_ULCF_CFG_16_15_2 0x2547 |
| #define MT6338_AFE_ADDA_ULCF_CFG_16_15_1 0x2548 |
| #define MT6338_AFE_ADDA_ULCF_CFG_16_15_0 0x2549 |
| #define MT6338_AFE_ADDA_ULCF_CFG_18_17_3 0x254a |
| #define MT6338_AFE_ADDA_ULCF_CFG_18_17_2 0x254b |
| #define MT6338_AFE_ADDA_ULCF_CFG_18_17_1 0x254c |
| #define MT6338_AFE_ADDA_ULCF_CFG_18_17_0 0x254d |
| #define MT6338_AFE_ADDA_ULCF_CFG_20_19_3 0x254e |
| #define MT6338_AFE_ADDA_ULCF_CFG_20_19_2 0x254f |
| #define MT6338_AFE_ADDA_ULCF_CFG_20_19_1 0x2550 |
| #define MT6338_AFE_ADDA_ULCF_CFG_20_19_0 0x2551 |
| #define MT6338_AFE_ADDA_ULCF_CFG_22_21_3 0x2552 |
| #define MT6338_AFE_ADDA_ULCF_CFG_22_21_2 0x2553 |
| #define MT6338_AFE_ADDA_ULCF_CFG_22_21_1 0x2554 |
| #define MT6338_AFE_ADDA_ULCF_CFG_22_21_0 0x2555 |
| #define MT6338_AFE_ADDA_ULCF_CFG_24_23_3 0x2556 |
| #define MT6338_AFE_ADDA_ULCF_CFG_24_23_2 0x2557 |
| #define MT6338_AFE_ADDA_ULCF_CFG_24_23_1 0x2558 |
| #define MT6338_AFE_ADDA_ULCF_CFG_24_23_0 0x2559 |
| #define MT6338_AFE_ADDA_ULCF_CFG_26_25_3 0x255a |
| #define MT6338_AFE_ADDA_ULCF_CFG_26_25_2 0x255b |
| #define MT6338_AFE_ADDA_ULCF_CFG_26_25_1 0x255c |
| #define MT6338_AFE_ADDA_ULCF_CFG_26_25_0 0x255d |
| #define MT6338_AFE_ADDA_ULCF_CFG_28_27_3 0x255e |
| #define MT6338_AFE_ADDA_ULCF_CFG_28_27_2 0x255f |
| #define MT6338_AFE_ADDA_ULCF_CFG_28_27_1 0x2560 |
| #define MT6338_AFE_ADDA_ULCF_CFG_28_27_0 0x2561 |
| #define MT6338_AFE_ADDA_ULCF_CFG_30_29_3 0x2562 |
| #define MT6338_AFE_ADDA_ULCF_CFG_30_29_2 0x2563 |
| #define MT6338_AFE_ADDA_ULCF_CFG_30_29_1 0x2564 |
| #define MT6338_AFE_ADDA_ULCF_CFG_30_29_0 0x2565 |
| #define MT6338_AFE_ADDA_ULCF_CFG_32_31_3 0x2566 |
| #define MT6338_AFE_ADDA_ULCF_CFG_32_31_2 0x2567 |
| #define MT6338_AFE_ADDA_ULCF_CFG_32_31_1 0x2568 |
| #define MT6338_AFE_ADDA_ULCF_CFG_32_31_0 0x2569 |
| #define MT6338_AFE_ADDA_UL_SRC_MON0_3 0x256a |
| #define MT6338_AFE_ADDA_UL_SRC_MON0_2 0x256b |
| #define MT6338_AFE_ADDA_UL_SRC_MON0_1 0x256c |
| #define MT6338_AFE_ADDA_UL_SRC_MON0_0 0x256d |
| #define MT6338_AFE_ADDA_UL_SRC_MON1_3 0x256e |
| #define MT6338_AFE_ADDA_UL_SRC_MON1_2 0x256f |
| #define MT6338_AFE_ADDA_UL_SRC_MON1_1 0x2570 |
| #define MT6338_AFE_ADDA_UL_SRC_MON1_0 0x2571 |
| #define MT6338_AFE_ADDA_SRC_DEBUG_1 0x2572 |
| #define MT6338_AFE_ADDA_SRC_DEBUG_0 0x2573 |
| #define MT6338_AFE_ADDA_SRC_DEBUG_MON0_1 0x2574 |
| #define MT6338_AFE_ADDA_SRC_DEBUG_MON0_0 0x2575 |
| #define MT6338_AFE_ADDA6_UL_SRC_CON0_3 0x2576 |
| #define MT6338_AFE_ADDA6_UL_SRC_CON0_2 0x2577 |
| #define MT6338_AFE_ADDA6_UL_SRC_CON0_1 0x2578 |
| #define MT6338_AFE_ADDA6_UL_SRC_CON0_0 0x2579 |
| #define MT6338_AFE_ADDA6_UL_SRC_CON1_3 0x257a |
| #define MT6338_AFE_ADDA6_UL_SRC_CON1_2 0x257b |
| #define MT6338_AFE_ADDA6_UL_SRC_CON1_1 0x257c |
| #define MT6338_AFE_ADDA6_UL_SRC_CON1_0 0x257d |
| #define MT6338_AUDIO_DIG_5TH_DSN_ID 0x2580 |
| #define MT6338_AUDIO_DIG_5TH_DSN_ID_H 0x2581 |
| #define MT6338_AUDIO_DIG_5TH_DSN_REV0 0x2582 |
| #define MT6338_AUDIO_DIG_5TH_DSN_REV0_H 0x2583 |
| #define MT6338_AUDIO_DIG_5TH_DSN_DBI 0x2584 |
| #define MT6338_AUDIO_DIG_5TH_DSN_DBI_H 0x2585 |
| #define MT6338_AUDIO_DIG_5TH_DSN_DXI 0x2586 |
| #define MT6338_AFE_ADDA6_UL_SRC_CON2_3 0x2587 |
| #define MT6338_AFE_ADDA6_UL_SRC_CON2_2 0x2588 |
| #define MT6338_AFE_ADDA6_UL_SRC_CON2_1 0x2589 |
| #define MT6338_AFE_ADDA6_UL_SRC_CON2_0 0x258a |
| #define MT6338_AFE_ADDA6_IIR_COEF_02_01_3 0x258b |
| #define MT6338_AFE_ADDA6_IIR_COEF_02_01_2 0x258c |
| #define MT6338_AFE_ADDA6_IIR_COEF_02_01_1 0x258d |
| #define MT6338_AFE_ADDA6_IIR_COEF_02_01_0 0x258e |
| #define MT6338_AFE_ADDA6_IIR_COEF_04_03_3 0x258f |
| #define MT6338_AFE_ADDA6_IIR_COEF_04_03_2 0x2590 |
| #define MT6338_AFE_ADDA6_IIR_COEF_04_03_1 0x2591 |
| #define MT6338_AFE_ADDA6_IIR_COEF_04_03_0 0x2592 |
| #define MT6338_AFE_ADDA6_IIR_COEF_06_05_3 0x2593 |
| #define MT6338_AFE_ADDA6_IIR_COEF_06_05_2 0x2594 |
| #define MT6338_AFE_ADDA6_IIR_COEF_06_05_1 0x2595 |
| #define MT6338_AFE_ADDA6_IIR_COEF_06_05_0 0x2596 |
| #define MT6338_AFE_ADDA6_IIR_COEF_08_07_3 0x2597 |
| #define MT6338_AFE_ADDA6_IIR_COEF_08_07_2 0x2598 |
| #define MT6338_AFE_ADDA6_IIR_COEF_08_07_1 0x2599 |
| #define MT6338_AFE_ADDA6_IIR_COEF_08_07_0 0x259a |
| #define MT6338_AFE_ADDA6_IIR_COEF_10_09_3 0x259b |
| #define MT6338_AFE_ADDA6_IIR_COEF_10_09_2 0x259c |
| #define MT6338_AFE_ADDA6_IIR_COEF_10_09_1 0x259d |
| #define MT6338_AFE_ADDA6_IIR_COEF_10_09_0 0x259e |
| #define MT6338_AFE_ADDA6_ULCF_CFG_02_01_3 0x259f |
| #define MT6338_AFE_ADDA6_ULCF_CFG_02_01_2 0x25a0 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_02_01_1 0x25a1 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_02_01_0 0x25a2 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_04_03_3 0x25a3 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_04_03_2 0x25a4 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_04_03_1 0x25a5 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_04_03_0 0x25a6 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_06_05_3 0x25a7 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_06_05_2 0x25a8 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_06_05_1 0x25a9 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_06_05_0 0x25aa |
| #define MT6338_AFE_ADDA6_ULCF_CFG_08_07_3 0x25ab |
| #define MT6338_AFE_ADDA6_ULCF_CFG_08_07_2 0x25ac |
| #define MT6338_AFE_ADDA6_ULCF_CFG_08_07_1 0x25ad |
| #define MT6338_AFE_ADDA6_ULCF_CFG_08_07_0 0x25ae |
| #define MT6338_AFE_ADDA6_ULCF_CFG_10_09_3 0x25af |
| #define MT6338_AFE_ADDA6_ULCF_CFG_10_09_2 0x25b0 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_10_09_1 0x25b1 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_10_09_0 0x25b2 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_12_11_3 0x25b3 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_12_11_2 0x25b4 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_12_11_1 0x25b5 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_12_11_0 0x25b6 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_14_13_3 0x25b7 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_14_13_2 0x25b8 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_14_13_1 0x25b9 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_14_13_0 0x25ba |
| #define MT6338_AFE_ADDA6_ULCF_CFG_16_15_3 0x25bb |
| #define MT6338_AFE_ADDA6_ULCF_CFG_16_15_2 0x25bc |
| #define MT6338_AFE_ADDA6_ULCF_CFG_16_15_1 0x25bd |
| #define MT6338_AFE_ADDA6_ULCF_CFG_16_15_0 0x25be |
| #define MT6338_AFE_ADDA6_ULCF_CFG_18_17_3 0x25bf |
| #define MT6338_AFE_ADDA6_ULCF_CFG_18_17_2 0x25c0 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_18_17_1 0x25c1 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_18_17_0 0x25c2 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_20_19_3 0x25c3 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_20_19_2 0x25c4 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_20_19_1 0x25c5 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_20_19_0 0x25c6 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_22_21_3 0x25c7 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_22_21_2 0x25c8 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_22_21_1 0x25c9 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_22_21_0 0x25ca |
| #define MT6338_AFE_ADDA6_ULCF_CFG_24_23_3 0x25cb |
| #define MT6338_AFE_ADDA6_ULCF_CFG_24_23_2 0x25cc |
| #define MT6338_AFE_ADDA6_ULCF_CFG_24_23_1 0x25cd |
| #define MT6338_AFE_ADDA6_ULCF_CFG_24_23_0 0x25ce |
| #define MT6338_AFE_ADDA6_ULCF_CFG_26_25_3 0x25cf |
| #define MT6338_AFE_ADDA6_ULCF_CFG_26_25_2 0x25d0 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_26_25_1 0x25d1 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_26_25_0 0x25d2 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_28_27_3 0x25d3 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_28_27_2 0x25d4 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_28_27_1 0x25d5 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_28_27_0 0x25d6 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_30_29_3 0x25d7 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_30_29_2 0x25d8 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_30_29_1 0x25d9 |
| #define MT6338_AFE_ADDA6_ULCF_CFG_30_29_0 0x25da |
| #define MT6338_AFE_ADDA6_ULCF_CFG_32_31_3 0x25db |
| #define MT6338_AFE_ADDA6_ULCF_CFG_32_31_2 0x25dc |
| #define MT6338_AFE_ADDA6_ULCF_CFG_32_31_1 0x25dd |
| #define MT6338_AFE_ADDA6_ULCF_CFG_32_31_0 0x25de |
| #define MT6338_AFE_ADDA6_UL_SRC_MON0_3 0x25df |
| #define MT6338_AFE_ADDA6_UL_SRC_MON0_2 0x25e0 |
| #define MT6338_AFE_ADDA6_UL_SRC_MON0_1 0x25e1 |
| #define MT6338_AFE_ADDA6_UL_SRC_MON0_0 0x25e2 |
| #define MT6338_AFE_ADDA6_UL_SRC_MON1_3 0x25e3 |
| #define MT6338_AFE_ADDA6_UL_SRC_MON1_2 0x25e4 |
| #define MT6338_AFE_ADDA6_UL_SRC_MON1_1 0x25e5 |
| #define MT6338_AFE_ADDA6_UL_SRC_MON1_0 0x25e6 |
| #define MT6338_AFE_ADDA6_SRC_DEBUG_1 0x25e7 |
| #define MT6338_AFE_ADDA6_SRC_DEBUG_0 0x25e8 |
| #define MT6338_AFE_ADDA6_SRC_DEBUG_MON0_1 0x25e9 |
| #define MT6338_AFE_ADDA6_SRC_DEBUG_MON0_0 0x25ea |
| #define MT6338_AUDIO_DIG_6TH_DSN_ID 0x2600 |
| #define MT6338_AUDIO_DIG_6TH_DSN_ID_H 0x2601 |
| #define MT6338_AUDIO_DIG_6TH_DSN_REV0 0x2602 |
| #define MT6338_AUDIO_DIG_6TH_DSN_REV0_H 0x2603 |
| #define MT6338_AUDIO_DIG_6TH_DSN_DBI 0x2604 |
| #define MT6338_AUDIO_DIG_6TH_DSN_DBI_H 0x2605 |
| #define MT6338_AUDIO_DIG_6TH_DSN_DXI 0x2606 |
| #define MT6338_AFE_DL_NLE_CF_H 0x2607 |
| #define MT6338_AFE_DL_NLE_CFG_L 0x2608 |
| #define MT6338_AFE_DL_NLE_MON_H 0x2609 |
| #define MT6338_AFE_DL_NLE_MON_L 0x260a |
| #define MT6338_AFUNC_AUD_CON0_H 0x260b |
| #define MT6338_AFUNC_AUD_CON0_L 0x260c |
| #define MT6338_AFUNC_AUD_CON1_H 0x260d |
| #define MT6338_AFUNC_AUD_CON1_L 0x260e |
| #define MT6338_AFUNC_AUD_CON2_H 0x260f |
| #define MT6338_AFUNC_AUD_CON2_L 0x2610 |
| #define MT6338_AFUNC_AUD_CON3_H 0x2611 |
| #define MT6338_AFUNC_AUD_CON4_H 0x2612 |
| #define MT6338_AFUNC_AUD_CON4_L 0x2613 |
| #define MT6338_AFUNC_AUD_CON5_H 0x2614 |
| #define MT6338_AFUNC_AUD_CON5_L 0x2615 |
| #define MT6338_AFUNC_AUD_CON6_H 0x2616 |
| #define MT6338_AFUNC_AUD_CON6_L 0x2617 |
| #define MT6338_AFUNC_AUD_CON7_H 0x2618 |
| #define MT6338_AFUNC_AUD_CON7_L 0x2619 |
| #define MT6338_AFUNC_AUD_CON8_H 0x261a |
| #define MT6338_AFUNC_AUD_CON8_L 0x261b |
| #define MT6338_AFUNC_AUD_CON9_H 0x261c |
| #define MT6338_AFUNC_AUD_CON9_L 0x261d |
| #define MT6338_AFUNC_AUD_CON10_H 0x261e |
| #define MT6338_AFUNC_AUD_CON10_L 0x261f |
| #define MT6338_AFUNC_AUD_CON11_H 0x2620 |
| #define MT6338_AFUNC_AUD_CON11_L 0x2621 |
| #define MT6338_AFUNC_AUD_CON12_H 0x2622 |
| #define MT6338_AFUNC_AUD_CON12_L 0x2623 |
| #define MT6338_AFUNC_AUD_MON0_H 0x2624 |
| #define MT6338_AFUNC_AUD_MON0_L 0x2625 |
| #define MT6338_AFUNC_AUD_MON1_H 0x2626 |
| #define MT6338_AFUNC_AUD_MON1_L 0x2627 |
| #define MT6338_AFE_ADC_ASYNC_FIFO_CFG 0x2628 |
| #define MT6338_AFE_AMIC_ARRAY_CFG 0x2629 |
| #define MT6338_AFUNC_AUD_CON13 0x262a |
| #define MT6338_AFUNC_AUD_CON14 0x262b |
| #define MT6338_AFUNC_AUD_CON15_H 0x262c |
| #define MT6338_AFUNC_AUD_CON15_L 0x262d |
| #define MT6338_AFUNC_AUD_CON16_H 0x262e |
| #define MT6338_AFUNC_AUD_CON16_L 0x262f |
| #define MT6338_AFUNC_AUD_CON17_H 0x2630 |
| #define MT6338_AFUNC_AUD_CON17_L 0x2631 |
| #define MT6338_AFUNC_AUD_CON18_H 0x2632 |
| #define MT6338_AFUNC_AUD_CON18_L 0x2633 |
| #define MT6338_AUDIO_DIG_7TH_DSN_ID 0x2680 |
| #define MT6338_AUDIO_DIG_7TH_DSN_ID_H 0x2681 |
| #define MT6338_AUDIO_DIG_7TH_DSN_REV0 0x2682 |
| #define MT6338_AUDIO_DIG_7TH_DSN_REV0_H 0x2683 |
| #define MT6338_AUDIO_DIG_7TH_DSN_DBI 0x2684 |
| #define MT6338_AUDIO_DIG_7TH_DSN_DBI_H 0x2685 |
| #define MT6338_AUDIO_DIG_7TH_DSN_DXI 0x2686 |
| #define MT6338_AFE_ADDA_DL_SRC_CON0_H 0x2687 |
| #define MT6338_AFE_ADDA_DL_SRC_CON0_M 0x2688 |
| #define MT6338_AFE_ADDA_DL_SRC_CON0_L 0x2689 |
| #define MT6338_AFE_ADDA_DL_SRC_CON0 0x268a |
| #define MT6338_AFE_ADDA_DL_SRC_CON1_H 0x268b |
| #define MT6338_AFE_ADDA_DL_SRC_CON1_M 0x268c |
| #define MT6338_AFE_ADDA_DL_SRC_CON1 0x268d |
| #define MT6338_AFE_ADDA_DL_SRC_DEBUG_MON0_H 0x268e |
| #define MT6338_AFE_ADDA_DL_SRC_DEBUG_MON0 0x268f |
| #define MT6338_AFE_ADDA_DL_PREDIS_CON0_H 0x2690 |
| #define MT6338_AFE_ADDA_DL_PREDIS_CON0_M 0x2691 |
| #define MT6338_AFE_ADDA_DL_PREDIS_CON0_L 0x2692 |
| #define MT6338_AFE_ADDA_DL_PREDIS_CON0 0x2693 |
| #define MT6338_AFE_ADDA_DL_PREDIS_CON1_H 0x2694 |
| #define MT6338_AFE_ADDA_DL_PREDIS_CON1_M 0x2695 |
| #define MT6338_AFE_ADDA_DL_PREDIS_CON1_L 0x2696 |
| #define MT6338_AFE_ADDA_DL_PREDIS_CON1 0x2697 |
| #define MT6338_AFE_ADDA_DL_PREDIS_CON2_H 0x2698 |
| #define MT6338_AFE_ADDA_DL_PREDIS_CON2_M 0x2699 |
| #define MT6338_AFE_ADDA_DL_PREDIS_CON2_L 0x269a |
| #define MT6338_AFE_ADDA_DL_PREDIS_CON2 0x269b |
| #define MT6338_AFE_ADDA_DL_PREDIS_CON3_H 0x269c |
| #define MT6338_AFE_ADDA_DL_PREDIS_CON3_M 0x269d |
| #define MT6338_AFE_ADDA_DL_PREDIS_CON3_L 0x269e |
| #define MT6338_AFE_ADDA_DL_PREDIS_CON3 0x269f |
| #define MT6338_AFE_ADDA_DL_SDM_DCCOMP_CON_H 0x26a0 |
| #define MT6338_AFE_ADDA_DL_SDM_DCCOMP_CON_L 0x26a1 |
| #define MT6338_AFE_ADDA_DL_SDM_DCCOMP_CON 0x26a2 |
| #define MT6338_AFE_ADDA_DL_SDM_TEST_L 0x26a3 |
| #define MT6338_AFE_ADDA_DL_SDM_TEST 0x26a4 |
| #define MT6338_AFE_ADDA_DL_DC_COMP_CFG0_H 0x26a5 |
| #define MT6338_AFE_ADDA_DL_DC_COMP_CFG0_M 0x26a6 |
| #define MT6338_AFE_ADDA_DL_DC_COMP_CFG0_L 0x26a7 |
| #define MT6338_AFE_ADDA_DL_DC_COMP_CFG0 0x26a8 |
| #define MT6338_AFE_ADDA_DL_DC_COMP_CFG1_H 0x26a9 |
| #define MT6338_AFE_ADDA_DL_DC_COMP_CFG1_M 0x26aa |
| #define MT6338_AFE_ADDA_DL_DC_COMP_CFG1_L 0x26ab |
| #define MT6338_AFE_ADDA_DL_DC_COMP_CFG1 0x26ac |
| #define MT6338_AFE_ADDA_DL_SDM_OUT_MON_H 0x26ad |
| #define MT6338_AFE_ADDA_DL_SDM_OUT_MON_M 0x26ae |
| #define MT6338_AFE_ADDA_DL_SDM_OUT_MON_L 0x26af |
| #define MT6338_AFE_ADDA_DL_SDM_OUT_MON 0x26b0 |
| #define MT6338_AFE_ADDA_DL_SRC_LCH_MON_M 0x26b1 |
| #define MT6338_AFE_ADDA_DL_SRC_LCH_MON_L 0x26b2 |
| #define MT6338_AFE_ADDA_DL_SRC_LCH_MON 0x26b3 |
| #define MT6338_AFE_ADDA_DL_SRC_RCH_MON_M 0x26b4 |
| #define MT6338_AFE_ADDA_DL_SRC_RCH_MON_L 0x26b5 |
| #define MT6338_AFE_ADDA_DL_SRC_RCH_MON 0x26b6 |
| #define MT6338_AFE_ADDA_DL_SRC_DEBUG_L 0x26b7 |
| #define MT6338_AFE_ADDA_DL_SRC_DEBUG 0x26b8 |
| #define MT6338_AFE_ADDA_DL_SDM_DITHER_CON_M 0x26b9 |
| #define MT6338_AFE_ADDA_DL_SDM_DITHER_CON 0x26ba |
| #define MT6338_AFE_ADDA_DL_SDM_AUTO_RESET_CON_H 0x26bb |
| #define MT6338_AFE_ADDA_DL_SDM_AUTO_RESET_CON_M 0x26bc |
| #define MT6338_AFE_ADDA_DL_SDM_AUTO_RESET_CON_L 0x26bd |
| #define MT6338_AFE_ADDA_DL_SDM_AUTO_RESET_CON 0x26be |
| #define MT6338_AFE_DL_XTALK_COMP_H1R2L_CON0_H 0x26bf |
| #define MT6338_AFE_DL_XTALK_COMP_H1R2L_CON0_M 0x26c0 |
| #define MT6338_AFE_DL_XTALK_COMP_H1R2L_CON0_L 0x26c1 |
| #define MT6338_AFE_DL_XTALK_COMP_H1R2L_CON0 0x26c2 |
| #define MT6338_AFE_DL_XTALK_COMP_H1L2R_CON0_H 0x26c3 |
| #define MT6338_AFE_DL_XTALK_COMP_H1L2R_CON0_M 0x26c4 |
| #define MT6338_AFE_DL_XTALK_COMP_H1L2R_CON0_L 0x26c5 |
| #define MT6338_AFE_DL_XTALK_COMP_H1L2R_CON0 0x26c6 |
| #define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON0_H 0x26c7 |
| #define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON0_M 0x26c8 |
| #define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON0_L 0x26c9 |
| #define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON0 0x26ca |
| #define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON1_M 0x26cb |
| #define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON1_L 0x26cc |
| #define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON1 0x26cd |
| #define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON2_M 0x26ce |
| #define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON2_L 0x26cf |
| #define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON2 0x26d0 |
| #define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON3_M 0x26d1 |
| #define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON3_L 0x26d2 |
| #define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON3 0x26d3 |
| #define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON4_M 0x26d4 |
| #define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON4_L 0x26d5 |
| #define MT6338_AFE_DL_XTALK_COMP_H2R2L_CON4 0x26d6 |
| #define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON0_H 0x26d7 |
| #define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON0_M 0x26d8 |
| #define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON0_L 0x26d9 |
| #define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON0 0x26da |
| #define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON1_M 0x26db |
| #define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON1_L 0x26dc |
| #define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON1 0x26dd |
| #define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON2_M 0x26de |
| #define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON2_L 0x26df |
| #define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON2 0x26e0 |
| #define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON3_M 0x26e1 |
| #define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON3_L 0x26e2 |
| #define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON3 0x26e3 |
| #define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON4_M 0x26e4 |
| #define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON4_L 0x26e5 |
| #define MT6338_AFE_DL_XTALK_COMP_H2L2R_CON4 0x26e6 |
| #define MT6338_AUDIO_DIG_8TH_DSN_ID 0x2700 |
| #define MT6338_AUDIO_DIG_8TH_DSN_ID_H 0x2701 |
| #define MT6338_AUDIO_DIG_8TH_DSN_REV0 0x2702 |
| #define MT6338_AUDIO_DIG_8TH_DSN_REV0_H 0x2703 |
| #define MT6338_AUDIO_DIG_8TH_DSN_DBI 0x2704 |
| #define MT6338_AUDIO_DIG_8TH_DSN_DBI_H 0x2705 |
| #define MT6338_AUDIO_DIG_8TH_DSN_DXI 0x2706 |
| #define MT6338_AFE_NLE_CFG_H 0x2707 |
| #define MT6338_AFE_NLE_CFG 0x2708 |
| #define MT6338_AFE_NLE_PRE_BUF_CFG_H 0x2709 |
| #define MT6338_AFE_NLE_PRE_BUF_CFG_M 0x270a |
| #define MT6338_AFE_NLE_PRE_BUF_CFG_L 0x270b |
| #define MT6338_AFE_NLE_PRE_BUF_CFG 0x270c |
| #define MT6338_AFE_NLE_PWR_DET_LCH_CFG_H 0x270d |
| #define MT6338_AFE_NLE_PWR_DET_LCH_CFG_M 0x270e |
| #define MT6338_AFE_NLE_PWR_DET_LCH_CFG_L 0x270f |
| #define MT6338_AFE_NLE_PWR_DET_LCH_CFG 0x2710 |
| #define MT6338_AFE_NLE_ZCD_LCH_CFG 0x2711 |
| #define MT6338_AFE_NLE_GAIN_ADJ_LCH_CFG0_H 0x2712 |
| #define MT6338_AFE_NLE_GAIN_ADJ_LCH_CFG0_M 0x2713 |
| #define MT6338_AFE_NLE_GAIN_ADJ_LCH_CFG0_L 0x2714 |
| #define MT6338_AFE_NLE_GAIN_ADJ_LCH_CFG0 0x2715 |
| #define MT6338_AFE_NLE_GAIN_IMP_LCH_CFG0_H 0x2716 |
| #define MT6338_AFE_NLE_GAIN_IMP_LCH_CFG0_M 0x2717 |
| #define MT6338_AFE_NLE_GAIN_IMP_LCH_CFG0_L 0x2718 |
| #define MT6338_AFE_NLE_GAIN_IMP_LCH_CFG0 0x2719 |
| #define MT6338_AFE_NLE_PWR_DET_LCH_MON_L 0x271a |
| #define MT6338_AFE_NLE_PWR_DET_LCH_MON 0x271b |
| #define MT6338_AFE_NLE_GAIN_ADJ_LCH_MON0_H 0x271c |
| #define MT6338_AFE_NLE_GAIN_ADJ_LCH_MON0_M 0x271d |
| #define MT6338_AFE_NLE_GAIN_ADJ_LCH_MON0_L 0x271e |
| #define MT6338_AFE_NLE_GAIN_ADJ_LCH_MON0 0x271f |
| #define MT6338_AFE_NLE_GAIN_ADJ_LCH_MON1_H 0x2720 |
| #define MT6338_AFE_NLE_GAIN_ADJ_LCH_MON1_M 0x2721 |
| #define MT6338_AFE_NLE_GAIN_ADJ_LCH_MON1_L 0x2722 |
| #define MT6338_AFE_NLE_GAIN_ADJ_LCH_MON1 0x2723 |
| #define MT6338_AFE_NLE_LCH_MON0_H 0x2724 |
| #define MT6338_AFE_NLE_LCH_MON0_M 0x2725 |
| #define MT6338_AFE_NLE_LCH_MON0_L 0x2726 |
| #define MT6338_AFE_NLE_LCH_MON0 0x2727 |
| #define MT6338_AFE_NLE_PWR_DET_RCH_CFG_H 0x2728 |
| #define MT6338_AFE_NLE_PWR_DET_RCH_CFG_M 0x2729 |
| #define MT6338_AFE_NLE_PWR_DET_RCH_CFG_L 0x272a |
| #define MT6338_AFE_NLE_PWR_DET_RCH_CFG 0x272b |
| #define MT6338_AFE_NLE_ZCD_RCH_CFG 0x272c |
| #define MT6338_AFE_NLE_GAIN_ADJ_RCH_CFG0_H 0x272d |
| #define MT6338_AFE_NLE_GAIN_ADJ_RCH_CFG0_M 0x272e |
| #define MT6338_AFE_NLE_GAIN_ADJ_RCH_CFG0_L 0x272f |
| #define MT6338_AFE_NLE_GAIN_ADJ_RCH_CFG0 0x2730 |
| #define MT6338_AFE_NLE_GAIN_IMP_RCH_CFG0_H 0x2731 |
| #define MT6338_AFE_NLE_GAIN_IMP_RCH_CFG0_M 0x2732 |
| #define MT6338_AFE_NLE_GAIN_IMP_RCH_CFG0_L 0x2733 |
| #define MT6338_AFE_NLE_GAIN_IMP_RCH_CFG0 0x2734 |
| #define MT6338_AFE_NLE_PWR_DET_RCH_MON_L 0x2735 |
| #define MT6338_AFE_NLE_PWR_DET_RCH_MON 0x2736 |
| #define MT6338_AFE_NLE_GAIN_ADJ_RCH_MON0_H 0x2737 |
| #define MT6338_AFE_NLE_GAIN_ADJ_RCH_MON0_M 0x2738 |
| #define MT6338_AFE_NLE_GAIN_ADJ_RCH_MON0_L 0x2739 |
| #define MT6338_AFE_NLE_GAIN_ADJ_RCH_MON0 0x273a |
| #define MT6338_AFE_NLE_GAIN_ADJ_RCH_MON1_H 0x273b |
| #define MT6338_AFE_NLE_GAIN_ADJ_RCH_MON1_M 0x273c |
| #define MT6338_AFE_NLE_GAIN_ADJ_RCH_MON1_L 0x273d |
| #define MT6338_AFE_NLE_GAIN_ADJ_RCH_MON1 0x273e |
| #define MT6338_AFE_NLE_RCH_MON0_H 0x273f |
| #define MT6338_AFE_NLE_RCH_MON0_M 0x2740 |
| #define MT6338_AFE_NLE_RCH_MON0_L 0x2741 |
| #define MT6338_AFE_NLE_RCH_MON0 0x2742 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G0_H 0x2743 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G0_M 0x2744 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G0_L 0x2745 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G0 0x2746 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G1_H 0x2747 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G1_M 0x2748 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G1_L 0x2749 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G1 0x274a |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G2_H 0x274b |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G2_M 0x274c |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G2_L 0x274d |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G2 0x274e |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G3_H 0x274f |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G3_M 0x2750 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G3_L 0x2751 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G3 0x2752 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G4_H 0x2753 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G4_M 0x2754 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G4_L 0x2755 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G4 0x2756 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G5_H 0x2757 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G5_M 0x2758 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G5_L 0x2759 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G5 0x275a |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G6_H 0x275b |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G6_M 0x275c |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G6_L 0x275d |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G6 0x275e |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G7_H 0x275f |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G7_M 0x2760 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G7_L 0x2761 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_LCH_G7 0x2762 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G0_H 0x2763 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G0_M 0x2764 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G0_L 0x2765 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G0 0x2766 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G1_H 0x2767 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G1_M 0x2768 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G1_L 0x2769 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G1 0x276a |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G2_H 0x276b |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G2_M 0x276c |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G2_L 0x276d |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G2 0x276e |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G3_H 0x276f |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G3_M 0x2770 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G3_L 0x2771 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G3 0x2772 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G4_H 0x2773 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G4_M 0x2774 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G4_L 0x2775 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G4 0x2776 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G5_H 0x2777 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G5_M 0x2778 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G5_L 0x2779 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G5 0x277a |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G6_H 0x277b |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G6_M 0x277c |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G6_L 0x277d |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G6 0x277e |
| #define MT6338_AUDIO_DIG_9TH_DSN_ID 0x2780 |
| #define MT6338_AUDIO_DIG_9TH_DSN_ID_H 0x2781 |
| #define MT6338_AUDIO_DIG_9TH_DSN_REV0 0x2782 |
| #define MT6338_AUDIO_DIG_9TH_DSN_REV0_H 0x2783 |
| #define MT6338_AUDIO_DIG_9TH_DSN_DBI 0x2784 |
| #define MT6338_AUDIO_DIG_9TH_DSN_DBI_H 0x2785 |
| #define MT6338_AUDIO_DIG_9TH_DSN_DXI 0x2786 |
| #define MT6338_AFE_ADDA_2ND_DL_SRC_CON0_H 0x2787 |
| #define MT6338_AFE_ADDA_2ND_DL_SRC_CON0_M 0x2788 |
| #define MT6338_AFE_ADDA_2ND_DL_SRC_CON0_L 0x2789 |
| #define MT6338_AFE_ADDA_2ND_DL_SRC_CON0 0x278a |
| #define MT6338_AFE_ADDA_2ND_DL_SRC_CON1_H 0x278b |
| #define MT6338_AFE_ADDA_2ND_DL_SRC_CON1_M 0x278c |
| #define MT6338_AFE_ADDA_2ND_DL_SRC_CON1 0x278d |
| #define MT6338_AFE_ADDA_2ND_DL_SRC_DEBUG_MON0_L 0x278e |
| #define MT6338_AFE_ADDA_2ND_DL_SRC_DEBUG_MON0 0x278f |
| #define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON0_H 0x2790 |
| #define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON0_M 0x2791 |
| #define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON0_L 0x2792 |
| #define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON0 0x2793 |
| #define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON1_H 0x2794 |
| #define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON1_M 0x2795 |
| #define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON1_L 0x2796 |
| #define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON1 0x2797 |
| #define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON2_H 0x2798 |
| #define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON2_M 0x2799 |
| #define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON2_L 0x279a |
| #define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON2 0x279b |
| #define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON3_H 0x279c |
| #define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON3_M 0x279d |
| #define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON3_L 0x279e |
| #define MT6338_AFE_ADDA_2ND_DL_PREDIS_CON3 0x279f |
| #define MT6338_AFE_ADDA_2ND_DL_SDM_DCCOMP_CON_H 0x27a0 |
| #define MT6338_AFE_ADDA_2ND_DL_SDM_DCCOMP_CON_L 0x27a1 |
| #define MT6338_AFE_ADDA_2ND_DL_SDM_DCCOMP_CON 0x27a2 |
| #define MT6338_AFE_ADDA_2ND_DL_SDM_TEST_L 0x27a3 |
| #define MT6338_AFE_ADDA_2ND_DL_SDM_TEST 0x27a4 |
| #define MT6338_AFE_ADDA_2ND_DL_DC_COMP_CFG0_H 0x27a5 |
| #define MT6338_AFE_ADDA_2ND_DL_DC_COMP_CFG0_M 0x27a6 |
| #define MT6338_AFE_ADDA_2ND_DL_DC_COMP_CFG0_L 0x27a7 |
| #define MT6338_AFE_ADDA_2ND_DL_DC_COMP_CFG0 0x27a8 |
| #define MT6338_AFE_ADDA_2ND_DL_DC_COMP_CFG1_H 0x27a9 |
| #define MT6338_AFE_ADDA_2ND_DL_DC_COMP_CFG1_M 0x27aa |
| #define MT6338_AFE_ADDA_2ND_DL_DC_COMP_CFG1_L 0x27ab |
| #define MT6338_AFE_ADDA_2ND_DL_DC_COMP_CFG1 0x27ac |
| #define MT6338_AFE_ADDA_2ND_DL_SRC_DEBUG_L 0x27ad |
| #define MT6338_AFE_ADDA_2ND_DL_SRC_DEBUG 0x27ae |
| #define MT6338_AFE_ADDA_2ND_DL_SRC_LCH_MON_M 0x27af |
| #define MT6338_AFE_ADDA_2ND_DL_SRC_LCH_MON_L 0x27b0 |
| #define MT6338_AFE_ADDA_2ND_DL_SRC_LCH_MON 0x27b1 |
| #define MT6338_AFE_ADDA_2ND_DL_SRC_RCH_MON_M 0x27b2 |
| #define MT6338_AFE_ADDA_2ND_DL_SRC_RCH_MON_L 0x27b3 |
| #define MT6338_AFE_ADDA_2ND_DL_SRC_RCH_MON 0x27b4 |
| #define MT6338_AFE_ADDA_2ND_DL_SDM_OUT_MON_H 0x27b5 |
| #define MT6338_AFE_ADDA_2ND_DL_SDM_OUT_MON_M 0x27b6 |
| #define MT6338_AFE_ADDA_2ND_DL_SDM_OUT_MON_L 0x27b7 |
| #define MT6338_AFE_ADDA_2ND_DL_SDM_OUT_MON 0x27b8 |
| #define MT6338_AFE_ADDA_2ND_DL_SDM_DITHER_CON_M 0x27b9 |
| #define MT6338_AFE_ADDA_2ND_DL_SDM_DITHER_CON 0x27ba |
| #define MT6338_AFE_ADDA_2ND_DL_SDM_AUTO_RESET_CON_H 0x27bb |
| #define MT6338_AFE_ADDA_2ND_DL_SDM_AUTO_RESET_CON_M 0x27bc |
| #define MT6338_AFE_ADDA_2ND_DL_SDM_AUTO_RESET_CON_L 0x27bd |
| #define MT6338_AFE_ADDA_2ND_DL_SDM_AUTO_RESET_CON 0x27be |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H1R2L_CON0_H 0x27bf |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H1R2L_CON0_M 0x27c0 |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H1R2L_CON0_L 0x27c1 |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H1R2L_CON0 0x27c2 |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H1L2R_CON0_H 0x27c3 |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H1L2R_CON0_M 0x27c4 |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H1L2R_CON0_L 0x27c5 |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H1L2R_CON0 0x27c6 |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON0_H 0x27c7 |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON0_M 0x27c8 |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON0_L 0x27c9 |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON0 0x27ca |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON1_M 0x27cb |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON1_L 0x27cc |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON1 0x27cd |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON2_M 0x27ce |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON2_L 0x27cf |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON2 0x27d0 |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON3_M 0x27d1 |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON3_L 0x27d2 |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON3 0x27d3 |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON4_M 0x27d4 |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON4_L 0x27d5 |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2R2L_CON4 0x27d6 |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON0_H 0x27d7 |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON0_M 0x27d8 |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON0_L 0x27d9 |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON0 0x27da |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON1_M 0x27db |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON1_L 0x27dc |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON1 0x27dd |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON2_M 0x27de |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON2_L 0x27df |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON2 0x27e0 |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON3_M 0x27e1 |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON3_L 0x27e2 |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON3 0x27e3 |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON4_M 0x27e4 |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON4_L 0x27e5 |
| #define MT6338_AFE_2ND_DL_XTALK_COMP_H2L2R_CON4 0x27e6 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G7_H 0x27e7 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G7_M 0x27e8 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G7_L 0x27e9 |
| #define MT6338_AFE_NLE_LNGAIN_COMP_RCH_G7 0x27ea |
| #define MT6338_AFE_NLE_D2A_DEBUG_H 0x27eb |
| #define MT6338_AFE_NLE_D2A_DEBUG_M 0x27ec |
| #define MT6338_AFE_NLE_D2A_DEBUG_L 0x27ed |
| #define MT6338_AFE_NLE_D2A_DEBUG 0x27ee |
| #define MT6338_AUDIO_DIG_10TH_DSN_ID 0x2800 |
| #define MT6338_AUDIO_DIG_10TH_DSN_ID_H 0x2801 |
| #define MT6338_AUDIO_DIG_10TH_DSN_REV0 0x2802 |
| #define MT6338_AUDIO_DIG_10TH_DSN_REV0_H 0x2803 |
| #define MT6338_AUDIO_DIG_10TH_DSN_DBI 0x2804 |
| #define MT6338_AUDIO_DIG_10TH_DSN_DBI_H 0x2805 |
| #define MT6338_AUDIO_DIG_10TH_DSN_DXI 0x2806 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_CONFIG_H 0x2807 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_CONFIG_M 0x2808 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_CONFIG_L 0x2809 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_CONFIG 0x280a |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_H 0x280b |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_M 0x280c |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_L 0x280d |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP1_TAP2_CONFIG 0x280e |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_H 0x280f |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_M 0x2810 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_L 0x2811 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP3_TAP4_CONFIG 0x2812 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_H 0x2813 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_M 0x2814 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_L 0x2815 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP5_TAP6_CONFIG 0x2816 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_H 0x2817 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_M 0x2818 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_L 0x2819 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP7_TAP8_CONFIG 0x281a |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_H 0x281b |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_M 0x281c |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_L 0x281d |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP9_TAP10_CONFIG 0x281e |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_H 0x281f |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_M 0x2820 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_L 0x2821 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP11_TAP12_CONFIG 0x2822 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_H 0x2823 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_M 0x2824 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_L 0x2825 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP13_TAP14_CONFIG 0x2826 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_H 0x2827 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_M 0x2828 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_L 0x2829 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP15_TAP16_CONFIG 0x282a |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_H 0x282b |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_M 0x282c |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_L 0x282d |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP17_TAP18_CONFIG 0x282e |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_H 0x282f |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_M 0x2830 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_L 0x2831 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP19_TAP20_CONFIG 0x2832 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_H 0x2833 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_M 0x2834 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_L 0x2835 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP21_TAP22_CONFIG 0x2836 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_H 0x2837 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_M 0x2838 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_L 0x2839 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP23_TAP24_CONFIG 0x283a |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_H 0x283b |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_M 0x283c |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_L 0x283d |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP25_TAP26_CONFIG 0x283e |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_H 0x283f |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_M 0x2840 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_L 0x2841 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP27_TAP28_CONFIG 0x2842 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_H 0x2843 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_M 0x2844 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_L 0x2845 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP29_TAP30_CONFIG 0x2846 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_H 0x2847 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_M 0x2848 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_L 0x2849 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP31_TAP32_CONFIG 0x284a |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_H 0x284b |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_M 0x284c |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_L 0x284d |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP33_TAP34_CONFIG 0x284e |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_H 0x284f |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_M 0x2850 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_L 0x2851 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP35_TAP36_CONFIG 0x2852 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_H 0x2853 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_M 0x2854 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_L 0x2855 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP37_TAP38_CONFIG 0x2856 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_H 0x2857 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_M 0x2858 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_L 0x2859 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP39_TAP40_CONFIG 0x285a |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_H 0x285b |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_M 0x285c |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_L 0x285d |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP41_TAP42_CONFIG 0x285e |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_H 0x285f |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_M 0x2860 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_L 0x2861 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP43_TAP44_CONFIG 0x2862 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_H 0x2863 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_M 0x2864 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_L 0x2865 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP45_TAP46_CONFIG 0x2866 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_H 0x2867 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_M 0x2868 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_L 0x2869 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP47_TAP48_CONFIG 0x286a |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_H 0x286b |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_M 0x286c |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_L 0x286d |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP49_TAP50_CONFIG 0x286e |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_H 0x286f |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_M 0x2870 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_L 0x2871 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP51_TAP52_CONFIG 0x2872 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_H 0x2873 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_M 0x2874 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_L 0x2875 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP53_TAP54_CONFIG 0x2876 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_H 0x2877 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_M 0x2878 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_L 0x2879 |
| #define MT6338_AFE_ADDA_DL_HBF1_SCF1_TAP55_TAP56_CONFIG 0x287a |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP57_TAP58_CONFIG_H 0x287b |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP57_TAP58_CONFIG_M 0x287c |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP57_TAP58_CONFIG_L 0x287d |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP57_TAP58_CONFIG 0x287e |
| #define MT6338_AUDIO_DIG_11TH_DSN_ID 0x2880 |
| #define MT6338_AUDIO_DIG_11TH_DSN_ID_H 0x2881 |
| #define MT6338_AUDIO_DIG_11TH_DSN_REV0 0x2882 |
| #define MT6338_AUDIO_DIG_11TH_DSN_REV0_H 0x2883 |
| #define MT6338_AUDIO_DIG_11TH_DSN_DBI 0x2884 |
| #define MT6338_AUDIO_DIG_11TH_DSN_DBI_H 0x2885 |
| #define MT6338_AUDIO_DIG_11TH_DSN_DXI 0x2886 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP59_TAP60_CONFIG_H 0x2887 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP59_TAP60_CONFIG_M 0x2888 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP59_TAP60_CONFIG_L 0x2889 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP59_TAP60_CONFIG 0x288a |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP61_TAP62_CONFIG_H 0x288b |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP61_TAP62_CONFIG_M 0x288c |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP61_TAP62_CONFIG_L 0x288d |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP61_TAP62_CONFIG 0x288e |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP63_TAP64_CONFIG_H 0x288f |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP63_TAP64_CONFIG_M 0x2890 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP63_TAP64_CONFIG_L 0x2891 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP63_TAP64_CONFIG 0x2892 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP65_TAP66_CONFIG_H 0x2893 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP65_TAP66_CONFIG_M 0x2894 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP65_TAP66_CONFIG_L 0x2895 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP65_TAP66_CONFIG 0x2896 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP67_TAP68_CONFIG_H 0x2897 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP67_TAP68_CONFIG_M 0x2898 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP67_TAP68_CONFIG_L 0x2899 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP67_TAP68_CONFIG 0x289a |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP69_TAP70_CONFIG_H 0x289b |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP69_TAP70_CONFIG_M 0x289c |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP69_TAP70_CONFIG_L 0x289d |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP69_TAP70_CONFIG 0x289e |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP71_TAP72_CONFIG_H 0x289f |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP71_TAP72_CONFIG_M 0x28a0 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP71_TAP72_CONFIG_L 0x28a1 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP71_TAP72_CONFIG 0x28a2 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP73_TAP74_CONFIG_H 0x28a3 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP73_TAP74_CONFIG_M 0x28a4 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP73_TAP74_CONFIG_L 0x28a5 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP73_TAP74_CONFIG 0x28a6 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP75_TAP76_CONFIG_H 0x28a7 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP75_TAP76_CONFIG_M 0x28a8 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP75_TAP76_CONFIG_L 0x28a9 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP75_TAP76_CONFIG 0x28aa |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP77_TAP78_CONFIG_H 0x28ab |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP77_TAP78_CONFIG_M 0x28ac |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP77_TAP78_CONFIG_L 0x28ad |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP77_TAP78_CONFIG 0x28ae |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP79_TAP80_CONFIG_H 0x28af |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP79_TAP80_CONFIG_M 0x28b0 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP79_TAP80_CONFIG_L 0x28b1 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP79_TAP80_CONFIG 0x28b2 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP81_TAP82_CONFIG_H 0x28b3 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP81_TAP82_CONFIG_M 0x28b4 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP81_TAP82_CONFIG_L 0x28b5 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP81_TAP82_CONFIG 0x28b6 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP83_TAP84_CONFIG_H 0x28b7 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP83_TAP84_CONFIG_M 0x28b8 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP83_TAP84_CONFIG_L 0x28b9 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP83_TAP84_CONFIG 0x28ba |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP85_TAP86_CONFIG_H 0x28bb |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP85_TAP86_CONFIG_M 0x28bc |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP85_TAP86_CONFIG_L 0x28bd |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP85_TAP86_CONFIG 0x28be |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP87_TAP88_CONFIG_H 0x28bf |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP87_TAP88_CONFIG_M 0x28c0 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP87_TAP88_CONFIG_L 0x28c1 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP87_TAP88_CONFIG 0x28c2 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP89_TAP90_CONFIG_H 0x28c3 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP89_TAP90_CONFIG_M 0x28c4 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP89_TAP90_CONFIG_L 0x28c5 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP89_TAP90_CONFIG 0x28c6 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP91_TAP92_CONFIG_H 0x28c7 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP91_TAP92_CONFIG_M 0x28c8 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP91_TAP92_CONFIG_L 0x28c9 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP91_TAP92_CONFIG 0x28ca |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP93_TAP94_CONFIG_H 0x28cb |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP93_TAP94_CONFIG_M 0x28cc |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP93_TAP94_CONFIG_L 0x28cd |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP93_TAP94_CONFIG 0x28ce |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP95_TAP96_CONFIG_H 0x28cf |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP95_TAP96_CONFIG_M 0x28d0 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP95_TAP96_CONFIG_L 0x28d1 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP95_TAP96_CONFIG 0x28d2 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP97_TAP98_CONFIG_H 0x28d3 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP97_TAP98_CONFIG_M 0x28d4 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP97_TAP98_CONFIG_L 0x28d5 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP97_TAP98_CONFIG 0x28d6 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP99_TAP100_CONFIG_H 0x28d7 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP99_TAP100_CONFIG_M 0x28d8 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP99_TAP100_CONFIG_L 0x28d9 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP99_TAP100_CONFIG 0x28da |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP101_TAP102_CONFIG_H 0x28db |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP101_TAP102_CONFIG_M 0x28dc |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP101_TAP102_CONFIG_L 0x28dd |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP101_TAP102_CONFIG 0x28de |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP103_TAP104_CONFIG_H 0x28df |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP103_TAP104_CONFIG_M 0x28e0 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP103_TAP104_CONFIG_L 0x28e1 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP103_TAP104_CONFIG 0x28e2 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP105_TAP106_CONFIG_H 0x28e3 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP105_TAP106_CONFIG_M 0x28e4 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP105_TAP106_CONFIG_L 0x28e5 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP105_TAP106_CONFIG 0x28e6 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP107_TAP108_CONFIG_H 0x28e7 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP107_TAP108_CONFIG_M 0x28e8 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP107_TAP108_CONFIG_L 0x28e9 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP107_TAP108_CONFIG 0x28ea |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP109_TAP110_CONFIG_H 0x28eb |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP109_TAP110_CONFIG_M 0x28ec |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP109_TAP110_CONFIG_L 0x28ed |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP109_TAP110_CONFIG 0x28ee |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP111_TAP112_CONFIG_H 0x28ef |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP111_TAP112_CONFIG_M 0x28f0 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP111_TAP112_CONFIG_L 0x28f1 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP111_TAP112_CONFIG 0x28f2 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP113_TAP114_CONFIG_H 0x28f3 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP113_TAP114_CONFIG_M 0x28f4 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP113_TAP114_CONFIG_L 0x28f5 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP113_TAP114_CONFIG 0x28f6 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP115_TAP116_CONFIG_H 0x28f7 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP115_TAP116_CONFIG_M 0x28f8 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP115_TAP116_CONFIG_L 0x28f9 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP115_TAP116_CONFIG 0x28fa |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP117_TAP118_CONFIG_H 0x28fb |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP117_TAP118_CONFIG_M 0x28fc |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP117_TAP118_CONFIG_L 0x28fd |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP117_TAP118_CONFIG 0x28fe |
| #define MT6338_AUDIO_DIG_12TH_DSN_ID 0x2900 |
| #define MT6338_AUDIO_DIG_12TH_DSN_ID_H 0x2901 |
| #define MT6338_AUDIO_DIG_12TH_DSN_REV0 0x2902 |
| #define MT6338_AUDIO_DIG_12TH_DSN_REV0_H 0x2903 |
| #define MT6338_AUDIO_DIG_12TH_DSN_DBI 0x2904 |
| #define MT6338_AUDIO_DIG_12TH_DSN_DBI_H 0x2905 |
| #define MT6338_AUDIO_DIG_12TH_DSN_DXI 0x2906 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP119_TAP120_CONFIG_H 0x2907 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP119_TAP120_CONFIG_M 0x2908 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP119_TAP120_CONFIG_L 0x2909 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP119_TAP120_CONFIG 0x290a |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP121_TAP122_CONFIG_H 0x290b |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP121_TAP122_CONFIG_M 0x290c |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP121_TAP122_CONFIG_L 0x290d |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP121_TAP122_CONFIG 0x290e |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP123_TAP124_CONFIG_H 0x290f |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP123_TAP124_CONFIG_M 0x2910 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP123_TAP124_CONFIG_L 0x2911 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP123_TAP124_CONFIG 0x2912 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP125_TAP126_CONFIG_H 0x2913 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP125_TAP126_CONFIG_M 0x2914 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP125_TAP126_CONFIG_L 0x2915 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP125_TAP126_CONFIG 0x2916 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP127_TAP128_CONFIG_H 0x2917 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP127_TAP128_CONFIG_M 0x2918 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP127_TAP128_CONFIG_L 0x2919 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP127_TAP128_CONFIG 0x291a |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP129_TAP130_CONFIG_H 0x291b |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP129_TAP130_CONFIG_M 0x291c |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP129_TAP130_CONFIG_L 0x291d |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP129_TAP130_CONFIG 0x291e |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP131_TAP132_CONFIG_H 0x291f |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP131_TAP132_CONFIG_M 0x2920 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP131_TAP132_CONFIG_L 0x2921 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP131_TAP132_CONFIG 0x2922 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP133_TAP134_CONFIG_H 0x2923 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP133_TAP134_CONFIG_M 0x2924 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP133_TAP134_CONFIG_L 0x2925 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP133_TAP134_CONFIG 0x2926 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP135_TAP136_CONFIG_H 0x2927 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP135_TAP136_CONFIG_M 0x2928 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP135_TAP136_CONFIG_L 0x2929 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP135_TAP136_CONFIG 0x292a |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP137_TAP138_CONFIG_H 0x292b |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP137_TAP138_CONFIG_M 0x292c |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP137_TAP138_CONFIG_L 0x292d |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP137_TAP138_CONFIG 0x292e |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP139_TAP140_CONFIG_H 0x292f |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP139_TAP140_CONFIG_M 0x2930 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP139_TAP140_CONFIG_L 0x2931 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP139_TAP140_CONFIG 0x2932 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP141_TAP142_CONFIG_H 0x2933 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP141_TAP142_CONFIG_M 0x2934 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP141_TAP142_CONFIG_L 0x2935 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP141_TAP142_CONFIG 0x2936 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP143_TAP144_CONFIG_H 0x2937 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP143_TAP144_CONFIG_M 0x2938 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP143_TAP144_CONFIG_L 0x2939 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP143_TAP144_CONFIG 0x293a |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP145_TAP146_CONFIG_H 0x293b |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP145_TAP146_CONFIG_M 0x293c |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP145_TAP146_CONFIG_L 0x293d |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP145_TAP146_CONFIG 0x293e |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP147_TAP148_CONFIG_H 0x293f |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP147_TAP148_CONFIG_M 0x2940 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP147_TAP148_CONFIG_L 0x2941 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP147_TAP148_CONFIG 0x2942 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP149_TAP150_CONFIG_H 0x2943 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP149_TAP150_CONFIG_M 0x2944 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP149_TAP150_CONFIG_L 0x2945 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP149_TAP150_CONFIG 0x2946 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP151_TAP152_CONFIG_H 0x2947 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP151_TAP152_CONFIG_M 0x2948 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP151_TAP152_CONFIG_L 0x2949 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP151_TAP152_CONFIG 0x294a |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP153_TAP154_CONFIG_H 0x294b |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP153_TAP154_CONFIG_M 0x294c |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP153_TAP154_CONFIG_L 0x294d |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP153_TAP154_CONFIG 0x294e |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP155_TAP156_CONFIG_H 0x294f |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP155_TAP156_CONFIG_M 0x2950 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP155_TAP156_CONFIG_L 0x2951 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP155_TAP156_CONFIG 0x2952 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP157_TAP158_CONFIG_H 0x2953 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP157_TAP158_CONFIG_M 0x2954 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP157_TAP158_CONFIG_L 0x2955 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP157_TAP158_CONFIG 0x2956 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP159_TAP160_CONFIG_H 0x2957 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP159_TAP160_CONFIG_M 0x2958 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP159_TAP160_CONFIG_L 0x2959 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP159_TAP160_CONFIG 0x295a |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP161_TAP162_CONFIG_H 0x295b |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP161_TAP162_CONFIG_M 0x295c |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP161_TAP162_CONFIG_L 0x295d |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP161_TAP162_CONFIG 0x295e |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP163_TAP164_CONFIG_H 0x295f |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP163_TAP164_CONFIG_M 0x2960 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP163_TAP164_CONFIG_L 0x2961 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP163_TAP164_CONFIG 0x2962 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP165_TAP166_CONFIG_H 0x2963 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP165_TAP166_CONFIG_M 0x2964 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP165_TAP166_CONFIG_L 0x2965 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP165_TAP166_CONFIG 0x2966 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP167_TAP168_CONFIG_H 0x2967 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP167_TAP168_CONFIG_M 0x2968 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP167_TAP168_CONFIG_L 0x2969 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP167_TAP168_CONFIG 0x296a |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP169_TAP170_CONFIG_H 0x296b |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP169_TAP170_CONFIG_M 0x296c |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP169_TAP170_CONFIG_L 0x296d |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP169_TAP170_CONFIG 0x296e |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP171_TAP172_CONFIG_H 0x296f |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP171_TAP172_CONFIG_M 0x2970 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP171_TAP172_CONFIG_L 0x2971 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP171_TAP172_CONFIG 0x2972 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP173_TAP174_CONFIG_H 0x2973 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP173_TAP174_CONFIG_M 0x2974 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP173_TAP174_CONFIG_L 0x2975 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP173_TAP174_CONFIG 0x2976 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP175_TAP176_CONFIG_H 0x2977 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP175_TAP176_CONFIG_M 0x2978 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP175_TAP176_CONFIG_L 0x2979 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP175_TAP176_CONFIG 0x297a |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP177_TAP178_CONFIG_H 0x297b |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP177_TAP178_CONFIG_M 0x297c |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP177_TAP178_CONFIG_L 0x297d |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP177_TAP178_CONFIG 0x297e |
| #define MT6338_AUDIO_DIG_13TH_DSN_ID 0x2980 |
| #define MT6338_AUDIO_DIG_13TH_DSN_ID_H 0x2981 |
| #define MT6338_AUDIO_DIG_13TH_DSN_REV0 0x2982 |
| #define MT6338_AUDIO_DIG_13TH_DSN_REV0_H 0x2983 |
| #define MT6338_AUDIO_DIG_13TH_DSN_DBI 0x2984 |
| #define MT6338_AUDIO_DIG_13TH_DSN_DBI_H 0x2985 |
| #define MT6338_AUDIO_DIG_13TH_DSN_DXI 0x2986 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP179_TAP180_CONFIG_H 0x2987 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP179_TAP180_CONFIG_M 0x2988 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP179_TAP180_CONFIG_L 0x2989 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP179_TAP180_CONFIG 0x298a |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP181_TAP182_CONFIG_H 0x298b |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP181_TAP182_CONFIG_M 0x298c |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP181_TAP182_CONFIG_L 0x298d |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP181_TAP182_CONFIG 0x298e |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP183_TAP184_CONFIG_H 0x298f |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP183_TAP184_CONFIG_M 0x2990 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP183_TAP184_CONFIG_L 0x2991 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP183_TAP184_CONFIG 0x2992 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP185_TAP186_CONFIG_H 0x2993 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP185_TAP186_CONFIG_M 0x2994 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP185_TAP186_CONFIG_L 0x2995 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP185_TAP186_CONFIG 0x2996 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP187_TAP188_CONFIG_H 0x2997 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP187_TAP188_CONFIG_M 0x2998 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP187_TAP188_CONFIG_L 0x2999 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP187_TAP188_CONFIG 0x299a |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP189_TAP190_CONFIG_H 0x299b |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP189_TAP190_CONFIG_M 0x299c |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP189_TAP190_CONFIG_L 0x299d |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP189_TAP190_CONFIG 0x299e |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP191_TAP192_CONFIG_H 0x299f |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP191_TAP192_CONFIG_M 0x29a0 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP191_TAP192_CONFIG_L 0x29a1 |
| #define MT6338_AFE_ADDA_DL_SCF1_TAP191_TAP192_CONFIG 0x29a2 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP179_TAP180_CONFIG_H 0x29a3 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP179_TAP180_CONFIG_M 0x29a4 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP179_TAP180_CONFIG_L 0x29a5 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP179_TAP180_CONFIG 0x29a6 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP181_TAP182_CONFIG_H 0x29a7 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP181_TAP182_CONFIG_M 0x29a8 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP181_TAP182_CONFIG_L 0x29a9 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP181_TAP182_CONFIG 0x29aa |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP183_TAP184_CONFIG_H 0x29ab |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP183_TAP184_CONFIG_M 0x29ac |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP183_TAP184_CONFIG_L 0x29ad |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP183_TAP184_CONFIG 0x29ae |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP185_TAP186_CONFIG_H 0x29af |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP185_TAP186_CONFIG_M 0x29b0 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP185_TAP186_CONFIG_L 0x29b1 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP185_TAP186_CONFIG 0x29b2 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP187_TAP188_CONFIG_H 0x29b3 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP187_TAP188_CONFIG_M 0x29b4 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP187_TAP188_CONFIG_L 0x29b5 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP187_TAP188_CONFIG 0x29b6 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP189_TAP190_CONFIG_H 0x29b7 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP189_TAP190_CONFIG_M 0x29b8 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP189_TAP190_CONFIG_L 0x29b9 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP189_TAP190_CONFIG 0x29ba |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP191_TAP192_CONFIG_H 0x29bb |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP191_TAP192_CONFIG_M 0x29bc |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP191_TAP192_CONFIG_L 0x29bd |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP191_TAP192_CONFIG 0x29be |
| #define MT6338_AUDIO_DIG_14TH_DSN_ID 0x2a00 |
| #define MT6338_AUDIO_DIG_14TH_DSN_ID_H 0x2a01 |
| #define MT6338_AUDIO_DIG_14TH_DSN_REV0 0x2a02 |
| #define MT6338_AUDIO_DIG_14TH_DSN_REV0_H 0x2a03 |
| #define MT6338_AUDIO_DIG_14TH_DSN_DBI 0x2a04 |
| #define MT6338_AUDIO_DIG_14TH_DSN_DBI_H 0x2a05 |
| #define MT6338_AUDIO_DIG_14TH_DSN_DXI 0x2a06 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_CONFIG_H 0x2a07 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_CONFIG_M 0x2a08 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_CONFIG_L 0x2a09 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_CONFIG 0x2a0a |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_H 0x2a0b |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_M 0x2a0c |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_L 0x2a0d |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP1_TAP2_CONFIG 0x2a0e |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_H 0x2a0f |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_M 0x2a10 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_L 0x2a11 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP3_TAP4_CONFIG 0x2a12 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_H 0x2a13 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_M 0x2a14 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_L 0x2a15 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP5_TAP6_CONFIG 0x2a16 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_H 0x2a17 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_M 0x2a18 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_L 0x2a19 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP7_TAP8_CONFIG 0x2a1a |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_H 0x2a1b |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_M 0x2a1c |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_L 0x2a1d |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP9_TAP10_CONFIG 0x2a1e |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_H 0x2a1f |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_M 0x2a20 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_L 0x2a21 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP11_TAP12_CONFIG 0x2a22 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_H 0x2a23 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_M 0x2a24 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_L 0x2a25 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP13_TAP14_CONFIG 0x2a26 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_H 0x2a27 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_M 0x2a28 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_L 0x2a29 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP15_TAP16_CONFIG 0x2a2a |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_H 0x2a2b |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_M 0x2a2c |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_L 0x2a2d |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP17_TAP18_CONFIG 0x2a2e |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_H 0x2a2f |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_M 0x2a30 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_L 0x2a31 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP19_TAP20_CONFIG 0x2a32 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_H 0x2a33 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_M 0x2a34 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_L 0x2a35 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP21_TAP22_CONFIG 0x2a36 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_H 0x2a37 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_M 0x2a38 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_L 0x2a39 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP23_TAP24_CONFIG 0x2a3a |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_H 0x2a3b |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_M 0x2a3c |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_L 0x2a3d |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP25_TAP26_CONFIG 0x2a3e |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_H 0x2a3f |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_M 0x2a40 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_L 0x2a41 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP27_TAP28_CONFIG 0x2a42 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_H 0x2a43 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_M 0x2a44 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_L 0x2a45 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP29_TAP30_CONFIG 0x2a46 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_H 0x2a47 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_M 0x2a48 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_L 0x2a49 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP31_TAP32_CONFIG 0x2a4a |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_H 0x2a4b |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_M 0x2a4c |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_L 0x2a4d |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP33_TAP34_CONFIG 0x2a4e |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_H 0x2a4f |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_M 0x2a50 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_L 0x2a51 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP35_TAP36_CONFIG 0x2a52 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_H 0x2a53 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_M 0x2a54 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_L 0x2a55 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP37_TAP38_CONFIG 0x2a56 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_H 0x2a57 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_M 0x2a58 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_L 0x2a59 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP39_TAP40_CONFIG 0x2a5a |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_H 0x2a5b |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_M 0x2a5c |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_L 0x2a5d |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP41_TAP42_CONFIG 0x2a5e |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_H 0x2a5f |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_M 0x2a60 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_L 0x2a61 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP43_TAP44_CONFIG 0x2a62 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_H 0x2a63 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_M 0x2a64 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_L 0x2a65 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP45_TAP46_CONFIG 0x2a66 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_H 0x2a67 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_M 0x2a68 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_L 0x2a69 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP47_TAP48_CONFIG 0x2a6a |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_H 0x2a6b |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_M 0x2a6c |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_L 0x2a6d |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP49_TAP50_CONFIG 0x2a6e |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_H 0x2a6f |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_M 0x2a70 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_L 0x2a71 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP51_TAP52_CONFIG 0x2a72 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_H 0x2a73 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_M 0x2a74 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_L 0x2a75 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP53_TAP54_CONFIG 0x2a76 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_H 0x2a77 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_M 0x2a78 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_L 0x2a79 |
| #define MT6338_AFE_ADDA_2ND_DL_HBF1_SCF1_TAP55_TAP56_CONFIG 0x2a7a |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP57_TAP58_CONFIG_H 0x2a7b |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP57_TAP58_CONFIG_M 0x2a7c |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP57_TAP58_CONFIG_L 0x2a7d |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP57_TAP58_CONFIG 0x2a7e |
| #define MT6338_AUDIO_DIG_15TH_DSN_ID 0x2a80 |
| #define MT6338_AUDIO_DIG_15TH_DSN_ID_H 0x2a81 |
| #define MT6338_AUDIO_DIG_15TH_DSN_REV0 0x2a82 |
| #define MT6338_AUDIO_DIG_15TH_DSN_REV0_H 0x2a83 |
| #define MT6338_AUDIO_DIG_15TH_DSN_DBI 0x2a84 |
| #define MT6338_AUDIO_DIG_15TH_DSN_DBI_H 0x2a85 |
| #define MT6338_AUDIO_DIG_15TH_DSN_DXI 0x2a86 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP59_TAP60_CONFIG_H 0x2a87 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP59_TAP60_CONFIG_M 0x2a88 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP59_TAP60_CONFIG_L 0x2a89 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP59_TAP60_CONFIG 0x2a8a |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP61_TAP62_CONFIG_H 0x2a8b |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP61_TAP62_CONFIG_M 0x2a8c |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP61_TAP62_CONFIG_L 0x2a8d |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP61_TAP62_CONFIG 0x2a8e |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP63_TAP64_CONFIG_H 0x2a8f |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP63_TAP64_CONFIG_M 0x2a90 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP63_TAP64_CONFIG_L 0x2a91 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP63_TAP64_CONFIG 0x2a92 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP65_TAP66_CONFIG_H 0x2a93 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP65_TAP66_CONFIG_M 0x2a94 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP65_TAP66_CONFIG_L 0x2a95 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP65_TAP66_CONFIG 0x2a96 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP67_TAP68_CONFIG_H 0x2a97 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP67_TAP68_CONFIG_M 0x2a98 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP67_TAP68_CONFIG_L 0x2a99 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP67_TAP68_CONFIG 0x2a9a |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP69_TAP70_CONFIG_H 0x2a9b |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP69_TAP70_CONFIG_M 0x2a9c |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP69_TAP70_CONFIG_L 0x2a9d |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP69_TAP70_CONFIG 0x2a9e |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP71_TAP72_CONFIG_H 0x2a9f |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP71_TAP72_CONFIG_M 0x2aa0 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP71_TAP72_CONFIG_L 0x2aa1 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP71_TAP72_CONFIG 0x2aa2 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP73_TAP74_CONFIG_H 0x2aa3 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP73_TAP74_CONFIG_M 0x2aa4 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP73_TAP74_CONFIG_L 0x2aa5 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP73_TAP74_CONFIG 0x2aa6 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP75_TAP76_CONFIG_H 0x2aa7 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP75_TAP76_CONFIG_M 0x2aa8 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP75_TAP76_CONFIG_L 0x2aa9 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP75_TAP76_CONFIG 0x2aaa |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP77_TAP78_CONFIG_H 0x2aab |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP77_TAP78_CONFIG_M 0x2aac |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP77_TAP78_CONFIG_L 0x2aad |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP77_TAP78_CONFIG 0x2aae |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP79_TAP80_CONFIG_H 0x2aaf |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP79_TAP80_CONFIG_M 0x2ab0 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP79_TAP80_CONFIG_L 0x2ab1 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP79_TAP80_CONFIG 0x2ab2 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP81_TAP82_CONFIG_H 0x2ab3 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP81_TAP82_CONFIG_M 0x2ab4 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP81_TAP82_CONFIG_L 0x2ab5 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP81_TAP82_CONFIG 0x2ab6 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP83_TAP84_CONFIG_H 0x2ab7 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP83_TAP84_CONFIG_M 0x2ab8 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP83_TAP84_CONFIG_L 0x2ab9 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP83_TAP84_CONFIG 0x2aba |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP85_TAP86_CONFIG_H 0x2abb |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP85_TAP86_CONFIG_M 0x2abc |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP85_TAP86_CONFIG_L 0x2abd |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP85_TAP86_CONFIG 0x2abe |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP87_TAP88_CONFIG_H 0x2abf |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP87_TAP88_CONFIG_M 0x2ac0 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP87_TAP88_CONFIG_L 0x2ac1 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP87_TAP88_CONFIG 0x2ac2 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP89_TAP90_CONFIG_H 0x2ac3 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP89_TAP90_CONFIG_M 0x2ac4 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP89_TAP90_CONFIG_L 0x2ac5 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP89_TAP90_CONFIG 0x2ac6 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP91_TAP92_CONFIG_H 0x2ac7 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP91_TAP92_CONFIG_M 0x2ac8 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP91_TAP92_CONFIG_L 0x2ac9 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP91_TAP92_CONFIG 0x2aca |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP93_TAP94_CONFIG_H 0x2acb |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP93_TAP94_CONFIG_M 0x2acc |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP93_TAP94_CONFIG_L 0x2acd |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP93_TAP94_CONFIG 0x2ace |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP95_TAP96_CONFIG_H 0x2acf |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP95_TAP96_CONFIG_M 0x2ad0 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP95_TAP96_CONFIG_L 0x2ad1 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP95_TAP96_CONFIG 0x2ad2 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP97_TAP98_CONFIG_H 0x2ad3 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP97_TAP98_CONFIG_M 0x2ad4 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP97_TAP98_CONFIG_L 0x2ad5 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP97_TAP98_CONFIG 0x2ad6 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP99_TAP100_CONFIG_H 0x2ad7 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP99_TAP100_CONFIG_M 0x2ad8 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP99_TAP100_CONFIG_L 0x2ad9 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP99_TAP100_CONFIG 0x2ada |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP101_TAP102_CONFIG_H 0x2adb |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP101_TAP102_CONFIG_M 0x2adc |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP101_TAP102_CONFIG_L 0x2add |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP101_TAP102_CONFIG 0x2ade |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP103_TAP104_CONFIG_H 0x2adf |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP103_TAP104_CONFIG_M 0x2ae0 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP103_TAP104_CONFIG_L 0x2ae1 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP103_TAP104_CONFIG 0x2ae2 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP105_TAP106_CONFIG_H 0x2ae3 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP105_TAP106_CONFIG_M 0x2ae4 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP105_TAP106_CONFIG_L 0x2ae5 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP105_TAP106_CONFIG 0x2ae6 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP107_TAP108_CONFIG_H 0x2ae7 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP107_TAP108_CONFIG_M 0x2ae8 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP107_TAP108_CONFIG_L 0x2ae9 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP107_TAP108_CONFIG 0x2aea |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP109_TAP110_CONFIG_H 0x2aeb |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP109_TAP110_CONFIG_M 0x2aec |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP109_TAP110_CONFIG_L 0x2aed |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP109_TAP110_CONFIG 0x2aee |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP111_TAP112_CONFIG_H 0x2aef |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP111_TAP112_CONFIG_M 0x2af0 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP111_TAP112_CONFIG_L 0x2af1 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP111_TAP112_CONFIG 0x2af2 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP113_TAP114_CONFIG_H 0x2af3 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP113_TAP114_CONFIG_M 0x2af4 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP113_TAP114_CONFIG_L 0x2af5 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP113_TAP114_CONFIG 0x2af6 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP115_TAP116_CONFIG_H 0x2af7 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP115_TAP116_CONFIG_M 0x2af8 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP115_TAP116_CONFIG_L 0x2af9 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP115_TAP116_CONFIG 0x2afa |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP117_TAP118_CONFIG_H 0x2afb |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP117_TAP118_CONFIG_M 0x2afc |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP117_TAP118_CONFIG_L 0x2afd |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP117_TAP118_CONFIG 0x2afe |
| #define MT6338_AUDIO_DIG_16TH_DSN_ID 0x2b00 |
| #define MT6338_AUDIO_DIG_16TH_DSN_ID_H 0x2b01 |
| #define MT6338_AUDIO_DIG_16TH_DSN_REV0 0x2b02 |
| #define MT6338_AUDIO_DIG_16TH_DSN_REV0_H 0x2b03 |
| #define MT6338_AUDIO_DIG_16TH_DSN_DBI 0x2b04 |
| #define MT6338_AUDIO_DIG_16TH_DSN_DBI_H 0x2b05 |
| #define MT6338_AUDIO_DIG_16TH_DSN_DXI 0x2b06 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP119_TAP120_CONFIG_H 0x2b07 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP119_TAP120_CONFIG_M 0x2b08 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP119_TAP120_CONFIG_L 0x2b09 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP119_TAP120_CONFIG 0x2b0a |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP121_TAP122_CONFIG_H 0x2b0b |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP121_TAP122_CONFIG_M 0x2b0c |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP121_TAP122_CONFIG_L 0x2b0d |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP121_TAP122_CONFIG 0x2b0e |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP123_TAP124_CONFIG_H 0x2b0f |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP123_TAP124_CONFIG_M 0x2b10 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP123_TAP124_CONFIG_L 0x2b11 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP123_TAP124_CONFIG 0x2b12 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP125_TAP126_CONFIG_H 0x2b13 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP125_TAP126_CONFIG_M 0x2b14 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP125_TAP126_CONFIG_L 0x2b15 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP125_TAP126_CONFIG 0x2b16 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP127_TAP128_CONFIG_H 0x2b17 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP127_TAP128_CONFIG_M 0x2b18 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP127_TAP128_CONFIG_L 0x2b19 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP127_TAP128_CONFIG 0x2b1a |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP129_TAP130_CONFIG_H 0x2b1b |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP129_TAP130_CONFIG_M 0x2b1c |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP129_TAP130_CONFIG_L 0x2b1d |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP129_TAP130_CONFIG 0x2b1e |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP131_TAP132_CONFIG_H 0x2b1f |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP131_TAP132_CONFIG_M 0x2b20 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP131_TAP132_CONFIG_L 0x2b21 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP131_TAP132_CONFIG 0x2b22 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP133_TAP134_CONFIG_H 0x2b23 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP133_TAP134_CONFIG_M 0x2b24 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP133_TAP134_CONFIG_L 0x2b25 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP133_TAP134_CONFIG 0x2b26 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP135_TAP136_CONFIG_H 0x2b27 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP135_TAP136_CONFIG_M 0x2b28 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP135_TAP136_CONFIG_L 0x2b29 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP135_TAP136_CONFIG 0x2b2a |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP137_TAP138_CONFIG_H 0x2b2b |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP137_TAP138_CONFIG_M 0x2b2c |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP137_TAP138_CONFIG_L 0x2b2d |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP137_TAP138_CONFIG 0x2b2e |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP139_TAP140_CONFIG_H 0x2b2f |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP139_TAP140_CONFIG_M 0x2b30 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP139_TAP140_CONFIG_L 0x2b31 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP139_TAP140_CONFIG 0x2b32 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP141_TAP142_CONFIG_H 0x2b33 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP141_TAP142_CONFIG_M 0x2b34 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP141_TAP142_CONFIG_L 0x2b35 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP141_TAP142_CONFIG 0x2b36 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP143_TAP144_CONFIG_H 0x2b37 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP143_TAP144_CONFIG_M 0x2b38 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP143_TAP144_CONFIG_L 0x2b39 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP143_TAP144_CONFIG 0x2b3a |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP145_TAP146_CONFIG_H 0x2b3b |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP145_TAP146_CONFIG_M 0x2b3c |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP145_TAP146_CONFIG_L 0x2b3d |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP145_TAP146_CONFIG 0x2b3e |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP147_TAP148_CONFIG_H 0x2b3f |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP147_TAP148_CONFIG_M 0x2b40 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP147_TAP148_CONFIG_L 0x2b41 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP147_TAP148_CONFIG 0x2b42 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP149_TAP150_CONFIG_H 0x2b43 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP149_TAP150_CONFIG_M 0x2b44 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP149_TAP150_CONFIG_L 0x2b45 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP149_TAP150_CONFIG 0x2b46 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP151_TAP152_CONFIG_H 0x2b47 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP151_TAP152_CONFIG_M 0x2b48 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP151_TAP152_CONFIG_L 0x2b49 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP151_TAP152_CONFIG 0x2b4a |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP153_TAP154_CONFIG_H 0x2b4b |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP153_TAP154_CONFIG_M 0x2b4c |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP153_TAP154_CONFIG_L 0x2b4d |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP153_TAP154_CONFIG 0x2b4e |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP155_TAP156_CONFIG_H 0x2b4f |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP155_TAP156_CONFIG_M 0x2b50 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP155_TAP156_CONFIG_L 0x2b51 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP155_TAP156_CONFIG 0x2b52 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP157_TAP158_CONFIG_H 0x2b53 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP157_TAP158_CONFIG_M 0x2b54 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP157_TAP158_CONFIG_L 0x2b55 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP157_TAP158_CONFIG 0x2b56 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP159_TAP160_CONFIG_H 0x2b57 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP159_TAP160_CONFIG_M 0x2b58 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP159_TAP160_CONFIG_L 0x2b59 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP159_TAP160_CONFIG 0x2b5a |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP161_TAP162_CONFIG_H 0x2b5b |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP161_TAP162_CONFIG_M 0x2b5c |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP161_TAP162_CONFIG_L 0x2b5d |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP161_TAP162_CONFIG 0x2b5e |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP163_TAP164_CONFIG_H 0x2b5f |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP163_TAP164_CONFIG_M 0x2b60 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP163_TAP164_CONFIG_L 0x2b61 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP163_TAP164_CONFIG 0x2b62 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP165_TAP166_CONFIG_H 0x2b63 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP165_TAP166_CONFIG_M 0x2b64 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP165_TAP166_CONFIG_L 0x2b65 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP165_TAP166_CONFIG 0x2b66 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP167_TAP168_CONFIG_H 0x2b67 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP167_TAP168_CONFIG_M 0x2b68 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP167_TAP168_CONFIG_L 0x2b69 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP167_TAP168_CONFIG 0x2b6a |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP169_TAP170_CONFIG_H 0x2b6b |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP169_TAP170_CONFIG_M 0x2b6c |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP169_TAP170_CONFIG_L 0x2b6d |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP169_TAP170_CONFIG 0x2b6e |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP171_TAP172_CONFIG_H 0x2b6f |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP171_TAP172_CONFIG_M 0x2b70 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP171_TAP172_CONFIG_L 0x2b71 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP171_TAP172_CONFIG 0x2b72 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP173_TAP174_CONFIG_H 0x2b73 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP173_TAP174_CONFIG_M 0x2b74 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP173_TAP174_CONFIG_L 0x2b75 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP173_TAP174_CONFIG 0x2b76 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP175_TAP176_CONFIG_H 0x2b77 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP175_TAP176_CONFIG_M 0x2b78 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP175_TAP176_CONFIG_L 0x2b79 |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP175_TAP176_CONFIG 0x2b7a |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP177_TAP178_CONFIG_H 0x2b7b |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP177_TAP178_CONFIG_M 0x2b7c |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP177_TAP178_CONFIG_L 0x2b7d |
| #define MT6338_AFE_ADDA_2ND_DL_SCF1_TAP177_TAP178_CONFIG 0x2b7e |
| #define MT6338_AUDIO_DIG_17TH_DSN_ID 0x2b80 |
| #define MT6338_AUDIO_DIG_17TH_DSN_ID_H 0x2b81 |
| #define MT6338_AUDIO_DIG_17TH_DSN_REV0 0x2b82 |
| #define MT6338_AUDIO_DIG_17TH_DSN_REV0_H 0x2b83 |
| #define MT6338_AUDIO_DIG_17TH_DSN_DBI 0x2b84 |
| #define MT6338_AUDIO_DIG_17TH_DSN_DBI_H 0x2b85 |
| #define MT6338_AUDIO_DIG_17TH_DSN_DXI 0x2b86 |
| #define MT6338_AUDIO_VAD_PBUF_MON_SEL 0x2b87 |
| #define MT6338_AUDIO_VAD_PBUF_MON_L 0x2b88 |
| #define MT6338_AUDIO_VAD_PBUF_MON_H 0x2b89 |
| #define MT6338_AUDIO_VAD_PBUF_CON0 0x2b8a |
| #define MT6338_AUDIO_VAD_PBUF_CON1 0x2b8b |
| #define MT6338_AUDIO_VAD_PBUF_CON2_L 0x2b8c |
| #define MT6338_AUDIO_VAD_PBUF_CON2_H 0x2b8d |
| #define MT6338_AUDIO_VAD_PBUF_CON3_L 0x2b8e |
| #define MT6338_AUDIO_VAD_PBUF_CON3_H 0x2b8f |
| #define MT6338_AUDIO_VAD_PBUF_CON4_L 0x2b90 |
| #define MT6338_AUDIO_VAD_PBUF_CON4_H 0x2b91 |
| #define MT6338_AUDIO_VAD_PBUF_CON5_L 0x2b92 |
| #define MT6338_AUDIO_VAD_PBUF_CON5_H 0x2b93 |
| #define MT6338_AUDIO_VAD_PBUF_CON6_L 0x2b94 |
| #define MT6338_AUDIO_VAD_PBUF_CON6_H 0x2b95 |
| #define MT6338_AUDIO_VAD_PBUF_WPTR_MON_L 0x2b96 |
| #define MT6338_AUDIO_VAD_PBUF_WPTR_MON_H 0x2b97 |
| #define MT6338_AUDIO_VAD_PBUF_RPTR_MON_L 0x2b98 |
| #define MT6338_AUDIO_VAD_PBUF_RPTR_MON_H 0x2b99 |
| #define MT6338_AUDIO_VAD_PBUF_RSV_L 0x2b9a |
| #define MT6338_AUDIO_VAD_PBUF_RSV_H 0x2b9b |
| #define MT6338_AFE_VOW_TOP_CON0 0x2b9c |
| #define MT6338_AFE_VOW_TOP_CON1 0x2b9d |
| #define MT6338_AFE_VOW_TOP_CON2 0x2b9e |
| #define MT6338_AFE_VOW_TOP_CON3 0x2b9f |
| #define MT6338_AFE_VOW_TOP_CON4 0x2ba0 |
| #define MT6338_AFE_VOW_TOP_CON5 0x2ba1 |
| #define MT6338_AFE_VOW_TOP_CON6 0x2ba2 |
| #define MT6338_AFE_VOW_TOP_CON7 0x2ba3 |
| #define MT6338_AFE_VOW_TOP_CON8 0x2ba4 |
| #define MT6338_AFE_VOW_TOP_CON9 0x2ba5 |
| #define MT6338_AFE_VOW_TOP_CON10 0x2ba6 |
| #define MT6338_AFE_VOW_TOP_CON11 0x2ba7 |
| #define MT6338_AFE_VOW_VAD_CFG0 0x2ba8 |
| #define MT6338_AFE_VOW_VAD_CFG1 0x2ba9 |
| #define MT6338_AFE_VOW_VAD_CFG2 0x2baa |
| #define MT6338_AFE_VOW_VAD_CFG3 0x2bab |
| #define MT6338_AFE_VOW_VAD_CFG4 0x2bac |
| #define MT6338_AFE_VOW_VAD_CFG5 0x2bad |
| #define MT6338_AFE_VOW_VAD_CFG6 0x2bae |
| #define MT6338_AFE_VOW_VAD_CFG7 0x2baf |
| #define MT6338_AFE_VOW_VAD_CFG8 0x2bb0 |
| #define MT6338_AFE_VOW_VAD_CFG9 0x2bb1 |
| #define MT6338_AFE_VOW_VAD_CFG10 0x2bb2 |
| #define MT6338_AFE_VOW_VAD_CFG11 0x2bb3 |
| #define MT6338_AFE_VOW_VAD_CFG12 0x2bb4 |
| #define MT6338_AFE_VOW_VAD_CFG13 0x2bb5 |
| #define MT6338_AFE_VOW_VAD_CFG14 0x2bb6 |
| #define MT6338_AFE_VOW_VAD_CFG15 0x2bb7 |
| #define MT6338_AFE_VOW_VAD_CFG16 0x2bb8 |
| #define MT6338_AFE_VOW_VAD_CFG17 0x2bb9 |
| #define MT6338_AFE_VOW_VAD_CFG18 0x2bba |
| #define MT6338_AFE_VOW_VAD_CFG19 0x2bbb |
| #define MT6338_AFE_VOW_VAD_CFG20 0x2bbc |
| #define MT6338_AFE_VOW_VAD_CFG21 0x2bbd |
| #define MT6338_AFE_VOW_VAD_CFG22 0x2bbe |
| #define MT6338_AFE_VOW_VAD_CFG23 0x2bbf |
| #define MT6338_AFE_VOW_VAD_CFG24 0x2bc0 |
| #define MT6338_AFE_VOW_VAD_CFG25 0x2bc1 |
| #define MT6338_AFE_VOW_VAD_CFG26 0x2bc2 |
| #define MT6338_AFE_VOW_VAD_CFG27 0x2bc3 |
| #define MT6338_AFE_VOW_VAD_CFG28 0x2bc4 |
| #define MT6338_AFE_VOW_VAD_CFG29 0x2bc5 |
| #define MT6338_AFE_VOW_VAD_CFG30 0x2bc6 |
| #define MT6338_AFE_VOW_VAD_CFG31 0x2bc7 |
| #define MT6338_AFE_VOW_VAD_CFG32 0x2bc8 |
| #define MT6338_AFE_VOW_VAD_CFG33 0x2bc9 |
| #define MT6338_AFE_VOW_VAD_CFG34 0x2bca |
| #define MT6338_AFE_VOW_VAD_CFG35 0x2bcb |
| #define MT6338_AFE_VOW_VAD_CFG36 0x2bcc |
| #define MT6338_AFE_VOW_VAD_CFG37 0x2bcd |
| #define MT6338_AFE_VOW_VAD_CFG38 0x2bce |
| #define MT6338_AFE_VOW_VAD_CFG39 0x2bcf |
| #define MT6338_AFE_VOW_VAD_CFG40 0x2bd0 |
| #define MT6338_AFE_VOW_VAD_CFG41 0x2bd1 |
| #define MT6338_AFE_VOW_VAD_CFG42 0x2bd2 |
| #define MT6338_AFE_VOW_VAD_CFG43 0x2bd3 |
| #define MT6338_AFE_VOW_VAD_CFG44 0x2bd4 |
| #define MT6338_AFE_VOW_VAD_CFG45 0x2bd5 |
| #define MT6338_AFE_VOW_VAD_CFG46 0x2bd6 |
| #define MT6338_AFE_VOW_VAD_CFG47 0x2bd7 |
| #define MT6338_AFE_VOW_VAD_CFG48 0x2bd8 |
| #define MT6338_AFE_VOW_VAD_CFG49 0x2bd9 |
| #define MT6338_AFE_VOW_VAD_CFG50 0x2bda |
| #define MT6338_AFE_VOW_VAD_CFG51 0x2bdb |
| #define MT6338_AFE_VOW_VAD_CFG52 0x2bdc |
| #define MT6338_AFE_VOW_VAD_CFG53 0x2bdd |
| #define MT6338_AFE_VOW_VAD_CFG54 0x2bde |
| #define MT6338_AFE_VOW_VAD_CFG55 0x2bdf |
| #define MT6338_AFE_VOW_VAD_CFG56 0x2be0 |
| #define MT6338_AFE_VOW_VAD_CFG57 0x2be1 |
| #define MT6338_AFE_VOW_VAD_CFG58 0x2be2 |
| #define MT6338_AFE_VOW_VAD_CFG59 0x2be3 |
| #define MT6338_AFE_VOW_VAD_CFG60 0x2be4 |
| #define MT6338_AFE_VOW_VAD_CFG61 0x2be5 |
| #define MT6338_AFE_VOW_VAD_CFG62 0x2be6 |
| #define MT6338_AFE_VOW_VAD_CFG63 0x2be7 |
| #define MT6338_AFE_VOW_VAD_CFG64 0x2be8 |
| #define MT6338_AFE_VOW_VAD_CFG65 0x2be9 |
| #define MT6338_AFE_VOW_TGEN_CFG0 0x2bea |
| #define MT6338_AFE_VOW_TGEN_CFG1 0x2beb |
| #define MT6338_AFE_VOW_TGEN_CFG2 0x2bec |
| #define MT6338_AFE_VOW_TGEN_CFG3 0x2bed |
| #define MT6338_AFE_VOW_TGEN_CFG4 0x2bee |
| #define MT6338_AFE_VOW_TGEN_CFG5 0x2bef |
| #define MT6338_AFE_VOW_TGEN_CFG6 0x2bf0 |
| #define MT6338_AFE_VOW_TGEN_CFG7 0x2bf1 |
| #define MT6338_AFE_VOW_HPF_CFG0 0x2bf2 |
| #define MT6338_AFE_VOW_HPF_CFG1 0x2bf3 |
| #define MT6338_AFE_VOW_HPF_CFG2 0x2bf4 |
| #define MT6338_AFE_VOW_HPF_CFG3 0x2bf5 |
| #define MT6338_AFE_VOW_HPF_CFG4 0x2bf6 |
| #define MT6338_AFE_VOW_HPF_CFG5 0x2bf7 |
| #define MT6338_AFE_VOW_HPF_CFG6 0x2bf8 |
| #define MT6338_AFE_VOW_HPF_CFG7 0x2bf9 |
| #define MT6338_AFE_VOW_INTR_CON 0x2bfa |
| #define MT6338_AUDIO_DIG_18TH_DSN_ID 0x2c00 |
| #define MT6338_AUDIO_DIG_18TH_DSN_ID_H 0x2c01 |
| #define MT6338_AUDIO_DIG_18TH_DSN_REV0 0x2c02 |
| #define MT6338_AUDIO_DIG_18TH_DSN_REV0_H 0x2c03 |
| #define MT6338_AUDIO_DIG_18TH_DSN_DBI 0x2c04 |
| #define MT6338_AUDIO_DIG_18TH_DSN_DBI_H 0x2c05 |
| #define MT6338_AUDIO_DIG_18TH_DSN_DXI 0x2c06 |
| #define MT6338_AUDIO_VOW_SRAM_L 0x2c07 |
| #define MT6338_AUDIO_VOW_SRAM_H 0x2c08 |
| #define MT6338_AUDIO_DIG_19TH_DSN_ID 0x2c80 |
| #define MT6338_AUDIO_DIG_19TH_DSN_ID_H 0x2c81 |
| #define MT6338_AUDIO_DIG_19TH_DSN_REV0 0x2c82 |
| #define MT6338_AUDIO_DIG_19TH_DSN_REV0_H 0x2c83 |
| #define MT6338_AUDIO_DIG_19TH_DSN_DBI 0x2c84 |
| #define MT6338_AUDIO_DIG_19TH_DSN_DBI_H 0x2c85 |
| #define MT6338_AUDIO_DIG_19TH_DSN_DXI 0x2c86 |
| #define MT6338_AFE_ADDA_MTKAIFV4_TX_CFG0 0x2c87 |
| #define MT6338_AFE_ADDA6_MTKAIFV4_TX_CFG0 0x2c88 |
| #define MT6338_AFE_MTKAIFV4_TX_CFG 0x2c89 |
| #define MT6338_AFE_ADDA_MTKAIFV4_RX_CFG0 0x2c8a |
| #define MT6338_AFE_ADDA_MTKAIFV4_RX_CFG1_0 0x2c8b |
| #define MT6338_AFE_ADDA_MTKAIFV4_RX_CFG1_1 0x2c8c |
| #define MT6338_AFE_ADDA_MTKAIFV4_RX_CFG1_2 0x2c8d |
| #define MT6338_AFE_ADDA_MTKAIFV4_RX_CFG1_3 0x2c8e |
| #define MT6338_AFE_ADDA6_MTKAIFV4_RX_CFG0 0x2c8f |
| #define MT6338_AFE_ADDA6_MTKAIFV4_RX_CFG1_0 0x2c90 |
| #define MT6338_AFE_ADDA6_MTKAIFV4_RX_CFG1_1 0x2c91 |
| #define MT6338_AFE_ADDA6_MTKAIFV4_RX_CFG1_2 0x2c92 |
| #define MT6338_AFE_ADDA6_MTKAIFV4_RX_CFG1_3 0x2c93 |
| #define MT6338_AFE_MTKAIFV4_RX_CFG 0x2c94 |
| #define MT6338_AFE_ADDA_MTKAIFV4_TX_SYNCWORD_CFG_0 0x2c95 |
| #define MT6338_AFE_ADDA_MTKAIFV4_TX_SYNCWORD_CFG_1 0x2c96 |
| #define MT6338_AFE_ADDA_MTKAIFV4_TX_SYNCWORD_CFG_2 0x2c97 |
| #define MT6338_AFE_ADDA_MTKAIFV4_TX_SYNCWORD_CFG_3 0x2c98 |
| #define MT6338_AFE_ADDA_MTKAIFV4_RX_SYNCWORD_CFG_0 0x2c99 |
| #define MT6338_AFE_ADDA_MTKAIFV4_RX_SYNCWORD_CFG_1 0x2c9a |
| #define MT6338_AFE_ADDA_MTKAIFV4_RX_SYNCWORD_CFG_2 0x2c9b |
| #define MT6338_AFE_ADDA_MTKAIFV4_RX_SYNCWORD_CFG_3 0x2c9c |
| #define MT6338_AFE_ADDA_MTKAIFV4_MON0 0x2c9d |
| #define MT6338_AFE_ADDA_MTKAIFV4_MON0_H 0x2c9e |
| #define MT6338_AFE_ADDA_MTKAIFV4_MON1_0 0x2c9f |
| #define MT6338_AFE_ADDA_MTKAIFV4_MON1_1 0x2ca0 |
| #define MT6338_AFE_ADDA_MTKAIFV4_MON1_2 0x2ca1 |
| #define MT6338_AFE_ADDA_MTKAIFV4_MON1_3 0x2ca2 |
| #define MT6338_AFE_ADDA6_MTKAIFV4_MON0 0x2ca3 |
| #define MT6338_AFE_ADDA6_MTKAIFV4_MON0_H 0x2ca4 |
| #define MT6338_AUDIO_DIG_20TH_DSN_ID 0x2d00 |
| #define MT6338_AUDIO_DIG_20TH_DSN_ID_H 0x2d01 |
| #define MT6338_AUDIO_DIG_20TH_DSN_REV0 0x2d02 |
| #define MT6338_AUDIO_DIG_20TH_DSN_REV0_H 0x2d03 |
| #define MT6338_AUDIO_DIG_20TH_DSN_DBI 0x2d04 |
| #define MT6338_AUDIO_DIG_20TH_DSN_DBI_H 0x2d05 |
| #define MT6338_AUDIO_DIG_20TH_DSN_DXI 0x2d06 |
| #define MT6338_ETDM_IN0_CON0_0 0x2d07 |
| #define MT6338_ETDM_IN0_CON0_1 0x2d08 |
| #define MT6338_ETDM_IN0_CON0_2 0x2d09 |
| #define MT6338_ETDM_IN0_CON0_3 0x2d0a |
| #define MT6338_ETDM_IN0_CON1_0 0x2d0b |
| #define MT6338_ETDM_IN0_CON1_1 0x2d0c |
| #define MT6338_ETDM_IN0_CON1_2 0x2d0d |
| #define MT6338_ETDM_IN0_CON1_3 0x2d0e |
| #define MT6338_ETDM_IN0_CON2_0 0x2d0f |
| #define MT6338_ETDM_IN0_CON2_1 0x2d10 |
| #define MT6338_ETDM_IN0_CON2_2 0x2d11 |
| #define MT6338_ETDM_IN0_CON2_3 0x2d12 |
| #define MT6338_ETDM_IN0_CON3_0 0x2d13 |
| #define MT6338_ETDM_IN0_CON3_1 0x2d14 |
| #define MT6338_ETDM_IN0_CON3_2 0x2d15 |
| #define MT6338_ETDM_IN0_CON3_3 0x2d16 |
| #define MT6338_ETDM_IN0_CON4_0 0x2d17 |
| #define MT6338_ETDM_IN0_CON4_1 0x2d18 |
| #define MT6338_ETDM_IN0_CON4_2 0x2d19 |
| #define MT6338_ETDM_IN0_CON4_3 0x2d1a |
| #define MT6338_ETDM_IN0_CON5_0 0x2d1b |
| #define MT6338_ETDM_IN0_CON5_1 0x2d1c |
| #define MT6338_ETDM_IN0_CON5_2 0x2d1d |
| #define MT6338_ETDM_IN0_CON5_3 0x2d1e |
| #define MT6338_ETDM_IN0_CON6_0 0x2d1f |
| #define MT6338_ETDM_IN0_CON6_1 0x2d20 |
| #define MT6338_ETDM_IN0_CON6_2 0x2d21 |
| #define MT6338_ETDM_IN0_CON6_3 0x2d22 |
| #define MT6338_ETDM_IN0_CON7_0 0x2d23 |
| #define MT6338_ETDM_IN0_CON7_1 0x2d24 |
| #define MT6338_ETDM_IN0_CON7_2 0x2d25 |
| #define MT6338_ETDM_IN0_CON7_3 0x2d26 |
| #define MT6338_ETDM_IN0_CON8_0 0x2d27 |
| #define MT6338_ETDM_IN0_CON8_1 0x2d28 |
| #define MT6338_ETDM_IN0_CON8_2 0x2d29 |
| #define MT6338_ETDM_IN0_CON8_3 0x2d2a |
| #define MT6338_ETDM_OUT0_CON0_0 0x2d2b |
| #define MT6338_ETDM_OUT0_CON0_1 0x2d2c |
| #define MT6338_ETDM_OUT0_CON0_2 0x2d2d |
| #define MT6338_ETDM_OUT0_CON0_3 0x2d2e |
| #define MT6338_ETDM_OUT0_CON1_0 0x2d2f |
| #define MT6338_ETDM_OUT0_CON1_1 0x2d30 |
| #define MT6338_ETDM_OUT0_CON1_2 0x2d31 |
| #define MT6338_ETDM_OUT0_CON1_3 0x2d32 |
| #define MT6338_ETDM_OUT0_CON2_0 0x2d33 |
| #define MT6338_ETDM_OUT0_CON2_1 0x2d34 |
| #define MT6338_ETDM_OUT0_CON2_2 0x2d35 |
| #define MT6338_ETDM_OUT0_CON2_3 0x2d36 |
| #define MT6338_ETDM_OUT0_CON3_0 0x2d37 |
| #define MT6338_ETDM_OUT0_CON3_1 0x2d38 |
| #define MT6338_ETDM_OUT0_CON3_2 0x2d39 |
| #define MT6338_ETDM_OUT0_CON3_3 0x2d3a |
| #define MT6338_ETDM_OUT0_CON4_0 0x2d3b |
| #define MT6338_ETDM_OUT0_CON4_1 0x2d3c |
| #define MT6338_ETDM_OUT0_CON4_2 0x2d3d |
| #define MT6338_ETDM_OUT0_CON4_3 0x2d3e |
| #define MT6338_ETDM_OUT0_CON5_0 0x2d3f |
| #define MT6338_ETDM_OUT0_CON5_1 0x2d40 |
| #define MT6338_ETDM_OUT0_CON5_2 0x2d41 |
| #define MT6338_ETDM_OUT0_CON5_3 0x2d42 |
| #define MT6338_ETDM_OUT0_CON6_0 0x2d43 |
| #define MT6338_ETDM_OUT0_CON6_1 0x2d44 |
| #define MT6338_ETDM_OUT0_CON6_2 0x2d45 |
| #define MT6338_ETDM_OUT0_CON6_3 0x2d46 |
| #define MT6338_ETDM_OUT0_CON7_0 0x2d47 |
| #define MT6338_ETDM_OUT0_CON7_1 0x2d48 |
| #define MT6338_ETDM_OUT0_CON7_2 0x2d49 |
| #define MT6338_ETDM_OUT0_CON7_3 0x2d4a |
| #define MT6338_ETDM_OUT0_CON8_0 0x2d4b |
| #define MT6338_ETDM_OUT0_CON8_1 0x2d4c |
| #define MT6338_ETDM_OUT0_CON8_2 0x2d4d |
| #define MT6338_ETDM_OUT0_CON8_3 0x2d4e |
| #define MT6338_ETDM_OUT0_CON9_0 0x2d4f |
| #define MT6338_ETDM_OUT0_CON9_1 0x2d50 |
| #define MT6338_ETDM_OUT0_CON9_2 0x2d51 |
| #define MT6338_ETDM_OUT0_CON9_3 0x2d52 |
| #define MT6338_ETDM_0_3_COWORK_CON0_0 0x2d53 |
| #define MT6338_ETDM_0_3_COWORK_CON0_1 0x2d54 |
| #define MT6338_ETDM_0_3_COWORK_CON0_2 0x2d55 |
| #define MT6338_ETDM_0_3_COWORK_CON0_3 0x2d56 |
| #define MT6338_ETDM_0_3_COWORK_CON1_0 0x2d57 |
| #define MT6338_ETDM_0_3_COWORK_CON1_1 0x2d58 |
| #define MT6338_ETDM_0_3_COWORK_CON1_2 0x2d59 |
| #define MT6338_ETDM_0_3_COWORK_CON1_3 0x2d5a |
| #define MT6338_ETDM_IN0_MON_0 0x2d5b |
| #define MT6338_ETDM_IN1_MON_1 0x2d5c |
| #define MT6338_ETDM_IN2_MON_2 0x2d5d |
| #define MT6338_ETDM_IN3_MON_3 0x2d5e |
| #define MT6338_ETDM_OUT0_MON_0 0x2d5f |
| #define MT6338_ETDM_OUT1_MON_1 0x2d60 |
| #define MT6338_ETDM_OUT2_MON_2 0x2d61 |
| #define MT6338_ETDM_OUT3_MON_3 0x2d62 |
| #define MT6338_AUDIO_DIG_21TH_DSN_ID 0x2d80 |
| #define MT6338_AUDIO_DIG_21TH_DSN_ID_H 0x2d81 |
| #define MT6338_AUDIO_DIG_21TH_DSN_REV0 0x2d82 |
| #define MT6338_AUDIO_DIG_21TH_DSN_REV0_H 0x2d83 |
| #define MT6338_AUDIO_DIG_21TH_DSN_DBI 0x2d84 |
| #define MT6338_AUDIO_DIG_21TH_DSN_DBI_H 0x2d85 |
| #define MT6338_AUDIO_DIG_21TH_DSN_DXI 0x2d86 |
| #define MT6338_AFE_GAIN1_CON0_1 0x2d87 |
| #define MT6338_AFE_GAIN1_CON0_0 0x2d88 |
| #define MT6338_AFE_GAIN1_CON1_3 0x2d89 |
| #define MT6338_AFE_GAIN1_CON1_2 0x2d8a |
| #define MT6338_AFE_GAIN1_CON1_1 0x2d8b |
| #define MT6338_AFE_GAIN1_CON1_0 0x2d8c |
| #define MT6338_AFE_GAIN1_CON2_2 0x2d8d |
| #define MT6338_AFE_GAIN1_CON2_1 0x2d8e |
| #define MT6338_AFE_GAIN1_CON2_0 0x2d8f |
| #define MT6338_AFE_GAIN1_CON3_2 0x2d90 |
| #define MT6338_AFE_GAIN1_CON3_1 0x2d91 |
| #define MT6338_AFE_GAIN1_CON3_0 0x2d92 |
| #define MT6338_AFE_GAIN1_CUR_3 0x2d93 |
| #define MT6338_AFE_GAIN1_CUR_2 0x2d94 |
| #define MT6338_AFE_GAIN1_CUR_1 0x2d95 |
| #define MT6338_AFE_GAIN1_CUR_0 0x2d96 |
| #define MT6338_AFE_GAIN1_CUR_PRE_3 0x2d97 |
| #define MT6338_AFE_GAIN1_CUR_PRE_2 0x2d98 |
| #define MT6338_AFE_GAIN1_CUR_PRE_1 0x2d99 |
| #define MT6338_AFE_GAIN1_CUR_PRE_0 0x2d9a |
| #define MT6338_AFE_GAIN2_CON0_1 0x2d9b |
| #define MT6338_AFE_GAIN2_CON0_0 0x2d9c |
| #define MT6338_AFE_GAIN2_CON1_3 0x2d9d |
| #define MT6338_AFE_GAIN2_CON1_2 0x2d9e |
| #define MT6338_AFE_GAIN2_CON1_1 0x2d9f |
| #define MT6338_AFE_GAIN2_CON1_0 0x2da0 |
| #define MT6338_AFE_GAIN2_CON2_2 0x2da1 |
| #define MT6338_AFE_GAIN2_CON2_1 0x2da2 |
| #define MT6338_AFE_GAIN2_CON2_0 0x2da3 |
| #define MT6338_AFE_GAIN2_CON3_2 0x2da4 |
| #define MT6338_AFE_GAIN2_CON3_1 0x2da5 |
| #define MT6338_AFE_GAIN2_CON3_0 0x2da6 |
| #define MT6338_AFE_GAIN2_CUR_3 0x2da7 |
| #define MT6338_AFE_GAIN2_CUR_2 0x2da8 |
| #define MT6338_AFE_GAIN2_CUR_1 0x2da9 |
| #define MT6338_AFE_GAIN2_CUR_0 0x2daa |
| #define MT6338_AFE_GAIN2_CUR_PRE_3 0x2dab |
| #define MT6338_AFE_GAIN2_CUR_PRE_2 0x2dac |
| #define MT6338_AFE_GAIN2_CUR_PRE_1 0x2dad |
| #define MT6338_AFE_GAIN2_CUR_PRE_0 0x2dae |
| #define MT6338_AUDIO_DIG_22TH_DSN_ID 0x2e00 |
| #define MT6338_AUDIO_DIG_22TH_DSN_ID_H 0x2e01 |
| #define MT6338_AUDIO_DIG_22TH_DSN_REV0 0x2e02 |
| #define MT6338_AUDIO_DIG_22TH_DSN_REV0_H 0x2e03 |
| #define MT6338_AUDIO_DIG_22TH_DSN_DBI 0x2e04 |
| #define MT6338_AUDIO_DIG_22TH_DSN_DBI_H 0x2e05 |
| #define MT6338_AUDIO_DIG_22TH_DSN_DXI 0x2e06 |
| #define MT6338_AFE_VOW_VAD_MON0 0x2e07 |
| #define MT6338_AFE_VOW_VAD_MON1 0x2e08 |
| #define MT6338_AFE_VOW_VAD_MON2 0x2e09 |
| #define MT6338_AFE_VOW_VAD_MON3 0x2e0a |
| #define MT6338_AFE_VOW_VAD_MON4 0x2e0b |
| #define MT6338_AFE_VOW_VAD_MON5 0x2e0c |
| #define MT6338_AFE_VOW_VAD_MON6 0x2e0d |
| #define MT6338_AFE_VOW_VAD_MON7 0x2e0e |
| #define MT6338_AFE_VOW_VAD_MON8 0x2e0f |
| #define MT6338_AFE_VOW_VAD_MON9 0x2e10 |
| #define MT6338_AFE_VOW_VAD_MON10 0x2e11 |
| #define MT6338_AFE_VOW_VAD_MON11 0x2e12 |
| #define MT6338_AFE_VOW_VAD_MON12 0x2e13 |
| #define MT6338_AFE_VOW_VAD_MON13 0x2e14 |
| #define MT6338_AFE_VOW_VAD_MON14 0x2e15 |
| #define MT6338_AFE_VOW_VAD_MON15 0x2e16 |
| #define MT6338_AFE_VOW_VAD_MON16 0x2e17 |
| #define MT6338_AFE_VOW_VAD_MON17 0x2e18 |
| #define MT6338_AFE_VOW_VAD_MON18 0x2e19 |
| #define MT6338_AFE_VOW_VAD_MON19 0x2e1a |
| #define MT6338_AFE_VOW_VAD_MON20 0x2e1b |
| #define MT6338_AFE_VOW_VAD_MON21 0x2e1c |
| #define MT6338_AFE_VOW_VAD_MON22 0x2e1d |
| #define MT6338_AFE_VOW_VAD_MON23 0x2e1e |
| #define MT6338_AFE_VOW_VAD_MON24 0x2e1f |
| #define MT6338_AFE_VOW_VAD_MON25 0x2e20 |
| #define MT6338_AFE_VOW_VAD_MON26 0x2e21 |
| #define MT6338_AFE_VOW_VAD_MON27 0x2e22 |
| #define MT6338_AFE_VOW_VAD_MON28 0x2e23 |
| #define MT6338_AFE_VOW_VAD_MON29 0x2e24 |
| #define MT6338_AFE_VOW_VAD_MON30 0x2e25 |
| #define MT6338_AFE_VOW_VAD_MON31 0x2e26 |
| #define MT6338_AFE_VOW_VAD_MON32 0x2e27 |
| #define MT6338_AFE_VOW_VAD_MON33 0x2e28 |
| #define MT6338_AFE_VOW_VAD_MON34 0x2e29 |
| #define MT6338_AFE_VOW_VAD_MON35 0x2e2a |
| #define MT6338_AFE_VOW_VAD_MON36 0x2e2b |
| #define MT6338_AFE_VOW_VAD_MON37 0x2e2c |
| #define MT6338_AFE_VOW_VAD_MON38 0x2e2d |
| #define MT6338_AFE_VOW_VAD_MON39 0x2e2e |
| #define MT6338_AFE_VOW_VAD_MON40 0x2e2f |
| #define MT6338_AFE_VOW_VAD_MON41 0x2e30 |
| #define MT6338_AFE_VOW_VAD_MON42 0x2e31 |
| #define MT6338_AFE_VOW_VAD_MON43 0x2e32 |
| #define MT6338_AFE_VOW_VAD_MON44 0x2e33 |
| #define MT6338_AFE_VOW_VAD_MON45 0x2e34 |
| #define MT6338_AFE_VOW_VAD_MON46 0x2e35 |
| #define MT6338_AFE_VOW_VAD_MON47 0x2e36 |
| #define MT6338_AUDENC_ANA_ID 0x2e80 |
| #define MT6338_AUDENC_DIG_ID 0x2e81 |
| #define MT6338_AUDENC_ANA_REV 0x2e82 |
| #define MT6338_AUDENC_DIG_REV 0x2e83 |
| #define MT6338_AUDENC_DBI 0x2e84 |
| #define MT6338_AUDENC_ESP 0x2e85 |
| #define MT6338_AUDENC_FPI 0x2e86 |
| #define MT6338_AUDENC_DXI 0x2e87 |
| #define MT6338_AUDENC_PMU_CON0 0x2e88 |
| #define MT6338_AUDENC_PMU_CON1 0x2e89 |
| #define MT6338_AUDENC_PMU_CON2 0x2e8a |
| #define MT6338_AUDENC_PMU_CON3 0x2e8b |
| #define MT6338_AUDENC_PMU_CON4 0x2e8c |
| #define MT6338_AUDENC_PMU_CON5 0x2e8d |
| #define MT6338_AUDENC_PMU_CON6 0x2e8e |
| #define MT6338_AUDENC_PMU_CON7 0x2e8f |
| #define MT6338_AUDENC_PMU_CON8 0x2e90 |
| #define MT6338_AUDENC_PMU_CON9 0x2e91 |
| #define MT6338_AUDENC_PMU_CON10 0x2e92 |
| #define MT6338_AUDENC_PMU_CON11 0x2e93 |
| #define MT6338_AUDENC_PMU_CON12 0x2e94 |
| #define MT6338_AUDENC_PMU_CON13 0x2e95 |
| #define MT6338_AUDENC_PMU_CON14 0x2e96 |
| #define MT6338_AUDENC_PMU_CON15 0x2e97 |
| #define MT6338_AUDENC_PMU_CON16 0x2e98 |
| #define MT6338_AUDENC_PMU_CON17 0x2e99 |
| #define MT6338_AUDENC_PMU_CON18 0x2e9a |
| #define MT6338_AUDENC_PMU_CON19 0x2e9b |
| #define MT6338_AUDENC_PMU_CON20 0x2e9c |
| #define MT6338_AUDENC_PMU_CON21 0x2e9d |
| #define MT6338_AUDENC_PMU_CON22 0x2e9e |
| #define MT6338_AUDENC_PMU_CON23 0x2e9f |
| #define MT6338_AUDENC_PMU_CON24 0x2ea0 |
| #define MT6338_AUDENC_PMU_CON25 0x2ea1 |
| #define MT6338_AUDENC_PMU_CON26 0x2ea2 |
| #define MT6338_AUDENC_PMU_CON27 0x2ea3 |
| #define MT6338_AUDENC_PMU_CON28 0x2ea4 |
| #define MT6338_AUDENC_PMU_CON29 0x2ea5 |
| #define MT6338_AUDENC_PMU_CON30 0x2ea6 |
| #define MT6338_AUDENC_PMU_CON31 0x2ea7 |
| #define MT6338_AUDENC_PMU_CON32 0x2ea8 |
| #define MT6338_AUDENC_PMU_CON33 0x2ea9 |
| #define MT6338_AUDENC_PMU_CON34 0x2eaa |
| #define MT6338_AUDENC_PMU_CON35 0x2eab |
| #define MT6338_AUDENC_PMU_CON36 0x2eac |
| #define MT6338_AUDENC_PMU_CON37 0x2ead |
| #define MT6338_AUDENC_PMU_CON38 0x2eae |
| #define MT6338_AUDENC_PMU_CON39 0x2eaf |
| #define MT6338_AUDENC_PMU_CON40 0x2eb0 |
| #define MT6338_AUDENC_PMU_CON41 0x2eb1 |
| #define MT6338_AUDENC_PMU_CON42 0x2eb2 |
| #define MT6338_AUDENC_PMU_CON43 0x2eb3 |
| #define MT6338_AUDENC_PMU_CON44 0x2eb4 |
| #define MT6338_AUDENC_PMU_CON45 0x2eb5 |
| #define MT6338_AUDENC_PMU_CON46 0x2eb6 |
| #define MT6338_AUDENC_PMU_CON47 0x2eb7 |
| #define MT6338_AUDENC_PMU_CON48 0x2eb8 |
| #define MT6338_AUDENC_PMU_CON49 0x2eb9 |
| #define MT6338_AUDENC_PMU_CON50 0x2eba |
| #define MT6338_AUDENC_PMU_CON51 0x2ebb |
| #define MT6338_AUDENC_PMU_CON52 0x2ebc |
| #define MT6338_AUDENC_PMU_CON53 0x2ebd |
| #define MT6338_AUDENC_PMU_CON54 0x2ebe |
| #define MT6338_AUDENC_PMU_CON55 0x2ebf |
| #define MT6338_AUDENC_PMU_CON56 0x2ec0 |
| #define MT6338_AUDENC_PMU_CON57 0x2ec1 |
| #define MT6338_AUDENC_PMU_CON58 0x2ec2 |
| #define MT6338_AUDENC_PMU_CON59 0x2ec3 |
| #define MT6338_AUDENC_PMU_CON60 0x2ec4 |
| #define MT6338_AUDENC_PMU_CON61 0x2ec5 |
| #define MT6338_AUDENC_PMU_CON62 0x2ec6 |
| #define MT6338_AUDENC_PMU_CON63 0x2ec7 |
| #define MT6338_AUDENC_PMU_CON64 0x2ec8 |
| #define MT6338_AUDENC_PMU_CON65 0x2ec9 |
| #define MT6338_AUDENC_PMU_CON66 0x2eca |
| #define MT6338_AUDENC_PMU_CON67 0x2ecb |
| #define MT6338_AUDENC_PMU_CON68 0x2ecc |
| #define MT6338_AUDENC_PMU_CON69 0x2ecd |
| #define MT6338_AUDENC_PMU_CON70 0x2ece |
| #define MT6338_AUDENC_PMU_CON71 0x2ecf |
| #define MT6338_AUDENC_PMU_CON72 0x2ed0 |
| #define MT6338_AUDENC_PMU_CON73 0x2ed1 |
| #define MT6338_AUDENC_PMU_CON74 0x2ed2 |
| #define MT6338_AUDENC_PMU_CON75 0x2ed3 |
| #define MT6338_AUDENC_PMU_CON76 0x2ed4 |
| #define MT6338_AUDENC_PMU_CON77 0x2ed5 |
| #define MT6338_AUDENC_PMU_CON78 0x2ed6 |
| #define MT6338_AUDENC_PMU_CON79 0x2ed7 |
| #define MT6338_AUDENC_PMU_CON80 0x2ed8 |
| #define MT6338_AUDENC_PMU_CON81 0x2ed9 |
| #define MT6338_AUDENC_2_PMU_CON0 0x2eda |
| #define MT6338_AUDENC_2_PMU_CON1 0x2edb |
| #define MT6338_AUDENC_2_PMU_CON2 0x2edc |
| #define MT6338_AUDENC_2_PMU_CON3 0x2edd |
| #define MT6338_AUDENC_2_PMU_CON4 0x2ede |
| #define MT6338_AUDENC_2_PMU_CON5 0x2edf |
| #define MT6338_AUDENC_2_PMU_CON6 0x2ee0 |
| #define MT6338_AUDENC_2_PMU_CON7 0x2ee1 |
| #define MT6338_AUDENC_2_PMU_CON8 0x2ee2 |
| #define MT6338_AUDENC_2_PMU_CON9 0x2ee3 |
| #define MT6338_AUDENC_2_PMU_CON10 0x2ee4 |
| #define MT6338_AUDENC_2_PMU_CON11 0x2ee5 |
| #define MT6338_AUDENC_2_PMU_CON12 0x2ee6 |
| #define MT6338_AUDENC_2_PMU_CON13 0x2ee7 |
| #define MT6338_AUDENC_ELR_NUM 0x2ee8 |
| #define MT6338_AUDENC_ELR_0 0x2ee9 |
| #define MT6338_AUDENC_ELR_1 0x2eea |
| #define MT6338_AUDENC_ELR_2 0x2eeb |
| #define MT6338_AUDENC_ELR_3 0x2eec |
| #define MT6338_AUDENC_ELR_4 0x2eed |
| #define MT6338_AUDDEC_ANA_ID 0x2f00 |
| #define MT6338_AUDDEC_DIG_ID 0x2f01 |
| #define MT6338_AUDDEC_ANA_REV 0x2f02 |
| #define MT6338_AUDDEC_DIG_REV 0x2f03 |
| #define MT6338_AUDDEC_DBI 0x2f04 |
| #define MT6338_AUDDEC_ESP 0x2f05 |
| #define MT6338_AUDDEC_FPI 0x2f06 |
| #define MT6338_AUDDEC_DXI 0x2f07 |
| #define MT6338_AUDDEC_PMU_CON0 0x2f08 |
| #define MT6338_AUDDEC_PMU_CON1 0x2f09 |
| #define MT6338_AUDDEC_PMU_CON2 0x2f0a |
| #define MT6338_AUDDEC_PMU_CON3 0x2f0b |
| #define MT6338_AUDDEC_PMU_CON4 0x2f0c |
| #define MT6338_AUDDEC_PMU_CON5 0x2f0d |
| #define MT6338_AUDDEC_PMU_CON6 0x2f0e |
| #define MT6338_AUDDEC_PMU_CON7 0x2f0f |
| #define MT6338_AUDDEC_PMU_CON8 0x2f10 |
| #define MT6338_AUDDEC_PMU_CON9 0x2f11 |
| #define MT6338_AUDDEC_PMU_CON10 0x2f12 |
| #define MT6338_AUDDEC_PMU_CON11 0x2f13 |
| #define MT6338_AUDDEC_PMU_CON12 0x2f14 |
| #define MT6338_AUDDEC_PMU_CON13 0x2f15 |
| #define MT6338_AUDDEC_PMU_CON14 0x2f16 |
| #define MT6338_AUDDEC_PMU_CON15 0x2f17 |
| #define MT6338_AUDDEC_PMU_CON16 0x2f18 |
| #define MT6338_AUDDEC_PMU_CON17 0x2f19 |
| #define MT6338_AUDDEC_PMU_CON18 0x2f1a |
| #define MT6338_AUDDEC_PMU_CON19 0x2f1b |
| #define MT6338_AUDDEC_PMU_CON20 0x2f1c |
| #define MT6338_AUDDEC_PMU_CON21 0x2f1d |
| #define MT6338_AUDDEC_PMU_CON22 0x2f1e |
| #define MT6338_AUDDEC_PMU_CON23 0x2f1f |
| #define MT6338_AUDDEC_PMU_CON24 0x2f20 |
| #define MT6338_AUDDEC_PMU_CON25 0x2f21 |
| #define MT6338_AUDDEC_PMU_CON26 0x2f22 |
| #define MT6338_AUDDEC_PMU_CON27 0x2f23 |
| #define MT6338_AUDDEC_PMU_CON28 0x2f24 |
| #define MT6338_AUDDEC_PMU_CON29 0x2f25 |
| #define MT6338_AUDDEC_PMU_CON30 0x2f26 |
| #define MT6338_AUDDEC_PMU_CON31 0x2f27 |
| #define MT6338_AUDDEC_PMU_CON32 0x2f28 |
| #define MT6338_AUDDEC_PMU_CON33 0x2f29 |
| #define MT6338_AUDDEC_PMU_CON34 0x2f2a |
| #define MT6338_AUDDEC_PMU_CON35 0x2f2b |
| #define MT6338_AUDDEC_PMU_CON36 0x2f2c |
| #define MT6338_AUDDEC_PMU_CON37 0x2f2d |
| #define MT6338_AUDDEC_PMU_CON38 0x2f2e |
| #define MT6338_AUDDEC_PMU_CON39 0x2f2f |
| #define MT6338_AUDDEC_PMU_CON40 0x2f30 |
| #define MT6338_AUDDEC_PMU_CON41 0x2f31 |
| #define MT6338_AUDDEC_PMU_CON42 0x2f32 |
| #define MT6338_AUDDEC_PMU_CON43 0x2f33 |
| #define MT6338_AUDDEC_PMU_CON44 0x2f34 |
| #define MT6338_AUDDEC_PMU_CON45 0x2f35 |
| #define MT6338_AUDDEC_PMU_CON46 0x2f36 |
| #define MT6338_AUDDEC_PMU_CON47 0x2f37 |
| #define MT6338_AUDDEC_PMU_CON48 0x2f38 |
| #define MT6338_AUDDEC_PMU_CON49 0x2f39 |
| #define MT6338_AUDDEC_2_PMU_CON0 0x2f3a |
| #define MT6338_AUDDEC_2_PMU_CON1 0x2f3b |
| #define MT6338_AUDDEC_2_PMU_CON2 0x2f3c |
| #define MT6338_AUDDEC_2_PMU_CON3 0x2f3d |
| #define MT6338_AUDDEC_2_PMU_CON4 0x2f3e |
| #define MT6338_AUDDEC_2_PMU_CON5 0x2f3f |
| #define MT6338_AUDDEC_2_PMU_CON6 0x2f40 |
| #define MT6338_AUDDEC_2_PMU_CON7 0x2f41 |
| #define MT6338_AUDDEC_2_PMU_CON8 0x2f42 |
| #define MT6338_AUDDEC_2_PMU_CON9 0x2f43 |
| #define MT6338_AUDDEC_2_PMU_CON10 0x2f44 |
| #define MT6338_AUDDEC_2_PMU_CON11 0x2f45 |
| #define MT6338_AUDDEC_2_PMU_CON12 0x2f46 |
| #define MT6338_AUDZCD_DSN_ID 0x2f80 |
| #define MT6338_AUDZCD_DSN_ID_H 0x2f81 |
| #define MT6338_AUDZCD_DSN_REV0 0x2f82 |
| #define MT6338_AUDZCD_DSN_REV0_H 0x2f83 |
| #define MT6338_AUDZCD_DSN_DBI 0x2f84 |
| #define MT6338_AUDZCD_DSN_DBI_H 0x2f85 |
| #define MT6338_AUDZCD_DSN_FPI 0x2f86 |
| #define MT6338_ZCD_CON0 0x2f87 |
| #define MT6338_ZCD_CON1 0x2f88 |
| #define MT6338_ZCD_CON1_H 0x2f89 |
| #define MT6338_ZCD_CON2 0x2f8a |
| #define MT6338_ZCD_CON2_H 0x2f8b |
| #define MT6338_ZCD_CON3 0x2f8c |
| #define MT6338_ZCD_CON4 0x2f8d |
| #define MT6338_ZCD_CON4_H 0x2f8e |
| #define MT6338_ZCD_CON5 0x2f8f |
| #define MT6338_ZCD_CON5_H 0x2f90 |
| #define MT6338_ACCDET_DSN_DIG_ID 0x3000 |
| #define MT6338_ACCDET_DSN_DIG_ID_H 0x3001 |
| #define MT6338_ACCDET_DSN_DIG_REV0 0x3002 |
| #define MT6338_ACCDET_DSN_DIG_REV0_H 0x3003 |
| #define MT6338_ACCDET_DSN_DBI 0x3004 |
| #define MT6338_ACCDET_DSN_DBI_H 0x3005 |
| #define MT6338_ACCDET_DSN_FPI 0x3006 |
| #define MT6338_ACCDET_CON0_L 0x3007 |
| #define MT6338_ACCDET_CON0_H 0x3008 |
| #define MT6338_ACCDET_CON1_L 0x3009 |
| #define MT6338_ACCDET_CON1_H 0x300a |
| #define MT6338_ACCDET_CON2_L 0x300b |
| #define MT6338_ACCDET_CON2_H 0x300c |
| #define MT6338_ACCDET_CON3_L 0x300d |
| #define MT6338_ACCDET_CON3_H 0x300e |
| #define MT6338_ACCDET_CON4_L 0x300f |
| #define MT6338_ACCDET_CON4_H 0x3010 |
| #define MT6338_ACCDET_CON5_L 0x3011 |
| #define MT6338_ACCDET_CON5_H 0x3012 |
| #define MT6338_ACCDET_CON6 0x3013 |
| #define MT6338_ACCDET_CON7_L 0x3014 |
| #define MT6338_ACCDET_CON7_H 0x3015 |
| #define MT6338_ACCDET_CON8_L 0x3016 |
| #define MT6338_ACCDET_CON8_H 0x3017 |
| #define MT6338_ACCDET_CON9_L 0x3018 |
| #define MT6338_ACCDET_CON9_H 0x3019 |
| #define MT6338_ACCDET_CON10_L 0x301a |
| #define MT6338_ACCDET_CON10_H 0x301b |
| #define MT6338_ACCDET_CON11_L 0x301c |
| #define MT6338_ACCDET_CON11_H 0x301d |
| #define MT6338_ACCDET_CON12_L 0x301e |
| #define MT6338_ACCDET_CON12_H 0x301f |
| #define MT6338_ACCDET_CON13_L 0x3020 |
| #define MT6338_ACCDET_CON13_H 0x3021 |
| #define MT6338_ACCDET_CON14_L 0x3022 |
| #define MT6338_ACCDET_CON14_H 0x3023 |
| #define MT6338_ACCDET_CON15 0x3024 |
| #define MT6338_ACCDET_CON16_L 0x3025 |
| #define MT6338_ACCDET_CON16_H 0x3026 |
| #define MT6338_ACCDET_CON17 0x3027 |
| #define MT6338_ACCDET_CON18_L 0x3028 |
| #define MT6338_ACCDET_CON18_H 0x3029 |
| #define MT6338_ACCDET_CON19_L 0x302a |
| #define MT6338_ACCDET_CON19_H 0x302b |
| #define MT6338_ACCDET_CON20_L 0x302c |
| #define MT6338_ACCDET_CON20_H 0x302d |
| #define MT6338_ACCDET_CON21_L 0x302e |
| #define MT6338_ACCDET_CON21_H 0x302f |
| #define MT6338_ACCDET_CON22_L 0x3030 |
| #define MT6338_ACCDET_CON22_H 0x3031 |
| #define MT6338_ACCDET_CON23_L 0x3032 |
| #define MT6338_ACCDET_CON23_H 0x3033 |
| #define MT6338_ACCDET_CON24 0x3034 |
| #define MT6338_ACCDET_CON25_L 0x3035 |
| #define MT6338_ACCDET_CON25_H 0x3036 |
| #define MT6338_ACCDET_CON26_L 0x3037 |
| #define MT6338_ACCDET_CON26_H 0x3038 |
| #define MT6338_ACCDET_CON27_L 0x3039 |
| #define MT6338_ACCDET_CON27_H 0x303a |
| #define MT6338_ACCDET_CON28_L 0x303b |
| #define MT6338_ACCDET_CON28_H 0x303c |
| #define MT6338_ACCDET_CON29_L 0x303d |
| #define MT6338_ACCDET_CON29_H 0x303e |
| #define MT6338_ACCDET_CON30_L 0x303f |
| #define MT6338_ACCDET_CON30_H 0x3040 |
| #define MT6338_ACCDET_CON31_L 0x3041 |
| #define MT6338_ACCDET_CON31_H 0x3042 |
| #define MT6338_ACCDET_CON32_L 0x3043 |
| #define MT6338_ACCDET_CON32_H 0x3044 |
| #define MT6338_ACCDET_CON33_L 0x3045 |
| #define MT6338_ACCDET_CON33_H 0x3046 |
| #define MT6338_ACCDET_CON34_L 0x3047 |
| #define MT6338_ACCDET_CON34_H 0x3048 |
| #define MT6338_ACCDET_CON35_L 0x3049 |
| #define MT6338_ACCDET_CON35_H 0x304a |
| #define MT6338_ACCDET_CON36 0x304b |
| #define MT6338_ACCDET_CON37 0x304c |
| #define MT6338_ACCDET_CON38_L 0x304d |
| #define MT6338_ACCDET_CON38_H 0x304e |
| #define MT6338_ACCDET_CON39 0x304f |
| #define MT6338_ACCDET_CON40 0x3050 |
| //mask is HEX; shift is Integer |
| |
| /* TOP_CKPDN_CON1 */ |
| #define RG_AUD_208M_CK_PDN_SFT 7 |
| #define RG_AUD_208M_CK_PDN_MASK 0x1 |
| #define RG_AUD_208M_CK_PDN_MASK_SFT (0x1 << 7) |
| #define RG_AUD_13M_CK_PDN_SFT 6 |
| #define RG_AUD_13M_CK_PDN_MASK 0x1 |
| #define RG_AUD_13M_CK_PDN_MASK_SFT (0x1 << 6) |
| #define RG_AUD_26M_CK_PDN_SFT 5 |
| #define RG_AUD_26M_CK_PDN_MASK 0x1 |
| #define RG_AUD_26M_CK_PDN_MASK_SFT (0x1 << 5) |
| #define RG_OSC_1M_CK_PDN_SFT 4 |
| #define RG_OSC_1M_CK_PDN_MASK 0x1 |
| #define RG_OSC_1M_CK_PDN_MASK_SFT (0x1 << 4) |
| #define RG_OSC_13M_CK_PDN_SFT 3 |
| #define RG_OSC_13M_CK_PDN_MASK 0x1 |
| #define RG_OSC_13M_CK_PDN_MASK_SFT (0x1 << 3) |
| #define RG_OSC_26M_CK_PDN_SFT 2 |
| #define RG_OSC_26M_CK_PDN_MASK 0x1 |
| #define RG_OSC_26M_CK_PDN_MASK_SFT (0x1 << 2) |
| #define RG_OSC_37P5K_CK_PDN_SFT 1 |
| #define RG_OSC_37P5K_CK_PDN_MASK 0x1 |
| #define RG_OSC_37P5K_CK_PDN_MASK_SFT (0x1 << 1) |
| #define RG_OSC_75K_CK_PDN_SFT 0 |
| #define RG_OSC_75K_CK_PDN_MASK 0x1 |
| #define RG_OSC_75K_CK_PDN_MASK_SFT (0x1 << 0) |
| |
| /* TOP_CKTST_CON0 */ |
| #define TOP_CKTST_CON0_RSV_SFT 5 |
| #define TOP_CKTST_CON0_RSV_MASK 0x7 |
| #define TOP_CKTST_CON0_RSV_MASK_SFT (0x7 << 5) |
| #define RG_AUD_13M_CK_TST_DIS_SFT 4 |
| #define RG_AUD_13M_CK_TST_DIS_MASK 0x1 |
| #define RG_AUD_13M_CK_TST_DIS_MASK_SFT (0x1 << 4) |
| #define RG_VCORE_26M_CK_TST_DIS_SFT 3 |
| #define RG_VCORE_26M_CK_TST_DIS_MASK 0x1 |
| #define RG_VCORE_26M_CK_TST_DIS_MASK_SFT (0x1 << 3) |
| #define RG_DSPPLL_208M_CK_TST_DIS_SFT 2 |
| #define RG_DSPPLL_208M_CK_TST_DIS_MASK 0x1 |
| #define RG_DSPPLL_208M_CK_TST_DIS_MASK_SFT (0x1 << 2) |
| #define RG_OSC_26M_CK_TST_DIS_SFT 1 |
| #define RG_OSC_26M_CK_TST_DIS_MASK 0x1 |
| #define RG_OSC_26M_CK_TST_DIS_MASK_SFT (0x1 << 1) |
| #define RG_OSC_75K_CK_TST_DIS_SFT 0 |
| #define RG_OSC_75K_CK_TST_DIS_MASK 0x1 |
| #define RG_OSC_75K_CK_TST_DIS_MASK_SFT (0x1 << 0) |
| |
| /* CLKSQ_PMU_CON0 */ |
| #define RG_CLKSQ_MONEN_SFT 0 |
| #define RG_CLKSQ_MONEN_MASK 0x1 |
| #define RG_CLKSQ_MONEN_MASK_SFT (0x1 << 0) |
| #define RG_CLKSQ_EN_SFT 1 |
| #define RG_CLKSQ_EN_MASK 0x1 |
| #define RG_CLKSQ_EN_MASK_SFT (0x1 << 1) |
| #define RG_CLKSQ_AUDENC_EN_SFT 2 |
| #define RG_CLKSQ_AUDENC_EN_MASK 0x1 |
| #define RG_CLKSQ_AUDENC_EN_MASK_SFT (0x1 << 2) |
| #define RG_CLKSQ_AUDDEC_EN_SFT 3 |
| #define RG_CLKSQ_AUDDEC_EN_MASK 0x1 |
| #define RG_CLKSQ_AUDDEC_EN_MASK_SFT (0x1 << 3) |
| |
| /* DA_INTF_STTING3 */ |
| #define RG_SRCLKEN_SEL_CO_SFT 0 |
| #define RG_SRCLKEN_SEL_CO_MASK 0x3 |
| #define RG_SRCLKEN_SEL_CO_MASK_SFT (0x3 << 0) |
| #define RG_HWMD_CO_CTL_SFT 2 |
| #define RG_HWMD_CO_CTL_MASK 0x1 |
| #define RG_HWMD_CO_CTL_MASK_SFT (0x1 << 2) |
| #define RG_CO_CTL_VALUE_SFT 3 |
| #define RG_CO_CTL_VALUE_MASK 0x1 |
| #define RG_CO_CTL_VALUE_MASK_SFT (0x1 << 3) |
| |
| /* MTC_CTL0 */ |
| #define RG_MTC_PWRACK_MODE_SFT 0 |
| #define RG_MTC_PWRACK_MODE_MASK 0x1 |
| #define RG_MTC_PWRACK_MODE_MASK_SFT (0x1 << 0) |
| #define RG_MTC_PWRACK_MODE_2ND_SFT 1 |
| #define RG_MTC_PWRACK_MODE_2ND_MASK 0x1 |
| #define RG_MTC_PWRACK_MODE_2ND_MASK_SFT (0x1 << 1) |
| #define RG_CO_OP_EN_SFT 4 |
| #define RG_CO_OP_EN_MASK 0x1 |
| #define RG_CO_OP_EN_MASK_SFT (0x1 << 4) |
| #define RG_CO_ALL_ON_2ND_SFT 5 |
| #define RG_CO_ALL_ON_2ND_MASK 0x1 |
| #define RG_CO_ALL_ON_2ND_MASK_SFT (0x1 << 5) |
| #define RG_MTC_PWRON_TIMING_SEL_SFT 6 |
| #define RG_MTC_PWRON_TIMING_SEL_MASK 0x1 |
| #define RG_MTC_PWRON_TIMING_SEL_MASK_SFT (0x1 << 6) |
| |
| /* PLL208M_PMU_CON0 */ |
| #define RG_PLL208M_SDM_PCW_CHG_SFT 0 |
| #define RG_PLL208M_SDM_PCW_CHG_MASK 0x1 |
| #define RG_PLL208M_SDM_PCW_CHG_MASK_SFT (0x1 << 0) |
| #define RG_PLL208M_SDM_PCW0_SFT 1 |
| #define RG_PLL208M_SDM_PCW0_MASK 0x7f |
| #define RG_PLL208M_SDM_PCW0_MASK_SFT (0x7f << 1) |
| |
| /* PLL208M_PMU_CON4 */ |
| #define RG_PLL208M_EN_SFT 0 |
| #define RG_PLL208M_EN_MASK 0x1 |
| #define RG_PLL208M_EN_MASK_SFT (0x1 << 0) |
| #define RG_PLL208M_POSDIV_SFT 1 |
| #define RG_PLL208M_POSDIV_MASK 0x7 |
| #define RG_PLL208M_POSDIV_MASK_SFT (0x7 << 1) |
| #define RG_PLL208M_SDM_FRA_EN_SFT 4 |
| #define RG_PLL208M_SDM_FRA_EN_MASK 0x1 |
| #define RG_PLL208M_SDM_FRA_EN_MASK_SFT (0x1 << 4) |
| #define RG_PLL208M_BP_SFT 5 |
| #define RG_PLL208M_BP_MASK 0x1 |
| #define RG_PLL208M_BP_MASK_SFT (0x1 << 5) |
| #define RG_PLL208M_BR_SFT 6 |
| #define RG_PLL208M_BR_MASK 0x1 |
| #define RG_PLL208M_BR_MASK_SFT (0x1 << 6) |
| #define RG_PLL208M_BLP_SFT 7 |
| #define RG_PLL208M_BLP_MASK 0x1 |
| #define RG_PLL208M_BLP_MASK_SFT (0x1 << 7) |
| |
| /* PLL208M_PMU_CON5 */ |
| #define RG_PLL208M_SDM_ISO_EN_SFT 0 |
| #define RG_PLL208M_SDM_ISO_EN_MASK 0x1 |
| #define RG_PLL208M_SDM_ISO_EN_MASK_SFT (0x1 << 0) |
| #define RG_PLL208M_SDM_PWR_ON_SFT 1 |
| #define RG_PLL208M_SDM_PWR_ON_MASK 0x1 |
| #define RG_PLL208M_SDM_PWR_ON_MASK_SFT (0x1 << 1) |
| |
| /* VOWPLL_PMU_CON0 */ |
| #define RG_VOWPLL_EN_SFT 0 |
| #define RG_VOWPLL_EN_MASK 0x1 |
| #define RG_VOWPLL_EN_MASK_SFT (0x1 << 0) |
| #define RG_VOWPLL_RST_SFT 1 |
| #define RG_VOWPLL_RST_MASK 0x1 |
| #define RG_VOWPLL_RST_MASK_SFT (0x1 << 1) |
| #define RG_VOWPLL_MONCK_EN_SFT 2 |
| #define RG_VOWPLL_MONCK_EN_MASK 0x1 |
| #define RG_VOWPLL_MONCK_EN_MASK_SFT (0x1 << 2) |
| #define RG_VOWPLL_MONVC_EN_SFT 3 |
| #define RG_VOWPLL_MONVC_EN_MASK 0x1 |
| #define RG_VOWPLL_MONVC_EN_MASK_SFT (0x1 << 3) |
| #define RG_VOWPLL_DIVEN_SFT 4 |
| #define RG_VOWPLL_DIVEN_MASK 0x7 |
| #define RG_VOWPLL_DIVEN_MASK_SFT (0x7 << 4) |
| #define RG_VOWPLL_ICO_SEL_SFT 7 |
| #define RG_VOWPLL_ICO_SEL_MASK 0x1 |
| #define RG_VOWPLL_ICO_SEL_MASK_SFT (0x1 << 7) |
| |
| /* LDO_VAUD18_CON0 */ |
| #define RG_LDO_VAUD18_EN_0_SFT 0 |
| #define RG_LDO_VAUD18_EN_0_MASK 0x1 |
| #define RG_LDO_VAUD18_EN_0_MASK_SFT (0x1 << 0) |
| #define RG_LDO_VAUD18_LP_SFT 1 |
| #define RG_LDO_VAUD18_LP_MASK 0x1 |
| #define RG_LDO_VAUD18_LP_MASK_SFT (0x1 << 1) |
| |
| /* LDO_VAUD18_CON2 */ |
| #define RG_LDO_VAUD18_DUMMY_LOAD_SFT 0 |
| #define RG_LDO_VAUD18_DUMMY_LOAD_MASK 0x3 |
| #define RG_LDO_VAUD18_DUMMY_LOAD_MASK_SFT (0x3 << 0) |
| #define RG_LDO_VAUD18_OP_MODE_SFT 2 |
| #define RG_LDO_VAUD18_OP_MODE_MASK 0x7 |
| #define RG_LDO_VAUD18_OP_MODE_MASK_SFT (0x7 << 2) |
| #define RG_LDO_VAUD18_CK_SW_MODE_SFT 7 |
| #define RG_LDO_VAUD18_CK_SW_MODE_MASK 0x1 |
| #define RG_LDO_VAUD18_CK_SW_MODE_MASK_SFT (0x1 << 7) |
| |
| /* LDO_VAUD18_OP_EN0 */ |
| #define RG_LDO_VAUD18_HW0_OP_EN_SFT 0 |
| #define RG_LDO_VAUD18_HW0_OP_EN_MASK 0x1 |
| #define RG_LDO_VAUD18_HW0_OP_EN_MASK_SFT (0x1 << 0) |
| #define RG_LDO_VAUD18_HW1_OP_EN_SFT 1 |
| #define RG_LDO_VAUD18_HW1_OP_EN_MASK 0x1 |
| #define RG_LDO_VAUD18_HW1_OP_EN_MASK_SFT (0x1 << 1) |
| #define RG_LDO_VAUD18_HW2_OP_EN_SFT 2 |
| #define RG_LDO_VAUD18_HW2_OP_EN_MASK 0x1 |
| #define RG_LDO_VAUD18_HW2_OP_EN_MASK_SFT (0x1 << 2) |
| #define RG_LDO_VAUD18_HW3_OP_EN_SFT 3 |
| #define RG_LDO_VAUD18_HW3_OP_EN_MASK 0x1 |
| #define RG_LDO_VAUD18_HW3_OP_EN_MASK_SFT (0x1 << 3) |
| #define RG_LDO_VAUD18_HW4_OP_EN_SFT 4 |
| #define RG_LDO_VAUD18_HW4_OP_EN_MASK 0x1 |
| #define RG_LDO_VAUD18_HW4_OP_EN_MASK_SFT (0x1 << 4) |
| #define RG_LDO_VAUD18_HW5_OP_EN_SFT 5 |
| #define RG_LDO_VAUD18_HW5_OP_EN_MASK 0x1 |
| #define RG_LDO_VAUD18_HW5_OP_EN_MASK_SFT (0x1 << 5) |
| #define RG_LDO_VAUD18_HW6_OP_EN_SFT 6 |
| #define RG_LDO_VAUD18_HW6_OP_EN_MASK 0x1 |
| #define RG_LDO_VAUD18_HW6_OP_EN_MASK_SFT (0x1 << 6) |
| #define RG_LDO_VAUD18_HW7_OP_EN_SFT 7 |
| #define RG_LDO_VAUD18_HW7_OP_EN_MASK 0x1 |
| #define RG_LDO_VAUD18_HW7_OP_EN_MASK_SFT (0x1 << 7) |
| |
| /* LDO_VAUD18_OP_CFG0 */ |
| #define RG_LDO_VAUD18_HW0_OP_CFG_SFT 0 |
| #define RG_LDO_VAUD18_HW0_OP_CFG_MASK 0x1 |
| #define RG_LDO_VAUD18_HW0_OP_CFG_MASK_SFT (0x1 << 0) |
| #define RG_LDO_VAUD18_HW1_OP_CFG_SFT 1 |
| #define RG_LDO_VAUD18_HW1_OP_CFG_MASK 0x1 |
| #define RG_LDO_VAUD18_HW1_OP_CFG_MASK_SFT (0x1 << 1) |
| #define RG_LDO_VAUD18_HW2_OP_CFG_SFT 2 |
| #define RG_LDO_VAUD18_HW2_OP_CFG_MASK 0x1 |
| #define RG_LDO_VAUD18_HW2_OP_CFG_MASK_SFT (0x1 << 2) |
| #define RG_LDO_VAUD18_HW3_OP_CFG_SFT 3 |
| #define RG_LDO_VAUD18_HW3_OP_CFG_MASK 0x1 |
| #define RG_LDO_VAUD18_HW3_OP_CFG_MASK_SFT (0x1 << 3) |
| #define RG_LDO_VAUD18_HW4_OP_CFG_SFT 4 |
| #define RG_LDO_VAUD18_HW4_OP_CFG_MASK 0x1 |
| #define RG_LDO_VAUD18_HW4_OP_CFG_MASK_SFT (0x1 << 4) |
| #define RG_LDO_VAUD18_HW5_OP_CFG_SFT 5 |
| #define RG_LDO_VAUD18_HW5_OP_CFG_MASK 0x1 |
| #define RG_LDO_VAUD18_HW5_OP_CFG_MASK_SFT (0x1 << 5) |
| #define RG_LDO_VAUD18_HW6_OP_CFG_SFT 6 |
| #define RG_LDO_VAUD18_HW6_OP_CFG_MASK 0x1 |
| #define RG_LDO_VAUD18_HW6_OP_CFG_MASK_SFT (0x1 << 6) |
| #define RG_LDO_VAUD18_HW7_OP_CFG_SFT 7 |
| #define RG_LDO_VAUD18_HW7_OP_CFG_MASK 0x1 |
| #define RG_LDO_VAUD18_HW7_OP_CFG_MASK_SFT (0x1 << 7) |
| |
| /* LDO_VAUD18_OP_EN1 */ |
| #define RG_LDO_VAUD18_HW8_OP_EN_SFT 0 |
| #define RG_LDO_VAUD18_HW8_OP_EN_MASK 0x1 |
| #define RG_LDO_VAUD18_HW8_OP_EN_MASK_SFT (0x1 << 0) |
| #define RG_LDO_VAUD18_HW9_OP_EN_SFT 1 |
| #define RG_LDO_VAUD18_HW9_OP_EN_MASK 0x1 |
| #define RG_LDO_VAUD18_HW9_OP_EN_MASK_SFT (0x1 << 1) |
| #define RG_LDO_VAUD18_HW10_OP_EN_SFT 2 |
| #define RG_LDO_VAUD18_HW10_OP_EN_MASK 0x1 |
| #define RG_LDO_VAUD18_HW10_OP_EN_MASK_SFT (0x1 << 2) |
| #define RG_LDO_VAUD18_HW11_OP_EN_SFT 3 |
| #define RG_LDO_VAUD18_HW11_OP_EN_MASK 0x1 |
| #define RG_LDO_VAUD18_HW11_OP_EN_MASK_SFT (0x1 << 3) |
| #define RG_LDO_VAUD18_HW12_OP_EN_SFT 4 |
| #define RG_LDO_VAUD18_HW12_OP_EN_MASK 0x1 |
| #define RG_LDO_VAUD18_HW12_OP_EN_MASK_SFT (0x1 << 4) |
| #define RG_LDO_VAUD18_HW13_OP_EN_SFT 5 |
| #define RG_LDO_VAUD18_HW13_OP_EN_MASK 0x1 |
| #define RG_LDO_VAUD18_HW13_OP_EN_MASK_SFT (0x1 << 5) |
| #define RG_LDO_VAUD18_HW14_OP_EN_SFT 6 |
| #define RG_LDO_VAUD18_HW14_OP_EN_MASK 0x1 |
| #define RG_LDO_VAUD18_HW14_OP_EN_MASK_SFT (0x1 << 6) |
| #define RG_LDO_VAUD18_SW_OP_EN_SFT 7 |
| #define RG_LDO_VAUD18_SW_OP_EN_MASK 0x1 |
| #define RG_LDO_VAUD18_SW_OP_EN_MASK_SFT (0x1 << 7) |
| |
| /* LDO_VAUD18_OP_CFG1 */ |
| #define RG_LDO_VAUD18_HW8_OP_CFG_SFT 0 |
| #define RG_LDO_VAUD18_HW8_OP_CFG_MASK 0x1 |
| #define RG_LDO_VAUD18_HW8_OP_CFG_MASK_SFT (0x1 << 0) |
| #define RG_LDO_VAUD18_HW9_OP_CFG_SFT 1 |
| #define RG_LDO_VAUD18_HW9_OP_CFG_MASK 0x1 |
| #define RG_LDO_VAUD18_HW9_OP_CFG_MASK_SFT (0x1 << 1) |
| #define RG_LDO_VAUD18_HW10_OP_CFG_SFT 2 |
| #define RG_LDO_VAUD18_HW10_OP_CFG_MASK 0x1 |
| #define RG_LDO_VAUD18_HW10_OP_CFG_MASK_SFT (0x1 << 2) |
| #define RG_LDO_VAUD18_HW11_OP_CFG_SFT 3 |
| #define RG_LDO_VAUD18_HW11_OP_CFG_MASK 0x1 |
| #define RG_LDO_VAUD18_HW11_OP_CFG_MASK_SFT (0x1 << 3) |
| #define RG_LDO_VAUD18_HW12_OP_CFG_SFT 4 |
| #define RG_LDO_VAUD18_HW12_OP_CFG_MASK 0x1 |
| #define RG_LDO_VAUD18_HW12_OP_CFG_MASK_SFT (0x1 << 4) |
| #define RG_LDO_VAUD18_HW13_OP_CFG_SFT 5 |
| #define RG_LDO_VAUD18_HW13_OP_CFG_MASK 0x1 |
| #define RG_LDO_VAUD18_HW13_OP_CFG_MASK_SFT (0x1 << 5) |
| #define RG_LDO_VAUD18_HW14_OP_CFG_SFT 6 |
| #define RG_LDO_VAUD18_HW14_OP_CFG_MASK 0x1 |
| #define RG_LDO_VAUD18_HW14_OP_CFG_MASK_SFT (0x1 << 6) |
| #define RG_LDO_VAUD18_SW_OP_CFG_SFT 7 |
| #define RG_LDO_VAUD18_SW_OP_CFG_MASK 0x1 |
| #define RG_LDO_VAUD18_SW_OP_CFG_MASK_SFT (0x1 << 7) |
| |
| /* VPLL18_PMU_CON0 */ |
| #define RG_VPLL18_LDO_VREF_EN_VA32_SFT 0 |
| #define RG_VPLL18_LDO_VREF_EN_VA32_MASK 0x1 |
| #define RG_VPLL18_LDO_VREF_EN_VA32_MASK_SFT (0x1 << 0) |
| #define RG_VPLL18_LDO_VREF_SEL_VA32_SFT 2 |
| #define RG_VPLL18_LDO_VREF_SEL_VA32_MASK 0x7 |
| #define RG_VPLL18_LDO_VREF_SEL_VA32_MASK_SFT (0x7 << 2) |
| #define RG_VPLL18_LDO_VOWPLL_EN_VA18_SFT 6 |
| #define RG_VPLL18_LDO_VOWPLL_EN_VA18_MASK 0x1 |
| #define RG_VPLL18_LDO_VOWPLL_EN_VA18_MASK_SFT (0x1 << 6) |
| #define RG_VPLL18_LDO_PLL208M_EN_VA18_SFT 7 |
| #define RG_VPLL18_LDO_PLL208M_EN_VA18_MASK 0x1 |
| #define RG_VPLL18_LDO_PLL208M_EN_VA18_MASK_SFT (0x1 << 7) |
| |
| /* AUD_TOP_ID */ |
| #define AUD_TOP_ANA_ID_SFT 0 |
| #define AUD_TOP_ANA_ID_MASK 0xff |
| #define AUD_TOP_ANA_ID_MASK_SFT (0xff << 0) |
| |
| /* AUD_TOP_ID_H */ |
| #define AUD_TOP_DIG_ID_SFT 0 |
| #define AUD_TOP_DIG_ID_MASK 0xff |
| #define AUD_TOP_DIG_ID_MASK_SFT (0xff << 0) |
| |
| /* AUD_TOP_REV0 */ |
| #define AUD_TOP_ANA_MINOR_REV_SFT 0 |
| #define AUD_TOP_ANA_MINOR_REV_MASK 0xf |
| #define AUD_TOP_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUD_TOP_ANA_MAJOR_REV_SFT 4 |
| #define AUD_TOP_ANA_MAJOR_REV_MASK 0xf |
| #define AUD_TOP_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUD_TOP_REV0_H */ |
| #define AUD_TOP_DIG_MINOR_REV_SFT 0 |
| #define AUD_TOP_DIG_MINOR_REV_MASK 0xf |
| #define AUD_TOP_DIG_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUD_TOP_DIG_MAJOR_REV_SFT 4 |
| #define AUD_TOP_DIG_MAJOR_REV_MASK 0xf |
| #define AUD_TOP_DIG_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUD_TOP_DBI */ |
| #define AUD_TOP_CBS_SFT 0 |
| #define AUD_TOP_CBS_MASK 0x3 |
| #define AUD_TOP_CBS_MASK_SFT (0x3 << 0) |
| #define AUD_TOP_BIX_SFT 2 |
| #define AUD_TOP_BIX_MASK 0x3 |
| #define AUD_TOP_BIX_MASK_SFT (0x3 << 2) |
| |
| /* AUD_TOP_DBI_H */ |
| #define AUD_TOP_ESP_SFT 0 |
| #define AUD_TOP_ESP_MASK 0xff |
| #define AUD_TOP_ESP_MASK_SFT (0xff << 0) |
| |
| /* AUD_TOP_DXI */ |
| #define AUD_TOP_FPI_SFT 0 |
| #define AUD_TOP_FPI_MASK 0xff |
| #define AUD_TOP_FPI_MASK_SFT (0xff << 0) |
| |
| /* AUD_TOP_CKPDN_TPM0 */ |
| #define AUD_TOP_CLK_OFFSET_SFT 0 |
| #define AUD_TOP_CLK_OFFSET_MASK 0xff |
| #define AUD_TOP_CLK_OFFSET_MASK_SFT (0xff << 0) |
| |
| /* AUD_TOP_CKPDN_TPM0_H */ |
| #define AUD_TOP_RST_OFFSET_SFT 0 |
| #define AUD_TOP_RST_OFFSET_MASK 0xff |
| #define AUD_TOP_RST_OFFSET_MASK_SFT (0xff << 0) |
| |
| /* AUD_TOP_CKPDN_TPM1 */ |
| #define AUD_TOP_INT_OFFSET_SFT 0 |
| #define AUD_TOP_INT_OFFSET_MASK 0xff |
| #define AUD_TOP_INT_OFFSET_MASK_SFT (0xff << 0) |
| |
| /* AUD_TOP_CKPDN_TPM1_H */ |
| #define AUD_TOP_INT_LEN_SFT 0 |
| #define AUD_TOP_INT_LEN_MASK 0xff |
| #define AUD_TOP_INT_LEN_MASK_SFT (0xff << 0) |
| |
| /* AUD_TOP_CKPDN_CON0 */ |
| #define RG_ACCDET_CK_PDN_SFT 0 |
| #define RG_ACCDET_CK_PDN_MASK 0x1 |
| #define RG_ACCDET_CK_PDN_MASK_SFT (0x1 << 0) |
| #define RG_AUD_CK_PDN_SFT 1 |
| #define RG_AUD_CK_PDN_MASK 0x1 |
| #define RG_AUD_CK_PDN_MASK_SFT (0x1 << 1) |
| #define RG_AUDIF_CK_PDN_SFT 2 |
| #define RG_AUDIF_CK_PDN_MASK 0x1 |
| #define RG_AUDIF_CK_PDN_MASK_SFT (0x1 << 2) |
| #define RG_ZCD13M_CK_PDN_SFT 5 |
| #define RG_ZCD13M_CK_PDN_MASK 0x1 |
| #define RG_ZCD13M_CK_PDN_MASK_SFT (0x1 << 5) |
| #define RG_AUDNCP_CK_PDN_SFT 6 |
| #define RG_AUDNCP_CK_PDN_MASK 0x1 |
| #define RG_AUDNCP_CK_PDN_MASK_SFT (0x1 << 6) |
| #define RG_PAD_AUD_CLK_MISO_CK_PDN_SFT 7 |
| #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK 0x1 |
| #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK_SFT (0x1 << 7) |
| |
| /* AUD_TOP_CKPDN_CON0_SET */ |
| #define RG_AUD_TOP_CKPDN_CON0_SET_SFT 0 |
| #define RG_AUD_TOP_CKPDN_CON0_SET_MASK 0xff |
| #define RG_AUD_TOP_CKPDN_CON0_SET_MASK_SFT (0xff << 0) |
| |
| /* AUD_TOP_CKPDN_CON0_CLR */ |
| #define RG_AUD_TOP_CKPDN_CON0_CLR_SFT 0 |
| #define RG_AUD_TOP_CKPDN_CON0_CLR_MASK 0xff |
| #define RG_AUD_TOP_CKPDN_CON0_CLR_MASK_SFT (0xff << 0) |
| |
| /* AUD_TOP_CKPDN_CON0_H */ |
| #define RG_AUD_INTRP_CK_PDN_SFT 0 |
| #define RG_AUD_INTRP_CK_PDN_MASK 0x1 |
| #define RG_AUD_INTRP_CK_PDN_MASK_SFT (0x1 << 0) |
| #define RG_SCK32K_CK_PDN_SFT 3 |
| #define RG_SCK32K_CK_PDN_MASK 0x1 |
| #define RG_SCK32K_CK_PDN_MASK_SFT (0x1 << 3) |
| #define RG_VOW32K_CK_PDN_SFT 4 |
| #define RG_VOW32K_CK_PDN_MASK 0x1 |
| #define RG_VOW32K_CK_PDN_MASK_SFT (0x1 << 4) |
| #define RG_VOW13M_CK_PDN_SFT 5 |
| #define RG_VOW13M_CK_PDN_MASK 0x1 |
| #define RG_VOW13M_CK_PDN_MASK_SFT (0x1 << 5) |
| #define RG_AUD208M_CK_PDN_SFT 6 |
| #define RG_AUD208M_CK_PDN_MASK 0x1 |
| #define RG_AUD208M_CK_PDN_MASK_SFT (0x1 << 6) |
| |
| /* AUD_TOP_CKPDN_CON0_H_SET */ |
| #define RG_AUD_TOP_CKPDN_CON0_SET_H_SFT 0 |
| #define RG_AUD_TOP_CKPDN_CON0_SET_H_MASK 0xff |
| #define RG_AUD_TOP_CKPDN_CON0_SET_H_MASK_SFT (0xff << 0) |
| |
| /* AUD_TOP_CKPDN_CON0_H_CLR */ |
| #define RG_AUD_TOP_CKPDN_CON0_CLR_H_SFT 0 |
| #define RG_AUD_TOP_CKPDN_CON0_CLR_H_MASK 0xff |
| #define RG_AUD_TOP_CKPDN_CON0_CLR_H_MASK_SFT (0xff << 0) |
| |
| /* AUD_TOP_CKSEL_CON0 */ |
| #define RG_AUD_CK_CKSEL_SFT 2 |
| #define RG_AUD_CK_CKSEL_MASK 0x1 |
| #define RG_AUD_CK_CKSEL_MASK_SFT (0x1 << 2) |
| #define RG_AUDIF_CK_CKSEL_SFT 3 |
| #define RG_AUDIF_CK_CKSEL_MASK 0x1 |
| #define RG_AUDIF_CK_CKSEL_MASK_SFT (0x1 << 3) |
| |
| /* AUD_TOP_CKSEL_CON0_SET */ |
| #define RG_AUD_TOP_CKSEL_CON0_SET_SFT 0 |
| #define RG_AUD_TOP_CKSEL_CON0_SET_MASK 0xf |
| #define RG_AUD_TOP_CKSEL_CON0_SET_MASK_SFT (0xf << 0) |
| |
| /* AUD_TOP_CKSEL_CON0_CLR */ |
| #define RG_AUD_TOP_CKSEL_CON0_CLR_SFT 0 |
| #define RG_AUD_TOP_CKSEL_CON0_CLR_MASK 0xf |
| #define RG_AUD_TOP_CKSEL_CON0_CLR_MASK_SFT (0xf << 0) |
| |
| /* AUD_TOP_CKTST_CON0 */ |
| #define RG_AUD26M_CK_TST_DIS_SFT 0 |
| #define RG_AUD26M_CK_TST_DIS_MASK 0x1 |
| #define RG_AUD26M_CK_TST_DIS_MASK_SFT (0x1 << 0) |
| #define RG_AUD_CK_TSTSEL_SFT 2 |
| #define RG_AUD_CK_TSTSEL_MASK 0x1 |
| #define RG_AUD_CK_TSTSEL_MASK_SFT (0x1 << 2) |
| #define RG_AUDIF_CK_TSTSEL_SFT 3 |
| #define RG_AUDIF_CK_TSTSEL_MASK 0x1 |
| #define RG_AUDIF_CK_TSTSEL_MASK_SFT (0x1 << 3) |
| #define RG_AUD26M_CK_TSTSEL_SFT 4 |
| #define RG_AUD26M_CK_TSTSEL_MASK 0x1 |
| #define RG_AUD26M_CK_TSTSEL_MASK_SFT (0x1 << 4) |
| |
| /* AUD_TOP_CKTST_CON0_H */ |
| #define RG_VOW13M_CK_TST_DIS_SFT 0 |
| #define RG_VOW13M_CK_TST_DIS_MASK 0x1 |
| #define RG_VOW13M_CK_TST_DIS_MASK_SFT (0x1 << 0) |
| #define RG_VOW13M_CK_TSTSEL_SFT 1 |
| #define RG_VOW13M_CK_TSTSEL_MASK 0x1 |
| #define RG_VOW13M_CK_TSTSEL_MASK_SFT (0x1 << 1) |
| #define RG_AUD208M_CK_TST_DIS_SFT 2 |
| #define RG_AUD208M_CK_TST_DIS_MASK 0x1 |
| #define RG_AUD208M_CK_TST_DIS_MASK_SFT (0x1 << 2) |
| #define RG_AUD208M_CK_TSTSEL_SFT 3 |
| #define RG_AUD208M_CK_TSTSEL_MASK 0x1 |
| #define RG_AUD208M_CK_TSTSEL_MASK_SFT (0x1 << 3) |
| #define RG_SCK_32K_CK_TST_DIS_SFT 4 |
| #define RG_SCK_32K_CK_TST_DIS_MASK 0x1 |
| #define RG_SCK_32K_CK_TST_DIS_MASK_SFT (0x1 << 4) |
| #define RG_SCK_32K_CK_TSTSEL_SFT 5 |
| #define RG_SCK_32K_CK_TSTSEL_MASK 0x1 |
| #define RG_SCK_32K_CK_TSTSEL_MASK_SFT (0x1 << 5) |
| |
| /* AUD_TOP_CLK_HWEN_CON0 */ |
| #define RG_AUD_INTRP_CK_PDN_HWEN_SFT 0 |
| #define RG_AUD_INTRP_CK_PDN_HWEN_MASK 0x1 |
| #define RG_AUD_INTRP_CK_PDN_HWEN_MASK_SFT (0x1 << 0) |
| |
| /* AUD_TOP_CLK_HWEN_CON0_SET */ |
| #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_SFT 0 |
| #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK 0xff |
| #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK_SFT (0xff << 0) |
| |
| /* AUD_TOP_CLK_HWEN_CON0_CLR */ |
| #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_SFT 0 |
| #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK 0xff |
| #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK_SFT (0xff << 0) |
| |
| /* AUD_TOP_RST_CON0 */ |
| #define RG_AUDIO_RST_SFT 0 |
| #define RG_AUDIO_RST_MASK 0x1 |
| #define RG_AUDIO_RST_MASK_SFT (0x1 << 0) |
| #define RG_ACCDET_RST_SFT 1 |
| #define RG_ACCDET_RST_MASK 0x1 |
| #define RG_ACCDET_RST_MASK_SFT (0x1 << 1) |
| #define RG_ZCD_RST_SFT 2 |
| #define RG_ZCD_RST_MASK 0x1 |
| #define RG_ZCD_RST_MASK_SFT (0x1 << 2) |
| #define RG_AUDNCP_RST_SFT 3 |
| #define RG_AUDNCP_RST_MASK 0x1 |
| #define RG_AUDNCP_RST_MASK_SFT (0x1 << 3) |
| |
| /* AUD_TOP_RST_CON0_SET */ |
| #define RG_AUD_TOP_RST_CON0_SET_SFT 0 |
| #define RG_AUD_TOP_RST_CON0_SET_MASK 0xf |
| #define RG_AUD_TOP_RST_CON0_SET_MASK_SFT (0xf << 0) |
| |
| /* AUD_TOP_RST_CON0_CLR */ |
| #define RG_AUD_TOP_RST_CON0_CLR_SFT 0 |
| #define RG_AUD_TOP_RST_CON0_CLR_MASK 0xf |
| #define RG_AUD_TOP_RST_CON0_CLR_MASK_SFT (0xf << 0) |
| |
| /* AUD_TOP_RST_BANK_CON0 */ |
| #define BANK_ACCDET_SWRST_SFT 0 |
| #define BANK_ACCDET_SWRST_MASK 0x1 |
| #define BANK_ACCDET_SWRST_MASK_SFT (0x1 << 0) |
| #define BANK_AUDIO_SWRST_SFT 1 |
| #define BANK_AUDIO_SWRST_MASK 0x1 |
| #define BANK_AUDIO_SWRST_MASK_SFT (0x1 << 1) |
| #define BANK_AUDZCD_SWRST_SFT 2 |
| #define BANK_AUDZCD_SWRST_MASK 0x1 |
| #define BANK_AUDZCD_SWRST_MASK_SFT (0x1 << 2) |
| |
| /* AUD_TOP_INT_CON0 */ |
| #define RG_INT_EN_AUDIO_SFT 0 |
| #define RG_INT_EN_AUDIO_MASK 0x1 |
| #define RG_INT_EN_AUDIO_MASK_SFT (0x1 << 0) |
| #define RG_INT_EN_VOW_SFT 1 |
| #define RG_INT_EN_VOW_MASK 0x1 |
| #define RG_INT_EN_VOW_MASK_SFT (0x1 << 1) |
| #define RG_INT_EN_ACCDET_SFT 5 |
| #define RG_INT_EN_ACCDET_MASK 0x1 |
| #define RG_INT_EN_ACCDET_MASK_SFT (0x1 << 5) |
| #define RG_INT_EN_ACCDET_EINT0_SFT 6 |
| #define RG_INT_EN_ACCDET_EINT0_MASK 0x1 |
| #define RG_INT_EN_ACCDET_EINT0_MASK_SFT (0x1 << 6) |
| #define RG_INT_EN_ACCDET_EINT1_SFT 7 |
| #define RG_INT_EN_ACCDET_EINT1_MASK 0x1 |
| #define RG_INT_EN_ACCDET_EINT1_MASK_SFT (0x1 << 7) |
| |
| /* AUD_TOP_INT_CON0_SET */ |
| #define RG_AUD_INT_CON0_SET_SFT 0 |
| #define RG_AUD_INT_CON0_SET_MASK 0xff |
| #define RG_AUD_INT_CON0_SET_MASK_SFT (0xff << 0) |
| |
| /* AUD_TOP_INT_CON0_CLR */ |
| #define RG_AUD_INT_CON0_CLR_SFT 0 |
| #define RG_AUD_INT_CON0_CLR_MASK 0xff |
| #define RG_AUD_INT_CON0_CLR_MASK_SFT (0xff << 0) |
| |
| /* AUD_TOP_INT_MASK_CON0 */ |
| #define RG_INT_MASK_AUDIO_SFT 0 |
| #define RG_INT_MASK_AUDIO_MASK 0x1 |
| #define RG_INT_MASK_AUDIO_MASK_SFT (0x1 << 0) |
| #define RG_INT_MASK_VOW_SFT 1 |
| #define RG_INT_MASK_VOW_MASK 0x1 |
| #define RG_INT_MASK_VOW_MASK_SFT (0x1 << 1) |
| #define RG_INT_MASK_ACCDET_SFT 5 |
| #define RG_INT_MASK_ACCDET_MASK 0x1 |
| #define RG_INT_MASK_ACCDET_MASK_SFT (0x1 << 5) |
| #define RG_INT_MASK_ACCDET_EINT0_SFT 6 |
| #define RG_INT_MASK_ACCDET_EINT0_MASK 0x1 |
| #define RG_INT_MASK_ACCDET_EINT0_MASK_SFT (0x1 << 6) |
| #define RG_INT_MASK_ACCDET_EINT1_SFT 7 |
| #define RG_INT_MASK_ACCDET_EINT1_MASK 0x1 |
| #define RG_INT_MASK_ACCDET_EINT1_MASK_SFT (0x1 << 7) |
| |
| /* AUD_TOP_INT_MASK_CON0_SET */ |
| #define RG_AUD_INT_MASK_CON0_SET_SFT 0 |
| #define RG_AUD_INT_MASK_CON0_SET_MASK 0xff |
| #define RG_AUD_INT_MASK_CON0_SET_MASK_SFT (0xff << 0) |
| |
| /* AUD_TOP_INT_MASK_CON0_CLR */ |
| #define RG_AUD_INT_MASK_CON0_CLR_SFT 0 |
| #define RG_AUD_INT_MASK_CON0_CLR_MASK 0xff |
| #define RG_AUD_INT_MASK_CON0_CLR_MASK_SFT (0xff << 0) |
| |
| /* AUD_TOP_INT_STATUS0 */ |
| #define RG_INT_STATUS_AUDIO_SFT 0 |
| #define RG_INT_STATUS_AUDIO_MASK 0x1 |
| #define RG_INT_STATUS_AUDIO_MASK_SFT (0x1 << 0) |
| #define RG_INT_STATUS_VOW_SFT 1 |
| #define RG_INT_STATUS_VOW_MASK 0x1 |
| #define RG_INT_STATUS_VOW_MASK_SFT (0x1 << 1) |
| #define RG_INT_STATUS_ACCDET_SFT 5 |
| #define RG_INT_STATUS_ACCDET_MASK 0x1 |
| #define RG_INT_STATUS_ACCDET_MASK_SFT (0x1 << 5) |
| #define RG_INT_STATUS_ACCDET_EINT0_SFT 6 |
| #define RG_INT_STATUS_ACCDET_EINT0_MASK 0x1 |
| #define RG_INT_STATUS_ACCDET_EINT0_MASK_SFT (0x1 << 6) |
| #define RG_INT_STATUS_ACCDET_EINT1_SFT 7 |
| #define RG_INT_STATUS_ACCDET_EINT1_MASK 0x1 |
| #define RG_INT_STATUS_ACCDET_EINT1_MASK_SFT (0x1 << 7) |
| |
| /* AUD_TOP_INT_RAW_STATUS0 */ |
| #define RG_INT_RAW_STATUS_AUDIO_SFT 0 |
| #define RG_INT_RAW_STATUS_AUDIO_MASK 0x1 |
| #define RG_INT_RAW_STATUS_AUDIO_MASK_SFT (0x1 << 0) |
| #define RG_INT_RAW_STATUS_VOW_SFT 1 |
| #define RG_INT_RAW_STATUS_VOW_MASK 0x1 |
| #define RG_INT_RAW_STATUS_VOW_MASK_SFT (0x1 << 1) |
| #define RG_INT_RAW_STATUS_ACCDET_SFT 5 |
| #define RG_INT_RAW_STATUS_ACCDET_MASK 0x1 |
| #define RG_INT_RAW_STATUS_ACCDET_MASK_SFT (0x1 << 5) |
| #define RG_INT_RAW_STATUS_ACCDET_EINT0_SFT 6 |
| #define RG_INT_RAW_STATUS_ACCDET_EINT0_MASK 0x1 |
| #define RG_INT_RAW_STATUS_ACCDET_EINT0_MASK_SFT (0x1 << 6) |
| #define RG_INT_RAW_STATUS_ACCDET_EINT1_SFT 7 |
| #define RG_INT_RAW_STATUS_ACCDET_EINT1_MASK 0x1 |
| #define RG_INT_RAW_STATUS_ACCDET_EINT1_MASK_SFT (0x1 << 7) |
| |
| /* AUD_TOP_INT_MISC_CON0 */ |
| #define RG_AUD_TOP_INT_POLARITY_SFT 0 |
| #define RG_AUD_TOP_INT_POLARITY_MASK 0x1 |
| #define RG_AUD_TOP_INT_POLARITY_MASK_SFT (0x1 << 0) |
| |
| /* AUD_TOP_MON_CON0 */ |
| #define RG_AUD_TOP_MON_SEL_SFT 0 |
| #define RG_AUD_TOP_MON_SEL_MASK 0x7 |
| #define RG_AUD_TOP_MON_SEL_MASK_SFT (0x7 << 0) |
| #define RG_AUD_CLK_INT_MON_FLAG_EN_SFT 3 |
| #define RG_AUD_CLK_INT_MON_FLAG_EN_MASK 0x1 |
| #define RG_AUD_CLK_INT_MON_FLAG_EN_MASK_SFT (0x1 << 3) |
| |
| /* AUD_TOP_MON_CON0_H */ |
| #define RG_AUD_CLK_INT_MON_FLAG_SEL_SFT 0 |
| #define RG_AUD_CLK_INT_MON_FLAG_SEL_MASK 0xff |
| #define RG_AUD_CLK_INT_MON_FLAG_SEL_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_CFG */ |
| #define RG_AUD_PAD_TOP_PHASE_MODE_SFT 0 |
| #define RG_AUD_PAD_TOP_PHASE_MODE_MASK 0x7f |
| #define RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT (0x7f << 0) |
| #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT 7 |
| #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK 0x1 |
| #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT (0x1 << 7) |
| |
| /* AUDIO_DIG_CFG_H */ |
| #define RG_AUD_PAD_TOP_PHASE_MODE2_SFT 0 |
| #define RG_AUD_PAD_TOP_PHASE_MODE2_MASK 0x7f |
| #define RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT (0x7f << 0) |
| #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT 7 |
| #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK 0x1 |
| #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT (0x1 << 7) |
| |
| /* AUDIO_DIG_CFG1 */ |
| #define RG_AUD_PAD_TOP_PHASE_MODE3_SFT 0 |
| #define RG_AUD_PAD_TOP_PHASE_MODE3_MASK 0x7f |
| #define RG_AUD_PAD_TOP_PHASE_MODE3_MASK_SFT (0x7f << 0) |
| #define RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_SFT 7 |
| #define RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK 0x1 |
| #define RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK_SFT (0x1 << 7) |
| |
| /* AFE_AUD_PAD_TOP */ |
| #define RG_AUD_PAD_TOP_TX_FIFO_ON_SFT 0 |
| #define RG_AUD_PAD_TOP_TX_FIFO_ON_MASK 0x1 |
| #define RG_AUD_PAD_TOP_TX_FIFO_ON_MASK_SFT (0x1 << 0) |
| #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_SFT 3 |
| #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK 0x1 |
| #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK_SFT (0x1 << 3) |
| #define RG_AUD_PAD_TOP_TX_FIFO_RSP_SFT 4 |
| #define RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK 0x7 |
| #define RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK_SFT (0x7 << 4) |
| |
| /* AFE_AUD_PAD_TOP_MON */ |
| #define ADDA_AUD_PAD_TOP_MON_L_SFT 0 |
| #define ADDA_AUD_PAD_TOP_MON_L_MASK 0xff |
| #define ADDA_AUD_PAD_TOP_MON_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_AUD_PAD_TOP_MON_H */ |
| #define ADDA_AUD_PAD_TOP_MON_H_SFT 0 |
| #define ADDA_AUD_PAD_TOP_MON_H_MASK 0xff |
| #define ADDA_AUD_PAD_TOP_MON_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_AUD_PAD_TOP_MON1 */ |
| #define ADDA_AUD_PAD_TOP_MON1_L_SFT 0 |
| #define ADDA_AUD_PAD_TOP_MON1_L_MASK 0xff |
| #define ADDA_AUD_PAD_TOP_MON1_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_AUD_PAD_TOP_MON1_H */ |
| #define ADDA_AUD_PAD_TOP_MON1_H_SFT 0 |
| #define ADDA_AUD_PAD_TOP_MON1_H_MASK 0xff |
| #define ADDA_AUD_PAD_TOP_MON1_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_AUD_PAD_TOP_MON2 */ |
| #define ADDA_AUD_PAD_TOP_MON2_L_SFT 0 |
| #define ADDA_AUD_PAD_TOP_MON2_L_MASK 0xff |
| #define ADDA_AUD_PAD_TOP_MON2_L_MASK_SFT (0xff << 0) |
| |
| /* AUD_TOP_SRAM_CON */ |
| #define AUDIO_MEM_PDN_SFT 0 |
| #define AUDIO_MEM_PDN_MASK 0x1 |
| #define AUDIO_MEM_PDN_MASK_SFT (0x1 << 0) |
| #define AUDIO_CO_MEM_PDN_SFT 1 |
| #define AUDIO_CO_MEM_PDN_MASK 0x1 |
| #define AUDIO_CO_MEM_PDN_MASK_SFT (0x1 << 1) |
| #define AUDIO_CO_MEM_PDN_SEL_SFT 2 |
| #define AUDIO_CO_MEM_PDN_SEL_MASK 0x1 |
| #define AUDIO_CO_MEM_PDN_SEL_MASK_SFT (0x1 << 2) |
| |
| /* AFE_DCCLK1_CFG0 */ |
| #define DCCLK1_DIV_L_SFT 5 |
| #define DCCLK1_DIV_L_MASK 0x7 |
| #define DCCLK1_DIV_L_MASK_SFT (0x7 << 5) |
| #define DCCLK1_INV_SFT 4 |
| #define DCCLK1_INV_MASK 0x1 |
| #define DCCLK1_INV_MASK_SFT (0x1 << 4) |
| #define DCCLK1_REF_CK_SEL_SFT 2 |
| #define DCCLK1_REF_CK_SEL_MASK 0x3 |
| #define DCCLK1_REF_CK_SEL_MASK_SFT (0x3 << 2) |
| #define DCCLK1_PDN_SFT 1 |
| #define DCCLK1_PDN_MASK 0x1 |
| #define DCCLK1_PDN_MASK_SFT (0x1 << 1) |
| #define DCCLK1_GEN_ON_SFT 0 |
| #define DCCLK1_GEN_ON_MASK 0x1 |
| #define DCCLK1_GEN_ON_MASK_SFT (0x1 << 0) |
| |
| /* AFE_DCCLK1_CFG1 */ |
| #define DCCLK1_DIV_H_SFT 0 |
| #define DCCLK1_DIV_H_MASK 0xff |
| #define DCCLK1_DIV_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_DCCLK1_CFG2 */ |
| #define DCCLK1_RESYNC_SRC_SEL_SFT 6 |
| #define DCCLK1_RESYNC_SRC_SEL_MASK 0x3 |
| #define DCCLK1_RESYNC_SRC_SEL_MASK_SFT (0x3 << 6) |
| #define DCCLK1_RESYNC_SRC_CK_INV_SFT 5 |
| #define DCCLK1_RESYNC_SRC_CK_INV_MASK 0x1 |
| #define DCCLK1_RESYNC_SRC_CK_INV_MASK_SFT (0x1 << 5) |
| #define DCCLK1_RESYNC_BYPASS_SFT 4 |
| #define DCCLK1_RESYNC_BYPASS_MASK 0x1 |
| #define DCCLK1_RESYNC_BYPASS_MASK_SFT (0x1 << 4) |
| #define DCCLK1_PHASE_SEL_SFT 0 |
| #define DCCLK1_PHASE_SEL_MASK 0xf |
| #define DCCLK1_PHASE_SEL_MASK_SFT (0xf << 0) |
| |
| /* AFE_DCCLK2_CFG0 */ |
| #define DCCLK2_DIV_L_SFT 5 |
| #define DCCLK2_DIV_L_MASK 0x7 |
| #define DCCLK2_DIV_L_MASK_SFT (0x7 << 5) |
| #define DCCLK2_INV_SFT 4 |
| #define DCCLK2_INV_MASK 0x1 |
| #define DCCLK2_INV_MASK_SFT (0x1 << 4) |
| #define DCCLK2_REF_CK_SEL_SFT 2 |
| #define DCCLK2_REF_CK_SEL_MASK 0x3 |
| #define DCCLK2_REF_CK_SEL_MASK_SFT (0x3 << 2) |
| #define DCCLK2_PDN_SFT 1 |
| #define DCCLK2_PDN_MASK 0x1 |
| #define DCCLK2_PDN_MASK_SFT (0x1 << 1) |
| #define DCCLK2_GEN_ON_SFT 0 |
| #define DCCLK2_GEN_ON_MASK 0x1 |
| #define DCCLK2_GEN_ON_MASK_SFT (0x1 << 0) |
| |
| /* AFE_DCCLK2_CFG1 */ |
| #define DCCLK2_DIV_H_SFT 0 |
| #define DCCLK2_DIV_H_MASK 0xff |
| #define DCCLK2_DIV_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_DCCLK2_CFG2 */ |
| #define DCCLK2_RESYNC_SRC_SEL_SFT 6 |
| #define DCCLK2_RESYNC_SRC_SEL_MASK 0x3 |
| #define DCCLK2_RESYNC_SRC_SEL_MASK_SFT (0x3 << 6) |
| #define DCCLK2_RESYNC_SRC_CK_INV_SFT 5 |
| #define DCCLK2_RESYNC_SRC_CK_INV_MASK 0x1 |
| #define DCCLK2_RESYNC_SRC_CK_INV_MASK_SFT (0x1 << 5) |
| #define DCCLK2_RESYNC_BYPASS_SFT 4 |
| #define DCCLK2_RESYNC_BYPASS_MASK 0x1 |
| #define DCCLK2_RESYNC_BYPASS_MASK_SFT (0x1 << 4) |
| #define DCCLK2_PHASE_SEL_SFT 0 |
| #define DCCLK2_PHASE_SEL_MASK 0xf |
| #define DCCLK2_PHASE_SEL_MASK_SFT (0xf << 0) |
| |
| /* AFE_DCCLK3_CFG0 */ |
| #define DCCLK3_DIV_L_SFT 5 |
| #define DCCLK3_DIV_L_MASK 0x7 |
| #define DCCLK3_DIV_L_MASK_SFT (0x7 << 5) |
| #define DCCLK3_INV_SFT 4 |
| #define DCCLK3_INV_MASK 0x1 |
| #define DCCLK3_INV_MASK_SFT (0x1 << 4) |
| #define DCCLK3_REF_CK_SEL_SFT 2 |
| #define DCCLK3_REF_CK_SEL_MASK 0x3 |
| #define DCCLK3_REF_CK_SEL_MASK_SFT (0x3 << 2) |
| #define DCCLK3_PDN_SFT 1 |
| #define DCCLK3_PDN_MASK 0x1 |
| #define DCCLK3_PDN_MASK_SFT (0x1 << 1) |
| #define DCCLK3_GEN_ON_SFT 0 |
| #define DCCLK3_GEN_ON_MASK 0x1 |
| #define DCCLK3_GEN_ON_MASK_SFT (0x1 << 0) |
| |
| /* AFE_DCCLK3_CFG1 */ |
| #define DCCLK3_DIV_H_SFT 0 |
| #define DCCLK3_DIV_H_MASK 0xff |
| #define DCCLK3_DIV_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_DCCLK3_CFG2 */ |
| #define DCCLK3_RESYNC_SRC_SEL_SFT 6 |
| #define DCCLK3_RESYNC_SRC_SEL_MASK 0x3 |
| #define DCCLK3_RESYNC_SRC_SEL_MASK_SFT (0x3 << 6) |
| #define DCCLK3_RESYNC_SRC_CK_INV_SFT 5 |
| #define DCCLK3_RESYNC_SRC_CK_INV_MASK 0x1 |
| #define DCCLK3_RESYNC_SRC_CK_INV_MASK_SFT (0x1 << 5) |
| #define DCCLK3_RESYNC_BYPASS_SFT 4 |
| #define DCCLK3_RESYNC_BYPASS_MASK 0x1 |
| #define DCCLK3_RESYNC_BYPASS_MASK_SFT (0x1 << 4) |
| #define DCCLK3_PHASE_SEL_SFT 0 |
| #define DCCLK3_PHASE_SEL_MASK 0xf |
| #define DCCLK3_PHASE_SEL_MASK_SFT (0xf << 0) |
| |
| /* AFE_DCCLK4_CFG0 */ |
| #define DCCLK4_DIV_L_SFT 5 |
| #define DCCLK4_DIV_L_MASK 0x7 |
| #define DCCLK4_DIV_L_MASK_SFT (0x7 << 5) |
| #define DCCLK4_INV_SFT 4 |
| #define DCCLK4_INV_MASK 0x1 |
| #define DCCLK4_INV_MASK_SFT (0x1 << 4) |
| #define DCCLK4_REF_CK_SEL_SFT 2 |
| #define DCCLK4_REF_CK_SEL_MASK 0x3 |
| #define DCCLK4_REF_CK_SEL_MASK_SFT (0x3 << 2) |
| #define DCCLK4_PDN_SFT 1 |
| #define DCCLK4_PDN_MASK 0x1 |
| #define DCCLK4_PDN_MASK_SFT (0x1 << 1) |
| #define DCCLK4_GEN_ON_SFT 0 |
| #define DCCLK4_GEN_ON_MASK 0x1 |
| #define DCCLK4_GEN_ON_MASK_SFT (0x1 << 0) |
| |
| /* AFE_DCCLK4_CFG1 */ |
| #define DCCLK4_DIV_H_SFT 0 |
| #define DCCLK4_DIV_H_MASK 0xff |
| #define DCCLK4_DIV_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_DCCLK4_CFG2 */ |
| #define DCCLK4_RESYNC_SRC_SEL_SFT 6 |
| #define DCCLK4_RESYNC_SRC_SEL_MASK 0x3 |
| #define DCCLK4_RESYNC_SRC_SEL_MASK_SFT (0x3 << 6) |
| #define DCCLK4_RESYNC_SRC_CK_INV_SFT 5 |
| #define DCCLK4_RESYNC_SRC_CK_INV_MASK 0x1 |
| #define DCCLK4_RESYNC_SRC_CK_INV_MASK_SFT (0x1 << 5) |
| #define DCCLK4_RESYNC_BYPASS_SFT 4 |
| #define DCCLK4_RESYNC_BYPASS_MASK 0x1 |
| #define DCCLK4_RESYNC_BYPASS_MASK_SFT (0x1 << 4) |
| #define DCCLK4_PHASE_SEL_SFT 0 |
| #define DCCLK4_PHASE_SEL_MASK 0xf |
| #define DCCLK4_PHASE_SEL_MASK_SFT (0xf << 0) |
| |
| /* AO_AFUNC_AUD_CON3_L */ |
| #define DIGMIC_TESTCK_SRC_SEL_SFT 4 |
| #define DIGMIC_TESTCK_SRC_SEL_MASK 0x7 |
| #define DIGMIC_TESTCK_SRC_SEL_MASK_SFT (0x7 << 4) |
| #define DIGMIC_TESTCK_SEL_SFT 0 |
| #define DIGMIC_TESTCK_SEL_MASK 0x1 |
| #define DIGMIC_TESTCK_SEL_MASK_SFT (0x1 << 0) |
| |
| /* AO_AFUNC_AUD_CON4_H */ |
| #define UL_FIFO_TESTIN_SFT 1 |
| #define UL_FIFO_TESTIN_MASK 0x1f |
| #define UL_FIFO_TESTIN_MASK_SFT (0x1f << 1) |
| |
| /* AO_AFUNC_AUD_CON4_L */ |
| #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_SFT 6 |
| #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK 0x1 |
| #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 6) |
| #define UL_FIFO_WDATA_TESTEN_SFT 5 |
| #define UL_FIFO_WDATA_TESTEN_MASK 0x1 |
| #define UL_FIFO_WDATA_TESTEN_MASK_SFT (0x1 << 5) |
| #define UL_FIFO_WDATA_TESTSRC_SEL_SFT 4 |
| #define UL_FIFO_WDATA_TESTSRC_SEL_MASK 0x1 |
| #define UL_FIFO_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 4) |
| |
| /* AO_AFUNC_AUD_CON7_H */ |
| #define UL2_DIGMIC_TESTCK_SRC_SEL_SFT 2 |
| #define UL2_DIGMIC_TESTCK_SRC_SEL_MASK 0x7 |
| #define UL2_DIGMIC_TESTCK_SRC_SEL_MASK_SFT (0x7 << 2) |
| #define UL2_DIGMIC_TESTCK_SEL_SFT 1 |
| #define UL2_DIGMIC_TESTCK_SEL_MASK 0x1 |
| #define UL2_DIGMIC_TESTCK_SEL_MASK_SFT (0x1 << 1) |
| |
| /* AO_AFUNC_AUD_CON7_L */ |
| #define UL2_FIFO_DIGMIC_WDATA_TESTSRC_SEL_SFT 6 |
| #define UL2_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK 0x1 |
| #define UL2_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 6) |
| #define UL2_FIFO_WDATA_TESTEN_SFT 5 |
| #define UL2_FIFO_WDATA_TESTEN_MASK 0x1 |
| #define UL2_FIFO_WDATA_TESTEN_MASK_SFT (0x1 << 5) |
| #define UL2_FIFO_WDATA_TESTSRC_SEL_SFT 4 |
| #define UL2_FIFO_WDATA_TESTSRC_SEL_MASK 0x1 |
| #define UL2_FIFO_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 4) |
| |
| /* AO_AFE_DMIC_ARRAY_CFG */ |
| #define RG_DMIC_ADC0_SOURCE_SEL_SFT 6 |
| #define RG_DMIC_ADC0_SOURCE_SEL_MASK 0x3 |
| #define RG_DMIC_ADC0_SOURCE_SEL_MASK_SFT (0x3 << 6) |
| #define RG_DMIC_ADC1_SOURCE_SEL_SFT 4 |
| #define RG_DMIC_ADC1_SOURCE_SEL_MASK 0x3 |
| #define RG_DMIC_ADC1_SOURCE_SEL_MASK_SFT (0x3 << 4) |
| #define RG_DMIC_ADC2_SOURCE_SEL_SFT 2 |
| #define RG_DMIC_ADC2_SOURCE_SEL_MASK 0x3 |
| #define RG_DMIC_ADC2_SOURCE_SEL_MASK_SFT (0x3 << 2) |
| #define RG_DMIC_ADC3_SOURCE_SEL_SFT 0 |
| #define RG_DMIC_ADC3_SOURCE_SEL_MASK 0x3 |
| #define RG_DMIC_ADC3_SOURCE_SEL_MASK_SFT (0x3 << 0) |
| |
| /* AO_AFE_ADC_ASYNC_FIFO_CFG */ |
| #define RG_AMIC_UL_ADC_CLK_SEL_SFT 3 |
| #define RG_AMIC_UL_ADC_CLK_SEL_MASK 0x1 |
| #define RG_AMIC_UL_ADC_CLK_SEL_MASK_SFT (0x1 << 3) |
| |
| /* AO_AUDIO_TOP_CON0 */ |
| #define PDN_ADC_CTL_SFT 5 |
| #define PDN_ADC_CTL_MASK 0x1 |
| #define PDN_ADC_CTL_MASK_SFT (0x1 << 5) |
| |
| /* AUDIO_DIG_DSN_ID */ |
| #define AUDIO_DIG_ANA_ID_SFT 0 |
| #define AUDIO_DIG_ANA_ID_MASK 0xff |
| #define AUDIO_DIG_ANA_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_DSN_ID_H */ |
| #define AUDIO_DIG_DIG_ID_SFT 0 |
| #define AUDIO_DIG_DIG_ID_MASK 0xff |
| #define AUDIO_DIG_DIG_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_DSN_REV0 */ |
| #define AUDIO_DIG_ANA_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_ANA_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_ANA_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_ANA_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_DSN_REV0_H */ |
| #define AUDIO_DIG_DIG_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_DIG_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_DIG_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_DIG_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_DIG_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_DIG_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_DSN_DBI */ |
| #define AUDIO_DIG_DSN_CBS_SFT 0 |
| #define AUDIO_DIG_DSN_CBS_MASK 0x3 |
| #define AUDIO_DIG_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDIO_DIG_DSN_BIX_SFT 2 |
| #define AUDIO_DIG_DSN_BIX_MASK 0x3 |
| #define AUDIO_DIG_DSN_BIX_MASK_SFT (0x3 << 2) |
| |
| /* AUDIO_DIG_DSN_DBI_H */ |
| #define AUDIO_DIG_1_ESP_SFT 0 |
| #define AUDIO_DIG_1_ESP_MASK 0xff |
| #define AUDIO_DIG_1_ESP_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_DSN_DXI */ |
| #define AUDIO_DIG_DSN_FPI_SFT 0 |
| #define AUDIO_DIG_DSN_FPI_MASK 0xff |
| #define AUDIO_DIG_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_TOP_CON0 */ |
| #define PDN_AFE_CTL_SFT 7 |
| #define PDN_AFE_CTL_MASK 0x1 |
| #define PDN_AFE_CTL_MASK_SFT (0x1 << 7) |
| #define PDN_DAC_CTL_SFT 6 |
| #define PDN_DAC_CTL_MASK 0x1 |
| #define PDN_DAC_CTL_MASK_SFT (0x1 << 6) |
| #define PDN_ADDA6_ADC_CTL_SFT 4 |
| #define PDN_ADDA6_ADC_CTL_MASK 0x1 |
| #define PDN_ADDA6_ADC_CTL_MASK_SFT (0x1 << 4) |
| #define PDN_I2S_DL_CTL_SFT 3 |
| #define PDN_I2S_DL_CTL_MASK 0x1 |
| #define PDN_I2S_DL_CTL_MASK_SFT (0x1 << 3) |
| #define PWR_CLK_DIS_CTL_SFT 2 |
| #define PWR_CLK_DIS_CTL_MASK 0x1 |
| #define PWR_CLK_DIS_CTL_MASK_SFT (0x1 << 2) |
| #define PDN_AFE_TESTMODEL_CTL_SFT 1 |
| #define PDN_AFE_TESTMODEL_CTL_MASK 0x1 |
| #define PDN_AFE_TESTMODEL_CTL_MASK_SFT (0x1 << 1) |
| #define PDN_RESERVED_SFT 0 |
| #define PDN_RESERVED_MASK 0x1 |
| #define PDN_RESERVED_MASK_SFT (0x1 << 0) |
| |
| /* AUDIO_TOP_CON1 */ |
| #define PDN_STF_CTL_SFT 7 |
| #define PDN_STF_CTL_MASK 0x1 |
| #define PDN_STF_CTL_MASK_SFT (0x1 << 7) |
| #define PDN_TDM_CTL_SFT 6 |
| #define PDN_TDM_CTL_MASK 0x1 |
| #define PDN_TDM_CTL_MASK_SFT (0x1 << 6) |
| #define PDN_ADC_HIRES_CTL_SFT 5 |
| #define PDN_ADC_HIRES_CTL_MASK 0x1 |
| #define PDN_ADC_HIRES_CTL_MASK_SFT (0x1 << 5) |
| #define PDN_ADDA6_ADC_HIRES_CTL_SFT 4 |
| #define PDN_ADDA6_ADC_HIRES_CTL_MASK 0x1 |
| #define PDN_ADDA6_ADC_HIRES_CTL_MASK_SFT (0x1 << 4) |
| #define PDN_GASRC4_CTL_SFT 3 |
| #define PDN_GASRC4_CTL_MASK 0x1 |
| #define PDN_GASRC4_CTL_MASK_SFT (0x1 << 3) |
| #define PDN_GASRC3_CTL_SFT 2 |
| #define PDN_GASRC3_CTL_MASK 0x1 |
| #define PDN_GASRC3_CTL_MASK_SFT (0x1 << 2) |
| #define PDN_GASRC2_CTL_SFT 1 |
| #define PDN_GASRC2_CTL_MASK 0x1 |
| #define PDN_GASRC2_CTL_MASK_SFT (0x1 << 1) |
| #define PDN_GASRC1_CTL_SFT 0 |
| #define PDN_GASRC1_CTL_MASK 0x1 |
| #define PDN_GASRC1_CTL_MASK_SFT (0x1 << 0) |
| |
| /* AUDIO_TOP_CON2 */ |
| #define PDN_DAC_NLE_CTL_SFT 7 |
| #define PDN_DAC_NLE_CTL_MASK 0x1 |
| #define PDN_DAC_NLE_CTL_MASK_SFT (0x1 << 7) |
| #define PDN_DAC2_PREDIS_CTL_SFT 6 |
| #define PDN_DAC2_PREDIS_CTL_MASK 0x1 |
| #define PDN_DAC2_PREDIS_CTL_MASK_SFT (0x1 << 6) |
| #define PDN_DAC_PREDIS_CTL_SFT 5 |
| #define PDN_DAC_PREDIS_CTL_MASK 0x1 |
| #define PDN_DAC_PREDIS_CTL_MASK_SFT (0x1 << 5) |
| #define PDN_DAC2_TML_CTL_SFT 4 |
| #define PDN_DAC2_TML_CTL_MASK 0x1 |
| #define PDN_DAC2_TML_CTL_MASK_SFT (0x1 << 4) |
| #define PDN_DAC_TML_CTL_SFT 3 |
| #define PDN_DAC_TML_CTL_MASK 0x1 |
| #define PDN_DAC_TML_CTL_MASK_SFT (0x1 << 3) |
| #define PDN_DAC2_HIRES_CTL_SFT 2 |
| #define PDN_DAC2_HIRES_CTL_MASK 0x1 |
| #define PDN_DAC2_HIRES_CTL_MASK_SFT (0x1 << 2) |
| #define PDN_DAC_HIRES_CTL_SFT 1 |
| #define PDN_DAC_HIRES_CTL_MASK 0x1 |
| #define PDN_DAC_HIRES_CTL_MASK_SFT (0x1 << 1) |
| #define PDN_DAC2_CTL_SFT 0 |
| #define PDN_DAC2_CTL_MASK 0x1 |
| #define PDN_DAC2_CTL_MASK_SFT (0x1 << 0) |
| |
| /* AUDIO_TOP_CON3 */ |
| #define PDN_HW_GAIN_CTL_SFT 1 |
| #define PDN_HW_GAIN_CTL_MASK 0x1 |
| #define PDN_HW_GAIN_CTL_MASK_SFT (0x1 << 1) |
| #define PDN_NCP_CTL_SFT 0 |
| #define PDN_NCP_CTL_MASK 0x1 |
| #define PDN_NCP_CTL_MASK_SFT (0x1 << 0) |
| |
| /* AFE_TOP_CON0 */ |
| #define DL_SINE_ON_SFT 1 |
| #define DL_SINE_ON_MASK 0x1 |
| #define DL_SINE_ON_MASK_SFT (0x1 << 1) |
| #define AFE_ON_SFT 0 |
| #define AFE_ON_MASK 0x1 |
| #define AFE_ON_MASK_SFT (0x1 << 0) |
| |
| /* AFE_MON_DEBUG0 */ |
| #define AFE_MON_SEL_SFT 0 |
| #define AFE_MON_SEL_MASK 0xff |
| #define AFE_MON_SEL_MASK_SFT (0xff << 0) |
| |
| /* AFE_MON_DEBUG1 */ |
| #define AUDIO_SYS_TOP_MON_SWAP_SFT 6 |
| #define AUDIO_SYS_TOP_MON_SWAP_MASK 0x3 |
| #define AUDIO_SYS_TOP_MON_SWAP_MASK_SFT (0x3 << 6) |
| #define AUDIO_SYS_TOP_MON_SEL_SFT 0 |
| #define AUDIO_SYS_TOP_MON_SEL_MASK 0x3f |
| #define AUDIO_SYS_TOP_MON_SEL_MASK_SFT (0x3f << 0) |
| |
| /* AFE_MTKAIF_MUX_CFG_H */ |
| #define RG_ADDA6_EN_SEL_SFT 4 |
| #define RG_ADDA6_EN_SEL_MASK 0x1 |
| #define RG_ADDA6_EN_SEL_MASK_SFT (0x1 << 4) |
| #define RG_ADDA6_CH2_SEL_SFT 2 |
| #define RG_ADDA6_CH2_SEL_MASK 0x3 |
| #define RG_ADDA6_CH2_SEL_MASK_SFT (0x3 << 2) |
| #define RG_ADDA6_CH1_SEL_SFT 0 |
| #define RG_ADDA6_CH1_SEL_MASK 0x3 |
| #define RG_ADDA6_CH1_SEL_MASK_SFT (0x3 << 0) |
| |
| /* AFE_MTKAIF_MUX_CFG */ |
| #define RG_ADDA_EN_SEL_SFT 4 |
| #define RG_ADDA_EN_SEL_MASK 0x1 |
| #define RG_ADDA_EN_SEL_MASK_SFT (0x1 << 4) |
| #define RG_ADDA_CH2_SEL_SFT 2 |
| #define RG_ADDA_CH2_SEL_MASK 0x3 |
| #define RG_ADDA_CH2_SEL_MASK_SFT (0x3 << 2) |
| #define RG_ADDA_CH1_SEL_SFT 0 |
| #define RG_ADDA_CH1_SEL_MASK 0x3 |
| #define RG_ADDA_CH1_SEL_MASK_SFT (0x3 << 0) |
| |
| /* AFE_SINEGEN_CON0 */ |
| #define SINEGEN_DAC_EN_SFT 2 |
| #define SINEGEN_DAC_EN_MASK 0x1 |
| #define SINEGEN_DAC_EN_MASK_SFT (0x1 << 2) |
| #define SINEGEN_MUTE_SW_CH2_SFT 1 |
| #define SINEGEN_MUTE_SW_CH2_MASK 0x1 |
| #define SINEGEN_MUTE_SW_CH2_MASK_SFT (0x1 << 1) |
| #define SINEGEN_MUTE_SW_CH1_SFT 0 |
| #define SINEGEN_MUTE_SW_CH1_MASK 0x1 |
| #define SINEGEN_MUTE_SW_CH1_MASK_SFT (0x1 << 0) |
| |
| /* AFE_SINEGEN_CON1 */ |
| #define SINEGEN_SINE_MODE_CH2_SFT 4 |
| #define SINEGEN_SINE_MODE_CH2_MASK 0xf |
| #define SINEGEN_SINE_MODE_CH2_MASK_SFT (0xf << 4) |
| #define SINEGEN_SINE_MODE_CH1_SFT 0 |
| #define SINEGEN_SINE_MODE_CH1_MASK 0xf |
| #define SINEGEN_SINE_MODE_CH1_MASK_SFT (0xf << 0) |
| |
| /* AFE_SINEGEN_CON2 */ |
| #define SINEGEN_INNER_LOOP_BACK_MODE_SFT 0 |
| #define SINEGEN_INNER_LOOP_BACK_MODE_MASK 0x3f |
| #define SINEGEN_INNER_LOOP_BACK_MODE_MASK_SFT (0x3f << 0) |
| |
| /* AFE_SINEGEN_CON3 */ |
| #define SINEGEN_AMP_DIV_CH1_SFT 5 |
| #define SINEGEN_AMP_DIV_CH1_MASK 0x7 |
| #define SINEGEN_AMP_DIV_CH1_MASK_SFT (0x7 << 5) |
| #define SINEGEN_FREQ_DIV_CH1_SFT 0 |
| #define SINEGEN_FREQ_DIV_CH1_MASK 0x1f |
| #define SINEGEN_FREQ_DIV_CH1_MASK_SFT (0x1f << 0) |
| |
| /* AFE_SINEGEN_CON4 */ |
| #define SINEGEN_AMP_DIV_CH2_SFT 5 |
| #define SINEGEN_AMP_DIV_CH2_MASK 0x7 |
| #define SINEGEN_AMP_DIV_CH2_MASK_SFT (0x7 << 5) |
| #define SINEGEN_FREQ_DIV_CH2_SFT 0 |
| #define SINEGEN_FREQ_DIV_CH2_MASK 0x1f |
| #define SINEGEN_FREQ_DIV_CH2_MASK_SFT (0x1f << 0) |
| |
| /* AFE_STF_CON0 */ |
| #define STF_SLT_CNT_FLAG_RESET_SFT 7 |
| #define STF_SLT_CNT_FLAG_RESET_MASK 0x1 |
| #define STF_SLT_CNT_FLAG_RESET_MASK_SFT (0x1 << 7) |
| #define STF_SLT_CNT_THD_H_SFT 3 |
| #define STF_SLT_CNT_THD_H_MASK 0xf |
| #define STF_SLT_CNT_THD_H_MASK_SFT (0xf << 3) |
| #define STF_ODD_MODE_SFT 1 |
| #define STF_ODD_MODE_MASK 0x1 |
| #define STF_ODD_MODE_MASK_SFT (0x1 << 1) |
| #define STF_ON_SFT 0 |
| #define STF_ON_MASK 0x1 |
| #define STF_ON_MASK_SFT (0x1 << 0) |
| |
| /* AFE_STF_CON0_M */ |
| #define STF_SLT_CNT_THD_SFT 0 |
| #define STF_SLT_CNT_THD_MASK 0xff |
| #define STF_SLT_CNT_THD_MASK_SFT (0xff << 0) |
| |
| /* AFE_STF_CON0_H */ |
| #define STF_HALF_TAP_NUM_SFT 0 |
| #define STF_HALF_TAP_NUM_MASK 0x3f |
| #define STF_HALF_TAP_NUM_MASK_SFT (0x3f << 0) |
| |
| /* AFE_STF_CON1 */ |
| #define STF_BYPASS_MODE_DL23_SFT 3 |
| #define STF_BYPASS_MODE_DL23_MASK 0x1 |
| #define STF_BYPASS_MODE_DL23_MASK_SFT (0x1 << 3) |
| #define STF_BYPASS_MODE_DL01_SFT 2 |
| #define STF_BYPASS_MODE_DL01_MASK 0x1 |
| #define STF_BYPASS_MODE_DL01_MASK_SFT (0x1 << 2) |
| #define STF_SOURCE_SEL_SFT 0 |
| #define STF_SOURCE_SEL_MASK 0x3 |
| #define STF_SOURCE_SEL_MASK_SFT (0x3 << 0) |
| |
| /* AFE_STF_COEFF */ |
| #define STF_COEFFICIENT_SFT 0 |
| #define STF_COEFFICIENT_MASK 0xff |
| #define STF_COEFFICIENT_MASK_SFT (0xff << 0) |
| |
| /* AFE_STF_COEFF_M */ |
| #define STF_COEFFICIENT_H_SFT 0 |
| #define STF_COEFFICIENT_H_MASK 0xff |
| #define STF_COEFFICIENT_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_STF_COEFF_H */ |
| #define STF_COEFFICIENT_ADDR_SFT 0 |
| #define STF_COEFFICIENT_ADDR_MASK 0x1f |
| #define STF_COEFFICIENT_ADDR_MASK_SFT (0x1f << 0) |
| |
| /* AFE_STF_GAIN */ |
| #define STF_GAIN_SFT 0 |
| #define STF_GAIN_MASK 0xff |
| #define STF_GAIN_MASK_SFT (0xff << 0) |
| |
| /* AFE_STF_GAIN_M */ |
| #define STF_GAIN_H_SFT 0 |
| #define STF_GAIN_H_MASK 0xff |
| #define STF_GAIN_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_STF_GAIN_H */ |
| #define STF_POSITIVE_GAIN_SFT 0 |
| #define STF_POSITIVE_GAIN_MASK 0x7 |
| #define STF_POSITIVE_GAIN_MASK_SFT (0x7 << 0) |
| |
| /* AFE_STF_COEFF_RD */ |
| #define STF_COEFFICIENT_ADDR_RD_SFT 0 |
| #define STF_COEFFICIENT_ADDR_RD_MASK 0x1f |
| #define STF_COEFFICIENT_ADDR_RD_MASK_SFT (0x1f << 0) |
| |
| /* AFE_STF_MON */ |
| #define STF_COEFF_CUR_SFT 0 |
| #define STF_COEFF_CUR_MASK 0xff |
| #define STF_COEFF_CUR_MASK_SFT (0xff << 0) |
| |
| /* AFE_STF_MON_M */ |
| #define STF_COEFF_CUR_H_SFT 0 |
| #define STF_COEFF_CUR_H_MASK 0xff |
| #define STF_COEFF_CUR_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_STF_MON_H */ |
| #define STF_SLT_CNT_SFT 0 |
| #define STF_SLT_CNT_MASK 0xff |
| #define STF_SLT_CNT_MASK_SFT (0xff << 0) |
| |
| /* AFE_STF_MON_H1 */ |
| #define STF_R_RDY_SFT 6 |
| #define STF_R_RDY_MASK 0x1 |
| #define STF_R_RDY_MASK_SFT (0x1 << 6) |
| #define STF_W_RDY_SFT 5 |
| #define STF_W_RDY_MASK 0x1 |
| #define STF_W_RDY_MASK_SFT (0x1 << 5) |
| #define STF_SLT_CNT_FLAG_SFT 4 |
| #define STF_SLT_CNT_FLAG_MASK 0x1 |
| #define STF_SLT_CNT_FLAG_MASK_SFT (0x1 << 4) |
| #define STF_SLT_CNT_H_SFT 0 |
| #define STF_SLT_CNT_H_MASK 0xf |
| #define STF_SLT_CNT_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_NCP_CFG0 */ |
| #define RG_NCP_DITHER_EN_SFT 7 |
| #define RG_NCP_DITHER_EN_MASK 0x1 |
| #define RG_NCP_DITHER_EN_MASK_SFT (0x1 << 7) |
| #define RG_NCP_DITHER_FIXED_CK0_ACK1_2P_SFT 4 |
| #define RG_NCP_DITHER_FIXED_CK0_ACK1_2P_MASK 0x7 |
| #define RG_NCP_DITHER_FIXED_CK0_ACK1_2P_MASK_SFT (0x7 << 4) |
| #define RG_NCP_DITHER_FIXED_CK0_ACK2_2P_SFT 1 |
| #define RG_NCP_DITHER_FIXED_CK0_ACK2_2P_MASK 0x7 |
| #define RG_NCP_DITHER_FIXED_CK0_ACK2_2P_MASK_SFT (0x7 << 1) |
| #define RG_NCP_ON_SFT 0 |
| #define RG_NCP_ON_MASK 0x1 |
| #define RG_NCP_ON_MASK_SFT (0x1 << 0) |
| |
| /* AFE_NCP_CFG1 */ |
| #define RG_NCP_CK1_VALID_CNT_SFT 1 |
| #define RG_NCP_CK1_VALID_CNT_MASK 0x7f |
| #define RG_NCP_CK1_VALID_CNT_MASK_SFT (0x7f << 1) |
| #define RG_NCP_ADITH_SFT 0 |
| #define RG_NCP_ADITH_MASK 0x1 |
| #define RG_NCP_ADITH_MASK_SFT (0x1 << 0) |
| |
| /* AFE_NCP_CFG2 */ |
| #define RG_Y_VAL_CFG_SFT 0 |
| #define RG_Y_VAL_CFG_MASK 0x7f |
| #define RG_Y_VAL_CFG_MASK_SFT (0x7f << 0) |
| |
| /* AFE_NCP_CFG3 */ |
| #define RG_XY_VAL_CFG_EN_SFT 7 |
| #define RG_XY_VAL_CFG_EN_MASK 0x1 |
| #define RG_XY_VAL_CFG_EN_MASK_SFT (0x1 << 7) |
| #define RG_X_VAL_CFG_SFT 0 |
| #define RG_X_VAL_CFG_MASK 0x7f |
| #define RG_X_VAL_CFG_MASK_SFT (0x7f << 0) |
| |
| /* AFE_NCP_CFG4 */ |
| #define RG_NCP_NONCLK_SET_SFT 1 |
| #define RG_NCP_NONCLK_SET_MASK 0x1 |
| #define RG_NCP_NONCLK_SET_MASK_SFT (0x1 << 1) |
| #define RG_NCP_PDDIS_EN_SFT 0 |
| #define RG_NCP_PDDIS_EN_MASK 0x1 |
| #define RG_NCP_PDDIS_EN_MASK_SFT (0x1 << 0) |
| |
| /* AFE_TOP_DEBUG0 */ |
| #define DL_DEBUG_SOURCE_SEL_SFT 6 |
| #define DL_DEBUG_SOURCE_SEL_MASK 0x3 |
| #define DL_DEBUG_SOURCE_SEL_MASK_SFT (0x3 << 6) |
| #define GASRC34_OUT_1X_DEBUG_SOURCE_SEL_SFT 5 |
| #define GASRC34_OUT_1X_DEBUG_SOURCE_SEL_MASK 0x1 |
| #define GASRC34_OUT_1X_DEBUG_SOURCE_SEL_MASK_SFT (0x1 << 5) |
| #define GASRC12_IN_1X_DEBUG_SOURCE_SEL_SFT 4 |
| #define GASRC12_IN_1X_DEBUG_SOURCE_SEL_MASK 0x1 |
| #define GASRC12_IN_1X_DEBUG_SOURCE_SEL_MASK_SFT (0x1 << 4) |
| #define STF_DEBUG_SOURCE_SEL_SFT 2 |
| #define STF_DEBUG_SOURCE_SEL_MASK 0x3 |
| #define STF_DEBUG_SOURCE_SEL_MASK_SFT (0x3 << 2) |
| #define GASRC34_DEBUG_SOURCE_SEL_SFT 0 |
| #define GASRC34_DEBUG_SOURCE_SEL_MASK 0x3 |
| #define GASRC34_DEBUG_SOURCE_SEL_MASK_SFT (0x3 << 0) |
| |
| /* AFE_MTKAIF_IN_MUX_CFG */ |
| #define RG_ADDA6_IN_CH2_SEL_SFT 6 |
| #define RG_ADDA6_IN_CH2_SEL_MASK 0x3 |
| #define RG_ADDA6_IN_CH2_SEL_MASK_SFT (0x3 << 6) |
| #define RG_ADDA6_IN_CH1_SEL_SFT 4 |
| #define RG_ADDA6_IN_CH1_SEL_MASK 0x3 |
| #define RG_ADDA6_IN_CH1_SEL_MASK_SFT (0x3 << 4) |
| #define RG_ADDA_IN_CH2_SEL_SFT 2 |
| #define RG_ADDA_IN_CH2_SEL_MASK 0x3 |
| #define RG_ADDA_IN_CH2_SEL_MASK_SFT (0x3 << 2) |
| #define RG_ADDA_IN_CH1_SEL_SFT 0 |
| #define RG_ADDA_IN_CH1_SEL_MASK 0x3 |
| #define RG_ADDA_IN_CH1_SEL_MASK_SFT (0x3 << 0) |
| |
| /* AUDIO_DIG_2ND_DSN_ID */ |
| #define AUDIO_DIG_2ND_ANA_ID_SFT 0 |
| #define AUDIO_DIG_2ND_ANA_ID_MASK 0xff |
| #define AUDIO_DIG_2ND_ANA_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_2ND_DSN_ID_H */ |
| #define AUDIO_DIG_2ND_DIG_ID_SFT 0 |
| #define AUDIO_DIG_2ND_DIG_ID_MASK 0xff |
| #define AUDIO_DIG_2ND_DIG_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_2ND_DSN_REV0 */ |
| #define AUDIO_DIG_2ND_ANA_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_2ND_ANA_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_2ND_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_2ND_ANA_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_2ND_ANA_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_2ND_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_2ND_DSN_REV0_H */ |
| #define AUDIO_DIG_2ND_DIG_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_2ND_DIG_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_2ND_DIG_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_2ND_DIG_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_2ND_DIG_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_2ND_DIG_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_2ND_DSN_DBI */ |
| #define AUDIO_DIG_2ND_DSN_CBS_SFT 0 |
| #define AUDIO_DIG_2ND_DSN_CBS_MASK 0x3 |
| #define AUDIO_DIG_2ND_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDIO_DIG_2ND_DSN_BIX_SFT 2 |
| #define AUDIO_DIG_2ND_DSN_BIX_MASK 0x3 |
| #define AUDIO_DIG_2ND_DSN_BIX_MASK_SFT (0x3 << 2) |
| |
| /* AUDIO_DIG_2ND_DSN_DBI_H */ |
| #define AUDIO_DIG_2_ESP_SFT 0 |
| #define AUDIO_DIG_2_ESP_MASK 0xff |
| #define AUDIO_DIG_2_ESP_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_2ND_DSN_DXI */ |
| #define AUDIO_DIG_2ND_DSN_FPI_SFT 0 |
| #define AUDIO_DIG_2ND_DSN_FPI_MASK 0xff |
| #define AUDIO_DIG_2ND_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* GENERAL_ASRC_EN_ON */ |
| #define GASRC4_EN_ON_SFT 3 |
| #define GASRC4_EN_ON_MASK 0x1 |
| #define GASRC4_EN_ON_MASK_SFT (0x1 << 3) |
| #define GASRC3_EN_ON_SFT 2 |
| #define GASRC3_EN_ON_MASK 0x1 |
| #define GASRC3_EN_ON_MASK_SFT (0x1 << 2) |
| #define GASRC2_EN_ON_SFT 1 |
| #define GASRC2_EN_ON_MASK 0x1 |
| #define GASRC2_EN_ON_MASK_SFT (0x1 << 1) |
| #define GASRC1_EN_ON_SFT 0 |
| #define GASRC1_EN_ON_MASK 0x1 |
| #define GASRC1_EN_ON_MASK_SFT (0x1 << 0) |
| |
| /* GASRC1_MODE */ |
| #define GASRC1_OUT_MODE_SFT 4 |
| #define GASRC1_OUT_MODE_MASK 0xf |
| #define GASRC1_OUT_MODE_MASK_SFT (0xf << 4) |
| #define GASRC1_IN_MODE_SFT 0 |
| #define GASRC1_IN_MODE_MASK 0xf |
| #define GASRC1_IN_MODE_MASK_SFT (0xf << 0) |
| |
| /* GASRC2_MODE */ |
| #define GASRC2_OUT_MODE_SFT 4 |
| #define GASRC2_OUT_MODE_MASK 0xf |
| #define GASRC2_OUT_MODE_MASK_SFT (0xf << 4) |
| #define GASRC2_IN_MODE_SFT 0 |
| #define GASRC2_IN_MODE_MASK 0xf |
| #define GASRC2_IN_MODE_MASK_SFT (0xf << 0) |
| |
| /* GASRC3_MODE */ |
| #define GASRC3_OUT_MODE_SFT 4 |
| #define GASRC3_OUT_MODE_MASK 0xf |
| #define GASRC3_OUT_MODE_MASK_SFT (0xf << 4) |
| #define GASRC3_IN_MODE_SFT 0 |
| #define GASRC3_IN_MODE_MASK 0xf |
| #define GASRC3_IN_MODE_MASK_SFT (0xf << 0) |
| |
| /* GASRC4_MODE */ |
| #define GASRC4_OUT_MODE_SFT 4 |
| #define GASRC4_OUT_MODE_MASK 0xf |
| #define GASRC4_OUT_MODE_MASK_SFT (0xf << 4) |
| #define GASRC4_IN_MODE_SFT 0 |
| #define GASRC4_IN_MODE_MASK 0xf |
| #define GASRC4_IN_MODE_MASK_SFT (0xf << 0) |
| |
| /* AFE_GASRC1_CON0 */ |
| #define GASRC1_CHSET_STR_CLR_SFT 4 |
| #define GASRC1_CHSET_STR_CLR_MASK 0x1 |
| #define GASRC1_CHSET_STR_CLR_MASK_SFT (0x1 << 4) |
| #define GASRC1_COEFF_SRAM_CTRL_SFT 1 |
| #define GASRC1_COEFF_SRAM_CTRL_MASK 0x1 |
| #define GASRC1_COEFF_SRAM_CTRL_MASK_SFT (0x1 << 1) |
| #define GASRC1_ASM_ON_SFT 0 |
| #define GASRC1_ASM_ON_MASK 0x1 |
| #define GASRC1_ASM_ON_MASK_SFT (0x1 << 0) |
| |
| /* AFE_GASRC1_CON1 */ |
| #define GASRC1_RESULT_SEL_SFT 0 |
| #define GASRC1_RESULT_SEL_MASK 0x7 |
| #define GASRC1_RESULT_SEL_MASK_SFT (0x7 << 0) |
| |
| /* AFE_GASRC1_CON2 */ |
| #define GASRC1_CHSET_STR_CLR_RD_SFT 5 |
| #define GASRC1_CHSET_STR_CLR_RD_MASK 0x1 |
| #define GASRC1_CHSET_STR_CLR_RD_MASK_SFT (0x1 << 5) |
| #define GASRC1_CHSET_ON_RD_SFT 2 |
| #define GASRC1_CHSET_ON_RD_MASK 0x1 |
| #define GASRC1_CHSET_ON_RD_MASK_SFT (0x1 << 2) |
| #define GASRC1_COEFF_SRAM_CTRL_RD_SFT 1 |
| #define GASRC1_COEFF_SRAM_CTRL_RD_MASK 0x1 |
| #define GASRC1_COEFF_SRAM_CTRL_RD_MASK_SFT (0x1 << 1) |
| #define GASRC1_ASM_ON_RD_SFT 0 |
| #define GASRC1_ASM_ON_RD_MASK 0x1 |
| #define GASRC1_ASM_ON_RD_MASK_SFT (0x1 << 0) |
| |
| /* AFE_GASRC1_CON2_M */ |
| #define GASRC1_CHSET_IIR_EN_SFT 3 |
| #define GASRC1_CHSET_IIR_EN_MASK 0x1 |
| #define GASRC1_CHSET_IIR_EN_MASK_SFT (0x1 << 3) |
| #define GASRC1_CHSET_IIR_STAGE_SFT 0 |
| #define GASRC1_CHSET_IIR_STAGE_MASK 0x7 |
| #define GASRC1_CHSET_IIR_STAGE_MASK_SFT (0x7 << 0) |
| |
| /* AFE_GASRC1_CON2_H */ |
| #define GASRC1_CHSET_O16BIT_SFT 3 |
| #define GASRC1_CHSET_O16BIT_MASK 0x1 |
| #define GASRC1_CHSET_O16BIT_MASK_SFT (0x1 << 3) |
| #define GASRC1_CHSET_CLR_IIR_HISTORY_SFT 1 |
| #define GASRC1_CHSET_CLR_IIR_HISTORY_MASK 0x1 |
| #define GASRC1_CHSET_CLR_IIR_HISTORY_MASK_SFT (0x1 << 1) |
| #define GASRC1_CHSET_IS_MONO_SFT 0 |
| #define GASRC1_CHSET_IS_MONO_MASK 0x1 |
| #define GASRC1_CHSET_IS_MONO_MASK_SFT (0x1 << 0) |
| |
| /* AFE_GASRC1_CON3 */ |
| #define GASRC1_ASM_FREQ_4_SFT 0 |
| #define GASRC1_ASM_FREQ_4_MASK 0xff |
| #define GASRC1_ASM_FREQ_4_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON3_M */ |
| #define GASRC1_ASM_FREQ_4_M_SFT 0 |
| #define GASRC1_ASM_FREQ_4_M_MASK 0xff |
| #define GASRC1_ASM_FREQ_4_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON3_H */ |
| #define GASRC1_ASM_FREQ_4_H_SFT 0 |
| #define GASRC1_ASM_FREQ_4_H_MASK 0xff |
| #define GASRC1_ASM_FREQ_4_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON4 */ |
| #define GASRC1_ASM_FREQ_5_SFT 0 |
| #define GASRC1_ASM_FREQ_5_MASK 0xff |
| #define GASRC1_ASM_FREQ_5_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON4_M */ |
| #define GASRC1_ASM_FREQ_5_M_SFT 0 |
| #define GASRC1_ASM_FREQ_5_M_MASK 0xff |
| #define GASRC1_ASM_FREQ_5_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON4_H */ |
| #define GASRC1_ASM_FREQ_5_H_SFT 0 |
| #define GASRC1_ASM_FREQ_5_H_MASK 0xff |
| #define GASRC1_ASM_FREQ_5_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON5 */ |
| #define GASRC1_FREQ_CALI_BP_DGL_SFT 7 |
| #define GASRC1_FREQ_CALI_BP_DGL_MASK 0x1 |
| #define GASRC1_FREQ_CALI_BP_DGL_MASK_SFT (0x1 << 7) |
| #define GASRC1_FREQ_CALI_MAX_GWIDTH_SFT 4 |
| #define GASRC1_FREQ_CALI_MAX_GWIDTH_MASK 0x7 |
| #define GASRC1_FREQ_CALI_MAX_GWIDTH_MASK_SFT (0x7 << 4) |
| #define GASRC1_AUTO_TUNE_FREQ4_SFT 3 |
| #define GASRC1_AUTO_TUNE_FREQ4_MASK 0x1 |
| #define GASRC1_AUTO_TUNE_FREQ4_MASK_SFT (0x1 << 3) |
| #define GASRC1_FREQ_CALI_AUTO_RESTART_SFT 2 |
| #define GASRC1_FREQ_CALI_AUTO_RESTART_MASK 0x1 |
| #define GASRC1_FREQ_CALI_AUTO_RESTART_MASK_SFT (0x1 << 2) |
| #define GASRC1_CALI_USE_FREQ_OUT_SFT 1 |
| #define GASRC1_CALI_USE_FREQ_OUT_MASK 0x1 |
| #define GASRC1_CALI_USE_FREQ_OUT_MASK_SFT (0x1 << 1) |
| #define GASRC1_CALI_EN_SFT 0 |
| #define GASRC1_CALI_EN_MASK 0x1 |
| #define GASRC1_CALI_EN_MASK_SFT (0x1 << 0) |
| |
| /* AFE_GASRC1_CON5_M */ |
| #define GASRC1_FREQ_CALI_AUTORST_EN_SFT 6 |
| #define GASRC1_FREQ_CALI_AUTORST_EN_MASK 0x1 |
| #define GASRC1_FREQ_CALI_AUTORST_EN_MASK_SFT (0x1 << 6) |
| #define GASRC1_FREQ_CALC_RUNNING_SFT 5 |
| #define GASRC1_FREQ_CALC_RUNNING_MASK 0x1 |
| #define GASRC1_FREQ_CALC_RUNNING_MASK_SFT (0x1 << 5) |
| #define GASRC1_AUTO_TUNE_FREQ5_SFT 4 |
| #define GASRC1_AUTO_TUNE_FREQ5_MASK 0x1 |
| #define GASRC1_AUTO_TUNE_FREQ5_MASK_SFT (0x1 << 4) |
| #define GASRC1_COMP_FREQ_RES_EN_SFT 3 |
| #define GASRC1_COMP_FREQ_RES_EN_MASK 0x1 |
| #define GASRC1_COMP_FREQ_RES_EN_MASK_SFT (0x1 << 3) |
| #define GASRC1_FREQ_CALI_SEL_SFT 0 |
| #define GASRC1_FREQ_CALI_SEL_MASK 0x3 |
| #define GASRC1_FREQ_CALI_SEL_MASK_SFT (0x3 << 0) |
| |
| /* AFE_GASRC1_CON5_H0 */ |
| #define GASRC1_FREQ_CALI_CYCLE_H0_SFT 0 |
| #define GASRC1_FREQ_CALI_CYCLE_H0_MASK 0xff |
| #define GASRC1_FREQ_CALI_CYCLE_H0_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON5_H1 */ |
| #define GASRC1_FREQ_CALI_CYCLE_H1_SFT 0 |
| #define GASRC1_FREQ_CALI_CYCLE_H1_MASK 0xff |
| #define GASRC1_FREQ_CALI_CYCLE_H1_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON6 */ |
| #define GASRC1_FREQ_CALC_DENOMINATOR_SFT 0 |
| #define GASRC1_FREQ_CALC_DENOMINATOR_MASK 0xff |
| #define GASRC1_FREQ_CALC_DENOMINATOR_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON6_M */ |
| #define GASRC1_FREQ_CALC_DENOMINATOR_M_SFT 0 |
| #define GASRC1_FREQ_CALC_DENOMINATOR_M_MASK 0xff |
| #define GASRC1_FREQ_CALC_DENOMINATOR_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON6_H */ |
| #define GASRC1_FREQ_CALC_DENOMINATOR_H_SFT 0 |
| #define GASRC1_FREQ_CALC_DENOMINATOR_H_MASK 0xff |
| #define GASRC1_FREQ_CALC_DENOMINATOR_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON7 */ |
| #define GASRC1_PRD_CALI_RESULT_RECORD_SFT 0 |
| #define GASRC1_PRD_CALI_RESULT_RECORD_MASK 0xff |
| #define GASRC1_PRD_CALI_RESULT_RECORD_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON7_M */ |
| #define GASRC1_PRD_CALI_RESULT_RECORD_M_SFT 0 |
| #define GASRC1_PRD_CALI_RESULT_RECORD_M_MASK 0xff |
| #define GASRC1_PRD_CALI_RESULT_RECORD_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON7_H */ |
| #define GASRC1_PRD_CALI_RESULT_RECORD_H_SFT 0 |
| #define GASRC1_PRD_CALI_RESULT_RECORD_H_MASK 0xff |
| #define GASRC1_PRD_CALI_RESULT_RECORD_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON8 */ |
| #define GASRC1_FREQ_CALI_RESULT_SFT 0 |
| #define GASRC1_FREQ_CALI_RESULT_MASK 0xff |
| #define GASRC1_FREQ_CALI_RESULT_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON8_M */ |
| #define GASRC1_FREQ_CALI_RESULT_M_SFT 0 |
| #define GASRC1_FREQ_CALI_RESULT_M_MASK 0xff |
| #define GASRC1_FREQ_CALI_RESULT_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON8_H */ |
| #define GASRC1_FREQ_CALI_RESULT_H_SFT 0 |
| #define GASRC1_FREQ_CALI_RESULT_H_MASK 0xff |
| #define GASRC1_FREQ_CALI_RESULT_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON9 */ |
| #define GASRC1_FREQ_CALI_AUTORST_TH_HIGH_SFT 0 |
| #define GASRC1_FREQ_CALI_AUTORST_TH_HIGH_MASK 0xff |
| #define GASRC1_FREQ_CALI_AUTORST_TH_HIGH_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON9_M */ |
| #define GASRC1_FREQ_CALI_AUTORST_TH_HIGH_M_SFT 0 |
| #define GASRC1_FREQ_CALI_AUTORST_TH_HIGH_M_MASK 0xff |
| #define GASRC1_FREQ_CALI_AUTORST_TH_HIGH_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON9_H */ |
| #define GASRC1_FREQ_CALI_AUTORST_TH_HIGH_H_SFT 0 |
| #define GASRC1_FREQ_CALI_AUTORST_TH_HIGH_H_MASK 0xff |
| #define GASRC1_FREQ_CALI_AUTORST_TH_HIGH_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON10 */ |
| #define GASRC1_FREQ_CALI_AUTORST_TH_LOW_SFT 0 |
| #define GASRC1_FREQ_CALI_AUTORST_TH_LOW_MASK 0xff |
| #define GASRC1_FREQ_CALI_AUTORST_TH_LOW_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON10_M */ |
| #define GASRC1_FREQ_CALI_AUTORST_TH_LOW_M_SFT 0 |
| #define GASRC1_FREQ_CALI_AUTORST_TH_LOW_M_MASK 0xff |
| #define GASRC1_FREQ_CALI_AUTORST_TH_LOW_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON10_H */ |
| #define GASRC1_FREQ_CALI_AUTORST_TH_LOW_H_SFT 0 |
| #define GASRC1_FREQ_CALI_AUTORST_TH_LOW_H_MASK 0xff |
| #define GASRC1_FREQ_CALI_AUTORST_TH_LOW_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON11 */ |
| #define GASRC1_RING_DBG_RD_SFT 0 |
| #define GASRC1_RING_DBG_RD_MASK 0xff |
| #define GASRC1_RING_DBG_RD_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON11_H */ |
| #define GASRC1_RING_DBG_RD_H_SFT 0 |
| #define GASRC1_RING_DBG_RD_H_MASK 0xff |
| #define GASRC1_RING_DBG_RD_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON12 */ |
| #define GASRC1_COEFF_SRAM_DATA_SFT 0 |
| #define GASRC1_COEFF_SRAM_DATA_MASK 0xff |
| #define GASRC1_COEFF_SRAM_DATA_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON12_M */ |
| #define GASRC1_COEFF_SRAM_DATA_M_SFT 0 |
| #define GASRC1_COEFF_SRAM_DATA_M_MASK 0xff |
| #define GASRC1_COEFF_SRAM_DATA_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON12_H */ |
| #define GASRC1_COEFF_SRAM_DATA_H_SFT 0 |
| #define GASRC1_COEFF_SRAM_DATA_H_MASK 0xff |
| #define GASRC1_COEFF_SRAM_DATA_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON13 */ |
| #define GASRC1_COEFF_SRAM_ADR_SFT 0 |
| #define GASRC1_COEFF_SRAM_ADR_MASK 0x3f |
| #define GASRC1_COEFF_SRAM_ADR_MASK_SFT (0x3f << 0) |
| |
| /* AFE_GASRC1_CON14 */ |
| #define GASRC1_COEFF_SRAM_DATA_RD_SFT 0 |
| #define GASRC1_COEFF_SRAM_DATA_RD_MASK 0xff |
| #define GASRC1_COEFF_SRAM_DATA_RD_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON14_M */ |
| #define GASRC1_COEFF_SRAM_DATA_M_RD_SFT 0 |
| #define GASRC1_COEFF_SRAM_DATA_M_RD_MASK 0xff |
| #define GASRC1_COEFF_SRAM_DATA_M_RD_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON14_H */ |
| #define GASRC1_COEFF_SRAM_DATA_H_RD_SFT 0 |
| #define GASRC1_COEFF_SRAM_DATA_H_RD_MASK 0xff |
| #define GASRC1_COEFF_SRAM_DATA_H_RD_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC1_CON15 */ |
| #define GASRC1_COEFF_SRAM_ADR_RD_SFT 0 |
| #define GASRC1_COEFF_SRAM_ADR_RD_MASK 0x3f |
| #define GASRC1_COEFF_SRAM_ADR_RD_MASK_SFT (0x3f << 0) |
| |
| /* AFE_GASRC2_CON0 */ |
| #define GASRC2_CHSET_STR_CLR_SFT 4 |
| #define GASRC2_CHSET_STR_CLR_MASK 0x1 |
| #define GASRC2_CHSET_STR_CLR_MASK_SFT (0x1 << 4) |
| #define GASRC2_COEFF_SRAM_CTRL_SFT 1 |
| #define GASRC2_COEFF_SRAM_CTRL_MASK 0x1 |
| #define GASRC2_COEFF_SRAM_CTRL_MASK_SFT (0x1 << 1) |
| #define GASRC2_ASM_ON_SFT 0 |
| #define GASRC2_ASM_ON_MASK 0x1 |
| #define GASRC2_ASM_ON_MASK_SFT (0x1 << 0) |
| |
| /* AFE_GASRC2_CON1 */ |
| #define GASRC2_RESULT_SEL_SFT 0 |
| #define GASRC2_RESULT_SEL_MASK 0x7 |
| #define GASRC2_RESULT_SEL_MASK_SFT (0x7 << 0) |
| |
| /* AFE_GASRC2_CON2 */ |
| #define GASRC2_CHSET_STR_CLR_RD_SFT 5 |
| #define GASRC2_CHSET_STR_CLR_RD_MASK 0x1 |
| #define GASRC2_CHSET_STR_CLR_RD_MASK_SFT (0x1 << 5) |
| #define GASRC2_CHSET_ON_RD_SFT 2 |
| #define GASRC2_CHSET_ON_RD_MASK 0x1 |
| #define GASRC2_CHSET_ON_RD_MASK_SFT (0x1 << 2) |
| #define GASRC2_COEFF_SRAM_CTRL_RD_SFT 1 |
| #define GASRC2_COEFF_SRAM_CTRL_RD_MASK 0x1 |
| #define GASRC2_COEFF_SRAM_CTRL_RD_MASK_SFT (0x1 << 1) |
| #define GASRC2_ASM_ON_RD_SFT 0 |
| #define GASRC2_ASM_ON_RD_MASK 0x1 |
| #define GASRC2_ASM_ON_RD_MASK_SFT (0x1 << 0) |
| |
| /* AFE_GASRC2_CON2_M */ |
| #define GASRC2_CHSET_IIR_EN_SFT 3 |
| #define GASRC2_CHSET_IIR_EN_MASK 0x1 |
| #define GASRC2_CHSET_IIR_EN_MASK_SFT (0x1 << 3) |
| #define GASRC2_CHSET_IIR_STAGE_SFT 0 |
| #define GASRC2_CHSET_IIR_STAGE_MASK 0x7 |
| #define GASRC2_CHSET_IIR_STAGE_MASK_SFT (0x7 << 0) |
| |
| /* AFE_GASRC2_CON2_H */ |
| #define GASRC2_CHSET_O16BIT_SFT 3 |
| #define GASRC2_CHSET_O16BIT_MASK 0x1 |
| #define GASRC2_CHSET_O16BIT_MASK_SFT (0x1 << 3) |
| #define GASRC2_CHSET_CLR_IIR_HISTORY_SFT 1 |
| #define GASRC2_CHSET_CLR_IIR_HISTORY_MASK 0x1 |
| #define GASRC2_CHSET_CLR_IIR_HISTORY_MASK_SFT (0x1 << 1) |
| #define GASRC2_CHSET_IS_MONO_SFT 0 |
| #define GASRC2_CHSET_IS_MONO_MASK 0x1 |
| #define GASRC2_CHSET_IS_MONO_MASK_SFT (0x1 << 0) |
| |
| /* AFE_GASRC2_CON3 */ |
| #define GASRC2_ASM_FREQ_4_SFT 0 |
| #define GASRC2_ASM_FREQ_4_MASK 0xff |
| #define GASRC2_ASM_FREQ_4_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON3_M */ |
| #define GASRC2_ASM_FREQ_4_M_SFT 0 |
| #define GASRC2_ASM_FREQ_4_M_MASK 0xff |
| #define GASRC2_ASM_FREQ_4_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON3_H */ |
| #define GASRC2_ASM_FREQ_4_H_SFT 0 |
| #define GASRC2_ASM_FREQ_4_H_MASK 0xff |
| #define GASRC2_ASM_FREQ_4_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON4 */ |
| #define GASRC2_ASM_FREQ_5_SFT 0 |
| #define GASRC2_ASM_FREQ_5_MASK 0xff |
| #define GASRC2_ASM_FREQ_5_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON4_M */ |
| #define GASRC2_ASM_FREQ_5_M_SFT 0 |
| #define GASRC2_ASM_FREQ_5_M_MASK 0xff |
| #define GASRC2_ASM_FREQ_5_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON4_H */ |
| #define GASRC2_ASM_FREQ_5_H_SFT 0 |
| #define GASRC2_ASM_FREQ_5_H_MASK 0xff |
| #define GASRC2_ASM_FREQ_5_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON5 */ |
| #define GASRC2_FREQ_CALI_BP_DGL_SFT 7 |
| #define GASRC2_FREQ_CALI_BP_DGL_MASK 0x1 |
| #define GASRC2_FREQ_CALI_BP_DGL_MASK_SFT (0x1 << 7) |
| #define GASRC2_FREQ_CALI_MAX_GWIDTH_SFT 4 |
| #define GASRC2_FREQ_CALI_MAX_GWIDTH_MASK 0x7 |
| #define GASRC2_FREQ_CALI_MAX_GWIDTH_MASK_SFT (0x7 << 4) |
| #define GASRC2_AUTO_TUNE_FREQ4_SFT 3 |
| #define GASRC2_AUTO_TUNE_FREQ4_MASK 0x1 |
| #define GASRC2_AUTO_TUNE_FREQ4_MASK_SFT (0x1 << 3) |
| #define GASRC2_FREQ_CALI_AUTO_RESTART_SFT 2 |
| #define GASRC2_FREQ_CALI_AUTO_RESTART_MASK 0x1 |
| #define GASRC2_FREQ_CALI_AUTO_RESTART_MASK_SFT (0x1 << 2) |
| #define GASRC2_CALI_USE_FREQ_OUT_SFT 1 |
| #define GASRC2_CALI_USE_FREQ_OUT_MASK 0x1 |
| #define GASRC2_CALI_USE_FREQ_OUT_MASK_SFT (0x1 << 1) |
| #define GASRC2_CALI_EN_SFT 0 |
| #define GASRC2_CALI_EN_MASK 0x1 |
| #define GASRC2_CALI_EN_MASK_SFT (0x1 << 0) |
| |
| /* AFE_GASRC2_CON5_M */ |
| #define GASRC2_FREQ_CALI_AUTORST_EN_SFT 6 |
| #define GASRC2_FREQ_CALI_AUTORST_EN_MASK 0x1 |
| #define GASRC2_FREQ_CALI_AUTORST_EN_MASK_SFT (0x1 << 6) |
| #define GASRC2_FREQ_CALC_RUNNING_SFT 5 |
| #define GASRC2_FREQ_CALC_RUNNING_MASK 0x1 |
| #define GASRC2_FREQ_CALC_RUNNING_MASK_SFT (0x1 << 5) |
| #define GASRC2_AUTO_TUNE_FREQ5_SFT 4 |
| #define GASRC2_AUTO_TUNE_FREQ5_MASK 0x1 |
| #define GASRC2_AUTO_TUNE_FREQ5_MASK_SFT (0x1 << 4) |
| #define GASRC2_COMP_FREQ_RES_EN_SFT 3 |
| #define GASRC2_COMP_FREQ_RES_EN_MASK 0x1 |
| #define GASRC2_COMP_FREQ_RES_EN_MASK_SFT (0x1 << 3) |
| #define GASRC2_FREQ_CALI_SEL_SFT 0 |
| #define GASRC2_FREQ_CALI_SEL_MASK 0x3 |
| #define GASRC2_FREQ_CALI_SEL_MASK_SFT (0x3 << 0) |
| |
| /* AFE_GASRC2_CON5_H0 */ |
| #define GASRC2_FREQ_CALI_CYCLE_H0_SFT 0 |
| #define GASRC2_FREQ_CALI_CYCLE_H0_MASK 0xff |
| #define GASRC2_FREQ_CALI_CYCLE_H0_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON5_H1 */ |
| #define GASRC2_FREQ_CALI_CYCLE_H1_SFT 0 |
| #define GASRC2_FREQ_CALI_CYCLE_H1_MASK 0xff |
| #define GASRC2_FREQ_CALI_CYCLE_H1_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON6 */ |
| #define GASRC2_FREQ_CALC_DENOMINATOR_SFT 0 |
| #define GASRC2_FREQ_CALC_DENOMINATOR_MASK 0xff |
| #define GASRC2_FREQ_CALC_DENOMINATOR_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON6_M */ |
| #define GASRC2_FREQ_CALC_DENOMINATOR_M_SFT 0 |
| #define GASRC2_FREQ_CALC_DENOMINATOR_M_MASK 0xff |
| #define GASRC2_FREQ_CALC_DENOMINATOR_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON6_H */ |
| #define GASRC2_FREQ_CALC_DENOMINATOR_H_SFT 0 |
| #define GASRC2_FREQ_CALC_DENOMINATOR_H_MASK 0xff |
| #define GASRC2_FREQ_CALC_DENOMINATOR_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON7 */ |
| #define GASRC2_PRD_CALI_RESULT_RECORD_SFT 0 |
| #define GASRC2_PRD_CALI_RESULT_RECORD_MASK 0xff |
| #define GASRC2_PRD_CALI_RESULT_RECORD_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON7_M */ |
| #define GASRC2_PRD_CALI_RESULT_RECORD_M_SFT 0 |
| #define GASRC2_PRD_CALI_RESULT_RECORD_M_MASK 0xff |
| #define GASRC2_PRD_CALI_RESULT_RECORD_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON7_H */ |
| #define GASRC2_PRD_CALI_RESULT_RECORD_H_SFT 0 |
| #define GASRC2_PRD_CALI_RESULT_RECORD_H_MASK 0xff |
| #define GASRC2_PRD_CALI_RESULT_RECORD_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON8 */ |
| #define GASRC2_FREQ_CALI_RESULT_SFT 0 |
| #define GASRC2_FREQ_CALI_RESULT_MASK 0xff |
| #define GASRC2_FREQ_CALI_RESULT_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON8_M */ |
| #define GASRC2_FREQ_CALI_RESULT_M_SFT 0 |
| #define GASRC2_FREQ_CALI_RESULT_M_MASK 0xff |
| #define GASRC2_FREQ_CALI_RESULT_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON8_H */ |
| #define GASRC2_FREQ_CALI_RESULT_H_SFT 0 |
| #define GASRC2_FREQ_CALI_RESULT_H_MASK 0xff |
| #define GASRC2_FREQ_CALI_RESULT_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON9 */ |
| #define GASRC2_FREQ_CALI_AUTORST_TH_HIGH_SFT 0 |
| #define GASRC2_FREQ_CALI_AUTORST_TH_HIGH_MASK 0xff |
| #define GASRC2_FREQ_CALI_AUTORST_TH_HIGH_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON9_M */ |
| #define GASRC2_FREQ_CALI_AUTORST_TH_HIGH_M_SFT 0 |
| #define GASRC2_FREQ_CALI_AUTORST_TH_HIGH_M_MASK 0xff |
| #define GASRC2_FREQ_CALI_AUTORST_TH_HIGH_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON9_H */ |
| #define GASRC2_FREQ_CALI_AUTORST_TH_HIGH_H_SFT 0 |
| #define GASRC2_FREQ_CALI_AUTORST_TH_HIGH_H_MASK 0xff |
| #define GASRC2_FREQ_CALI_AUTORST_TH_HIGH_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON10 */ |
| #define GASRC2_FREQ_CALI_AUTORST_TH_LOW_SFT 0 |
| #define GASRC2_FREQ_CALI_AUTORST_TH_LOW_MASK 0xff |
| #define GASRC2_FREQ_CALI_AUTORST_TH_LOW_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON10_M */ |
| #define GASRC2_FREQ_CALI_AUTORST_TH_LOW_M_SFT 0 |
| #define GASRC2_FREQ_CALI_AUTORST_TH_LOW_M_MASK 0xff |
| #define GASRC2_FREQ_CALI_AUTORST_TH_LOW_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON10_H */ |
| #define GASRC2_FREQ_CALI_AUTORST_TH_LOW_H_SFT 0 |
| #define GASRC2_FREQ_CALI_AUTORST_TH_LOW_H_MASK 0xff |
| #define GASRC2_FREQ_CALI_AUTORST_TH_LOW_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON11 */ |
| #define GASRC2_RING_DBG_RD_SFT 0 |
| #define GASRC2_RING_DBG_RD_MASK 0xff |
| #define GASRC2_RING_DBG_RD_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON11_H */ |
| #define GASRC2_RING_DBG_RD_H_SFT 0 |
| #define GASRC2_RING_DBG_RD_H_MASK 0xff |
| #define GASRC2_RING_DBG_RD_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON12 */ |
| #define GASRC2_COEFF_SRAM_DATA_SFT 0 |
| #define GASRC2_COEFF_SRAM_DATA_MASK 0xff |
| #define GASRC2_COEFF_SRAM_DATA_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON12_M */ |
| #define GASRC2_COEFF_SRAM_DATA_M_SFT 0 |
| #define GASRC2_COEFF_SRAM_DATA_M_MASK 0xff |
| #define GASRC2_COEFF_SRAM_DATA_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON12_H */ |
| #define GASRC2_COEFF_SRAM_DATA_H_SFT 0 |
| #define GASRC2_COEFF_SRAM_DATA_H_MASK 0xff |
| #define GASRC2_COEFF_SRAM_DATA_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON13 */ |
| #define GASRC2_COEFF_SRAM_ADR_SFT 0 |
| #define GASRC2_COEFF_SRAM_ADR_MASK 0x3f |
| #define GASRC2_COEFF_SRAM_ADR_MASK_SFT (0x3f << 0) |
| |
| /* AFE_GASRC2_CON14 */ |
| #define GASRC2_COEFF_SRAM_DATA_RD_SFT 0 |
| #define GASRC2_COEFF_SRAM_DATA_RD_MASK 0xff |
| #define GASRC2_COEFF_SRAM_DATA_RD_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON14_M */ |
| #define GASRC2_COEFF_SRAM_DATA_M_RD_SFT 0 |
| #define GASRC2_COEFF_SRAM_DATA_M_RD_MASK 0xff |
| #define GASRC2_COEFF_SRAM_DATA_M_RD_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON14_H */ |
| #define GASRC2_COEFF_SRAM_DATA_H_RD_SFT 0 |
| #define GASRC2_COEFF_SRAM_DATA_H_RD_MASK 0xff |
| #define GASRC2_COEFF_SRAM_DATA_H_RD_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC2_CON15 */ |
| #define GASRC2_COEFF_SRAM_ADR_RD_SFT 0 |
| #define GASRC2_COEFF_SRAM_ADR_RD_MASK 0x3f |
| #define GASRC2_COEFF_SRAM_ADR_RD_MASK_SFT (0x3f << 0) |
| |
| /* AFE_GASRC_CK_SEL */ |
| #define GASRC4_HIRES_CK_SEL_SFT 3 |
| #define GASRC4_HIRES_CK_SEL_MASK 0x1 |
| #define GASRC4_HIRES_CK_SEL_MASK_SFT (0x1 << 3) |
| #define GASRC3_HIRES_CK_SEL_SFT 2 |
| #define GASRC3_HIRES_CK_SEL_MASK 0x1 |
| #define GASRC3_HIRES_CK_SEL_MASK_SFT (0x1 << 2) |
| #define GASRC2_HIRES_CK_SEL_SFT 1 |
| #define GASRC2_HIRES_CK_SEL_MASK 0x1 |
| #define GASRC2_HIRES_CK_SEL_MASK_SFT (0x1 << 1) |
| #define GASRC1_HIRES_CK_SEL_SFT 0 |
| #define GASRC1_HIRES_CK_SEL_MASK 0x1 |
| #define GASRC1_HIRES_CK_SEL_MASK_SFT (0x1 << 0) |
| |
| /* AUDIO_DIG_3RD_DSN_ID */ |
| #define AUDIO_DIG_3RD_ANA_ID_SFT 0 |
| #define AUDIO_DIG_3RD_ANA_ID_MASK 0xff |
| #define AUDIO_DIG_3RD_ANA_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_3RD_DSN_ID_H */ |
| #define AUDIO_DIG_3RD_DIG_ID_SFT 0 |
| #define AUDIO_DIG_3RD_DIG_ID_MASK 0xff |
| #define AUDIO_DIG_3RD_DIG_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_3RD_DSN_REV0 */ |
| #define AUDIO_DIG_3RD_ANA_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_3RD_ANA_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_3RD_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_3RD_ANA_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_3RD_ANA_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_3RD_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_3RD_DSN_REV0_H */ |
| #define AUDIO_DIG_3RD_DIG_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_3RD_DIG_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_3RD_DIG_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_3RD_DIG_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_3RD_DIG_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_3RD_DIG_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_3RD_DSN_DBI */ |
| #define AUDIO_DIG_3RD_DSN_CBS_SFT 0 |
| #define AUDIO_DIG_3RD_DSN_CBS_MASK 0x3 |
| #define AUDIO_DIG_3RD_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDIO_DIG_3RD_DSN_BIX_SFT 2 |
| #define AUDIO_DIG_3RD_DSN_BIX_MASK 0x3 |
| #define AUDIO_DIG_3RD_DSN_BIX_MASK_SFT (0x3 << 2) |
| |
| /* AUDIO_DIG_3RD_DSN_DBI_H */ |
| #define AUDIO_DIG_3_ESP_SFT 0 |
| #define AUDIO_DIG_3_ESP_MASK 0xff |
| #define AUDIO_DIG_3_ESP_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_3RD_DSN_DXI */ |
| #define AUDIO_DIG_3RD_DSN_FPI_SFT 0 |
| #define AUDIO_DIG_3RD_DSN_FPI_MASK 0xff |
| #define AUDIO_DIG_3RD_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON0 */ |
| #define GASRC3_CHSET_STR_CLR_SFT 4 |
| #define GASRC3_CHSET_STR_CLR_MASK 0x1 |
| #define GASRC3_CHSET_STR_CLR_MASK_SFT (0x1 << 4) |
| #define GASRC3_COEFF_SRAM_CTRL_SFT 1 |
| #define GASRC3_COEFF_SRAM_CTRL_MASK 0x1 |
| #define GASRC3_COEFF_SRAM_CTRL_MASK_SFT (0x1 << 1) |
| #define GASRC3_ASM_ON_SFT 0 |
| #define GASRC3_ASM_ON_MASK 0x1 |
| #define GASRC3_ASM_ON_MASK_SFT (0x1 << 0) |
| |
| /* AFE_GASRC3_CON1 */ |
| #define GASRC3_RESULT_SEL_SFT 0 |
| #define GASRC3_RESULT_SEL_MASK 0x7 |
| #define GASRC3_RESULT_SEL_MASK_SFT (0x7 << 0) |
| |
| /* AFE_GASRC3_CON2 */ |
| #define GASRC3_CHSET_STR_CLR_RD_SFT 5 |
| #define GASRC3_CHSET_STR_CLR_RD_MASK 0x1 |
| #define GASRC3_CHSET_STR_CLR_RD_MASK_SFT (0x1 << 5) |
| #define GASRC3_CHSET_ON_RD_SFT 2 |
| #define GASRC3_CHSET_ON_RD_MASK 0x1 |
| #define GASRC3_CHSET_ON_RD_MASK_SFT (0x1 << 2) |
| #define GASRC3_COEFF_SRAM_CTRL_RD_SFT 1 |
| #define GASRC3_COEFF_SRAM_CTRL_RD_MASK 0x1 |
| #define GASRC3_COEFF_SRAM_CTRL_RD_MASK_SFT (0x1 << 1) |
| #define GASRC3_ASM_ON_RD_SFT 0 |
| #define GASRC3_ASM_ON_RD_MASK 0x1 |
| #define GASRC3_ASM_ON_RD_MASK_SFT (0x1 << 0) |
| |
| /* AFE_GASRC3_CON2_M */ |
| #define GASRC3_CHSET_IIR_EN_SFT 3 |
| #define GASRC3_CHSET_IIR_EN_MASK 0x1 |
| #define GASRC3_CHSET_IIR_EN_MASK_SFT (0x1 << 3) |
| #define GASRC3_CHSET_IIR_STAGE_SFT 0 |
| #define GASRC3_CHSET_IIR_STAGE_MASK 0x7 |
| #define GASRC3_CHSET_IIR_STAGE_MASK_SFT (0x7 << 0) |
| |
| /* AFE_GASRC3_CON2_H */ |
| #define GASRC3_CHSET_O16BIT_SFT 3 |
| #define GASRC3_CHSET_O16BIT_MASK 0x1 |
| #define GASRC3_CHSET_O16BIT_MASK_SFT (0x1 << 3) |
| #define GASRC3_CHSET_CLR_IIR_HISTORY_SFT 1 |
| #define GASRC3_CHSET_CLR_IIR_HISTORY_MASK 0x1 |
| #define GASRC3_CHSET_CLR_IIR_HISTORY_MASK_SFT (0x1 << 1) |
| #define GASRC3_CHSET_IS_MONO_SFT 0 |
| #define GASRC3_CHSET_IS_MONO_MASK 0x1 |
| #define GASRC3_CHSET_IS_MONO_MASK_SFT (0x1 << 0) |
| |
| /* AFE_GASRC3_CON3 */ |
| #define GASRC3_ASM_FREQ_4_SFT 0 |
| #define GASRC3_ASM_FREQ_4_MASK 0xff |
| #define GASRC3_ASM_FREQ_4_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON3_M */ |
| #define GASRC3_ASM_FREQ_4_M_SFT 0 |
| #define GASRC3_ASM_FREQ_4_M_MASK 0xff |
| #define GASRC3_ASM_FREQ_4_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON3_H */ |
| #define GASRC3_ASM_FREQ_4_H_SFT 0 |
| #define GASRC3_ASM_FREQ_4_H_MASK 0xff |
| #define GASRC3_ASM_FREQ_4_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON4 */ |
| #define GASRC3_ASM_FREQ_5_SFT 0 |
| #define GASRC3_ASM_FREQ_5_MASK 0xff |
| #define GASRC3_ASM_FREQ_5_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON4_M */ |
| #define GASRC3_ASM_FREQ_5_M_SFT 0 |
| #define GASRC3_ASM_FREQ_5_M_MASK 0xff |
| #define GASRC3_ASM_FREQ_5_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON4_H */ |
| #define GASRC3_ASM_FREQ_5_H_SFT 0 |
| #define GASRC3_ASM_FREQ_5_H_MASK 0xff |
| #define GASRC3_ASM_FREQ_5_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON5 */ |
| #define GASRC3_FREQ_CALI_BP_DGL_SFT 7 |
| #define GASRC3_FREQ_CALI_BP_DGL_MASK 0x1 |
| #define GASRC3_FREQ_CALI_BP_DGL_MASK_SFT (0x1 << 7) |
| #define GASRC3_FREQ_CALI_MAX_GWIDTH_SFT 4 |
| #define GASRC3_FREQ_CALI_MAX_GWIDTH_MASK 0x7 |
| #define GASRC3_FREQ_CALI_MAX_GWIDTH_MASK_SFT (0x7 << 4) |
| #define GASRC3_AUTO_TUNE_FREQ4_SFT 3 |
| #define GASRC3_AUTO_TUNE_FREQ4_MASK 0x1 |
| #define GASRC3_AUTO_TUNE_FREQ4_MASK_SFT (0x1 << 3) |
| #define GASRC3_FREQ_CALI_AUTO_RESTART_SFT 2 |
| #define GASRC3_FREQ_CALI_AUTO_RESTART_MASK 0x1 |
| #define GASRC3_FREQ_CALI_AUTO_RESTART_MASK_SFT (0x1 << 2) |
| #define GASRC3_CALI_USE_FREQ_OUT_SFT 1 |
| #define GASRC3_CALI_USE_FREQ_OUT_MASK 0x1 |
| #define GASRC3_CALI_USE_FREQ_OUT_MASK_SFT (0x1 << 1) |
| #define GASRC3_CALI_EN_SFT 0 |
| #define GASRC3_CALI_EN_MASK 0x1 |
| #define GASRC3_CALI_EN_MASK_SFT (0x1 << 0) |
| |
| /* AFE_GASRC3_CON5_M */ |
| #define GASRC3_FREQ_CALI_AUTORST_EN_SFT 6 |
| #define GASRC3_FREQ_CALI_AUTORST_EN_MASK 0x1 |
| #define GASRC3_FREQ_CALI_AUTORST_EN_MASK_SFT (0x1 << 6) |
| #define GASRC3_FREQ_CALC_RUNNING_SFT 5 |
| #define GASRC3_FREQ_CALC_RUNNING_MASK 0x1 |
| #define GASRC3_FREQ_CALC_RUNNING_MASK_SFT (0x1 << 5) |
| #define GASRC3_AUTO_TUNE_FREQ5_SFT 4 |
| #define GASRC3_AUTO_TUNE_FREQ5_MASK 0x1 |
| #define GASRC3_AUTO_TUNE_FREQ5_MASK_SFT (0x1 << 4) |
| #define GASRC3_COMP_FREQ_RES_EN_SFT 3 |
| #define GASRC3_COMP_FREQ_RES_EN_MASK 0x1 |
| #define GASRC3_COMP_FREQ_RES_EN_MASK_SFT (0x1 << 3) |
| #define GASRC3_FREQ_CALI_SEL_SFT 0 |
| #define GASRC3_FREQ_CALI_SEL_MASK 0x3 |
| #define GASRC3_FREQ_CALI_SEL_MASK_SFT (0x3 << 0) |
| |
| /* AFE_GASRC3_CON5_H0 */ |
| #define GASRC3_FREQ_CALI_CYCLE_H0_SFT 0 |
| #define GASRC3_FREQ_CALI_CYCLE_H0_MASK 0xff |
| #define GASRC3_FREQ_CALI_CYCLE_H0_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON5_H1 */ |
| #define GASRC3_FREQ_CALI_CYCLE_H1_SFT 0 |
| #define GASRC3_FREQ_CALI_CYCLE_H1_MASK 0xff |
| #define GASRC3_FREQ_CALI_CYCLE_H1_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON6 */ |
| #define GASRC3_FREQ_CALC_DENOMINATOR_SFT 0 |
| #define GASRC3_FREQ_CALC_DENOMINATOR_MASK 0xff |
| #define GASRC3_FREQ_CALC_DENOMINATOR_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON6_M */ |
| #define GASRC3_FREQ_CALC_DENOMINATOR_M_SFT 0 |
| #define GASRC3_FREQ_CALC_DENOMINATOR_M_MASK 0xff |
| #define GASRC3_FREQ_CALC_DENOMINATOR_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON6_H */ |
| #define GASRC3_FREQ_CALC_DENOMINATOR_H_SFT 0 |
| #define GASRC3_FREQ_CALC_DENOMINATOR_H_MASK 0xff |
| #define GASRC3_FREQ_CALC_DENOMINATOR_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON7 */ |
| #define GASRC3_PRD_CALI_RESULT_RECORD_SFT 0 |
| #define GASRC3_PRD_CALI_RESULT_RECORD_MASK 0xff |
| #define GASRC3_PRD_CALI_RESULT_RECORD_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON7_M */ |
| #define GASRC3_PRD_CALI_RESULT_RECORD_M_SFT 0 |
| #define GASRC3_PRD_CALI_RESULT_RECORD_M_MASK 0xff |
| #define GASRC3_PRD_CALI_RESULT_RECORD_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON7_H */ |
| #define GASRC3_PRD_CALI_RESULT_RECORD_H_SFT 0 |
| #define GASRC3_PRD_CALI_RESULT_RECORD_H_MASK 0xff |
| #define GASRC3_PRD_CALI_RESULT_RECORD_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON8 */ |
| #define GASRC3_FREQ_CALI_RESULT_SFT 0 |
| #define GASRC3_FREQ_CALI_RESULT_MASK 0xff |
| #define GASRC3_FREQ_CALI_RESULT_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON8_M */ |
| #define GASRC3_FREQ_CALI_RESULT_M_SFT 0 |
| #define GASRC3_FREQ_CALI_RESULT_M_MASK 0xff |
| #define GASRC3_FREQ_CALI_RESULT_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON8_H */ |
| #define GASRC3_FREQ_CALI_RESULT_H_SFT 0 |
| #define GASRC3_FREQ_CALI_RESULT_H_MASK 0xff |
| #define GASRC3_FREQ_CALI_RESULT_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON9 */ |
| #define GASRC3_FREQ_CALI_AUTORST_TH_HIGH_SFT 0 |
| #define GASRC3_FREQ_CALI_AUTORST_TH_HIGH_MASK 0xff |
| #define GASRC3_FREQ_CALI_AUTORST_TH_HIGH_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON9_M */ |
| #define GASRC3_FREQ_CALI_AUTORST_TH_HIGH_M_SFT 0 |
| #define GASRC3_FREQ_CALI_AUTORST_TH_HIGH_M_MASK 0xff |
| #define GASRC3_FREQ_CALI_AUTORST_TH_HIGH_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON9_H */ |
| #define GASRC3_FREQ_CALI_AUTORST_TH_HIGH_H_SFT 0 |
| #define GASRC3_FREQ_CALI_AUTORST_TH_HIGH_H_MASK 0xff |
| #define GASRC3_FREQ_CALI_AUTORST_TH_HIGH_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON10 */ |
| #define GASRC3_FREQ_CALI_AUTORST_TH_LOW_SFT 0 |
| #define GASRC3_FREQ_CALI_AUTORST_TH_LOW_MASK 0xff |
| #define GASRC3_FREQ_CALI_AUTORST_TH_LOW_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON10_M */ |
| #define GASRC3_FREQ_CALI_AUTORST_TH_LOW_M_SFT 0 |
| #define GASRC3_FREQ_CALI_AUTORST_TH_LOW_M_MASK 0xff |
| #define GASRC3_FREQ_CALI_AUTORST_TH_LOW_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON10_H */ |
| #define GASRC3_FREQ_CALI_AUTORST_TH_LOW_H_SFT 0 |
| #define GASRC3_FREQ_CALI_AUTORST_TH_LOW_H_MASK 0xff |
| #define GASRC3_FREQ_CALI_AUTORST_TH_LOW_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON11 */ |
| #define GASRC3_RING_DBG_RD_SFT 0 |
| #define GASRC3_RING_DBG_RD_MASK 0xff |
| #define GASRC3_RING_DBG_RD_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON11_H */ |
| #define GASRC3_RING_DBG_RD_H_SFT 0 |
| #define GASRC3_RING_DBG_RD_H_MASK 0xff |
| #define GASRC3_RING_DBG_RD_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON12 */ |
| #define GASRC3_COEFF_SRAM_DATA_SFT 0 |
| #define GASRC3_COEFF_SRAM_DATA_MASK 0xff |
| #define GASRC3_COEFF_SRAM_DATA_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON12_M */ |
| #define GASRC3_COEFF_SRAM_DATA_M_SFT 0 |
| #define GASRC3_COEFF_SRAM_DATA_M_MASK 0xff |
| #define GASRC3_COEFF_SRAM_DATA_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON12_H */ |
| #define GASRC3_COEFF_SRAM_DATA_H_SFT 0 |
| #define GASRC3_COEFF_SRAM_DATA_H_MASK 0xff |
| #define GASRC3_COEFF_SRAM_DATA_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON13 */ |
| #define GASRC3_COEFF_SRAM_ADR_SFT 0 |
| #define GASRC3_COEFF_SRAM_ADR_MASK 0x3f |
| #define GASRC3_COEFF_SRAM_ADR_MASK_SFT (0x3f << 0) |
| |
| /* AFE_GASRC3_CON14 */ |
| #define GASRC3_COEFF_SRAM_DATA_RD_SFT 0 |
| #define GASRC3_COEFF_SRAM_DATA_RD_MASK 0xff |
| #define GASRC3_COEFF_SRAM_DATA_RD_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON14_M */ |
| #define GASRC3_COEFF_SRAM_DATA_M_RD_SFT 0 |
| #define GASRC3_COEFF_SRAM_DATA_M_RD_MASK 0xff |
| #define GASRC3_COEFF_SRAM_DATA_M_RD_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON14_H */ |
| #define GASRC3_COEFF_SRAM_DATA_H_RD_SFT 0 |
| #define GASRC3_COEFF_SRAM_DATA_H_RD_MASK 0xff |
| #define GASRC3_COEFF_SRAM_DATA_H_RD_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC3_CON15 */ |
| #define GASRC3_COEFF_SRAM_ADR_RD_SFT 0 |
| #define GASRC3_COEFF_SRAM_ADR_RD_MASK 0x3f |
| #define GASRC3_COEFF_SRAM_ADR_RD_MASK_SFT (0x3f << 0) |
| |
| /* AFE_GASRC4_CON0 */ |
| #define GASRC4_CHSET_STR_CLR_SFT 4 |
| #define GASRC4_CHSET_STR_CLR_MASK 0x1 |
| #define GASRC4_CHSET_STR_CLR_MASK_SFT (0x1 << 4) |
| #define GASRC4_COEFF_SRAM_CTRL_SFT 1 |
| #define GASRC4_COEFF_SRAM_CTRL_MASK 0x1 |
| #define GASRC4_COEFF_SRAM_CTRL_MASK_SFT (0x1 << 1) |
| #define GASRC4_ASM_ON_SFT 0 |
| #define GASRC4_ASM_ON_MASK 0x1 |
| #define GASRC4_ASM_ON_MASK_SFT (0x1 << 0) |
| |
| /* AFE_GASRC4_CON1 */ |
| #define GASRC4_RESULT_SEL_SFT 0 |
| #define GASRC4_RESULT_SEL_MASK 0x7 |
| #define GASRC4_RESULT_SEL_MASK_SFT (0x7 << 0) |
| |
| /* AFE_GASRC4_CON2 */ |
| #define GASRC4_CHSET_STR_CLR_RD_SFT 5 |
| #define GASRC4_CHSET_STR_CLR_RD_MASK 0x1 |
| #define GASRC4_CHSET_STR_CLR_RD_MASK_SFT (0x1 << 5) |
| #define GASRC4_CHSET_ON_RD_SFT 2 |
| #define GASRC4_CHSET_ON_RD_MASK 0x1 |
| #define GASRC4_CHSET_ON_RD_MASK_SFT (0x1 << 2) |
| #define GASRC4_COEFF_SRAM_CTRL_RD_SFT 1 |
| #define GASRC4_COEFF_SRAM_CTRL_RD_MASK 0x1 |
| #define GASRC4_COEFF_SRAM_CTRL_RD_MASK_SFT (0x1 << 1) |
| #define GASRC4_ASM_ON_RD_SFT 0 |
| #define GASRC4_ASM_ON_RD_MASK 0x1 |
| #define GASRC4_ASM_ON_RD_MASK_SFT (0x1 << 0) |
| |
| /* AFE_GASRC4_CON2_M */ |
| #define GASRC4_CHSET_IIR_EN_SFT 3 |
| #define GASRC4_CHSET_IIR_EN_MASK 0x1 |
| #define GASRC4_CHSET_IIR_EN_MASK_SFT (0x1 << 3) |
| #define GASRC4_CHSET_IIR_STAGE_SFT 0 |
| #define GASRC4_CHSET_IIR_STAGE_MASK 0x7 |
| #define GASRC4_CHSET_IIR_STAGE_MASK_SFT (0x7 << 0) |
| |
| /* AFE_GASRC4_CON2_H */ |
| #define GASRC4_CHSET_O16BIT_SFT 3 |
| #define GASRC4_CHSET_O16BIT_MASK 0x1 |
| #define GASRC4_CHSET_O16BIT_MASK_SFT (0x1 << 3) |
| #define GASRC4_CHSET_CLR_IIR_HISTORY_SFT 1 |
| #define GASRC4_CHSET_CLR_IIR_HISTORY_MASK 0x1 |
| #define GASRC4_CHSET_CLR_IIR_HISTORY_MASK_SFT (0x1 << 1) |
| #define GASRC4_CHSET_IS_MONO_SFT 0 |
| #define GASRC4_CHSET_IS_MONO_MASK 0x1 |
| #define GASRC4_CHSET_IS_MONO_MASK_SFT (0x1 << 0) |
| |
| /* AFE_GASRC4_CON3 */ |
| #define GASRC4_ASM_FREQ_4_SFT 0 |
| #define GASRC4_ASM_FREQ_4_MASK 0xff |
| #define GASRC4_ASM_FREQ_4_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON3_M */ |
| #define GASRC4_ASM_FREQ_4_M_SFT 0 |
| #define GASRC4_ASM_FREQ_4_M_MASK 0xff |
| #define GASRC4_ASM_FREQ_4_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON3_H */ |
| #define GASRC4_ASM_FREQ_4_H_SFT 0 |
| #define GASRC4_ASM_FREQ_4_H_MASK 0xff |
| #define GASRC4_ASM_FREQ_4_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON4 */ |
| #define GASRC4_ASM_FREQ_5_SFT 0 |
| #define GASRC4_ASM_FREQ_5_MASK 0xff |
| #define GASRC4_ASM_FREQ_5_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON4_M */ |
| #define GASRC4_ASM_FREQ_5_M_SFT 0 |
| #define GASRC4_ASM_FREQ_5_M_MASK 0xff |
| #define GASRC4_ASM_FREQ_5_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON4_H */ |
| #define GASRC4_ASM_FREQ_5_H_SFT 0 |
| #define GASRC4_ASM_FREQ_5_H_MASK 0xff |
| #define GASRC4_ASM_FREQ_5_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON5 */ |
| #define GASRC4_FREQ_CALI_BP_DGL_SFT 7 |
| #define GASRC4_FREQ_CALI_BP_DGL_MASK 0x1 |
| #define GASRC4_FREQ_CALI_BP_DGL_MASK_SFT (0x1 << 7) |
| #define GASRC4_FREQ_CALI_MAX_GWIDTH_SFT 4 |
| #define GASRC4_FREQ_CALI_MAX_GWIDTH_MASK 0x7 |
| #define GASRC4_FREQ_CALI_MAX_GWIDTH_MASK_SFT (0x7 << 4) |
| #define GASRC4_AUTO_TUNE_FREQ4_SFT 3 |
| #define GASRC4_AUTO_TUNE_FREQ4_MASK 0x1 |
| #define GASRC4_AUTO_TUNE_FREQ4_MASK_SFT (0x1 << 3) |
| #define GASRC4_FREQ_CALI_AUTO_RESTART_SFT 2 |
| #define GASRC4_FREQ_CALI_AUTO_RESTART_MASK 0x1 |
| #define GASRC4_FREQ_CALI_AUTO_RESTART_MASK_SFT (0x1 << 2) |
| #define GASRC4_CALI_USE_FREQ_OUT_SFT 1 |
| #define GASRC4_CALI_USE_FREQ_OUT_MASK 0x1 |
| #define GASRC4_CALI_USE_FREQ_OUT_MASK_SFT (0x1 << 1) |
| #define GASRC4_CALI_EN_SFT 0 |
| #define GASRC4_CALI_EN_MASK 0x1 |
| #define GASRC4_CALI_EN_MASK_SFT (0x1 << 0) |
| |
| /* AFE_GASRC4_CON5_M */ |
| #define GASRC4_FREQ_CALI_AUTORST_EN_SFT 6 |
| #define GASRC4_FREQ_CALI_AUTORST_EN_MASK 0x1 |
| #define GASRC4_FREQ_CALI_AUTORST_EN_MASK_SFT (0x1 << 6) |
| #define GASRC4_FREQ_CALC_RUNNING_SFT 5 |
| #define GASRC4_FREQ_CALC_RUNNING_MASK 0x1 |
| #define GASRC4_FREQ_CALC_RUNNING_MASK_SFT (0x1 << 5) |
| #define GASRC4_AUTO_TUNE_FREQ5_SFT 4 |
| #define GASRC4_AUTO_TUNE_FREQ5_MASK 0x1 |
| #define GASRC4_AUTO_TUNE_FREQ5_MASK_SFT (0x1 << 4) |
| #define GASRC4_COMP_FREQ_RES_EN_SFT 3 |
| #define GASRC4_COMP_FREQ_RES_EN_MASK 0x1 |
| #define GASRC4_COMP_FREQ_RES_EN_MASK_SFT (0x1 << 3) |
| #define GASRC4_FREQ_CALI_SEL_SFT 0 |
| #define GASRC4_FREQ_CALI_SEL_MASK 0x3 |
| #define GASRC4_FREQ_CALI_SEL_MASK_SFT (0x3 << 0) |
| |
| /* AFE_GASRC4_CON5_H0 */ |
| #define GASRC4_FREQ_CALI_CYCLE_H0_SFT 0 |
| #define GASRC4_FREQ_CALI_CYCLE_H0_MASK 0xff |
| #define GASRC4_FREQ_CALI_CYCLE_H0_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON5_H1 */ |
| #define GASRC4_FREQ_CALI_CYCLE_H1_SFT 0 |
| #define GASRC4_FREQ_CALI_CYCLE_H1_MASK 0xff |
| #define GASRC4_FREQ_CALI_CYCLE_H1_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON6 */ |
| #define GASRC4_FREQ_CALC_DENOMINATOR_SFT 0 |
| #define GASRC4_FREQ_CALC_DENOMINATOR_MASK 0xff |
| #define GASRC4_FREQ_CALC_DENOMINATOR_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON6_M */ |
| #define GASRC4_FREQ_CALC_DENOMINATOR_M_SFT 0 |
| #define GASRC4_FREQ_CALC_DENOMINATOR_M_MASK 0xff |
| #define GASRC4_FREQ_CALC_DENOMINATOR_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON6_H */ |
| #define GASRC4_FREQ_CALC_DENOMINATOR_H_SFT 0 |
| #define GASRC4_FREQ_CALC_DENOMINATOR_H_MASK 0xff |
| #define GASRC4_FREQ_CALC_DENOMINATOR_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON7 */ |
| #define GASRC4_PRD_CALI_RESULT_RECORD_SFT 0 |
| #define GASRC4_PRD_CALI_RESULT_RECORD_MASK 0xff |
| #define GASRC4_PRD_CALI_RESULT_RECORD_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON7_M */ |
| #define GASRC4_PRD_CALI_RESULT_RECORD_M_SFT 0 |
| #define GASRC4_PRD_CALI_RESULT_RECORD_M_MASK 0xff |
| #define GASRC4_PRD_CALI_RESULT_RECORD_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON7_H */ |
| #define GASRC4_PRD_CALI_RESULT_RECORD_H_SFT 0 |
| #define GASRC4_PRD_CALI_RESULT_RECORD_H_MASK 0xff |
| #define GASRC4_PRD_CALI_RESULT_RECORD_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON8 */ |
| #define GASRC4_FREQ_CALI_RESULT_SFT 0 |
| #define GASRC4_FREQ_CALI_RESULT_MASK 0xff |
| #define GASRC4_FREQ_CALI_RESULT_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON8_M */ |
| #define GASRC4_FREQ_CALI_RESULT_M_SFT 0 |
| #define GASRC4_FREQ_CALI_RESULT_M_MASK 0xff |
| #define GASRC4_FREQ_CALI_RESULT_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON8_H */ |
| #define GASRC4_FREQ_CALI_RESULT_H_SFT 0 |
| #define GASRC4_FREQ_CALI_RESULT_H_MASK 0xff |
| #define GASRC4_FREQ_CALI_RESULT_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON9 */ |
| #define GASRC4_FREQ_CALI_AUTORST_TH_HIGH_SFT 0 |
| #define GASRC4_FREQ_CALI_AUTORST_TH_HIGH_MASK 0xff |
| #define GASRC4_FREQ_CALI_AUTORST_TH_HIGH_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON9_M */ |
| #define GASRC4_FREQ_CALI_AUTORST_TH_HIGH_M_SFT 0 |
| #define GASRC4_FREQ_CALI_AUTORST_TH_HIGH_M_MASK 0xff |
| #define GASRC4_FREQ_CALI_AUTORST_TH_HIGH_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON9_H */ |
| #define GASRC4_FREQ_CALI_AUTORST_TH_HIGH_H_SFT 0 |
| #define GASRC4_FREQ_CALI_AUTORST_TH_HIGH_H_MASK 0xff |
| #define GASRC4_FREQ_CALI_AUTORST_TH_HIGH_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON10 */ |
| #define GASRC4_FREQ_CALI_AUTORST_TH_LOW_SFT 0 |
| #define GASRC4_FREQ_CALI_AUTORST_TH_LOW_MASK 0xff |
| #define GASRC4_FREQ_CALI_AUTORST_TH_LOW_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON10_M */ |
| #define GASRC4_FREQ_CALI_AUTORST_TH_LOW_M_SFT 0 |
| #define GASRC4_FREQ_CALI_AUTORST_TH_LOW_M_MASK 0xff |
| #define GASRC4_FREQ_CALI_AUTORST_TH_LOW_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON10_H */ |
| #define GASRC4_FREQ_CALI_AUTORST_TH_LOW_H_SFT 0 |
| #define GASRC4_FREQ_CALI_AUTORST_TH_LOW_H_MASK 0xff |
| #define GASRC4_FREQ_CALI_AUTORST_TH_LOW_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON11 */ |
| #define GASRC4_RING_DBG_RD_SFT 0 |
| #define GASRC4_RING_DBG_RD_MASK 0xff |
| #define GASRC4_RING_DBG_RD_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON11_H */ |
| #define GASRC4_RING_DBG_RD_H_SFT 0 |
| #define GASRC4_RING_DBG_RD_H_MASK 0xff |
| #define GASRC4_RING_DBG_RD_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON12 */ |
| #define GASRC4_COEFF_SRAM_DATA_SFT 0 |
| #define GASRC4_COEFF_SRAM_DATA_MASK 0xff |
| #define GASRC4_COEFF_SRAM_DATA_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON12_M */ |
| #define GASRC4_COEFF_SRAM_DATA_M_SFT 0 |
| #define GASRC4_COEFF_SRAM_DATA_M_MASK 0xff |
| #define GASRC4_COEFF_SRAM_DATA_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON12_H */ |
| #define GASRC4_COEFF_SRAM_DATA_H_SFT 0 |
| #define GASRC4_COEFF_SRAM_DATA_H_MASK 0xff |
| #define GASRC4_COEFF_SRAM_DATA_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON13 */ |
| #define GASRC4_COEFF_SRAM_ADR_SFT 0 |
| #define GASRC4_COEFF_SRAM_ADR_MASK 0x3f |
| #define GASRC4_COEFF_SRAM_ADR_MASK_SFT (0x3f << 0) |
| |
| /* AFE_GASRC4_CON14 */ |
| #define GASRC4_COEFF_SRAM_DATA_RD_SFT 0 |
| #define GASRC4_COEFF_SRAM_DATA_RD_MASK 0xff |
| #define GASRC4_COEFF_SRAM_DATA_RD_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON14_M */ |
| #define GASRC4_COEFF_SRAM_DATA_M_RD_SFT 0 |
| #define GASRC4_COEFF_SRAM_DATA_M_RD_MASK 0xff |
| #define GASRC4_COEFF_SRAM_DATA_M_RD_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON14_H */ |
| #define GASRC4_COEFF_SRAM_DATA_H_RD_SFT 0 |
| #define GASRC4_COEFF_SRAM_DATA_H_RD_MASK 0xff |
| #define GASRC4_COEFF_SRAM_DATA_H_RD_MASK_SFT (0xff << 0) |
| |
| /* AFE_GASRC4_CON15 */ |
| #define GASRC4_COEFF_SRAM_ADR_RD_SFT 0 |
| #define GASRC4_COEFF_SRAM_ADR_RD_MASK 0x3f |
| #define GASRC4_COEFF_SRAM_ADR_RD_MASK_SFT (0x3f << 0) |
| |
| /* AUDIO_DIG_4TH_DSN_ID */ |
| #define AUDIO_DIG_4TH_ANA_ID_SFT 0 |
| #define AUDIO_DIG_4TH_ANA_ID_MASK 0xff |
| #define AUDIO_DIG_4TH_ANA_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_4TH_DSN_ID_H */ |
| #define AUDIO_DIG_4TH_DIG_ID_SFT 0 |
| #define AUDIO_DIG_4TH_DIG_ID_MASK 0xff |
| #define AUDIO_DIG_4TH_DIG_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_4TH_DSN_REV0 */ |
| #define AUDIO_DIG_4TH_ANA_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_4TH_ANA_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_4TH_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_4TH_ANA_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_4TH_ANA_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_4TH_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_4TH_DSN_REV0_H */ |
| #define AUDIO_DIG_4TH_DIG_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_4TH_DIG_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_4TH_DIG_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_4TH_DIG_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_4TH_DIG_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_4TH_DIG_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_4TH_DSN_DBI */ |
| #define AUDIO_DIG_4TH_DSN_CBS_SFT 0 |
| #define AUDIO_DIG_4TH_DSN_CBS_MASK 0x3 |
| #define AUDIO_DIG_4TH_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDIO_DIG_4TH_DSN_BIX_SFT 2 |
| #define AUDIO_DIG_4TH_DSN_BIX_MASK 0x3 |
| #define AUDIO_DIG_4TH_DSN_BIX_MASK_SFT (0x3 << 2) |
| |
| /* AUDIO_DIG_4TH_DSN_DBI_H */ |
| #define AUDIO_DIG_4_ESP_SFT 0 |
| #define AUDIO_DIG_4_ESP_MASK 0xff |
| #define AUDIO_DIG_4_ESP_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_4TH_DSN_DXI */ |
| #define AUDIO_DIG_4TH_DSN_FPI_SFT 0 |
| #define AUDIO_DIG_4TH_DSN_FPI_MASK 0xff |
| #define AUDIO_DIG_4TH_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_UL_DL_CON0_2 */ |
| #define MT6338_AFE_ADDA_UL_LR_SWAP_SFT 4 |
| #define MT6338_AFE_ADDA_UL_LR_SWAP_MASK 0x1 |
| #define MT6338_AFE_ADDA_UL_LR_SWAP_MASK_SFT (0x1 << 4) |
| #define MT6338_AFE_ADDA_FIFO_AUTO_RST_SFT 3 |
| #define MT6338_AFE_ADDA_FIFO_AUTO_RST_MASK 0x1 |
| #define MT6338_AFE_ADDA_FIFO_AUTO_RST_MASK_SFT (0x1 << 3) |
| #define MT6338_AFE_ADDA_UL_FIFO_DIGMIC_TESTIN_SFT 1 |
| #define MT6338_AFE_ADDA_UL_FIFO_DIGMIC_TESTIN_MASK 0x3 |
| #define MT6338_AFE_ADDA_UL_FIFO_DIGMIC_TESTIN_MASK_SFT (0x3 << 1) |
| #define MT6338_AFE_ADDA_UL_FIFO_DIGMIC_WDATA_TESTEN_SFT 0 |
| #define MT6338_AFE_ADDA_UL_FIFO_DIGMIC_WDATA_TESTEN_MASK 0x1 |
| #define MT6338_AFE_ADDA_UL_FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT (0x1 << 0) |
| |
| /* AFE_ADDA_UL_DL_CON0_1 */ |
| #define MT6338_AFE_ADDA6_UL_LR_SWAP_SFT 4 |
| #define MT6338_AFE_ADDA6_UL_LR_SWAP_MASK 0x1 |
| #define MT6338_AFE_ADDA6_UL_LR_SWAP_MASK_SFT (0x1 << 4) |
| #define MT6338_AFE_ADDA6_FIFO_AUTO_RST_SFT 3 |
| #define MT6338_AFE_ADDA6_FIFO_AUTO_RST_MASK 0x1 |
| #define MT6338_AFE_ADDA6_FIFO_AUTO_RST_MASK_SFT (0x1 << 3) |
| #define MT6338_AFE_ADDA6_UL_FIFO_DIGMIC_TESTIN_SFT 1 |
| #define MT6338_AFE_ADDA6_UL_FIFO_DIGMIC_TESTIN_MASK 0x3 |
| #define MT6338_AFE_ADDA6_UL_FIFO_DIGMIC_TESTIN_MASK_SFT (0x3 << 1) |
| #define MT6338_AFE_ADDA6_UL_FIFO_DIGMIC_WDATA_TESTEN_SFT 0 |
| #define MT6338_AFE_ADDA6_UL_FIFO_DIGMIC_WDATA_TESTEN_MASK 0x1 |
| #define MT6338_AFE_ADDA6_UL_FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT (0x1 << 0) |
| |
| /* AFE_ADDA_UL_DL_CON0_0 */ |
| #define MT6338_ADDA_USE_OLD_VERSION_SFT 4 |
| #define MT6338_ADDA_USE_OLD_VERSION_MASK 0x1 |
| #define MT6338_ADDA_USE_OLD_VERSION_MASK_SFT (0x1 << 4) |
| #define MT6338_ADDA6_USE_OLD_VERSION_SFT 3 |
| #define MT6338_ADDA6_USE_OLD_VERSION_MASK 0x1 |
| #define MT6338_ADDA6_USE_OLD_VERSION_MASK_SFT (0x1 << 3) |
| #define MT6338_AFE_DMIC_CKDIV_RST_SFT 2 |
| #define MT6338_AFE_DMIC_CKDIV_RST_MASK 0x1 |
| #define MT6338_AFE_DMIC_CKDIV_RST_MASK_SFT (0x1 << 2) |
| #define MT6338_AFE_DMIC_CKDIV_ON_SFT 1 |
| #define MT6338_AFE_DMIC_CKDIV_ON_MASK 0x1 |
| #define MT6338_AFE_DMIC_CKDIV_ON_MASK_SFT (0x1 << 1) |
| #define MT6338_ADDA_AFE_ON_SFT 0 |
| #define MT6338_ADDA_AFE_ON_MASK 0x1 |
| #define MT6338_ADDA_AFE_ON_MASK_SFT (0x1 << 0) |
| |
| |
| /* AFE_ADDA_UL_SRC_CON0_3 */ |
| #define ADDA_ULCF_CFG_EN_CTL_SFT 7 |
| #define ADDA_ULCF_CFG_EN_CTL_MASK 0x1 |
| #define ADDA_ULCF_CFG_EN_CTL_MASK_SFT (0x1 << 7) |
| #define ADDA_UL_DMIC_PHASE_SEL_CH1_SFT 3 |
| #define ADDA_UL_DMIC_PHASE_SEL_CH1_MASK 0x7 |
| #define ADDA_UL_DMIC_PHASE_SEL_CH1_MASK_SFT (0x7 << 3) |
| #define ADDA_UL_DMIC_PHASE_SEL_CH2_SFT 0 |
| #define ADDA_UL_DMIC_PHASE_SEL_CH2_MASK 0x7 |
| #define ADDA_UL_DMIC_PHASE_SEL_CH2_MASK_SFT (0x7 << 0) |
| |
| /* AFE_ADDA_UL_SRC_CON0_2 */ |
| #define MT6338_ADDA_UL_TWO_WIRE_MODE_CTL_SFT 7 |
| #define MT6338_ADDA_UL_TWO_WIRE_MODE_CTL_MASK 0x1 |
| #define MT6338_ADDA_UL_TWO_WIRE_MODE_CTL_MASK_SFT (0x1 << 7) |
| #define MT6338_ADDA_UL_GAIN_MODE_SFT 5 |
| #define MT6338_ADDA_UL_GAIN_MODE_MASK 0x3 |
| #define MT6338_ADDA_UL_GAIN_MODE_MASK_SFT (0x3 << 5) |
| #define MT6338_ADDA_UL_MODE_3P25M_CH2_CTL_SFT 4 |
| #define MT6338_ADDA_UL_MODE_3P25M_CH2_CTL_MASK 0x1 |
| #define MT6338_ADDA_UL_MODE_3P25M_CH2_CTL_MASK_SFT (0x1 << 4) |
| #define MT6338_ADDA_UL_MODE_3P25M_CH1_CTL_SFT 3 |
| #define MT6338_ADDA_UL_MODE_3P25M_CH1_CTL_MASK 0x1 |
| #define MT6338_ADDA_UL_MODE_3P25M_CH1_CTL_MASK_SFT (0x1 << 3) |
| #define MT6338_ADDA_UL_VOICE_MODE_CH1_CH2_CTL_SFT 0 |
| #define MT6338_ADDA_UL_VOICE_MODE_CH1_CH2_CTL_MASK 0x7 |
| #define MT6338_ADDA_UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT (0x7 << 0) |
| |
| /* AFE_ADDA_UL_SRC_CON0_1 */ |
| #define ADDA_DMIC_LOW_POWER_MODE_CTL_SFT 5 |
| #define ADDA_DMIC_LOW_POWER_MODE_CTL_MASK 0x3 |
| #define ADDA_DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 5) |
| #define ADDA_UL_DISABLE_HW_CG_CTL_SFT 4 |
| #define ADDA_UL_DISABLE_HW_CG_CTL_MASK 0x1 |
| #define ADDA_UL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 4) |
| #define ADDA_UL_IIR_ON_TMP_CTL_SFT 3 |
| #define ADDA_UL_IIR_ON_TMP_CTL_MASK 0x1 |
| #define ADDA_UL_IIR_ON_TMP_CTL_MASK_SFT (0x1 << 3) |
| #define ADDA_UL_IIRMODE_CTL_SFT 0 |
| #define ADDA_UL_IIRMODE_CTL_MASK 0x7 |
| #define ADDA_UL_IIRMODE_CTL_MASK_SFT (0x7 << 0) |
| |
| /* AFE_ADDA_UL_SRC_CON0_0 */ |
| #define ADDA_DIGMIC_4P33M_SEL_SFT 6 |
| #define ADDA_DIGMIC_4P33M_SEL_MASK 0x1 |
| #define ADDA_DIGMIC_4P33M_SEL_MASK_SFT (0x1 << 6) |
| #define ADDA_DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5 |
| #define ADDA_DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1 |
| #define ADDA_DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5) |
| #define ADDA_UL_LOOP_BACK_MODE_CTL_SFT 2 |
| #define ADDA_UL_LOOP_BACK_MODE_CTL_MASK 0x1 |
| #define ADDA_UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2) |
| #define ADDA_UL_SDM_3_LEVEL_CTL_SFT 1 |
| #define ADDA_UL_SDM_3_LEVEL_CTL_MASK 0x1 |
| #define ADDA_UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1) |
| #define ADDA_UL_SRC_ON_TMP_CTL_SFT 0 |
| #define ADDA_UL_SRC_ON_TMP_CTL_MASK 0x1 |
| #define ADDA_UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0) |
| |
| /* AFE_ADDA_UL_SRC_CON1_3 */ |
| #define ADDA_C_DAC_EN_CTL_SFT 7 |
| #define ADDA_C_DAC_EN_CTL_MASK 0x1 |
| #define ADDA_C_DAC_EN_CTL_MASK_SFT (0x1 << 7) |
| #define ADDA_C_MUTE_SW_CTL_SFT 6 |
| #define ADDA_C_MUTE_SW_CTL_MASK 0x1 |
| #define ADDA_C_MUTE_SW_CTL_MASK_SFT (0x1 << 6) |
| #define ADDA_ASDM_SRC_SEL_CTL_SFT 5 |
| #define ADDA_ASDM_SRC_SEL_CTL_MASK 0x1 |
| #define ADDA_ASDM_SRC_SEL_CTL_MASK_SFT (0x1 << 5) |
| #define ADDA_C_FREQ_DIV_CH2_CTL_SFT 0 |
| #define ADDA_C_FREQ_DIV_CH2_CTL_MASK 0x1f |
| #define ADDA_C_FREQ_DIV_CH2_CTL_MASK_SFT (0x1f << 0) |
| |
| /* AFE_ADDA_UL_SRC_CON1_2 */ |
| #define ADDA_C_AMP_DIV_CH2_CTL_SFT 4 |
| #define ADDA_C_AMP_DIV_CH2_CTL_MASK 0x7 |
| #define ADDA_C_AMP_DIV_CH2_CTL_MASK_SFT (0x7 << 4) |
| #define ADDA_C_SINE_MODE_CH2_CTL_SFT 0 |
| #define ADDA_C_SINE_MODE_CH2_CTL_MASK 0xf |
| #define ADDA_C_SINE_MODE_CH2_CTL_MASK_SFT (0xf << 0) |
| |
| /* AFE_ADDA_UL_SRC_CON1_1 */ |
| #define ADDA_C_FREQ_DIV_CH1_CTL_SFT 0 |
| #define ADDA_C_FREQ_DIV_CH1_CTL_MASK 0x1f |
| #define ADDA_C_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 0) |
| |
| /* AFE_ADDA_UL_SRC_CON1_0 */ |
| #define ADDA_C_AMP_DIV_CH1_CTL_SFT 4 |
| #define ADDA_C_AMP_DIV_CH1_CTL_MASK 0x7 |
| #define ADDA_C_AMP_DIV_CH1_CTL_MASK_SFT (0x7 << 4) |
| #define ADDA_C_SINE_MODE_CH1_CTL_SFT 0 |
| #define ADDA_C_SINE_MODE_CH1_CTL_MASK 0xf |
| #define ADDA_C_SINE_MODE_CH1_CTL_MASK_SFT (0xf << 0) |
| |
| /* AFE_ADDA_UL_SRC_CON2_3 */ |
| #define ADDA_UL_ODDTAP_MODE_SFT 6 |
| #define ADDA_UL_ODDTAP_MODE_MASK 0x1 |
| #define ADDA_UL_ODDTAP_MODE_MASK_SFT (0x1 << 6) |
| #define ADDA_UL_HALF_TAP_NUM_SFT 0 |
| #define ADDA_UL_HALF_TAP_NUM_MASK 0x3f |
| #define ADDA_UL_HALF_TAP_NUM_MASK_SFT (0x3f << 0) |
| |
| /* AFE_ADDA_UL_SRC_CON2_2 */ |
| #define ADDA_UL_NEW_GAIN_MODE_SFT 3 |
| #define ADDA_UL_NEW_GAIN_MODE_MASK 0x3 |
| #define ADDA_UL_NEW_GAIN_MODE_MASK_SFT (0x3 << 3) |
| #define ADDA_UL_POSTIVEGAIN_SFT 0 |
| #define ADDA_UL_POSTIVEGAIN_MASK 0x7 |
| #define ADDA_UL_POSTIVEGAIN_MASK_SFT (0x7 << 0) |
| |
| /* AFE_ADDA_UL_SRC_CON2_1 */ |
| #define ADDA_UL_GAIN_VALUE_1_SFT 0 |
| #define ADDA_UL_GAIN_VALUE_1_MASK 0xff |
| #define ADDA_UL_GAIN_VALUE_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_UL_SRC_CON2_0 */ |
| #define ADDA_UL_GAIN_VALUE_0_SFT 0 |
| #define ADDA_UL_GAIN_VALUE_0_MASK 0xff |
| #define ADDA_UL_GAIN_VALUE_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_IIR_COEF_02_01_3 */ |
| #define ADDA_IIR_COEF_02_01_3_SFT 0 |
| #define ADDA_IIR_COEF_02_01_3_MASK 0xff |
| #define ADDA_IIR_COEF_02_01_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_IIR_COEF_02_01_2 */ |
| #define ADDA_IIR_COEF_02_01_2_SFT 0 |
| #define ADDA_IIR_COEF_02_01_2_MASK 0xff |
| #define ADDA_IIR_COEF_02_01_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_IIR_COEF_02_01_1 */ |
| #define ADDA_IIR_COEF_02_01_1_SFT 0 |
| #define ADDA_IIR_COEF_02_01_1_MASK 0xff |
| #define ADDA_IIR_COEF_02_01_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_IIR_COEF_02_01_0 */ |
| #define ADDA_IIR_COEF_02_01_0_SFT 0 |
| #define ADDA_IIR_COEF_02_01_0_MASK 0xff |
| #define ADDA_IIR_COEF_02_01_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_IIR_COEF_04_03_3 */ |
| #define ADDA_IIR_COEF_04_03_3_SFT 0 |
| #define ADDA_IIR_COEF_04_03_3_MASK 0xff |
| #define ADDA_IIR_COEF_04_03_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_IIR_COEF_04_03_2 */ |
| #define ADDA_IIR_COEF_04_03_2_SFT 0 |
| #define ADDA_IIR_COEF_04_03_2_MASK 0xff |
| #define ADDA_IIR_COEF_04_03_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_IIR_COEF_04_03_1 */ |
| #define ADDA_IIR_COEF_04_03_1_SFT 0 |
| #define ADDA_IIR_COEF_04_03_1_MASK 0xff |
| #define ADDA_IIR_COEF_04_03_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_IIR_COEF_04_03_0 */ |
| #define ADDA_IIR_COEF_04_03_0_SFT 0 |
| #define ADDA_IIR_COEF_04_03_0_MASK 0xff |
| #define ADDA_IIR_COEF_04_03_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_IIR_COEF_06_05_3 */ |
| #define ADDA_IIR_COEF_06_05_3_SFT 0 |
| #define ADDA_IIR_COEF_06_05_3_MASK 0xff |
| #define ADDA_IIR_COEF_06_05_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_IIR_COEF_06_05_2 */ |
| #define ADDA_IIR_COEF_06_05_2_SFT 0 |
| #define ADDA_IIR_COEF_06_05_2_MASK 0xff |
| #define ADDA_IIR_COEF_06_05_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_IIR_COEF_06_05_1 */ |
| #define ADDA_IIR_COEF_06_05_1_SFT 0 |
| #define ADDA_IIR_COEF_06_05_1_MASK 0xff |
| #define ADDA_IIR_COEF_06_05_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_IIR_COEF_06_05_0 */ |
| #define ADDA_IIR_COEF_06_05_0_SFT 0 |
| #define ADDA_IIR_COEF_06_05_0_MASK 0xff |
| #define ADDA_IIR_COEF_06_05_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_IIR_COEF_08_07_3 */ |
| #define ADDA_IIR_COEF_08_07_3_SFT 0 |
| #define ADDA_IIR_COEF_08_07_3_MASK 0xff |
| #define ADDA_IIR_COEF_08_07_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_IIR_COEF_08_07_2 */ |
| #define ADDA_IIR_COEF_08_07_2_SFT 0 |
| #define ADDA_IIR_COEF_08_07_2_MASK 0xff |
| #define ADDA_IIR_COEF_08_07_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_IIR_COEF_08_07_1 */ |
| #define ADDA_IIR_COEF_08_07_1_SFT 0 |
| #define ADDA_IIR_COEF_08_07_1_MASK 0xff |
| #define ADDA_IIR_COEF_08_07_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_IIR_COEF_08_07_0 */ |
| #define ADDA_IIR_COEF_08_07_0_SFT 0 |
| #define ADDA_IIR_COEF_08_07_0_MASK 0xff |
| #define ADDA_IIR_COEF_08_07_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_IIR_COEF_10_09_3 */ |
| #define ADDA_IIR_COEF_10_09_3_SFT 0 |
| #define ADDA_IIR_COEF_10_09_3_MASK 0xff |
| #define ADDA_IIR_COEF_10_09_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_IIR_COEF_10_09_2 */ |
| #define ADDA_IIR_COEF_10_09_2_SFT 0 |
| #define ADDA_IIR_COEF_10_09_2_MASK 0xff |
| #define ADDA_IIR_COEF_10_09_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_IIR_COEF_10_09_1 */ |
| #define ADDA_IIR_COEF_10_09_1_SFT 0 |
| #define ADDA_IIR_COEF_10_09_1_MASK 0xff |
| #define ADDA_IIR_COEF_10_09_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_IIR_COEF_10_09_0 */ |
| #define ADDA_IIR_COEF_10_09_0_SFT 0 |
| #define ADDA_IIR_COEF_10_09_0_MASK 0xff |
| #define ADDA_IIR_COEF_10_09_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_02_01_3 */ |
| #define ADDA_ULCF_CFG_02_01_3_SFT 0 |
| #define ADDA_ULCF_CFG_02_01_3_MASK 0xff |
| #define ADDA_ULCF_CFG_02_01_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_02_01_2 */ |
| #define ADDA_ULCF_CFG_02_01_2_SFT 0 |
| #define ADDA_ULCF_CFG_02_01_2_MASK 0xff |
| #define ADDA_ULCF_CFG_02_01_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_02_01_1 */ |
| #define ADDA_ULCF_CFG_02_01_1_SFT 0 |
| #define ADDA_ULCF_CFG_02_01_1_MASK 0xff |
| #define ADDA_ULCF_CFG_02_01_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_02_01_0 */ |
| #define ADDA_ULCF_CFG_02_01_0_SFT 0 |
| #define ADDA_ULCF_CFG_02_01_0_MASK 0xff |
| #define ADDA_ULCF_CFG_02_01_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_04_03_3 */ |
| #define ADDA_ULCF_CFG_04_03_3_SFT 0 |
| #define ADDA_ULCF_CFG_04_03_3_MASK 0xff |
| #define ADDA_ULCF_CFG_04_03_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_04_03_2 */ |
| #define ADDA_ULCF_CFG_04_03_2_SFT 0 |
| #define ADDA_ULCF_CFG_04_03_2_MASK 0xff |
| #define ADDA_ULCF_CFG_04_03_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_04_03_1 */ |
| #define ADDA_ULCF_CFG_04_03_1_SFT 0 |
| #define ADDA_ULCF_CFG_04_03_1_MASK 0xff |
| #define ADDA_ULCF_CFG_04_03_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_04_03_0 */ |
| #define ADDA_ULCF_CFG_04_03_0_SFT 0 |
| #define ADDA_ULCF_CFG_04_03_0_MASK 0xff |
| #define ADDA_ULCF_CFG_04_03_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_06_05_3 */ |
| #define ADDA_ULCF_CFG_06_05_3_SFT 0 |
| #define ADDA_ULCF_CFG_06_05_3_MASK 0xff |
| #define ADDA_ULCF_CFG_06_05_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_06_05_2 */ |
| #define ADDA_ULCF_CFG_06_05_2_SFT 0 |
| #define ADDA_ULCF_CFG_06_05_2_MASK 0xff |
| #define ADDA_ULCF_CFG_06_05_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_06_05_1 */ |
| #define ADDA_ULCF_CFG_06_05_1_SFT 0 |
| #define ADDA_ULCF_CFG_06_05_1_MASK 0xff |
| #define ADDA_ULCF_CFG_06_05_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_06_05_0 */ |
| #define ADDA_ULCF_CFG_06_05_0_SFT 0 |
| #define ADDA_ULCF_CFG_06_05_0_MASK 0xff |
| #define ADDA_ULCF_CFG_06_05_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_08_07_3 */ |
| #define ADDA_ULCF_CFG_08_07_3_SFT 0 |
| #define ADDA_ULCF_CFG_08_07_3_MASK 0xff |
| #define ADDA_ULCF_CFG_08_07_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_08_07_2 */ |
| #define ADDA_ULCF_CFG_08_07_2_SFT 0 |
| #define ADDA_ULCF_CFG_08_07_2_MASK 0xff |
| #define ADDA_ULCF_CFG_08_07_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_08_07_1 */ |
| #define ADDA_ULCF_CFG_08_07_1_SFT 0 |
| #define ADDA_ULCF_CFG_08_07_1_MASK 0xff |
| #define ADDA_ULCF_CFG_08_07_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_08_07_0 */ |
| #define ADDA_ULCF_CFG_08_07_0_SFT 0 |
| #define ADDA_ULCF_CFG_08_07_0_MASK 0xff |
| #define ADDA_ULCF_CFG_08_07_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_10_09_3 */ |
| #define ADDA_ULCF_CFG_10_09_3_SFT 0 |
| #define ADDA_ULCF_CFG_10_09_3_MASK 0xff |
| #define ADDA_ULCF_CFG_10_09_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_10_09_2 */ |
| #define ADDA_ULCF_CFG_10_09_2_SFT 0 |
| #define ADDA_ULCF_CFG_10_09_2_MASK 0xff |
| #define ADDA_ULCF_CFG_10_09_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_10_09_1 */ |
| #define ADDA_ULCF_CFG_10_09_1_SFT 0 |
| #define ADDA_ULCF_CFG_10_09_1_MASK 0xff |
| #define ADDA_ULCF_CFG_10_09_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_10_09_0 */ |
| #define ADDA_ULCF_CFG_10_09_0_SFT 0 |
| #define ADDA_ULCF_CFG_10_09_0_MASK 0xff |
| #define ADDA_ULCF_CFG_10_09_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_12_11_3 */ |
| #define ADDA_ULCF_CFG_12_11_3_SFT 0 |
| #define ADDA_ULCF_CFG_12_11_3_MASK 0xff |
| #define ADDA_ULCF_CFG_12_11_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_12_11_2 */ |
| #define ADDA_ULCF_CFG_12_11_2_SFT 0 |
| #define ADDA_ULCF_CFG_12_11_2_MASK 0xff |
| #define ADDA_ULCF_CFG_12_11_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_12_11_1 */ |
| #define ADDA_ULCF_CFG_12_11_1_SFT 0 |
| #define ADDA_ULCF_CFG_12_11_1_MASK 0xff |
| #define ADDA_ULCF_CFG_12_11_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_12_11_0 */ |
| #define ADDA_ULCF_CFG_12_11_0_SFT 0 |
| #define ADDA_ULCF_CFG_12_11_0_MASK 0xff |
| #define ADDA_ULCF_CFG_12_11_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_14_13_3 */ |
| #define ADDA_ULCF_CFG_14_13_3_SFT 0 |
| #define ADDA_ULCF_CFG_14_13_3_MASK 0xff |
| #define ADDA_ULCF_CFG_14_13_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_14_13_2 */ |
| #define ADDA_ULCF_CFG_14_13_2_SFT 0 |
| #define ADDA_ULCF_CFG_14_13_2_MASK 0xff |
| #define ADDA_ULCF_CFG_14_13_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_14_13_1 */ |
| #define ADDA_ULCF_CFG_14_13_1_SFT 0 |
| #define ADDA_ULCF_CFG_14_13_1_MASK 0xff |
| #define ADDA_ULCF_CFG_14_13_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_14_13_0 */ |
| #define ADDA_ULCF_CFG_14_13_0_SFT 0 |
| #define ADDA_ULCF_CFG_14_13_0_MASK 0xff |
| #define ADDA_ULCF_CFG_14_13_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_16_15_3 */ |
| #define ADDA_ULCF_CFG_16_15_3_SFT 0 |
| #define ADDA_ULCF_CFG_16_15_3_MASK 0xff |
| #define ADDA_ULCF_CFG_16_15_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_16_15_2 */ |
| #define ADDA_ULCF_CFG_16_15_2_SFT 0 |
| #define ADDA_ULCF_CFG_16_15_2_MASK 0xff |
| #define ADDA_ULCF_CFG_16_15_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_16_15_1 */ |
| #define ADDA_ULCF_CFG_16_15_1_SFT 0 |
| #define ADDA_ULCF_CFG_16_15_1_MASK 0xff |
| #define ADDA_ULCF_CFG_16_15_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_16_15_0 */ |
| #define ADDA_ULCF_CFG_16_15_0_SFT 0 |
| #define ADDA_ULCF_CFG_16_15_0_MASK 0xff |
| #define ADDA_ULCF_CFG_16_15_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_18_17_3 */ |
| #define ADDA_ULCF_CFG_18_17_3_SFT 0 |
| #define ADDA_ULCF_CFG_18_17_3_MASK 0xff |
| #define ADDA_ULCF_CFG_18_17_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_18_17_2 */ |
| #define ADDA_ULCF_CFG_18_17_2_SFT 0 |
| #define ADDA_ULCF_CFG_18_17_2_MASK 0xff |
| #define ADDA_ULCF_CFG_18_17_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_18_17_1 */ |
| #define ADDA_ULCF_CFG_18_17_1_SFT 0 |
| #define ADDA_ULCF_CFG_18_17_1_MASK 0xff |
| #define ADDA_ULCF_CFG_18_17_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_18_17_0 */ |
| #define ADDA_ULCF_CFG_18_17_0_SFT 0 |
| #define ADDA_ULCF_CFG_18_17_0_MASK 0xff |
| #define ADDA_ULCF_CFG_18_17_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_20_19_3 */ |
| #define ADDA_ULCF_CFG_20_19_3_SFT 0 |
| #define ADDA_ULCF_CFG_20_19_3_MASK 0xff |
| #define ADDA_ULCF_CFG_20_19_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_20_19_2 */ |
| #define ADDA_ULCF_CFG_20_19_2_SFT 0 |
| #define ADDA_ULCF_CFG_20_19_2_MASK 0xff |
| #define ADDA_ULCF_CFG_20_19_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_20_19_1 */ |
| #define ADDA_ULCF_CFG_20_19_1_SFT 0 |
| #define ADDA_ULCF_CFG_20_19_1_MASK 0xff |
| #define ADDA_ULCF_CFG_20_19_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_20_19_0 */ |
| #define ADDA_ULCF_CFG_20_19_0_SFT 0 |
| #define ADDA_ULCF_CFG_20_19_0_MASK 0xff |
| #define ADDA_ULCF_CFG_20_19_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_22_21_3 */ |
| #define ADDA_ULCF_CFG_22_21_3_SFT 0 |
| #define ADDA_ULCF_CFG_22_21_3_MASK 0xff |
| #define ADDA_ULCF_CFG_22_21_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_22_21_2 */ |
| #define ADDA_ULCF_CFG_22_21_2_SFT 0 |
| #define ADDA_ULCF_CFG_22_21_2_MASK 0xff |
| #define ADDA_ULCF_CFG_22_21_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_22_21_1 */ |
| #define ADDA_ULCF_CFG_22_21_1_SFT 0 |
| #define ADDA_ULCF_CFG_22_21_1_MASK 0xff |
| #define ADDA_ULCF_CFG_22_21_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_22_21_0 */ |
| #define ADDA_ULCF_CFG_22_21_0_SFT 0 |
| #define ADDA_ULCF_CFG_22_21_0_MASK 0xff |
| #define ADDA_ULCF_CFG_22_21_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_24_23_3 */ |
| #define ADDA_ULCF_CFG_24_23_3_SFT 0 |
| #define ADDA_ULCF_CFG_24_23_3_MASK 0xff |
| #define ADDA_ULCF_CFG_24_23_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_24_23_2 */ |
| #define ADDA_ULCF_CFG_24_23_2_SFT 0 |
| #define ADDA_ULCF_CFG_24_23_2_MASK 0xff |
| #define ADDA_ULCF_CFG_24_23_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_24_23_1 */ |
| #define ADDA_ULCF_CFG_24_23_1_SFT 0 |
| #define ADDA_ULCF_CFG_24_23_1_MASK 0xff |
| #define ADDA_ULCF_CFG_24_23_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_24_23_0 */ |
| #define ADDA_ULCF_CFG_24_23_0_SFT 0 |
| #define ADDA_ULCF_CFG_24_23_0_MASK 0xff |
| #define ADDA_ULCF_CFG_24_23_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_26_25_3 */ |
| #define ADDA_ULCF_CFG_26_25_3_SFT 0 |
| #define ADDA_ULCF_CFG_26_25_3_MASK 0xff |
| #define ADDA_ULCF_CFG_26_25_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_26_25_2 */ |
| #define ADDA_ULCF_CFG_26_25_2_SFT 0 |
| #define ADDA_ULCF_CFG_26_25_2_MASK 0xff |
| #define ADDA_ULCF_CFG_26_25_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_26_25_1 */ |
| #define ADDA_ULCF_CFG_26_25_1_SFT 0 |
| #define ADDA_ULCF_CFG_26_25_1_MASK 0xff |
| #define ADDA_ULCF_CFG_26_25_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_26_25_0 */ |
| #define ADDA_ULCF_CFG_26_25_0_SFT 0 |
| #define ADDA_ULCF_CFG_26_25_0_MASK 0xff |
| #define ADDA_ULCF_CFG_26_25_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_28_27_3 */ |
| #define ADDA_ULCF_CFG_28_27_3_SFT 0 |
| #define ADDA_ULCF_CFG_28_27_3_MASK 0xff |
| #define ADDA_ULCF_CFG_28_27_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_28_27_2 */ |
| #define ADDA_ULCF_CFG_28_27_2_SFT 0 |
| #define ADDA_ULCF_CFG_28_27_2_MASK 0xff |
| #define ADDA_ULCF_CFG_28_27_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_28_27_1 */ |
| #define ADDA_ULCF_CFG_28_27_1_SFT 0 |
| #define ADDA_ULCF_CFG_28_27_1_MASK 0xff |
| #define ADDA_ULCF_CFG_28_27_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_28_27_0 */ |
| #define ADDA_ULCF_CFG_28_27_0_SFT 0 |
| #define ADDA_ULCF_CFG_28_27_0_MASK 0xff |
| #define ADDA_ULCF_CFG_28_27_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_30_29_3 */ |
| #define ADDA_ULCF_CFG_30_29_3_SFT 0 |
| #define ADDA_ULCF_CFG_30_29_3_MASK 0xff |
| #define ADDA_ULCF_CFG_30_29_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_30_29_2 */ |
| #define ADDA_ULCF_CFG_30_29_2_SFT 0 |
| #define ADDA_ULCF_CFG_30_29_2_MASK 0xff |
| #define ADDA_ULCF_CFG_30_29_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_30_29_1 */ |
| #define ADDA_ULCF_CFG_30_29_1_SFT 0 |
| #define ADDA_ULCF_CFG_30_29_1_MASK 0xff |
| #define ADDA_ULCF_CFG_30_29_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_30_29_0 */ |
| #define ADDA_ULCF_CFG_30_29_0_SFT 0 |
| #define ADDA_ULCF_CFG_30_29_0_MASK 0xff |
| #define ADDA_ULCF_CFG_30_29_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_32_31_3 */ |
| #define ADDA_ULCF_CFG_32_31_3_SFT 0 |
| #define ADDA_ULCF_CFG_32_31_3_MASK 0xff |
| #define ADDA_ULCF_CFG_32_31_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_32_31_2 */ |
| #define ADDA_ULCF_CFG_32_31_2_SFT 0 |
| #define ADDA_ULCF_CFG_32_31_2_MASK 0xff |
| #define ADDA_ULCF_CFG_32_31_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_32_31_1 */ |
| #define ADDA_ULCF_CFG_32_31_1_SFT 0 |
| #define ADDA_ULCF_CFG_32_31_1_MASK 0xff |
| #define ADDA_ULCF_CFG_32_31_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_ULCF_CFG_32_31_0 */ |
| #define ADDA_ULCF_CFG_32_31_0_SFT 0 |
| #define ADDA_ULCF_CFG_32_31_0_MASK 0xff |
| #define ADDA_ULCF_CFG_32_31_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_UL_SRC_MON0_3 */ |
| #define ADDA_UL_SRC_ON_MON_SFT 7 |
| #define ADDA_UL_SRC_ON_MON_MASK 0x1 |
| #define ADDA_UL_SRC_ON_MON_MASK_SFT (0x1 << 7) |
| #define ADDA_UL_SDM_3_LEVEL_MON_SFT 6 |
| #define ADDA_UL_SDM_3_LEVEL_MON_MASK 0x1 |
| #define ADDA_UL_SDM_3_LEVEL_MON_MASK_SFT (0x1 << 6) |
| #define ADDA_UL_LOOP_BACK_MODE_MON_SFT 5 |
| #define ADDA_UL_LOOP_BACK_MODE_MON_MASK 0x1 |
| #define ADDA_UL_LOOP_BACK_MODE_MON_MASK_SFT (0x1 << 5) |
| #define ADDA_DATA_COMB_IN_CH1_SFT 0 |
| #define ADDA_DATA_COMB_IN_CH1_MASK 0x1f |
| #define ADDA_DATA_COMB_IN_CH1_MASK_SFT (0x1f << 0) |
| |
| /* AFE_ADDA_UL_SRC_MON0_2 */ |
| #define ADDA_DATA_COMB_OUT_CH1_2_SFT 0 |
| #define ADDA_DATA_COMB_OUT_CH1_2_MASK 0xff |
| #define ADDA_DATA_COMB_OUT_CH1_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_UL_SRC_MON0_1 */ |
| #define ADDA_DATA_COMB_OUT_CH1_1_SFT 0 |
| #define ADDA_DATA_COMB_OUT_CH1_1_MASK 0xff |
| #define ADDA_DATA_COMB_OUT_CH1_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_UL_SRC_MON0_0 */ |
| #define ADDA_DATA_COMB_OUT_CH1_0_SFT 0 |
| #define ADDA_DATA_COMB_OUT_CH1_0_MASK 0xff |
| #define ADDA_DATA_COMB_OUT_CH1_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_UL_SRC_MON1_3 */ |
| #define ADDA_UL_VOICE_MODE_CTL_SFT 5 |
| #define ADDA_UL_VOICE_MODE_CTL_MASK 0x7 |
| #define ADDA_UL_VOICE_MODE_CTL_MASK_SFT (0x7 << 5) |
| #define ADDA_DATA_COMB_IN_CH2_SFT 0 |
| #define ADDA_DATA_COMB_IN_CH2_MASK 0x1f |
| #define ADDA_DATA_COMB_IN_CH2_MASK_SFT (0x1f << 0) |
| |
| /* AFE_ADDA_UL_SRC_MON1_2 */ |
| #define ADDA_DATA_COMB_OUT_CH2_2_SFT 0 |
| #define ADDA_DATA_COMB_OUT_CH2_2_MASK 0xff |
| #define ADDA_DATA_COMB_OUT_CH2_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_UL_SRC_MON1_1 */ |
| #define ADDA_DATA_COMB_OUT_CH2_1_SFT 0 |
| #define ADDA_DATA_COMB_OUT_CH2_1_MASK 0xff |
| #define ADDA_DATA_COMB_OUT_CH2_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_UL_SRC_MON1_0 */ |
| #define ADDA_DATA_COMB_OUT_CH2_0_SFT 0 |
| #define ADDA_DATA_COMB_OUT_CH2_0_MASK 0xff |
| #define ADDA_DATA_COMB_OUT_CH2_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_SRC_DEBUG_1 */ |
| #define ADDA_UL_SLT_CNT_FLAG_RESET_CTL_SFT 3 |
| #define ADDA_UL_SLT_CNT_FLAG_RESET_CTL_MASK 0x1 |
| #define ADDA_UL_SLT_CNT_FLAG_RESET_CTL_MASK_SFT (0x1 << 3) |
| #define ADDA_SLT_CNT_THD_CTL_1_SFT 0 |
| #define ADDA_SLT_CNT_THD_CTL_1_MASK 0x7 |
| #define ADDA_SLT_CNT_THD_CTL_1_MASK_SFT (0x7 << 0) |
| |
| /* AFE_ADDA_SRC_DEBUG_0 */ |
| #define ADDA_SLT_CNT_THD_CTL_0_SFT 0 |
| #define ADDA_SLT_CNT_THD_CTL_0_MASK 0xff |
| #define ADDA_SLT_CNT_THD_CTL_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_SRC_DEBUG_MON0_1 */ |
| #define ADDA_SLT_CNT_FLAG_CTL_SFT 4 |
| #define ADDA_SLT_CNT_FLAG_CTL_MASK 0x1 |
| #define ADDA_SLT_CNT_FLAG_CTL_MASK_SFT (0x1 << 4) |
| #define ADDA_SLT_COUNTER_CTL_1_SFT 0 |
| #define ADDA_SLT_COUNTER_CTL_1_MASK 0xf |
| #define ADDA_SLT_COUNTER_CTL_1_MASK_SFT (0xf << 0) |
| |
| /* AFE_ADDA_SRC_DEBUG_MON0_0 */ |
| #define ADDA_SLT_COUNTER_CTL_0_SFT 0 |
| #define ADDA_SLT_COUNTER_CTL_0_MASK 0xff |
| #define ADDA_SLT_COUNTER_CTL_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_UL_SRC_CON0_3 */ |
| #define ADDA6_ULCF_CFG_EN_CTL_SFT 7 |
| #define ADDA6_ULCF_CFG_EN_CTL_MASK 0x1 |
| #define ADDA6_ULCF_CFG_EN_CTL_MASK_SFT (0x1 << 7) |
| #define ADDA6_UL_DMIC_PHASE_SEL_CH1_SFT 3 |
| #define ADDA6_UL_DMIC_PHASE_SEL_CH1_MASK 0x7 |
| #define ADDA6_UL_DMIC_PHASE_SEL_CH1_MASK_SFT (0x7 << 3) |
| #define ADDA6_UL_DMIC_PHASE_SEL_CH2_SFT 0 |
| #define ADDA6_UL_DMIC_PHASE_SEL_CH2_MASK 0x7 |
| #define ADDA6_UL_DMIC_PHASE_SEL_CH2_MASK_SFT (0x7 << 0) |
| |
| /* AFE_ADDA6_UL_SRC_CON0_2 */ |
| #define ADDA6_UL_TWO_WIRE_MODE_CTL_SFT 7 |
| #define ADDA6_UL_TWO_WIRE_MODE_CTL_MASK 0x1 |
| #define ADDA6_UL_TWO_WIRE_MODE_CTL_MASK_SFT (0x1 << 7) |
| #define ADDA6_UL_GAIN_MODE_SFT 5 |
| #define ADDA6_UL_GAIN_MODE_MASK 0x3 |
| #define ADDA6_UL_GAIN_MODE_MASK_SFT (0x3 << 5) |
| #define ADDA6_UL_MODE_3P25M_CH2_CTL_SFT 4 |
| #define ADDA6_UL_MODE_3P25M_CH2_CTL_MASK 0x1 |
| #define ADDA6_UL_MODE_3P25M_CH2_CTL_MASK_SFT (0x1 << 4) |
| #define ADDA6_UL_MODE_3P25M_CH1_CTL_SFT 3 |
| #define ADDA6_UL_MODE_3P25M_CH1_CTL_MASK 0x1 |
| #define ADDA6_UL_MODE_3P25M_CH1_CTL_MASK_SFT (0x1 << 3) |
| #define ADDA6_UL_VOICE_MODE_CH1_CH2_CTL_SFT 0 |
| #define ADDA6_UL_VOICE_MODE_CH1_CH2_CTL_MASK 0x7 |
| #define ADDA6_UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT (0x7 << 0) |
| |
| /* AFE_ADDA6_UL_SRC_CON0_1 */ |
| #define ADDA6_DMIC_LOW_POWER_MODE_CTL_SFT 5 |
| #define ADDA6_DMIC_LOW_POWER_MODE_CTL_MASK 0x3 |
| #define ADDA6_DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 5) |
| #define ADDA6_UL_DISABLE_HW_CG_CTL_SFT 4 |
| #define ADDA6_UL_DISABLE_HW_CG_CTL_MASK 0x1 |
| #define ADDA6_UL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 4) |
| #define ADDA6_UL_IIR_ON_TMP_CTL_SFT 3 |
| #define ADDA6_UL_IIR_ON_TMP_CTL_MASK 0x1 |
| #define ADDA6_UL_IIR_ON_TMP_CTL_MASK_SFT (0x1 << 3) |
| #define ADDA6_UL_IIRMODE_CTL_SFT 0 |
| #define ADDA6_UL_IIRMODE_CTL_MASK 0x7 |
| #define ADDA6_UL_IIRMODE_CTL_MASK_SFT (0x7 << 0) |
| |
| /* AFE_ADDA6_UL_SRC_CON0_0 */ |
| #define ADDA6_DIGMIC_4P33M_SEL_SFT 6 |
| #define ADDA6_DIGMIC_4P33M_SEL_MASK 0x1 |
| #define ADDA6_DIGMIC_4P33M_SEL_MASK_SFT (0x1 << 6) |
| #define ADDA6_DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5 |
| #define ADDA6_DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1 |
| #define ADDA6_DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5) |
| #define ADDA6_UL_LOOP_BACK_MODE_CTL_SFT 2 |
| #define ADDA6_UL_LOOP_BACK_MODE_CTL_MASK 0x1 |
| #define ADDA6_UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2) |
| #define ADDA6_UL_SDM_3_LEVEL_CTL_SFT 1 |
| #define ADDA6_UL_SDM_3_LEVEL_CTL_MASK 0x1 |
| #define ADDA6_UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1) |
| #define ADDA6_UL_SRC_ON_TMP_CTL_SFT 0 |
| #define ADDA6_UL_SRC_ON_TMP_CTL_MASK 0x1 |
| #define ADDA6_UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0) |
| |
| /* AFE_ADDA6_UL_SRC_CON1_3 */ |
| #define ADDA6_C_DAC_EN_CTL_SFT 7 |
| #define ADDA6_C_DAC_EN_CTL_MASK 0x1 |
| #define ADDA6_C_DAC_EN_CTL_MASK_SFT (0x1 << 7) |
| #define ADDA6_C_MUTE_SW_CTL_SFT 6 |
| #define ADDA6_C_MUTE_SW_CTL_MASK 0x1 |
| #define ADDA6_C_MUTE_SW_CTL_MASK_SFT (0x1 << 6) |
| #define ADDA6_ASDM_SRC_SEL_CTL_SFT 5 |
| #define ADDA6_ASDM_SRC_SEL_CTL_MASK 0x1 |
| #define ADDA6_ASDM_SRC_SEL_CTL_MASK_SFT (0x1 << 5) |
| #define ADDA6_C_FREQ_DIV_CH2_CTL_SFT 0 |
| #define ADDA6_C_FREQ_DIV_CH2_CTL_MASK 0x1f |
| #define ADDA6_C_FREQ_DIV_CH2_CTL_MASK_SFT (0x1f << 0) |
| |
| /* AFE_ADDA6_UL_SRC_CON1_2 */ |
| #define ADDA6_C_AMP_DIV_CH2_CTL_SFT 4 |
| #define ADDA6_C_AMP_DIV_CH2_CTL_MASK 0x7 |
| #define ADDA6_C_AMP_DIV_CH2_CTL_MASK_SFT (0x7 << 4) |
| #define ADDA6_C_SINE_MODE_CH2_CTL_SFT 0 |
| #define ADDA6_C_SINE_MODE_CH2_CTL_MASK 0xf |
| #define ADDA6_C_SINE_MODE_CH2_CTL_MASK_SFT (0xf << 0) |
| |
| /* AFE_ADDA6_UL_SRC_CON1_1 */ |
| #define ADDA6_C_FREQ_DIV_CH1_CTL_SFT 0 |
| #define ADDA6_C_FREQ_DIV_CH1_CTL_MASK 0x1f |
| #define ADDA6_C_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 0) |
| |
| /* AFE_ADDA6_UL_SRC_CON1_0 */ |
| #define ADDA6_C_AMP_DIV_CH1_CTL_SFT 4 |
| #define ADDA6_C_AMP_DIV_CH1_CTL_MASK 0x7 |
| #define ADDA6_C_AMP_DIV_CH1_CTL_MASK_SFT (0x7 << 4) |
| #define ADDA6_C_SINE_MODE_CH1_CTL_SFT 0 |
| #define ADDA6_C_SINE_MODE_CH1_CTL_MASK 0xf |
| #define ADDA6_C_SINE_MODE_CH1_CTL_MASK_SFT (0xf << 0) |
| |
| /* AUDIO_DIG_5TH_DSN_ID */ |
| #define AUDIO_DIG_5TH_ANA_ID_SFT 0 |
| #define AUDIO_DIG_5TH_ANA_ID_MASK 0xff |
| #define AUDIO_DIG_5TH_ANA_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_5TH_DSN_ID_H */ |
| #define AUDIO_DIG_5TH_DIG_ID_SFT 0 |
| #define AUDIO_DIG_5TH_DIG_ID_MASK 0xff |
| #define AUDIO_DIG_5TH_DIG_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_5TH_DSN_REV0 */ |
| #define AUDIO_DIG_5TH_ANA_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_5TH_ANA_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_5TH_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_5TH_ANA_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_5TH_ANA_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_5TH_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_5TH_DSN_REV0_H */ |
| #define AUDIO_DIG_5TH_DIG_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_5TH_DIG_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_5TH_DIG_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_5TH_DIG_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_5TH_DIG_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_5TH_DIG_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_5TH_DSN_DBI */ |
| #define AUDIO_DIG_5TH_DSN_CBS_SFT 0 |
| #define AUDIO_DIG_5TH_DSN_CBS_MASK 0x3 |
| #define AUDIO_DIG_5TH_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDIO_DIG_5TH_DSN_BIX_SFT 2 |
| #define AUDIO_DIG_5TH_DSN_BIX_MASK 0x3 |
| #define AUDIO_DIG_5TH_DSN_BIX_MASK_SFT (0x3 << 2) |
| |
| /* AUDIO_DIG_5TH_DSN_DBI_H */ |
| #define AUDIO_DIG_5_ESP_SFT 0 |
| #define AUDIO_DIG_5_ESP_MASK 0xff |
| #define AUDIO_DIG_5_ESP_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_5TH_DSN_DXI */ |
| #define AUDIO_DIG_5TH_DSN_FPI_SFT 0 |
| #define AUDIO_DIG_5TH_DSN_FPI_MASK 0xff |
| #define AUDIO_DIG_5TH_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_UL_SRC_CON2_3 */ |
| #define ADDA6_UL_ODDTAP_MODE_SFT 6 |
| #define ADDA6_UL_ODDTAP_MODE_MASK 0x1 |
| #define ADDA6_UL_ODDTAP_MODE_MASK_SFT (0x1 << 6) |
| #define ADDA6_UL_HALF_TAP_NUM_SFT 0 |
| #define ADDA6_UL_HALF_TAP_NUM_MASK 0x3f |
| #define ADDA6_UL_HALF_TAP_NUM_MASK_SFT (0x3f << 0) |
| |
| /* AFE_ADDA6_UL_SRC_CON2_2 */ |
| #define ADDA6_UL_NEW_GAIN_MODE_SFT 3 |
| #define ADDA6_UL_NEW_GAIN_MODE_MASK 0x3 |
| #define ADDA6_UL_NEW_GAIN_MODE_MASK_SFT (0x3 << 3) |
| #define ADDA6_UL_POSTIVEGAIN_SFT 0 |
| #define ADDA6_UL_POSTIVEGAIN_MASK 0x7 |
| #define ADDA6_UL_POSTIVEGAIN_MASK_SFT (0x7 << 0) |
| |
| /* AFE_ADDA6_UL_SRC_CON2_1 */ |
| #define ADDA6_UL_GAIN_VALUE_1_SFT 0 |
| #define ADDA6_UL_GAIN_VALUE_1_MASK 0xff |
| #define ADDA6_UL_GAIN_VALUE_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_UL_SRC_CON2_0 */ |
| #define ADDA6_UL_GAIN_VALUE_0_SFT 0 |
| #define ADDA6_UL_GAIN_VALUE_0_MASK 0xff |
| #define ADDA6_UL_GAIN_VALUE_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_IIR_COEF_02_01_3 */ |
| #define ADDA6_IIR_COEF_02_01_3_SFT 0 |
| #define ADDA6_IIR_COEF_02_01_3_MASK 0xff |
| #define ADDA6_IIR_COEF_02_01_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_IIR_COEF_02_01_2 */ |
| #define ADDA6_IIR_COEF_02_01_2_SFT 0 |
| #define ADDA6_IIR_COEF_02_01_2_MASK 0xff |
| #define ADDA6_IIR_COEF_02_01_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_IIR_COEF_02_01_1 */ |
| #define ADDA6_IIR_COEF_02_01_1_SFT 0 |
| #define ADDA6_IIR_COEF_02_01_1_MASK 0xff |
| #define ADDA6_IIR_COEF_02_01_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_IIR_COEF_02_01_0 */ |
| #define ADDA6_IIR_COEF_02_01_0_SFT 0 |
| #define ADDA6_IIR_COEF_02_01_0_MASK 0xff |
| #define ADDA6_IIR_COEF_02_01_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_IIR_COEF_04_03_3 */ |
| #define ADDA6_IIR_COEF_04_03_3_SFT 0 |
| #define ADDA6_IIR_COEF_04_03_3_MASK 0xff |
| #define ADDA6_IIR_COEF_04_03_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_IIR_COEF_04_03_2 */ |
| #define ADDA6_IIR_COEF_04_03_2_SFT 0 |
| #define ADDA6_IIR_COEF_04_03_2_MASK 0xff |
| #define ADDA6_IIR_COEF_04_03_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_IIR_COEF_04_03_1 */ |
| #define ADDA6_IIR_COEF_04_03_1_SFT 0 |
| #define ADDA6_IIR_COEF_04_03_1_MASK 0xff |
| #define ADDA6_IIR_COEF_04_03_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_IIR_COEF_04_03_0 */ |
| #define ADDA6_IIR_COEF_04_03_0_SFT 0 |
| #define ADDA6_IIR_COEF_04_03_0_MASK 0xff |
| #define ADDA6_IIR_COEF_04_03_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_IIR_COEF_06_05_3 */ |
| #define ADDA6_IIR_COEF_06_05_3_SFT 0 |
| #define ADDA6_IIR_COEF_06_05_3_MASK 0xff |
| #define ADDA6_IIR_COEF_06_05_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_IIR_COEF_06_05_2 */ |
| #define ADDA6_IIR_COEF_06_05_2_SFT 0 |
| #define ADDA6_IIR_COEF_06_05_2_MASK 0xff |
| #define ADDA6_IIR_COEF_06_05_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_IIR_COEF_06_05_1 */ |
| #define ADDA6_IIR_COEF_06_05_1_SFT 0 |
| #define ADDA6_IIR_COEF_06_05_1_MASK 0xff |
| #define ADDA6_IIR_COEF_06_05_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_IIR_COEF_06_05_0 */ |
| #define ADDA6_IIR_COEF_06_05_0_SFT 0 |
| #define ADDA6_IIR_COEF_06_05_0_MASK 0xff |
| #define ADDA6_IIR_COEF_06_05_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_IIR_COEF_08_07_3 */ |
| #define ADDA6_IIR_COEF_08_07_3_SFT 0 |
| #define ADDA6_IIR_COEF_08_07_3_MASK 0xff |
| #define ADDA6_IIR_COEF_08_07_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_IIR_COEF_08_07_2 */ |
| #define ADDA6_IIR_COEF_08_07_2_SFT 0 |
| #define ADDA6_IIR_COEF_08_07_2_MASK 0xff |
| #define ADDA6_IIR_COEF_08_07_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_IIR_COEF_08_07_1 */ |
| #define ADDA6_IIR_COEF_08_07_1_SFT 0 |
| #define ADDA6_IIR_COEF_08_07_1_MASK 0xff |
| #define ADDA6_IIR_COEF_08_07_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_IIR_COEF_08_07_0 */ |
| #define ADDA6_IIR_COEF_08_07_0_SFT 0 |
| #define ADDA6_IIR_COEF_08_07_0_MASK 0xff |
| #define ADDA6_IIR_COEF_08_07_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_IIR_COEF_10_09_3 */ |
| #define ADDA6_IIR_COEF_10_09_3_SFT 0 |
| #define ADDA6_IIR_COEF_10_09_3_MASK 0xff |
| #define ADDA6_IIR_COEF_10_09_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_IIR_COEF_10_09_2 */ |
| #define ADDA6_IIR_COEF_10_09_2_SFT 0 |
| #define ADDA6_IIR_COEF_10_09_2_MASK 0xff |
| #define ADDA6_IIR_COEF_10_09_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_IIR_COEF_10_09_1 */ |
| #define ADDA6_IIR_COEF_10_09_1_SFT 0 |
| #define ADDA6_IIR_COEF_10_09_1_MASK 0xff |
| #define ADDA6_IIR_COEF_10_09_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_IIR_COEF_10_09_0 */ |
| #define ADDA6_IIR_COEF_10_09_0_SFT 0 |
| #define ADDA6_IIR_COEF_10_09_0_MASK 0xff |
| #define ADDA6_IIR_COEF_10_09_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_02_01_3 */ |
| #define ADDA6_ULCF_CFG_02_01_3_SFT 0 |
| #define ADDA6_ULCF_CFG_02_01_3_MASK 0xff |
| #define ADDA6_ULCF_CFG_02_01_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_02_01_2 */ |
| #define ADDA6_ULCF_CFG_02_01_2_SFT 0 |
| #define ADDA6_ULCF_CFG_02_01_2_MASK 0xff |
| #define ADDA6_ULCF_CFG_02_01_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_02_01_1 */ |
| #define ADDA6_ULCF_CFG_02_01_1_SFT 0 |
| #define ADDA6_ULCF_CFG_02_01_1_MASK 0xff |
| #define ADDA6_ULCF_CFG_02_01_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_02_01_0 */ |
| #define ADDA6_ULCF_CFG_02_01_0_SFT 0 |
| #define ADDA6_ULCF_CFG_02_01_0_MASK 0xff |
| #define ADDA6_ULCF_CFG_02_01_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_04_03_3 */ |
| #define ADDA6_ULCF_CFG_04_03_3_SFT 0 |
| #define ADDA6_ULCF_CFG_04_03_3_MASK 0xff |
| #define ADDA6_ULCF_CFG_04_03_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_04_03_2 */ |
| #define ADDA6_ULCF_CFG_04_03_2_SFT 0 |
| #define ADDA6_ULCF_CFG_04_03_2_MASK 0xff |
| #define ADDA6_ULCF_CFG_04_03_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_04_03_1 */ |
| #define ADDA6_ULCF_CFG_04_03_1_SFT 0 |
| #define ADDA6_ULCF_CFG_04_03_1_MASK 0xff |
| #define ADDA6_ULCF_CFG_04_03_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_04_03_0 */ |
| #define ADDA6_ULCF_CFG_04_03_0_SFT 0 |
| #define ADDA6_ULCF_CFG_04_03_0_MASK 0xff |
| #define ADDA6_ULCF_CFG_04_03_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_06_05_3 */ |
| #define ADDA6_ULCF_CFG_06_05_3_SFT 0 |
| #define ADDA6_ULCF_CFG_06_05_3_MASK 0xff |
| #define ADDA6_ULCF_CFG_06_05_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_06_05_2 */ |
| #define ADDA6_ULCF_CFG_06_05_2_SFT 0 |
| #define ADDA6_ULCF_CFG_06_05_2_MASK 0xff |
| #define ADDA6_ULCF_CFG_06_05_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_06_05_1 */ |
| #define ADDA6_ULCF_CFG_06_05_1_SFT 0 |
| #define ADDA6_ULCF_CFG_06_05_1_MASK 0xff |
| #define ADDA6_ULCF_CFG_06_05_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_06_05_0 */ |
| #define ADDA6_ULCF_CFG_06_05_0_SFT 0 |
| #define ADDA6_ULCF_CFG_06_05_0_MASK 0xff |
| #define ADDA6_ULCF_CFG_06_05_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_08_07_3 */ |
| #define ADDA6_ULCF_CFG_08_07_3_SFT 0 |
| #define ADDA6_ULCF_CFG_08_07_3_MASK 0xff |
| #define ADDA6_ULCF_CFG_08_07_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_08_07_2 */ |
| #define ADDA6_ULCF_CFG_08_07_2_SFT 0 |
| #define ADDA6_ULCF_CFG_08_07_2_MASK 0xff |
| #define ADDA6_ULCF_CFG_08_07_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_08_07_1 */ |
| #define ADDA6_ULCF_CFG_08_07_1_SFT 0 |
| #define ADDA6_ULCF_CFG_08_07_1_MASK 0xff |
| #define ADDA6_ULCF_CFG_08_07_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_08_07_0 */ |
| #define ADDA6_ULCF_CFG_08_07_0_SFT 0 |
| #define ADDA6_ULCF_CFG_08_07_0_MASK 0xff |
| #define ADDA6_ULCF_CFG_08_07_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_10_09_3 */ |
| #define ADDA6_ULCF_CFG_10_09_3_SFT 0 |
| #define ADDA6_ULCF_CFG_10_09_3_MASK 0xff |
| #define ADDA6_ULCF_CFG_10_09_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_10_09_2 */ |
| #define ADDA6_ULCF_CFG_10_09_2_SFT 0 |
| #define ADDA6_ULCF_CFG_10_09_2_MASK 0xff |
| #define ADDA6_ULCF_CFG_10_09_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_10_09_1 */ |
| #define ADDA6_ULCF_CFG_10_09_1_SFT 0 |
| #define ADDA6_ULCF_CFG_10_09_1_MASK 0xff |
| #define ADDA6_ULCF_CFG_10_09_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_10_09_0 */ |
| #define ADDA6_ULCF_CFG_10_09_0_SFT 0 |
| #define ADDA6_ULCF_CFG_10_09_0_MASK 0xff |
| #define ADDA6_ULCF_CFG_10_09_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_12_11_3 */ |
| #define ADDA6_ULCF_CFG_12_11_3_SFT 0 |
| #define ADDA6_ULCF_CFG_12_11_3_MASK 0xff |
| #define ADDA6_ULCF_CFG_12_11_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_12_11_2 */ |
| #define ADDA6_ULCF_CFG_12_11_2_SFT 0 |
| #define ADDA6_ULCF_CFG_12_11_2_MASK 0xff |
| #define ADDA6_ULCF_CFG_12_11_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_12_11_1 */ |
| #define ADDA6_ULCF_CFG_12_11_1_SFT 0 |
| #define ADDA6_ULCF_CFG_12_11_1_MASK 0xff |
| #define ADDA6_ULCF_CFG_12_11_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_12_11_0 */ |
| #define ADDA6_ULCF_CFG_12_11_0_SFT 0 |
| #define ADDA6_ULCF_CFG_12_11_0_MASK 0xff |
| #define ADDA6_ULCF_CFG_12_11_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_14_13_3 */ |
| #define ADDA6_ULCF_CFG_14_13_3_SFT 0 |
| #define ADDA6_ULCF_CFG_14_13_3_MASK 0xff |
| #define ADDA6_ULCF_CFG_14_13_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_14_13_2 */ |
| #define ADDA6_ULCF_CFG_14_13_2_SFT 0 |
| #define ADDA6_ULCF_CFG_14_13_2_MASK 0xff |
| #define ADDA6_ULCF_CFG_14_13_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_14_13_1 */ |
| #define ADDA6_ULCF_CFG_14_13_1_SFT 0 |
| #define ADDA6_ULCF_CFG_14_13_1_MASK 0xff |
| #define ADDA6_ULCF_CFG_14_13_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_14_13_0 */ |
| #define ADDA6_ULCF_CFG_14_13_0_SFT 0 |
| #define ADDA6_ULCF_CFG_14_13_0_MASK 0xff |
| #define ADDA6_ULCF_CFG_14_13_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_16_15_3 */ |
| #define ADDA6_ULCF_CFG_16_15_3_SFT 0 |
| #define ADDA6_ULCF_CFG_16_15_3_MASK 0xff |
| #define ADDA6_ULCF_CFG_16_15_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_16_15_2 */ |
| #define ADDA6_ULCF_CFG_16_15_2_SFT 0 |
| #define ADDA6_ULCF_CFG_16_15_2_MASK 0xff |
| #define ADDA6_ULCF_CFG_16_15_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_16_15_1 */ |
| #define ADDA6_ULCF_CFG_16_15_1_SFT 0 |
| #define ADDA6_ULCF_CFG_16_15_1_MASK 0xff |
| #define ADDA6_ULCF_CFG_16_15_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_16_15_0 */ |
| #define ADDA6_ULCF_CFG_16_15_0_SFT 0 |
| #define ADDA6_ULCF_CFG_16_15_0_MASK 0xff |
| #define ADDA6_ULCF_CFG_16_15_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_18_17_3 */ |
| #define ADDA6_ULCF_CFG_18_17_3_SFT 0 |
| #define ADDA6_ULCF_CFG_18_17_3_MASK 0xff |
| #define ADDA6_ULCF_CFG_18_17_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_18_17_2 */ |
| #define ADDA6_ULCF_CFG_18_17_2_SFT 0 |
| #define ADDA6_ULCF_CFG_18_17_2_MASK 0xff |
| #define ADDA6_ULCF_CFG_18_17_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_18_17_1 */ |
| #define ADDA6_ULCF_CFG_18_17_1_SFT 0 |
| #define ADDA6_ULCF_CFG_18_17_1_MASK 0xff |
| #define ADDA6_ULCF_CFG_18_17_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_18_17_0 */ |
| #define ADDA6_ULCF_CFG_18_17_0_SFT 0 |
| #define ADDA6_ULCF_CFG_18_17_0_MASK 0xff |
| #define ADDA6_ULCF_CFG_18_17_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_20_19_3 */ |
| #define ADDA6_ULCF_CFG_20_19_3_SFT 0 |
| #define ADDA6_ULCF_CFG_20_19_3_MASK 0xff |
| #define ADDA6_ULCF_CFG_20_19_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_20_19_2 */ |
| #define ADDA6_ULCF_CFG_20_19_2_SFT 0 |
| #define ADDA6_ULCF_CFG_20_19_2_MASK 0xff |
| #define ADDA6_ULCF_CFG_20_19_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_20_19_1 */ |
| #define ADDA6_ULCF_CFG_20_19_1_SFT 0 |
| #define ADDA6_ULCF_CFG_20_19_1_MASK 0xff |
| #define ADDA6_ULCF_CFG_20_19_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_20_19_0 */ |
| #define ADDA6_ULCF_CFG_20_19_0_SFT 0 |
| #define ADDA6_ULCF_CFG_20_19_0_MASK 0xff |
| #define ADDA6_ULCF_CFG_20_19_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_22_21_3 */ |
| #define ADDA6_ULCF_CFG_22_21_3_SFT 0 |
| #define ADDA6_ULCF_CFG_22_21_3_MASK 0xff |
| #define ADDA6_ULCF_CFG_22_21_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_22_21_2 */ |
| #define ADDA6_ULCF_CFG_22_21_2_SFT 0 |
| #define ADDA6_ULCF_CFG_22_21_2_MASK 0xff |
| #define ADDA6_ULCF_CFG_22_21_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_22_21_1 */ |
| #define ADDA6_ULCF_CFG_22_21_1_SFT 0 |
| #define ADDA6_ULCF_CFG_22_21_1_MASK 0xff |
| #define ADDA6_ULCF_CFG_22_21_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_22_21_0 */ |
| #define ADDA6_ULCF_CFG_22_21_0_SFT 0 |
| #define ADDA6_ULCF_CFG_22_21_0_MASK 0xff |
| #define ADDA6_ULCF_CFG_22_21_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_24_23_3 */ |
| #define ADDA6_ULCF_CFG_24_23_3_SFT 0 |
| #define ADDA6_ULCF_CFG_24_23_3_MASK 0xff |
| #define ADDA6_ULCF_CFG_24_23_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_24_23_2 */ |
| #define ADDA6_ULCF_CFG_24_23_2_SFT 0 |
| #define ADDA6_ULCF_CFG_24_23_2_MASK 0xff |
| #define ADDA6_ULCF_CFG_24_23_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_24_23_1 */ |
| #define ADDA6_ULCF_CFG_24_23_1_SFT 0 |
| #define ADDA6_ULCF_CFG_24_23_1_MASK 0xff |
| #define ADDA6_ULCF_CFG_24_23_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_24_23_0 */ |
| #define ADDA6_ULCF_CFG_24_23_0_SFT 0 |
| #define ADDA6_ULCF_CFG_24_23_0_MASK 0xff |
| #define ADDA6_ULCF_CFG_24_23_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_26_25_3 */ |
| #define ADDA6_ULCF_CFG_26_25_3_SFT 0 |
| #define ADDA6_ULCF_CFG_26_25_3_MASK 0xff |
| #define ADDA6_ULCF_CFG_26_25_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_26_25_2 */ |
| #define ADDA6_ULCF_CFG_26_25_2_SFT 0 |
| #define ADDA6_ULCF_CFG_26_25_2_MASK 0xff |
| #define ADDA6_ULCF_CFG_26_25_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_26_25_1 */ |
| #define ADDA6_ULCF_CFG_26_25_1_SFT 0 |
| #define ADDA6_ULCF_CFG_26_25_1_MASK 0xff |
| #define ADDA6_ULCF_CFG_26_25_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_26_25_0 */ |
| #define ADDA6_ULCF_CFG_26_25_0_SFT 0 |
| #define ADDA6_ULCF_CFG_26_25_0_MASK 0xff |
| #define ADDA6_ULCF_CFG_26_25_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_28_27_3 */ |
| #define ADDA6_ULCF_CFG_28_27_3_SFT 0 |
| #define ADDA6_ULCF_CFG_28_27_3_MASK 0xff |
| #define ADDA6_ULCF_CFG_28_27_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_28_27_2 */ |
| #define ADDA6_ULCF_CFG_28_27_2_SFT 0 |
| #define ADDA6_ULCF_CFG_28_27_2_MASK 0xff |
| #define ADDA6_ULCF_CFG_28_27_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_28_27_1 */ |
| #define ADDA6_ULCF_CFG_28_27_1_SFT 0 |
| #define ADDA6_ULCF_CFG_28_27_1_MASK 0xff |
| #define ADDA6_ULCF_CFG_28_27_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_28_27_0 */ |
| #define ADDA6_ULCF_CFG_28_27_0_SFT 0 |
| #define ADDA6_ULCF_CFG_28_27_0_MASK 0xff |
| #define ADDA6_ULCF_CFG_28_27_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_30_29_3 */ |
| #define ADDA6_ULCF_CFG_30_29_3_SFT 0 |
| #define ADDA6_ULCF_CFG_30_29_3_MASK 0xff |
| #define ADDA6_ULCF_CFG_30_29_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_30_29_2 */ |
| #define ADDA6_ULCF_CFG_30_29_2_SFT 0 |
| #define ADDA6_ULCF_CFG_30_29_2_MASK 0xff |
| #define ADDA6_ULCF_CFG_30_29_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_30_29_1 */ |
| #define ADDA6_ULCF_CFG_30_29_1_SFT 0 |
| #define ADDA6_ULCF_CFG_30_29_1_MASK 0xff |
| #define ADDA6_ULCF_CFG_30_29_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_30_29_0 */ |
| #define ADDA6_ULCF_CFG_30_29_0_SFT 0 |
| #define ADDA6_ULCF_CFG_30_29_0_MASK 0xff |
| #define ADDA6_ULCF_CFG_30_29_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_32_31_3 */ |
| #define ADDA6_ULCF_CFG_32_31_3_SFT 0 |
| #define ADDA6_ULCF_CFG_32_31_3_MASK 0xff |
| #define ADDA6_ULCF_CFG_32_31_3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_32_31_2 */ |
| #define ADDA6_ULCF_CFG_32_31_2_SFT 0 |
| #define ADDA6_ULCF_CFG_32_31_2_MASK 0xff |
| #define ADDA6_ULCF_CFG_32_31_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_32_31_1 */ |
| #define ADDA6_ULCF_CFG_32_31_1_SFT 0 |
| #define ADDA6_ULCF_CFG_32_31_1_MASK 0xff |
| #define ADDA6_ULCF_CFG_32_31_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_ULCF_CFG_32_31_0 */ |
| #define ADDA6_ULCF_CFG_32_31_0_SFT 0 |
| #define ADDA6_ULCF_CFG_32_31_0_MASK 0xff |
| #define ADDA6_ULCF_CFG_32_31_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_UL_SRC_MON0_3 */ |
| #define ADDA6_UL_SRC_ON_MON_SFT 7 |
| #define ADDA6_UL_SRC_ON_MON_MASK 0x1 |
| #define ADDA6_UL_SRC_ON_MON_MASK_SFT (0x1 << 7) |
| #define ADDA6_UL_SDM_3_LEVEL_MON_SFT 6 |
| #define ADDA6_UL_SDM_3_LEVEL_MON_MASK 0x1 |
| #define ADDA6_UL_SDM_3_LEVEL_MON_MASK_SFT (0x1 << 6) |
| #define ADDA6_UL_LOOP_BACK_MODE_MON_SFT 5 |
| #define ADDA6_UL_LOOP_BACK_MODE_MON_MASK 0x1 |
| #define ADDA6_UL_LOOP_BACK_MODE_MON_MASK_SFT (0x1 << 5) |
| #define ADDA6_DATA_COMB_IN_CH1_SFT 0 |
| #define ADDA6_DATA_COMB_IN_CH1_MASK 0x1f |
| #define ADDA6_DATA_COMB_IN_CH1_MASK_SFT (0x1f << 0) |
| |
| /* AFE_ADDA6_UL_SRC_MON0_2 */ |
| #define ADDA6_DATA_COMB_OUT_CH1_2_SFT 0 |
| #define ADDA6_DATA_COMB_OUT_CH1_2_MASK 0xff |
| #define ADDA6_DATA_COMB_OUT_CH1_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_UL_SRC_MON0_1 */ |
| #define ADDA6_DATA_COMB_OUT_CH1_1_SFT 0 |
| #define ADDA6_DATA_COMB_OUT_CH1_1_MASK 0xff |
| #define ADDA6_DATA_COMB_OUT_CH1_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_UL_SRC_MON0_0 */ |
| #define ADDA6_DATA_COMB_OUT_CH1_0_SFT 0 |
| #define ADDA6_DATA_COMB_OUT_CH1_0_MASK 0xff |
| #define ADDA6_DATA_COMB_OUT_CH1_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_UL_SRC_MON1_3 */ |
| #define ADDA6_UL_VOICE_MODE_CTL_SFT 5 |
| #define ADDA6_UL_VOICE_MODE_CTL_MASK 0x7 |
| #define ADDA6_UL_VOICE_MODE_CTL_MASK_SFT (0x7 << 5) |
| #define ADDA6_DATA_COMB_IN_CH2_SFT 0 |
| #define ADDA6_DATA_COMB_IN_CH2_MASK 0x1f |
| #define ADDA6_DATA_COMB_IN_CH2_MASK_SFT (0x1f << 0) |
| |
| /* AFE_ADDA6_UL_SRC_MON1_2 */ |
| #define ADDA6_DATA_COMB_OUT_CH2_2_SFT 0 |
| #define ADDA6_DATA_COMB_OUT_CH2_2_MASK 0xff |
| #define ADDA6_DATA_COMB_OUT_CH2_2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_UL_SRC_MON1_1 */ |
| #define ADDA6_DATA_COMB_OUT_CH2_1_SFT 0 |
| #define ADDA6_DATA_COMB_OUT_CH2_1_MASK 0xff |
| #define ADDA6_DATA_COMB_OUT_CH2_1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_UL_SRC_MON1_0 */ |
| #define ADDA6_DATA_COMB_OUT_CH2_0_SFT 0 |
| #define ADDA6_DATA_COMB_OUT_CH2_0_MASK 0xff |
| #define ADDA6_DATA_COMB_OUT_CH2_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_SRC_DEBUG_1 */ |
| #define ADDA6_UL_SLT_CNT_FLAG_RESET_CTL_SFT 3 |
| #define ADDA6_UL_SLT_CNT_FLAG_RESET_CTL_MASK 0x1 |
| #define ADDA6_UL_SLT_CNT_FLAG_RESET_CTL_MASK_SFT (0x1 << 3) |
| #define ADDA6_SLT_CNT_THD_CTL_1_SFT 0 |
| #define ADDA6_SLT_CNT_THD_CTL_1_MASK 0x7 |
| #define ADDA6_SLT_CNT_THD_CTL_1_MASK_SFT (0x7 << 0) |
| |
| /* AFE_ADDA6_SRC_DEBUG_0 */ |
| #define ADDA6_SLT_CNT_THD_CTL_0_SFT 0 |
| #define ADDA6_SLT_CNT_THD_CTL_0_MASK 0xff |
| #define ADDA6_SLT_CNT_THD_CTL_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_SRC_DEBUG_MON0_1 */ |
| #define ADDA6_SLT_CNT_FLAG_CTL_SFT 4 |
| #define ADDA6_SLT_CNT_FLAG_CTL_MASK 0x1 |
| #define ADDA6_SLT_CNT_FLAG_CTL_MASK_SFT (0x1 << 4) |
| #define ADDA6_SLT_COUNTER_CTL_1_SFT 0 |
| #define ADDA6_SLT_COUNTER_CTL_1_MASK 0xf |
| #define ADDA6_SLT_COUNTER_CTL_1_MASK_SFT (0xf << 0) |
| |
| /* AFE_ADDA6_SRC_DEBUG_MON0_0 */ |
| #define ADDA6_SLT_COUNTER_CTL_0_SFT 0 |
| #define ADDA6_SLT_COUNTER_CTL_0_MASK 0xff |
| #define ADDA6_SLT_COUNTER_CTL_0_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_6TH_DSN_ID */ |
| #define AUDIO_DIG_6TH_ANA_ID_SFT 0 |
| #define AUDIO_DIG_6TH_ANA_ID_MASK 0xff |
| #define AUDIO_DIG_6TH_ANA_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_6TH_DSN_ID_H */ |
| #define AUDIO_DIG_6TH_DIG_ID_SFT 0 |
| #define AUDIO_DIG_6TH_DIG_ID_MASK 0xff |
| #define AUDIO_DIG_6TH_DIG_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_6TH_DSN_REV0 */ |
| #define AUDIO_DIG_6TH_ANA_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_6TH_ANA_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_6TH_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_6TH_ANA_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_6TH_ANA_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_6TH_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_6TH_DSN_REV0_H */ |
| #define AUDIO_DIG_6TH_DIG_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_6TH_DIG_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_6TH_DIG_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_6TH_DIG_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_6TH_DIG_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_6TH_DIG_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_6TH_DSN_DBI */ |
| #define AUDIO_DIG_6TH_DSN_CBS_SFT 0 |
| #define AUDIO_DIG_6TH_DSN_CBS_MASK 0x3 |
| #define AUDIO_DIG_6TH_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDIO_DIG_6TH_DSN_BIX_SFT 2 |
| #define AUDIO_DIG_6TH_DSN_BIX_MASK 0x3 |
| #define AUDIO_DIG_6TH_DSN_BIX_MASK_SFT (0x3 << 2) |
| |
| /* AUDIO_DIG_6TH_DSN_DBI_H */ |
| #define AUDIO_DIG_6_ESP_SFT 0 |
| #define AUDIO_DIG_6_ESP_MASK 0xff |
| #define AUDIO_DIG_6_ESP_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_6TH_DSN_DXI */ |
| #define AUDIO_DIG_6TH_DSN_FPI_SFT 0 |
| #define AUDIO_DIG_6TH_DSN_FPI_MASK 0xff |
| #define AUDIO_DIG_6TH_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_NLE_CF_H */ |
| #define NLE_RCH_HPGAIN_SEL_SFT 2 |
| #define NLE_RCH_HPGAIN_SEL_MASK 0x1 |
| #define NLE_RCH_HPGAIN_SEL_MASK_SFT (0x1 << 2) |
| #define NLE_RCH_CH_SEL_SFT 1 |
| #define NLE_RCH_CH_SEL_MASK 0x1 |
| #define NLE_RCH_CH_SEL_MASK_SFT (0x1 << 1) |
| #define NLE_RCH_ON_SFT 0 |
| #define NLE_RCH_ON_MASK 0x1 |
| #define NLE_RCH_ON_MASK_SFT (0x1 << 0) |
| |
| /* AFE_DL_NLE_CFG_L */ |
| #define NLE_LCH_HPGAIN_SEL_SFT 2 |
| #define NLE_LCH_HPGAIN_SEL_MASK 0x1 |
| #define NLE_LCH_HPGAIN_SEL_MASK_SFT (0x1 << 2) |
| #define NLE_LCH_CH_SEL_SFT 1 |
| #define NLE_LCH_CH_SEL_MASK 0x1 |
| #define NLE_LCH_CH_SEL_MASK_SFT (0x1 << 1) |
| #define NLE_LCH_ON_SFT 0 |
| #define NLE_LCH_ON_MASK 0x1 |
| #define NLE_LCH_ON_MASK_SFT (0x1 << 0) |
| |
| /* AFE_DL_NLE_MON_H */ |
| #define NLE_MONITOR_H_SFT 0 |
| #define NLE_MONITOR_H_MASK 0x7f |
| #define NLE_MONITOR_H_MASK_SFT (0x7f << 0) |
| |
| /* AFE_DL_NLE_MON_L */ |
| #define NLE_MONITOR_L_SFT 0 |
| #define NLE_MONITOR_L_MASK 0x7f |
| #define NLE_MONITOR_L_MASK_SFT (0x7f << 0) |
| |
| /* AFUNC_AUD_CON0_H */ |
| #define CCI_AUD_ANACK_SEL_SFT 7 |
| #define CCI_AUD_ANACK_SEL_MASK 0x1 |
| #define CCI_AUD_ANACK_SEL_MASK_SFT (0x1 << 7) |
| #define CCI_AUDIO_FIFO_WPTR_SFT 4 |
| #define CCI_AUDIO_FIFO_WPTR_MASK 0x7 |
| #define CCI_AUDIO_FIFO_WPTR_MASK_SFT (0x7 << 4) |
| #define CCI_SCRAMBLER_CG_EN_SFT 3 |
| #define CCI_SCRAMBLER_CG_EN_MASK 0x1 |
| #define CCI_SCRAMBLER_CG_EN_MASK_SFT (0x1 << 3) |
| #define CCI_LCH_INV_SFT 2 |
| #define CCI_LCH_INV_MASK 0x1 |
| #define CCI_LCH_INV_MASK_SFT (0x1 << 2) |
| #define CCI_RAND_EN_SFT 1 |
| #define CCI_RAND_EN_MASK 0x1 |
| #define CCI_RAND_EN_MASK_SFT (0x1 << 1) |
| #define CCI_SPLT_SCRMB_CLK_ON_SFT 0 |
| #define CCI_SPLT_SCRMB_CLK_ON_MASK 0x1 |
| #define CCI_SPLT_SCRMB_CLK_ON_MASK_SFT (0x1 << 0) |
| |
| /* AFUNC_AUD_CON0_L */ |
| #define CCI_SPLT_SCRMB_ON_SFT 7 |
| #define CCI_SPLT_SCRMB_ON_MASK 0x1 |
| #define CCI_SPLT_SCRMB_ON_MASK_SFT (0x1 << 7) |
| #define CCI_AUD_IDAC_TEST_EN_SFT 6 |
| #define CCI_AUD_IDAC_TEST_EN_MASK 0x1 |
| #define CCI_AUD_IDAC_TEST_EN_MASK_SFT (0x1 << 6) |
| #define CCI_ZERO_PAD_DISABLE_SFT 5 |
| #define CCI_ZERO_PAD_DISABLE_MASK 0x1 |
| #define CCI_ZERO_PAD_DISABLE_MASK_SFT (0x1 << 5) |
| #define CCI_AUD_SPLIT_TEST_EN_SFT 4 |
| #define CCI_AUD_SPLIT_TEST_EN_MASK 0x1 |
| #define CCI_AUD_SPLIT_TEST_EN_MASK_SFT (0x1 << 4) |
| #define CCI_AUD_SDM_MUTEL_SFT 3 |
| #define CCI_AUD_SDM_MUTEL_MASK 0x1 |
| #define CCI_AUD_SDM_MUTEL_MASK_SFT (0x1 << 3) |
| #define CCI_AUD_SDM_MUTER_SFT 2 |
| #define CCI_AUD_SDM_MUTER_MASK 0x1 |
| #define CCI_AUD_SDM_MUTER_MASK_SFT (0x1 << 2) |
| #define PWM_SHIFT_POINTER_EN_SFT 1 |
| #define PWM_SHIFT_POINTER_EN_MASK 0x1 |
| #define PWM_SHIFT_POINTER_EN_MASK_SFT (0x1 << 1) |
| #define ENABLE_PWM_SFT 0 |
| #define ENABLE_PWM_MASK 0x1 |
| #define ENABLE_PWM_MASK_SFT (0x1 << 0) |
| |
| /* AFUNC_AUD_CON1_H */ |
| #define AUD_SDM_TEST_L_SFT 0 |
| #define AUD_SDM_TEST_L_MASK 0xff |
| #define AUD_SDM_TEST_L_MASK_SFT (0xff << 0) |
| |
| /* AFUNC_AUD_CON1_L */ |
| #define AUD_SDM_TEST_R_SFT 0 |
| #define AUD_SDM_TEST_R_MASK 0xff |
| #define AUD_SDM_TEST_R_MASK_SFT (0xff << 0) |
| |
| /* AFUNC_AUD_CON2_H */ |
| #define SCRAMBLER_EN_HIFI_SFT 4 |
| #define SCRAMBLER_EN_HIFI_MASK 0x7 |
| #define SCRAMBLER_EN_HIFI_MASK_SFT (0x7 << 4) |
| #define MOD_SHIFT_MODE_SFT 2 |
| #define MOD_SHIFT_MODE_MASK 0x1 |
| #define MOD_SHIFT_MODE_MASK_SFT (0x1 << 2) |
| #define HIFI_3P25M_CG_MODE_SFT 1 |
| #define HIFI_3P25M_CG_MODE_MASK 0x1 |
| #define HIFI_3P25M_CG_MODE_MASK_SFT (0x1 << 1) |
| #define R_SPLITTER_TRUNC_RND_SFT 0 |
| #define R_SPLITTER_TRUNC_RND_MASK 0x1 |
| #define R_SPLITTER_TRUNC_RND_MASK_SFT (0x1 << 0) |
| |
| /* AFUNC_AUD_CON2_L */ |
| #define CCI_AUD_DAC_ANA_MUTE_SFT 7 |
| #define CCI_AUD_DAC_ANA_MUTE_MASK 0x1 |
| #define CCI_AUD_DAC_ANA_MUTE_MASK_SFT (0x1 << 7) |
| #define CCI_AUD_DAC_ANA_RSTB_SEL_SFT 6 |
| #define CCI_AUD_DAC_ANA_RSTB_SEL_MASK 0x1 |
| #define CCI_AUD_DAC_ANA_RSTB_SEL_MASK_SFT (0x1 << 6) |
| #define CCI_AUDIO_FIFO_CLKIN_INV_SFT 4 |
| #define CCI_AUDIO_FIFO_CLKIN_INV_MASK 0x1 |
| #define CCI_AUDIO_FIFO_CLKIN_INV_MASK_SFT (0x1 << 4) |
| #define CCI_AUDIO_FIFO_ENABLE_SFT 3 |
| #define CCI_AUDIO_FIFO_ENABLE_MASK 0x1 |
| #define CCI_AUDIO_FIFO_ENABLE_MASK_SFT (0x1 << 3) |
| #define CCI_ACD_MODE_SFT 2 |
| #define CCI_ACD_MODE_MASK 0x1 |
| #define CCI_ACD_MODE_MASK_SFT (0x1 << 2) |
| #define CCI_AFIFO_CLK_PWDB_SFT 1 |
| #define CCI_AFIFO_CLK_PWDB_MASK 0x1 |
| #define CCI_AFIFO_CLK_PWDB_MASK_SFT (0x1 << 1) |
| #define CCI_ACD_FUNC_RSTB_SFT 0 |
| #define CCI_ACD_FUNC_RSTB_MASK 0x1 |
| #define CCI_ACD_FUNC_RSTB_MASK_SFT (0x1 << 0) |
| |
| /* AFUNC_AUD_CON3_H */ |
| #define SDM_ANA6P5M_TESTCK_SEL_SFT 7 |
| #define SDM_ANA6P5M_TESTCK_SEL_MASK 0x1 |
| #define SDM_ANA6P5M_TESTCK_SEL_MASK_SFT (0x1 << 7) |
| #define SDM_ANA6P5M_TESTCK_SRC_SEL_SFT 4 |
| #define SDM_ANA6P5M_TESTCK_SRC_SEL_MASK 0x7 |
| #define SDM_ANA6P5M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 4) |
| #define SDM_TESTCK_SRC_SEL_SFT 0 |
| #define SDM_TESTCK_SRC_SEL_MASK 0x7 |
| #define SDM_TESTCK_SRC_SEL_MASK_SFT (0x7 << 0) |
| |
| /* AFUNC_AUD_CON4_H */ |
| #define UL_FIFO_WCLK_INV_SFT 0 |
| #define UL_FIFO_WCLK_INV_MASK 0x1 |
| #define UL_FIFO_WCLK_INV_MASK_SFT (0x1 << 0) |
| |
| /* AFUNC_AUD_CON4_L */ |
| #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_SFT 3 |
| #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK 0x1 |
| #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK_SFT (0x1 << 3) |
| #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_SFT 0 |
| #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK 0x7 |
| #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 0) |
| |
| /* AFUNC_AUD_CON5_H */ |
| #define R_AUD_DAC_POS_LARGE_MONO_SFT 0 |
| #define R_AUD_DAC_POS_LARGE_MONO_MASK 0xff |
| #define R_AUD_DAC_POS_LARGE_MONO_MASK_SFT (0xff << 0) |
| |
| /* AFUNC_AUD_CON5_L */ |
| #define R_AUD_DAC_NEG_LARGE_MONO_SFT 0 |
| #define R_AUD_DAC_NEG_LARGE_MONO_MASK 0xff |
| #define R_AUD_DAC_NEG_LARGE_MONO_MASK_SFT (0xff << 0) |
| |
| /* AFUNC_AUD_CON6_H */ |
| #define R_AUD_DAC_POS_SMALL_MONO_SFT 4 |
| #define R_AUD_DAC_POS_SMALL_MONO_MASK 0xf |
| #define R_AUD_DAC_POS_SMALL_MONO_MASK_SFT (0xf << 4) |
| #define R_AUD_DAC_NEG_SMALL_MONO_SFT 0 |
| #define R_AUD_DAC_NEG_SMALL_MONO_MASK 0xf |
| #define R_AUD_DAC_NEG_SMALL_MONO_MASK_SFT (0xf << 0) |
| |
| /* AFUNC_AUD_CON6_L */ |
| #define R_AUD_DAC_POS_TINY_MONO_SFT 6 |
| #define R_AUD_DAC_POS_TINY_MONO_MASK 0x3 |
| #define R_AUD_DAC_POS_TINY_MONO_MASK_SFT (0x3 << 6) |
| #define R_AUD_DAC_NEG_TINY_MONO_SFT 4 |
| #define R_AUD_DAC_NEG_TINY_MONO_MASK 0x3 |
| #define R_AUD_DAC_NEG_TINY_MONO_MASK_SFT (0x3 << 4) |
| #define R_AUD_DAC_MONO_SEL_SFT 3 |
| #define R_AUD_DAC_MONO_SEL_MASK 0x1 |
| #define R_AUD_DAC_MONO_SEL_MASK_SFT (0x1 << 3) |
| #define R_AUD_DAC_2ND_MONO_SEL_SFT 2 |
| #define R_AUD_DAC_2ND_MONO_SEL_MASK 0x1 |
| #define R_AUD_DAC_2ND_MONO_SEL_MASK_SFT (0x1 << 2) |
| #define R_AUD_DAC_3TH_SEL_SFT 1 |
| #define R_AUD_DAC_3TH_SEL_MASK 0x1 |
| #define R_AUD_DAC_3TH_SEL_MASK_SFT (0x1 << 1) |
| #define R_AUD_DAC_SW_RSTB_SFT 0 |
| #define R_AUD_DAC_SW_RSTB_MASK 0x1 |
| #define R_AUD_DAC_SW_RSTB_MASK_SFT (0x1 << 0) |
| |
| /* AFUNC_AUD_CON7_H */ |
| #define UL2_FIFO_WCLK_INV_SFT 0 |
| #define UL2_FIFO_WCLK_INV_MASK 0x1 |
| #define UL2_FIFO_WCLK_INV_MASK_SFT (0x1 << 0) |
| |
| /* AFUNC_AUD_CON7_L */ |
| #define UL2_FIFO_WCLK_6P5M_TESTCK_SEL_SFT 3 |
| #define UL2_FIFO_WCLK_6P5M_TESTCK_SEL_MASK 0x1 |
| #define UL2_FIFO_WCLK_6P5M_TESTCK_SEL_MASK_SFT (0x1 << 3) |
| #define UL2_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_SFT 0 |
| #define UL2_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK 0x7 |
| #define UL2_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 0) |
| |
| /* AFUNC_AUD_CON8_H */ |
| #define SPLITTER2_DITHER_EN_SFT 1 |
| #define SPLITTER2_DITHER_EN_MASK 0x1 |
| #define SPLITTER2_DITHER_EN_MASK_SFT (0x1 << 1) |
| #define SPLITTER1_DITHER_EN_SFT 0 |
| #define SPLITTER1_DITHER_EN_MASK 0x1 |
| #define SPLITTER1_DITHER_EN_MASK_SFT (0x1 << 0) |
| |
| /* AFUNC_AUD_CON8_L */ |
| #define SPLITTER2_DITHER_GAIN_SFT 4 |
| #define SPLITTER2_DITHER_GAIN_MASK 0xf |
| #define SPLITTER2_DITHER_GAIN_MASK_SFT (0xf << 4) |
| #define SPLITTER1_DITHER_GAIN_SFT 0 |
| #define SPLITTER1_DITHER_GAIN_MASK 0xf |
| #define SPLITTER1_DITHER_GAIN_MASK_SFT (0xf << 0) |
| |
| /* AFUNC_AUD_CON9_H */ |
| #define CCI_AUD_ANACK_SEL_2ND_SFT 7 |
| #define CCI_AUD_ANACK_SEL_2ND_MASK 0x1 |
| #define CCI_AUD_ANACK_SEL_2ND_MASK_SFT (0x1 << 7) |
| #define CCI_AUDIO_FIFO_WPTR_2ND_SFT 4 |
| #define CCI_AUDIO_FIFO_WPTR_2ND_MASK 0x7 |
| #define CCI_AUDIO_FIFO_WPTR_2ND_MASK_SFT (0x7 << 4) |
| #define CCI_SCRAMBLER_CG_EN_2ND_SFT 3 |
| #define CCI_SCRAMBLER_CG_EN_2ND_MASK 0x1 |
| #define CCI_SCRAMBLER_CG_EN_2ND_MASK_SFT (0x1 << 3) |
| #define CCI_LCH_INV_2ND_SFT 2 |
| #define CCI_LCH_INV_2ND_MASK 0x1 |
| #define CCI_LCH_INV_2ND_MASK_SFT (0x1 << 2) |
| #define CCI_RAND_EN_2ND_SFT 1 |
| #define CCI_RAND_EN_2ND_MASK 0x1 |
| #define CCI_RAND_EN_2ND_MASK_SFT (0x1 << 1) |
| #define CCI_SPLT_SCRMB_CLK_ON_2ND_SFT 0 |
| #define CCI_SPLT_SCRMB_CLK_ON_2ND_MASK 0x1 |
| #define CCI_SPLT_SCRMB_CLK_ON_2ND_MASK_SFT (0x1 << 0) |
| |
| /* AFUNC_AUD_CON9_L */ |
| #define CCI_SPLT_SCRMB_ON_2ND_SFT 7 |
| #define CCI_SPLT_SCRMB_ON_2ND_MASK 0x1 |
| #define CCI_SPLT_SCRMB_ON_2ND_MASK_SFT (0x1 << 7) |
| #define CCI_AUD_IDAC_TEST_EN_2ND_SFT 6 |
| #define CCI_AUD_IDAC_TEST_EN_2ND_MASK 0x1 |
| #define CCI_AUD_IDAC_TEST_EN_2ND_MASK_SFT (0x1 << 6) |
| #define CCI_ZERO_PAD_DISABLE_2ND_SFT 5 |
| #define CCI_ZERO_PAD_DISABLE_2ND_MASK 0x1 |
| #define CCI_ZERO_PAD_DISABLE_2ND_MASK_SFT (0x1 << 5) |
| #define CCI_AUD_SPLIT_TEST_EN_2ND_SFT 4 |
| #define CCI_AUD_SPLIT_TEST_EN_2ND_MASK 0x1 |
| #define CCI_AUD_SPLIT_TEST_EN_2ND_MASK_SFT (0x1 << 4) |
| #define CCI_AUD_SDM_MUTEL_2ND_SFT 3 |
| #define CCI_AUD_SDM_MUTEL_2ND_MASK 0x1 |
| #define CCI_AUD_SDM_MUTEL_2ND_MASK_SFT (0x1 << 3) |
| #define CCI_AUD_SDM_MUTER_2ND_SFT 2 |
| #define CCI_AUD_SDM_MUTER_2ND_MASK 0x1 |
| #define CCI_AUD_SDM_MUTER_2ND_MASK_SFT (0x1 << 2) |
| #define CCI_AUD_SDM_7BIT_SEL_2ND_SFT 1 |
| #define CCI_AUD_SDM_7BIT_SEL_2ND_MASK 0x1 |
| #define CCI_AUD_SDM_7BIT_SEL_2ND_MASK_SFT (0x1 << 1) |
| #define CCI_SCRAMBLER_EN_2ND_SFT 0 |
| #define CCI_SCRAMBLER_EN_2ND_MASK 0x1 |
| #define CCI_SCRAMBLER_EN_2ND_MASK_SFT (0x1 << 0) |
| |
| /* AFUNC_AUD_CON10_H */ |
| #define AUD_SDM_TEST_L_2ND_SFT 0 |
| #define AUD_SDM_TEST_L_2ND_MASK 0xff |
| #define AUD_SDM_TEST_L_2ND_MASK_SFT (0xff << 0) |
| |
| /* AFUNC_AUD_CON10_L */ |
| #define AUD_SDM_TEST_R_2ND_SFT 0 |
| #define AUD_SDM_TEST_R_2ND_MASK 0xff |
| #define AUD_SDM_TEST_R_2ND_MASK_SFT (0xff << 0) |
| |
| /* AFUNC_AUD_CON11_H */ |
| #define R_SPLITTER_TRUNC_RND_2ND_SFT 0 |
| #define R_SPLITTER_TRUNC_RND_2ND_MASK 0x1 |
| #define R_SPLITTER_TRUNC_RND_2ND_MASK_SFT (0x1 << 0) |
| |
| /* AFUNC_AUD_CON11_L */ |
| #define CCI_AUD_DAC_ANA_MUTE_2ND_SFT 7 |
| #define CCI_AUD_DAC_ANA_MUTE_2ND_MASK 0x1 |
| #define CCI_AUD_DAC_ANA_MUTE_2ND_MASK_SFT (0x1 << 7) |
| #define CCI_AUD_DAC_ANA_RSTB_SEL_2ND_SFT 6 |
| #define CCI_AUD_DAC_ANA_RSTB_SEL_2ND_MASK 0x1 |
| #define CCI_AUD_DAC_ANA_RSTB_SEL_2ND_MASK_SFT (0x1 << 6) |
| #define CCI_AUDIO_FIFO_CLKIN_INV_2ND_SFT 4 |
| #define CCI_AUDIO_FIFO_CLKIN_INV_2ND_MASK 0x1 |
| #define CCI_AUDIO_FIFO_CLKIN_INV_2ND_MASK_SFT (0x1 << 4) |
| #define CCI_AUDIO_FIFO_ENABLE_2ND_SFT 3 |
| #define CCI_AUDIO_FIFO_ENABLE_2ND_MASK 0x1 |
| #define CCI_AUDIO_FIFO_ENABLE_2ND_MASK_SFT (0x1 << 3) |
| #define CCI_ACD_MODE_2ND_SFT 2 |
| #define CCI_ACD_MODE_2ND_MASK 0x1 |
| #define CCI_ACD_MODE_2ND_MASK_SFT (0x1 << 2) |
| #define CCI_AFIFO_CLK_PWDB_2ND_SFT 1 |
| #define CCI_AFIFO_CLK_PWDB_2ND_MASK 0x1 |
| #define CCI_AFIFO_CLK_PWDB_2ND_MASK_SFT (0x1 << 1) |
| #define CCI_ACD_FUNC_RSTB_2ND_SFT 0 |
| #define CCI_ACD_FUNC_RSTB_2ND_MASK 0x1 |
| #define CCI_ACD_FUNC_RSTB_2ND_MASK_SFT (0x1 << 0) |
| |
| /* AFUNC_AUD_CON12_H */ |
| #define DA_AUDHPRNEGR_EN_VAUDP18_SFT 7 |
| #define DA_AUDHPRNEGR_EN_VAUDP18_MASK 0x1 |
| #define DA_AUDHPRNEGR_EN_VAUDP18_MASK_SFT (0x1 << 7) |
| #define DA_AUDHPLNEGR_EN_VAUDP18_SFT 6 |
| #define DA_AUDHPLNEGR_EN_VAUDP18_MASK 0x1 |
| #define DA_AUDHPLNEGR_EN_VAUDP18_MASK_SFT (0x1 << 6) |
| #define DA_HPRCMFBSWST_EN_VAUDP18_SFT 5 |
| #define DA_HPRCMFBSWST_EN_VAUDP18_MASK 0x1 |
| #define DA_HPRCMFBSWST_EN_VAUDP18_MASK_SFT (0x1 << 5) |
| #define DA_HPLCMFBSWST_EN_VAUDP18_SFT 4 |
| #define DA_HPLCMFBSWST_EN_VAUDP18_MASK 0x1 |
| #define DA_HPLCMFBSWST_EN_VAUDP18_MASK_SFT (0x1 << 4) |
| #define SPLITTER2_DITHER_EN_2ND_SFT 1 |
| #define SPLITTER2_DITHER_EN_2ND_MASK 0x1 |
| #define SPLITTER2_DITHER_EN_2ND_MASK_SFT (0x1 << 1) |
| #define SPLITTER1_DITHER_EN_2ND_SFT 0 |
| #define SPLITTER1_DITHER_EN_2ND_MASK 0x1 |
| #define SPLITTER1_DITHER_EN_2ND_MASK_SFT (0x1 << 0) |
| |
| /* AFUNC_AUD_CON12_L */ |
| #define SPLITTER2_DITHER_GAIN_2ND_SFT 4 |
| #define SPLITTER2_DITHER_GAIN_2ND_MASK 0xf |
| #define SPLITTER2_DITHER_GAIN_2ND_MASK_SFT (0xf << 4) |
| #define SPLITTER1_DITHER_GAIN_2ND_SFT 0 |
| #define SPLITTER1_DITHER_GAIN_2ND_MASK 0xf |
| #define SPLITTER1_DITHER_GAIN_2ND_MASK_SFT (0xf << 0) |
| |
| /* AFUNC_AUD_MON0_H */ |
| #define AUD_SCR_OUT_L_SFT 0 |
| #define AUD_SCR_OUT_L_MASK 0xff |
| #define AUD_SCR_OUT_L_MASK_SFT (0xff << 0) |
| |
| /* AFUNC_AUD_MON0_L */ |
| #define AUD_SCR_OUT_R_SFT 0 |
| #define AUD_SCR_OUT_R_MASK 0xff |
| #define AUD_SCR_OUT_R_MASK_SFT (0xff << 0) |
| |
| /* AFUNC_AUD_MON1_H */ |
| #define AUD_SCR_OUT_L_2ND_SFT 0 |
| #define AUD_SCR_OUT_L_2ND_MASK 0xff |
| #define AUD_SCR_OUT_L_2ND_MASK_SFT (0xff << 0) |
| |
| /* AFUNC_AUD_MON1_L */ |
| #define AUD_SCR_OUT_R_2ND_SFT 0 |
| #define AUD_SCR_OUT_R_2ND_MASK 0xff |
| #define AUD_SCR_OUT_R_2ND_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADC_ASYNC_FIFO_CFG */ |
| #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_SFT 5 |
| #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK 0x1 |
| #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 5) |
| #define RG_UL_ASYNC_FIFO_SOFT_RST_SFT 4 |
| #define RG_UL_ASYNC_FIFO_SOFT_RST_MASK 0x1 |
| #define RG_UL_ASYNC_FIFO_SOFT_RST_MASK_SFT (0x1 << 4) |
| #define RG_UL2_ASYNC_FIFO_SOFT_RST_EN_SFT 2 |
| #define RG_UL2_ASYNC_FIFO_SOFT_RST_EN_MASK 0x1 |
| #define RG_UL2_ASYNC_FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 2) |
| #define RG_UL2_ASYNC_FIFO_SOFT_RST_SFT 1 |
| #define RG_UL2_ASYNC_FIFO_SOFT_RST_MASK 0x1 |
| #define RG_UL2_ASYNC_FIFO_SOFT_RST_MASK_SFT (0x1 << 1) |
| #define RG_AMIC_UL2_ADC_CLK_SEL_SFT 0 |
| #define RG_AMIC_UL2_ADC_CLK_SEL_MASK 0x1 |
| #define RG_AMIC_UL2_ADC_CLK_SEL_MASK_SFT (0x1 << 0) |
| |
| /* AFE_AMIC_ARRAY_CFG */ |
| #define RG_AMIC_ADC0_SOURCE_SEL_SFT 6 |
| #define RG_AMIC_ADC0_SOURCE_SEL_MASK 0x3 |
| #define RG_AMIC_ADC0_SOURCE_SEL_MASK_SFT (0x3 << 6) |
| #define RG_AMIC_ADC1_SOURCE_SEL_SFT 4 |
| #define RG_AMIC_ADC1_SOURCE_SEL_MASK 0x3 |
| #define RG_AMIC_ADC1_SOURCE_SEL_MASK_SFT (0x3 << 4) |
| #define RG_AMIC_ADC2_SOURCE_SEL_SFT 2 |
| #define RG_AMIC_ADC2_SOURCE_SEL_MASK 0x3 |
| #define RG_AMIC_ADC2_SOURCE_SEL_MASK_SFT (0x3 << 2) |
| #define RG_AMIC_ADC3_SOURCE_SEL_SFT 0 |
| #define RG_AMIC_ADC3_SOURCE_SEL_MASK 0x3 |
| #define RG_AMIC_ADC3_SOURCE_SEL_MASK_SFT (0x3 << 0) |
| |
| /* AFUNC_AUD_CON13 */ |
| #define SDM_ANA26M_TESTCK_SEL_SFT 7 |
| #define SDM_ANA26M_TESTCK_SEL_MASK 0x1 |
| #define SDM_ANA26M_TESTCK_SEL_MASK_SFT (0x1 << 7) |
| #define SDM_ANA26M_TESTCK_SRC_SEL_SFT 4 |
| #define SDM_ANA26M_TESTCK_SRC_SEL_MASK 0x7 |
| #define SDM_ANA26M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 4) |
| #define CCI_AUD_ANA26MCK_SEL_SFT 0 |
| #define CCI_AUD_ANA26MCK_SEL_MASK 0x1 |
| #define CCI_AUD_ANA26MCK_SEL_MASK_SFT (0x1 << 0) |
| |
| /* AFUNC_AUD_CON14 */ |
| #define R_AUD_DAC_POS_LARGE_MONO_HIFI_SFT 4 |
| #define R_AUD_DAC_POS_LARGE_MONO_HIFI_MASK 0xf |
| #define R_AUD_DAC_POS_LARGE_MONO_HIFI_MASK_SFT (0xf << 4) |
| #define R_AUD_DAC_NEG_LARGE_MONO_HIFI_SFT 0 |
| #define R_AUD_DAC_NEG_LARGE_MONO_HIFI_MASK 0xf |
| #define R_AUD_DAC_NEG_LARGE_MONO_HIFI_MASK_SFT (0xf << 0) |
| |
| /* AFUNC_AUD_CON15_H */ |
| #define R_AUD_DAC_POS_SMALL_MONO_HIFI_H_SFT 0 |
| #define R_AUD_DAC_POS_SMALL_MONO_HIFI_H_MASK 0xff |
| #define R_AUD_DAC_POS_SMALL_MONO_HIFI_H_MASK_SFT (0xff << 0) |
| |
| /* AFUNC_AUD_CON15_L */ |
| #define R_AUD_DAC_POS_SMALL_MONO_HIFI_L_SFT 0 |
| #define R_AUD_DAC_POS_SMALL_MONO_HIFI_L_MASK 0xff |
| #define R_AUD_DAC_POS_SMALL_MONO_HIFI_L_MASK_SFT (0xff << 0) |
| |
| /* AFUNC_AUD_CON16_H */ |
| #define R_AUD_DAC_NEG_SMALL_MONO_HIFI_H_SFT 0 |
| #define R_AUD_DAC_NEG_SMALL_MONO_HIFI_H_MASK 0xff |
| #define R_AUD_DAC_NEG_SMALL_MONO_HIFI_H_MASK_SFT (0xff << 0) |
| |
| /* AFUNC_AUD_CON16_L */ |
| #define R_AUD_DAC_NEG_SMALL_MONO_HIFI_L_SFT 0 |
| #define R_AUD_DAC_NEG_SMALL_MONO_HIFI_L_MASK 0xff |
| #define R_AUD_DAC_NEG_SMALL_MONO_HIFI_L_MASK_SFT (0xff << 0) |
| |
| /* AFUNC_AUD_CON17_H */ |
| #define R_AUD_DAC_POS_TINY_MONO_HIFI_H_SFT 0 |
| #define R_AUD_DAC_POS_TINY_MONO_HIFI_H_MASK 0xff |
| #define R_AUD_DAC_POS_TINY_MONO_HIFI_H_MASK_SFT (0xff << 0) |
| |
| /* AFUNC_AUD_CON17_L */ |
| #define R_AUD_DAC_POS_TINY_MONO_HIFI_L_SFT 0 |
| #define R_AUD_DAC_POS_TINY_MONO_HIFI_L_MASK 0xff |
| #define R_AUD_DAC_POS_TINY_MONO_HIFI_L_MASK_SFT (0xff << 0) |
| |
| /* AFUNC_AUD_CON18_H */ |
| #define R_AUD_DAC_NEG_TINY_MONO_HIFI_H_SFT 0 |
| #define R_AUD_DAC_NEG_TINY_MONO_HIFI_H_MASK 0xff |
| #define R_AUD_DAC_NEG_TINY_MONO_HIFI_H_MASK_SFT (0xff << 0) |
| |
| /* AFUNC_AUD_CON18_L */ |
| #define R_AUD_DAC_NEG_TINY_MONO_HIFI_L_SFT 0 |
| #define R_AUD_DAC_NEG_TINY_MONO_HIFI_L_MASK 0xff |
| #define R_AUD_DAC_NEG_TINY_MONO_HIFI_L_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_7TH_DSN_ID */ |
| #define AUDIO_DIG_7TH_ANA_ID_SFT 0 |
| #define AUDIO_DIG_7TH_ANA_ID_MASK 0xff |
| #define AUDIO_DIG_7TH_ANA_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_7TH_DSN_ID_H */ |
| #define AUDIO_DIG_7TH_DIG_ID_SFT 0 |
| #define AUDIO_DIG_7TH_DIG_ID_MASK 0xff |
| #define AUDIO_DIG_7TH_DIG_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_7TH_DSN_REV0 */ |
| #define AUDIO_DIG_7TH_ANA_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_7TH_ANA_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_7TH_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_7TH_ANA_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_7TH_ANA_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_7TH_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_7TH_DSN_REV0_H */ |
| #define AUDIO_DIG_7TH_DIG_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_7TH_DIG_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_7TH_DIG_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_7TH_DIG_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_7TH_DIG_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_7TH_DIG_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_7TH_DSN_DBI */ |
| #define AUDIO_DIG_7TH_DSN_CBS_SFT 0 |
| #define AUDIO_DIG_7TH_DSN_CBS_MASK 0x3 |
| #define AUDIO_DIG_7TH_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDIO_DIG_7TH_DSN_BIX_SFT 2 |
| #define AUDIO_DIG_7TH_DSN_BIX_MASK 0x3 |
| #define AUDIO_DIG_7TH_DSN_BIX_MASK_SFT (0x3 << 2) |
| |
| /* AUDIO_DIG_7TH_DSN_DBI_H */ |
| #define AUDIO_DIG_7_ESP_SFT 0 |
| #define AUDIO_DIG_7_ESP_MASK 0xff |
| #define AUDIO_DIG_7_ESP_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_7TH_DSN_DXI */ |
| #define AUDIO_DIG_7TH_DSN_FPI_SFT 0 |
| #define AUDIO_DIG_7TH_DSN_FPI_MASK 0xff |
| #define AUDIO_DIG_7TH_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SRC_CON0_H */ |
| #define AFE_DL_INPUT_MODE_CTL_SFT 4 |
| #define AFE_DL_INPUT_MODE_CTL_MASK 0xf |
| #define AFE_DL_INPUT_MODE_CTL_MASK_SFT (0xf << 4) |
| #define AFE_DL_CH1_SATURATION_EN_CTL_SFT 3 |
| #define AFE_DL_CH1_SATURATION_EN_CTL_MASK 0x1 |
| #define AFE_DL_CH1_SATURATION_EN_CTL_MASK_SFT (0x1 << 3) |
| #define AFE_DL_CH2_SATURATION_EN_CTL_SFT 2 |
| #define AFE_DL_CH2_SATURATION_EN_CTL_MASK 0x1 |
| #define AFE_DL_CH2_SATURATION_EN_CTL_MASK_SFT (0x1 << 2) |
| #define AFE_DL_OUTPUT_SEL_CTL_SFT 0 |
| #define AFE_DL_OUTPUT_SEL_CTL_MASK 0x3 |
| #define AFE_DL_OUTPUT_SEL_CTL_MASK_SFT (0x3 << 0) |
| |
| /* AFE_ADDA_DL_SRC_CON0_M */ |
| #define AFE_DL_FADEIN_0START_EN_SFT 0 |
| #define AFE_DL_FADEIN_0START_EN_MASK 0x3 |
| #define AFE_DL_FADEIN_0START_EN_MASK_SFT (0x3 << 0) |
| |
| /* AFE_ADDA_DL_SRC_CON0_L */ |
| #define AFE_DL_DISABLE_HW_CG_CTL_SFT 7 |
| #define AFE_DL_DISABLE_HW_CG_CTL_MASK 0x1 |
| #define AFE_DL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 7) |
| #define AFE_DL_C_DATA_EN_SEL_CTL_PRE_SFT 6 |
| #define AFE_DL_C_DATA_EN_SEL_CTL_PRE_MASK 0x1 |
| #define AFE_DL_C_DATA_EN_SEL_CTL_PRE_MASK_SFT (0x1 << 6) |
| #define AFE_DL_MUTE_CH1_OFF_CTL_PRE_SFT 4 |
| #define AFE_DL_MUTE_CH1_OFF_CTL_PRE_MASK 0x1 |
| #define AFE_DL_MUTE_CH1_OFF_CTL_PRE_MASK_SFT (0x1 << 4) |
| #define AFE_DL_MUTE_CH2_OFF_CTL_PRE_SFT 3 |
| #define AFE_DL_MUTE_CH2_OFF_CTL_PRE_MASK 0x1 |
| #define AFE_DL_MUTE_CH2_OFF_CTL_PRE_MASK_SFT (0x1 << 3) |
| #define AFE_DL_ARAMPSP_CTL_PRE_SFT 1 |
| #define AFE_DL_ARAMPSP_CTL_PRE_MASK 0x3 |
| #define AFE_DL_ARAMPSP_CTL_PRE_MASK_SFT (0x3 << 1) |
| |
| /* AFE_ADDA_DL_SRC_CON0 */ |
| #define AFE_DL_LR_SWAP_SFT 7 |
| #define AFE_DL_LR_SWAP_MASK 0x1 |
| #define AFE_DL_LR_SWAP_MASK_SFT (0x1 << 7) |
| #define AFE_DL_VOICE_MODE_CTL_PRE_SFT 5 |
| #define AFE_DL_VOICE_MODE_CTL_PRE_MASK 0x1 |
| #define AFE_DL_VOICE_MODE_CTL_PRE_MASK_SFT (0x1 << 5) |
| #define AFE_DL_MUTE_CH1_ON_CTL_PRE_SFT 4 |
| #define AFE_DL_MUTE_CH1_ON_CTL_PRE_MASK 0x1 |
| #define AFE_DL_MUTE_CH1_ON_CTL_PRE_MASK_SFT (0x1 << 4) |
| #define AFE_DL_MUTE_CH2_ON_CTL_PRE_SFT 3 |
| #define AFE_DL_MUTE_CH2_ON_CTL_PRE_MASK 0x1 |
| #define AFE_DL_MUTE_CH2_ON_CTL_PRE_MASK_SFT (0x1 << 3) |
| #define AFE_DL_GAIN_ON_CTL_PRE_SFT 1 |
| #define AFE_DL_GAIN_ON_CTL_PRE_MASK 0x1 |
| #define AFE_DL_GAIN_ON_CTL_PRE_MASK_SFT (0x1 << 1) |
| #define AFE_DL_SRC_ON_TMP_CTL_PRE_SFT 0 |
| #define AFE_DL_SRC_ON_TMP_CTL_PRE_MASK 0x1 |
| #define AFE_DL_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0) |
| |
| /* AFE_ADDA_DL_SRC_CON1_H */ |
| #define AFE_DL_GAIN_CTL_PRE_H_SFT 0 |
| #define AFE_DL_GAIN_CTL_PRE_H_MASK 0xff |
| #define AFE_DL_GAIN_CTL_PRE_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SRC_CON1_M */ |
| #define AFE_DL_GAIN_CTL_PRE_SFT 0 |
| #define AFE_DL_GAIN_CTL_PRE_MASK 0xff |
| #define AFE_DL_GAIN_CTL_PRE_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SRC_CON1 */ |
| #define AFE_DL_GAIN_MODE_CTL_SFT 0 |
| #define AFE_DL_GAIN_MODE_CTL_MASK 0x1 |
| #define AFE_DL_GAIN_MODE_CTL_MASK_SFT (0x1 << 0) |
| |
| /* AFE_ADDA_DL_SRC_DEBUG_MON0_H */ |
| #define AFE_DL_SLT_CNT_FLAG_CTL_SFT 7 |
| #define AFE_DL_SLT_CNT_FLAG_CTL_MASK 0x1 |
| #define AFE_DL_SLT_CNT_FLAG_CTL_MASK_SFT (0x1 << 7) |
| #define AFE_DL_INI_SRAM_FINISH_CTL_SFT 4 |
| #define AFE_DL_INI_SRAM_FINISH_CTL_MASK 0x1 |
| #define AFE_DL_INI_SRAM_FINISH_CTL_MASK_SFT (0x1 << 4) |
| #define AFE_DL_SLT_COUNTER_CTL_H_SFT 0 |
| #define AFE_DL_SLT_COUNTER_CTL_H_MASK 0xf |
| #define AFE_DL_SLT_COUNTER_CTL_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_ADDA_DL_SRC_DEBUG_MON0 */ |
| #define AFE_DL_SLT_COUNTER_CTL_SFT 0 |
| #define AFE_DL_SLT_COUNTER_CTL_MASK 0xff |
| #define AFE_DL_SLT_COUNTER_CTL_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_PREDIS_CON0_H */ |
| #define AFE_DL_PREDIS_ON_CH1_CTL_SFT 7 |
| #define AFE_DL_PREDIS_ON_CH1_CTL_MASK 0x1 |
| #define AFE_DL_PREDIS_ON_CH1_CTL_MASK_SFT (0x1 << 7) |
| #define AFE_DL_PREDIS_A2_CH1_CTL_H_SFT 0 |
| #define AFE_DL_PREDIS_A2_CH1_CTL_H_MASK 0xf |
| #define AFE_DL_PREDIS_A2_CH1_CTL_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_ADDA_DL_PREDIS_CON0_M */ |
| #define AFE_DL_PREDIS_A2_CH1_CTL_SFT 0 |
| #define AFE_DL_PREDIS_A2_CH1_CTL_MASK 0xff |
| #define AFE_DL_PREDIS_A2_CH1_CTL_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_PREDIS_CON0_L */ |
| #define AFE_DL_PREDIS_A3_CH1_CTL_H_SFT 0 |
| #define AFE_DL_PREDIS_A3_CH1_CTL_H_MASK 0xf |
| #define AFE_DL_PREDIS_A3_CH1_CTL_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_ADDA_DL_PREDIS_CON0 */ |
| #define AFE_DL_PREDIS_A3_CH1_CTL_SFT 0 |
| #define AFE_DL_PREDIS_A3_CH1_CTL_MASK 0xff |
| #define AFE_DL_PREDIS_A3_CH1_CTL_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_PREDIS_CON1_H */ |
| #define AFE_DL_PREDIS_ON_CH2_CTL_SFT 7 |
| #define AFE_DL_PREDIS_ON_CH2_CTL_MASK 0x1 |
| #define AFE_DL_PREDIS_ON_CH2_CTL_MASK_SFT (0x1 << 7) |
| #define AFE_DL_PREDIS_A2_CH2_CTL_H_SFT 0 |
| #define AFE_DL_PREDIS_A2_CH2_CTL_H_MASK 0xf |
| #define AFE_DL_PREDIS_A2_CH2_CTL_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_ADDA_DL_PREDIS_CON1_M */ |
| #define AFE_DL_PREDIS_A2_CH2_CTL_SFT 0 |
| #define AFE_DL_PREDIS_A2_CH2_CTL_MASK 0xff |
| #define AFE_DL_PREDIS_A2_CH2_CTL_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_PREDIS_CON1_L */ |
| #define AFE_DL_PREDIS_A3_CH2_CTL_H_SFT 0 |
| #define AFE_DL_PREDIS_A3_CH2_CTL_H_MASK 0xf |
| #define AFE_DL_PREDIS_A3_CH2_CTL_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_ADDA_DL_PREDIS_CON1 */ |
| #define AFE_DL_PREDIS_A3_CH2_CTL_SFT 0 |
| #define AFE_DL_PREDIS_A3_CH2_CTL_MASK 0xff |
| #define AFE_DL_PREDIS_A3_CH2_CTL_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_PREDIS_CON2_H */ |
| #define AFE_DL_PREDIS_A4_CH1_CTL_H_SFT 0 |
| #define AFE_DL_PREDIS_A4_CH1_CTL_H_MASK 0xf |
| #define AFE_DL_PREDIS_A4_CH1_CTL_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_ADDA_DL_PREDIS_CON2_M */ |
| #define AFE_DL_PREDIS_A4_CH1_CTL_SFT 0 |
| #define AFE_DL_PREDIS_A4_CH1_CTL_MASK 0xff |
| #define AFE_DL_PREDIS_A4_CH1_CTL_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_PREDIS_CON2_L */ |
| #define AFE_DL_PREDIS_A5_CH1_CTL_H_SFT 0 |
| #define AFE_DL_PREDIS_A5_CH1_CTL_H_MASK 0xf |
| #define AFE_DL_PREDIS_A5_CH1_CTL_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_ADDA_DL_PREDIS_CON2 */ |
| #define AFE_DL_PREDIS_A5_CH1_CTL_SFT 0 |
| #define AFE_DL_PREDIS_A5_CH1_CTL_MASK 0xff |
| #define AFE_DL_PREDIS_A5_CH1_CTL_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_PREDIS_CON3_H */ |
| #define AFE_DL_PREDIS_A4_CH2_CTL_H_SFT 0 |
| #define AFE_DL_PREDIS_A4_CH2_CTL_H_MASK 0xf |
| #define AFE_DL_PREDIS_A4_CH2_CTL_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_ADDA_DL_PREDIS_CON3_M */ |
| #define AFE_DL_PREDIS_A4_CH2_CTL_SFT 0 |
| #define AFE_DL_PREDIS_A4_CH2_CTL_MASK 0xff |
| #define AFE_DL_PREDIS_A4_CH2_CTL_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_PREDIS_CON3_L */ |
| #define AFE_DL_PREDIS_A5_CH2_CTL_H_SFT 0 |
| #define AFE_DL_PREDIS_A5_CH2_CTL_H_MASK 0xf |
| #define AFE_DL_PREDIS_A5_CH2_CTL_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_ADDA_DL_PREDIS_CON3 */ |
| #define AFE_DL_PREDIS_A5_CH2_CTL_SFT 0 |
| #define AFE_DL_PREDIS_A5_CH2_CTL_MASK 0xff |
| #define AFE_DL_PREDIS_A5_CH2_CTL_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SDM_DCCOMP_CON_H */ |
| #define AFE_DL_USE_NEW_2ND_12BIT_SDM_SFT 7 |
| #define AFE_DL_USE_NEW_2ND_12BIT_SDM_MASK 0x1 |
| #define AFE_DL_USE_NEW_2ND_12BIT_SDM_MASK_SFT (0x1 << 7) |
| #define AFE_DL_USE_NEW_2ND_SDM_SFT 6 |
| #define AFE_DL_USE_NEW_2ND_SDM_MASK 0x1 |
| #define AFE_DL_USE_NEW_2ND_SDM_MASK_SFT (0x1 << 6) |
| #define AFE_DL_USE_3RD_SDM_SFT 4 |
| #define AFE_DL_USE_3RD_SDM_MASK 0x1 |
| #define AFE_DL_USE_3RD_SDM_MASK_SFT (0x1 << 4) |
| |
| /* AFE_ADDA_DL_SDM_DCCOMP_CON_L */ |
| #define MT6338_AFE_DL_DCM_AUTO_IDLE_EN_SFT 6 |
| #define MT6338_AFE_DL_DCM_AUTO_IDLE_EN_MASK 0x1 |
| #define MT6338_AFE_DL_DCM_AUTO_IDLE_EN_MASK_SFT (0x1 << 6) |
| #define MT6338_AFE_DL_SRC_DCM_EN_SFT 5 |
| #define MT6338_AFE_DL_SRC_DCM_EN_MASK 0x1 |
| #define MT6338_AFE_DL_SRC_DCM_EN_MASK_SFT (0x1 << 5) |
| #define MT6338_AFE_DL_POST_SRC_DCM_EN_SFT 4 |
| #define MT6338_AFE_DL_POST_SRC_DCM_EN_MASK 0x1 |
| #define MT6338_AFE_DL_POST_SRC_DCM_EN_MASK_SFT (0x1 << 4) |
| #define MT6338_AFE_DL_AUD_SDM_MONO_SFT 1 |
| #define MT6338_AFE_DL_AUD_SDM_MONO_MASK 0x1 |
| #define MT6338_AFE_DL_AUD_SDM_MONO_MASK_SFT (0x1 << 1) |
| #define MT6338_AFE_DL_AUD_DC_COMP_EN_SFT 0 |
| #define MT6338_AFE_DL_AUD_DC_COMP_EN_MASK 0x1 |
| #define MT6338_AFE_DL_AUD_DC_COMP_EN_MASK_SFT (0x1 << 0) |
| |
| /* AFE_ADDA_DL_SDM_DCCOMP_CON */ |
| #define AFE_DL_ATTGAIN_CTL_SFT 0 |
| #define AFE_DL_ATTGAIN_CTL_MASK 0x3f |
| #define AFE_DL_ATTGAIN_CTL_MASK_SFT (0x3f << 0) |
| |
| /* AFE_ADDA_DL_SDM_TEST_L */ |
| #define AFE_DL_TRI_AMP_DIV_SFT 4 |
| #define AFE_DL_TRI_AMP_DIV_MASK 0x7 |
| #define AFE_DL_TRI_AMP_DIV_MASK_SFT (0x7 << 4) |
| #define AFE_DL_TRI_FREQ_DIV_H_SFT 0 |
| #define AFE_DL_TRI_FREQ_DIV_H_MASK 0x3 |
| #define AFE_DL_TRI_FREQ_DIV_H_MASK_SFT (0x3 << 0) |
| |
| /* AFE_ADDA_DL_SDM_TEST */ |
| #define AFE_DL_TRI_FREQ_DIV_SFT 4 |
| #define AFE_DL_TRI_FREQ_DIV_MASK 0xf |
| #define AFE_DL_TRI_FREQ_DIV_MASK_SFT (0xf << 4) |
| #define AFE_DL_RG_DL_LEFT_SAT_RSTN_SFT 3 |
| #define AFE_DL_RG_DL_LEFT_SAT_RSTN_MASK 0x1 |
| #define AFE_DL_RG_DL_LEFT_SAT_RSTN_MASK_SFT (0x1 << 3) |
| #define AFE_DL_RG_DL_RIGHT_SAT_RSTN_SFT 2 |
| #define AFE_DL_RG_DL_RIGHT_SAT_RSTN_MASK 0x1 |
| #define AFE_DL_RG_DL_RIGHT_SAT_RSTN_MASK_SFT (0x1 << 2) |
| #define AFE_DL_TRI_MUTE_SW_SFT 1 |
| #define AFE_DL_TRI_MUTE_SW_MASK 0x1 |
| #define AFE_DL_TRI_MUTE_SW_MASK_SFT (0x1 << 1) |
| #define AFE_DL_TRI_DAC_EN_SFT 0 |
| #define AFE_DL_TRI_DAC_EN_MASK 0x1 |
| #define AFE_DL_TRI_DAC_EN_MASK_SFT (0x1 << 0) |
| |
| /* AFE_ADDA_DL_DC_COMP_CFG0_H */ |
| #define AFE_DL_AUD_DC_COMP_LCH_H_H_SFT 0 |
| #define AFE_DL_AUD_DC_COMP_LCH_H_H_MASK 0xff |
| #define AFE_DL_AUD_DC_COMP_LCH_H_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_DC_COMP_CFG0_M */ |
| #define AFE_DL_AUD_DC_COMP_LCH_H_SFT 0 |
| #define AFE_DL_AUD_DC_COMP_LCH_H_MASK 0xff |
| #define AFE_DL_AUD_DC_COMP_LCH_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_DC_COMP_CFG0_L */ |
| #define AFE_DL_AUD_DC_COMP_LCH_L_H_SFT 0 |
| #define AFE_DL_AUD_DC_COMP_LCH_L_H_MASK 0xff |
| #define AFE_DL_AUD_DC_COMP_LCH_L_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_DC_COMP_CFG0 */ |
| #define AFE_DL_AUD_DC_COMP_LCH_L_SFT 0 |
| #define AFE_DL_AUD_DC_COMP_LCH_L_MASK 0xff |
| #define AFE_DL_AUD_DC_COMP_LCH_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_DC_COMP_CFG1_H */ |
| #define AFE_DL_AUD_DC_COMP_RCH_H_H_SFT 0 |
| #define AFE_DL_AUD_DC_COMP_RCH_H_H_MASK 0xff |
| #define AFE_DL_AUD_DC_COMP_RCH_H_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_DC_COMP_CFG1_M */ |
| #define AFE_DL_AUD_DC_COMP_RCH_H_SFT 0 |
| #define AFE_DL_AUD_DC_COMP_RCH_H_MASK 0xff |
| #define AFE_DL_AUD_DC_COMP_RCH_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_DC_COMP_CFG1_L */ |
| #define AFE_DL_AUD_DC_COMP_RCH_L_H_SFT 0 |
| #define AFE_DL_AUD_DC_COMP_RCH_L_H_MASK 0xff |
| #define AFE_DL_AUD_DC_COMP_RCH_L_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_DC_COMP_CFG1 */ |
| #define AFE_DL_AUD_DC_COMP_RCH_L_SFT 0 |
| #define AFE_DL_AUD_DC_COMP_RCH_L_MASK 0xff |
| #define AFE_DL_AUD_DC_COMP_RCH_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SDM_OUT_MON_H */ |
| #define AFE_DL_SDM_DITHER_MON_SFT 4 |
| #define AFE_DL_SDM_DITHER_MON_MASK 0x3 |
| #define AFE_DL_SDM_DITHER_MON_MASK_SFT (0x3 << 4) |
| #define AFE_DL_ZERO_OUT_R_SFT 3 |
| #define AFE_DL_ZERO_OUT_R_MASK 0x1 |
| #define AFE_DL_ZERO_OUT_R_MASK_SFT (0x1 << 3) |
| #define AFE_DL_SIGN_OUT_R_SFT 2 |
| #define AFE_DL_SIGN_OUT_R_MASK 0x1 |
| #define AFE_DL_SIGN_OUT_R_MASK_SFT (0x1 << 2) |
| #define AFE_DL_ZERO_OUT_L_SFT 1 |
| #define AFE_DL_ZERO_OUT_L_MASK 0x1 |
| #define AFE_DL_ZERO_OUT_L_MASK_SFT (0x1 << 1) |
| #define AFE_DL_SIGN_OUT_L_SFT 0 |
| #define AFE_DL_SIGN_OUT_L_MASK 0x1 |
| #define AFE_DL_SIGN_OUT_L_MASK_SFT (0x1 << 0) |
| |
| /* AFE_ADDA_DL_SDM_OUT_MON_M */ |
| #define AFE_DL_BF_SDM_LEFT_SAT_SFT 5 |
| #define AFE_DL_BF_SDM_LEFT_SAT_MASK 0x1 |
| #define AFE_DL_BF_SDM_LEFT_SAT_MASK_SFT (0x1 << 5) |
| #define AFE_DL_BF_SDM_RIGHT_SAT_SFT 4 |
| #define AFE_DL_BF_SDM_RIGHT_SAT_MASK 0x1 |
| #define AFE_DL_BF_SDM_RIGHT_SAT_MASK_SFT (0x1 << 4) |
| #define AFE_DL_3RD_SDM_AUTO_RESET_R_SFT 3 |
| #define AFE_DL_3RD_SDM_AUTO_RESET_R_MASK 0x1 |
| #define AFE_DL_3RD_SDM_AUTO_RESET_R_MASK_SFT (0x1 << 3) |
| #define AFE_DL_3RD_SDM_AUTO_RESET_L_SFT 2 |
| #define AFE_DL_3RD_SDM_AUTO_RESET_L_MASK 0x1 |
| #define AFE_DL_3RD_SDM_AUTO_RESET_L_MASK_SFT (0x1 << 2) |
| #define AFE_DL_2ND_SDM_AUTO_RESET_R_SFT 1 |
| #define AFE_DL_2ND_SDM_AUTO_RESET_R_MASK 0x1 |
| #define AFE_DL_2ND_SDM_AUTO_RESET_R_MASK_SFT (0x1 << 1) |
| #define AFE_DL_2ND_SDM_AUTO_RESET_L_SFT 0 |
| #define AFE_DL_2ND_SDM_AUTO_RESET_L_MASK 0x1 |
| #define AFE_DL_2ND_SDM_AUTO_RESET_L_MASK_SFT (0x1 << 0) |
| |
| /* AFE_ADDA_DL_SDM_OUT_MON_L */ |
| #define AFE_DL_AUD_SDM_OUT_L_SFT 0 |
| #define AFE_DL_AUD_SDM_OUT_L_MASK 0xff |
| #define AFE_DL_AUD_SDM_OUT_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SDM_OUT_MON */ |
| #define AFE_DL_AUD_SDM_OUT_R_SFT 0 |
| #define AFE_DL_AUD_SDM_OUT_R_MASK 0xff |
| #define AFE_DL_AUD_SDM_OUT_R_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SRC_LCH_MON_M */ |
| #define AFE_DL_ASDM_LEFT_H_SFT 0 |
| #define AFE_DL_ASDM_LEFT_H_MASK 0xff |
| #define AFE_DL_ASDM_LEFT_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SRC_LCH_MON_L */ |
| #define AFE_DL_ASDM_LEFT_M_SFT 0 |
| #define AFE_DL_ASDM_LEFT_M_MASK 0xff |
| #define AFE_DL_ASDM_LEFT_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SRC_LCH_MON */ |
| #define AFE_DL_ASDM_LEFT_SFT 0 |
| #define AFE_DL_ASDM_LEFT_MASK 0xff |
| #define AFE_DL_ASDM_LEFT_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SRC_RCH_MON_M */ |
| #define AFE_DL_ASDM_RIGHT_H_SFT 0 |
| #define AFE_DL_ASDM_RIGHT_H_MASK 0xff |
| #define AFE_DL_ASDM_RIGHT_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SRC_RCH_MON_L */ |
| #define AFE_DL_ASDM_RIGHT_M_SFT 0 |
| #define AFE_DL_ASDM_RIGHT_M_MASK 0xff |
| #define AFE_DL_ASDM_RIGHT_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SRC_RCH_MON */ |
| #define AFE_DL_ASDM_RIGHT_SFT 0 |
| #define AFE_DL_ASDM_RIGHT_MASK 0xff |
| #define AFE_DL_ASDM_RIGHT_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SRC_DEBUG_L */ |
| #define AFE_DL_SLT_CNT_FLAG_RESET_CTL_SFT 4 |
| #define AFE_DL_SLT_CNT_FLAG_RESET_CTL_MASK 0x1 |
| #define AFE_DL_SLT_CNT_FLAG_RESET_CTL_MASK_SFT (0x1 << 4) |
| #define AFE_DL_SLT_CNT_THD_CTL_H_SFT 0 |
| #define AFE_DL_SLT_CNT_THD_CTL_H_MASK 0xf |
| #define AFE_DL_SLT_CNT_THD_CTL_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_ADDA_DL_SRC_DEBUG */ |
| #define AFE_DL_SLT_CNT_THD_CTL_SFT 0 |
| #define AFE_DL_SLT_CNT_THD_CTL_MASK 0xff |
| #define AFE_DL_SLT_CNT_THD_CTL_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SDM_DITHER_CON_M */ |
| #define AFE_DL_SDM_DITHER_64TAP_EN_SFT 4 |
| #define AFE_DL_SDM_DITHER_64TAP_EN_MASK 0x1 |
| #define AFE_DL_SDM_DITHER_64TAP_EN_MASK_SFT (0x1 << 4) |
| #define AFE_DL_SDM_DITHER_EN_SFT 0 |
| #define AFE_DL_SDM_DITHER_EN_MASK 0x1 |
| #define AFE_DL_SDM_DITHER_EN_MASK_SFT (0x1 << 0) |
| |
| /* AFE_ADDA_DL_SDM_DITHER_CON */ |
| #define AFE_DL_SDM_DITHER_GAIN_SFT 0 |
| #define AFE_DL_SDM_DITHER_GAIN_MASK 0xff |
| #define AFE_DL_SDM_DITHER_GAIN_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SDM_AUTO_RESET_CON_H */ |
| #define AFE_DL_SDM_AUTO_RESET_TEST_ON_SFT 7 |
| #define AFE_DL_SDM_AUTO_RESET_TEST_ON_MASK 0x1 |
| #define AFE_DL_SDM_AUTO_RESET_TEST_ON_MASK_SFT (0x1 << 7) |
| #define AFE_DL_SDM_AUTO_RESET_SOURCE_SEL_SFT 0 |
| #define AFE_DL_SDM_AUTO_RESET_SOURCE_SEL_MASK 0x1 |
| #define AFE_DL_SDM_AUTO_RESET_SOURCE_SEL_MASK_SFT (0x1 << 0) |
| |
| /* AFE_ADDA_DL_SDM_AUTO_RESET_CON_M */ |
| #define AFE_DL_SDM_AUTO_RESET_COUNT_TH_H_SFT 0 |
| #define AFE_DL_SDM_AUTO_RESET_COUNT_TH_H_MASK 0xff |
| #define AFE_DL_SDM_AUTO_RESET_COUNT_TH_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SDM_AUTO_RESET_CON_L */ |
| #define AFE_DL_SDM_AUTO_RESET_COUNT_TH_L_SFT 0 |
| #define AFE_DL_SDM_AUTO_RESET_COUNT_TH_L_MASK 0xff |
| #define AFE_DL_SDM_AUTO_RESET_COUNT_TH_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SDM_AUTO_RESET_CON */ |
| #define AFE_DL_SDM_AUTO_RESET_COUNT_TH_SFT 0 |
| #define AFE_DL_SDM_AUTO_RESET_COUNT_TH_MASK 0xff |
| #define AFE_DL_SDM_AUTO_RESET_COUNT_TH_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H1R2L_CON0_H */ |
| #define AFE_DL_XTALK_COMP_H1_R2L_ENABLE_SFT 7 |
| #define AFE_DL_XTALK_COMP_H1_R2L_ENABLE_MASK 0x1 |
| #define AFE_DL_XTALK_COMP_H1_R2L_ENABLE_MASK_SFT (0x1 << 7) |
| |
| /* AFE_DL_XTALK_COMP_H1R2L_CON0_M */ |
| #define AFE_DL_XTALK_COMP_H1_R2L_COEFF_H_SFT 0 |
| #define AFE_DL_XTALK_COMP_H1_R2L_COEFF_H_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H1_R2L_COEFF_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H1R2L_CON0_L */ |
| #define AFE_DL_XTALK_COMP_H1_R2L_COEFF_M_SFT 0 |
| #define AFE_DL_XTALK_COMP_H1_R2L_COEFF_M_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H1_R2L_COEFF_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H1R2L_CON0 */ |
| #define AFE_DL_XTALK_COMP_H1_R2L_COEFF_SFT 0 |
| #define AFE_DL_XTALK_COMP_H1_R2L_COEFF_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H1_R2L_COEFF_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H1L2R_CON0_H */ |
| #define AFE_DL_XTALK_COMP_H1_L2R_ENABLE_SFT 7 |
| #define AFE_DL_XTALK_COMP_H1_L2R_ENABLE_MASK 0x1 |
| #define AFE_DL_XTALK_COMP_H1_L2R_ENABLE_MASK_SFT (0x1 << 7) |
| |
| /* AFE_DL_XTALK_COMP_H1L2R_CON0_M */ |
| #define AFE_DL_XTALK_COMP_H1_L2R_COEFF_H_SFT 0 |
| #define AFE_DL_XTALK_COMP_H1_L2R_COEFF_H_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H1_L2R_COEFF_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H1L2R_CON0_L */ |
| #define AFE_DL_XTALK_COMP_H1_L2R_COEFF_M_SFT 0 |
| #define AFE_DL_XTALK_COMP_H1_L2R_COEFF_M_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H1_L2R_COEFF_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H1L2R_CON0 */ |
| #define AFE_DL_XTALK_COMP_H1_L2R_COEFF_SFT 0 |
| #define AFE_DL_XTALK_COMP_H1_L2R_COEFF_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H1_L2R_COEFF_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2R2L_CON0_H */ |
| #define AFE_DL_XTALK_COMP_H2_R2L_ENABLE_SFT 7 |
| #define AFE_DL_XTALK_COMP_H2_R2L_ENABLE_MASK 0x1 |
| #define AFE_DL_XTALK_COMP_H2_R2L_ENABLE_MASK_SFT (0x1 << 7) |
| |
| /* AFE_DL_XTALK_COMP_H2R2L_CON0_M */ |
| #define AFE_DL_XTALK_COMP_H2_R2L_B0_COEFF_H_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_R2L_B0_COEFF_H_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_R2L_B0_COEFF_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2R2L_CON0_L */ |
| #define AFE_DL_XTALK_COMP_H2_R2L_B0_COEFF_M_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_R2L_B0_COEFF_M_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_R2L_B0_COEFF_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2R2L_CON0 */ |
| #define AFE_DL_XTALK_COMP_H2_R2L_B0_COEFF_L_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_R2L_B0_COEFF_L_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_R2L_B0_COEFF_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2R2L_CON1_M */ |
| #define AFE_DL_XTALK_COMP_H2_R2L_B1_COEFF_H_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_R2L_B1_COEFF_H_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_R2L_B1_COEFF_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2R2L_CON1_L */ |
| #define AFE_DL_XTALK_COMP_H2_R2L_B1_COEFF_M_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_R2L_B1_COEFF_M_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_R2L_B1_COEFF_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2R2L_CON1 */ |
| #define AFE_DL_XTALK_COMP_H2_R2L_B1_COEFF_L_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_R2L_B1_COEFF_L_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_R2L_B1_COEFF_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2R2L_CON2_M */ |
| #define AFE_DL_XTALK_COMP_H2_R2L_B2_COEFF_H_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_R2L_B2_COEFF_H_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_R2L_B2_COEFF_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2R2L_CON2_L */ |
| #define AFE_DL_XTALK_COMP_H2_R2L_B2_COEFF_M_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_R2L_B2_COEFF_M_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_R2L_B2_COEFF_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2R2L_CON2 */ |
| #define AFE_DL_XTALK_COMP_H2_R2L_B2_COEFF_L_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_R2L_B2_COEFF_L_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_R2L_B2_COEFF_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2R2L_CON3_M */ |
| #define AFE_DL_XTALK_COMP_H2_R2L_A1_COEFF_H_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_R2L_A1_COEFF_H_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_R2L_A1_COEFF_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2R2L_CON3_L */ |
| #define AFE_DL_XTALK_COMP_H2_R2L_A1_COEFF_M_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_R2L_A1_COEFF_M_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_R2L_A1_COEFF_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2R2L_CON3 */ |
| #define AFE_DL_XTALK_COMP_H2_R2L_A1_COEFF_L_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_R2L_A1_COEFF_L_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_R2L_A1_COEFF_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2R2L_CON4_M */ |
| #define AFE_DL_XTALK_COMP_H2_R2L_A2_COEFF_H_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_R2L_A2_COEFF_H_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_R2L_A2_COEFF_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2R2L_CON4_L */ |
| #define AFE_DL_XTALK_COMP_H2_R2L_A2_COEFF_M_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_R2L_A2_COEFF_M_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_R2L_A2_COEFF_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2R2L_CON4 */ |
| #define AFE_DL_XTALK_COMP_H2_R2L_A2_COEFF_L_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_R2L_A2_COEFF_L_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_R2L_A2_COEFF_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2L2R_CON0_H */ |
| #define AFE_DL_XTALK_COMP_H2_L2R_ENABLE_SFT 7 |
| #define AFE_DL_XTALK_COMP_H2_L2R_ENABLE_MASK 0x1 |
| #define AFE_DL_XTALK_COMP_H2_L2R_ENABLE_MASK_SFT (0x1 << 7) |
| |
| /* AFE_DL_XTALK_COMP_H2L2R_CON0_M */ |
| #define AFE_DL_XTALK_COMP_H2_L2R_B0_COEFF_H_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_L2R_B0_COEFF_H_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_L2R_B0_COEFF_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2L2R_CON0_L */ |
| #define AFE_DL_XTALK_COMP_H2_L2R_B0_COEFF_M_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_L2R_B0_COEFF_M_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_L2R_B0_COEFF_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2L2R_CON0 */ |
| #define AFE_DL_XTALK_COMP_H2_L2R_B0_COEFF_L_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_L2R_B0_COEFF_L_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_L2R_B0_COEFF_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2L2R_CON1_M */ |
| #define AFE_DL_XTALK_COMP_H2_L2R_B1_COEFF_H_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_L2R_B1_COEFF_H_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_L2R_B1_COEFF_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2L2R_CON1_L */ |
| #define AFE_DL_XTALK_COMP_H2_L2R_B1_COEFF_M_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_L2R_B1_COEFF_M_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_L2R_B1_COEFF_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2L2R_CON1 */ |
| #define AFE_DL_XTALK_COMP_H2_L2R_B1_COEFF_L_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_L2R_B1_COEFF_L_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_L2R_B1_COEFF_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2L2R_CON2_M */ |
| #define AFE_DL_XTALK_COMP_H2_L2R_B2_COEFF_H_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_L2R_B2_COEFF_H_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_L2R_B2_COEFF_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2L2R_CON2_L */ |
| #define AFE_DL_XTALK_COMP_H2_L2R_B2_COEFF_M_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_L2R_B2_COEFF_M_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_L2R_B2_COEFF_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2L2R_CON2 */ |
| #define AFE_DL_XTALK_COMP_H2_L2R_B2_COEFF_L_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_L2R_B2_COEFF_L_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_L2R_B2_COEFF_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2L2R_CON3_M */ |
| #define AFE_DL_XTALK_COMP_H2_L2R_A1_COEFF_H_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_L2R_A1_COEFF_H_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_L2R_A1_COEFF_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2L2R_CON3_L */ |
| #define AFE_DL_XTALK_COMP_H2_L2R_A1_COEFF_M_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_L2R_A1_COEFF_M_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_L2R_A1_COEFF_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2L2R_CON3 */ |
| #define AFE_DL_XTALK_COMP_H2_L2R_A1_COEFF_L_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_L2R_A1_COEFF_L_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_L2R_A1_COEFF_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2L2R_CON4_M */ |
| #define AFE_DL_XTALK_COMP_H2_L2R_A2_COEFF_H_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_L2R_A2_COEFF_H_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_L2R_A2_COEFF_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2L2R_CON4_L */ |
| #define AFE_DL_XTALK_COMP_H2_L2R_A2_COEFF_M_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_L2R_A2_COEFF_M_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_L2R_A2_COEFF_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_DL_XTALK_COMP_H2L2R_CON4 */ |
| #define AFE_DL_XTALK_COMP_H2_L2R_A2_COEFF_L_SFT 0 |
| #define AFE_DL_XTALK_COMP_H2_L2R_A2_COEFF_L_MASK 0xff |
| #define AFE_DL_XTALK_COMP_H2_L2R_A2_COEFF_L_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_8TH_DSN_ID */ |
| #define AUDIO_DIG_8TH_ANA_ID_SFT 0 |
| #define AUDIO_DIG_8TH_ANA_ID_MASK 0xff |
| #define AUDIO_DIG_8TH_ANA_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_8TH_DSN_ID_H */ |
| #define AUDIO_DIG_8TH_DIG_ID_SFT 0 |
| #define AUDIO_DIG_8TH_DIG_ID_MASK 0xff |
| #define AUDIO_DIG_8TH_DIG_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_8TH_DSN_REV0 */ |
| #define AUDIO_DIG_8TH_ANA_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_8TH_ANA_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_8TH_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_8TH_ANA_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_8TH_ANA_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_8TH_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_8TH_DSN_REV0_H */ |
| #define AUDIO_DIG_8TH_DIG_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_8TH_DIG_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_8TH_DIG_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_8TH_DIG_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_8TH_DIG_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_8TH_DIG_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_8TH_DSN_DBI */ |
| #define AUDIO_DIG_8TH_DSN_CBS_SFT 0 |
| #define AUDIO_DIG_8TH_DSN_CBS_MASK 0x3 |
| #define AUDIO_DIG_8TH_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDIO_DIG_8TH_DSN_BIX_SFT 2 |
| #define AUDIO_DIG_8TH_DSN_BIX_MASK 0x3 |
| #define AUDIO_DIG_8TH_DSN_BIX_MASK_SFT (0x3 << 2) |
| |
| /* AUDIO_DIG_8TH_DSN_DBI_H */ |
| #define AUDIO_DIG_8_ESP_SFT 0 |
| #define AUDIO_DIG_8_ESP_MASK 0xff |
| #define AUDIO_DIG_8_ESP_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_8TH_DSN_DXI */ |
| #define AUDIO_DIG_8TH_DSN_FPI_SFT 0 |
| #define AUDIO_DIG_8TH_DSN_FPI_MASK 0xff |
| #define AUDIO_DIG_8TH_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_CFG_H */ |
| #define SW_RSTB_SFT 7 |
| #define SW_RSTB_MASK 0x1 |
| #define SW_RSTB_MASK_SFT (0x1 << 7) |
| |
| /* AFE_NLE_CFG */ |
| #define RG_LOW_LATENCY_MODE_SFT 2 |
| #define RG_LOW_LATENCY_MODE_MASK 0x1 |
| #define RG_LOW_LATENCY_MODE_MASK_SFT (0x1 << 2) |
| #define RG_BYPASS_NLE_SFT 1 |
| #define RG_BYPASS_NLE_MASK 0x1 |
| #define RG_BYPASS_NLE_MASK_SFT (0x1 << 1) |
| #define RG_AFE_NLE_ON_SFT 0 |
| #define RG_AFE_NLE_ON_MASK 0x1 |
| #define RG_AFE_NLE_ON_MASK_SFT (0x1 << 0) |
| |
| /* AFE_NLE_PRE_BUF_CFG_H */ |
| #define BYPASS_DELAY_SFT 2 |
| #define BYPASS_DELAY_MASK 0x1 |
| #define BYPASS_DELAY_MASK_SFT (0x1 << 2) |
| |
| /* AFE_NLE_PRE_BUF_CFG_M */ |
| #define SRAM_ADDR_REG_H_SFT 0 |
| #define SRAM_ADDR_REG_H_MASK 0x7f |
| #define SRAM_ADDR_REG_H_MASK_SFT (0x7f << 0) |
| |
| /* AFE_NLE_PRE_BUF_CFG_L */ |
| #define SRAM_ADDR_REG_SFT 4 |
| #define SRAM_ADDR_REG_MASK 0xf |
| #define SRAM_ADDR_REG_MASK_SFT (0xf << 4) |
| #define POINT_END_H_SFT 0 |
| #define POINT_END_H_MASK 0x7 |
| #define POINT_END_H_MASK_SFT (0x7 << 0) |
| |
| /* AFE_NLE_PRE_BUF_CFG */ |
| #define POINT_END_SFT 0 |
| #define POINT_END_MASK 0xff |
| #define POINT_END_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_PWR_DET_LCH_CFG_H */ |
| #define RG_H2L_BYPASS_1ST_START_LCH_SFT 7 |
| #define RG_H2L_BYPASS_1ST_START_LCH_MASK 0x1 |
| #define RG_H2L_BYPASS_1ST_START_LCH_MASK_SFT (0x1 << 7) |
| #define RG_SW_DISABLE_POWER_DETECT_LCH_SFT 6 |
| #define RG_SW_DISABLE_POWER_DETECT_LCH_MASK 0x1 |
| #define RG_SW_DISABLE_POWER_DETECT_LCH_MASK_SFT (0x1 << 6) |
| #define RG_H2L_HOLD_TIME_LCH_SFT 0 |
| #define RG_H2L_HOLD_TIME_LCH_MASK 0x1f |
| #define RG_H2L_HOLD_TIME_LCH_MASK_SFT (0x1f << 0) |
| |
| /* AFE_NLE_PWR_DET_LCH_CFG_M */ |
| #define RG_NLE_VTH_LCH_H_SFT 0 |
| #define RG_NLE_VTH_LCH_H_MASK 0xff |
| #define RG_NLE_VTH_LCH_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_PWR_DET_LCH_CFG_L */ |
| #define RG_NLE_VTH_LCH_M_SFT 0 |
| #define RG_NLE_VTH_LCH_M_MASK 0xff |
| #define RG_NLE_VTH_LCH_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_PWR_DET_LCH_CFG */ |
| #define RG_NLE_VTH_LCH_SFT 0 |
| #define RG_NLE_VTH_LCH_MASK 0xff |
| #define RG_NLE_VTH_LCH_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_ZCD_LCH_CFG */ |
| #define RG_ZCD_CHECK_MODE_LCH_SFT 2 |
| #define RG_ZCD_CHECK_MODE_LCH_MASK 0x1 |
| #define RG_ZCD_CHECK_MODE_LCH_MASK_SFT (0x1 << 2) |
| #define RG_ZCD_MODE_SEL_LCH_SFT 0 |
| #define RG_ZCD_MODE_SEL_LCH_MASK 0x3 |
| #define RG_ZCD_MODE_SEL_LCH_MASK_SFT (0x3 << 0) |
| |
| /* AFE_NLE_GAIN_ADJ_LCH_CFG0_H */ |
| #define RG_GAIN_ADJ_BYPASS_ZCD_LCH_SFT 7 |
| #define RG_GAIN_ADJ_BYPASS_ZCD_LCH_MASK 0x1 |
| #define RG_GAIN_ADJ_BYPASS_ZCD_LCH_MASK_SFT (0x1 << 7) |
| #define RG_TIME_OUT_LCH_SFT 0 |
| #define RG_TIME_OUT_LCH_MASK 0x3f |
| #define RG_TIME_OUT_LCH_MASK_SFT (0x3f << 0) |
| |
| /* AFE_NLE_GAIN_ADJ_LCH_CFG0_M */ |
| #define RG_HOLD_TIME_PER_JUMP_LCH_SFT 4 |
| #define RG_HOLD_TIME_PER_JUMP_LCH_MASK 0x7 |
| #define RG_HOLD_TIME_PER_JUMP_LCH_MASK_SFT (0x7 << 4) |
| #define RG_GAIN_STEP_PER_JUMP_LCH_SFT 0 |
| #define RG_GAIN_STEP_PER_JUMP_LCH_MASK 0x3 |
| #define RG_GAIN_STEP_PER_JUMP_LCH_MASK_SFT (0x3 << 0) |
| |
| /* AFE_NLE_GAIN_ADJ_LCH_CFG0_L */ |
| #define RG_GAIN_STEP_PER_ZCD_LCH_SFT 0 |
| #define RG_GAIN_STEP_PER_ZCD_LCH_MASK 0x7 |
| #define RG_GAIN_STEP_PER_ZCD_LCH_MASK_SFT (0x7 << 0) |
| |
| /* AFE_NLE_GAIN_ADJ_LCH_CFG0 */ |
| #define RG_AG_MIN_LCH_SFT 4 |
| #define RG_AG_MIN_LCH_MASK 0x7 |
| #define RG_AG_MIN_LCH_MASK_SFT (0x7 << 4) |
| #define RG_AG_MAX_LCH_SFT 0 |
| #define RG_AG_MAX_LCH_MASK 0x7 |
| #define RG_AG_MAX_LCH_MASK_SFT (0x7 << 0) |
| |
| /* AFE_NLE_GAIN_IMP_LCH_CFG0_H */ |
| #define RG_DG_SAT_LCH_SFT 7 |
| #define RG_DG_SAT_LCH_MASK 0x1 |
| #define RG_DG_SAT_LCH_MASK_SFT (0x1 << 7) |
| #define RG_DG_OUTPUT_DEBUG_MODE_LCH_SFT 6 |
| #define RG_DG_OUTPUT_DEBUG_MODE_LCH_MASK 0x1 |
| #define RG_DG_OUTPUT_DEBUG_MODE_LCH_MASK_SFT (0x1 << 6) |
| #define RG_DG_FIX_MANUAL_MODE_LCH_SFT 5 |
| #define RG_DG_FIX_MANUAL_MODE_LCH_MASK 0x1 |
| #define RG_DG_FIX_MANUAL_MODE_LCH_MASK_SFT (0x1 << 5) |
| #define RG_AG_FIX_MANUAL_MODE_LCH_SFT 4 |
| #define RG_AG_FIX_MANUAL_MODE_LCH_MASK 0x1 |
| #define RG_AG_FIX_MANUAL_MODE_LCH_MASK_SFT (0x1 << 4) |
| #define RG_DG_DELAY_LCH_SFT 0 |
| #define RG_DG_DELAY_LCH_MASK 0x7 |
| #define RG_DG_DELAY_LCH_MASK_SFT (0x7 << 0) |
| |
| /* AFE_NLE_GAIN_IMP_LCH_CFG0_M */ |
| #define RG_AG_DELAY_LCH_SFT 0 |
| #define RG_AG_DELAY_LCH_MASK 0x3f |
| #define RG_AG_DELAY_LCH_MASK_SFT (0x3f << 0) |
| |
| /* AFE_NLE_GAIN_IMP_LCH_CFG0_L */ |
| #define RG_DG_MANUAL_LCH_SFT 0 |
| #define RG_DG_MANUAL_LCH_MASK 0x7 |
| #define RG_DG_MANUAL_LCH_MASK_SFT (0x7 << 0) |
| |
| /* AFE_NLE_GAIN_IMP_LCH_CFG0 */ |
| #define RG_AG_MANUAL_LCH_SFT 0 |
| #define RG_AG_MANUAL_LCH_MASK 0x7 |
| #define RG_AG_MANUAL_LCH_MASK_SFT (0x7 << 0) |
| |
| /* AFE_NLE_PWR_DET_LCH_MON_L */ |
| #define NLE_PWR_DETECT_STATUS_LCH_SFT 3 |
| #define NLE_PWR_DETECT_STATUS_LCH_MASK 0x1 |
| #define NLE_PWR_DETECT_STATUS_LCH_MASK_SFT (0x1 << 3) |
| #define PWR_DET_D_LCH_SFT 2 |
| #define PWR_DET_D_LCH_MASK 0x1 |
| #define PWR_DET_D_LCH_MASK_SFT (0x1 << 2) |
| #define PWR_DET_LCH_SFT 1 |
| #define PWR_DET_LCH_MASK 0x1 |
| #define PWR_DET_LCH_MASK_SFT (0x1 << 1) |
| #define H2L_HOLD_TIME_CNT_START_LCH_SFT 0 |
| #define H2L_HOLD_TIME_CNT_START_LCH_MASK 0x1 |
| #define H2L_HOLD_TIME_CNT_START_LCH_MASK_SFT (0x1 << 0) |
| |
| /* AFE_NLE_PWR_DET_LCH_MON */ |
| #define H2L_HOLD_TIME_CNT_LCH_SFT 0 |
| #define H2L_HOLD_TIME_CNT_LCH_MASK 0xff |
| #define H2L_HOLD_TIME_CNT_LCH_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_GAIN_ADJ_LCH_MON0_H */ |
| #define GAIN_STEP_PER_JUMP_LCH_SFT 4 |
| #define GAIN_STEP_PER_JUMP_LCH_MASK 0x7 |
| #define GAIN_STEP_PER_JUMP_LCH_MASK_SFT (0x7 << 4) |
| |
| /* AFE_NLE_GAIN_ADJ_LCH_MON0_M */ |
| #define GAIN_STEP_PER_ZCD_LCH_SFT 4 |
| #define GAIN_STEP_PER_ZCD_LCH_MASK 0x7 |
| #define GAIN_STEP_PER_ZCD_LCH_MASK_SFT (0x7 << 4) |
| |
| /* AFE_NLE_GAIN_ADJ_LCH_MON0_L */ |
| #define DG_TARGET_LCH_SFT 0 |
| #define DG_TARGET_LCH_MASK 0x7 |
| #define DG_TARGET_LCH_MASK_SFT (0x7 << 0) |
| #define DG_LCH_SFT 3 |
| #define DG_LCH_MASK 0x7 |
| #define DG_LCH_MASK_SFT (0x7 << 3) |
| |
| /* AFE_NLE_GAIN_ADJ_LCH_MON0 */ |
| #define CS_LCH_SFT 0 |
| #define CS_LCH_MASK 0xff |
| #define CS_LCH_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_GAIN_ADJ_LCH_MON1_H */ |
| #define TIME_OUT_FLAG_LCH_SFT 7 |
| #define TIME_OUT_FLAG_LCH_MASK 0x1 |
| #define TIME_OUT_FLAG_LCH_MASK_SFT (0x1 << 7) |
| #define TIME_OUT_CNT_START_LCH_SFT 6 |
| #define TIME_OUT_CNT_START_LCH_MASK 0x1 |
| #define TIME_OUT_CNT_START_LCH_MASK_SFT (0x1 << 6) |
| #define DG_MAX_LCH_SFT 0 |
| #define DG_MAX_LCH_MASK 0x7 |
| #define DG_MAX_LCH_MASK_SFT (0x7 << 0) |
| |
| /* AFE_NLE_GAIN_ADJ_LCH_MON1_M */ |
| #define HOLD_TIME_PER_JUMP_LCH_SFT 0 |
| #define HOLD_TIME_PER_JUMP_LCH_MASK 0xff |
| #define HOLD_TIME_PER_JUMP_LCH_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_GAIN_ADJ_LCH_MON1_L */ |
| #define HOLD_TIME_PER_JUMP_CNT_LCH_SFT 1 |
| #define HOLD_TIME_PER_JUMP_CNT_LCH_MASK 0x7f |
| #define HOLD_TIME_PER_JUMP_CNT_LCH_MASK_SFT (0x7f << 1) |
| #define TIME_OUT_CNT_LCH_H_SFT 0 |
| #define TIME_OUT_CNT_LCH_H_MASK 0x1 |
| #define TIME_OUT_CNT_LCH_H_MASK_SFT (0x1 << 0) |
| |
| /* AFE_NLE_GAIN_ADJ_LCH_MON1 */ |
| #define TIME_OUT_CNT_LCH_SFT 0 |
| #define TIME_OUT_CNT_LCH_MASK 0xff |
| #define TIME_OUT_CNT_LCH_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LCH_MON0_H */ |
| #define ZCD_CHECK_ON_LCH_SFT 6 |
| #define ZCD_CHECK_ON_LCH_MASK 0x1 |
| #define ZCD_CHECK_ON_LCH_MASK_SFT (0x1 << 6) |
| #define ZCD_FLAG_LCH_SFT 5 |
| #define ZCD_FLAG_LCH_MASK 0x1 |
| #define ZCD_FLAG_LCH_MASK_SFT (0x1 << 5) |
| #define NLE_STATUS_LCH_SFT 4 |
| #define NLE_STATUS_LCH_MASK 0x1 |
| #define NLE_STATUS_LCH_MASK_SFT (0x1 << 4) |
| #define DG_LCH_MON_SFT 0 |
| #define DG_LCH_MON_MASK 0x7 |
| #define DG_LCH_MON_MASK_SFT (0x7 << 0) |
| |
| /* AFE_NLE_LCH_MON0_M */ |
| #define AG_IMP_LCH_SFT 5 |
| #define AG_IMP_LCH_MASK 0x7 |
| #define AG_IMP_LCH_MASK_SFT (0x7 << 5) |
| #define DG_IMP_LCH_H_SFT 0 |
| #define DG_IMP_LCH_H_MASK 0x1f |
| #define DG_IMP_LCH_H_MASK_SFT (0x1f << 0) |
| |
| /* AFE_NLE_LCH_MON0_L */ |
| #define DG_IMP_LCH_M_SFT 0 |
| #define DG_IMP_LCH_M_MASK 0xff |
| #define DG_IMP_LCH_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LCH_MON0 */ |
| #define DG_IMP_LCH_SFT 0 |
| #define DG_IMP_LCH_MASK 0xff |
| #define DG_IMP_LCH_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_PWR_DET_RCH_CFG_H */ |
| #define RG_H2L_BYPASS_1ST_START_RCH_SFT 7 |
| #define RG_H2L_BYPASS_1ST_START_RCH_MASK 0x1 |
| #define RG_H2L_BYPASS_1ST_START_RCH_MASK_SFT (0x1 << 7) |
| #define RG_SW_DISABLE_POWER_DETECT_RCH_SFT 6 |
| #define RG_SW_DISABLE_POWER_DETECT_RCH_MASK 0x1 |
| #define RG_SW_DISABLE_POWER_DETECT_RCH_MASK_SFT (0x1 << 6) |
| #define RG_H2L_HOLD_TIME_RCH_SFT 0 |
| #define RG_H2L_HOLD_TIME_RCH_MASK 0x1f |
| #define RG_H2L_HOLD_TIME_RCH_MASK_SFT (0x1f << 0) |
| |
| /* AFE_NLE_PWR_DET_RCH_CFG_M */ |
| #define RG_NLE_VTH_RCH_H_SFT 0 |
| #define RG_NLE_VTH_RCH_H_MASK 0xff |
| #define RG_NLE_VTH_RCH_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_PWR_DET_RCH_CFG_L */ |
| #define RG_NLE_VTH_RCH_M_SFT 0 |
| #define RG_NLE_VTH_RCH_M_MASK 0xff |
| #define RG_NLE_VTH_RCH_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_PWR_DET_RCH_CFG */ |
| #define RG_NLE_VTH_RCH_SFT 0 |
| #define RG_NLE_VTH_RCH_MASK 0xff |
| #define RG_NLE_VTH_RCH_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_ZCD_RCH_CFG */ |
| #define RG_ZCD_CHECK_MODE_RCH_SFT 2 |
| #define RG_ZCD_CHECK_MODE_RCH_MASK 0x1 |
| #define RG_ZCD_CHECK_MODE_RCH_MASK_SFT (0x1 << 2) |
| #define RG_ZCD_MODE_SEL_RCH_SFT 0 |
| #define RG_ZCD_MODE_SEL_RCH_MASK 0x3 |
| #define RG_ZCD_MODE_SEL_RCH_MASK_SFT (0x3 << 0) |
| |
| /* AFE_NLE_GAIN_ADJ_RCH_CFG0_H */ |
| #define RG_GAIN_ADJ_BYPASS_ZCD_RCH_SFT 7 |
| #define RG_GAIN_ADJ_BYPASS_ZCD_RCH_MASK 0x1 |
| #define RG_GAIN_ADJ_BYPASS_ZCD_RCH_MASK_SFT (0x1 << 7) |
| #define RG_TIME_OUT_RCH_SFT 0 |
| #define RG_TIME_OUT_RCH_MASK 0x3f |
| #define RG_TIME_OUT_RCH_MASK_SFT (0x3f << 0) |
| |
| /* AFE_NLE_GAIN_ADJ_RCH_CFG0_M */ |
| #define RG_HOLD_TIME_PER_JUMP_RCH_SFT 4 |
| #define RG_HOLD_TIME_PER_JUMP_RCH_MASK 0x7 |
| #define RG_HOLD_TIME_PER_JUMP_RCH_MASK_SFT (0x7 << 4) |
| #define RG_GAIN_STEP_PER_JUMP_RCH_SFT 0 |
| #define RG_GAIN_STEP_PER_JUMP_RCH_MASK 0x3 |
| #define RG_GAIN_STEP_PER_JUMP_RCH_MASK_SFT (0x3 << 0) |
| |
| /* AFE_NLE_GAIN_ADJ_RCH_CFG0_L */ |
| #define RG_GAIN_STEP_PER_ZCD_RCH_SFT 0 |
| #define RG_GAIN_STEP_PER_ZCD_RCH_MASK 0x7 |
| #define RG_GAIN_STEP_PER_ZCD_RCH_MASK_SFT (0x7 << 0) |
| |
| /* AFE_NLE_GAIN_ADJ_RCH_CFG0 */ |
| #define RG_AG_MIN_RCH_SFT 4 |
| #define RG_AG_MIN_RCH_MASK 0x7 |
| #define RG_AG_MIN_RCH_MASK_SFT (0x7 << 4) |
| #define RG_AG_MAX_RCH_SFT 0 |
| #define RG_AG_MAX_RCH_MASK 0x7 |
| #define RG_AG_MAX_RCH_MASK_SFT (0x7 << 0) |
| |
| /* AFE_NLE_GAIN_IMP_RCH_CFG0_H */ |
| #define RG_DG_SAT_RCH_SFT 7 |
| #define RG_DG_SAT_RCH_MASK 0x1 |
| #define RG_DG_SAT_RCH_MASK_SFT (0x1 << 7) |
| #define RG_DG_OUTPUT_DEBUG_MODE_RCH_SFT 6 |
| #define RG_DG_OUTPUT_DEBUG_MODE_RCH_MASK 0x1 |
| #define RG_DG_OUTPUT_DEBUG_MODE_RCH_MASK_SFT (0x1 << 6) |
| #define RG_DG_FIX_MANUAL_MODE_RCH_SFT 5 |
| #define RG_DG_FIX_MANUAL_MODE_RCH_MASK 0x1 |
| #define RG_DG_FIX_MANUAL_MODE_RCH_MASK_SFT (0x1 << 5) |
| #define RG_AG_FIX_MANUAL_MODE_RCH_SFT 4 |
| #define RG_AG_FIX_MANUAL_MODE_RCH_MASK 0x1 |
| #define RG_AG_FIX_MANUAL_MODE_RCH_MASK_SFT (0x1 << 4) |
| #define RG_DG_DELAY_RCH_SFT 0 |
| #define RG_DG_DELAY_RCH_MASK 0x7 |
| #define RG_DG_DELAY_RCH_MASK_SFT (0x7 << 0) |
| |
| /* AFE_NLE_GAIN_IMP_RCH_CFG0_M */ |
| #define RG_AG_DELAY_RCH_SFT 0 |
| #define RG_AG_DELAY_RCH_MASK 0x3f |
| #define RG_AG_DELAY_RCH_MASK_SFT (0x3f << 0) |
| |
| /* AFE_NLE_GAIN_IMP_RCH_CFG0_L */ |
| #define RG_DG_MANUAL_RCH_SFT 0 |
| #define RG_DG_MANUAL_RCH_MASK 0x7 |
| #define RG_DG_MANUAL_RCH_MASK_SFT (0x7 << 0) |
| |
| /* AFE_NLE_GAIN_IMP_RCH_CFG0 */ |
| #define RG_AG_MANUAL_RCH_SFT 0 |
| #define RG_AG_MANUAL_RCH_MASK 0x7 |
| #define RG_AG_MANUAL_RCH_MASK_SFT (0x7 << 0) |
| |
| /* AFE_NLE_PWR_DET_RCH_MON_L */ |
| #define NLE_PWR_DETECT_STATUS_RCH_SFT 3 |
| #define NLE_PWR_DETECT_STATUS_RCH_MASK 0x1 |
| #define NLE_PWR_DETECT_STATUS_RCH_MASK_SFT (0x1 << 3) |
| #define PWR_DET_D_RCH_SFT 2 |
| #define PWR_DET_D_RCH_MASK 0x1 |
| #define PWR_DET_D_RCH_MASK_SFT (0x1 << 2) |
| #define PWR_DET_RCH_SFT 1 |
| #define PWR_DET_RCH_MASK 0x1 |
| #define PWR_DET_RCH_MASK_SFT (0x1 << 1) |
| #define H2L_HOLD_TIME_CNT_START_RCH_SFT 0 |
| #define H2L_HOLD_TIME_CNT_START_RCH_MASK 0x1 |
| #define H2L_HOLD_TIME_CNT_START_RCH_MASK_SFT (0x1 << 0) |
| |
| /* AFE_NLE_PWR_DET_RCH_MON */ |
| #define H2L_HOLD_TIME_CNT_RCH_SFT 0 |
| #define H2L_HOLD_TIME_CNT_RCH_MASK 0xff |
| #define H2L_HOLD_TIME_CNT_RCH_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_GAIN_ADJ_RCH_MON0_H */ |
| #define GAIN_STEP_PER_JUMP_RCH_SFT 4 |
| #define GAIN_STEP_PER_JUMP_RCH_MASK 0x7 |
| #define GAIN_STEP_PER_JUMP_RCH_MASK_SFT (0x7 << 4) |
| |
| /* AFE_NLE_GAIN_ADJ_RCH_MON0_M */ |
| #define GAIN_STEP_PER_ZCD_RCH_SFT 4 |
| #define GAIN_STEP_PER_ZCD_RCH_MASK 0x7 |
| #define GAIN_STEP_PER_ZCD_RCH_MASK_SFT (0x7 << 4) |
| |
| /* AFE_NLE_GAIN_ADJ_RCH_MON0_L */ |
| #define DG_TARGET_RCH_SFT 4 |
| #define DG_TARGET_RCH_MASK 0x7 |
| #define DG_TARGET_RCH_MASK_SFT (0x7 << 4) |
| #define DG_RCH_SFT 0 |
| #define DG_RCH_MASK 0x7 |
| #define DG_RCH_MASK_SFT (0x7 << 0) |
| |
| /* AFE_NLE_GAIN_ADJ_RCH_MON0 */ |
| #define CS_RCH_SFT 0 |
| #define CS_RCH_MASK 0xff |
| #define CS_RCH_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_GAIN_ADJ_RCH_MON1_H */ |
| #define TIME_OUT_FLAG_RCH_SFT 7 |
| #define TIME_OUT_FLAG_RCH_MASK 0x1 |
| #define TIME_OUT_FLAG_RCH_MASK_SFT (0x1 << 7) |
| #define TIME_OUT_CNT_START_RCH_SFT 6 |
| #define TIME_OUT_CNT_START_RCH_MASK 0x1 |
| #define TIME_OUT_CNT_START_RCH_MASK_SFT (0x1 << 6) |
| #define DG_MAX_RCH_SFT 0 |
| #define DG_MAX_RCH_MASK 0x7 |
| #define DG_MAX_RCH_MASK_SFT (0x7 << 0) |
| |
| /* AFE_NLE_GAIN_ADJ_RCH_MON1_M */ |
| #define HOLD_TIME_PER_JUMP_RCH_SFT 0 |
| #define HOLD_TIME_PER_JUMP_RCH_MASK 0xff |
| #define HOLD_TIME_PER_JUMP_RCH_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_GAIN_ADJ_RCH_MON1_L */ |
| #define HOLD_TIME_PER_JUMP_CNT_RCH_SFT 1 |
| #define HOLD_TIME_PER_JUMP_CNT_RCH_MASK 0x7f |
| #define HOLD_TIME_PER_JUMP_CNT_RCH_MASK_SFT (0x7f << 1) |
| #define TIME_OUT_CNT_RCH_H_SFT 0 |
| #define TIME_OUT_CNT_RCH_H_MASK 0x1 |
| #define TIME_OUT_CNT_RCH_H_MASK_SFT (0x1 << 0) |
| |
| /* AFE_NLE_GAIN_ADJ_RCH_MON1 */ |
| #define TIME_OUT_CNT_RCH_SFT 0 |
| #define TIME_OUT_CNT_RCH_MASK 0xff |
| #define TIME_OUT_CNT_RCH_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_RCH_MON0_H */ |
| #define ZCD_CHECK_ON_RCH_SFT 6 |
| #define ZCD_CHECK_ON_RCH_MASK 0x1 |
| #define ZCD_CHECK_ON_RCH_MASK_SFT (0x1 << 6) |
| #define ZCD_FLAG_RCH_SFT 5 |
| #define ZCD_FLAG_RCH_MASK 0x1 |
| #define ZCD_FLAG_RCH_MASK_SFT (0x1 << 5) |
| #define NLE_STATUS_RCH_SFT 4 |
| #define NLE_STATUS_RCH_MASK 0x1 |
| #define NLE_STATUS_RCH_MASK_SFT (0x1 << 4) |
| #define DG_RCH_MON_SFT 0 |
| #define DG_RCH_MON_MASK 0x7 |
| #define DG_RCH_MON_MASK_SFT (0x7 << 0) |
| |
| /* AFE_NLE_RCH_MON0_M */ |
| #define AG_IMP_RCH_SFT 5 |
| #define AG_IMP_RCH_MASK 0x7 |
| #define AG_IMP_RCH_MASK_SFT (0x7 << 5) |
| #define DG_IMP_RCH_H_SFT 0 |
| #define DG_IMP_RCH_H_MASK 0x1f |
| #define DG_IMP_RCH_H_MASK_SFT (0x1f << 0) |
| |
| /* AFE_NLE_RCH_MON0_L */ |
| #define DG_IMP_RCH_M_SFT 0 |
| #define DG_IMP_RCH_M_MASK 0xff |
| #define DG_IMP_RCH_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_RCH_MON0 */ |
| #define DG_IMP_RCH_SFT 0 |
| #define DG_IMP_RCH_MASK 0xff |
| #define DG_IMP_RCH_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G0_H */ |
| #define RG_DG_STEP_LCH_SW_CONFIG_MODE_SFT 7 |
| #define RG_DG_STEP_LCH_SW_CONFIG_MODE_MASK 0x1 |
| #define RG_DG_STEP_LCH_SW_CONFIG_MODE_MASK_SFT (0x1 << 7) |
| #define RG_DG_LNGAIN_COMP_LCH_G0_H_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G0_H_MASK 0x3 |
| #define RG_DG_LNGAIN_COMP_LCH_G0_H_MASK_SFT (0x3 << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G0_M */ |
| #define RG_DG_LNGAIN_COMP_LCH_G0_M_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G0_M_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_LCH_G0_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G0_L */ |
| #define RG_DG_LNGAIN_COMP_LCH_G0_L_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G0_L_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_LCH_G0_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G0 */ |
| #define RG_DG_LNGAIN_COMP_LCH_G0_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G0_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_LCH_G0_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G1_H */ |
| #define RG_DG_LNGAIN_COMP_LCH_G1_H_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G1_H_MASK 0x3 |
| #define RG_DG_LNGAIN_COMP_LCH_G1_H_MASK_SFT (0x3 << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G1_M */ |
| #define RG_DG_LNGAIN_COMP_LCH_G1_M_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G1_M_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_LCH_G1_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G1_L */ |
| #define RG_DG_LNGAIN_COMP_LCH_G1_L_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G1_L_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_LCH_G1_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G1 */ |
| #define RG_DG_LNGAIN_COMP_LCH_G1_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G1_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_LCH_G1_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G2_H */ |
| #define RG_DG_LNGAIN_COMP_LCH_G2_H_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G2_H_MASK 0x3 |
| #define RG_DG_LNGAIN_COMP_LCH_G2_H_MASK_SFT (0x3 << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G2_M */ |
| #define RG_DG_LNGAIN_COMP_LCH_G2_M_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G2_M_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_LCH_G2_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G2_L */ |
| #define RG_DG_LNGAIN_COMP_LCH_G2_L_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G2_L_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_LCH_G2_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G2 */ |
| #define RG_DG_LNGAIN_COMP_LCH_G2_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G2_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_LCH_G2_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G3_H */ |
| #define RG_DG_LNGAIN_COMP_LCH_G3_H_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G3_H_MASK 0x3 |
| #define RG_DG_LNGAIN_COMP_LCH_G3_H_MASK_SFT (0x3 << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G3_M */ |
| #define RG_DG_LNGAIN_COMP_LCH_G3_M_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G3_M_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_LCH_G3_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G3_L */ |
| #define RG_DG_LNGAIN_COMP_LCH_G3_L_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G3_L_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_LCH_G3_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G3 */ |
| #define RG_DG_LNGAIN_COMP_LCH_G3_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G3_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_LCH_G3_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G4_H */ |
| #define RG_DG_LNGAIN_COMP_LCH_G4_H_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G4_H_MASK 0x3 |
| #define RG_DG_LNGAIN_COMP_LCH_G4_H_MASK_SFT (0x3 << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G4_M */ |
| #define RG_DG_LNGAIN_COMP_LCH_G4_M_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G4_M_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_LCH_G4_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G4_L */ |
| #define RG_DG_LNGAIN_COMP_LCH_G4_L_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G4_L_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_LCH_G4_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G4 */ |
| #define RG_DG_LNGAIN_COMP_LCH_G4_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G4_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_LCH_G4_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G5_H */ |
| #define RG_DG_LNGAIN_COMP_LCH_G5_H_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G5_H_MASK 0x3 |
| #define RG_DG_LNGAIN_COMP_LCH_G5_H_MASK_SFT (0x3 << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G5_M */ |
| #define RG_DG_LNGAIN_COMP_LCH_G5_M_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G5_M_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_LCH_G5_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G5_L */ |
| #define RG_DG_LNGAIN_COMP_LCH_G5_L_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G5_L_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_LCH_G5_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G5 */ |
| #define RG_DG_LNGAIN_COMP_LCH_G5_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G5_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_LCH_G5_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G6_H */ |
| #define RG_DG_LNGAIN_COMP_LCH_G6_H_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G6_H_MASK 0x3 |
| #define RG_DG_LNGAIN_COMP_LCH_G6_H_MASK_SFT (0x3 << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G6_M */ |
| #define RG_DG_LNGAIN_COMP_LCH_G6_M_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G6_M_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_LCH_G6_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G6_L */ |
| #define RG_DG_LNGAIN_COMP_LCH_G6_L_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G6_L_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_LCH_G6_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G6 */ |
| #define RG_DG_LNGAIN_COMP_LCH_G6_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G6_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_LCH_G6_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G7_H */ |
| #define RG_DG_LNGAIN_COMP_LCH_G7_H_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G7_H_MASK 0x3 |
| #define RG_DG_LNGAIN_COMP_LCH_G7_H_MASK_SFT (0x3 << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G7_M */ |
| #define RG_DG_LNGAIN_COMP_LCH_G7_M_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G7_M_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_LCH_G7_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G7_L */ |
| #define RG_DG_LNGAIN_COMP_LCH_G7_L_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G7_L_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_LCH_G7_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_LCH_G7 */ |
| #define RG_DG_LNGAIN_COMP_LCH_G7_SFT 0 |
| #define RG_DG_LNGAIN_COMP_LCH_G7_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_LCH_G7_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G0_H */ |
| #define RG_DG_STEP_RCH_SW_CONFIG_MODE_SFT 7 |
| #define RG_DG_STEP_RCH_SW_CONFIG_MODE_MASK 0x1 |
| #define RG_DG_STEP_RCH_SW_CONFIG_MODE_MASK_SFT (0x1 << 7) |
| #define RG_DG_LNGAIN_COMP_RCH_G0_H_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G0_H_MASK 0x3 |
| #define RG_DG_LNGAIN_COMP_RCH_G0_H_MASK_SFT (0x3 << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G0_M */ |
| #define RG_DG_LNGAIN_COMP_RCH_G0_M_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G0_M_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_RCH_G0_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G0_L */ |
| #define RG_DG_LNGAIN_COMP_RCH_G0_L_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G0_L_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_RCH_G0_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G0 */ |
| #define RG_DG_LNGAIN_COMP_RCH_G0_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G0_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_RCH_G0_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G1_H */ |
| #define RG_DG_LNGAIN_COMP_RCH_G1_H_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G1_H_MASK 0x3 |
| #define RG_DG_LNGAIN_COMP_RCH_G1_H_MASK_SFT (0x3 << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G1_M */ |
| #define RG_DG_LNGAIN_COMP_RCH_G1_M_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G1_M_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_RCH_G1_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G1_L */ |
| #define RG_DG_LNGAIN_COMP_RCH_G1_L_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G1_L_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_RCH_G1_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G1 */ |
| #define RG_DG_LNGAIN_COMP_RCH_G1_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G1_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_RCH_G1_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G2_H */ |
| #define RG_DG_LNGAIN_COMP_RCH_G2_H_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G2_H_MASK 0x3 |
| #define RG_DG_LNGAIN_COMP_RCH_G2_H_MASK_SFT (0x3 << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G2_M */ |
| #define RG_DG_LNGAIN_COMP_RCH_G2_M_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G2_M_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_RCH_G2_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G2_L */ |
| #define RG_DG_LNGAIN_COMP_RCH_G2_L_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G2_L_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_RCH_G2_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G2 */ |
| #define RG_DG_LNGAIN_COMP_RCH_G2_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G2_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_RCH_G2_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G3_H */ |
| #define RG_DG_LNGAIN_COMP_RCH_G3_H_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G3_H_MASK 0x3 |
| #define RG_DG_LNGAIN_COMP_RCH_G3_H_MASK_SFT (0x3 << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G3_M */ |
| #define RG_DG_LNGAIN_COMP_RCH_G3_M_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G3_M_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_RCH_G3_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G3_L */ |
| #define RG_DG_LNGAIN_COMP_RCH_G3_L_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G3_L_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_RCH_G3_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G3 */ |
| #define RG_DG_LNGAIN_COMP_RCH_G3_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G3_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_RCH_G3_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G4_H */ |
| #define RG_DG_LNGAIN_COMP_RCH_G4_H_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G4_H_MASK 0x3 |
| #define RG_DG_LNGAIN_COMP_RCH_G4_H_MASK_SFT (0x3 << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G4_M */ |
| #define RG_DG_LNGAIN_COMP_RCH_G4_M_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G4_M_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_RCH_G4_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G4_L */ |
| #define RG_DG_LNGAIN_COMP_RCH_G4_L_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G4_L_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_RCH_G4_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G4 */ |
| #define RG_DG_LNGAIN_COMP_RCH_G4_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G4_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_RCH_G4_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G5_H */ |
| #define RG_DG_LNGAIN_COMP_RCH_G5_H_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G5_H_MASK 0x3 |
| #define RG_DG_LNGAIN_COMP_RCH_G5_H_MASK_SFT (0x3 << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G5_M */ |
| #define RG_DG_LNGAIN_COMP_RCH_G5_M_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G5_M_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_RCH_G5_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G5_L */ |
| #define RG_DG_LNGAIN_COMP_RCH_G5_L_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G5_L_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_RCH_G5_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G5 */ |
| #define RG_DG_LNGAIN_COMP_RCH_G5_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G5_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_RCH_G5_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G6_H */ |
| #define RG_DG_LNGAIN_COMP_RCH_G6_H_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G6_H_MASK 0x3 |
| #define RG_DG_LNGAIN_COMP_RCH_G6_H_MASK_SFT (0x3 << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G6_M */ |
| #define RG_DG_LNGAIN_COMP_RCH_G6_M_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G6_M_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_RCH_G6_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G6_L */ |
| #define RG_DG_LNGAIN_COMP_RCH_G6_L_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G6_L_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_RCH_G6_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G6 */ |
| #define RG_DG_LNGAIN_COMP_RCH_G6_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G6_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_RCH_G6_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_9TH_DSN_ID */ |
| #define AUDIO_DIG_9TH_ANA_ID_SFT 0 |
| #define AUDIO_DIG_9TH_ANA_ID_MASK 0xff |
| #define AUDIO_DIG_9TH_ANA_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_9TH_DSN_ID_H */ |
| #define AUDIO_DIG_9TH_DIG_ID_SFT 0 |
| #define AUDIO_DIG_9TH_DIG_ID_MASK 0xff |
| #define AUDIO_DIG_9TH_DIG_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_9TH_DSN_REV0 */ |
| #define AUDIO_DIG_9TH_ANA_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_9TH_ANA_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_9TH_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_9TH_ANA_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_9TH_ANA_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_9TH_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_9TH_DSN_REV0_H */ |
| #define AUDIO_DIG_9TH_DIG_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_9TH_DIG_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_9TH_DIG_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_9TH_DIG_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_9TH_DIG_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_9TH_DIG_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_9TH_DSN_DBI */ |
| #define AUDIO_DIG_9TH_DSN_CBS_SFT 0 |
| #define AUDIO_DIG_9TH_DSN_CBS_MASK 0x3 |
| #define AUDIO_DIG_9TH_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDIO_DIG_9TH_DSN_BIX_SFT 2 |
| #define AUDIO_DIG_9TH_DSN_BIX_MASK 0x3 |
| #define AUDIO_DIG_9TH_DSN_BIX_MASK_SFT (0x3 << 2) |
| |
| /* AUDIO_DIG_9TH_DSN_DBI_H */ |
| #define AUDIO_DIG_9_ESP_SFT 0 |
| #define AUDIO_DIG_9_ESP_MASK 0xff |
| #define AUDIO_DIG_9_ESP_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_9TH_DSN_DXI */ |
| #define AUDIO_DIG_9TH_DSN_FPI_SFT 0 |
| #define AUDIO_DIG_9TH_DSN_FPI_MASK 0xff |
| #define AUDIO_DIG_9TH_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SRC_CON0_H */ |
| #define AFE_2ND_DL_INPUT_MODE_CTL_SFT 4 |
| #define AFE_2ND_DL_INPUT_MODE_CTL_MASK 0xf |
| #define AFE_2ND_DL_INPUT_MODE_CTL_MASK_SFT (0xf << 4) |
| #define AFE_2ND_DL_CH1_SATURATION_EN_CTL_SFT 3 |
| #define AFE_2ND_DL_CH1_SATURATION_EN_CTL_MASK 0x1 |
| #define AFE_2ND_DL_CH1_SATURATION_EN_CTL_MASK_SFT (0x1 << 3) |
| #define AFE_2ND_DL_CH2_SATURATION_EN_CTL_SFT 2 |
| #define AFE_2ND_DL_CH2_SATURATION_EN_CTL_MASK 0x1 |
| #define AFE_2ND_DL_CH2_SATURATION_EN_CTL_MASK_SFT (0x1 << 2) |
| #define AFE_2ND_DL_OUTPUT_SEL_CTL_SFT 0 |
| #define AFE_2ND_DL_OUTPUT_SEL_CTL_MASK 0x3 |
| #define AFE_2ND_DL_OUTPUT_SEL_CTL_MASK_SFT (0x3 << 0) |
| |
| /* AFE_ADDA_2ND_DL_SRC_CON0_M */ |
| #define AFE_2ND_DL_FADEIN_0START_EN_SFT 0 |
| #define AFE_2ND_DL_FADEIN_0START_EN_MASK 0x3 |
| #define AFE_2ND_DL_FADEIN_0START_EN_MASK_SFT (0x3 << 0) |
| |
| /* AFE_ADDA_2ND_DL_SRC_CON0_L */ |
| #define AFE_2ND_DL_DL_DISABLE_HW_CG_CTL_SFT 7 |
| #define AFE_2ND_DL_DL_DISABLE_HW_CG_CTL_MASK 0x1 |
| #define AFE_2ND_DL_DL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 7) |
| #define AFE_2ND_DL_C_DATA_EN_SEL_CTL_PRE_SFT 6 |
| #define AFE_2ND_DL_C_DATA_EN_SEL_CTL_PRE_MASK 0x1 |
| #define AFE_2ND_DL_C_DATA_EN_SEL_CTL_PRE_MASK_SFT (0x1 << 6) |
| #define AFE_2ND_DL_MUTE_CH1_OFF_CTL_PRE_SFT 4 |
| #define AFE_2ND_DL_MUTE_CH1_OFF_CTL_PRE_MASK 0x1 |
| #define AFE_2ND_DL_MUTE_CH1_OFF_CTL_PRE_MASK_SFT (0x1 << 4) |
| #define AFE_2ND_DL_MUTE_CH2_OFF_CTL_PRE_SFT 3 |
| #define AFE_2ND_DL_MUTE_CH2_OFF_CTL_PRE_MASK 0x1 |
| #define AFE_2ND_DL_MUTE_CH2_OFF_CTL_PRE_MASK_SFT (0x1 << 3) |
| #define AFE_2ND_DL_ARAMPSP_CTL_PRE_SFT 1 |
| #define AFE_2ND_DL_ARAMPSP_CTL_PRE_MASK 0x3 |
| #define AFE_2ND_DL_ARAMPSP_CTL_PRE_MASK_SFT (0x3 << 1) |
| |
| /* AFE_ADDA_2ND_DL_SRC_CON0 */ |
| #define AFE_2ND_DL_VOICE_MODE_CTL_PRE_SFT 5 |
| #define AFE_2ND_DL_VOICE_MODE_CTL_PRE_MASK 0x1 |
| #define AFE_2ND_DL_VOICE_MODE_CTL_PRE_MASK_SFT (0x1 << 5) |
| #define AFE_2ND_DL_MUTE_CH1_ON_CTL_PRE_SFT 4 |
| #define AFE_2ND_DL_MUTE_CH1_ON_CTL_PRE_MASK 0x1 |
| #define AFE_2ND_DL_MUTE_CH1_ON_CTL_PRE_MASK_SFT (0x1 << 4) |
| #define AFE_2ND_DL_MUTE_CH2_ON_CTL_PRE_SFT 3 |
| #define AFE_2ND_DL_MUTE_CH2_ON_CTL_PRE_MASK 0x1 |
| #define AFE_2ND_DL_MUTE_CH2_ON_CTL_PRE_MASK_SFT (0x1 << 3) |
| #define AFE_2ND_DL_GAIN_ON_CTL_PRE_SFT 1 |
| #define AFE_2ND_DL_GAIN_ON_CTL_PRE_MASK 0x1 |
| #define AFE_2ND_DL_GAIN_ON_CTL_PRE_MASK_SFT (0x1 << 1) |
| #define AFE_2ND_DL_SRC_ON_TMP_CTL_PRE_SFT 0 |
| #define AFE_2ND_DL_SRC_ON_TMP_CTL_PRE_MASK 0x1 |
| #define AFE_2ND_DL_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0) |
| |
| /* AFE_ADDA_2ND_DL_SRC_CON1_H */ |
| #define AFE_2ND_DL_GAIN_CTL_PRE_H_SFT 0 |
| #define AFE_2ND_DL_GAIN_CTL_PRE_H_MASK 0xff |
| #define AFE_2ND_DL_GAIN_CTL_PRE_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SRC_CON1_M */ |
| #define AFE_2ND_DL_GAIN_CTL_PRE_SFT 0 |
| #define AFE_2ND_DL_GAIN_CTL_PRE_MASK 0xff |
| #define AFE_2ND_DL_GAIN_CTL_PRE_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SRC_CON1 */ |
| #define AFE_2ND_DL_GAIN_MODE_CTL_SFT 0 |
| #define AFE_2ND_DL_GAIN_MODE_CTL_MASK 0x1 |
| #define AFE_2ND_DL_GAIN_MODE_CTL_MASK_SFT (0x1 << 0) |
| |
| /* AFE_ADDA_2ND_DL_SRC_DEBUG_MON0_L */ |
| #define AFE_2ND_DL_SLT_CNT_FLAG_CTL_SFT 7 |
| #define AFE_2ND_DL_SLT_CNT_FLAG_CTL_MASK 0x1 |
| #define AFE_2ND_DL_SLT_CNT_FLAG_CTL_MASK_SFT (0x1 << 7) |
| #define AFE_2ND_DL_INI_SRAM_FINISH_CTL_SFT 4 |
| #define AFE_2ND_DL_INI_SRAM_FINISH_CTL_MASK 0x1 |
| #define AFE_2ND_DL_INI_SRAM_FINISH_CTL_MASK_SFT (0x1 << 4) |
| #define AFE_2ND_DL_SLT_COUNTER_CTL_H_SFT 0 |
| #define AFE_2ND_DL_SLT_COUNTER_CTL_H_MASK 0xf |
| #define AFE_2ND_DL_SLT_COUNTER_CTL_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_ADDA_2ND_DL_SRC_DEBUG_MON0 */ |
| #define AFE_2ND_DL_SLT_COUNTER_CTL_SFT 0 |
| #define AFE_2ND_DL_SLT_COUNTER_CTL_MASK 0xff |
| #define AFE_2ND_DL_SLT_COUNTER_CTL_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_PREDIS_CON0_H */ |
| #define AFE_2ND_DL_PREDIS_ON_CH1_CTL_SFT 7 |
| #define AFE_2ND_DL_PREDIS_ON_CH1_CTL_MASK 0x1 |
| #define AFE_2ND_DL_PREDIS_ON_CH1_CTL_MASK_SFT (0x1 << 7) |
| #define AFE_2ND_DL_PREDIS_A2_CH1_CTL_H_SFT 0 |
| #define AFE_2ND_DL_PREDIS_A2_CH1_CTL_H_MASK 0xf |
| #define AFE_2ND_DL_PREDIS_A2_CH1_CTL_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_ADDA_2ND_DL_PREDIS_CON0_M */ |
| #define AFE_2ND_DL_PREDIS_A2_CH1_CTL_SFT 0 |
| #define AFE_2ND_DL_PREDIS_A2_CH1_CTL_MASK 0xff |
| #define AFE_2ND_DL_PREDIS_A2_CH1_CTL_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_PREDIS_CON0_L */ |
| #define AFE_2ND_DL_PREDIS_A3_CH1_CTL_H_SFT 0 |
| #define AFE_2ND_DL_PREDIS_A3_CH1_CTL_H_MASK 0xf |
| #define AFE_2ND_DL_PREDIS_A3_CH1_CTL_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_ADDA_2ND_DL_PREDIS_CON0 */ |
| #define AFE_2ND_DL_PREDIS_A3_CH1_CTL_SFT 0 |
| #define AFE_2ND_DL_PREDIS_A3_CH1_CTL_MASK 0xff |
| #define AFE_2ND_DL_PREDIS_A3_CH1_CTL_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_PREDIS_CON1_H */ |
| #define AFE_2ND_DL_PREDIS_ON_CH2_CTL_SFT 7 |
| #define AFE_2ND_DL_PREDIS_ON_CH2_CTL_MASK 0x1 |
| #define AFE_2ND_DL_PREDIS_ON_CH2_CTL_MASK_SFT (0x1 << 7) |
| #define AFE_2ND_DL_PREDIS_A2_CH2_CTL_H_SFT 0 |
| #define AFE_2ND_DL_PREDIS_A2_CH2_CTL_H_MASK 0xf |
| #define AFE_2ND_DL_PREDIS_A2_CH2_CTL_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_ADDA_2ND_DL_PREDIS_CON1_M */ |
| #define AFE_2ND_DL_PREDIS_A2_CH2_CTL_SFT 0 |
| #define AFE_2ND_DL_PREDIS_A2_CH2_CTL_MASK 0xff |
| #define AFE_2ND_DL_PREDIS_A2_CH2_CTL_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_PREDIS_CON1_L */ |
| #define AFE_2ND_DL_PREDIS_A3_CH2_CTL_H_SFT 0 |
| #define AFE_2ND_DL_PREDIS_A3_CH2_CTL_H_MASK 0xf |
| #define AFE_2ND_DL_PREDIS_A3_CH2_CTL_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_ADDA_2ND_DL_PREDIS_CON1 */ |
| #define AFE_2ND_DL_PREDIS_A3_CH2_CTL_SFT 0 |
| #define AFE_2ND_DL_PREDIS_A3_CH2_CTL_MASK 0xff |
| #define AFE_2ND_DL_PREDIS_A3_CH2_CTL_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_PREDIS_CON2_H */ |
| #define AFE_2ND_DL_PREDIS_A4_CH1_CTL_H_SFT 0 |
| #define AFE_2ND_DL_PREDIS_A4_CH1_CTL_H_MASK 0xf |
| #define AFE_2ND_DL_PREDIS_A4_CH1_CTL_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_ADDA_2ND_DL_PREDIS_CON2_M */ |
| #define AFE_2ND_DL_PREDIS_A4_CH1_CTL_SFT 0 |
| #define AFE_2ND_DL_PREDIS_A4_CH1_CTL_MASK 0xff |
| #define AFE_2ND_DL_PREDIS_A4_CH1_CTL_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_PREDIS_CON2_L */ |
| #define AFE_2ND_DL_PREDIS_A5_CH1_CTL_H_SFT 0 |
| #define AFE_2ND_DL_PREDIS_A5_CH1_CTL_H_MASK 0xf |
| #define AFE_2ND_DL_PREDIS_A5_CH1_CTL_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_ADDA_2ND_DL_PREDIS_CON2 */ |
| #define AFE_2ND_DL_PREDIS_A5_CH1_CTL_SFT 0 |
| #define AFE_2ND_DL_PREDIS_A5_CH1_CTL_MASK 0xff |
| #define AFE_2ND_DL_PREDIS_A5_CH1_CTL_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_PREDIS_CON3_H */ |
| #define AFE_2ND_DL_PREDIS_A4_CH2_CTL_H_SFT 0 |
| #define AFE_2ND_DL_PREDIS_A4_CH2_CTL_H_MASK 0xf |
| #define AFE_2ND_DL_PREDIS_A4_CH2_CTL_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_ADDA_2ND_DL_PREDIS_CON3_M */ |
| #define AFE_2ND_DL_PREDIS_A4_CH2_CTL_SFT 0 |
| #define AFE_2ND_DL_PREDIS_A4_CH2_CTL_MASK 0xff |
| #define AFE_2ND_DL_PREDIS_A4_CH2_CTL_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_PREDIS_CON3_L */ |
| #define AFE_2ND_DL_PREDIS_A5_CH2_CTL_H_SFT 0 |
| #define AFE_2ND_DL_PREDIS_A5_CH2_CTL_H_MASK 0xf |
| #define AFE_2ND_DL_PREDIS_A5_CH2_CTL_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_ADDA_2ND_DL_PREDIS_CON3 */ |
| #define AFE_2ND_DL_PREDIS_A5_CH2_CTL_SFT 0 |
| #define AFE_2ND_DL_PREDIS_A5_CH2_CTL_MASK 0xff |
| #define AFE_2ND_DL_PREDIS_A5_CH2_CTL_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SDM_DCCOMP_CON_H */ |
| #define AFE_2ND_DL_USE_NEW_2ND_12BIT_SDM_SFT 7 |
| #define AFE_2ND_DL_USE_NEW_2ND_12BIT_SDM_MASK 0x1 |
| #define AFE_2ND_DL_USE_NEW_2ND_12BIT_SDM_MASK_SFT (0x1 << 7) |
| #define AFE_2ND_DL_USE_NEW_2ND_SDM_SFT 6 |
| #define AFE_2ND_DL_USE_NEW_2ND_SDM_MASK 0x1 |
| #define AFE_2ND_DL_USE_NEW_2ND_SDM_MASK_SFT (0x1 << 6) |
| #define AFE_2ND_DL_USE_3RD_SDM_SFT 4 |
| #define AFE_2ND_DL_USE_3RD_SDM_MASK 0x1 |
| #define AFE_2ND_DL_USE_3RD_SDM_MASK_SFT (0x1 << 4) |
| |
| /* AFE_ADDA_2ND_DL_SDM_DCCOMP_CON_L */ |
| #define AFE_2ND_DL_DL_DCM_AUTO_IDLE_EN_SFT 6 |
| #define AFE_2ND_DL_DL_DCM_AUTO_IDLE_EN_MASK 0x1 |
| #define AFE_2ND_DL_DL_DCM_AUTO_IDLE_EN_MASK_SFT (0x1 << 6) |
| #define AFE_2ND_DL_AFE_DL_SRC_DCM_EN_SFT 5 |
| #define AFE_2ND_DL_AFE_DL_SRC_DCM_EN_MASK 0x1 |
| #define AFE_2ND_DL_AFE_DL_SRC_DCM_EN_MASK_SFT (0x1 << 5) |
| #define AFE_2ND_DL_AFE_DL_POST_SRC_DCM_EN_SFT 4 |
| #define AFE_2ND_DL_AFE_DL_POST_SRC_DCM_EN_MASK 0x1 |
| #define AFE_2ND_DL_AFE_DL_POST_SRC_DCM_EN_MASK_SFT (0x1 << 4) |
| #define AFE_2ND_DL_AUD_SDM_MONO_SFT 1 |
| #define AFE_2ND_DL_AUD_SDM_MONO_MASK 0x1 |
| #define AFE_2ND_DL_AUD_SDM_MONO_MASK_SFT (0x1 << 1) |
| #define AFE_2ND_DL_AUD_DC_COMP_EN_SFT 0 |
| #define AFE_2ND_DL_AUD_DC_COMP_EN_MASK 0x1 |
| #define AFE_2ND_DL_AUD_DC_COMP_EN_MASK_SFT (0x1 << 0) |
| |
| /* AFE_ADDA_2ND_DL_SDM_DCCOMP_CON */ |
| #define AFE_2ND_DL_ATTGAIN_CTL_SFT 0 |
| #define AFE_2ND_DL_ATTGAIN_CTL_MASK 0x3f |
| #define AFE_2ND_DL_ATTGAIN_CTL_MASK_SFT (0x3f << 0) |
| |
| /* AFE_ADDA_2ND_DL_SDM_TEST_L */ |
| #define AFE_2ND_DL_TRI_AMP_DIV_SFT 4 |
| #define AFE_2ND_DL_TRI_AMP_DIV_MASK 0x7 |
| #define AFE_2ND_DL_TRI_AMP_DIV_MASK_SFT (0x7 << 4) |
| #define AFE_2ND_DL_TRI_FREQ_DIV_H_SFT 0 |
| #define AFE_2ND_DL_TRI_FREQ_DIV_H_MASK 0x3 |
| #define AFE_2ND_DL_TRI_FREQ_DIV_H_MASK_SFT (0x3 << 0) |
| |
| /* AFE_ADDA_2ND_DL_SDM_TEST */ |
| #define AFE_2ND_DL_TRI_FREQ_DIV_SFT 4 |
| #define AFE_2ND_DL_TRI_FREQ_DIV_MASK 0xf |
| #define AFE_2ND_DL_TRI_FREQ_DIV_MASK_SFT (0xf << 4) |
| #define AFE_2ND_DL_RG_DL_LEFT_SAT_RSTN_SFT 3 |
| #define AFE_2ND_DL_RG_DL_LEFT_SAT_RSTN_MASK 0x1 |
| #define AFE_2ND_DL_RG_DL_LEFT_SAT_RSTN_MASK_SFT (0x1 << 3) |
| #define AFE_2ND_DL_RG_DL_RIGHT_SAT_RSTN_SFT 2 |
| #define AFE_2ND_DL_RG_DL_RIGHT_SAT_RSTN_MASK 0x1 |
| #define AFE_2ND_DL_RG_DL_RIGHT_SAT_RSTN_MASK_SFT (0x1 << 2) |
| #define AFE_2ND_DL_TRI_MUTE_SW_SFT 1 |
| #define AFE_2ND_DL_TRI_MUTE_SW_MASK 0x1 |
| #define AFE_2ND_DL_TRI_MUTE_SW_MASK_SFT (0x1 << 1) |
| #define AFE_2ND_DL_TRI_DAC_EN_SFT 0 |
| #define AFE_2ND_DL_TRI_DAC_EN_MASK 0x1 |
| #define AFE_2ND_DL_TRI_DAC_EN_MASK_SFT (0x1 << 0) |
| |
| /* AFE_ADDA_2ND_DL_DC_COMP_CFG0_H */ |
| #define AFE_2ND_DL_AUD_DC_COMP_LCH_H_H_SFT 0 |
| #define AFE_2ND_DL_AUD_DC_COMP_LCH_H_H_MASK 0xff |
| #define AFE_2ND_DL_AUD_DC_COMP_LCH_H_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_DC_COMP_CFG0_M */ |
| #define AFE_2ND_DL_AUD_DC_COMP_LCH_H_SFT 0 |
| #define AFE_2ND_DL_AUD_DC_COMP_LCH_H_MASK 0xff |
| #define AFE_2ND_DL_AUD_DC_COMP_LCH_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_DC_COMP_CFG0_L */ |
| #define AFE_2ND_DL_AUD_DC_COMP_LCH_L_H_SFT 0 |
| #define AFE_2ND_DL_AUD_DC_COMP_LCH_L_H_MASK 0xff |
| #define AFE_2ND_DL_AUD_DC_COMP_LCH_L_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_DC_COMP_CFG0 */ |
| #define AFE_2ND_DL_AUD_DC_COMP_LCH_L_SFT 0 |
| #define AFE_2ND_DL_AUD_DC_COMP_LCH_L_MASK 0xff |
| #define AFE_2ND_DL_AUD_DC_COMP_LCH_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_DC_COMP_CFG1_H */ |
| #define AFE_2ND_DL_AUD_DC_COMP_RCH_H_H_SFT 0 |
| #define AFE_2ND_DL_AUD_DC_COMP_RCH_H_H_MASK 0xff |
| #define AFE_2ND_DL_AUD_DC_COMP_RCH_H_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_DC_COMP_CFG1_M */ |
| #define AFE_2ND_DL_AUD_DC_COMP_RCH_H_SFT 0 |
| #define AFE_2ND_DL_AUD_DC_COMP_RCH_H_MASK 0xff |
| #define AFE_2ND_DL_AUD_DC_COMP_RCH_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_DC_COMP_CFG1_L */ |
| #define AFE_2ND_DL_AUD_DC_COMP_RCH_L_H_SFT 0 |
| #define AFE_2ND_DL_AUD_DC_COMP_RCH_L_H_MASK 0xff |
| #define AFE_2ND_DL_AUD_DC_COMP_RCH_L_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_DC_COMP_CFG1 */ |
| #define AFE_2ND_DL_AUD_DC_COMP_RCH_L_SFT 0 |
| #define AFE_2ND_DL_AUD_DC_COMP_RCH_L_MASK 0xff |
| #define AFE_2ND_DL_AUD_DC_COMP_RCH_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SRC_DEBUG_L */ |
| #define AFE_2ND_DL_SLT_CNT_FLAG_RESET_CTL_SFT 4 |
| #define AFE_2ND_DL_SLT_CNT_FLAG_RESET_CTL_MASK 0x1 |
| #define AFE_2ND_DL_SLT_CNT_FLAG_RESET_CTL_MASK_SFT (0x1 << 4) |
| #define AFE_2ND_DL_SLT_CNT_THD_CTL_H_SFT 0 |
| #define AFE_2ND_DL_SLT_CNT_THD_CTL_H_MASK 0xf |
| #define AFE_2ND_DL_SLT_CNT_THD_CTL_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_ADDA_2ND_DL_SRC_DEBUG */ |
| #define AFE_2ND_DL_SLT_CNT_THD_CTL_SFT 0 |
| #define AFE_2ND_DL_SLT_CNT_THD_CTL_MASK 0xff |
| #define AFE_2ND_DL_SLT_CNT_THD_CTL_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SRC_LCH_MON_M */ |
| #define AFE_2ND_DL_ASDM_LEFT_H_SFT 0 |
| #define AFE_2ND_DL_ASDM_LEFT_H_MASK 0xff |
| #define AFE_2ND_DL_ASDM_LEFT_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SRC_LCH_MON_L */ |
| #define AFE_2ND_DL_ASDM_LEFT_M_SFT 0 |
| #define AFE_2ND_DL_ASDM_LEFT_M_MASK 0xff |
| #define AFE_2ND_DL_ASDM_LEFT_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SRC_LCH_MON */ |
| #define AFE_2ND_DL_ASDM_LEFT_SFT 0 |
| #define AFE_2ND_DL_ASDM_LEFT_MASK 0xff |
| #define AFE_2ND_DL_ASDM_LEFT_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SRC_RCH_MON_M */ |
| #define AFE_2ND_DL_ASDM_RIGHT_H_SFT 0 |
| #define AFE_2ND_DL_ASDM_RIGHT_H_MASK 0xff |
| #define AFE_2ND_DL_ASDM_RIGHT_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SRC_RCH_MON_L */ |
| #define AFE_2ND_DL_ASDM_RIGHT_M_SFT 0 |
| #define AFE_2ND_DL_ASDM_RIGHT_M_MASK 0xff |
| #define AFE_2ND_DL_ASDM_RIGHT_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SRC_RCH_MON */ |
| #define AFE_2ND_DL_ASDM_RIGHT_SFT 0 |
| #define AFE_2ND_DL_ASDM_RIGHT_MASK 0xff |
| #define AFE_2ND_DL_ASDM_RIGHT_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SDM_OUT_MON_H */ |
| #define AFE_2ND_DL_SDM_DITHER_MON_SFT 4 |
| #define AFE_2ND_DL_SDM_DITHER_MON_MASK 0x1 |
| #define AFE_2ND_DL_SDM_DITHER_MON_MASK_SFT (0x1 << 4) |
| #define AFE_2ND_DL_ZERO_OUT_R_SFT 3 |
| #define AFE_2ND_DL_ZERO_OUT_R_MASK 0x1 |
| #define AFE_2ND_DL_ZERO_OUT_R_MASK_SFT (0x1 << 3) |
| #define AFE_2ND_DL_SIGN_OUT_R_SFT 2 |
| #define AFE_2ND_DL_SIGN_OUT_R_MASK 0x1 |
| #define AFE_2ND_DL_SIGN_OUT_R_MASK_SFT (0x1 << 2) |
| #define AFE_2ND_DL_ZERO_OUT_L_SFT 1 |
| #define AFE_2ND_DL_ZERO_OUT_L_MASK 0x1 |
| #define AFE_2ND_DL_ZERO_OUT_L_MASK_SFT (0x1 << 1) |
| #define AFE_2ND_DL_SIGN_OUT_L_SFT 0 |
| #define AFE_2ND_DL_SIGN_OUT_L_MASK 0x1 |
| #define AFE_2ND_DL_SIGN_OUT_L_MASK_SFT (0x1 << 0) |
| |
| /* AFE_ADDA_2ND_DL_SDM_OUT_MON_M */ |
| #define AFE_2ND_DL_BF_SDM_LEFT_SAT_SFT 5 |
| #define AFE_2ND_DL_BF_SDM_LEFT_SAT_MASK 0x1 |
| #define AFE_2ND_DL_BF_SDM_LEFT_SAT_MASK_SFT (0x1 << 5) |
| #define AFE_2ND_DL_BF_SDM_RIGHT_SAT_SFT 4 |
| #define AFE_2ND_DL_BF_SDM_RIGHT_SAT_MASK 0x1 |
| #define AFE_2ND_DL_BF_SDM_RIGHT_SAT_MASK_SFT (0x1 << 4) |
| #define AFE_2ND_DL_3RD_SDM_AUTO_RESET_R_SFT 3 |
| #define AFE_2ND_DL_3RD_SDM_AUTO_RESET_R_MASK 0x1 |
| #define AFE_2ND_DL_3RD_SDM_AUTO_RESET_R_MASK_SFT (0x1 << 3) |
| #define AFE_2ND_DL_3RD_SDM_AUTO_RESET_L_SFT 2 |
| #define AFE_2ND_DL_3RD_SDM_AUTO_RESET_L_MASK 0x1 |
| #define AFE_2ND_DL_3RD_SDM_AUTO_RESET_L_MASK_SFT (0x1 << 2) |
| #define AFE_2ND_DL_2ND_SDM_AUTO_RESET_R_SFT 1 |
| #define AFE_2ND_DL_2ND_SDM_AUTO_RESET_R_MASK 0x1 |
| #define AFE_2ND_DL_2ND_SDM_AUTO_RESET_R_MASK_SFT (0x1 << 1) |
| #define AFE_2ND_DL_2ND_SDM_AUTO_RESET_L_SFT 0 |
| #define AFE_2ND_DL_2ND_SDM_AUTO_RESET_L_MASK 0x1 |
| #define AFE_2ND_DL_2ND_SDM_AUTO_RESET_L_MASK_SFT (0x1 << 0) |
| |
| /* AFE_ADDA_2ND_DL_SDM_OUT_MON_L */ |
| #define AFE_2ND_DL_2ND_AUD_SDM_OUT_L_SFT 0 |
| #define AFE_2ND_DL_2ND_AUD_SDM_OUT_L_MASK 0xff |
| #define AFE_2ND_DL_2ND_AUD_SDM_OUT_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SDM_OUT_MON */ |
| #define AFE_2ND_DL_2ND_AUD_SDM_OUT_R_SFT 0 |
| #define AFE_2ND_DL_2ND_AUD_SDM_OUT_R_MASK 0xff |
| #define AFE_2ND_DL_2ND_AUD_SDM_OUT_R_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SDM_DITHER_CON_M */ |
| #define AFE_3RD_DAC_DL_SDM_DITHER_64TAP_EN_SFT 4 |
| #define AFE_3RD_DAC_DL_SDM_DITHER_64TAP_EN_MASK 0x1 |
| #define AFE_3RD_DAC_DL_SDM_DITHER_64TAP_EN_MASK_SFT (0x1 << 4) |
| #define AFE_2ND_DAC_DL_SDM_DITHER_EN_SFT 0 |
| #define AFE_2ND_DAC_DL_SDM_DITHER_EN_MASK 0x1 |
| #define AFE_2ND_DAC_DL_SDM_DITHER_EN_MASK_SFT (0x1 << 0) |
| |
| /* AFE_ADDA_2ND_DL_SDM_DITHER_CON */ |
| #define AFE_2ND_DAC_DL_SDM_DITHER_GAIN_SFT 0 |
| #define AFE_2ND_DAC_DL_SDM_DITHER_GAIN_MASK 0xff |
| #define AFE_2ND_DAC_DL_SDM_DITHER_GAIN_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SDM_AUTO_RESET_CON_H */ |
| #define AFE_2ND_DL_SDM_AUTO_RESET_TEST_ON_SFT 7 |
| #define AFE_2ND_DL_SDM_AUTO_RESET_TEST_ON_MASK 0x1 |
| #define AFE_2ND_DL_SDM_AUTO_RESET_TEST_ON_MASK_SFT (0x1 << 7) |
| #define AFE_2ND_DL_SDM_AUTO_RESET_SOURCE_SEL_SFT 0 |
| #define AFE_2ND_DL_SDM_AUTO_RESET_SOURCE_SEL_MASK 0x1 |
| #define AFE_2ND_DL_SDM_AUTO_RESET_SOURCE_SEL_MASK_SFT (0x1 << 0) |
| |
| /* AFE_ADDA_2ND_DL_SDM_AUTO_RESET_CON_M */ |
| #define AFE_2ND_DL_SDM_AUTO_RESET_COUNT_TH_H_SFT 0 |
| #define AFE_2ND_DL_SDM_AUTO_RESET_COUNT_TH_H_MASK 0xff |
| #define AFE_2ND_DL_SDM_AUTO_RESET_COUNT_TH_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SDM_AUTO_RESET_CON_L */ |
| #define AFE_2ND_DL_SDM_AUTO_RESET_COUNT_TH_M_SFT 0 |
| #define AFE_2ND_DL_SDM_AUTO_RESET_COUNT_TH_M_MASK 0xff |
| #define AFE_2ND_DL_SDM_AUTO_RESET_COUNT_TH_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SDM_AUTO_RESET_CON */ |
| #define AFE_2ND_DL_SDM_AUTO_RESET_COUNT_TH_SFT 0 |
| #define AFE_2ND_DL_SDM_AUTO_RESET_COUNT_TH_MASK 0xff |
| #define AFE_2ND_DL_SDM_AUTO_RESET_COUNT_TH_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H1R2L_CON0_H */ |
| #define AFE_2ND_DL_XTALK_COMP_H1_R2L_ENABLE_SFT 7 |
| #define AFE_2ND_DL_XTALK_COMP_H1_R2L_ENABLE_MASK 0x1 |
| #define AFE_2ND_DL_XTALK_COMP_H1_R2L_ENABLE_MASK_SFT (0x1 << 7) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H1R2L_CON0_M */ |
| #define AFE_2ND_DL_XTALK_COMP_H1_R2L_COEFF_H_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H1_R2L_COEFF_H_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H1_R2L_COEFF_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H1R2L_CON0_L */ |
| #define AFE_2ND_DL_XTALK_COMP_H1_R2L_COEFF_M_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H1_R2L_COEFF_M_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H1_R2L_COEFF_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H1R2L_CON0 */ |
| #define AFE_2ND_DL_XTALK_COMP_H1_R2L_COEFF_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H1_R2L_COEFF_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H1_R2L_COEFF_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H1L2R_CON0_H */ |
| #define AFE_2ND_DL_XTALK_COMP_H1_L2R_ENABLE_SFT 7 |
| #define AFE_2ND_DL_XTALK_COMP_H1_L2R_ENABLE_MASK 0x1 |
| #define AFE_2ND_DL_XTALK_COMP_H1_L2R_ENABLE_MASK_SFT (0x1 << 7) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H1L2R_CON0_M */ |
| #define AFE_2ND_DL_XTALK_COMP_H1_L2R_COEFF_H_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H1_L2R_COEFF_H_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H1_L2R_COEFF_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H1L2R_CON0_L */ |
| #define AFE_2ND_DL_XTALK_COMP_H1_L2R_COEFF_M_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H1_L2R_COEFF_M_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H1_L2R_COEFF_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H1L2R_CON0 */ |
| #define AFE_2ND_DL_XTALK_COMP_H1_L2R_COEFF_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H1_L2R_COEFF_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H1_L2R_COEFF_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2R2L_CON0_H */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_ENABLE_SFT 7 |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_ENABLE_MASK 0x1 |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_ENABLE_MASK_SFT (0x1 << 7) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2R2L_CON0_M */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B0_COEFF_H_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B0_COEFF_H_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B0_COEFF_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2R2L_CON0_L */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B0_COEFF_M_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B0_COEFF_M_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B0_COEFF_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2R2L_CON0 */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B0_COEFF_L_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B0_COEFF_L_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B0_COEFF_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2R2L_CON1_M */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B1_COEFF_H_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B1_COEFF_H_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B1_COEFF_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2R2L_CON1_L */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B1_COEFF_M_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B1_COEFF_M_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B1_COEFF_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2R2L_CON1 */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B1_COEFF_L_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B1_COEFF_L_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B1_COEFF_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2R2L_CON2_M */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B2_COEFF_H_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B2_COEFF_H_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B2_COEFF_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2R2L_CON2_L */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B2_COEFF_M_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B2_COEFF_M_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B2_COEFF_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2R2L_CON2 */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B2_COEFF_L_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B2_COEFF_L_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_B2_COEFF_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2R2L_CON3_M */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_A1_COEFF_H_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_A1_COEFF_H_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_A1_COEFF_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2R2L_CON3_L */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_A1_COEFF_M_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_A1_COEFF_M_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_A1_COEFF_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2R2L_CON3 */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_A1_COEFF_L_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_A1_COEFF_L_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_A1_COEFF_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2R2L_CON4_M */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_A2_COEFF_H_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_A2_COEFF_H_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_A2_COEFF_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2R2L_CON4_L */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_A2_COEFF_M_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_A2_COEFF_M_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_A2_COEFF_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2R2L_CON4 */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_A2_COEFF_L_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_A2_COEFF_L_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_R2L_A2_COEFF_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2L2R_CON0_H */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_ENABLE_SFT 7 |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_ENABLE_MASK 0x1 |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_ENABLE_MASK_SFT (0x1 << 7) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2L2R_CON0_M */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B0_COEFF_H_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B0_COEFF_H_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B0_COEFF_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2L2R_CON0_L */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B0_COEFF_M_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B0_COEFF_M_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B0_COEFF_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2L2R_CON0 */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B0_COEFF_L_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B0_COEFF_L_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B0_COEFF_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2L2R_CON1_M */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B1_COEFF_H_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B1_COEFF_H_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B1_COEFF_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2L2R_CON1_L */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B1_COEFF_M_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B1_COEFF_M_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B1_COEFF_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2L2R_CON1 */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B1_COEFF_L_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B1_COEFF_L_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B1_COEFF_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2L2R_CON2_M */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B2_COEFF_H_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B2_COEFF_H_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B2_COEFF_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2L2R_CON2_L */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B2_COEFF_M_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B2_COEFF_M_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B2_COEFF_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2L2R_CON2 */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B2_COEFF_L_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B2_COEFF_L_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_B2_COEFF_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2L2R_CON3_M */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_A1_COEFF_H_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_A1_COEFF_H_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_A1_COEFF_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2L2R_CON3_L */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_A1_COEFF_M_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_A1_COEFF_M_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_A1_COEFF_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2L2R_CON3 */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_A1_COEFF_L_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_A1_COEFF_L_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_A1_COEFF_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2L2R_CON4_M */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_A2_COEFF_H_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_A2_COEFF_H_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_A2_COEFF_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2L2R_CON4_L */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_A2_COEFF_M_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_A2_COEFF_M_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_A2_COEFF_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_2ND_DL_XTALK_COMP_H2L2R_CON4 */ |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_A2_COEFF_L_SFT 0 |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_A2_COEFF_L_MASK 0xff |
| #define AFE_2ND_DL_XTALK_COMP_H2_L2R_A2_COEFF_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G7_H */ |
| #define RG_DG_LNGAIN_COMP_RCH_G7_H_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G7_H_MASK 0x3 |
| #define RG_DG_LNGAIN_COMP_RCH_G7_H_MASK_SFT (0x3 << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G7_M */ |
| #define RG_DG_LNGAIN_COMP_RCH_G7_M_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G7_M_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_RCH_G7_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G7_L */ |
| #define RG_DG_LNGAIN_COMP_RCH_G7_L_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G7_L_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_RCH_G7_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_LNGAIN_COMP_RCH_G7 */ |
| #define RG_DG_LNGAIN_COMP_RCH_G7_SFT 0 |
| #define RG_DG_LNGAIN_COMP_RCH_G7_MASK 0xff |
| #define RG_DG_LNGAIN_COMP_RCH_G7_MASK_SFT (0xff << 0) |
| |
| /* AFE_NLE_D2A_DEBUG_H */ |
| #define RG_D2A_SIGNAL_SW_DEBUG_MODE_RCH_SFT 7 |
| #define RG_D2A_SIGNAL_SW_DEBUG_MODE_RCH_MASK 0x1 |
| #define RG_D2A_SIGNAL_SW_DEBUG_MODE_RCH_MASK_SFT (0x1 << 7) |
| #define RG_DA_ANA_HP_LNGAIN_ATT_RCH_SFT 0 |
| #define RG_DA_ANA_HP_LNGAIN_ATT_RCH_MASK 0x7 |
| #define RG_DA_ANA_HP_LNGAIN_ATT_RCH_MASK_SFT (0x7 << 0) |
| |
| /* AFE_NLE_D2A_DEBUG_M */ |
| #define RG_DA_HP_OUTSTG_LN_RCH_SFT 7 |
| #define RG_DA_HP_OUTSTG_LN_RCH_MASK 0x1 |
| #define RG_DA_HP_OUTSTG_LN_RCH_MASK_SFT (0x1 << 7) |
| #define RG_DA_HP_LNSW_EN_RCH_SFT 6 |
| #define RG_DA_HP_LNSW_EN_RCH_MASK 0x1 |
| #define RG_DA_HP_LNSW_EN_RCH_MASK_SFT (0x1 << 6) |
| #define RG_DA_HPCMFB_LN_EN_RCH_SFT 5 |
| #define RG_DA_HPCMFB_LN_EN_RCH_MASK 0x1 |
| #define RG_DA_HPCMFB_LN_EN_RCH_MASK_SFT (0x1 << 5) |
| #define RG_DA_HPCMFB_EN_RCH_SFT 4 |
| #define RG_DA_HPCMFB_EN_RCH_MASK 0x1 |
| #define RG_DA_HPCMFB_EN_RCH_MASK_SFT (0x1 << 4) |
| #define RG_DA_HP_OUTSTG_RCH_SFT 0 |
| #define RG_DA_HP_OUTSTG_RCH_MASK 0x7 |
| #define RG_DA_HP_OUTSTG_RCH_MASK_SFT (0x7 << 0) |
| |
| /* AFE_NLE_D2A_DEBUG_L */ |
| #define RG_D2A_SIGNAL_SW_DEBUG_MODE_LCH_SFT 7 |
| #define RG_D2A_SIGNAL_SW_DEBUG_MODE_LCH_MASK 0x1 |
| #define RG_D2A_SIGNAL_SW_DEBUG_MODE_LCH_MASK_SFT (0x1 << 7) |
| #define RG_DA_ANA_HP_LNGAIN_ATT_LCH_SFT 0 |
| #define RG_DA_ANA_HP_LNGAIN_ATT_LCH_MASK 0x7 |
| #define RG_DA_ANA_HP_LNGAIN_ATT_LCH_MASK_SFT (0x7 << 0) |
| |
| /* AFE_NLE_D2A_DEBUG */ |
| #define RG_DA_HP_OUTSTG_LN_LCH_SFT 7 |
| #define RG_DA_HP_OUTSTG_LN_LCH_MASK 0x1 |
| #define RG_DA_HP_OUTSTG_LN_LCH_MASK_SFT (0x1 << 7) |
| #define RG_DA_HP_LNSW_EN_LCH_SFT 6 |
| #define RG_DA_HP_LNSW_EN_LCH_MASK 0x1 |
| #define RG_DA_HP_LNSW_EN_LCH_MASK_SFT (0x1 << 6) |
| #define RG_DA_HPCMFB_LN_EN_LCH_SFT 5 |
| #define RG_DA_HPCMFB_LN_EN_LCH_MASK 0x1 |
| #define RG_DA_HPCMFB_LN_EN_LCH_MASK_SFT (0x1 << 5) |
| #define RG_DA_HPCMFB_EN_LCH_SFT 4 |
| #define RG_DA_HPCMFB_EN_LCH_MASK 0x1 |
| #define RG_DA_HPCMFB_EN_LCH_MASK_SFT (0x1 << 4) |
| #define RG_DA_HP_OUTSTG_LCH_SFT 0 |
| #define RG_DA_HP_OUTSTG_LCH_MASK 0x7 |
| #define RG_DA_HP_OUTSTG_LCH_MASK_SFT (0x7 << 0) |
| |
| /* AUDIO_DIG_10TH_DSN_ID */ |
| #define AUDIO_DIG_10TH_ANA_ID_SFT 0 |
| #define AUDIO_DIG_10TH_ANA_ID_MASK 0xff |
| #define AUDIO_DIG_10TH_ANA_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_10TH_DSN_ID_H */ |
| #define AUDIO_DIG_10TH_DIG_ID_SFT 0 |
| #define AUDIO_DIG_10TH_DIG_ID_MASK 0xff |
| #define AUDIO_DIG_10TH_DIG_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_10TH_DSN_REV0 */ |
| #define AUDIO_DIG_10TH_ANA_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_10TH_ANA_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_10TH_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_10TH_ANA_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_10TH_ANA_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_10TH_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_10TH_DSN_REV0_H */ |
| #define AUDIO_DIG_10TH_DIG_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_10TH_DIG_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_10TH_DIG_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_10TH_DIG_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_10TH_DIG_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_10TH_DIG_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_10TH_DSN_DBI */ |
| #define AUDIO_DIG_10TH_DSN_CBS_SFT 0 |
| #define AUDIO_DIG_10TH_DSN_CBS_MASK 0x3 |
| #define AUDIO_DIG_10TH_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDIO_DIG_10TH_DSN_BIX_SFT 2 |
| #define AUDIO_DIG_10TH_DSN_BIX_MASK 0x3 |
| #define AUDIO_DIG_10TH_DSN_BIX_MASK_SFT (0x3 << 2) |
| |
| /* AUDIO_DIG_10TH_DSN_DBI_H */ |
| #define AUDIO_DIG_10_ESP_SFT 0 |
| #define AUDIO_DIG_10_ESP_MASK 0xff |
| #define AUDIO_DIG_10_ESP_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_10TH_DSN_DXI */ |
| #define AUDIO_DIG_10TH_DSN_FPI_SFT 0 |
| #define AUDIO_DIG_10TH_DSN_FPI_MASK 0xff |
| #define AUDIO_DIG_10TH_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_CONFIG_H */ |
| #define AFE_DL_HBF1_SW_CONFIG_SFT 7 |
| #define AFE_DL_HBF1_SW_CONFIG_MASK 0x1 |
| #define AFE_DL_HBF1_SW_CONFIG_MASK_SFT (0x1 << 7) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_CONFIG_M */ |
| #define AFE_DL_HBF1_TAPNUM_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_TAPNUM_CONFIG_MASK 0x7f |
| #define AFE_DL_HBF1_TAPNUM_CONFIG_MASK_SFT (0x7f << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_CONFIG_L */ |
| #define AFE_DL_SCF1_SW_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_SW_CONFIG_MASK 0x1 |
| #define AFE_DL_SCF1_SW_CONFIG_MASK_SFT (0x1 << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_CONFIG */ |
| #define AFE_DL_SCF1_TAPNUM_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAPNUM_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAPNUM_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP1_TAP2_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP3_TAP4_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP5_TAP6_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP7_TAP8_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP9_TAP10_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP11_TAP12_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP13_TAP14_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP15_TAP16_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP17_TAP18_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP19_TAP20_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP21_TAP22_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP23_TAP24_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP25_TAP26_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP27_TAP28_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP29_TAP30_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP31_TAP32_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP33_TAP34_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP35_TAP36_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP37_TAP38_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP39_TAP40_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP41_TAP42_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP43_TAP44_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP45_TAP46_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP47_TAP48_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP49_TAP50_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP51_TAP52_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP53_TAP54_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_H */ |
| #define AFE_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_H_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_H_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_M */ |
| #define AFE_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_M_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_M_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_L */ |
| #define AFE_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_L_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_L_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_HBF1_SCF1_TAP55_TAP56_CONFIG */ |
| #define AFE_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_SFT 0 |
| #define AFE_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_MASK 0xff |
| #define AFE_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP57_TAP58_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP57_TAP58_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP57_TAP58_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP57_TAP58_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP57_TAP58_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP57_TAP58_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP57_TAP58_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP57_TAP58_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP57_TAP58_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP57_TAP58_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP57_TAP58_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP57_TAP58_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP57_TAP58_CONFIG */ |
| #define AFE_DL_SCF1_TAP57_TAP58_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP57_TAP58_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP57_TAP58_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_11TH_DSN_ID */ |
| #define AUDIO_DIG_11TH_ANA_ID_SFT 0 |
| #define AUDIO_DIG_11TH_ANA_ID_MASK 0xff |
| #define AUDIO_DIG_11TH_ANA_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_11TH_DSN_ID_H */ |
| #define AUDIO_DIG_11TH_DIG_ID_SFT 0 |
| #define AUDIO_DIG_11TH_DIG_ID_MASK 0xff |
| #define AUDIO_DIG_11TH_DIG_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_11TH_DSN_REV0 */ |
| #define AUDIO_DIG_11TH_ANA_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_11TH_ANA_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_11TH_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_11TH_ANA_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_11TH_ANA_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_11TH_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_11TH_DSN_REV0_H */ |
| #define AUDIO_DIG_11TH_DIG_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_11TH_DIG_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_11TH_DIG_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_11TH_DIG_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_11TH_DIG_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_11TH_DIG_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_11TH_DSN_DBI */ |
| #define AUDIO_DIG_11TH_DSN_CBS_SFT 0 |
| #define AUDIO_DIG_11TH_DSN_CBS_MASK 0x3 |
| #define AUDIO_DIG_11TH_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDIO_DIG_11TH_DSN_BIX_SFT 2 |
| #define AUDIO_DIG_11TH_DSN_BIX_MASK 0x3 |
| #define AUDIO_DIG_11TH_DSN_BIX_MASK_SFT (0x3 << 2) |
| |
| /* AUDIO_DIG_11TH_DSN_DBI_H */ |
| #define AUDIO_DIG_11_ESP_SFT 0 |
| #define AUDIO_DIG_11_ESP_MASK 0xff |
| #define AUDIO_DIG_11_ESP_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_11TH_DSN_DXI */ |
| #define AUDIO_DIG_11TH_DSN_FPI_SFT 0 |
| #define AUDIO_DIG_11TH_DSN_FPI_MASK 0xff |
| #define AUDIO_DIG_11TH_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP59_TAP60_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP59_TAP60_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP59_TAP60_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP59_TAP60_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP59_TAP60_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP59_TAP60_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP59_TAP60_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP59_TAP60_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP59_TAP60_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP59_TAP60_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP59_TAP60_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP59_TAP60_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP59_TAP60_CONFIG */ |
| #define AFE_DL_SCF1_TAP59_TAP60_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP59_TAP60_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP59_TAP60_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP61_TAP62_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP61_TAP62_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP61_TAP62_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP61_TAP62_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP61_TAP62_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP61_TAP62_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP61_TAP62_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP61_TAP62_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP61_TAP62_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP61_TAP62_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP61_TAP62_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP61_TAP62_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP61_TAP62_CONFIG */ |
| #define AFE_DL_SCF1_TAP61_TAP62_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP61_TAP62_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP61_TAP62_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP63_TAP64_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP63_TAP64_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP63_TAP64_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP63_TAP64_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP63_TAP64_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP63_TAP64_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP63_TAP64_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP63_TAP64_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP63_TAP64_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP63_TAP64_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP63_TAP64_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP63_TAP64_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP63_TAP64_CONFIG */ |
| #define AFE_DL_SCF1_TAP63_TAP64_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP63_TAP64_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP63_TAP64_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP65_TAP66_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP65_TAP66_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP65_TAP66_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP65_TAP66_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP65_TAP66_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP65_TAP66_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP65_TAP66_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP65_TAP66_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP65_TAP66_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP65_TAP66_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP65_TAP66_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP65_TAP66_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP65_TAP66_CONFIG */ |
| #define AFE_DL_SCF1_TAP65_TAP66_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP65_TAP66_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP65_TAP66_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP67_TAP68_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP67_TAP68_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP67_TAP68_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP67_TAP68_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP67_TAP68_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP67_TAP68_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP67_TAP68_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP67_TAP68_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP67_TAP68_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP67_TAP68_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP67_TAP68_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP67_TAP68_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP67_TAP68_CONFIG */ |
| #define AFE_DL_SCF1_TAP67_TAP68_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP67_TAP68_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP67_TAP68_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP69_TAP70_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP69_TAP70_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP69_TAP70_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP69_TAP70_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP69_TAP70_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP69_TAP70_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP69_TAP70_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP69_TAP70_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP69_TAP70_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP69_TAP70_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP69_TAP70_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP69_TAP70_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP69_TAP70_CONFIG */ |
| #define AFE_DL_SCF1_TAP69_TAP70_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP69_TAP70_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP69_TAP70_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP71_TAP72_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP71_TAP72_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP71_TAP72_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP71_TAP72_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP71_TAP72_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP71_TAP72_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP71_TAP72_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP71_TAP72_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP71_TAP72_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP71_TAP72_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP71_TAP72_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP71_TAP72_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP71_TAP72_CONFIG */ |
| #define AFE_DL_SCF1_TAP71_TAP72_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP71_TAP72_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP71_TAP72_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP73_TAP74_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP73_TAP74_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP73_TAP74_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP73_TAP74_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP73_TAP74_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP73_TAP74_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP73_TAP74_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP73_TAP74_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP73_TAP74_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP73_TAP74_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP73_TAP74_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP73_TAP74_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP73_TAP74_CONFIG */ |
| #define AFE_DL_SCF1_TAP73_TAP74_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP73_TAP74_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP73_TAP74_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP75_TAP76_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP75_TAP76_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP75_TAP76_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP75_TAP76_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP75_TAP76_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP75_TAP76_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP75_TAP76_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP75_TAP76_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP75_TAP76_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP75_TAP76_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP75_TAP76_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP75_TAP76_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP75_TAP76_CONFIG */ |
| #define AFE_DL_SCF1_TAP75_TAP76_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP75_TAP76_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP75_TAP76_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP77_TAP78_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP77_TAP78_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP77_TAP78_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP77_TAP78_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP77_TAP78_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP77_TAP78_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP77_TAP78_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP77_TAP78_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP77_TAP78_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP77_TAP78_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP77_TAP78_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP77_TAP78_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP77_TAP78_CONFIG */ |
| #define AFE_DL_SCF1_TAP77_TAP78_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP77_TAP78_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP77_TAP78_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP79_TAP80_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP79_TAP80_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP79_TAP80_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP79_TAP80_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP79_TAP80_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP79_TAP80_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP79_TAP80_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP79_TAP80_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP79_TAP80_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP79_TAP80_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP79_TAP80_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP79_TAP80_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP79_TAP80_CONFIG */ |
| #define AFE_DL_SCF1_TAP79_TAP80_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP79_TAP80_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP79_TAP80_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP81_TAP82_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP81_TAP82_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP81_TAP82_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP81_TAP82_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP81_TAP82_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP81_TAP82_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP81_TAP82_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP81_TAP82_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP81_TAP82_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP81_TAP82_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP81_TAP82_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP81_TAP82_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP81_TAP82_CONFIG */ |
| #define AFE_DL_SCF1_TAP81_TAP82_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP81_TAP82_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP81_TAP82_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP83_TAP84_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP83_TAP84_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP83_TAP84_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP83_TAP84_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP83_TAP84_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP83_TAP84_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP83_TAP84_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP83_TAP84_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP83_TAP84_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP83_TAP84_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP83_TAP84_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP83_TAP84_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP83_TAP84_CONFIG */ |
| #define AFE_DL_SCF1_TAP83_TAP84_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP83_TAP84_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP83_TAP84_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP85_TAP86_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP85_TAP86_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP85_TAP86_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP85_TAP86_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP85_TAP86_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP85_TAP86_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP85_TAP86_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP85_TAP86_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP85_TAP86_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP85_TAP86_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP85_TAP86_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP85_TAP86_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP85_TAP86_CONFIG */ |
| #define AFE_DL_SCF1_TAP85_TAP86_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP85_TAP86_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP85_TAP86_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP87_TAP88_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP87_TAP88_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP87_TAP88_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP87_TAP88_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP87_TAP88_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP87_TAP88_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP87_TAP88_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP87_TAP88_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP87_TAP88_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP87_TAP88_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP87_TAP88_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP87_TAP88_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP87_TAP88_CONFIG */ |
| #define AFE_DL_SCF1_TAP87_TAP88_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP87_TAP88_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP87_TAP88_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP89_TAP90_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP89_TAP90_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP89_TAP90_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP89_TAP90_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP89_TAP90_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP89_TAP90_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP89_TAP90_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP89_TAP90_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP89_TAP90_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP89_TAP90_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP89_TAP90_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP89_TAP90_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP89_TAP90_CONFIG */ |
| #define AFE_DL_SCF1_TAP89_TAP90_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP89_TAP90_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP89_TAP90_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP91_TAP92_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP91_TAP92_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP91_TAP92_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP91_TAP92_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP91_TAP92_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP91_TAP92_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP91_TAP92_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP91_TAP92_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP91_TAP92_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP91_TAP92_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP91_TAP92_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP91_TAP92_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP91_TAP92_CONFIG */ |
| #define AFE_DL_SCF1_TAP91_TAP92_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP91_TAP92_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP91_TAP92_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP93_TAP94_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP93_TAP94_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP93_TAP94_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP93_TAP94_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP93_TAP94_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP93_TAP94_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP93_TAP94_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP93_TAP94_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP93_TAP94_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP93_TAP94_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP93_TAP94_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP93_TAP94_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP93_TAP94_CONFIG */ |
| #define AFE_DL_SCF1_TAP93_TAP94_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP93_TAP94_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP93_TAP94_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP95_TAP96_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP95_TAP96_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP95_TAP96_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP95_TAP96_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP95_TAP96_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP95_TAP96_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP95_TAP96_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP95_TAP96_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP95_TAP96_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP95_TAP96_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP95_TAP96_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP95_TAP96_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP95_TAP96_CONFIG */ |
| #define AFE_DL_SCF1_TAP95_TAP96_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP95_TAP96_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP95_TAP96_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP97_TAP98_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP97_TAP98_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP97_TAP98_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP97_TAP98_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP97_TAP98_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP97_TAP98_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP97_TAP98_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP97_TAP98_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP97_TAP98_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP97_TAP98_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP97_TAP98_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP97_TAP98_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP97_TAP98_CONFIG */ |
| #define AFE_DL_SCF1_TAP97_TAP98_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP97_TAP98_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP97_TAP98_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP99_TAP100_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP99_TAP100_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP99_TAP100_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP99_TAP100_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP99_TAP100_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP99_TAP100_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP99_TAP100_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP99_TAP100_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP99_TAP100_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP99_TAP100_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP99_TAP100_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP99_TAP100_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP99_TAP100_CONFIG */ |
| #define AFE_DL_SCF1_TAP99_TAP100_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP99_TAP100_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP99_TAP100_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP101_TAP102_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP101_TAP102_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP101_TAP102_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP101_TAP102_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP101_TAP102_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP101_TAP102_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP101_TAP102_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP101_TAP102_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP101_TAP102_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP101_TAP102_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP101_TAP102_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP101_TAP102_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP101_TAP102_CONFIG */ |
| #define AFE_DL_SCF1_TAP101_TAP102_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP101_TAP102_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP101_TAP102_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP103_TAP104_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP103_TAP104_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP103_TAP104_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP103_TAP104_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP103_TAP104_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP103_TAP104_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP103_TAP104_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP103_TAP104_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP103_TAP104_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP103_TAP104_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP103_TAP104_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP103_TAP104_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP103_TAP104_CONFIG */ |
| #define AFE_DL_SCF1_TAP103_TAP104_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP103_TAP104_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP103_TAP104_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP105_TAP106_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP105_TAP106_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP105_TAP106_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP105_TAP106_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP105_TAP106_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP105_TAP106_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP105_TAP106_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP105_TAP106_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP105_TAP106_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP105_TAP106_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP105_TAP106_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP105_TAP106_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP105_TAP106_CONFIG */ |
| #define AFE_DL_SCF1_TAP105_TAP106_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP105_TAP106_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP105_TAP106_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP107_TAP108_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP107_TAP108_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP107_TAP108_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP107_TAP108_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP107_TAP108_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP107_TAP108_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP107_TAP108_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP107_TAP108_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP107_TAP108_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP107_TAP108_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP107_TAP108_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP107_TAP108_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP107_TAP108_CONFIG */ |
| #define AFE_DL_SCF1_TAP107_TAP108_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP107_TAP108_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP107_TAP108_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP109_TAP110_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP109_TAP110_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP109_TAP110_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP109_TAP110_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP109_TAP110_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP109_TAP110_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP109_TAP110_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP109_TAP110_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP109_TAP110_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP109_TAP110_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP109_TAP110_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP109_TAP110_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP109_TAP110_CONFIG */ |
| #define AFE_DL_SCF1_TAP109_TAP110_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP109_TAP110_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP109_TAP110_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP111_TAP112_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP111_TAP112_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP111_TAP112_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP111_TAP112_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP111_TAP112_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP111_TAP112_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP111_TAP112_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP111_TAP112_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP111_TAP112_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP111_TAP112_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP111_TAP112_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP111_TAP112_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP111_TAP112_CONFIG */ |
| #define AFE_DL_SCF1_TAP111_TAP112_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP111_TAP112_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP111_TAP112_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP113_TAP114_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP113_TAP114_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP113_TAP114_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP113_TAP114_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP113_TAP114_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP113_TAP114_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP113_TAP114_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP113_TAP114_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP113_TAP114_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP113_TAP114_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP113_TAP114_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP113_TAP114_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP113_TAP114_CONFIG */ |
| #define AFE_DL_SCF1_TAP113_TAP114_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP113_TAP114_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP113_TAP114_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP115_TAP116_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP115_TAP116_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP115_TAP116_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP115_TAP116_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP115_TAP116_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP115_TAP116_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP115_TAP116_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP115_TAP116_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP115_TAP116_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP115_TAP116_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP115_TAP116_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP115_TAP116_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP115_TAP116_CONFIG */ |
| #define AFE_DL_SCF1_TAP115_TAP116_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP115_TAP116_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP115_TAP116_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP117_TAP118_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP117_TAP118_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP117_TAP118_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP117_TAP118_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP117_TAP118_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP117_TAP118_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP117_TAP118_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP117_TAP118_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP117_TAP118_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP117_TAP118_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP117_TAP118_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP117_TAP118_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP117_TAP118_CONFIG */ |
| #define AFE_DL_SCF1_TAP117_TAP118_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP117_TAP118_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP117_TAP118_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_12TH_DSN_ID */ |
| #define AUDIO_DIG_12TH_ANA_ID_SFT 0 |
| #define AUDIO_DIG_12TH_ANA_ID_MASK 0xff |
| #define AUDIO_DIG_12TH_ANA_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_12TH_DSN_ID_H */ |
| #define AUDIO_DIG_12TH_DIG_ID_SFT 0 |
| #define AUDIO_DIG_12TH_DIG_ID_MASK 0xff |
| #define AUDIO_DIG_12TH_DIG_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_12TH_DSN_REV0 */ |
| #define AUDIO_DIG_12TH_ANA_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_12TH_ANA_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_12TH_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_12TH_ANA_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_12TH_ANA_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_12TH_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_12TH_DSN_REV0_H */ |
| #define AUDIO_DIG_12TH_DIG_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_12TH_DIG_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_12TH_DIG_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_12TH_DIG_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_12TH_DIG_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_12TH_DIG_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_12TH_DSN_DBI */ |
| #define AUDIO_DIG_12TH_DSN_CBS_SFT 0 |
| #define AUDIO_DIG_12TH_DSN_CBS_MASK 0x3 |
| #define AUDIO_DIG_12TH_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDIO_DIG_12TH_DSN_BIX_SFT 2 |
| #define AUDIO_DIG_12TH_DSN_BIX_MASK 0x3 |
| #define AUDIO_DIG_12TH_DSN_BIX_MASK_SFT (0x3 << 2) |
| |
| /* AUDIO_DIG_12TH_DSN_DBI_H */ |
| #define AUDIO_DIG_12_ESP_SFT 0 |
| #define AUDIO_DIG_12_ESP_MASK 0xff |
| #define AUDIO_DIG_12_ESP_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_12TH_DSN_DXI */ |
| #define AUDIO_DIG_12TH_DSN_FPI_SFT 0 |
| #define AUDIO_DIG_12TH_DSN_FPI_MASK 0xff |
| #define AUDIO_DIG_12TH_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP119_TAP120_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP119_TAP120_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP119_TAP120_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP119_TAP120_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP119_TAP120_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP119_TAP120_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP119_TAP120_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP119_TAP120_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP119_TAP120_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP119_TAP120_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP119_TAP120_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP119_TAP120_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP119_TAP120_CONFIG */ |
| #define AFE_DL_SCF1_TAP119_TAP120_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP119_TAP120_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP119_TAP120_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP121_TAP122_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP121_TAP122_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP121_TAP122_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP121_TAP122_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP121_TAP122_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP121_TAP122_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP121_TAP122_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP121_TAP122_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP121_TAP122_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP121_TAP122_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP121_TAP122_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP121_TAP122_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP121_TAP122_CONFIG */ |
| #define AFE_DL_SCF1_TAP121_TAP122_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP121_TAP122_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP121_TAP122_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP123_TAP124_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP123_TAP124_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP123_TAP124_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP123_TAP124_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP123_TAP124_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP123_TAP124_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP123_TAP124_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP123_TAP124_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP123_TAP124_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP123_TAP124_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP123_TAP124_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP123_TAP124_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP123_TAP124_CONFIG */ |
| #define AFE_DL_SCF1_TAP123_TAP124_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP123_TAP124_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP123_TAP124_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP125_TAP126_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP125_TAP126_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP125_TAP126_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP125_TAP126_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP125_TAP126_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP125_TAP126_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP125_TAP126_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP125_TAP126_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP125_TAP126_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP125_TAP126_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP125_TAP126_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP125_TAP126_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP125_TAP126_CONFIG */ |
| #define AFE_DL_SCF1_TAP125_TAP126_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP125_TAP126_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP125_TAP126_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP127_TAP128_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP127_TAP128_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP127_TAP128_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP127_TAP128_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP127_TAP128_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP127_TAP128_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP127_TAP128_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP127_TAP128_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP127_TAP128_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP127_TAP128_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP127_TAP128_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP127_TAP128_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP127_TAP128_CONFIG */ |
| #define AFE_DL_SCF1_TAP127_TAP128_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP127_TAP128_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP127_TAP128_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP129_TAP130_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP129_TAP130_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP129_TAP130_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP129_TAP130_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP129_TAP130_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP129_TAP130_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP129_TAP130_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP129_TAP130_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP129_TAP130_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP129_TAP130_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP129_TAP130_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP129_TAP130_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP129_TAP130_CONFIG */ |
| #define AFE_DL_SCF1_TAP129_TAP130_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP129_TAP130_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP129_TAP130_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP131_TAP132_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP131_TAP132_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP131_TAP132_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP131_TAP132_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP131_TAP132_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP131_TAP132_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP131_TAP132_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP131_TAP132_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP131_TAP132_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP131_TAP132_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP131_TAP132_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP131_TAP132_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP131_TAP132_CONFIG */ |
| #define AFE_DL_SCF1_TAP131_TAP132_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP131_TAP132_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP131_TAP132_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP133_TAP134_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP133_TAP134_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP133_TAP134_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP133_TAP134_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP133_TAP134_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP133_TAP134_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP133_TAP134_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP133_TAP134_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP133_TAP134_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP133_TAP134_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP133_TAP134_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP133_TAP134_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP133_TAP134_CONFIG */ |
| #define AFE_DL_SCF1_TAP133_TAP134_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP133_TAP134_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP133_TAP134_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP135_TAP136_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP135_TAP136_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP135_TAP136_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP135_TAP136_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP135_TAP136_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP135_TAP136_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP135_TAP136_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP135_TAP136_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP135_TAP136_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP135_TAP136_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP135_TAP136_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP135_TAP136_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP135_TAP136_CONFIG */ |
| #define AFE_DL_SCF1_TAP135_TAP136_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP135_TAP136_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP135_TAP136_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP137_TAP138_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP137_TAP138_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP137_TAP138_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP137_TAP138_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP137_TAP138_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP137_TAP138_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP137_TAP138_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP137_TAP138_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP137_TAP138_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP137_TAP138_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP137_TAP138_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP137_TAP138_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP137_TAP138_CONFIG */ |
| #define AFE_DL_SCF1_TAP137_TAP138_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP137_TAP138_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP137_TAP138_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP139_TAP140_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP139_TAP140_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP139_TAP140_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP139_TAP140_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP139_TAP140_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP139_TAP140_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP139_TAP140_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP139_TAP140_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP139_TAP140_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP139_TAP140_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP139_TAP140_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP139_TAP140_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP139_TAP140_CONFIG */ |
| #define AFE_DL_SCF1_TAP139_TAP140_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP139_TAP140_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP139_TAP140_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP141_TAP142_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP141_TAP142_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP141_TAP142_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP141_TAP142_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP141_TAP142_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP141_TAP142_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP141_TAP142_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP141_TAP142_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP141_TAP142_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP141_TAP142_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP141_TAP142_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP141_TAP142_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP141_TAP142_CONFIG */ |
| #define AFE_DL_SCF1_TAP141_TAP142_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP141_TAP142_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP141_TAP142_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP143_TAP144_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP143_TAP144_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP143_TAP144_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP143_TAP144_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP143_TAP144_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP143_TAP144_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP143_TAP144_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP143_TAP144_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP143_TAP144_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP143_TAP144_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP143_TAP144_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP143_TAP144_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP143_TAP144_CONFIG */ |
| #define AFE_DL_SCF1_TAP143_TAP144_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP143_TAP144_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP143_TAP144_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP145_TAP146_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP145_TAP146_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP145_TAP146_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP145_TAP146_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP145_TAP146_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP145_TAP146_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP145_TAP146_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP145_TAP146_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP145_TAP146_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP145_TAP146_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP145_TAP146_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP145_TAP146_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP145_TAP146_CONFIG */ |
| #define AFE_DL_SCF1_TAP145_TAP146_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP145_TAP146_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP145_TAP146_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP147_TAP148_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP147_TAP148_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP147_TAP148_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP147_TAP148_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP147_TAP148_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP147_TAP148_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP147_TAP148_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP147_TAP148_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP147_TAP148_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP147_TAP148_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP147_TAP148_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP147_TAP148_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP147_TAP148_CONFIG */ |
| #define AFE_DL_SCF1_TAP147_TAP148_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP147_TAP148_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP147_TAP148_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP149_TAP150_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP149_TAP150_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP149_TAP150_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP149_TAP150_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP149_TAP150_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP149_TAP150_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP149_TAP150_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP149_TAP150_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP149_TAP150_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP149_TAP150_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP149_TAP150_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP149_TAP150_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP149_TAP150_CONFIG */ |
| #define AFE_DL_SCF1_TAP149_TAP150_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP149_TAP150_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP149_TAP150_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP151_TAP152_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP151_TAP152_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP151_TAP152_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP151_TAP152_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP151_TAP152_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP151_TAP152_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP151_TAP152_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP151_TAP152_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP151_TAP152_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP151_TAP152_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP151_TAP152_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP151_TAP152_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP151_TAP152_CONFIG */ |
| #define AFE_DL_SCF1_TAP151_TAP152_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP151_TAP152_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP151_TAP152_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP153_TAP154_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP153_TAP154_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP153_TAP154_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP153_TAP154_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP153_TAP154_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP153_TAP154_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP153_TAP154_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP153_TAP154_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP153_TAP154_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP153_TAP154_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP153_TAP154_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP153_TAP154_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP153_TAP154_CONFIG */ |
| #define AFE_DL_SCF1_TAP153_TAP154_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP153_TAP154_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP153_TAP154_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP155_TAP156_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP155_TAP156_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP155_TAP156_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP155_TAP156_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP155_TAP156_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP155_TAP156_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP155_TAP156_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP155_TAP156_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP155_TAP156_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP155_TAP156_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP155_TAP156_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP155_TAP156_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP155_TAP156_CONFIG */ |
| #define AFE_DL_SCF1_TAP155_TAP156_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP155_TAP156_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP155_TAP156_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP157_TAP158_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP157_TAP158_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP157_TAP158_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP157_TAP158_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP157_TAP158_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP157_TAP158_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP157_TAP158_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP157_TAP158_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP157_TAP158_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP157_TAP158_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP157_TAP158_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP157_TAP158_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP157_TAP158_CONFIG */ |
| #define AFE_DL_SCF1_TAP157_TAP158_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP157_TAP158_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP157_TAP158_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP159_TAP160_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP159_TAP160_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP159_TAP160_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP159_TAP160_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP159_TAP160_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP159_TAP160_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP159_TAP160_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP159_TAP160_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP159_TAP160_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP159_TAP160_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP159_TAP160_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP159_TAP160_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP159_TAP160_CONFIG */ |
| #define AFE_DL_SCF1_TAP159_TAP160_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP159_TAP160_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP159_TAP160_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP161_TAP162_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP161_TAP162_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP161_TAP162_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP161_TAP162_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP161_TAP162_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP161_TAP162_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP161_TAP162_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP161_TAP162_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP161_TAP162_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP161_TAP162_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP161_TAP162_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP161_TAP162_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP161_TAP162_CONFIG */ |
| #define AFE_DL_SCF1_TAP161_TAP162_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP161_TAP162_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP161_TAP162_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP163_TAP164_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP163_TAP164_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP163_TAP164_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP163_TAP164_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP163_TAP164_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP163_TAP164_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP163_TAP164_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP163_TAP164_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP163_TAP164_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP163_TAP164_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP163_TAP164_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP163_TAP164_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP163_TAP164_CONFIG */ |
| #define AFE_DL_SCF1_TAP163_TAP164_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP163_TAP164_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP163_TAP164_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP165_TAP166_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP165_TAP166_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP165_TAP166_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP165_TAP166_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP165_TAP166_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP165_TAP166_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP165_TAP166_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP165_TAP166_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP165_TAP166_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP165_TAP166_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP165_TAP166_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP165_TAP166_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP165_TAP166_CONFIG */ |
| #define AFE_DL_SCF1_TAP165_TAP166_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP165_TAP166_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP165_TAP166_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP167_TAP168_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP167_TAP168_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP167_TAP168_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP167_TAP168_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP167_TAP168_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP167_TAP168_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP167_TAP168_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP167_TAP168_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP167_TAP168_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP167_TAP168_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP167_TAP168_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP167_TAP168_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP167_TAP168_CONFIG */ |
| #define AFE_DL_SCF1_TAP167_TAP168_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP167_TAP168_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP167_TAP168_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP169_TAP170_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP169_TAP170_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP169_TAP170_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP169_TAP170_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP169_TAP170_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP169_TAP170_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP169_TAP170_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP169_TAP170_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP169_TAP170_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP169_TAP170_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP169_TAP170_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP169_TAP170_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP169_TAP170_CONFIG */ |
| #define AFE_DL_SCF1_TAP169_TAP170_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP169_TAP170_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP169_TAP170_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP171_TAP172_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP171_TAP172_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP171_TAP172_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP171_TAP172_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP171_TAP172_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP171_TAP172_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP171_TAP172_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP171_TAP172_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP171_TAP172_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP171_TAP172_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP171_TAP172_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP171_TAP172_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP171_TAP172_CONFIG */ |
| #define AFE_DL_SCF1_TAP171_TAP172_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP171_TAP172_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP171_TAP172_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP173_TAP174_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP173_TAP174_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP173_TAP174_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP173_TAP174_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP173_TAP174_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP173_TAP174_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP173_TAP174_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP173_TAP174_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP173_TAP174_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP173_TAP174_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP173_TAP174_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP173_TAP174_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP173_TAP174_CONFIG */ |
| #define AFE_DL_SCF1_TAP173_TAP174_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP173_TAP174_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP173_TAP174_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP175_TAP176_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP175_TAP176_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP175_TAP176_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP175_TAP176_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP175_TAP176_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP175_TAP176_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP175_TAP176_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP175_TAP176_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP175_TAP176_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP175_TAP176_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP175_TAP176_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP175_TAP176_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP175_TAP176_CONFIG */ |
| #define AFE_DL_SCF1_TAP175_TAP176_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP175_TAP176_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP175_TAP176_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP177_TAP178_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP177_TAP178_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP177_TAP178_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP177_TAP178_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP177_TAP178_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP177_TAP178_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP177_TAP178_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP177_TAP178_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP177_TAP178_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP177_TAP178_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP177_TAP178_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP177_TAP178_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP177_TAP178_CONFIG */ |
| #define AFE_DL_SCF1_TAP177_TAP178_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP177_TAP178_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP177_TAP178_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_13TH_DSN_ID */ |
| #define AUDIO_DIG_13TH_ANA_ID_SFT 0 |
| #define AUDIO_DIG_13TH_ANA_ID_MASK 0xff |
| #define AUDIO_DIG_13TH_ANA_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_13TH_DSN_ID_H */ |
| #define AUDIO_DIG_13TH_DIG_ID_SFT 0 |
| #define AUDIO_DIG_13TH_DIG_ID_MASK 0xff |
| #define AUDIO_DIG_13TH_DIG_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_13TH_DSN_REV0 */ |
| #define AUDIO_DIG_13TH_ANA_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_13TH_ANA_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_13TH_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_13TH_ANA_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_13TH_ANA_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_13TH_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_13TH_DSN_REV0_H */ |
| #define AUDIO_DIG_13TH_DIG_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_13TH_DIG_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_13TH_DIG_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_13TH_DIG_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_13TH_DIG_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_13TH_DIG_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_13TH_DSN_DBI */ |
| #define AUDIO_DIG_13TH_DSN_CBS_SFT 0 |
| #define AUDIO_DIG_13TH_DSN_CBS_MASK 0x3 |
| #define AUDIO_DIG_13TH_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDIO_DIG_13TH_DSN_BIX_SFT 2 |
| #define AUDIO_DIG_13TH_DSN_BIX_MASK 0x3 |
| #define AUDIO_DIG_13TH_DSN_BIX_MASK_SFT (0x3 << 2) |
| |
| /* AUDIO_DIG_13TH_DSN_DBI_H */ |
| #define AUDIO_DIG_13_ESP_SFT 0 |
| #define AUDIO_DIG_13_ESP_MASK 0xff |
| #define AUDIO_DIG_13_ESP_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_13TH_DSN_DXI */ |
| #define AUDIO_DIG_13TH_DSN_FPI_SFT 0 |
| #define AUDIO_DIG_13TH_DSN_FPI_MASK 0xff |
| #define AUDIO_DIG_13TH_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP179_TAP180_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP179_TAP180_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP179_TAP180_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP179_TAP180_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP179_TAP180_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP179_TAP180_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP179_TAP180_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP179_TAP180_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP179_TAP180_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP179_TAP180_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP179_TAP180_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP179_TAP180_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP179_TAP180_CONFIG */ |
| #define AFE_DL_SCF1_TAP179_TAP180_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP179_TAP180_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP179_TAP180_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP181_TAP182_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP181_TAP182_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP181_TAP182_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP181_TAP182_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP181_TAP182_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP181_TAP182_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP181_TAP182_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP181_TAP182_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP181_TAP182_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP181_TAP182_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP181_TAP182_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP181_TAP182_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP181_TAP182_CONFIG */ |
| #define AFE_DL_SCF1_TAP181_TAP182_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP181_TAP182_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP181_TAP182_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP183_TAP184_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP183_TAP184_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP183_TAP184_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP183_TAP184_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP183_TAP184_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP183_TAP184_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP183_TAP184_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP183_TAP184_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP183_TAP184_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP183_TAP184_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP183_TAP184_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP183_TAP184_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP183_TAP184_CONFIG */ |
| #define AFE_DL_SCF1_TAP183_TAP184_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP183_TAP184_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP183_TAP184_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP185_TAP186_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP185_TAP186_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP185_TAP186_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP185_TAP186_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP185_TAP186_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP185_TAP186_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP185_TAP186_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP185_TAP186_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP185_TAP186_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP185_TAP186_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP185_TAP186_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP185_TAP186_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP185_TAP186_CONFIG */ |
| #define AFE_DL_SCF1_TAP185_TAP186_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP185_TAP186_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP185_TAP186_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP187_TAP188_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP187_TAP188_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP187_TAP188_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP187_TAP188_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP187_TAP188_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP187_TAP188_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP187_TAP188_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP187_TAP188_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP187_TAP188_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP187_TAP188_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP187_TAP188_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP187_TAP188_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP187_TAP188_CONFIG */ |
| #define AFE_DL_SCF1_TAP187_TAP188_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP187_TAP188_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP187_TAP188_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP189_TAP190_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP189_TAP190_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP189_TAP190_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP189_TAP190_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP189_TAP190_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP189_TAP190_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP189_TAP190_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP189_TAP190_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP189_TAP190_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP189_TAP190_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP189_TAP190_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP189_TAP190_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP189_TAP190_CONFIG */ |
| #define AFE_DL_SCF1_TAP189_TAP190_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP189_TAP190_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP189_TAP190_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP191_TAP192_CONFIG_H */ |
| #define AFE_DL_SCF1_TAP191_TAP192_CONFIG_H_SFT 0 |
| #define AFE_DL_SCF1_TAP191_TAP192_CONFIG_H_MASK 0xff |
| #define AFE_DL_SCF1_TAP191_TAP192_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP191_TAP192_CONFIG_M */ |
| #define AFE_DL_SCF1_TAP191_TAP192_CONFIG_M_SFT 0 |
| #define AFE_DL_SCF1_TAP191_TAP192_CONFIG_M_MASK 0xff |
| #define AFE_DL_SCF1_TAP191_TAP192_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP191_TAP192_CONFIG_L */ |
| #define AFE_DL_SCF1_TAP191_TAP192_CONFIG_L_SFT 0 |
| #define AFE_DL_SCF1_TAP191_TAP192_CONFIG_L_MASK 0xff |
| #define AFE_DL_SCF1_TAP191_TAP192_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_DL_SCF1_TAP191_TAP192_CONFIG */ |
| #define AFE_DL_SCF1_TAP191_TAP192_CONFIG_SFT 0 |
| #define AFE_DL_SCF1_TAP191_TAP192_CONFIG_MASK 0xff |
| #define AFE_DL_SCF1_TAP191_TAP192_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP179_TAP180_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP179_TAP180_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP179_TAP180_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP179_TAP180_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP179_TAP180_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP179_TAP180_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP179_TAP180_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP179_TAP180_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP179_TAP180_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP179_TAP180_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP179_TAP180_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP179_TAP180_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP179_TAP180_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP179_TAP180_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP179_TAP180_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP179_TAP180_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP181_TAP182_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP181_TAP182_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP181_TAP182_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP181_TAP182_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP181_TAP182_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP181_TAP182_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP181_TAP182_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP181_TAP182_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP181_TAP182_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP181_TAP182_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP181_TAP182_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP181_TAP182_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP181_TAP182_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP181_TAP182_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP181_TAP182_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP181_TAP182_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP183_TAP184_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP183_TAP184_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP183_TAP184_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP183_TAP184_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP183_TAP184_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP183_TAP184_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP183_TAP184_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP183_TAP184_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP183_TAP184_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP183_TAP184_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP183_TAP184_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP183_TAP184_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP183_TAP184_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP183_TAP184_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP183_TAP184_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP183_TAP184_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP185_TAP186_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP185_TAP186_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP185_TAP186_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP185_TAP186_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP185_TAP186_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP185_TAP186_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP185_TAP186_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP185_TAP186_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP185_TAP186_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP185_TAP186_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP185_TAP186_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP185_TAP186_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP185_TAP186_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP185_TAP186_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP185_TAP186_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP185_TAP186_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP187_TAP188_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP187_TAP188_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP187_TAP188_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP187_TAP188_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP187_TAP188_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP187_TAP188_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP187_TAP188_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP187_TAP188_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP187_TAP188_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP187_TAP188_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP187_TAP188_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP187_TAP188_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP187_TAP188_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP187_TAP188_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP187_TAP188_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP187_TAP188_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP189_TAP190_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP189_TAP190_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP189_TAP190_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP189_TAP190_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP189_TAP190_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP189_TAP190_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP189_TAP190_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP189_TAP190_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP189_TAP190_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP189_TAP190_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP189_TAP190_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP189_TAP190_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP189_TAP190_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP189_TAP190_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP189_TAP190_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP189_TAP190_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP191_TAP192_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP191_TAP192_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP191_TAP192_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP191_TAP192_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP191_TAP192_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP191_TAP192_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP191_TAP192_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP191_TAP192_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP191_TAP192_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP191_TAP192_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP191_TAP192_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP191_TAP192_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP191_TAP192_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP191_TAP192_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP191_TAP192_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP191_TAP192_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_14TH_DSN_ID */ |
| #define AUDIO_DIG_14TH_ANA_ID_SFT 0 |
| #define AUDIO_DIG_14TH_ANA_ID_MASK 0xff |
| #define AUDIO_DIG_14TH_ANA_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_14TH_DSN_ID_H */ |
| #define AUDIO_DIG_14TH_DIG_ID_SFT 0 |
| #define AUDIO_DIG_14TH_DIG_ID_MASK 0xff |
| #define AUDIO_DIG_14TH_DIG_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_14TH_DSN_REV0 */ |
| #define AUDIO_DIG_14TH_ANA_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_14TH_ANA_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_14TH_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_14TH_ANA_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_14TH_ANA_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_14TH_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_14TH_DSN_REV0_H */ |
| #define AUDIO_DIG_14TH_DIG_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_14TH_DIG_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_14TH_DIG_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_14TH_DIG_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_14TH_DIG_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_14TH_DIG_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_14TH_DSN_DBI */ |
| #define AUDIO_DIG_14TH_DSN_CBS_SFT 0 |
| #define AUDIO_DIG_14TH_DSN_CBS_MASK 0x3 |
| #define AUDIO_DIG_14TH_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDIO_DIG_14TH_DSN_BIX_SFT 2 |
| #define AUDIO_DIG_14TH_DSN_BIX_MASK 0x3 |
| #define AUDIO_DIG_14TH_DSN_BIX_MASK_SFT (0x3 << 2) |
| |
| /* AUDIO_DIG_14TH_DSN_DBI_H */ |
| #define AUDIO_DIG_14_ESP_SFT 0 |
| #define AUDIO_DIG_14_ESP_MASK 0xff |
| #define AUDIO_DIG_14_ESP_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_14TH_DSN_DXI */ |
| #define AUDIO_DIG_14TH_DSN_FPI_SFT 0 |
| #define AUDIO_DIG_14TH_DSN_FPI_MASK 0xff |
| #define AUDIO_DIG_14TH_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SW_CONFIG_SFT 7 |
| #define AFE_2ND_DL_HBF1_SW_CONFIG_MASK 0x1 |
| #define AFE_2ND_DL_HBF1_SW_CONFIG_MASK_SFT (0x1 << 7) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_TAPNUM_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_TAPNUM_CONFIG_MASK 0x7f |
| #define AFE_2ND_DL_HBF1_TAPNUM_CONFIG_MASK_SFT (0x7f << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_SW_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_SW_CONFIG_MASK 0x1 |
| #define AFE_2ND_DL_SCF1_SW_CONFIG_MASK_SFT (0x1 << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAPNUM_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAPNUM_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAPNUM_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP1_TAP2_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP1_TAP2_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP3_TAP4_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP3_TAP4_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP5_TAP6_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP5_TAP6_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP7_TAP8_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP7_TAP8_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP9_TAP10_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP9_TAP10_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP11_TAP12_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP11_TAP12_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP13_TAP14_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP13_TAP14_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP15_TAP16_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP15_TAP16_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP17_TAP18_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP17_TAP18_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP19_TAP20_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP19_TAP20_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP21_TAP22_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP21_TAP22_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP23_TAP24_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP23_TAP24_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP25_TAP26_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP25_TAP26_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP27_TAP28_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP27_TAP28_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP29_TAP30_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP29_TAP30_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP31_TAP32_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP31_TAP32_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP33_TAP34_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP33_TAP34_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP35_TAP36_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP35_TAP36_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP37_TAP38_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP37_TAP38_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP39_TAP40_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP39_TAP40_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP41_TAP42_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP41_TAP42_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP43_TAP44_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP43_TAP44_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP45_TAP46_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP45_TAP46_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP47_TAP48_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP47_TAP48_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP49_TAP50_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP49_TAP50_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP51_TAP52_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP51_TAP52_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP53_TAP54_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP53_TAP54_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_H */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_M */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_L */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_HBF1_SCF1_TAP55_TAP56_CONFIG */ |
| #define AFE_2ND_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_SFT 0 |
| #define AFE_2ND_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_HBF1_SCF1_TAP55_TAP56_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP57_TAP58_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP57_TAP58_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP57_TAP58_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP57_TAP58_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP57_TAP58_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP57_TAP58_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP57_TAP58_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP57_TAP58_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP57_TAP58_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP57_TAP58_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP57_TAP58_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP57_TAP58_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP57_TAP58_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP57_TAP58_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP57_TAP58_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP57_TAP58_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_15TH_DSN_ID */ |
| #define AUDIO_DIG_15TH_ANA_ID_SFT 0 |
| #define AUDIO_DIG_15TH_ANA_ID_MASK 0xff |
| #define AUDIO_DIG_15TH_ANA_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_15TH_DSN_ID_H */ |
| #define AUDIO_DIG_15TH_DIG_ID_SFT 0 |
| #define AUDIO_DIG_15TH_DIG_ID_MASK 0xff |
| #define AUDIO_DIG_15TH_DIG_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_15TH_DSN_REV0 */ |
| #define AUDIO_DIG_15TH_ANA_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_15TH_ANA_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_15TH_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_15TH_ANA_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_15TH_ANA_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_15TH_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_15TH_DSN_REV0_H */ |
| #define AUDIO_DIG_15TH_DIG_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_15TH_DIG_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_15TH_DIG_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_15TH_DIG_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_15TH_DIG_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_15TH_DIG_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_15TH_DSN_DBI */ |
| #define AUDIO_DIG_15TH_DSN_CBS_SFT 0 |
| #define AUDIO_DIG_15TH_DSN_CBS_MASK 0x3 |
| #define AUDIO_DIG_15TH_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDIO_DIG_15TH_DSN_BIX_SFT 2 |
| #define AUDIO_DIG_15TH_DSN_BIX_MASK 0x3 |
| #define AUDIO_DIG_15TH_DSN_BIX_MASK_SFT (0x3 << 2) |
| |
| /* AUDIO_DIG_15TH_DSN_DBI_H */ |
| #define AUDIO_DIG_15_ESP_SFT 0 |
| #define AUDIO_DIG_15_ESP_MASK 0xff |
| #define AUDIO_DIG_15_ESP_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_15TH_DSN_DXI */ |
| #define AUDIO_DIG_15TH_DSN_FPI_SFT 0 |
| #define AUDIO_DIG_15TH_DSN_FPI_MASK 0xff |
| #define AUDIO_DIG_15TH_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP59_TAP60_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP59_TAP60_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP59_TAP60_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP59_TAP60_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP59_TAP60_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP59_TAP60_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP59_TAP60_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP59_TAP60_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP59_TAP60_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP59_TAP60_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP59_TAP60_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP59_TAP60_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP59_TAP60_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP59_TAP60_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP59_TAP60_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP59_TAP60_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP61_TAP62_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP61_TAP62_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP61_TAP62_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP61_TAP62_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP61_TAP62_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP61_TAP62_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP61_TAP62_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP61_TAP62_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP61_TAP62_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP61_TAP62_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP61_TAP62_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP61_TAP62_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP61_TAP62_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP61_TAP62_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP61_TAP62_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP61_TAP62_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP63_TAP64_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP63_TAP64_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP63_TAP64_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP63_TAP64_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP63_TAP64_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP63_TAP64_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP63_TAP64_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP63_TAP64_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP63_TAP64_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP63_TAP64_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP63_TAP64_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP63_TAP64_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP63_TAP64_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP63_TAP64_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP63_TAP64_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP63_TAP64_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP65_TAP66_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP65_TAP66_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP65_TAP66_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP65_TAP66_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP65_TAP66_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP65_TAP66_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP65_TAP66_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP65_TAP66_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP65_TAP66_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP65_TAP66_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP65_TAP66_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP65_TAP66_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP65_TAP66_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP65_TAP66_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP65_TAP66_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP65_TAP66_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP67_TAP68_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP67_TAP68_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP67_TAP68_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP67_TAP68_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP67_TAP68_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP67_TAP68_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP67_TAP68_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP67_TAP68_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP67_TAP68_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP67_TAP68_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP67_TAP68_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP67_TAP68_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP67_TAP68_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP67_TAP68_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP67_TAP68_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP67_TAP68_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP69_TAP70_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP69_TAP70_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP69_TAP70_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP69_TAP70_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP69_TAP70_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP69_TAP70_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP69_TAP70_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP69_TAP70_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP69_TAP70_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP69_TAP70_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP69_TAP70_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP69_TAP70_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP69_TAP70_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP69_TAP70_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP69_TAP70_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP69_TAP70_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP71_TAP72_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP71_TAP72_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP71_TAP72_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP71_TAP72_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP71_TAP72_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP71_TAP72_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP71_TAP72_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP71_TAP72_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP71_TAP72_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP71_TAP72_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP71_TAP72_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP71_TAP72_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP71_TAP72_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP71_TAP72_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP71_TAP72_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP71_TAP72_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP73_TAP74_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP73_TAP74_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP73_TAP74_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP73_TAP74_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP73_TAP74_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP73_TAP74_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP73_TAP74_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP73_TAP74_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP73_TAP74_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP73_TAP74_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP73_TAP74_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP73_TAP74_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP73_TAP74_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP73_TAP74_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP73_TAP74_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP73_TAP74_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP75_TAP76_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP75_TAP76_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP75_TAP76_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP75_TAP76_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP75_TAP76_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP75_TAP76_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP75_TAP76_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP75_TAP76_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP75_TAP76_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP75_TAP76_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP75_TAP76_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP75_TAP76_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP75_TAP76_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP75_TAP76_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP75_TAP76_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP75_TAP76_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP77_TAP78_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP77_TAP78_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP77_TAP78_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP77_TAP78_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP77_TAP78_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP77_TAP78_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP77_TAP78_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP77_TAP78_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP77_TAP78_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP77_TAP78_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP77_TAP78_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP77_TAP78_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP77_TAP78_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP77_TAP78_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP77_TAP78_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP77_TAP78_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP79_TAP80_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP79_TAP80_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP79_TAP80_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP79_TAP80_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP79_TAP80_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP79_TAP80_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP79_TAP80_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP79_TAP80_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP79_TAP80_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP79_TAP80_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP79_TAP80_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP79_TAP80_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP79_TAP80_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP79_TAP80_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP79_TAP80_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP79_TAP80_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP81_TAP82_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP81_TAP82_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP81_TAP82_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP81_TAP82_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP81_TAP82_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP81_TAP82_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP81_TAP82_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP81_TAP82_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP81_TAP82_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP81_TAP82_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP81_TAP82_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP81_TAP82_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP81_TAP82_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP81_TAP82_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP81_TAP82_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP81_TAP82_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP83_TAP84_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP83_TAP84_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP83_TAP84_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP83_TAP84_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP83_TAP84_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP83_TAP84_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP83_TAP84_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP83_TAP84_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP83_TAP84_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP83_TAP84_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP83_TAP84_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP83_TAP84_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP83_TAP84_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP83_TAP84_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP83_TAP84_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP83_TAP84_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP85_TAP86_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP85_TAP86_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP85_TAP86_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP85_TAP86_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP85_TAP86_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP85_TAP86_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP85_TAP86_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP85_TAP86_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP85_TAP86_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP85_TAP86_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP85_TAP86_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP85_TAP86_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP85_TAP86_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP85_TAP86_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP85_TAP86_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP85_TAP86_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP87_TAP88_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP87_TAP88_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP87_TAP88_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP87_TAP88_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP87_TAP88_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP87_TAP88_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP87_TAP88_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP87_TAP88_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP87_TAP88_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP87_TAP88_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP87_TAP88_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP87_TAP88_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP87_TAP88_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP87_TAP88_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP87_TAP88_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP87_TAP88_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP89_TAP90_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP89_TAP90_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP89_TAP90_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP89_TAP90_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP89_TAP90_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP89_TAP90_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP89_TAP90_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP89_TAP90_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP89_TAP90_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP89_TAP90_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP89_TAP90_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP89_TAP90_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP89_TAP90_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP89_TAP90_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP89_TAP90_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP89_TAP90_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP91_TAP92_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP91_TAP92_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP91_TAP92_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP91_TAP92_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP91_TAP92_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP91_TAP92_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP91_TAP92_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP91_TAP92_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP91_TAP92_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP91_TAP92_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP91_TAP92_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP91_TAP92_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP91_TAP92_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP91_TAP92_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP91_TAP92_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP91_TAP92_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP93_TAP94_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP93_TAP94_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP93_TAP94_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP93_TAP94_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP93_TAP94_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP93_TAP94_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP93_TAP94_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP93_TAP94_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP93_TAP94_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP93_TAP94_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP93_TAP94_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP93_TAP94_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP93_TAP94_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP93_TAP94_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP93_TAP94_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP93_TAP94_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP95_TAP96_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP95_TAP96_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP95_TAP96_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP95_TAP96_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP95_TAP96_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP95_TAP96_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP95_TAP96_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP95_TAP96_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP95_TAP96_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP95_TAP96_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP95_TAP96_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP95_TAP96_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP95_TAP96_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP95_TAP96_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP95_TAP96_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP95_TAP96_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP97_TAP98_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP97_TAP98_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP97_TAP98_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP97_TAP98_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP97_TAP98_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP97_TAP98_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP97_TAP98_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP97_TAP98_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP97_TAP98_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP97_TAP98_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP97_TAP98_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP97_TAP98_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP97_TAP98_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP97_TAP98_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP97_TAP98_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP97_TAP98_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP99_TAP100_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP99_TAP100_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP99_TAP100_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP99_TAP100_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP99_TAP100_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP99_TAP100_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP99_TAP100_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP99_TAP100_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP99_TAP100_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP99_TAP100_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP99_TAP100_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP99_TAP100_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP99_TAP100_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP99_TAP100_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP99_TAP100_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP99_TAP100_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP101_TAP102_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP101_TAP102_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP101_TAP102_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP101_TAP102_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP101_TAP102_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP101_TAP102_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP101_TAP102_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP101_TAP102_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP101_TAP102_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP101_TAP102_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP101_TAP102_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP101_TAP102_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP101_TAP102_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP101_TAP102_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP101_TAP102_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP101_TAP102_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP103_TAP104_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP103_TAP104_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP103_TAP104_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP103_TAP104_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP103_TAP104_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP103_TAP104_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP103_TAP104_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP103_TAP104_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP103_TAP104_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP103_TAP104_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP103_TAP104_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP103_TAP104_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP103_TAP104_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP103_TAP104_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP103_TAP104_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP103_TAP104_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP105_TAP106_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP105_TAP106_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP105_TAP106_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP105_TAP106_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP105_TAP106_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP105_TAP106_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP105_TAP106_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP105_TAP106_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP105_TAP106_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP105_TAP106_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP105_TAP106_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP105_TAP106_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP105_TAP106_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP105_TAP106_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP105_TAP106_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP105_TAP106_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP107_TAP108_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP107_TAP108_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP107_TAP108_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP107_TAP108_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP107_TAP108_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP107_TAP108_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP107_TAP108_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP107_TAP108_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP107_TAP108_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP107_TAP108_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP107_TAP108_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP107_TAP108_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP107_TAP108_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP107_TAP108_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP107_TAP108_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP107_TAP108_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP109_TAP110_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP109_TAP110_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP109_TAP110_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP109_TAP110_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP109_TAP110_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP109_TAP110_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP109_TAP110_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP109_TAP110_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP109_TAP110_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP109_TAP110_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP109_TAP110_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP109_TAP110_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP109_TAP110_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP109_TAP110_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP109_TAP110_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP109_TAP110_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP111_TAP112_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP111_TAP112_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP111_TAP112_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP111_TAP112_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP111_TAP112_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP111_TAP112_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP111_TAP112_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP111_TAP112_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP111_TAP112_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP111_TAP112_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP111_TAP112_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP111_TAP112_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP111_TAP112_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP111_TAP112_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP111_TAP112_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP111_TAP112_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP113_TAP114_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP113_TAP114_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP113_TAP114_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP113_TAP114_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP113_TAP114_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP113_TAP114_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP113_TAP114_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP113_TAP114_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP113_TAP114_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP113_TAP114_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP113_TAP114_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP113_TAP114_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP113_TAP114_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP113_TAP114_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP113_TAP114_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP113_TAP114_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP115_TAP116_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP115_TAP116_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP115_TAP116_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP115_TAP116_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP115_TAP116_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP115_TAP116_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP115_TAP116_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP115_TAP116_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP115_TAP116_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP115_TAP116_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP115_TAP116_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP115_TAP116_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP115_TAP116_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP115_TAP116_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP115_TAP116_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP115_TAP116_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP117_TAP118_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP117_TAP118_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP117_TAP118_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP117_TAP118_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP117_TAP118_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP117_TAP118_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP117_TAP118_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP117_TAP118_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP117_TAP118_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP117_TAP118_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP117_TAP118_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP117_TAP118_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP117_TAP118_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP117_TAP118_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP117_TAP118_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP117_TAP118_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_16TH_DSN_ID */ |
| #define AUDIO_DIG_16TH_ANA_ID_SFT 0 |
| #define AUDIO_DIG_16TH_ANA_ID_MASK 0xff |
| #define AUDIO_DIG_16TH_ANA_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_16TH_DSN_ID_H */ |
| #define AUDIO_DIG_16TH_DIG_ID_SFT 0 |
| #define AUDIO_DIG_16TH_DIG_ID_MASK 0xff |
| #define AUDIO_DIG_16TH_DIG_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_16TH_DSN_REV0 */ |
| #define AUDIO_DIG_16TH_ANA_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_16TH_ANA_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_16TH_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_16TH_ANA_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_16TH_ANA_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_16TH_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_16TH_DSN_REV0_H */ |
| #define AUDIO_DIG_16TH_DIG_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_16TH_DIG_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_16TH_DIG_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_16TH_DIG_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_16TH_DIG_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_16TH_DIG_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_16TH_DSN_DBI */ |
| #define AUDIO_DIG_16TH_DSN_CBS_SFT 0 |
| #define AUDIO_DIG_16TH_DSN_CBS_MASK 0x3 |
| #define AUDIO_DIG_16TH_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDIO_DIG_16TH_DSN_BIX_SFT 2 |
| #define AUDIO_DIG_16TH_DSN_BIX_MASK 0x3 |
| #define AUDIO_DIG_16TH_DSN_BIX_MASK_SFT (0x3 << 2) |
| |
| /* AUDIO_DIG_16TH_DSN_DBI_H */ |
| #define AUDIO_DIG_16_ESP_SFT 0 |
| #define AUDIO_DIG_16_ESP_MASK 0xff |
| #define AUDIO_DIG_16_ESP_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_16TH_DSN_DXI */ |
| #define AUDIO_DIG_16TH_DSN_FPI_SFT 0 |
| #define AUDIO_DIG_16TH_DSN_FPI_MASK 0xff |
| #define AUDIO_DIG_16TH_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP119_TAP120_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP119_TAP120_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP119_TAP120_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP119_TAP120_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP119_TAP120_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP119_TAP120_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP119_TAP120_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP119_TAP120_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP119_TAP120_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP119_TAP120_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP119_TAP120_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP119_TAP120_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP119_TAP120_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP119_TAP120_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP119_TAP120_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP119_TAP120_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP121_TAP122_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP121_TAP122_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP121_TAP122_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP121_TAP122_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP121_TAP122_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP121_TAP122_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP121_TAP122_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP121_TAP122_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP121_TAP122_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP121_TAP122_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP121_TAP122_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP121_TAP122_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP121_TAP122_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP121_TAP122_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP121_TAP122_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP121_TAP122_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP123_TAP124_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP123_TAP124_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP123_TAP124_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP123_TAP124_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP123_TAP124_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP123_TAP124_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP123_TAP124_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP123_TAP124_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP123_TAP124_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP123_TAP124_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP123_TAP124_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP123_TAP124_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP123_TAP124_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP123_TAP124_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP123_TAP124_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP123_TAP124_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP125_TAP126_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP125_TAP126_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP125_TAP126_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP125_TAP126_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP125_TAP126_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP125_TAP126_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP125_TAP126_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP125_TAP126_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP125_TAP126_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP125_TAP126_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP125_TAP126_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP125_TAP126_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP125_TAP126_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP125_TAP126_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP125_TAP126_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP125_TAP126_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP127_TAP128_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP127_TAP128_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP127_TAP128_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP127_TAP128_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP127_TAP128_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP127_TAP128_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP127_TAP128_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP127_TAP128_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP127_TAP128_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP127_TAP128_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP127_TAP128_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP127_TAP128_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP127_TAP128_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP127_TAP128_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP127_TAP128_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP127_TAP128_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP129_TAP130_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP129_TAP130_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP129_TAP130_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP129_TAP130_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP129_TAP130_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP129_TAP130_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP129_TAP130_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP129_TAP130_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP129_TAP130_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP129_TAP130_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP129_TAP130_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP129_TAP130_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP129_TAP130_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP129_TAP130_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP129_TAP130_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP129_TAP130_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP131_TAP132_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP131_TAP132_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP131_TAP132_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP131_TAP132_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP131_TAP132_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP131_TAP132_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP131_TAP132_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP131_TAP132_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP131_TAP132_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP131_TAP132_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP131_TAP132_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP131_TAP132_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP131_TAP132_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP131_TAP132_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP131_TAP132_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP131_TAP132_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP133_TAP134_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP133_TAP134_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP133_TAP134_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP133_TAP134_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP133_TAP134_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP133_TAP134_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP133_TAP134_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP133_TAP134_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP133_TAP134_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP133_TAP134_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP133_TAP134_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP133_TAP134_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP133_TAP134_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP133_TAP134_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP133_TAP134_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP133_TAP134_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP135_TAP136_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP135_TAP136_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP135_TAP136_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP135_TAP136_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP135_TAP136_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP135_TAP136_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP135_TAP136_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP135_TAP136_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP135_TAP136_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP135_TAP136_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP135_TAP136_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP135_TAP136_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP135_TAP136_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP135_TAP136_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP135_TAP136_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP135_TAP136_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP137_TAP138_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP137_TAP138_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP137_TAP138_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP137_TAP138_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP137_TAP138_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP137_TAP138_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP137_TAP138_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP137_TAP138_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP137_TAP138_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP137_TAP138_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP137_TAP138_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP137_TAP138_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP137_TAP138_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP137_TAP138_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP137_TAP138_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP137_TAP138_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP139_TAP140_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP139_TAP140_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP139_TAP140_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP139_TAP140_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP139_TAP140_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP139_TAP140_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP139_TAP140_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP139_TAP140_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP139_TAP140_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP139_TAP140_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP139_TAP140_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP139_TAP140_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP139_TAP140_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP139_TAP140_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP139_TAP140_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP139_TAP140_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP141_TAP142_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP141_TAP142_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP141_TAP142_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP141_TAP142_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP141_TAP142_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP141_TAP142_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP141_TAP142_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP141_TAP142_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP141_TAP142_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP141_TAP142_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP141_TAP142_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP141_TAP142_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP141_TAP142_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP141_TAP142_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP141_TAP142_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP141_TAP142_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP143_TAP144_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP143_TAP144_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP143_TAP144_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP143_TAP144_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP143_TAP144_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP143_TAP144_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP143_TAP144_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP143_TAP144_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP143_TAP144_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP143_TAP144_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP143_TAP144_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP143_TAP144_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP143_TAP144_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP143_TAP144_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP143_TAP144_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP143_TAP144_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP145_TAP146_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP145_TAP146_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP145_TAP146_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP145_TAP146_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP145_TAP146_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP145_TAP146_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP145_TAP146_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP145_TAP146_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP145_TAP146_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP145_TAP146_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP145_TAP146_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP145_TAP146_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP145_TAP146_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP145_TAP146_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP145_TAP146_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP145_TAP146_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP147_TAP148_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP147_TAP148_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP147_TAP148_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP147_TAP148_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP147_TAP148_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP147_TAP148_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP147_TAP148_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP147_TAP148_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP147_TAP148_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP147_TAP148_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP147_TAP148_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP147_TAP148_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP147_TAP148_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP147_TAP148_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP147_TAP148_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP147_TAP148_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP149_TAP150_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP149_TAP150_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP149_TAP150_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP149_TAP150_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP149_TAP150_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP149_TAP150_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP149_TAP150_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP149_TAP150_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP149_TAP150_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP149_TAP150_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP149_TAP150_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP149_TAP150_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP149_TAP150_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP149_TAP150_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP149_TAP150_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP149_TAP150_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP151_TAP152_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP151_TAP152_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP151_TAP152_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP151_TAP152_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP151_TAP152_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP151_TAP152_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP151_TAP152_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP151_TAP152_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP151_TAP152_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP151_TAP152_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP151_TAP152_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP151_TAP152_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP151_TAP152_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP151_TAP152_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP151_TAP152_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP151_TAP152_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP153_TAP154_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP153_TAP154_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP153_TAP154_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP153_TAP154_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP153_TAP154_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP153_TAP154_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP153_TAP154_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP153_TAP154_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP153_TAP154_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP153_TAP154_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP153_TAP154_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP153_TAP154_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP153_TAP154_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP153_TAP154_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP153_TAP154_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP153_TAP154_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP155_TAP156_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP155_TAP156_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP155_TAP156_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP155_TAP156_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP155_TAP156_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP155_TAP156_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP155_TAP156_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP155_TAP156_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP155_TAP156_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP155_TAP156_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP155_TAP156_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP155_TAP156_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP155_TAP156_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP155_TAP156_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP155_TAP156_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP155_TAP156_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP157_TAP158_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP157_TAP158_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP157_TAP158_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP157_TAP158_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP157_TAP158_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP157_TAP158_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP157_TAP158_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP157_TAP158_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP157_TAP158_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP157_TAP158_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP157_TAP158_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP157_TAP158_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP157_TAP158_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP157_TAP158_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP157_TAP158_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP157_TAP158_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP159_TAP160_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP159_TAP160_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP159_TAP160_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP159_TAP160_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP159_TAP160_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP159_TAP160_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP159_TAP160_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP159_TAP160_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP159_TAP160_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP159_TAP160_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP159_TAP160_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP159_TAP160_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP159_TAP160_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP159_TAP160_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP159_TAP160_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP159_TAP160_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP161_TAP162_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP161_TAP162_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP161_TAP162_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP161_TAP162_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP161_TAP162_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP161_TAP162_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP161_TAP162_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP161_TAP162_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP161_TAP162_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP161_TAP162_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP161_TAP162_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP161_TAP162_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP161_TAP162_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP161_TAP162_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP161_TAP162_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP161_TAP162_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP163_TAP164_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP163_TAP164_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP163_TAP164_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP163_TAP164_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP163_TAP164_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP163_TAP164_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP163_TAP164_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP163_TAP164_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP163_TAP164_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP163_TAP164_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP163_TAP164_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP163_TAP164_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP163_TAP164_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP163_TAP164_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP163_TAP164_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP163_TAP164_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP165_TAP166_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP165_TAP166_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP165_TAP166_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP165_TAP166_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP165_TAP166_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP165_TAP166_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP165_TAP166_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP165_TAP166_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP165_TAP166_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP165_TAP166_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP165_TAP166_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP165_TAP166_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP165_TAP166_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP165_TAP166_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP165_TAP166_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP165_TAP166_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP167_TAP168_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP167_TAP168_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP167_TAP168_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP167_TAP168_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP167_TAP168_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP167_TAP168_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP167_TAP168_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP167_TAP168_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP167_TAP168_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP167_TAP168_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP167_TAP168_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP167_TAP168_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP167_TAP168_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP167_TAP168_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP167_TAP168_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP167_TAP168_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP169_TAP170_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP169_TAP170_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP169_TAP170_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP169_TAP170_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP169_TAP170_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP169_TAP170_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP169_TAP170_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP169_TAP170_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP169_TAP170_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP169_TAP170_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP169_TAP170_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP169_TAP170_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP169_TAP170_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP169_TAP170_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP169_TAP170_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP169_TAP170_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP171_TAP172_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP171_TAP172_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP171_TAP172_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP171_TAP172_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP171_TAP172_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP171_TAP172_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP171_TAP172_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP171_TAP172_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP171_TAP172_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP171_TAP172_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP171_TAP172_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP171_TAP172_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP171_TAP172_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP171_TAP172_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP171_TAP172_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP171_TAP172_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP173_TAP174_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP173_TAP174_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP173_TAP174_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP173_TAP174_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP173_TAP174_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP173_TAP174_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP173_TAP174_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP173_TAP174_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP173_TAP174_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP173_TAP174_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP173_TAP174_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP173_TAP174_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP173_TAP174_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP173_TAP174_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP173_TAP174_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP173_TAP174_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP175_TAP176_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP175_TAP176_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP175_TAP176_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP175_TAP176_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP175_TAP176_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP175_TAP176_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP175_TAP176_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP175_TAP176_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP175_TAP176_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP175_TAP176_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP175_TAP176_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP175_TAP176_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP175_TAP176_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP175_TAP176_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP175_TAP176_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP175_TAP176_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP177_TAP178_CONFIG_H */ |
| #define AFE_2ND_DL_SCF1_TAP177_TAP178_CONFIG_H_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP177_TAP178_CONFIG_H_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP177_TAP178_CONFIG_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP177_TAP178_CONFIG_M */ |
| #define AFE_2ND_DL_SCF1_TAP177_TAP178_CONFIG_M_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP177_TAP178_CONFIG_M_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP177_TAP178_CONFIG_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP177_TAP178_CONFIG_L */ |
| #define AFE_2ND_DL_SCF1_TAP177_TAP178_CONFIG_L_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP177_TAP178_CONFIG_L_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP177_TAP178_CONFIG_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_2ND_DL_SCF1_TAP177_TAP178_CONFIG */ |
| #define AFE_2ND_DL_SCF1_TAP177_TAP178_CONFIG_SFT 0 |
| #define AFE_2ND_DL_SCF1_TAP177_TAP178_CONFIG_MASK 0xff |
| #define AFE_2ND_DL_SCF1_TAP177_TAP178_CONFIG_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_17TH_DSN_ID */ |
| #define AUDIO_DIG_17TH_ANA_ID_SFT 0 |
| #define AUDIO_DIG_17TH_ANA_ID_MASK 0xff |
| #define AUDIO_DIG_17TH_ANA_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_17TH_DSN_ID_H */ |
| #define AUDIO_DIG_17TH_DIG_ID_SFT 0 |
| #define AUDIO_DIG_17TH_DIG_ID_MASK 0xff |
| #define AUDIO_DIG_17TH_DIG_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_17TH_DSN_REV0 */ |
| #define AUDIO_DIG_17TH_ANA_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_17TH_ANA_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_17TH_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_17TH_ANA_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_17TH_ANA_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_17TH_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_17TH_DSN_REV0_H */ |
| #define AUDIO_DIG_17TH_DIG_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_17TH_DIG_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_17TH_DIG_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_17TH_DIG_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_17TH_DIG_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_17TH_DIG_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_17TH_DSN_DBI */ |
| #define AUDIO_DIG_17TH_DSN_CBS_SFT 0 |
| #define AUDIO_DIG_17TH_DSN_CBS_MASK 0x3 |
| #define AUDIO_DIG_17TH_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDIO_DIG_17TH_DSN_BIX_SFT 2 |
| #define AUDIO_DIG_17TH_DSN_BIX_MASK 0x3 |
| #define AUDIO_DIG_17TH_DSN_BIX_MASK_SFT (0x3 << 2) |
| |
| /* AUDIO_DIG_17TH_DSN_DBI_H */ |
| #define AUDIO_DIG_17_ESP_SFT 0 |
| #define AUDIO_DIG_17_ESP_MASK 0xff |
| #define AUDIO_DIG_17_ESP_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_17TH_DSN_DXI */ |
| #define AUDIO_DIG_17TH_DSN_FPI_SFT 0 |
| #define AUDIO_DIG_17TH_DSN_FPI_MASK 0xff |
| #define AUDIO_DIG_17TH_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_VAD_PBUF_MON_SEL */ |
| #define RG_VAD_PBUF_MON_SEL_SFT 0 |
| #define RG_VAD_PBUF_MON_SEL_MASK 0xff |
| #define RG_VAD_PBUF_MON_SEL_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_VAD_PBUF_MON_L */ |
| #define RG_VAD_PBUF_MON_L_SFT 0 |
| #define RG_VAD_PBUF_MON_L_MASK 0xff |
| #define RG_VAD_PBUF_MON_L_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_VAD_PBUF_MON_H */ |
| #define RG_VAD_PBUF_MON_H_SFT 0 |
| #define RG_VAD_PBUF_MON_H_MASK 0xff |
| #define RG_VAD_PBUF_MON_H_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_VAD_PBUF_CON0 */ |
| #define RG_VAD_PBUF_READ_BURST_EN_SFT 7 |
| #define RG_VAD_PBUF_READ_BURST_EN_MASK 0x1 |
| #define RG_VAD_PBUF_READ_BURST_EN_MASK_SFT (0x1 << 7) |
| #define RG_VAD_CH_NUM_SFT 4 |
| #define RG_VAD_CH_NUM_MASK 0x3 |
| #define RG_VAD_CH_NUM_MASK_SFT (0x3 << 4) |
| #define RG_VAD_RPTR_INITIAL_SFT 2 |
| #define RG_VAD_RPTR_INITIAL_MASK 0x1 |
| #define RG_VAD_RPTR_INITIAL_MASK_SFT (0x1 << 2) |
| #define RG_VAD_BYTE_SWAP_SFT 1 |
| #define RG_VAD_BYTE_SWAP_MASK 0x1 |
| #define RG_VAD_BYTE_SWAP_MASK_SFT (0x1 << 1) |
| #define RG_VAD_PBUF_ON_SFT 0 |
| #define RG_VAD_PBUF_ON_MASK 0x1 |
| #define RG_VAD_PBUF_ON_MASK_SFT (0x1 << 0) |
| |
| /* AUDIO_VAD_PBUF_CON1 */ |
| #define RG_VAD_CH3_DATA_SEL_SFT 6 |
| #define RG_VAD_CH3_DATA_SEL_MASK 0x3 |
| #define RG_VAD_CH3_DATA_SEL_MASK_SFT (0x3 << 6) |
| #define RG_VAD_CH2_DATA_SEL_SFT 4 |
| #define RG_VAD_CH2_DATA_SEL_MASK 0x3 |
| #define RG_VAD_CH2_DATA_SEL_MASK_SFT (0x3 << 4) |
| #define RG_VAD_CH1_DATA_SEL_SFT 2 |
| #define RG_VAD_CH1_DATA_SEL_MASK 0x3 |
| #define RG_VAD_CH1_DATA_SEL_MASK_SFT (0x3 << 2) |
| #define RG_VAD_CH0_DATA_SEL_SFT 0 |
| #define RG_VAD_CH0_DATA_SEL_MASK 0x3 |
| #define RG_VAD_CH0_DATA_SEL_MASK_SFT (0x3 << 0) |
| |
| /* AUDIO_VAD_PBUF_CON2_L */ |
| #define RG_VAD_UPDATE_CNT_L_SFT 0 |
| #define RG_VAD_UPDATE_CNT_L_MASK 0xff |
| #define RG_VAD_UPDATE_CNT_L_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_VAD_PBUF_CON2_H */ |
| #define RG_VAD_UPDATE_CNT_H_SFT 0 |
| #define RG_VAD_UPDATE_CNT_H_MASK 0xff |
| #define RG_VAD_UPDATE_CNT_H_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_VAD_PBUF_CON3_L */ |
| #define RG_VAD_SRAM_SIZE_L_SFT 0 |
| #define RG_VAD_SRAM_SIZE_L_MASK 0xff |
| #define RG_VAD_SRAM_SIZE_L_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_VAD_PBUF_CON3_H */ |
| #define RG_VAD_SRAM_SIZE_H_SFT 0 |
| #define RG_VAD_SRAM_SIZE_H_MASK 0xff |
| #define RG_VAD_SRAM_SIZE_H_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_VAD_PBUF_CON4_L */ |
| #define RG_VAD_SRAM_RSP_L_SFT 0 |
| #define RG_VAD_SRAM_RSP_L_MASK 0xff |
| #define RG_VAD_SRAM_RSP_L_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_VAD_PBUF_CON4_H */ |
| #define RG_VAD_SRAM_RSP_H_SFT 0 |
| #define RG_VAD_SRAM_RSP_H_MASK 0xff |
| #define RG_VAD_SRAM_RSP_H_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_VAD_PBUF_CON5_L */ |
| #define RG_VAD_PBUF_FIFO_THD_L_SFT 0 |
| #define RG_VAD_PBUF_FIFO_THD_L_MASK 0xff |
| #define RG_VAD_PBUF_FIFO_THD_L_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_VAD_PBUF_CON5_H */ |
| #define RG_VAD_PBUF_FIFO_THD_H_SFT 0 |
| #define RG_VAD_PBUF_FIFO_THD_H_MASK 0xff |
| #define RG_VAD_PBUF_FIFO_THD_H_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_VAD_PBUF_CON6_L */ |
| #define RG_VAD_PBUF_BURST_READ_TIMES_L_SFT 0 |
| #define RG_VAD_PBUF_BURST_READ_TIMES_L_MASK 0xff |
| #define RG_VAD_PBUF_BURST_READ_TIMES_L_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_VAD_PBUF_CON6_H */ |
| #define RG_VAD_PBUF_BURST_READ_TIMES_H_SFT 0 |
| #define RG_VAD_PBUF_BURST_READ_TIMES_H_MASK 0xff |
| #define RG_VAD_PBUF_BURST_READ_TIMES_H_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_VAD_PBUF_WPTR_MON_L */ |
| #define RG_VAD_PBUF_WPTR_MON_L_SFT 0 |
| #define RG_VAD_PBUF_WPTR_MON_L_MASK 0xff |
| #define RG_VAD_PBUF_WPTR_MON_L_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_VAD_PBUF_WPTR_MON_H */ |
| #define RG_VAD_PBUF_WPTR_MON_H_SFT 0 |
| #define RG_VAD_PBUF_WPTR_MON_H_MASK 0xff |
| #define RG_VAD_PBUF_WPTR_MON_H_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_VAD_PBUF_RPTR_MON_L */ |
| #define RG_VAD_PBUF_RPTR_MON_L_SFT 0 |
| #define RG_VAD_PBUF_RPTR_MON_L_MASK 0xff |
| #define RG_VAD_PBUF_RPTR_MON_L_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_VAD_PBUF_RPTR_MON_H */ |
| #define RG_VAD_PBUF_RPTR_MON_H_SFT 0 |
| #define RG_VAD_PBUF_RPTR_MON_H_MASK 0xff |
| #define RG_VAD_PBUF_RPTR_MON_H_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_VAD_PBUF_RSV_L */ |
| #define RG_VAD_PBUF_RSV_L_SFT 0 |
| #define RG_VAD_PBUF_RSV_L_MASK 0xff |
| #define RG_VAD_PBUF_RSV_L_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_VAD_PBUF_RSV_H */ |
| #define RG_VAD_PBUF_RSV_H_SFT 0 |
| #define RG_VAD_PBUF_RSV_H_MASK 0xff |
| #define RG_VAD_PBUF_RSV_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_TOP_CON0 */ |
| #define PDN_VOW_SFT 7 |
| #define PDN_VOW_MASK 0x1 |
| #define PDN_VOW_MASK_SFT (0x1 << 7) |
| #define VOW_DMIC_CK_SEL_SFT 5 |
| #define VOW_DMIC_CK_SEL_MASK 0x3 |
| #define VOW_DMIC_CK_SEL_MASK_SFT (0x3 << 5) |
| #define MAIN_DMIC_CK_VOW_SEL_SFT 4 |
| #define MAIN_DMIC_CK_VOW_SEL_MASK 0x1 |
| #define MAIN_DMIC_CK_VOW_SEL_MASK_SFT (0x1 << 4) |
| #define VOW_CIC_MODE_SEL_SFT 2 |
| #define VOW_CIC_MODE_SEL_MASK 0x3 |
| #define VOW_CIC_MODE_SEL_MASK_SFT (0x3 << 2) |
| #define VOW_SDM_3_LEVEL_SFT 1 |
| #define VOW_SDM_3_LEVEL_MASK 0x1 |
| #define VOW_SDM_3_LEVEL_MASK_SFT (0x1 << 1) |
| #define VOW_LOOP_BACK_MODE_SFT 0 |
| #define VOW_LOOP_BACK_MODE_MASK 0x1 |
| #define VOW_LOOP_BACK_MODE_MASK_SFT (0x1 << 0) |
| |
| /* AFE_VOW_TOP_CON1 */ |
| #define VOW_INTR_SW_MODE_SFT 7 |
| #define VOW_INTR_SW_MODE_MASK 0x1 |
| #define VOW_INTR_SW_MODE_MASK_SFT (0x1 << 7) |
| #define VOW_INTR_SW_VAL_SFT 6 |
| #define VOW_INTR_SW_VAL_MASK 0x1 |
| #define VOW_INTR_SW_VAL_MASK_SFT (0x1 << 6) |
| #define RG_VOW_INTR_CH4_BIT_CTRL_SFT 3 |
| #define RG_VOW_INTR_CH4_BIT_CTRL_MASK 0x1 |
| #define RG_VOW_INTR_CH4_BIT_CTRL_MASK_SFT (0x1 << 3) |
| #define RG_VOW_INTR_CH3_BIT_CTRL_SFT 2 |
| #define RG_VOW_INTR_CH3_BIT_CTRL_MASK 0x1 |
| #define RG_VOW_INTR_CH3_BIT_CTRL_MASK_SFT (0x1 << 2) |
| #define RG_VOW_INTR_CH2_BIT_CTRL_SFT 1 |
| #define RG_VOW_INTR_CH2_BIT_CTRL_MASK 0x1 |
| #define RG_VOW_INTR_CH2_BIT_CTRL_MASK_SFT (0x1 << 1) |
| #define RG_VOW_INTR_CH1_BIT_CTRL_SFT 0 |
| #define RG_VOW_INTR_CH1_BIT_CTRL_MASK 0x1 |
| #define RG_VOW_INTR_CH1_BIT_CTRL_MASK_SFT (0x1 << 0) |
| |
| /* AFE_VOW_TOP_CON2 */ |
| #define VOW_DMIC1_CK_PDN_SFT 7 |
| #define VOW_DMIC1_CK_PDN_MASK 0x1 |
| #define VOW_DMIC1_CK_PDN_MASK_SFT (0x1 << 7) |
| #define VOW_DIGMIC_ON_CH1_SFT 6 |
| #define VOW_DIGMIC_ON_CH1_MASK 0x1 |
| #define VOW_DIGMIC_ON_CH1_MASK_SFT (0x1 << 6) |
| #define VOW_CK_DIV_RST_CH1_SFT 5 |
| #define VOW_CK_DIV_RST_CH1_MASK 0x1 |
| #define VOW_CK_DIV_RST_CH1_MASK_SFT (0x1 << 5) |
| #define VOW_ADC_CK_PDN_CH1_SFT 4 |
| #define VOW_ADC_CK_PDN_CH1_MASK 0x1 |
| #define VOW_ADC_CK_PDN_CH1_MASK_SFT (0x1 << 4) |
| #define VOW_CK_PDN_CH1_SFT 3 |
| #define VOW_CK_PDN_CH1_MASK 0x1 |
| #define VOW_CK_PDN_CH1_MASK_SFT (0x1 << 3) |
| #define S_N_VALUE_RST_CH1_SFT 2 |
| #define S_N_VALUE_RST_CH1_MASK 0x1 |
| #define S_N_VALUE_RST_CH1_MASK_SFT (0x1 << 2) |
| #define SAMPLE_BASE_MODE_CH1_SFT 1 |
| #define SAMPLE_BASE_MODE_CH1_MASK 0x1 |
| #define SAMPLE_BASE_MODE_CH1_MASK_SFT (0x1 << 1) |
| #define VOW_ON_CH1_SFT 0 |
| #define VOW_ON_CH1_MASK 0x1 |
| #define VOW_ON_CH1_MASK_SFT (0x1 << 0) |
| |
| /* AFE_VOW_TOP_CON3 */ |
| #define VOW_ADC_CLK_INV_CH1_SFT 7 |
| #define VOW_ADC_CLK_INV_CH1_MASK 0x1 |
| #define VOW_ADC_CLK_INV_CH1_MASK_SFT (0x1 << 7) |
| #define VOW_INTR_SOURCE_SEL_CH1_SFT 6 |
| #define VOW_INTR_SOURCE_SEL_CH1_MASK 0x1 |
| #define VOW_INTR_SOURCE_SEL_CH1_MASK_SFT (0x1 << 6) |
| #define VOW_INTR_CLR_CH1_SFT 5 |
| #define VOW_INTR_CLR_CH1_MASK 0x1 |
| #define VOW_INTR_CLR_CH1_MASK_SFT (0x1 << 5) |
| #define VOW_DIGMIC_CK_PHASE_SEL_CH1_SFT 0 |
| #define VOW_DIGMIC_CK_PHASE_SEL_CH1_MASK 0x1f |
| #define VOW_DIGMIC_CK_PHASE_SEL_CH1_MASK_SFT (0x1f << 0) |
| |
| /* AFE_VOW_TOP_CON4 */ |
| #define VOW_DMIC2_CK_PDN_SFT 7 |
| #define VOW_DMIC2_CK_PDN_MASK 0x1 |
| #define VOW_DMIC2_CK_PDN_MASK_SFT (0x1 << 7) |
| #define VOW_DIGMIC_ON_CH2_SFT 6 |
| #define VOW_DIGMIC_ON_CH2_MASK 0x1 |
| #define VOW_DIGMIC_ON_CH2_MASK_SFT (0x1 << 6) |
| #define VOW_CK_DIV_RST_CH2_SFT 5 |
| #define VOW_CK_DIV_RST_CH2_MASK 0x1 |
| #define VOW_CK_DIV_RST_CH2_MASK_SFT (0x1 << 5) |
| #define VOW_ADC_CK_PDN_CH2_SFT 4 |
| #define VOW_ADC_CK_PDN_CH2_MASK 0x1 |
| #define VOW_ADC_CK_PDN_CH2_MASK_SFT (0x1 << 4) |
| #define VOW_CK_PDN_CH2_SFT 3 |
| #define VOW_CK_PDN_CH2_MASK 0x1 |
| #define VOW_CK_PDN_CH2_MASK_SFT (0x1 << 3) |
| #define S_N_VALUE_RST_CH2_SFT 2 |
| #define S_N_VALUE_RST_CH2_MASK 0x1 |
| #define S_N_VALUE_RST_CH2_MASK_SFT (0x1 << 2) |
| #define SAMPLE_BASE_MODE_CH2_SFT 1 |
| #define SAMPLE_BASE_MODE_CH2_MASK 0x1 |
| #define SAMPLE_BASE_MODE_CH2_MASK_SFT (0x1 << 1) |
| #define VOW_ON_CH2_SFT 0 |
| #define VOW_ON_CH2_MASK 0x1 |
| #define VOW_ON_CH2_MASK_SFT (0x1 << 0) |
| |
| /* AFE_VOW_TOP_CON5 */ |
| #define VOW_ADC_CLK_INV_CH2_SFT 7 |
| #define VOW_ADC_CLK_INV_CH2_MASK 0x1 |
| #define VOW_ADC_CLK_INV_CH2_MASK_SFT (0x1 << 7) |
| #define VOW_INTR_SOURCE_SEL_CH2_SFT 6 |
| #define VOW_INTR_SOURCE_SEL_CH2_MASK 0x1 |
| #define VOW_INTR_SOURCE_SEL_CH2_MASK_SFT (0x1 << 6) |
| #define VOW_INTR_CLR_CH2_SFT 5 |
| #define VOW_INTR_CLR_CH2_MASK 0x1 |
| #define VOW_INTR_CLR_CH2_MASK_SFT (0x1 << 5) |
| #define VOW_DIGMIC_CK_PHASE_SEL_CH2_SFT 0 |
| #define VOW_DIGMIC_CK_PHASE_SEL_CH2_MASK 0x1f |
| #define VOW_DIGMIC_CK_PHASE_SEL_CH2_MASK_SFT (0x1f << 0) |
| |
| /* AFE_VOW_TOP_CON6 */ |
| #define VOW_DMIC3_CK_PDN_SFT 7 |
| #define VOW_DMIC3_CK_PDN_MASK 0x1 |
| #define VOW_DMIC3_CK_PDN_MASK_SFT (0x1 << 7) |
| #define VOW_DIGMIC_ON_CH3_SFT 6 |
| #define VOW_DIGMIC_ON_CH3_MASK 0x1 |
| #define VOW_DIGMIC_ON_CH3_MASK_SFT (0x1 << 6) |
| #define VOW_CK_DIV_RST_CH3_SFT 5 |
| #define VOW_CK_DIV_RST_CH3_MASK 0x1 |
| #define VOW_CK_DIV_RST_CH3_MASK_SFT (0x1 << 5) |
| #define VOW_ADC_CK_PDN_CH3_SFT 4 |
| #define VOW_ADC_CK_PDN_CH3_MASK 0x1 |
| #define VOW_ADC_CK_PDN_CH3_MASK_SFT (0x1 << 4) |
| #define VOW_CK_PDN_CH3_SFT 3 |
| #define VOW_CK_PDN_CH3_MASK 0x1 |
| #define VOW_CK_PDN_CH3_MASK_SFT (0x1 << 3) |
| #define S_N_VALUE_RST_CH3_SFT 2 |
| #define S_N_VALUE_RST_CH3_MASK 0x1 |
| #define S_N_VALUE_RST_CH3_MASK_SFT (0x1 << 2) |
| #define SAMPLE_BASE_MODE_CH3_SFT 1 |
| #define SAMPLE_BASE_MODE_CH3_MASK 0x1 |
| #define SAMPLE_BASE_MODE_CH3_MASK_SFT (0x1 << 1) |
| #define VOW_ON_CH3_SFT 0 |
| #define VOW_ON_CH3_MASK 0x1 |
| #define VOW_ON_CH3_MASK_SFT (0x1 << 0) |
| |
| /* AFE_VOW_TOP_CON7 */ |
| #define VOW_ADC_CLK_INV_CH3_SFT 7 |
| #define VOW_ADC_CLK_INV_CH3_MASK 0x1 |
| #define VOW_ADC_CLK_INV_CH3_MASK_SFT (0x1 << 7) |
| #define VOW_INTR_SOURCE_SEL_CH3_SFT 6 |
| #define VOW_INTR_SOURCE_SEL_CH3_MASK 0x1 |
| #define VOW_INTR_SOURCE_SEL_CH3_MASK_SFT (0x1 << 6) |
| #define VOW_INTR_CLR_CH3_SFT 5 |
| #define VOW_INTR_CLR_CH3_MASK 0x1 |
| #define VOW_INTR_CLR_CH3_MASK_SFT (0x1 << 5) |
| #define VOW_DIGMIC_CK_PHASE_SEL_CH3_SFT 0 |
| #define VOW_DIGMIC_CK_PHASE_SEL_CH3_MASK 0x1f |
| #define VOW_DIGMIC_CK_PHASE_SEL_CH3_MASK_SFT (0x1f << 0) |
| |
| /* AFE_VOW_TOP_CON8 */ |
| #define VOW_DMIC4_CK_PDN_SFT 7 |
| #define VOW_DMIC4_CK_PDN_MASK 0x1 |
| #define VOW_DMIC4_CK_PDN_MASK_SFT (0x1 << 7) |
| #define VOW_DIGMIC_ON_CH4_SFT 6 |
| #define VOW_DIGMIC_ON_CH4_MASK 0x1 |
| #define VOW_DIGMIC_ON_CH4_MASK_SFT (0x1 << 6) |
| #define VOW_CK_DIV_RST_CH4_SFT 5 |
| #define VOW_CK_DIV_RST_CH4_MASK 0x1 |
| #define VOW_CK_DIV_RST_CH4_MASK_SFT (0x1 << 5) |
| #define VOW_ADC_CK_PDN_CH4_SFT 4 |
| #define VOW_ADC_CK_PDN_CH4_MASK 0x1 |
| #define VOW_ADC_CK_PDN_CH4_MASK_SFT (0x1 << 4) |
| #define VOW_CK_PDN_CH4_SFT 3 |
| #define VOW_CK_PDN_CH4_MASK 0x1 |
| #define VOW_CK_PDN_CH4_MASK_SFT (0x1 << 3) |
| #define S_N_VALUE_RST_CH4_SFT 2 |
| #define S_N_VALUE_RST_CH4_MASK 0x1 |
| #define S_N_VALUE_RST_CH4_MASK_SFT (0x1 << 2) |
| #define SAMPLE_BASE_MODE_CH4_SFT 1 |
| #define SAMPLE_BASE_MODE_CH4_MASK 0x1 |
| #define SAMPLE_BASE_MODE_CH4_MASK_SFT (0x1 << 1) |
| #define VOW_ON_CH4_SFT 0 |
| #define VOW_ON_CH4_MASK 0x1 |
| #define VOW_ON_CH4_MASK_SFT (0x1 << 0) |
| |
| /* AFE_VOW_TOP_CON9 */ |
| #define VOW_ADC_CLK_INV_CH4_SFT 7 |
| #define VOW_ADC_CLK_INV_CH4_MASK 0x1 |
| #define VOW_ADC_CLK_INV_CH4_MASK_SFT (0x1 << 7) |
| #define VOW_INTR_SOURCE_SEL_CH4_SFT 6 |
| #define VOW_INTR_SOURCE_SEL_CH4_MASK 0x1 |
| #define VOW_INTR_SOURCE_SEL_CH4_MASK_SFT (0x1 << 6) |
| #define VOW_INTR_CLR_CH4_SFT 5 |
| #define VOW_INTR_CLR_CH4_MASK 0x1 |
| #define VOW_INTR_CLR_CH4_MASK_SFT (0x1 << 5) |
| #define VOW_DIGMIC_CK_PHASE_SEL_CH4_SFT 0 |
| #define VOW_DIGMIC_CK_PHASE_SEL_CH4_MASK 0x1f |
| #define VOW_DIGMIC_CK_PHASE_SEL_CH4_MASK_SFT (0x1f << 0) |
| |
| /* AFE_VOW_TOP_CON10 */ |
| #define VOW_ADC_TESTCK_SRC_SEL_SFT 4 |
| #define VOW_ADC_TESTCK_SRC_SEL_MASK 0x7 |
| #define VOW_ADC_TESTCK_SRC_SEL_MASK_SFT (0x7 << 4) |
| #define VOW_ADC_TESTCK_SEL_SFT 0 |
| #define VOW_ADC_TESTCK_SEL_MASK 0x1 |
| #define VOW_ADC_TESTCK_SEL_MASK_SFT (0x1 << 0) |
| |
| /* AFE_VOW_TOP_CON11 */ |
| #define RG_VOW_DMIC0_1_CLK_SRC_SEL_SFT 4 |
| #define RG_VOW_DMIC0_1_CLK_SRC_SEL_MASK 0x1 |
| #define RG_VOW_DMIC0_1_CLK_SRC_SEL_MASK_SFT (0x1 << 4) |
| #define RG_VOW_DMIC2_3_CLK_SRC_SEL_SFT 0 |
| #define RG_VOW_DMIC2_3_CLK_SRC_SEL_MASK 0x1 |
| #define RG_VOW_DMIC2_3_CLK_SRC_SEL_MASK_SFT (0x1 << 0) |
| |
| /* AFE_VOW_VAD_CFG0 */ |
| #define AMPREF_CH1_H_SFT 0 |
| #define AMPREF_CH1_H_MASK 0xff |
| #define AMPREF_CH1_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG1 */ |
| #define AMPREF_CH1_L_SFT 0 |
| #define AMPREF_CH1_L_MASK 0xff |
| #define AMPREF_CH1_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG2 */ |
| #define AMPREF_CH2_H_SFT 0 |
| #define AMPREF_CH2_H_MASK 0xff |
| #define AMPREF_CH2_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG3 */ |
| #define AMPREF_CH2_L_SFT 0 |
| #define AMPREF_CH2_L_MASK 0xff |
| #define AMPREF_CH2_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG4 */ |
| #define AMPREF_CH3_H_SFT 0 |
| #define AMPREF_CH3_H_MASK 0xff |
| #define AMPREF_CH3_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG5 */ |
| #define AMPREF_CH3_L_SFT 0 |
| #define AMPREF_CH3_L_MASK 0xff |
| #define AMPREF_CH3_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG6 */ |
| #define AMPREF_CH4_H_SFT 0 |
| #define AMPREF_CH4_H_MASK 0xff |
| #define AMPREF_CH4_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG7 */ |
| #define AMPREF_CH4_L_SFT 0 |
| #define AMPREF_CH4_L_MASK 0xff |
| #define AMPREF_CH4_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG8 */ |
| #define TIMERINI_CH1_H_SFT 0 |
| #define TIMERINI_CH1_H_MASK 0xff |
| #define TIMERINI_CH1_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG9 */ |
| #define TIMERINI_CH1_L_SFT 0 |
| #define TIMERINI_CH1_L_MASK 0xff |
| #define TIMERINI_CH1_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG10 */ |
| #define TIMERINI_CH2_H_SFT 0 |
| #define TIMERINI_CH2_H_MASK 0xff |
| #define TIMERINI_CH2_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG11 */ |
| #define TIMERINI_CH2_L_SFT 0 |
| #define TIMERINI_CH2_L_MASK 0xff |
| #define TIMERINI_CH2_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG12 */ |
| #define TIMERINI_CH3_H_SFT 0 |
| #define TIMERINI_CH3_H_MASK 0xff |
| #define TIMERINI_CH3_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG13 */ |
| #define TIMERINI_CH3_L_SFT 0 |
| #define TIMERINI_CH3_L_MASK 0xff |
| #define TIMERINI_CH3_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG14 */ |
| #define TIMERINI_CH4_H_SFT 0 |
| #define TIMERINI_CH4_H_MASK 0xff |
| #define TIMERINI_CH4_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG15 */ |
| #define TIMERINI_CH4_L_SFT 0 |
| #define TIMERINI_CH4_L_MASK 0xff |
| #define TIMERINI_CH4_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG16 */ |
| #define VOW_IRQ_LATCH_SNR_EN_CH1_SFT 7 |
| #define VOW_IRQ_LATCH_SNR_EN_CH1_MASK 0x1 |
| #define VOW_IRQ_LATCH_SNR_EN_CH1_MASK_SFT (0x1 << 7) |
| #define B_DEFAULT_CH1_SFT 4 |
| #define B_DEFAULT_CH1_MASK 0x7 |
| #define B_DEFAULT_CH1_MASK_SFT (0x7 << 4) |
| #define A_DEFAULT_CH1_SFT 0 |
| #define A_DEFAULT_CH1_MASK 0x7 |
| #define A_DEFAULT_CH1_MASK_SFT (0x7 << 0) |
| |
| /* AFE_VOW_VAD_CFG17 */ |
| #define B_INI_CH1_SFT 4 |
| #define B_INI_CH1_MASK 0x7 |
| #define B_INI_CH1_MASK_SFT (0x7 << 4) |
| #define A_INI_CH1_SFT 0 |
| #define A_INI_CH1_MASK 0x7 |
| #define A_INI_CH1_MASK_SFT (0x7 << 0) |
| |
| /* AFE_VOW_VAD_CFG18 */ |
| #define VOW_IRQ_LATCH_SNR_EN_CH2_SFT 7 |
| #define VOW_IRQ_LATCH_SNR_EN_CH2_MASK 0x1 |
| #define VOW_IRQ_LATCH_SNR_EN_CH2_MASK_SFT (0x1 << 7) |
| #define B_DEFAULT_CH2_SFT 4 |
| #define B_DEFAULT_CH2_MASK 0x7 |
| #define B_DEFAULT_CH2_MASK_SFT (0x7 << 4) |
| #define A_DEFAULT_CH2_SFT 0 |
| #define A_DEFAULT_CH2_MASK 0x7 |
| #define A_DEFAULT_CH2_MASK_SFT (0x7 << 0) |
| |
| /* AFE_VOW_VAD_CFG19 */ |
| #define B_INI_CH2_SFT 4 |
| #define B_INI_CH2_MASK 0x7 |
| #define B_INI_CH2_MASK_SFT (0x7 << 4) |
| #define A_INI_CH2_SFT 0 |
| #define A_INI_CH2_MASK 0x7 |
| #define A_INI_CH2_MASK_SFT (0x7 << 0) |
| |
| /* AFE_VOW_VAD_CFG20 */ |
| #define VOW_IRQ_LATCH_SNR_EN_CH3_SFT 7 |
| #define VOW_IRQ_LATCH_SNR_EN_CH3_MASK 0x1 |
| #define VOW_IRQ_LATCH_SNR_EN_CH3_MASK_SFT (0x1 << 7) |
| #define B_DEFAULT_CH3_SFT 4 |
| #define B_DEFAULT_CH3_MASK 0x7 |
| #define B_DEFAULT_CH3_MASK_SFT (0x7 << 4) |
| #define A_DEFAULT_CH3_SFT 0 |
| #define A_DEFAULT_CH3_MASK 0x7 |
| #define A_DEFAULT_CH3_MASK_SFT (0x7 << 0) |
| |
| /* AFE_VOW_VAD_CFG21 */ |
| #define B_INI_CH3_SFT 4 |
| #define B_INI_CH3_MASK 0x7 |
| #define B_INI_CH3_MASK_SFT (0x7 << 4) |
| #define A_INI_CH3_SFT 0 |
| #define A_INI_CH3_MASK 0x7 |
| #define A_INI_CH3_MASK_SFT (0x7 << 0) |
| |
| /* AFE_VOW_VAD_CFG22 */ |
| #define VOW_IRQ_LATCH_SNR_EN_CH4_SFT 7 |
| #define VOW_IRQ_LATCH_SNR_EN_CH4_MASK 0x1 |
| #define VOW_IRQ_LATCH_SNR_EN_CH4_MASK_SFT (0x1 << 7) |
| #define B_DEFAULT_CH4_SFT 4 |
| #define B_DEFAULT_CH4_MASK 0x7 |
| #define B_DEFAULT_CH4_MASK_SFT (0x7 << 4) |
| #define A_DEFAULT_CH4_SFT 0 |
| #define A_DEFAULT_CH4_MASK 0x7 |
| #define A_DEFAULT_CH4_MASK_SFT (0x7 << 0) |
| |
| /* AFE_VOW_VAD_CFG23 */ |
| #define B_INI_CH4_SFT 4 |
| #define B_INI_CH4_MASK 0x7 |
| #define B_INI_CH4_MASK_SFT (0x7 << 4) |
| #define A_INI_CH4_SFT 0 |
| #define A_INI_CH4_MASK 0x7 |
| #define A_INI_CH4_MASK_SFT (0x7 << 0) |
| |
| /* AFE_VOW_VAD_CFG24 */ |
| #define K_BETA_RISE_CH1_SFT 4 |
| #define K_BETA_RISE_CH1_MASK 0xf |
| #define K_BETA_RISE_CH1_MASK_SFT (0xf << 4) |
| #define K_BETA_FALL_CH1_SFT 0 |
| #define K_BETA_FALL_CH1_MASK 0xf |
| #define K_BETA_FALL_CH1_MASK_SFT (0xf << 0) |
| |
| /* AFE_VOW_VAD_CFG25 */ |
| #define K_ALPHA_RISE_CH1_SFT 4 |
| #define K_ALPHA_RISE_CH1_MASK 0xf |
| #define K_ALPHA_RISE_CH1_MASK_SFT (0xf << 4) |
| #define K_ALPHA_FALL_CH1_SFT 0 |
| #define K_ALPHA_FALL_CH1_MASK 0xf |
| #define K_ALPHA_FALL_CH1_MASK_SFT (0xf << 0) |
| |
| /* AFE_VOW_VAD_CFG26 */ |
| #define K_BETA_RISE_CH2_SFT 4 |
| #define K_BETA_RISE_CH2_MASK 0xf |
| #define K_BETA_RISE_CH2_MASK_SFT (0xf << 4) |
| #define K_BETA_FALL_CH2_SFT 0 |
| #define K_BETA_FALL_CH2_MASK 0xf |
| #define K_BETA_FALL_CH2_MASK_SFT (0xf << 0) |
| |
| /* AFE_VOW_VAD_CFG27 */ |
| #define K_ALPHA_RISE_CH2_SFT 4 |
| #define K_ALPHA_RISE_CH2_MASK 0xf |
| #define K_ALPHA_RISE_CH2_MASK_SFT (0xf << 4) |
| #define K_ALPHA_FALL_CH2_SFT 0 |
| #define K_ALPHA_FALL_CH2_MASK 0xf |
| #define K_ALPHA_FALL_CH2_MASK_SFT (0xf << 0) |
| |
| /* AFE_VOW_VAD_CFG28 */ |
| #define K_BETA_RISE_CH3_SFT 4 |
| #define K_BETA_RISE_CH3_MASK 0xf |
| #define K_BETA_RISE_CH3_MASK_SFT (0xf << 4) |
| #define K_BETA_FALL_CH3_SFT 0 |
| #define K_BETA_FALL_CH3_MASK 0xf |
| #define K_BETA_FALL_CH3_MASK_SFT (0xf << 0) |
| |
| /* AFE_VOW_VAD_CFG29 */ |
| #define K_ALPHA_RISE_CH3_SFT 4 |
| #define K_ALPHA_RISE_CH3_MASK 0xf |
| #define K_ALPHA_RISE_CH3_MASK_SFT (0xf << 4) |
| #define K_ALPHA_FALL_CH3_SFT 0 |
| #define K_ALPHA_FALL_CH3_MASK 0xf |
| #define K_ALPHA_FALL_CH3_MASK_SFT (0xf << 0) |
| |
| /* AFE_VOW_VAD_CFG30 */ |
| #define K_BETA_RISE_CH4_SFT 4 |
| #define K_BETA_RISE_CH4_MASK 0xf |
| #define K_BETA_RISE_CH4_MASK_SFT (0xf << 4) |
| #define K_BETA_FALL_CH4_SFT 0 |
| #define K_BETA_FALL_CH4_MASK 0xf |
| #define K_BETA_FALL_CH4_MASK_SFT (0xf << 0) |
| |
| /* AFE_VOW_VAD_CFG31 */ |
| #define K_ALPHA_RISE_CH4_SFT 4 |
| #define K_ALPHA_RISE_CH4_MASK 0xf |
| #define K_ALPHA_RISE_CH4_MASK_SFT (0xf << 4) |
| #define K_ALPHA_FALL_CH4_SFT 0 |
| #define K_ALPHA_FALL_CH4_MASK 0xf |
| #define K_ALPHA_FALL_CH4_MASK_SFT (0xf << 0) |
| |
| /* AFE_VOW_VAD_CFG32 */ |
| #define N_MIN_CH1_H_SFT 0 |
| #define N_MIN_CH1_H_MASK 0xff |
| #define N_MIN_CH1_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG33 */ |
| #define N_MIN_CH1_L_SFT 0 |
| #define N_MIN_CH1_L_MASK 0xff |
| #define N_MIN_CH1_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG34 */ |
| #define N_MIN_CH2_H_SFT 0 |
| #define N_MIN_CH2_H_MASK 0xff |
| #define N_MIN_CH2_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG35 */ |
| #define N_MIN_CH2_L_SFT 0 |
| #define N_MIN_CH2_L_MASK 0xff |
| #define N_MIN_CH2_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG36 */ |
| #define N_MIN_CH3_H_SFT 0 |
| #define N_MIN_CH3_H_MASK 0xff |
| #define N_MIN_CH3_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG37 */ |
| #define N_MIN_CH3_L_SFT 0 |
| #define N_MIN_CH3_L_MASK 0xff |
| #define N_MIN_CH3_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG38 */ |
| #define N_MIN_CH4_H_SFT 0 |
| #define N_MIN_CH4_H_MASK 0xff |
| #define N_MIN_CH4_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG39 */ |
| #define N_MIN_CH4_L_SFT 0 |
| #define N_MIN_CH4_L_MASK 0xff |
| #define N_MIN_CH4_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG40 */ |
| #define VOW_SN_INI_CFG_EN_CH1_SFT 7 |
| #define VOW_SN_INI_CFG_EN_CH1_MASK 0x1 |
| #define VOW_SN_INI_CFG_EN_CH1_MASK_SFT (0x1 << 7) |
| #define VOW_SN_INI_CFG_VAL_CH1_H_SFT 0 |
| #define VOW_SN_INI_CFG_VAL_CH1_H_MASK 0x7f |
| #define VOW_SN_INI_CFG_VAL_CH1_H_MASK_SFT (0x7f << 0) |
| |
| /* AFE_VOW_VAD_CFG41 */ |
| #define VOW_SN_INI_CFG_VAL_CH1_L_SFT 0 |
| #define VOW_SN_INI_CFG_VAL_CH1_L_MASK 0xff |
| #define VOW_SN_INI_CFG_VAL_CH1_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG42 */ |
| #define VOW_SN_INI_CFG_EN_CH2_SFT 7 |
| #define VOW_SN_INI_CFG_EN_CH2_MASK 0x1 |
| #define VOW_SN_INI_CFG_EN_CH2_MASK_SFT (0x1 << 7) |
| #define VOW_SN_INI_CFG_VAL_CH2_H_SFT 0 |
| #define VOW_SN_INI_CFG_VAL_CH2_H_MASK 0x7f |
| #define VOW_SN_INI_CFG_VAL_CH2_H_MASK_SFT (0x7f << 0) |
| |
| /* AFE_VOW_VAD_CFG43 */ |
| #define VOW_SN_INI_CFG_VAL_CH2_L_SFT 0 |
| #define VOW_SN_INI_CFG_VAL_CH2_L_MASK 0xff |
| #define VOW_SN_INI_CFG_VAL_CH2_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG44 */ |
| #define VOW_SN_INI_CFG_EN_CH3_SFT 7 |
| #define VOW_SN_INI_CFG_EN_CH3_MASK 0x1 |
| #define VOW_SN_INI_CFG_EN_CH3_MASK_SFT (0x1 << 7) |
| #define VOW_SN_INI_CFG_VAL_CH3_H_SFT 0 |
| #define VOW_SN_INI_CFG_VAL_CH3_H_MASK 0x7f |
| #define VOW_SN_INI_CFG_VAL_CH3_H_MASK_SFT (0x7f << 0) |
| |
| /* AFE_VOW_VAD_CFG45 */ |
| #define VOW_SN_INI_CFG_VAL_CH3_L_SFT 0 |
| #define VOW_SN_INI_CFG_VAL_CH3_L_MASK 0xff |
| #define VOW_SN_INI_CFG_VAL_CH3_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG46 */ |
| #define VOW_SN_INI_CFG_EN_CH4_SFT 7 |
| #define VOW_SN_INI_CFG_EN_CH4_MASK 0x1 |
| #define VOW_SN_INI_CFG_EN_CH4_MASK_SFT (0x1 << 7) |
| #define VOW_SN_INI_CFG_VAL_CH4_H_SFT 0 |
| #define VOW_SN_INI_CFG_VAL_CH4_H_MASK 0x7f |
| #define VOW_SN_INI_CFG_VAL_CH4_H_MASK_SFT (0x7f << 0) |
| |
| /* AFE_VOW_VAD_CFG47 */ |
| #define VOW_SN_INI_CFG_VAL_CH4_L_SFT 0 |
| #define VOW_SN_INI_CFG_VAL_CH4_L_MASK 0xff |
| #define VOW_SN_INI_CFG_VAL_CH4_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG48 */ |
| #define K_GAMMA_CH1_SFT 4 |
| #define K_GAMMA_CH1_MASK 0xf |
| #define K_GAMMA_CH1_MASK_SFT (0xf << 4) |
| #define K_GAMMA_CH2_SFT 0 |
| #define K_GAMMA_CH2_MASK 0xf |
| #define K_GAMMA_CH2_MASK_SFT (0xf << 0) |
| |
| /* AFE_VOW_VAD_CFG49 */ |
| #define K_GAMMA_CH3_SFT 4 |
| #define K_GAMMA_CH3_MASK 0xf |
| #define K_GAMMA_CH3_MASK_SFT (0xf << 4) |
| #define K_GAMMA_CH4_SFT 0 |
| #define K_GAMMA_CH4_MASK 0xf |
| #define K_GAMMA_CH4_MASK_SFT (0xf << 0) |
| |
| /* AFE_VOW_VAD_CFG50 */ |
| #define VAD_SIL_THD_HH_CH1_SFT 0 |
| #define VAD_SIL_THD_HH_CH1_MASK 0xff |
| #define VAD_SIL_THD_HH_CH1_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG51 */ |
| #define VAD_SIL_THD_HL_CH1_SFT 0 |
| #define VAD_SIL_THD_HL_CH1_MASK 0xff |
| #define VAD_SIL_THD_HL_CH1_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG52 */ |
| #define VAD_SIL_THD_LH_CH1_SFT 0 |
| #define VAD_SIL_THD_LH_CH1_MASK 0xff |
| #define VAD_SIL_THD_LH_CH1_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG53 */ |
| #define VAD_SIL_THD_LL_CH1_SFT 0 |
| #define VAD_SIL_THD_LL_CH1_MASK 0xff |
| #define VAD_SIL_THD_LL_CH1_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG54 */ |
| #define VAD_SIL_THD_HH_CH2_SFT 0 |
| #define VAD_SIL_THD_HH_CH2_MASK 0xff |
| #define VAD_SIL_THD_HH_CH2_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG55 */ |
| #define VAD_SIL_THD_HL_CH2_SFT 0 |
| #define VAD_SIL_THD_HL_CH2_MASK 0xff |
| #define VAD_SIL_THD_HL_CH2_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG56 */ |
| #define VAD_SIL_THD_LH_CH2_SFT 0 |
| #define VAD_SIL_THD_LH_CH2_MASK 0xff |
| #define VAD_SIL_THD_LH_CH2_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG57 */ |
| #define VAD_SIL_THD_LL_CH2_SFT 0 |
| #define VAD_SIL_THD_LL_CH2_MASK 0xff |
| #define VAD_SIL_THD_LL_CH2_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG58 */ |
| #define VAD_SIL_THD_HH_CH3_SFT 0 |
| #define VAD_SIL_THD_HH_CH3_MASK 0xff |
| #define VAD_SIL_THD_HH_CH3_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG59 */ |
| #define VAD_SIL_THD_HL_CH3_SFT 0 |
| #define VAD_SIL_THD_HL_CH3_MASK 0xff |
| #define VAD_SIL_THD_HL_CH3_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG60 */ |
| #define VAD_SIL_THD_LH_CH3_SFT 0 |
| #define VAD_SIL_THD_LH_CH3_MASK 0xff |
| #define VAD_SIL_THD_LH_CH3_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG61 */ |
| #define VAD_SIL_THD_LL_CH3_SFT 0 |
| #define VAD_SIL_THD_LL_CH3_MASK 0xff |
| #define VAD_SIL_THD_LL_CH3_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG62 */ |
| #define VAD_SIL_THD_HH_CH4_SFT 0 |
| #define VAD_SIL_THD_HH_CH4_MASK 0xff |
| #define VAD_SIL_THD_HH_CH4_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG63 */ |
| #define VAD_SIL_THD_HL_CH4_SFT 0 |
| #define VAD_SIL_THD_HL_CH4_MASK 0xff |
| #define VAD_SIL_THD_HL_CH4_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG64 */ |
| #define VAD_SIL_THD_LH_CH4_SFT 0 |
| #define VAD_SIL_THD_LH_CH4_MASK 0xff |
| #define VAD_SIL_THD_LH_CH4_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_CFG65 */ |
| #define VAD_SIL_THD_LL_CH4_SFT 0 |
| #define VAD_SIL_THD_LL_CH4_MASK 0xff |
| #define VAD_SIL_THD_LL_CH4_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_TGEN_CFG0 */ |
| #define VOW_TGEN_EN_CH1_SFT 7 |
| #define VOW_TGEN_EN_CH1_MASK 0x1 |
| #define VOW_TGEN_EN_CH1_MASK_SFT (0x1 << 7) |
| #define VOW_TGEN_MUTE_SW_CH1_SFT 6 |
| #define VOW_TGEN_MUTE_SW_CH1_MASK 0x1 |
| #define VOW_TGEN_MUTE_SW_CH1_MASK_SFT (0x1 << 6) |
| #define VOW_TGEN_FREQ_DIV_CH1_H_SFT 0 |
| #define VOW_TGEN_FREQ_DIV_CH1_H_MASK 0x3f |
| #define VOW_TGEN_FREQ_DIV_CH1_H_MASK_SFT (0x3f << 0) |
| |
| /* AFE_VOW_TGEN_CFG1 */ |
| #define VOW_TGEN_FREQ_DIV_CH1_L_SFT 0 |
| #define VOW_TGEN_FREQ_DIV_CH1_L_MASK 0xff |
| #define VOW_TGEN_FREQ_DIV_CH1_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_TGEN_CFG2 */ |
| #define VOW_TGEN_EN_CH2_SFT 7 |
| #define VOW_TGEN_EN_CH2_MASK 0x1 |
| #define VOW_TGEN_EN_CH2_MASK_SFT (0x1 << 7) |
| #define VOW_TGEN_MUTE_SW_CH2_SFT 6 |
| #define VOW_TGEN_MUTE_SW_CH2_MASK 0x1 |
| #define VOW_TGEN_MUTE_SW_CH2_MASK_SFT (0x1 << 6) |
| #define VOW_TGEN_FREQ_DIV_CH2_H_SFT 0 |
| #define VOW_TGEN_FREQ_DIV_CH2_H_MASK 0x3f |
| #define VOW_TGEN_FREQ_DIV_CH2_H_MASK_SFT (0x3f << 0) |
| |
| /* AFE_VOW_TGEN_CFG3 */ |
| #define VOW_TGEN_FREQ_DIV_CH2_L_SFT 0 |
| #define VOW_TGEN_FREQ_DIV_CH2_L_MASK 0xff |
| #define VOW_TGEN_FREQ_DIV_CH2_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_TGEN_CFG4 */ |
| #define VOW_TGEN_EN_CH3_SFT 7 |
| #define VOW_TGEN_EN_CH3_MASK 0x1 |
| #define VOW_TGEN_EN_CH3_MASK_SFT (0x1 << 7) |
| #define VOW_TGEN_MUTE_SW_CH3_SFT 6 |
| #define VOW_TGEN_MUTE_SW_CH3_MASK 0x1 |
| #define VOW_TGEN_MUTE_SW_CH3_MASK_SFT (0x1 << 6) |
| #define VOW_TGEN_FREQ_DIV_CH3_H_SFT 0 |
| #define VOW_TGEN_FREQ_DIV_CH3_H_MASK 0x3f |
| #define VOW_TGEN_FREQ_DIV_CH3_H_MASK_SFT (0x3f << 0) |
| |
| /* AFE_VOW_TGEN_CFG5 */ |
| #define VOW_TGEN_FREQ_DIV_CH3_L_SFT 0 |
| #define VOW_TGEN_FREQ_DIV_CH3_L_MASK 0xff |
| #define VOW_TGEN_FREQ_DIV_CH3_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_TGEN_CFG6 */ |
| #define VOW_TGEN_EN_CH4_SFT 7 |
| #define VOW_TGEN_EN_CH4_MASK 0x1 |
| #define VOW_TGEN_EN_CH4_MASK_SFT (0x1 << 7) |
| #define VOW_TGEN_MUTE_SW_CH4_SFT 6 |
| #define VOW_TGEN_MUTE_SW_CH4_MASK 0x1 |
| #define VOW_TGEN_MUTE_SW_CH4_MASK_SFT (0x1 << 6) |
| #define VOW_TGEN_FREQ_DIV_CH4_H_SFT 0 |
| #define VOW_TGEN_FREQ_DIV_CH4_H_MASK 0x3f |
| #define VOW_TGEN_FREQ_DIV_CH4_H_MASK_SFT (0x3f << 0) |
| |
| /* AFE_VOW_TGEN_CFG7 */ |
| #define VOW_TGEN_FREQ_DIV_CH4_L_SFT 0 |
| #define VOW_TGEN_FREQ_DIV_CH4_L_MASK 0xff |
| #define VOW_TGEN_FREQ_DIV_CH4_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_HPF_CFG0 */ |
| #define VOW_HPF_DC_TEST_CH1_SFT 0 |
| #define VOW_HPF_DC_TEST_CH1_MASK 0xf |
| #define VOW_HPF_DC_TEST_CH1_MASK_SFT (0xf << 0) |
| |
| /* AFE_VOW_HPF_CFG1 */ |
| #define RG_BASELINE_ALPHA_ORDER_CH1_SFT 4 |
| #define RG_BASELINE_ALPHA_ORDER_CH1_MASK 0xf |
| #define RG_BASELINE_ALPHA_ORDER_CH1_MASK_SFT (0xf << 4) |
| #define RG_MTKAIF_HPF_BYPASS_CH1_SFT 2 |
| #define RG_MTKAIF_HPF_BYPASS_CH1_MASK 0x1 |
| #define RG_MTKAIF_HPF_BYPASS_CH1_MASK_SFT (0x1 << 2) |
| #define RG_SNRDET_HPF_BYPASS_CH1_SFT 1 |
| #define RG_SNRDET_HPF_BYPASS_CH1_MASK 0x1 |
| #define RG_SNRDET_HPF_BYPASS_CH1_MASK_SFT (0x1 << 1) |
| #define RG_HPF_ON_CH1_SFT 0 |
| #define RG_HPF_ON_CH1_MASK 0x1 |
| #define RG_HPF_ON_CH1_MASK_SFT (0x1 << 0) |
| |
| /* AFE_VOW_HPF_CFG2 */ |
| #define VOW_HPF_DC_TEST_CH2_SFT 0 |
| #define VOW_HPF_DC_TEST_CH2_MASK 0xf |
| #define VOW_HPF_DC_TEST_CH2_MASK_SFT (0xf << 0) |
| |
| /* AFE_VOW_HPF_CFG3 */ |
| #define RG_BASELINE_ALPHA_ORDER_CH2_SFT 4 |
| #define RG_BASELINE_ALPHA_ORDER_CH2_MASK 0xf |
| #define RG_BASELINE_ALPHA_ORDER_CH2_MASK_SFT (0xf << 4) |
| #define RG_MTKAIF_HPF_BYPASS_CH2_SFT 2 |
| #define RG_MTKAIF_HPF_BYPASS_CH2_MASK 0x1 |
| #define RG_MTKAIF_HPF_BYPASS_CH2_MASK_SFT (0x1 << 2) |
| #define RG_SNRDET_HPF_BYPASS_CH2_SFT 1 |
| #define RG_SNRDET_HPF_BYPASS_CH2_MASK 0x1 |
| #define RG_SNRDET_HPF_BYPASS_CH2_MASK_SFT (0x1 << 1) |
| #define RG_HPF_ON_CH2_SFT 0 |
| #define RG_HPF_ON_CH2_MASK 0x1 |
| #define RG_HPF_ON_CH2_MASK_SFT (0x1 << 0) |
| |
| /* AFE_VOW_HPF_CFG4 */ |
| #define VOW_HPF_DC_TEST_CH3_SFT 0 |
| #define VOW_HPF_DC_TEST_CH3_MASK 0xf |
| #define VOW_HPF_DC_TEST_CH3_MASK_SFT (0xf << 0) |
| |
| /* AFE_VOW_HPF_CFG5 */ |
| #define RG_BASELINE_ALPHA_ORDER_CH3_SFT 4 |
| #define RG_BASELINE_ALPHA_ORDER_CH3_MASK 0xf |
| #define RG_BASELINE_ALPHA_ORDER_CH3_MASK_SFT (0xf << 4) |
| #define RG_MTKAIF_HPF_BYPASS_CH3_SFT 2 |
| #define RG_MTKAIF_HPF_BYPASS_CH3_MASK 0x1 |
| #define RG_MTKAIF_HPF_BYPASS_CH3_MASK_SFT (0x1 << 2) |
| #define RG_SNRDET_HPF_BYPASS_CH3_SFT 1 |
| #define RG_SNRDET_HPF_BYPASS_CH3_MASK 0x1 |
| #define RG_SNRDET_HPF_BYPASS_CH3_MASK_SFT (0x1 << 1) |
| #define RG_HPF_ON_CH3_SFT 0 |
| #define RG_HPF_ON_CH3_MASK 0x1 |
| #define RG_HPF_ON_CH3_MASK_SFT (0x1 << 0) |
| |
| /* AFE_VOW_HPF_CFG6 */ |
| #define VOW_HPF_DC_TEST_CH4_SFT 0 |
| #define VOW_HPF_DC_TEST_CH4_MASK 0xf |
| #define VOW_HPF_DC_TEST_CH4_MASK_SFT (0xf << 0) |
| |
| /* AFE_VOW_HPF_CFG7 */ |
| #define RG_BASELINE_ALPHA_ORDER_CH4_SFT 4 |
| #define RG_BASELINE_ALPHA_ORDER_CH4_MASK 0xf |
| #define RG_BASELINE_ALPHA_ORDER_CH4_MASK_SFT (0xf << 4) |
| #define RG_MTKAIF_HPF_BYPASS_CH4_SFT 2 |
| #define RG_MTKAIF_HPF_BYPASS_CH4_MASK 0x1 |
| #define RG_MTKAIF_HPF_BYPASS_CH4_MASK_SFT (0x1 << 2) |
| #define RG_SNRDET_HPF_BYPASS_CH4_SFT 1 |
| #define RG_SNRDET_HPF_BYPASS_CH4_MASK 0x1 |
| #define RG_SNRDET_HPF_BYPASS_CH4_MASK_SFT (0x1 << 1) |
| #define RG_HPF_ON_CH4_SFT 0 |
| #define RG_HPF_ON_CH4_MASK 0x1 |
| #define RG_HPF_ON_CH4_MASK_SFT (0x1 << 0) |
| |
| /* AFE_VOW_INTR_CON */ |
| #define RG_VOW_VAD_PBUF_FIFO_IRQ_CLR_SFT 7 |
| #define RG_VOW_VAD_PBUF_FIFO_IRQ_CLR_MASK 0x1 |
| #define RG_VOW_VAD_PBUF_FIFO_IRQ_CLR_MASK_SFT (0x1 << 7) |
| #define RG_VOW_VAD_PBUF_FIFO_IRQ_CTRL_SFT 6 |
| #define RG_VOW_VAD_PBUF_FIFO_IRQ_CTRL_MASK 0x1 |
| #define RG_VOW_VAD_PBUF_FIFO_IRQ_CTRL_MASK_SFT (0x1 << 6) |
| #define RG_VOW_VAD_PBUF_FIFO_IRQ_STATUS_SFT 5 |
| #define RG_VOW_VAD_PBUF_FIFO_IRQ_STATUS_MASK 0x1 |
| #define RG_VOW_VAD_PBUF_FIFO_IRQ_STATUS_MASK_SFT (0x1 << 5) |
| #define RG_VOW_VAD_IRQ_STATUS_SFT 4 |
| #define RG_VOW_VAD_IRQ_STATUS_MASK 0x1 |
| #define RG_VOW_VAD_IRQ_STATUS_MASK_SFT (0x1 << 4) |
| #define RG_VOW_VAD_CH4_IRQ_STATUS_SFT 3 |
| #define RG_VOW_VAD_CH4_IRQ_STATUS_MASK 0x1 |
| #define RG_VOW_VAD_CH4_IRQ_STATUS_MASK_SFT (0x1 << 3) |
| #define RG_VOW_VAD_CH3_IRQ_STATUS_SFT 2 |
| #define RG_VOW_VAD_CH3_IRQ_STATUS_MASK 0x1 |
| #define RG_VOW_VAD_CH3_IRQ_STATUS_MASK_SFT (0x1 << 2) |
| #define RG_VOW_VAD_CH2_IRQ_STATUS_SFT 1 |
| #define RG_VOW_VAD_CH2_IRQ_STATUS_MASK 0x1 |
| #define RG_VOW_VAD_CH2_IRQ_STATUS_MASK_SFT (0x1 << 1) |
| #define RG_VOW_VAD_CH1_IRQ_STATUS_SFT 0 |
| #define RG_VOW_VAD_CH1_IRQ_STATUS_MASK 0x1 |
| #define RG_VOW_VAD_CH1_IRQ_STATUS_MASK_SFT (0x1 << 0) |
| |
| /* AUDIO_DIG_18TH_DSN_ID */ |
| #define AUDIO_DIG_18TH_ANA_ID_SFT 0 |
| #define AUDIO_DIG_18TH_ANA_ID_MASK 0xff |
| #define AUDIO_DIG_18TH_ANA_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_18TH_DSN_ID_H */ |
| #define AUDIO_DIG_18TH_DIG_ID_SFT 0 |
| #define AUDIO_DIG_18TH_DIG_ID_MASK 0xff |
| #define AUDIO_DIG_18TH_DIG_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_18TH_DSN_REV0 */ |
| #define AUDIO_DIG_18TH_ANA_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_18TH_ANA_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_18TH_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_18TH_ANA_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_18TH_ANA_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_18TH_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_18TH_DSN_REV0_H */ |
| #define AUDIO_DIG_18TH_DIG_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_18TH_DIG_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_18TH_DIG_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_18TH_DIG_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_18TH_DIG_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_18TH_DIG_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_18TH_DSN_DBI */ |
| #define AUDIO_DIG_18TH_DSN_CBS_SFT 0 |
| #define AUDIO_DIG_18TH_DSN_CBS_MASK 0x3 |
| #define AUDIO_DIG_18TH_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDIO_DIG_18TH_DSN_BIX_SFT 2 |
| #define AUDIO_DIG_18TH_DSN_BIX_MASK 0x3 |
| #define AUDIO_DIG_18TH_DSN_BIX_MASK_SFT (0x3 << 2) |
| |
| /* AUDIO_DIG_18TH_DSN_DBI_H */ |
| #define AUDIO_DIG_18_ESP_SFT 0 |
| #define AUDIO_DIG_18_ESP_MASK 0xff |
| #define AUDIO_DIG_18_ESP_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_18TH_DSN_DXI */ |
| #define AUDIO_DIG_18TH_DSN_FPI_SFT 0 |
| #define AUDIO_DIG_18TH_DSN_FPI_MASK 0xff |
| #define AUDIO_DIG_18TH_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_VOW_SRAM_L */ |
| #define AUDIO_VOW_SRAM_L_SFT 0 |
| #define AUDIO_VOW_SRAM_L_MASK 0xff |
| #define AUDIO_VOW_SRAM_L_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_VOW_SRAM_H */ |
| #define AUDIO_VOW_SRAM_H_SFT 0 |
| #define AUDIO_VOW_SRAM_H_MASK 0xff |
| #define AUDIO_VOW_SRAM_H_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_19TH_DSN_ID */ |
| #define AUDIO_DIG_19TH_ANA_ID_SFT 0 |
| #define AUDIO_DIG_19TH_ANA_ID_MASK 0xff |
| #define AUDIO_DIG_19TH_ANA_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_19TH_DSN_ID_H */ |
| #define AUDIO_DIG_19TH_DIG_ID_SFT 0 |
| #define AUDIO_DIG_19TH_DIG_ID_MASK 0xff |
| #define AUDIO_DIG_19TH_DIG_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_19TH_DSN_REV0 */ |
| #define AUDIO_DIG_19TH_ANA_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_19TH_ANA_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_19TH_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_19TH_ANA_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_19TH_ANA_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_19TH_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_19TH_DSN_REV0_H */ |
| #define AUDIO_DIG_19TH_DIG_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_19TH_DIG_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_19TH_DIG_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_19TH_DIG_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_19TH_DIG_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_19TH_DIG_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_19TH_DSN_DBI */ |
| #define AUDIO_DIG_19TH_DSN_CBS_SFT 0 |
| #define AUDIO_DIG_19TH_DSN_CBS_MASK 0x3 |
| #define AUDIO_DIG_19TH_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDIO_DIG_19TH_DSN_BIX_SFT 2 |
| #define AUDIO_DIG_19TH_DSN_BIX_MASK 0x3 |
| #define AUDIO_DIG_19TH_DSN_BIX_MASK_SFT (0x3 << 2) |
| |
| /* AUDIO_DIG_19TH_DSN_DBI_H */ |
| #define AUDIO_DIG_19_ESP_SFT 0 |
| #define AUDIO_DIG_19_ESP_MASK 0xff |
| #define AUDIO_DIG_19_ESP_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_19TH_DSN_DXI */ |
| #define AUDIO_DIG_19TH_DSN_FPI_SFT 0 |
| #define AUDIO_DIG_19TH_DSN_FPI_MASK 0xff |
| #define AUDIO_DIG_19TH_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_MTKAIFV4_TX_CFG0 */ |
| #define MT6338_MTKAIFV4_TXIF_AFE_ON_SFT 0 |
| #define MT6338_MTKAIFV4_TXIF_AFE_ON_MASK 0x1 |
| #define MT6338_MTKAIFV4_TXIF_AFE_ON_MASK_SFT (0x1 << 0) |
| #define MT6338_MTKAIFV4_TXIF_FOUR_CHANNEL_SFT 1 |
| #define MT6338_MTKAIFV4_TXIF_FOUR_CHANNEL_MASK 0x1 |
| #define MT6338_MTKAIFV4_TXIF_FOUR_CHANNEL_MASK_SFT (0x1 << 1) |
| #define MT6338_MTKAIFV4_TXIF_INPUT_MODE_SFT 3 |
| #define MT6338_MTKAIFV4_TXIF_INPUT_MODE_MASK 0x1f |
| #define MT6338_MTKAIFV4_TXIF_INPUT_MODE_MASK_SFT (0x1f << 3) |
| |
| /* AFE_ADDA6_MTKAIFV4_TX_CFG0 */ |
| #define MT6338_ADDA6_MTKAIFV4_TXIF_AFE_ON_SFT 0 |
| #define MT6338_ADDA6_MTKAIFV4_TXIF_AFE_ON_MASK 0x1 |
| #define MT6338_ADDA6_MTKAIFV4_TXIF_AFE_ON_MASK_SFT (0x1 << 0) |
| #define MT6338_ADDA6_MTKAIFV4_TXIF_FOUR_CHANNEL_SFT 1 |
| #define MT6338_ADDA6_MTKAIFV4_TXIF_FOUR_CHANNEL_MASK 0x1 |
| #define MT6338_ADDA6_MTKAIFV4_TXIF_FOUR_CHANNEL_MASK_SFT (0x1 << 1) |
| #define MT6338_ADDA6_MTKAIFV4_TXIF_INPUT_MODE_SFT 3 |
| #define MT6338_ADDA6_MTKAIFV4_TXIF_INPUT_MODE_MASK 0x1f |
| #define MT6338_ADDA6_MTKAIFV4_TXIF_INPUT_MODE_MASK_SFT (0x1f << 3) |
| |
| /* AFE_MTKAIFV4_TX_CFG */ |
| #define MT6338_MTKAIFV4_ADDA_OUT_EN_SEL_SFT 0 |
| #define MT6338_MTKAIFV4_ADDA_OUT_EN_SEL_MASK 0x1 |
| #define MT6338_MTKAIFV4_ADDA_OUT_EN_SEL_MASK_SFT (0x1 << 0) |
| #define MT6338_MTKAIFV4_ADDA6_OUT_EN_SEL_SFT 1 |
| #define MT6338_MTKAIFV4_ADDA6_OUT_EN_SEL_MASK 0x1 |
| #define MT6338_MTKAIFV4_ADDA6_OUT_EN_SEL_MASK_SFT (0x1 << 1) |
| #define MT6338_MTKAIFV4_TXIF_PROTOCOL3_SFT 2 |
| #define MT6338_MTKAIFV4_TXIF_PROTOCOL3_MASK 0x1 |
| #define MT6338_MTKAIFV4_TXIF_PROTOCOL3_MASK_SFT (0x1 << 2) |
| #define MT6338_MTKAIFV4_TXIF_EN_SEL_SFT 3 |
| #define MT6338_MTKAIFV4_TXIF_EN_SEL_MASK 0x1 |
| #define MT6338_MTKAIFV4_TXIF_EN_SEL_MASK_SFT (0x1 << 3) |
| #define MT6338_ADDA6_MTKAIFV4_TXIF_EN_SEL_SFT 4 |
| #define MT6338_ADDA6_MTKAIFV4_TXIF_EN_SEL_MASK 0x1 |
| #define MT6338_ADDA6_MTKAIFV4_TXIF_EN_SEL_MASK_SFT (0x1 << 4) |
| #define MT6338_MTKAIFV4_LOOPBACK2_SFT 5 |
| #define MT6338_MTKAIFV4_LOOPBACK2_MASK 0x1 |
| #define MT6338_MTKAIFV4_LOOPBACK2_MASK_SFT (0x1 << 5) |
| |
| /* AFE_ADDA_MTKAIFV4_RX_CFG0 */ |
| #define MT6338_MTKAIFV4_RXIF_AFE_ON_SFT 0 |
| #define MT6338_MTKAIFV4_RXIF_AFE_ON_MASK 0x1 |
| #define MT6338_MTKAIFV4_RXIF_AFE_ON_MASK_SFT (0x1 << 0) |
| #define MT6338_MTKAIFV4_RXIF_FOUR_CHANNEL_SFT 1 |
| #define MT6338_MTKAIFV4_RXIF_FOUR_CHANNEL_MASK 0x1 |
| #define MT6338_MTKAIFV4_RXIF_FOUR_CHANNEL_MASK_SFT (0x1 << 1) |
| #define MT6338_MTKAIFV4_LOOPBACK1_SFT 2 |
| #define MT6338_MTKAIFV4_LOOPBACK1_MASK 0x1 |
| #define MT6338_MTKAIFV4_LOOPBACK1_MASK_SFT (0x1 << 2) |
| #define MT6338_MTKAIFV4_RXIF_INPUT_MODE_SFT 3 |
| #define MT6338_MTKAIFV4_RXIF_INPUT_MODE_MASK 0x1f |
| #define MT6338_MTKAIFV4_RXIF_INPUT_MODE_MASK_SFT (0x1f << 3) |
| |
| /* AFE_ADDA_MTKAIFV4_RX_CFG1_0 */ |
| #define MTKAIFV4_RXIF_SELF_DEFINE_TABLE_SFT 0 |
| #define MTKAIFV4_RXIF_SELF_DEFINE_TABLE_MASK 0x1 |
| #define MTKAIFV4_RXIF_SELF_DEFINE_TABLE_MASK_SFT (0x1 << 0) |
| #define MTKAIFV4_RXIF_FIFO_RSP_SFT 1 |
| #define MTKAIFV4_RXIF_FIFO_RSP_MASK 0x7 |
| #define MTKAIFV4_RXIF_FIFO_RSP_MASK_SFT (0x7 << 1) |
| #define MTKAIFV4_RXIF_SYNC_CHECK_ROUND_SFT 4 |
| #define MTKAIFV4_RXIF_SYNC_CHECK_ROUND_MASK 0xf |
| #define MTKAIFV4_RXIF_SYNC_CHECK_ROUND_MASK_SFT (0xf << 4) |
| |
| /* AFE_ADDA_MTKAIFV4_RX_CFG1_1 */ |
| #define MT6338_MTKAIFV4_RXIF_INVALID_SYNC_CHECK_ROUND_SFT 0 |
| #define MT6338_MTKAIFV4_RXIF_INVALID_SYNC_CHECK_ROUND_MASK 0xf |
| #define MT6338_MTKAIFV4_RXIF_INVALID_SYNC_CHECK_ROUND_MASK_SFT (0xf << 0) |
| #define MT6338_MTKAIFV4_RXIF_SYNC_CNT_TABLE_HIGH_SFT 4 |
| #define MT6338_MTKAIFV4_RXIF_SYNC_CNT_TABLE_HIGH_MASK 0xf |
| #define MT6338_MTKAIFV4_RXIF_SYNC_CNT_TABLE_HIGH_MASK_SFT (0xf << 4) |
| |
| /* AFE_ADDA_MTKAIFV4_RX_CFG1_2 */ |
| #define MTKAIFV4_RXIF_SYNC_CNT_TABLE_LOW_SFT 0 |
| #define MTKAIFV4_RXIF_SYNC_CNT_TABLE_LOW_MASK 0xff |
| #define MTKAIFV4_RXIF_SYNC_CNT_TABLE_LOW_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_MTKAIFV4_RX_CFG1_3 */ |
| #define MT6338_MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_SFT 0 |
| #define MT6338_MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_MASK 0x1f |
| #define MT6338_MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_MASK_SFT (0x1f << 0) |
| #define MT6338_RG_MTKAIF_RXIF_PROTOCOL3_SFT 5 |
| #define MT6338_RG_MTKAIF_RXIF_PROTOCOL3_MASK 0x1 |
| #define MT6338_RG_MTKAIF_RXIF_PROTOCOL3_MASK_SFT (0x1 << 5) |
| #define MT6338_RG_MTKAIF_RXIF_FIFO_INTEN_SFT 6 |
| #define MT6338_RG_MTKAIF_RXIF_FIFO_INTEN_MASK 0x1 |
| #define MT6338_RG_MTKAIF_RXIF_FIFO_INTEN_MASK_SFT (0x1 << 6) |
| |
| /* AFE_ADDA6_MTKAIFV4_RX_CFG0 */ |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_AFE_ON_SFT 0 |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_AFE_ON_MASK 0x1 |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_AFE_ON_MASK_SFT (0x1 << 0) |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_FOUR_CHANNEL_SFT 1 |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_FOUR_CHANNEL_MASK 0x1 |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_FOUR_CHANNEL_MASK_SFT (0x1 << 1) |
| #define MT6338_ADDA6_MTKAIFV4_LOOPBACK1_SFT 2 |
| #define MT6338_ADDA6_MTKAIFV4_LOOPBACK1_MASK 0x1 |
| #define MT6338_ADDA6_MTKAIFV4_LOOPBACK1_MASK_SFT (0x1 << 2) |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_INPUT_MODE_SFT 3 |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_INPUT_MODE_MASK 0x1f |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_INPUT_MODE_MASK_SFT (0x1f << 3) |
| |
| /* AFE_ADDA6_MTKAIFV4_RX_CFG1_0 */ |
| #define ADDA6_MTKAIFV4_RXIF_SELF_DEFINE_TABLE_SFT 0 |
| #define ADDA6_MTKAIFV4_RXIF_SELF_DEFINE_TABLE_MASK 0x1 |
| #define ADDA6_MTKAIFV4_RXIF_SELF_DEFINE_TABLE_MASK_SFT (0x1 << 0) |
| #define ADDA6_MTKAIFV4_RXIF_FIFO_RSP_SFT 1 |
| #define ADDA6_MTKAIFV4_RXIF_FIFO_RSP_MASK 0x7 |
| #define ADDA6_MTKAIFV4_RXIF_FIFO_RSP_MASK_SFT (0x7 << 1) |
| #define ADDA6_MTKAIFV4_RXIF_SYNC_CHECK_ROUND_SFT 4 |
| #define ADDA6_MTKAIFV4_RXIF_SYNC_CHECK_ROUND_MASK 0xf |
| #define ADDA6_MTKAIFV4_RXIF_SYNC_CHECK_ROUND_MASK_SFT (0xf << 4) |
| |
| /* AFE_ADDA6_MTKAIFV4_RX_CFG1_1 */ |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_INVALID_SYNC_CHECK_ROUND_SFT 0 |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_INVALID_SYNC_CHECK_ROUND_MASK 0xf |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_INVALID_SYNC_CHECK_ROUND_MASK_SFT (0xf << 0) |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_SYNC_CNT_TABLE_HIGH_SFT 4 |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_SYNC_CNT_TABLE_HIGH_MASK 0xf |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_SYNC_CNT_TABLE_HIGH_MASK_SFT (0xf << 4) |
| |
| /* AFE_ADDA6_MTKAIFV4_RX_CFG1_2 */ |
| #define ADDA6_MTKAIFV4_RXIF_SYNC_CNT_TABLE_LOW_SFT 0 |
| #define ADDA6_MTKAIFV4_RXIF_SYNC_CNT_TABLE_LOW_MASK 0xff |
| #define ADDA6_MTKAIFV4_RXIF_SYNC_CNT_TABLE_LOW_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_MTKAIFV4_RX_CFG1_3 */ |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_SFT 0 |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_MASK 0x1f |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_SYNC_SEARCH_TABLE_MASK_SFT (0x1f << 0) |
| |
| /* AFE_MTKAIFV4_RX_CFG */ |
| #define MT6338_MTKAIFV4_ADDA_IN_EN_SEL_SFT 0 |
| #define MT6338_MTKAIFV4_ADDA_IN_EN_SEL_MASK 0x1 |
| #define MT6338_MTKAIFV4_ADDA_IN_EN_SEL_MASK_SFT (0x1 << 0) |
| #define MT6338_MTKAIFV4_ADDA6_IN_EN_SEL_SFT 1 |
| #define MT6338_MTKAIFV4_ADDA6_IN_EN_SEL_MASK 0x1 |
| #define MT6338_MTKAIFV4_ADDA6_IN_EN_SEL_MASK_SFT (0x1 << 1) |
| #define MT6338_MTKAIFV4_RXIF_LOOPBACK_MODE_SFT 2 |
| #define MT6338_MTKAIFV4_RXIF_LOOPBACK_MODE_MASK 0x1 |
| #define MT6338_MTKAIFV4_RXIF_LOOPBACK_MODE_MASK_SFT (0x1 << 2) |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_LOOPBACK_MODE_SFT 3 |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_LOOPBACK_MODE_MASK 0x1 |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_LOOPBACK_MODE_MASK_SFT (0x1 << 3) |
| #define MT6338_MTKAIFV4_RXIF_EN_SEL_SFT 4 |
| #define MT6338_MTKAIFV4_RXIF_EN_SEL_MASK 0x1 |
| #define MT6338_MTKAIFV4_RXIF_EN_SEL_MASK_SFT (0x1 << 4) |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_EN_SEL_SFT 5 |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_EN_SEL_MASK 0x1 |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_EN_SEL_MASK_SFT (0x1 << 5) |
| #define MT6338_MTKAIFV4_RXIF_CLKINV_SFT 6 |
| #define MT6338_MTKAIFV4_RXIF_CLKINV_MASK 0x1 |
| #define MT6338_MTKAIFV4_RXIF_CLKINV_MASK_SFT (0x1 << 6) |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_CLKINV_SFT 7 |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_CLKINV_MASK 0x1 |
| #define MT6338_ADDA6_MTKAIFV4_RXIF_CLKINV_MASK_SFT (0x1 << 7) |
| |
| /* AFE_ADDA_MTKAIFV4_TX_SYNCWORD_CFG_0 */ |
| #define ADDA_MTKAIFV4_TXIF_SYNCWORD_7_0_SFT 0 |
| #define ADDA_MTKAIFV4_TXIF_SYNCWORD_7_0_MASK 0xff |
| #define ADDA_MTKAIFV4_TXIF_SYNCWORD_7_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_MTKAIFV4_TX_SYNCWORD_CFG_1 */ |
| #define ADDA_MTKAIFV4_TXIF_SYNCWORD_15_8_SFT 0 |
| #define ADDA_MTKAIFV4_TXIF_SYNCWORD_15_8_MASK 0xff |
| #define ADDA_MTKAIFV4_TXIF_SYNCWORD_15_8_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_MTKAIFV4_TX_SYNCWORD_CFG_2 */ |
| #define ADDA6_MTKAIFV4_TXIF_SYNCWORD_7_0_SFT 0 |
| #define ADDA6_MTKAIFV4_TXIF_SYNCWORD_7_0_MASK 0xff |
| #define ADDA6_MTKAIFV4_TXIF_SYNCWORD_7_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_MTKAIFV4_TX_SYNCWORD_CFG_3 */ |
| #define ADDA6_MTKAIFV4_TXIF_SYNCWORD_15_8_SFT 0 |
| #define ADDA6_MTKAIFV4_TXIF_SYNCWORD_15_8_MASK 0xff |
| #define ADDA6_MTKAIFV4_TXIF_SYNCWORD_15_8_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_MTKAIFV4_RX_SYNCWORD_CFG_0 */ |
| #define ADDA_MTKAIFV4_RXIF_SYNCWORD_7_0_SFT 0 |
| #define ADDA_MTKAIFV4_RXIF_SYNCWORD_7_0_MASK 0xff |
| #define ADDA_MTKAIFV4_RXIF_SYNCWORD_7_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_MTKAIFV4_RX_SYNCWORD_CFG_1 */ |
| #define ADDA_MTKAIFV4_RXIF_SYNCWORD_15_8_SFT 0 |
| #define ADDA_MTKAIFV4_RXIF_SYNCWORD_15_8_MASK 0xff |
| #define ADDA_MTKAIFV4_RXIF_SYNCWORD_15_8_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_MTKAIFV4_RX_SYNCWORD_CFG_2 */ |
| #define ADDA6_MTKAIFV4_RXIF_SYNCWORD_7_0_SFT 0 |
| #define ADDA6_MTKAIFV4_RXIF_SYNCWORD_7_0_MASK 0xff |
| #define ADDA6_MTKAIFV4_RXIF_SYNCWORD_7_0_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_MTKAIFV4_RX_SYNCWORD_CFG_3 */ |
| #define ADDA6_MTKAIFV4_RXIF_SYNCWORD_15_8_SFT 0 |
| #define ADDA6_MTKAIFV4_RXIF_SYNCWORD_15_8_MASK 0xff |
| #define ADDA6_MTKAIFV4_RXIF_SYNCWORD_15_8_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_MTKAIFV4_MON0 */ |
| #define MTKAIFV4_RXIF_ADC_FIFO_READ_POINTER_SFT 0 |
| #define MTKAIFV4_RXIF_ADC_FIFO_READ_POINTER_MASK 0xf |
| #define MTKAIFV4_RXIF_ADC_FIFO_READ_POINTER_MASK_SFT (0xf << 0) |
| #define MTKAIFV4_RXIF_ADC_FIFO_WRITE_POINTER_SFT 4 |
| #define MTKAIFV4_RXIF_ADC_FIFO_WRITE_POINTER_MASK 0xf |
| #define MTKAIFV4_RXIF_ADC_FIFO_WRITE_POINTER_MASK_SFT (0xf << 4) |
| |
| /* AFE_ADDA_MTKAIFV4_MON0_H */ |
| #define MTKAIFV4_RXIF_ADC_FIFO_STATUS_SFT 0 |
| #define MTKAIFV4_RXIF_ADC_FIFO_STATUS_MASK 0xf |
| #define MTKAIFV4_RXIF_ADC_FIFO_STATUS_MASK_SFT (0xf << 0) |
| #define MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_SFT 4 |
| #define MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_MASK 0x1 |
| #define MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_MASK_SFT (0x1 << 4) |
| #define MTKAIFV4_PROTOCOL3_RXIF_SDATA_IN_SFT 5 |
| #define MTKAIFV4_PROTOCOL3_RXIF_SDATA_IN_MASK 0x1 |
| #define MTKAIFV4_PROTOCOL3_RXIF_SDATA_IN_MASK_SFT (0x1 << 5) |
| #define MTKAIFV4_TXIF_SDATA_OUT_SFT 6 |
| #define MTKAIFV4_TXIF_SDATA_OUT_MASK 0x1 |
| #define MTKAIFV4_TXIF_SDATA_OUT_MASK_SFT (0x1 << 6) |
| |
| /* AFE_ADDA_MTKAIFV4_MON1_0 */ |
| #define MTKAIFV4_RXIF_OUT_CH1_SFT 0 |
| #define MTKAIFV4_RXIF_OUT_CH1_MASK 0xff |
| #define MTKAIFV4_RXIF_OUT_CH1_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_MTKAIFV4_MON1_1 */ |
| #define MTKAIFV4_RXIF_OUT_CH2_SFT 0 |
| #define MTKAIFV4_RXIF_OUT_CH2_MASK 0xff |
| #define MTKAIFV4_RXIF_OUT_CH2_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_MTKAIFV4_MON1_2 */ |
| #define MTKAIFV4_RXIF_OUT_CH3_SFT 0 |
| #define MTKAIFV4_RXIF_OUT_CH3_MASK 0xff |
| #define MTKAIFV4_RXIF_OUT_CH3_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA_MTKAIFV4_MON1_3 */ |
| #define MTKAIFV4_RXIF_OUT_CH4_SFT 0 |
| #define MTKAIFV4_RXIF_OUT_CH4_MASK 0xff |
| #define MTKAIFV4_RXIF_OUT_CH4_MASK_SFT (0xff << 0) |
| |
| /* AFE_ADDA6_MTKAIFV4_MON0 */ |
| #define ADDA6_MTKAIFV4_RXIF_ADC_FIFO_READ_POINTER_SFT 0 |
| #define ADDA6_MTKAIFV4_RXIF_ADC_FIFO_READ_POINTER_MASK 0xf |
| #define ADDA6_MTKAIFV4_RXIF_ADC_FIFO_READ_POINTER_MASK_SFT (0xf << 0) |
| #define ADDA6_MTKAIFV4_RXIF_ADC_FIFO_WRITE_POINTER_SFT 4 |
| #define ADDA6_MTKAIFV4_RXIF_ADC_FIFO_WRITE_POINTER_MASK 0xf |
| #define ADDA6_MTKAIFV4_RXIF_ADC_FIFO_WRITE_POINTER_MASK_SFT (0xf << 4) |
| |
| /* AFE_ADDA6_MTKAIFV4_MON0_H */ |
| #define ADDA6_MTKAIFV4_RXIF_ADC_FIFO_STATUS_SFT 0 |
| #define ADDA6_MTKAIFV4_RXIF_ADC_FIFO_STATUS_MASK 0xf |
| #define ADDA6_MTKAIFV4_RXIF_ADC_FIFO_STATUS_MASK_SFT (0xf << 0) |
| #define ADDA6_MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_SFT 4 |
| #define ADDA6_MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_MASK 0x1 |
| #define ADDA6_MTKAIFV4_RXIF_SEARCH_FAIL_FLAG_MASK_SFT (0x1 << 4) |
| #define ADDA6_MTKAIFV3_PROTOCOL3_RXIF_SDATA_IN_SFT 5 |
| #define ADDA6_MTKAIFV3_PROTOCOL3_RXIF_SDATA_IN_MASK 0x1 |
| #define ADDA6_MTKAIFV3_PROTOCOL3_RXIF_SDATA_IN_MASK_SFT (0x1 << 5) |
| #define ADDA6_MTKAIFV4_TXIF_SDATA_OUT_SFT 6 |
| #define ADDA6_MTKAIFV4_TXIF_SDATA_OUT_MASK 0x1 |
| #define ADDA6_MTKAIFV4_TXIF_SDATA_OUT_MASK_SFT (0x1 << 6) |
| |
| /* AUDIO_DIG_20TH_DSN_ID */ |
| #define AUDIO_DIG_20TH_ANA_ID_SFT 0 |
| #define AUDIO_DIG_20TH_ANA_ID_MASK 0xff |
| #define AUDIO_DIG_20TH_ANA_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_20TH_DSN_ID_H */ |
| #define AUDIO_DIG_20TH_DIG_ID_SFT 0 |
| #define AUDIO_DIG_20TH_DIG_ID_MASK 0xff |
| #define AUDIO_DIG_20TH_DIG_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_20TH_DSN_REV0 */ |
| #define AUDIO_DIG_20TH_ANA_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_20TH_ANA_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_20TH_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_20TH_ANA_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_20TH_ANA_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_20TH_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_20TH_DSN_REV0_H */ |
| #define AUDIO_DIG_20TH_DIG_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_20TH_DIG_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_20TH_DIG_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_20TH_DIG_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_20TH_DIG_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_20TH_DIG_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_20TH_DSN_DBI */ |
| #define AUDIO_DIG_20TH_DSN_CBS_SFT 0 |
| #define AUDIO_DIG_20TH_DSN_CBS_MASK 0x3 |
| #define AUDIO_DIG_20TH_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDIO_DIG_20TH_DSN_BIX_SFT 2 |
| #define AUDIO_DIG_20TH_DSN_BIX_MASK 0x3 |
| #define AUDIO_DIG_20TH_DSN_BIX_MASK_SFT (0x3 << 2) |
| |
| /* AUDIO_DIG_20TH_DSN_DBI_H */ |
| #define AUDIO_DIG_20_ESP_SFT 0 |
| #define AUDIO_DIG_20_ESP_MASK 0xff |
| #define AUDIO_DIG_20_ESP_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_20TH_DSN_DXI */ |
| #define AUDIO_DIG_20TH_DSN_FPI_SFT 0 |
| #define AUDIO_DIG_20TH_DSN_FPI_MASK 0xff |
| #define AUDIO_DIG_20TH_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON0_0 */ |
| #define RG_ETDM_IN0_CON0_0_SFT 0 |
| #define RG_ETDM_IN0_CON0_0_MASK 0xff |
| #define RG_ETDM_IN0_CON0_0_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON0_1 */ |
| #define RG_ETDM_IN0_CON0_1_SFT 0 |
| #define RG_ETDM_IN0_CON0_1_MASK 0xff |
| #define RG_ETDM_IN0_CON0_1_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON0_2 */ |
| #define RG_ETDM_IN0_CON0_2_SFT 0 |
| #define RG_ETDM_IN0_CON0_2_MASK 0xff |
| #define RG_ETDM_IN0_CON0_2_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON0_3 */ |
| #define RG_ETDM_IN0_CON0_3_SFT 0 |
| #define RG_ETDM_IN0_CON0_3_MASK 0xff |
| #define RG_ETDM_IN0_CON0_3_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON1_0 */ |
| #define RG_ETDM_IN0_CON1_0_SFT 0 |
| #define RG_ETDM_IN0_CON1_0_MASK 0xff |
| #define RG_ETDM_IN0_CON1_0_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON1_1 */ |
| #define RG_ETDM_IN0_CON1_1_SFT 0 |
| #define RG_ETDM_IN0_CON1_1_MASK 0xff |
| #define RG_ETDM_IN0_CON1_1_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON1_2 */ |
| #define RG_ETDM_IN0_CON1_2_SFT 0 |
| #define RG_ETDM_IN0_CON1_2_MASK 0xff |
| #define RG_ETDM_IN0_CON1_2_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON1_3 */ |
| #define RG_ETDM_IN0_CON1_3_SFT 0 |
| #define RG_ETDM_IN0_CON1_3_MASK 0xff |
| #define RG_ETDM_IN0_CON1_3_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON2_0 */ |
| #define RG_ETDM_IN0_CON2_0_SFT 0 |
| #define RG_ETDM_IN0_CON2_0_MASK 0xff |
| #define RG_ETDM_IN0_CON2_0_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON2_1 */ |
| #define RG_ETDM_IN0_CON2_1_SFT 0 |
| #define RG_ETDM_IN0_CON2_1_MASK 0xff |
| #define RG_ETDM_IN0_CON2_1_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON2_2 */ |
| #define RG_ETDM_IN0_CON2_2_SFT 0 |
| #define RG_ETDM_IN0_CON2_2_MASK 0xff |
| #define RG_ETDM_IN0_CON2_2_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON2_3 */ |
| #define RG_ETDM_IN0_CON2_3_SFT 0 |
| #define RG_ETDM_IN0_CON2_3_MASK 0xff |
| #define RG_ETDM_IN0_CON2_3_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON3_0 */ |
| #define RG_ETDM_IN0_CON3_0_SFT 0 |
| #define RG_ETDM_IN0_CON3_0_MASK 0xff |
| #define RG_ETDM_IN0_CON3_0_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON3_1 */ |
| #define RG_ETDM_IN0_CON3_1_SFT 0 |
| #define RG_ETDM_IN0_CON3_1_MASK 0xff |
| #define RG_ETDM_IN0_CON3_1_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON3_2 */ |
| #define RG_ETDM_IN0_CON3_2_SFT 0 |
| #define RG_ETDM_IN0_CON3_2_MASK 0xff |
| #define RG_ETDM_IN0_CON3_2_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON3_3 */ |
| #define RG_ETDM_IN0_CON3_3_SFT 0 |
| #define RG_ETDM_IN0_CON3_3_MASK 0xff |
| #define RG_ETDM_IN0_CON3_3_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON4_0 */ |
| #define RG_ETDM_IN0_CON4_0_SFT 0 |
| #define RG_ETDM_IN0_CON4_0_MASK 0xff |
| #define RG_ETDM_IN0_CON4_0_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON4_1 */ |
| #define RG_ETDM_IN0_CON4_1_SFT 0 |
| #define RG_ETDM_IN0_CON4_1_MASK 0xff |
| #define RG_ETDM_IN0_CON4_1_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON4_2 */ |
| #define RG_ETDM_IN0_CON4_2_SFT 0 |
| #define RG_ETDM_IN0_CON4_2_MASK 0xff |
| #define RG_ETDM_IN0_CON4_2_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON4_3 */ |
| #define RG_ETDM_IN0_CON4_3_SFT 0 |
| #define RG_ETDM_IN0_CON4_3_MASK 0xff |
| #define RG_ETDM_IN0_CON4_3_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON5_0 */ |
| #define RG_ETDM_IN0_CON5_0_SFT 0 |
| #define RG_ETDM_IN0_CON5_0_MASK 0xff |
| #define RG_ETDM_IN0_CON5_0_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON5_1 */ |
| #define RG_ETDM_IN0_CON5_1_SFT 0 |
| #define RG_ETDM_IN0_CON5_1_MASK 0xff |
| #define RG_ETDM_IN0_CON5_1_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON5_2 */ |
| #define RG_ETDM_IN0_CON5_2_SFT 0 |
| #define RG_ETDM_IN0_CON5_2_MASK 0xff |
| #define RG_ETDM_IN0_CON5_2_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON5_3 */ |
| #define RG_ETDM_IN0_CON5_3_SFT 0 |
| #define RG_ETDM_IN0_CON5_3_MASK 0xff |
| #define RG_ETDM_IN0_CON5_3_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON6_0 */ |
| #define RG_ETDM_IN0_CON6_0_SFT 0 |
| #define RG_ETDM_IN0_CON6_0_MASK 0xff |
| #define RG_ETDM_IN0_CON6_0_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON6_1 */ |
| #define RG_ETDM_IN0_CON6_1_SFT 0 |
| #define RG_ETDM_IN0_CON6_1_MASK 0xff |
| #define RG_ETDM_IN0_CON6_1_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON6_2 */ |
| #define RG_ETDM_IN0_CON6_2_SFT 0 |
| #define RG_ETDM_IN0_CON6_2_MASK 0xff |
| #define RG_ETDM_IN0_CON6_2_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON6_3 */ |
| #define RG_ETDM_IN0_CON6_3_SFT 0 |
| #define RG_ETDM_IN0_CON6_3_MASK 0xff |
| #define RG_ETDM_IN0_CON6_3_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON7_0 */ |
| #define RG_ETDM_IN0_CON7_0_SFT 0 |
| #define RG_ETDM_IN0_CON7_0_MASK 0xff |
| #define RG_ETDM_IN0_CON7_0_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON7_1 */ |
| #define RG_ETDM_IN0_CON7_1_SFT 0 |
| #define RG_ETDM_IN0_CON7_1_MASK 0xff |
| #define RG_ETDM_IN0_CON7_1_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON7_2 */ |
| #define RG_ETDM_IN0_CON7_2_SFT 0 |
| #define RG_ETDM_IN0_CON7_2_MASK 0xff |
| #define RG_ETDM_IN0_CON7_2_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON7_3 */ |
| #define RG_ETDM_IN0_CON7_3_SFT 0 |
| #define RG_ETDM_IN0_CON7_3_MASK 0xff |
| #define RG_ETDM_IN0_CON7_3_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON8_0 */ |
| #define RG_ETDM_IN0_CON8_0_SFT 0 |
| #define RG_ETDM_IN0_CON8_0_MASK 0xff |
| #define RG_ETDM_IN0_CON8_0_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON8_1 */ |
| #define RG_ETDM_IN0_CON8_1_SFT 0 |
| #define RG_ETDM_IN0_CON8_1_MASK 0xff |
| #define RG_ETDM_IN0_CON8_1_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON8_2 */ |
| #define RG_ETDM_IN0_CON8_2_SFT 0 |
| #define RG_ETDM_IN0_CON8_2_MASK 0xff |
| #define RG_ETDM_IN0_CON8_2_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_CON8_3 */ |
| #define RG_ETDM_IN0_CON8_3_SFT 0 |
| #define RG_ETDM_IN0_CON8_3_MASK 0xff |
| #define RG_ETDM_IN0_CON8_3_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON0_0 */ |
| #define RG_ETDM_OUT0_CON0_0_SFT 0 |
| #define RG_ETDM_OUT0_CON0_0_MASK 0xff |
| #define RG_ETDM_OUT0_CON0_0_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON0_1 */ |
| #define RG_ETDM_OUT0_CON0_1_SFT 0 |
| #define RG_ETDM_OUT0_CON0_1_MASK 0xff |
| #define RG_ETDM_OUT0_CON0_1_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON0_2 */ |
| #define RG_ETDM_OUT0_CON0_2_SFT 0 |
| #define RG_ETDM_OUT0_CON0_2_MASK 0xff |
| #define RG_ETDM_OUT0_CON0_2_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON0_3 */ |
| #define RG_ETDM_OUT0_CON0_3_SFT 0 |
| #define RG_ETDM_OUT0_CON0_3_MASK 0xff |
| #define RG_ETDM_OUT0_CON0_3_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON1_0 */ |
| #define RG_ETDM_OUT0_CON1_0_SFT 0 |
| #define RG_ETDM_OUT0_CON1_0_MASK 0xff |
| #define RG_ETDM_OUT0_CON1_0_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON1_1 */ |
| #define RG_ETDM_OUT0_CON1_1_SFT 0 |
| #define RG_ETDM_OUT0_CON1_1_MASK 0xff |
| #define RG_ETDM_OUT0_CON1_1_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON1_2 */ |
| #define RG_ETDM_OUT0_CON1_2_SFT 0 |
| #define RG_ETDM_OUT0_CON1_2_MASK 0xff |
| #define RG_ETDM_OUT0_CON1_2_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON1_3 */ |
| #define RG_ETDM_OUT0_CON1_3_SFT 0 |
| #define RG_ETDM_OUT0_CON1_3_MASK 0xff |
| #define RG_ETDM_OUT0_CON1_3_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON2_0 */ |
| #define RG_ETDM_OUT0_CON2_0_SFT 0 |
| #define RG_ETDM_OUT0_CON2_0_MASK 0xff |
| #define RG_ETDM_OUT0_CON2_0_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON2_1 */ |
| #define RG_ETDM_OUT0_CON2_1_SFT 0 |
| #define RG_ETDM_OUT0_CON2_1_MASK 0xff |
| #define RG_ETDM_OUT0_CON2_1_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON2_2 */ |
| #define RG_ETDM_OUT0_CON2_2_SFT 0 |
| #define RG_ETDM_OUT0_CON2_2_MASK 0xff |
| #define RG_ETDM_OUT0_CON2_2_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON2_3 */ |
| #define RG_ETDM_OUT0_CON2_3_SFT 0 |
| #define RG_ETDM_OUT0_CON2_3_MASK 0xff |
| #define RG_ETDM_OUT0_CON2_3_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON3_0 */ |
| #define RG_ETDM_OUT0_CON3_0_SFT 0 |
| #define RG_ETDM_OUT0_CON3_0_MASK 0xff |
| #define RG_ETDM_OUT0_CON3_0_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON3_1 */ |
| #define RG_ETDM_OUT0_CON3_1_SFT 0 |
| #define RG_ETDM_OUT0_CON3_1_MASK 0xff |
| #define RG_ETDM_OUT0_CON3_1_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON3_2 */ |
| #define RG_ETDM_OUT0_CON3_2_SFT 0 |
| #define RG_ETDM_OUT0_CON3_2_MASK 0xff |
| #define RG_ETDM_OUT0_CON3_2_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON3_3 */ |
| #define RG_ETDM_OUT0_CON3_3_SFT 0 |
| #define RG_ETDM_OUT0_CON3_3_MASK 0xff |
| #define RG_ETDM_OUT0_CON3_3_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON4_0 */ |
| #define RG_ETDM_OUT0_CON4_0_SFT 0 |
| #define RG_ETDM_OUT0_CON4_0_MASK 0xff |
| #define RG_ETDM_OUT0_CON4_0_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON4_1 */ |
| #define RG_ETDM_OUT0_CON4_1_SFT 0 |
| #define RG_ETDM_OUT0_CON4_1_MASK 0xff |
| #define RG_ETDM_OUT0_CON4_1_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON4_2 */ |
| #define RG_ETDM_OUT0_CON4_2_SFT 0 |
| #define RG_ETDM_OUT0_CON4_2_MASK 0xff |
| #define RG_ETDM_OUT0_CON4_2_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON4_3 */ |
| #define RG_ETDM_OUT0_CON4_3_SFT 0 |
| #define RG_ETDM_OUT0_CON4_3_MASK 0xff |
| #define RG_ETDM_OUT0_CON4_3_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON5_0 */ |
| #define RG_ETDM_OUT0_CON5_0_SFT 0 |
| #define RG_ETDM_OUT0_CON5_0_MASK 0xff |
| #define RG_ETDM_OUT0_CON5_0_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON5_1 */ |
| #define RG_ETDM_OUT0_CON5_1_SFT 0 |
| #define RG_ETDM_OUT0_CON5_1_MASK 0xff |
| #define RG_ETDM_OUT0_CON5_1_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON5_2 */ |
| #define RG_ETDM_OUT0_CON5_2_SFT 0 |
| #define RG_ETDM_OUT0_CON5_2_MASK 0xff |
| #define RG_ETDM_OUT0_CON5_2_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON5_3 */ |
| #define RG_ETDM_OUT0_CON5_3_SFT 0 |
| #define RG_ETDM_OUT0_CON5_3_MASK 0xff |
| #define RG_ETDM_OUT0_CON5_3_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON6_0 */ |
| #define RG_ETDM_OUT0_CON6_0_SFT 0 |
| #define RG_ETDM_OUT0_CON6_0_MASK 0xff |
| #define RG_ETDM_OUT0_CON6_0_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON6_1 */ |
| #define RG_ETDM_OUT0_CON6_1_SFT 0 |
| #define RG_ETDM_OUT0_CON6_1_MASK 0xff |
| #define RG_ETDM_OUT0_CON6_1_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON6_2 */ |
| #define RG_ETDM_OUT0_CON6_2_SFT 0 |
| #define RG_ETDM_OUT0_CON6_2_MASK 0xff |
| #define RG_ETDM_OUT0_CON6_2_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON6_3 */ |
| #define RG_ETDM_OUT0_CON6_3_SFT 0 |
| #define RG_ETDM_OUT0_CON6_3_MASK 0xff |
| #define RG_ETDM_OUT0_CON6_3_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON7_0 */ |
| #define RG_ETDM_OUT0_CON7_0_SFT 0 |
| #define RG_ETDM_OUT0_CON7_0_MASK 0xff |
| #define RG_ETDM_OUT0_CON7_0_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON7_1 */ |
| #define RG_ETDM_OUT0_CON7_1_SFT 0 |
| #define RG_ETDM_OUT0_CON7_1_MASK 0xff |
| #define RG_ETDM_OUT0_CON7_1_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON7_2 */ |
| #define RG_ETDM_OUT0_CON7_2_SFT 0 |
| #define RG_ETDM_OUT0_CON7_2_MASK 0xff |
| #define RG_ETDM_OUT0_CON7_2_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON7_3 */ |
| #define RG_ETDM_OUT0_CON7_3_SFT 0 |
| #define RG_ETDM_OUT0_CON7_3_MASK 0xff |
| #define RG_ETDM_OUT0_CON7_3_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON8_0 */ |
| #define RG_ETDM_OUT0_CON8_0_SFT 0 |
| #define RG_ETDM_OUT0_CON8_0_MASK 0xff |
| #define RG_ETDM_OUT0_CON8_0_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON8_1 */ |
| #define RG_ETDM_OUT0_CON8_1_SFT 0 |
| #define RG_ETDM_OUT0_CON8_1_MASK 0xff |
| #define RG_ETDM_OUT0_CON8_1_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON8_2 */ |
| #define RG_ETDM_OUT0_CON8_2_SFT 0 |
| #define RG_ETDM_OUT0_CON8_2_MASK 0xff |
| #define RG_ETDM_OUT0_CON8_2_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON8_3 */ |
| #define RG_ETDM_OUT0_CON8_3_SFT 0 |
| #define RG_ETDM_OUT0_CON8_3_MASK 0xff |
| #define RG_ETDM_OUT0_CON8_3_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON9_0 */ |
| #define RG_ETDM_OUT0_CON9_0_SFT 0 |
| #define RG_ETDM_OUT0_CON9_0_MASK 0xff |
| #define RG_ETDM_OUT0_CON9_0_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON9_1 */ |
| #define RG_ETDM_OUT0_CON9_1_SFT 0 |
| #define RG_ETDM_OUT0_CON9_1_MASK 0xff |
| #define RG_ETDM_OUT0_CON9_1_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON9_2 */ |
| #define RG_ETDM_OUT0_CON9_2_SFT 0 |
| #define RG_ETDM_OUT0_CON9_2_MASK 0xff |
| #define RG_ETDM_OUT0_CON9_2_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_CON9_3 */ |
| #define RG_ETDM_OUT0_CON9_3_SFT 0 |
| #define RG_ETDM_OUT0_CON9_3_MASK 0xff |
| #define RG_ETDM_OUT0_CON9_3_MASK_SFT (0xff << 0) |
| |
| /* ETDM_0_3_COWORK_CON0_0 */ |
| #define RG_ETDM_0_3_COWORK_CON0_0_SFT 0 |
| #define RG_ETDM_0_3_COWORK_CON0_0_MASK 0xff |
| #define RG_ETDM_0_3_COWORK_CON0_0_MASK_SFT (0xff << 0) |
| |
| /* ETDM_0_3_COWORK_CON0_1 */ |
| #define RG_ETDM_0_3_COWORK_CON0_1_SFT 0 |
| #define RG_ETDM_0_3_COWORK_CON0_1_MASK 0xff |
| #define RG_ETDM_0_3_COWORK_CON0_1_MASK_SFT (0xff << 0) |
| |
| /* ETDM_0_3_COWORK_CON0_2 */ |
| #define RG_ETDM_0_3_COWORK_CON0_2_SFT 0 |
| #define RG_ETDM_0_3_COWORK_CON0_2_MASK 0xff |
| #define RG_ETDM_0_3_COWORK_CON0_2_MASK_SFT (0xff << 0) |
| |
| /* ETDM_0_3_COWORK_CON0_3 */ |
| #define RG_ETDM_0_3_COWORK_CON0_3_SFT 0 |
| #define RG_ETDM_0_3_COWORK_CON0_3_MASK 0xff |
| #define RG_ETDM_0_3_COWORK_CON0_3_MASK_SFT (0xff << 0) |
| |
| /* ETDM_0_3_COWORK_CON1_0 */ |
| #define RG_ETDM_0_3_COWORK_CON1_0_SFT 0 |
| #define RG_ETDM_0_3_COWORK_CON1_0_MASK 0xff |
| #define RG_ETDM_0_3_COWORK_CON1_0_MASK_SFT (0xff << 0) |
| |
| /* ETDM_0_3_COWORK_CON1_1 */ |
| #define RG_ETDM_0_3_COWORK_CON1_1_SFT 0 |
| #define RG_ETDM_0_3_COWORK_CON1_1_MASK 0xff |
| #define RG_ETDM_0_3_COWORK_CON1_1_MASK_SFT (0xff << 0) |
| |
| /* ETDM_0_3_COWORK_CON1_2 */ |
| #define RG_ETDM_0_3_COWORK_CON1_2_SFT 0 |
| #define RG_ETDM_0_3_COWORK_CON1_2_MASK 0xff |
| #define RG_ETDM_0_3_COWORK_CON1_2_MASK_SFT (0xff << 0) |
| |
| /* ETDM_0_3_COWORK_CON1_3 */ |
| #define RG_ETDM_0_3_COWORK_CON1_3_SFT 0 |
| #define RG_ETDM_0_3_COWORK_CON1_3_MASK 0xff |
| #define RG_ETDM_0_3_COWORK_CON1_3_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN0_MON_0 */ |
| #define RG_ETDM_IN0_MON_0_SFT 0 |
| #define RG_ETDM_IN0_MON_0_MASK 0xff |
| #define RG_ETDM_IN0_MON_0_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN1_MON_1 */ |
| #define RG_ETDM_IN0_MON_1_SFT 0 |
| #define RG_ETDM_IN0_MON_1_MASK 0xff |
| #define RG_ETDM_IN0_MON_1_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN2_MON_2 */ |
| #define RG_ETDM_IN0_MON_2_SFT 0 |
| #define RG_ETDM_IN0_MON_2_MASK 0xff |
| #define RG_ETDM_IN0_MON_2_MASK_SFT (0xff << 0) |
| |
| /* ETDM_IN3_MON_3 */ |
| #define RG_ETDM_IN0_MON_3_SFT 0 |
| #define RG_ETDM_IN0_MON_3_MASK 0xff |
| #define RG_ETDM_IN0_MON_3_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT0_MON_0 */ |
| #define RG_ETDM_OUT0_MON_0_SFT 0 |
| #define RG_ETDM_OUT0_MON_0_MASK 0xff |
| #define RG_ETDM_OUT0_MON_0_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT1_MON_1 */ |
| #define RG_ETDM_OUT0_MON_1_SFT 0 |
| #define RG_ETDM_OUT0_MON_1_MASK 0xff |
| #define RG_ETDM_OUT0_MON_1_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT2_MON_2 */ |
| #define RG_ETDM_OUT0_MON_2_SFT 0 |
| #define RG_ETDM_OUT0_MON_2_MASK 0xff |
| #define RG_ETDM_OUT0_MON_2_MASK_SFT (0xff << 0) |
| |
| /* ETDM_OUT3_MON_3 */ |
| #define RG_ETDM_OUT0_MON_3_SFT 0 |
| #define RG_ETDM_OUT0_MON_3_MASK 0xff |
| #define RG_ETDM_OUT0_MON_3_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_21TH_DSN_ID */ |
| #define AUDIO_DIG_21TH_ANA_ID_SFT 0 |
| #define AUDIO_DIG_21TH_ANA_ID_MASK 0xff |
| #define AUDIO_DIG_21TH_ANA_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_21TH_DSN_ID_H */ |
| #define AUDIO_DIG_21TH_DIG_ID_SFT 0 |
| #define AUDIO_DIG_21TH_DIG_ID_MASK 0xff |
| #define AUDIO_DIG_21TH_DIG_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_21TH_DSN_REV0 */ |
| #define AUDIO_DIG_21TH_ANA_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_21TH_ANA_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_21TH_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_21TH_ANA_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_21TH_ANA_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_21TH_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_21TH_DSN_REV0_H */ |
| #define AUDIO_DIG_21TH_DIG_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_21TH_DIG_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_21TH_DIG_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_21TH_DIG_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_21TH_DIG_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_21TH_DIG_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_21TH_DSN_DBI */ |
| #define AUDIO_DIG_21TH_DSN_CBS_SFT 0 |
| #define AUDIO_DIG_21TH_DSN_CBS_MASK 0x3 |
| #define AUDIO_DIG_21TH_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDIO_DIG_21TH_DSN_BIX_SFT 2 |
| #define AUDIO_DIG_21TH_DSN_BIX_MASK 0x3 |
| #define AUDIO_DIG_21TH_DSN_BIX_MASK_SFT (0x3 << 2) |
| |
| /* AUDIO_DIG_21TH_DSN_DBI_H */ |
| #define AUDIO_DIG_21_ESP_SFT 0 |
| #define AUDIO_DIG_21_ESP_MASK 0xff |
| #define AUDIO_DIG_21_ESP_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_21TH_DSN_DXI */ |
| #define AUDIO_DIG_21TH_DSN_FPI_SFT 0 |
| #define AUDIO_DIG_21TH_DSN_FPI_MASK 0xff |
| #define AUDIO_DIG_21TH_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN1_CON0_1 */ |
| #define MT6338_GAIN1_SAMPLE_PER_STEP_SFT 0 |
| #define MT6338_GAIN1_SAMPLE_PER_STEP_MASK 0xff |
| #define MT6338_GAIN1_SAMPLE_PER_STEP_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN1_CON0_0 */ |
| #define GAIN1_MODE_SFT 4 |
| #define GAIN1_MODE_MASK 0xf |
| #define GAIN1_MODE_MASK_SFT (0xf << 4) |
| #define GAIN1_ON_SFT 0 |
| #define GAIN1_ON_MASK 0x1 |
| #define GAIN1_ON_MASK_SFT (0x1 << 0) |
| |
| /* AFE_GAIN1_CON1_3 */ |
| #define GAIN1_TARGET_H_SFT 0 |
| #define GAIN1_TARGET_H_MASK 0xf |
| #define GAIN1_TARGET_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_GAIN1_CON1_2 */ |
| #define GAIN1_TARGET_M_SFT 0 |
| #define GAIN1_TARGET_M_MASK 0xff |
| #define GAIN1_TARGET_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN1_CON1_1 */ |
| #define GAIN1_TARGET_M2_SFT 0 |
| #define GAIN1_TARGET_M2_MASK 0xff |
| #define GAIN1_TARGET_M2_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN1_CON1_0 */ |
| #define GAIN1_TARGET_L_SFT 0 |
| #define GAIN1_TARGET_L_MASK 0xff |
| #define GAIN1_TARGET_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN1_CON2_2 */ |
| #define GAIN1_DOWN_STEP_H_SFT 0 |
| #define GAIN1_DOWN_STEP_H_MASK 0xf |
| #define GAIN1_DOWN_STEP_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_GAIN1_CON2_1 */ |
| #define GAIN1_DOWN_STEP_M_SFT 0 |
| #define GAIN1_DOWN_STEP_M_MASK 0xff |
| #define GAIN1_DOWN_STEP_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN1_CON2_0 */ |
| #define GAIN1_DOWN_STEP_L_SFT 0 |
| #define GAIN1_DOWN_STEP_L_MASK 0xff |
| #define GAIN1_DOWN_STEP_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN1_CON3_2 */ |
| #define GAIN1_UP_STEP_H_SFT 0 |
| #define GAIN1_UP_STEP_H_MASK 0xf |
| #define GAIN1_UP_STEP_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_GAIN1_CON3_1 */ |
| #define GAIN1_UP_STEP_M_SFT 0 |
| #define GAIN1_UP_STEP_M_MASK 0xff |
| #define GAIN1_UP_STEP_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN1_CON3_0 */ |
| #define GAIN1_UP_STEP_L_SFT 0 |
| #define GAIN1_UP_STEP_L_MASK 0xff |
| #define GAIN1_UP_STEP_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN1_CUR_3 */ |
| #define GAIN1_CUR_H_SFT 0 |
| #define GAIN1_CUR_H_MASK 0xf |
| #define GAIN1_CUR_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_GAIN1_CUR_2 */ |
| #define GAIN1_CUR_M_SFT 0 |
| #define GAIN1_CUR_M_MASK 0xff |
| #define GAIN1_CUR_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN1_CUR_1 */ |
| #define GAIN1_CUR_M2_SFT 0 |
| #define GAIN1_CUR_M2_MASK 0xff |
| #define GAIN1_CUR_M2_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN1_CUR_0 */ |
| #define GAIN1_CUR_L_SFT 0 |
| #define GAIN1_CUR_L_MASK 0xff |
| #define GAIN1_CUR_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN1_CUR_PRE_3 */ |
| #define GAIN1_CUR_PRE_H_SFT 0 |
| #define GAIN1_CUR_PRE_H_MASK 0xf |
| #define GAIN1_CUR_PRE_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_GAIN1_CUR_PRE_2 */ |
| #define GAIN1_CUR_PRE_M_SFT 0 |
| #define GAIN1_CUR_PRE_M_MASK 0xff |
| #define GAIN1_CUR_PRE_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN1_CUR_PRE_1 */ |
| #define GAIN1_CUR_PRE_M2_SFT 0 |
| #define GAIN1_CUR_PRE_M2_MASK 0xff |
| #define GAIN1_CUR_PRE_M2_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN1_CUR_PRE_0 */ |
| #define GAIN1_CUR_PRE_L_SFT 0 |
| #define GAIN1_CUR_PRE_L_MASK 0xff |
| #define GAIN1_CUR_PRE_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN2_CON0_1 */ |
| #define MT6338_GAIN2_SAMPLE_PER_STEP_SFT 0 |
| #define MT6338_GAIN2_SAMPLE_PER_STEP_MASK 0xff |
| #define MT6338_GAIN2_SAMPLE_PER_STEP_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN2_CON0_0 */ |
| #define GAIN2_MODE_SFT 4 |
| #define GAIN2_MODE_MASK 0xf |
| #define GAIN2_MODE_MASK_SFT (0xf << 4) |
| #define GAIN2_ON_SFT 0 |
| #define GAIN2_ON_MASK 0x1 |
| #define GAIN2_ON_MASK_SFT (0x1 << 0) |
| |
| /* AFE_GAIN2_CON1_3 */ |
| #define GAIN2_TARGET_H_SFT 0 |
| #define GAIN2_TARGET_H_MASK 0xf |
| #define GAIN2_TARGET_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_GAIN2_CON1_2 */ |
| #define GAIN2_TARGET_M_SFT 0 |
| #define GAIN2_TARGET_M_MASK 0xff |
| #define GAIN2_TARGET_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN2_CON1_1 */ |
| #define GAIN2_TARGET_M2_SFT 0 |
| #define GAIN2_TARGET_M2_MASK 0xff |
| #define GAIN2_TARGET_M2_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN2_CON1_0 */ |
| #define GAIN2_TARGET_L_SFT 0 |
| #define GAIN2_TARGET_L_MASK 0xff |
| #define GAIN2_TARGET_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN2_CON2_2 */ |
| #define GAIN2_DOWN_STEP_H_SFT 0 |
| #define GAIN2_DOWN_STEP_H_MASK 0xf |
| #define GAIN2_DOWN_STEP_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_GAIN2_CON2_1 */ |
| #define GAIN2_DOWN_STEP_M_SFT 0 |
| #define GAIN2_DOWN_STEP_M_MASK 0xff |
| #define GAIN2_DOWN_STEP_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN2_CON2_0 */ |
| #define GAIN2_DOWN_STEP_L_SFT 0 |
| #define GAIN2_DOWN_STEP_L_MASK 0xff |
| #define GAIN2_DOWN_STEP_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN2_CON3_2 */ |
| #define GAIN2_UP_STEP_H_SFT 0 |
| #define GAIN2_UP_STEP_H_MASK 0xf |
| #define GAIN2_UP_STEP_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_GAIN2_CON3_1 */ |
| #define GAIN2_UP_STEP_M_SFT 0 |
| #define GAIN2_UP_STEP_M_MASK 0xff |
| #define GAIN2_UP_STEP_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN2_CON3_0 */ |
| #define GAIN2_UP_STEP_L_SFT 0 |
| #define GAIN2_UP_STEP_L_MASK 0xff |
| #define GAIN2_UP_STEP_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN2_CUR_3 */ |
| #define GAIN2_CUR_H_SFT 0 |
| #define GAIN2_CUR_H_MASK 0xf |
| #define GAIN2_CUR_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_GAIN2_CUR_2 */ |
| #define GAIN2_CUR_M_SFT 0 |
| #define GAIN2_CUR_M_MASK 0xff |
| #define GAIN2_CUR_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN2_CUR_1 */ |
| #define GAIN2_CUR_M2_SFT 0 |
| #define GAIN2_CUR_M2_MASK 0xff |
| #define GAIN2_CUR_M2_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN2_CUR_0 */ |
| #define GAIN2_CUR_L_SFT 0 |
| #define GAIN2_CUR_L_MASK 0xff |
| #define GAIN2_CUR_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN2_CUR_PRE_3 */ |
| #define GAIN2_CUR_PRE_H_SFT 0 |
| #define GAIN2_CUR_PRE_H_MASK 0xf |
| #define GAIN2_CUR_PRE_H_MASK_SFT (0xf << 0) |
| |
| /* AFE_GAIN2_CUR_PRE_2 */ |
| #define GAIN2_CUR_PRE_M_SFT 0 |
| #define GAIN2_CUR_PRE_M_MASK 0xff |
| #define GAIN2_CUR_PRE_M_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN2_CUR_PRE_1 */ |
| #define GAIN2_CUR_PRE_M2_SFT 0 |
| #define GAIN2_CUR_PRE_M2_MASK 0xff |
| #define GAIN2_CUR_PRE_M2_MASK_SFT (0xff << 0) |
| |
| /* AFE_GAIN2_CUR_PRE_0 */ |
| #define GAIN2_CUR_PRE_L_SFT 0 |
| #define GAIN2_CUR_PRE_L_MASK 0xff |
| #define GAIN2_CUR_PRE_L_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_22TH_DSN_ID */ |
| #define AUDIO_DIG_22TH_ANA_ID_SFT 0 |
| #define AUDIO_DIG_22TH_ANA_ID_MASK 0xff |
| #define AUDIO_DIG_22TH_ANA_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_22TH_DSN_ID_H */ |
| #define AUDIO_DIG_22TH_DIG_ID_SFT 0 |
| #define AUDIO_DIG_22TH_DIG_ID_MASK 0xff |
| #define AUDIO_DIG_22TH_DIG_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_22TH_DSN_REV0 */ |
| #define AUDIO_DIG_22TH_ANA_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_22TH_ANA_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_22TH_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_22TH_ANA_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_22TH_ANA_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_22TH_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_22TH_DSN_REV0_H */ |
| #define AUDIO_DIG_22TH_DIG_MINOR_REV_SFT 0 |
| #define AUDIO_DIG_22TH_DIG_MINOR_REV_MASK 0xf |
| #define AUDIO_DIG_22TH_DIG_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDIO_DIG_22TH_DIG_MAJOR_REV_SFT 4 |
| #define AUDIO_DIG_22TH_DIG_MAJOR_REV_MASK 0xf |
| #define AUDIO_DIG_22TH_DIG_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDIO_DIG_22TH_DSN_DBI */ |
| #define AUDIO_DIG_22TH_DSN_CBS_SFT 0 |
| #define AUDIO_DIG_22TH_DSN_CBS_MASK 0x3 |
| #define AUDIO_DIG_22TH_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDIO_DIG_22TH_DSN_BIX_SFT 2 |
| #define AUDIO_DIG_22TH_DSN_BIX_MASK 0x3 |
| #define AUDIO_DIG_22TH_DSN_BIX_MASK_SFT (0x3 << 2) |
| |
| /* AUDIO_DIG_22TH_DSN_DBI_H */ |
| #define AUDIO_DIG_22_ESP_SFT 0 |
| #define AUDIO_DIG_22_ESP_MASK 0xff |
| #define AUDIO_DIG_22_ESP_MASK_SFT (0xff << 0) |
| |
| /* AUDIO_DIG_22TH_DSN_DXI */ |
| #define AUDIO_DIG_22TH_DSN_FPI_SFT 0 |
| #define AUDIO_DIG_22TH_DSN_FPI_MASK 0xff |
| #define AUDIO_DIG_22TH_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON0 */ |
| #define VOW_DOWNCNT_CH1_H_SFT 0 |
| #define VOW_DOWNCNT_CH1_H_MASK 0xff |
| #define VOW_DOWNCNT_CH1_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON1 */ |
| #define VOW_DOWNCNT_CH1_L_SFT 0 |
| #define VOW_DOWNCNT_CH1_L_MASK 0xff |
| #define VOW_DOWNCNT_CH1_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON2 */ |
| #define VOW_DOWNCNT_CH2_H_SFT 0 |
| #define VOW_DOWNCNT_CH2_H_MASK 0xff |
| #define VOW_DOWNCNT_CH2_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON3 */ |
| #define VOW_DOWNCNT_CH2_L_SFT 0 |
| #define VOW_DOWNCNT_CH2_L_MASK 0xff |
| #define VOW_DOWNCNT_CH2_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON4 */ |
| #define VOW_DOWNCNT_CH3_H_SFT 0 |
| #define VOW_DOWNCNT_CH3_H_MASK 0xff |
| #define VOW_DOWNCNT_CH3_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON5 */ |
| #define VOW_DOWNCNT_CH3_L_SFT 0 |
| #define VOW_DOWNCNT_CH3_L_MASK 0xff |
| #define VOW_DOWNCNT_CH3_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON6 */ |
| #define VOW_DOWNCNT_CH4_H_SFT 0 |
| #define VOW_DOWNCNT_CH4_H_MASK 0xff |
| #define VOW_DOWNCNT_CH4_H_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON7 */ |
| #define VOW_DOWNCNT_CH4_L_SFT 0 |
| #define VOW_DOWNCNT_CH4_L_MASK 0xff |
| #define VOW_DOWNCNT_CH4_L_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON8 */ |
| #define K_TMP_MON_CH1_SFT 3 |
| #define K_TMP_MON_CH1_MASK 0xf |
| #define K_TMP_MON_CH1_MASK_SFT (0xf << 3) |
| #define SLT_COUNTER_MON_CH1_SFT 0 |
| #define SLT_COUNTER_MON_CH1_MASK 0x7 |
| #define SLT_COUNTER_MON_CH1_MASK_SFT (0x7 << 0) |
| |
| /* AFE_VOW_VAD_MON9 */ |
| #define VOW_B_CH1_SFT 4 |
| #define VOW_B_CH1_MASK 0x7 |
| #define VOW_B_CH1_MASK_SFT (0x7 << 4) |
| #define VOW_A_CH1_SFT 1 |
| #define VOW_A_CH1_MASK 0x7 |
| #define VOW_A_CH1_MASK_SFT (0x7 << 1) |
| #define SECOND_CNT_START_CH1_SFT 0 |
| #define SECOND_CNT_START_CH1_MASK 0x1 |
| #define SECOND_CNT_START_CH1_MASK_SFT (0x1 << 0) |
| |
| /* AFE_VOW_VAD_MON10 */ |
| #define K_TMP_MON_CH2_SFT 3 |
| #define K_TMP_MON_CH2_MASK 0xf |
| #define K_TMP_MON_CH2_MASK_SFT (0xf << 3) |
| #define SLT_COUNTER_MON_CH2_SFT 0 |
| #define SLT_COUNTER_MON_CH2_MASK 0x7 |
| #define SLT_COUNTER_MON_CH2_MASK_SFT (0x7 << 0) |
| |
| /* AFE_VOW_VAD_MON11 */ |
| #define VOW_B_CH2_SFT 4 |
| #define VOW_B_CH2_MASK 0x7 |
| #define VOW_B_CH2_MASK_SFT (0x7 << 4) |
| #define VOW_A_CH2_SFT 1 |
| #define VOW_A_CH2_MASK 0x7 |
| #define VOW_A_CH2_MASK_SFT (0x7 << 1) |
| #define SECOND_CNT_START_CH2_SFT 0 |
| #define SECOND_CNT_START_CH2_MASK 0x1 |
| #define SECOND_CNT_START_CH2_MASK_SFT (0x1 << 0) |
| |
| /* AFE_VOW_VAD_MON12 */ |
| #define K_TMP_MON_CH3_SFT 3 |
| #define K_TMP_MON_CH3_MASK 0xf |
| #define K_TMP_MON_CH3_MASK_SFT (0xf << 3) |
| #define SLT_COUNTER_MON_CH3_SFT 0 |
| #define SLT_COUNTER_MON_CH3_MASK 0x7 |
| #define SLT_COUNTER_MON_CH3_MASK_SFT (0x7 << 0) |
| |
| /* AFE_VOW_VAD_MON13 */ |
| #define VOW_B_CH3_SFT 4 |
| #define VOW_B_CH3_MASK 0x7 |
| #define VOW_B_CH3_MASK_SFT (0x7 << 4) |
| #define VOW_A_CH3_SFT 1 |
| #define VOW_A_CH3_MASK 0x7 |
| #define VOW_A_CH3_MASK_SFT (0x7 << 1) |
| #define SECOND_CNT_START_CH3_SFT 0 |
| #define SECOND_CNT_START_CH3_MASK 0x1 |
| #define SECOND_CNT_START_CH3_MASK_SFT (0x1 << 0) |
| |
| /* AFE_VOW_VAD_MON14 */ |
| #define K_TMP_MON_CH4_SFT 3 |
| #define K_TMP_MON_CH4_MASK 0xf |
| #define K_TMP_MON_CH4_MASK_SFT (0xf << 3) |
| #define SLT_COUNTER_MON_CH4_SFT 0 |
| #define SLT_COUNTER_MON_CH4_MASK 0x7 |
| #define SLT_COUNTER_MON_CH4_MASK_SFT (0x7 << 0) |
| |
| /* AFE_VOW_VAD_MON15 */ |
| #define VOW_B_CH4_SFT 4 |
| #define VOW_B_CH4_MASK 0x7 |
| #define VOW_B_CH4_MASK_SFT (0x7 << 4) |
| #define VOW_A_CH4_SFT 1 |
| #define VOW_A_CH4_MASK 0x7 |
| #define VOW_A_CH4_MASK_SFT (0x7 << 1) |
| #define SECOND_CNT_START_CH4_SFT 0 |
| #define SECOND_CNT_START_CH4_MASK 0x1 |
| #define SECOND_CNT_START_CH4_MASK_SFT (0x1 << 0) |
| |
| /* AFE_VOW_VAD_MON16 */ |
| #define VOW_S_HH_CH1_SFT 0 |
| #define VOW_S_HH_CH1_MASK 0xff |
| #define VOW_S_HH_CH1_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON17 */ |
| #define VOW_S_HL_CH1_SFT 0 |
| #define VOW_S_HL_CH1_MASK 0xff |
| #define VOW_S_HL_CH1_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON18 */ |
| #define VOW_S_LH_CH1_SFT 0 |
| #define VOW_S_LH_CH1_MASK 0xff |
| #define VOW_S_LH_CH1_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON19 */ |
| #define VOW_S_LL_CH1_SFT 0 |
| #define VOW_S_LL_CH1_MASK 0xff |
| #define VOW_S_LL_CH1_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON20 */ |
| #define VOW_N_HH_CH1_SFT 0 |
| #define VOW_N_HH_CH1_MASK 0xff |
| #define VOW_N_HH_CH1_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON21 */ |
| #define VOW_N_HL_CH1_SFT 0 |
| #define VOW_N_HL_CH1_MASK 0xff |
| #define VOW_N_HL_CH1_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON22 */ |
| #define VOW_N_LH_CH1_SFT 0 |
| #define VOW_N_LH_CH1_MASK 0xff |
| #define VOW_N_LH_CH1_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON23 */ |
| #define VOW_N_LL_CH1_SFT 0 |
| #define VOW_N_LL_CH1_MASK 0xff |
| #define VOW_N_LL_CH1_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON24 */ |
| #define VOW_S_HH_CH2_SFT 0 |
| #define VOW_S_HH_CH2_MASK 0xff |
| #define VOW_S_HH_CH2_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON25 */ |
| #define VOW_S_HL_CH2_SFT 0 |
| #define VOW_S_HL_CH2_MASK 0xff |
| #define VOW_S_HL_CH2_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON26 */ |
| #define VOW_S_LH_CH2_SFT 0 |
| #define VOW_S_LH_CH2_MASK 0xff |
| #define VOW_S_LH_CH2_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON27 */ |
| #define VOW_S_LL_CH2_SFT 0 |
| #define VOW_S_LL_CH2_MASK 0xff |
| #define VOW_S_LL_CH2_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON28 */ |
| #define VOW_N_HH_CH2_SFT 0 |
| #define VOW_N_HH_CH2_MASK 0xff |
| #define VOW_N_HH_CH2_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON29 */ |
| #define VOW_N_HL_CH2_SFT 0 |
| #define VOW_N_HL_CH2_MASK 0xff |
| #define VOW_N_HL_CH2_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON30 */ |
| #define VOW_N_LH_CH2_SFT 0 |
| #define VOW_N_LH_CH2_MASK 0xff |
| #define VOW_N_LH_CH2_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON31 */ |
| #define VOW_N_LL_CH2_SFT 0 |
| #define VOW_N_LL_CH2_MASK 0xff |
| #define VOW_N_LL_CH2_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON32 */ |
| #define VOW_S_HH_CH3_SFT 0 |
| #define VOW_S_HH_CH3_MASK 0xff |
| #define VOW_S_HH_CH3_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON33 */ |
| #define VOW_S_HL_CH3_SFT 0 |
| #define VOW_S_HL_CH3_MASK 0xff |
| #define VOW_S_HL_CH3_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON34 */ |
| #define VOW_S_LH_CH3_SFT 0 |
| #define VOW_S_LH_CH3_MASK 0xff |
| #define VOW_S_LH_CH3_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON35 */ |
| #define VOW_S_LL_CH3_SFT 0 |
| #define VOW_S_LL_CH3_MASK 0xff |
| #define VOW_S_LL_CH3_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON36 */ |
| #define VOW_N_HH_CH3_SFT 0 |
| #define VOW_N_HH_CH3_MASK 0xff |
| #define VOW_N_HH_CH3_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON37 */ |
| #define VOW_N_HL_CH3_SFT 0 |
| #define VOW_N_HL_CH3_MASK 0xff |
| #define VOW_N_HL_CH3_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON38 */ |
| #define VOW_N_LH_CH3_SFT 0 |
| #define VOW_N_LH_CH3_MASK 0xff |
| #define VOW_N_LH_CH3_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON39 */ |
| #define VOW_N_LL_CH3_SFT 0 |
| #define VOW_N_LL_CH3_MASK 0xff |
| #define VOW_N_LL_CH3_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON40 */ |
| #define VOW_S_HH_CH4_SFT 0 |
| #define VOW_S_HH_CH4_MASK 0xff |
| #define VOW_S_HH_CH4_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON41 */ |
| #define VOW_S_HL_CH4_SFT 0 |
| #define VOW_S_HL_CH4_MASK 0xff |
| #define VOW_S_HL_CH4_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON42 */ |
| #define VOW_S_LH_CH4_SFT 0 |
| #define VOW_S_LH_CH4_MASK 0xff |
| #define VOW_S_LH_CH4_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON43 */ |
| #define VOW_S_LL_CH4_SFT 0 |
| #define VOW_S_LL_CH4_MASK 0xff |
| #define VOW_S_LL_CH4_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON44 */ |
| #define VOW_N_HH_CH4_SFT 0 |
| #define VOW_N_HH_CH4_MASK 0xff |
| #define VOW_N_HH_CH4_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON45 */ |
| #define VOW_N_HL_CH4_SFT 0 |
| #define VOW_N_HL_CH4_MASK 0xff |
| #define VOW_N_HL_CH4_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON46 */ |
| #define VOW_N_LH_CH4_SFT 0 |
| #define VOW_N_LH_CH4_MASK 0xff |
| #define VOW_N_LH_CH4_MASK_SFT (0xff << 0) |
| |
| /* AFE_VOW_VAD_MON47 */ |
| #define VOW_N_LL_CH4_SFT 0 |
| #define VOW_N_LL_CH4_MASK 0xff |
| #define VOW_N_LL_CH4_MASK_SFT (0xff << 0) |
| |
| /* AUDENC_ANA_ID */ |
| #define AUDENC_ANA_ID_SFT 0 |
| #define AUDENC_ANA_ID_MASK 0xff |
| #define AUDENC_ANA_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDENC_DIG_ID */ |
| #define AUDENC_DIG_ID_SFT 0 |
| #define AUDENC_DIG_ID_MASK 0xff |
| #define AUDENC_DIG_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDENC_ANA_REV */ |
| #define AUDENC_ANA_MINOR_REV_SFT 0 |
| #define AUDENC_ANA_MINOR_REV_MASK 0xf |
| #define AUDENC_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDENC_ANA_MAJOR_REV_SFT 4 |
| #define AUDENC_ANA_MAJOR_REV_MASK 0xf |
| #define AUDENC_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDENC_DIG_REV */ |
| #define AUDENC_DIG_MINOR_REV_SFT 0 |
| #define AUDENC_DIG_MINOR_REV_MASK 0xf |
| #define AUDENC_DIG_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDENC_DIG_MAJOR_REV_SFT 4 |
| #define AUDENC_DIG_MAJOR_REV_MASK 0xf |
| #define AUDENC_DIG_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDENC_DBI */ |
| #define AUDENC_CBS_SFT 0 |
| #define AUDENC_CBS_MASK 0x3 |
| #define AUDENC_CBS_MASK_SFT (0x3 << 0) |
| #define AUDENC_BIX_SFT 2 |
| #define AUDENC_BIX_MASK 0x3 |
| #define AUDENC_BIX_MASK_SFT (0x3 << 2) |
| |
| /* AUDENC_ESP */ |
| #define AUDENC_ESP_SFT 0 |
| #define AUDENC_ESP_MASK 0xff |
| #define AUDENC_ESP_MASK_SFT (0xff << 0) |
| |
| /* AUDENC_FPI */ |
| #define AUDENC_FPI_SFT 0 |
| #define AUDENC_FPI_MASK 0xff |
| #define AUDENC_FPI_MASK_SFT (0xff << 0) |
| |
| /* AUDENC_DXI */ |
| #define AUDENC_DXI_SFT 0 |
| #define AUDENC_DXI_MASK 0xff |
| #define AUDENC_DXI_MASK_SFT (0xff << 0) |
| |
| /* AUDENC_PMU_CON0 */ |
| #define RG_AUDPREAMPLON_SFT 0 |
| #define RG_AUDPREAMPLON_MASK 0x1 |
| #define RG_AUDPREAMPLON_MASK_SFT (0x1 << 0) |
| #define RG_AUDPREAMPLDCCEN_SFT 1 |
| #define RG_AUDPREAMPLDCCEN_MASK 0x1 |
| #define RG_AUDPREAMPLDCCEN_MASK_SFT (0x1 << 1) |
| #define RG_AUDPREAMPLDCPRECHARGE_SFT 2 |
| #define RG_AUDPREAMPLDCPRECHARGE_MASK 0x1 |
| #define RG_AUDPREAMPLDCPRECHARGE_MASK_SFT (0x1 << 2) |
| #define RG_AUDPREAMPLPGATEST_SFT 3 |
| #define RG_AUDPREAMPLPGATEST_MASK 0x1 |
| #define RG_AUDPREAMPLPGATEST_MASK_SFT (0x1 << 3) |
| #define RG_AUDPREAMPLVSCALE_SFT 4 |
| #define RG_AUDPREAMPLVSCALE_MASK 0x3 |
| #define RG_AUDPREAMPLVSCALE_MASK_SFT (0x3 << 4) |
| #define RG_AUDPREAMPLINPUTSEL_SFT 6 |
| #define RG_AUDPREAMPLINPUTSEL_MASK 0x3 |
| #define RG_AUDPREAMPLINPUTSEL_MASK_SFT (0x3 << 6) |
| |
| /* AUDENC_PMU_CON1 */ |
| #define RG_AUDPREAMPLGAIN_SFT 0 |
| #define RG_AUDPREAMPLGAIN_MASK 0xf |
| #define RG_AUDPREAMPLGAIN_MASK_SFT (0xf << 0) |
| #define RG_AUDADCLPWRUP_SFT 4 |
| #define RG_AUDADCLPWRUP_MASK 0x1 |
| #define RG_AUDADCLPWRUP_MASK_SFT (0x1 << 4) |
| #define RG_AUDADCLINPUTSEL_SFT 5 |
| #define RG_AUDADCLINPUTSEL_MASK 0x3 |
| #define RG_AUDADCLINPUTSEL_MASK_SFT (0x3 << 5) |
| |
| /* AUDENC_PMU_CON2 */ |
| #define RG_AUDPREAMPRON_SFT 0 |
| #define RG_AUDPREAMPRON_MASK 0x1 |
| #define RG_AUDPREAMPRON_MASK_SFT (0x1 << 0) |
| #define RG_AUDPREAMPRDCCEN_SFT 1 |
| #define RG_AUDPREAMPRDCCEN_MASK 0x1 |
| #define RG_AUDPREAMPRDCCEN_MASK_SFT (0x1 << 1) |
| #define RG_AUDPREAMPRDCPRECHARGE_SFT 2 |
| #define RG_AUDPREAMPRDCPRECHARGE_MASK 0x1 |
| #define RG_AUDPREAMPRDCPRECHARGE_MASK_SFT (0x1 << 2) |
| #define RG_AUDPREAMPRPGATEST_SFT 3 |
| #define RG_AUDPREAMPRPGATEST_MASK 0x1 |
| #define RG_AUDPREAMPRPGATEST_MASK_SFT (0x1 << 3) |
| #define RG_AUDPREAMPRVSCALE_SFT 4 |
| #define RG_AUDPREAMPRVSCALE_MASK 0x3 |
| #define RG_AUDPREAMPRVSCALE_MASK_SFT (0x3 << 4) |
| #define RG_AUDPREAMPRINPUTSEL_SFT 6 |
| #define RG_AUDPREAMPRINPUTSEL_MASK 0x3 |
| #define RG_AUDPREAMPRINPUTSEL_MASK_SFT (0x3 << 6) |
| |
| /* AUDENC_PMU_CON3 */ |
| #define RG_AUDPREAMPRGAIN_SFT 0 |
| #define RG_AUDPREAMPRGAIN_MASK 0xf |
| #define RG_AUDPREAMPRGAIN_MASK_SFT (0xf << 0) |
| #define RG_AUDADCRPWRUP_SFT 4 |
| #define RG_AUDADCRPWRUP_MASK 0x1 |
| #define RG_AUDADCRPWRUP_MASK_SFT (0x1 << 4) |
| #define RG_AUDADCRINPUTSEL_SFT 5 |
| #define RG_AUDADCRINPUTSEL_MASK 0x3 |
| #define RG_AUDADCRINPUTSEL_MASK_SFT (0x3 << 5) |
| |
| /* AUDENC_PMU_CON4 */ |
| #define RG_AUDPREAMP3ON_SFT 0 |
| #define RG_AUDPREAMP3ON_MASK 0x1 |
| #define RG_AUDPREAMP3ON_MASK_SFT (0x1 << 0) |
| #define RG_AUDPREAMP3DCCEN_SFT 1 |
| #define RG_AUDPREAMP3DCCEN_MASK 0x1 |
| #define RG_AUDPREAMP3DCCEN_MASK_SFT (0x1 << 1) |
| #define RG_AUDPREAMP3DCPRECHARGE_SFT 2 |
| #define RG_AUDPREAMP3DCPRECHARGE_MASK 0x1 |
| #define RG_AUDPREAMP3DCPRECHARGE_MASK_SFT (0x1 << 2) |
| #define RG_AUDPREAMP3PGATEST_SFT 3 |
| #define RG_AUDPREAMP3PGATEST_MASK 0x1 |
| #define RG_AUDPREAMP3PGATEST_MASK_SFT (0x1 << 3) |
| #define RG_AUDPREAMP3VSCALE_SFT 4 |
| #define RG_AUDPREAMP3VSCALE_MASK 0x3 |
| #define RG_AUDPREAMP3VSCALE_MASK_SFT (0x3 << 4) |
| #define RG_AUDPREAMP3INPUTSEL_SFT 6 |
| #define RG_AUDPREAMP3INPUTSEL_MASK 0x3 |
| #define RG_AUDPREAMP3INPUTSEL_MASK_SFT (0x3 << 6) |
| |
| /* AUDENC_PMU_CON5 */ |
| #define RG_AUDPREAMP3GAIN_SFT 0 |
| #define RG_AUDPREAMP3GAIN_MASK 0xf |
| #define RG_AUDPREAMP3GAIN_MASK_SFT (0xf << 0) |
| #define RG_AUDADC3PWRUP_SFT 4 |
| #define RG_AUDADC3PWRUP_MASK 0x1 |
| #define RG_AUDADC3PWRUP_MASK_SFT (0x1 << 4) |
| #define RG_AUDADC3INPUTSEL_SFT 5 |
| #define RG_AUDADC3INPUTSEL_MASK 0x3 |
| #define RG_AUDADC3INPUTSEL_MASK_SFT (0x3 << 5) |
| |
| /* AUDENC_PMU_CON6 */ |
| #define RG_AUDPREAMP4ON_SFT 0 |
| #define RG_AUDPREAMP4ON_MASK 0x1 |
| #define RG_AUDPREAMP4ON_MASK_SFT (0x1 << 0) |
| #define RG_AUDPREAMP4DCCEN_SFT 1 |
| #define RG_AUDPREAMP4DCCEN_MASK 0x1 |
| #define RG_AUDPREAMP4DCCEN_MASK_SFT (0x1 << 1) |
| #define RG_AUDPREAMP4DCPRECHARGE_SFT 2 |
| #define RG_AUDPREAMP4DCPRECHARGE_MASK 0x1 |
| #define RG_AUDPREAMP4DCPRECHARGE_MASK_SFT (0x1 << 2) |
| #define RG_AUDPREAMP4PGATEST_SFT 3 |
| #define RG_AUDPREAMP4PGATEST_MASK 0x1 |
| #define RG_AUDPREAMP4PGATEST_MASK_SFT (0x1 << 3) |
| #define RG_AUDPREAMP4VSCALE_SFT 4 |
| #define RG_AUDPREAMP4VSCALE_MASK 0x3 |
| #define RG_AUDPREAMP4VSCALE_MASK_SFT (0x3 << 4) |
| #define RG_AUDPREAMP4INPUTSEL_SFT 6 |
| #define RG_AUDPREAMP4INPUTSEL_MASK 0x3 |
| #define RG_AUDPREAMP4INPUTSEL_MASK_SFT (0x3 << 6) |
| |
| /* AUDENC_PMU_CON7 */ |
| #define RG_AUDPREAMP4GAIN_SFT 0 |
| #define RG_AUDPREAMP4GAIN_MASK 0xf |
| #define RG_AUDPREAMP4GAIN_MASK_SFT (0xf << 0) |
| #define RG_AUDADC4PWRUP_SFT 4 |
| #define RG_AUDADC4PWRUP_MASK 0x1 |
| #define RG_AUDADC4PWRUP_MASK_SFT (0x1 << 4) |
| #define RG_AUDADC4INPUTSEL_SFT 5 |
| #define RG_AUDADC4INPUTSEL_MASK 0x3 |
| #define RG_AUDADC4INPUTSEL_MASK_SFT (0x3 << 5) |
| |
| /* AUDENC_PMU_CON8 */ |
| #define RG_AUDULHALFBIAS_SFT 0 |
| #define RG_AUDULHALFBIAS_MASK 0x1 |
| #define RG_AUDULHALFBIAS_MASK_SFT (0x1 << 0) |
| #define RG_AUDGLBVOWLPWEN_SFT 1 |
| #define RG_AUDGLBVOWLPWEN_MASK 0x1 |
| #define RG_AUDGLBVOWLPWEN_MASK_SFT (0x1 << 1) |
| #define RG_AUDPREAMPLPEN_SFT 2 |
| #define RG_AUDPREAMPLPEN_MASK 0x1 |
| #define RG_AUDPREAMPLPEN_MASK_SFT (0x1 << 2) |
| #define RG_AUDADC1STSTAGELPEN_SFT 3 |
| #define RG_AUDADC1STSTAGELPEN_MASK 0x1 |
| #define RG_AUDADC1STSTAGELPEN_MASK_SFT (0x1 << 3) |
| #define RG_AUDADC2NDSTAGELPEN_SFT 4 |
| #define RG_AUDADC2NDSTAGELPEN_MASK 0x1 |
| #define RG_AUDADC2NDSTAGELPEN_MASK_SFT (0x1 << 4) |
| #define RG_AUDADCFLASHLPEN_SFT 5 |
| #define RG_AUDADCFLASHLPEN_MASK 0x1 |
| #define RG_AUDADCFLASHLPEN_MASK_SFT (0x1 << 5) |
| #define RG_AUDPREAMPIDDTEST_SFT 6 |
| #define RG_AUDPREAMPIDDTEST_MASK 0x3 |
| #define RG_AUDPREAMPIDDTEST_MASK_SFT (0x3 << 6) |
| |
| /* AUDENC_PMU_CON9 */ |
| #define RG_AUDADC1STSTAGEIDDTEST_SFT 0 |
| #define RG_AUDADC1STSTAGEIDDTEST_MASK 0x3 |
| #define RG_AUDADC1STSTAGEIDDTEST_MASK_SFT (0x3 << 0) |
| #define RG_AUDADC2NDSTAGEIDDTEST_SFT 2 |
| #define RG_AUDADC2NDSTAGEIDDTEST_MASK 0x3 |
| #define RG_AUDADC2NDSTAGEIDDTEST_MASK_SFT (0x3 << 2) |
| #define RG_AUDADCREFBUFIDDTEST_SFT 4 |
| #define RG_AUDADCREFBUFIDDTEST_MASK 0x3 |
| #define RG_AUDADCREFBUFIDDTEST_MASK_SFT (0x3 << 4) |
| #define RG_AUDADCFLASHIDDTEST_SFT 6 |
| #define RG_AUDADCFLASHIDDTEST_MASK 0x3 |
| #define RG_AUDADCFLASHIDDTEST_MASK_SFT (0x3 << 6) |
| |
| /* AUDENC_PMU_CON10 */ |
| #define RG_AUDPREAMPLNEGGAIN_SFT 0 |
| #define RG_AUDPREAMPLNEGGAIN_MASK 0x3 |
| #define RG_AUDPREAMPLNEGGAIN_MASK_SFT (0x3 << 0) |
| #define RG_AUDPREAMPRNEGGAIN_SFT 2 |
| #define RG_AUDPREAMPRNEGGAIN_MASK 0x3 |
| #define RG_AUDPREAMPRNEGGAIN_MASK_SFT (0x3 << 2) |
| #define RG_AUDPREAMP3NEGGAIN_SFT 4 |
| #define RG_AUDPREAMP3NEGGAIN_MASK 0x3 |
| #define RG_AUDPREAMP3NEGGAIN_MASK_SFT (0x3 << 4) |
| #define RG_AUDPREAMP4NEGGAIN_SFT 6 |
| #define RG_AUDPREAMP4NEGGAIN_MASK 0x3 |
| #define RG_AUDPREAMP4NEGGAIN_MASK_SFT (0x3 << 6) |
| |
| /* AUDENC_PMU_CON11 */ |
| #define RG_AUDPREAMPL_CARA_18_SFT 0 |
| #define RG_AUDPREAMPL_CARA_18_MASK 0x1 |
| #define RG_AUDPREAMPL_CARA_18_MASK_SFT (0x1 << 0) |
| #define RG_AUDPREAMPL_CARA_24_SFT 1 |
| #define RG_AUDPREAMPL_CARA_24_MASK 0x1 |
| #define RG_AUDPREAMPL_CARA_24_MASK_SFT (0x1 << 1) |
| #define RG_AUDPREAMPR_CARA_18_SFT 2 |
| #define RG_AUDPREAMPR_CARA_18_MASK 0x1 |
| #define RG_AUDPREAMPR_CARA_18_MASK_SFT (0x1 << 2) |
| #define RG_AUDPREAMPR_CARA_24_SFT 3 |
| #define RG_AUDPREAMPR_CARA_24_MASK 0x1 |
| #define RG_AUDPREAMPR_CARA_24_MASK_SFT (0x1 << 3) |
| #define RG_AUDPREAMP3_CARA_18_SFT 4 |
| #define RG_AUDPREAMP3_CARA_18_MASK 0x1 |
| #define RG_AUDPREAMP3_CARA_18_MASK_SFT (0x1 << 4) |
| #define RG_AUDPREAMP3_CARA_24_SFT 5 |
| #define RG_AUDPREAMP3_CARA_24_MASK 0x1 |
| #define RG_AUDPREAMP3_CARA_24_MASK_SFT (0x1 << 5) |
| #define RG_AUDPREAMP4_CARA_18_SFT 6 |
| #define RG_AUDPREAMP4_CARA_18_MASK 0x1 |
| #define RG_AUDPREAMP4_CARA_18_MASK_SFT (0x1 << 6) |
| #define RG_AUDPREAMP4_CARA_24_SFT 7 |
| #define RG_AUDPREAMP4_CARA_24_MASK 0x1 |
| #define RG_AUDPREAMP4_CARA_24_MASK_SFT (0x1 << 7) |
| |
| /* AUDENC_PMU_CON12 */ |
| #define RG_AUDPREAMPLMODE_SFT 0 |
| #define RG_AUDPREAMPLMODE_MASK 0x7 |
| #define RG_AUDPREAMPLMODE_MASK_SFT (0x7 << 0) |
| #define RG_AUDPREAMPRMODE_SFT 4 |
| #define RG_AUDPREAMPRMODE_MASK 0x7 |
| #define RG_AUDPREAMPRMODE_MASK_SFT (0x7 << 4) |
| |
| /* AUDENC_PMU_CON13 */ |
| #define RG_AUDPREAMP3MODE_SFT 0 |
| #define RG_AUDPREAMP3MODE_MASK 0x7 |
| #define RG_AUDPREAMP3MODE_MASK_SFT (0x7 << 0) |
| #define RG_AUDPREAMP4MODE_SFT 4 |
| #define RG_AUDPREAMP4MODE_MASK 0x7 |
| #define RG_AUDPREAMP4MODE_MASK_SFT (0x7 << 4) |
| |
| /* AUDENC_PMU_CON14 */ |
| #define RG_AUDADCLMODE_SFT 0 |
| #define RG_AUDADCLMODE_MASK 0x7 |
| #define RG_AUDADCLMODE_MASK_SFT (0x7 << 0) |
| #define RG_AUDADCL_VOW_SFT 3 |
| #define RG_AUDADCL_VOW_MASK 0x1 |
| #define RG_AUDADCL_VOW_MASK_SFT (0x1 << 3) |
| #define RG_AUDADCRMODE_SFT 4 |
| #define RG_AUDADCRMODE_MASK 0x7 |
| #define RG_AUDADCRMODE_MASK_SFT (0x7 << 4) |
| #define RG_AUDADCR_VOW_SFT 7 |
| #define RG_AUDADCR_VOW_MASK 0x1 |
| #define RG_AUDADCR_VOW_MASK_SFT (0x1 << 7) |
| |
| /* AUDENC_PMU_CON15 */ |
| #define RG_AUDADC3MODE_SFT 0 |
| #define RG_AUDADC3MODE_MASK 0x7 |
| #define RG_AUDADC3MODE_MASK_SFT (0x7 << 0) |
| #define RG_AUDADC3_VOW_SFT 3 |
| #define RG_AUDADC3_VOW_MASK 0x1 |
| #define RG_AUDADC3_VOW_MASK_SFT (0x1 << 3) |
| #define RG_AUDADC4MODE_SFT 4 |
| #define RG_AUDADC4MODE_MASK 0x7 |
| #define RG_AUDADC4MODE_MASK_SFT (0x7 << 4) |
| #define RG_AUDADC4_VOW_SFT 7 |
| #define RG_AUDADC4_VOW_MASK 0x1 |
| #define RG_AUDADC4_VOW_MASK_SFT (0x1 << 7) |
| |
| /* AUDENC_PMU_CON16 */ |
| #define RG_AUDRULHALFBIAS_SFT 0 |
| #define RG_AUDRULHALFBIAS_MASK 0x1 |
| #define RG_AUDRULHALFBIAS_MASK_SFT (0x1 << 0) |
| #define RG_AUDGLBRVOWLPWEN_SFT 1 |
| #define RG_AUDGLBRVOWLPWEN_MASK 0x1 |
| #define RG_AUDGLBRVOWLPWEN_MASK_SFT (0x1 << 1) |
| #define RG_AUDRPREAMPLPEN_SFT 2 |
| #define RG_AUDRPREAMPLPEN_MASK 0x1 |
| #define RG_AUDRPREAMPLPEN_MASK_SFT (0x1 << 2) |
| #define RG_AUDRADC1STSTAGELPEN_SFT 3 |
| #define RG_AUDRADC1STSTAGELPEN_MASK 0x1 |
| #define RG_AUDRADC1STSTAGELPEN_MASK_SFT (0x1 << 3) |
| #define RG_AUDRADC2NDSTAGELPEN_SFT 4 |
| #define RG_AUDRADC2NDSTAGELPEN_MASK 0x1 |
| #define RG_AUDRADC2NDSTAGELPEN_MASK_SFT (0x1 << 4) |
| #define RG_AUDRADCFLASHLPEN_SFT 5 |
| #define RG_AUDRADCFLASHLPEN_MASK 0x1 |
| #define RG_AUDRADCFLASHLPEN_MASK_SFT (0x1 << 5) |
| #define RG_AUDRPREAMPIDDTEST_SFT 6 |
| #define RG_AUDRPREAMPIDDTEST_MASK 0x3 |
| #define RG_AUDRPREAMPIDDTEST_MASK_SFT (0x3 << 6) |
| |
| /* AUDENC_PMU_CON17 */ |
| #define RG_AUDRADC1STSTAGEIDDTEST_SFT 0 |
| #define RG_AUDRADC1STSTAGEIDDTEST_MASK 0x3 |
| #define RG_AUDRADC1STSTAGEIDDTEST_MASK_SFT (0x3 << 0) |
| #define RG_AUDRADC2NDSTAGEIDDTEST_SFT 2 |
| #define RG_AUDRADC2NDSTAGEIDDTEST_MASK 0x3 |
| #define RG_AUDRADC2NDSTAGEIDDTEST_MASK_SFT (0x3 << 2) |
| #define RG_AUDRADCREFBUFIDDTEST_SFT 4 |
| #define RG_AUDRADCREFBUFIDDTEST_MASK 0x3 |
| #define RG_AUDRADCREFBUFIDDTEST_MASK_SFT (0x3 << 4) |
| #define RG_AUDRADCFLASHIDDTEST_SFT 6 |
| #define RG_AUDRADCFLASHIDDTEST_MASK 0x3 |
| #define RG_AUDRADCFLASHIDDTEST_MASK_SFT (0x3 << 6) |
| |
| /* AUDENC_PMU_CON18 */ |
| #define RG_AUDADCLCLKRSTB_SFT 0 |
| #define RG_AUDADCLCLKRSTB_MASK 0x1 |
| #define RG_AUDADCLCLKRSTB_MASK_SFT (0x1 << 0) |
| #define RG_AUDADCLCLKSEL_SFT 1 |
| #define RG_AUDADCLCLKSEL_MASK 0x3 |
| #define RG_AUDADCLCLKSEL_MASK_SFT (0x3 << 1) |
| #define RG_AUDADCLCLKSOURCE_SFT 3 |
| #define RG_AUDADCLCLKSOURCE_MASK 0x3 |
| #define RG_AUDADCLCLKSOURCE_MASK_SFT (0x3 << 3) |
| #define RG_AUDADCLCLKGENMODE_SFT 5 |
| #define RG_AUDADCLCLKGENMODE_MASK 0x3 |
| #define RG_AUDADCLCLKGENMODE_MASK_SFT (0x3 << 5) |
| |
| /* AUDENC_PMU_CON19 */ |
| #define RG_AUDADCRCLKRSTB_SFT 0 |
| #define RG_AUDADCRCLKRSTB_MASK 0x1 |
| #define RG_AUDADCRCLKRSTB_MASK_SFT (0x1 << 0) |
| #define RG_AUDADCRCLKSEL_SFT 1 |
| #define RG_AUDADCRCLKSEL_MASK 0x3 |
| #define RG_AUDADCRCLKSEL_MASK_SFT (0x3 << 1) |
| #define RG_AUDADCRCLKSOURCE_SFT 3 |
| #define RG_AUDADCRCLKSOURCE_MASK 0x3 |
| #define RG_AUDADCRCLKSOURCE_MASK_SFT (0x3 << 3) |
| #define RG_AUDADCRCLKGENMODE_SFT 5 |
| #define RG_AUDADCRCLKGENMODE_MASK 0x3 |
| #define RG_AUDADCRCLKGENMODE_MASK_SFT (0x3 << 5) |
| |
| /* AUDENC_PMU_CON20 */ |
| #define RG_AUDADC3CLKRSTB_SFT 0 |
| #define RG_AUDADC3CLKRSTB_MASK 0x1 |
| #define RG_AUDADC3CLKRSTB_MASK_SFT (0x1 << 0) |
| #define RG_AUDADC3CLKSEL_SFT 1 |
| #define RG_AUDADC3CLKSEL_MASK 0x3 |
| #define RG_AUDADC3CLKSEL_MASK_SFT (0x3 << 1) |
| #define RG_AUDADC3CLKSOURCE_SFT 3 |
| #define RG_AUDADC3CLKSOURCE_MASK 0x3 |
| #define RG_AUDADC3CLKSOURCE_MASK_SFT (0x3 << 3) |
| #define RG_AUDADC3CLKGENMODE_SFT 5 |
| #define RG_AUDADC3CLKGENMODE_MASK 0x3 |
| #define RG_AUDADC3CLKGENMODE_MASK_SFT (0x3 << 5) |
| |
| /* AUDENC_PMU_CON21 */ |
| #define RG_AUDADC4CLKRSTB_SFT 0 |
| #define RG_AUDADC4CLKRSTB_MASK 0x1 |
| #define RG_AUDADC4CLKRSTB_MASK_SFT (0x1 << 0) |
| #define RG_AUDADC4CLKSEL_SFT 1 |
| #define RG_AUDADC4CLKSEL_MASK 0x3 |
| #define RG_AUDADC4CLKSEL_MASK_SFT (0x3 << 1) |
| #define RG_AUDADC4CLKSOURCE_SFT 3 |
| #define RG_AUDADC4CLKSOURCE_MASK 0x3 |
| #define RG_AUDADC4CLKSOURCE_MASK_SFT (0x3 << 3) |
| #define RG_AUDADC4CLKGENMODE_SFT 5 |
| #define RG_AUDADC4CLKGENMODE_MASK 0x3 |
| #define RG_AUDADC4CLKGENMODE_MASK_SFT (0x3 << 5) |
| |
| /* AUDENC_PMU_CON22 */ |
| #define RG_AUDPREAMPL_ACCFS_SFT 0 |
| #define RG_AUDPREAMPL_ACCFS_MASK 0x1 |
| #define RG_AUDPREAMPL_ACCFS_MASK_SFT (0x1 << 0) |
| #define RG_AUDPREAMPR_ACCFS_SFT 1 |
| #define RG_AUDPREAMPR_ACCFS_MASK 0x1 |
| #define RG_AUDPREAMPR_ACCFS_MASK_SFT (0x1 << 1) |
| #define RG_AUDPREAMP3_ACCFS_SFT 2 |
| #define RG_AUDPREAMP3_ACCFS_MASK 0x1 |
| #define RG_AUDPREAMP3_ACCFS_MASK_SFT (0x1 << 2) |
| #define RG_AUDPREAMP4_ACCFS_SFT 3 |
| #define RG_AUDPREAMP4_ACCFS_MASK 0x1 |
| #define RG_AUDPREAMP4_ACCFS_MASK_SFT (0x1 << 3) |
| #define RG_AUDSPAREPGA1_SFT 4 |
| #define RG_AUDSPAREPGA1_MASK 0xf |
| #define RG_AUDSPAREPGA1_MASK_SFT (0xf << 4) |
| |
| /* AUDENC_PMU_CON23 */ |
| #define RG_AUDSPAREPGA2_SFT 0 |
| #define RG_AUDSPAREPGA2_MASK 0xff |
| #define RG_AUDSPAREPGA2_MASK_SFT (0xff << 0) |
| |
| /* AUDENC_PMU_CON24 */ |
| #define RG_AUDADC1STSTAGESDENB_SFT 0 |
| #define RG_AUDADC1STSTAGESDENB_MASK 0x1 |
| #define RG_AUDADC1STSTAGESDENB_MASK_SFT (0x1 << 0) |
| #define RG_AUDADC2NDSTAGERESET_SFT 1 |
| #define RG_AUDADC2NDSTAGERESET_MASK 0x1 |
| #define RG_AUDADC2NDSTAGERESET_MASK_SFT (0x1 << 1) |
| #define RG_AUDADC3RDSTAGERESET_SFT 2 |
| #define RG_AUDADC3RDSTAGERESET_MASK 0x1 |
| #define RG_AUDADC3RDSTAGERESET_MASK_SFT (0x1 << 2) |
| #define RG_AUDADCFSRESET_SFT 3 |
| #define RG_AUDADCFSRESET_MASK 0x1 |
| #define RG_AUDADCFSRESET_MASK_SFT (0x1 << 3) |
| #define RG_AUDADCWIDECM_SFT 4 |
| #define RG_AUDADCWIDECM_MASK 0x1 |
| #define RG_AUDADCWIDECM_MASK_SFT (0x1 << 4) |
| #define RG_AUDADCNOPATEST_SFT 5 |
| #define RG_AUDADCNOPATEST_MASK 0x1 |
| #define RG_AUDADCNOPATEST_MASK_SFT (0x1 << 5) |
| #define RG_AUDADCBYPASS_SFT 6 |
| #define RG_AUDADCBYPASS_MASK 0x1 |
| #define RG_AUDADCBYPASS_MASK_SFT (0x1 << 6) |
| #define RG_AUDADCFFBYPASS_SFT 7 |
| #define RG_AUDADCFFBYPASS_MASK 0x1 |
| #define RG_AUDADCFFBYPASS_MASK_SFT (0x1 << 7) |
| |
| /* AUDENC_PMU_CON25 */ |
| #define RG_AUDADCDACFBCURRENT_SFT 0 |
| #define RG_AUDADCDACFBCURRENT_MASK 0x1 |
| #define RG_AUDADCDACFBCURRENT_MASK_SFT (0x1 << 0) |
| #define RG_AUDADCDACIDDTEST_SFT 1 |
| #define RG_AUDADCDACIDDTEST_MASK 0x3 |
| #define RG_AUDADCDACIDDTEST_MASK_SFT (0x3 << 1) |
| #define RG_AUDADCDACNRZ_SFT 3 |
| #define RG_AUDADCDACNRZ_MASK 0x1 |
| #define RG_AUDADCDACNRZ_MASK_SFT (0x1 << 3) |
| #define RG_AUDADCNODEM_SFT 4 |
| #define RG_AUDADCNODEM_MASK 0x1 |
| #define RG_AUDADCNODEM_MASK_SFT (0x1 << 4) |
| #define RG_AUDADCDACTEST_SFT 5 |
| #define RG_AUDADCDACTEST_MASK 0x1 |
| #define RG_AUDADCDACTEST_MASK_SFT (0x1 << 5) |
| #define RG_AUDADCDAC0P25FS_SFT 6 |
| #define RG_AUDADCDAC0P25FS_MASK 0x1 |
| #define RG_AUDADCDAC0P25FS_MASK_SFT (0x1 << 6) |
| #define RG_AUDADCRDAC0P25FS_SFT 7 |
| #define RG_AUDADCRDAC0P25FS_MASK 0x1 |
| #define RG_AUDADCRDAC0P25FS_MASK_SFT (0x1 << 7) |
| |
| /* AUDENC_PMU_CON26 */ |
| #define RG_AUDADCTESTDATA1_SFT 0 |
| #define RG_AUDADCTESTDATA1_MASK 0xff |
| #define RG_AUDADCTESTDATA1_MASK_SFT (0xff << 0) |
| |
| /* AUDENC_PMU_CON27 */ |
| #define RG_AUDADCTESTDATA2_SFT 0 |
| #define RG_AUDADCTESTDATA2_MASK 0xff |
| #define RG_AUDADCTESTDATA2_MASK_SFT (0xff << 0) |
| |
| /* AUDENC_PMU_CON28 */ |
| #define RG_AUDRCTUNEL_SFT 0 |
| #define RG_AUDRCTUNEL_MASK 0x1f |
| #define RG_AUDRCTUNEL_MASK_SFT (0x1f << 0) |
| #define RG_AUDRCTUNELSEL_SFT 5 |
| #define RG_AUDRCTUNELSEL_MASK 0x1 |
| #define RG_AUDRCTUNELSEL_MASK_SFT (0x1 << 5) |
| |
| /* AUDENC_PMU_CON29 */ |
| #define RG_AUDRCTUNER_SFT 0 |
| #define RG_AUDRCTUNER_MASK 0x1f |
| #define RG_AUDRCTUNER_MASK_SFT (0x1f << 0) |
| #define RG_AUDRCTUNERSEL_SFT 5 |
| #define RG_AUDRCTUNERSEL_MASK 0x1 |
| #define RG_AUDRCTUNERSEL_MASK_SFT (0x1 << 5) |
| |
| /* AUDENC_PMU_CON30 */ |
| #define RG_AUDRCTUNE3_SFT 0 |
| #define RG_AUDRCTUNE3_MASK 0x1f |
| #define RG_AUDRCTUNE3_MASK_SFT (0x1f << 0) |
| #define RG_AUDRCTUNE3SEL_SFT 5 |
| #define RG_AUDRCTUNE3SEL_MASK 0x1 |
| #define RG_AUDRCTUNE3SEL_MASK_SFT (0x1 << 5) |
| |
| /* AUDENC_PMU_CON31 */ |
| #define RG_AUDRCTUNE4_SFT 0 |
| #define RG_AUDRCTUNE4_MASK 0x1f |
| #define RG_AUDRCTUNE4_MASK_SFT (0x1f << 0) |
| #define RG_AUDRCTUNE4SEL_SFT 5 |
| #define RG_AUDRCTUNE4SEL_MASK 0x1 |
| #define RG_AUDRCTUNE4SEL_MASK_SFT (0x1 << 5) |
| |
| /* AUDENC_PMU_CON32 */ |
| #define RGS_AUDRCTUNELREAD_SFT 0 |
| #define RGS_AUDRCTUNELREAD_MASK 0x1f |
| #define RGS_AUDRCTUNELREAD_MASK_SFT (0x1f << 0) |
| |
| /* AUDENC_PMU_CON33 */ |
| #define RGS_AUDRCTUNERREAD_SFT 0 |
| #define RGS_AUDRCTUNERREAD_MASK 0x1f |
| #define RGS_AUDRCTUNERREAD_MASK_SFT (0x1f << 0) |
| |
| /* AUDENC_PMU_CON34 */ |
| #define RGS_AUDRCTUNE3READ_SFT 0 |
| #define RGS_AUDRCTUNE3READ_MASK 0x1f |
| #define RGS_AUDRCTUNE3READ_MASK_SFT (0x1f << 0) |
| |
| /* AUDENC_PMU_CON35 */ |
| #define RGS_AUDRCTUNE4READ_SFT 0 |
| #define RGS_AUDRCTUNE4READ_MASK 0x1f |
| #define RGS_AUDRCTUNE4READ_MASK_SFT (0x1f << 0) |
| |
| /* AUDENC_PMU_CON36 */ |
| #define RG_AUDPGA_DECAP_SFT 0 |
| #define RG_AUDPGA_DECAP_MASK 0x1 |
| #define RG_AUDPGA_DECAP_MASK_SFT (0x1 << 0) |
| #define RG_AUDPGA_CAPRA_SFT 1 |
| #define RG_AUDPGA_CAPRA_MASK 0x1 |
| #define RG_AUDPGA_CAPRA_MASK_SFT (0x1 << 1) |
| #define RG_AUDPGA_ACCCMP_SFT 2 |
| #define RG_AUDPGA_ACCCMP_MASK 0x1 |
| #define RG_AUDPGA_ACCCMP_MASK_SFT (0x1 << 2) |
| #define RG_AUDENC_SPARE2_SFT 3 |
| #define RG_AUDENC_SPARE2_MASK 0x1f |
| #define RG_AUDENC_SPARE2_MASK_SFT (0x1f << 3) |
| |
| /* AUDENC_PMU_CON37 */ |
| #define RG_AUDENC_SPARE3_SFT 0 |
| #define RG_AUDENC_SPARE3_MASK 0xff |
| #define RG_AUDENC_SPARE3_MASK_SFT (0xff << 0) |
| |
| /* AUDENC_PMU_CON38 */ |
| #define RG_AUDPREAMPLACCGAIN_SFT 0 |
| #define RG_AUDPREAMPLACCGAIN_MASK 0x7 |
| #define RG_AUDPREAMPLACCGAIN_MASK_SFT (0x7 << 0) |
| #define RG_AUDPREAMPRACCGAIN_SFT 4 |
| #define RG_AUDPREAMPRACCGAIN_MASK 0x7 |
| #define RG_AUDPREAMPRACCGAIN_MASK_SFT (0x7 << 4) |
| |
| /* AUDENC_PMU_CON39 */ |
| #define RG_AUDPREAMP3ACCGAIN_SFT 0 |
| #define RG_AUDPREAMP3ACCGAIN_MASK 0x7 |
| #define RG_AUDPREAMP3ACCGAIN_MASK_SFT (0x7 << 0) |
| #define RG_AUDPREAMP4ACCGAIN_SFT 4 |
| #define RG_AUDPREAMP4ACCGAIN_MASK 0x7 |
| #define RG_AUDPREAMP4ACCGAIN_MASK_SFT (0x7 << 4) |
| |
| /* AUDENC_PMU_CON40 */ |
| #define RG_AUDLADC1STSTAGEVOW_SFT 0 |
| #define RG_AUDLADC1STSTAGEVOW_MASK 0x1 |
| #define RG_AUDLADC1STSTAGEVOW_MASK_SFT (0x1 << 0) |
| #define RG_AUDRADC1STSTAGEVOW_SFT 1 |
| #define RG_AUDRADC1STSTAGEVOW_MASK 0x1 |
| #define RG_AUDRADC1STSTAGEVOW_MASK_SFT (0x1 << 1) |
| #define RG_AUD3ADC1STSTAGEVOW_SFT 2 |
| #define RG_AUD3ADC1STSTAGEVOW_MASK 0x1 |
| #define RG_AUD3ADC1STSTAGEVOW_MASK_SFT (0x1 << 2) |
| #define RG_AUD4ADC1STSTAGEVOW_SFT 3 |
| #define RG_AUD4ADC1STSTAGEVOW_MASK 0x1 |
| #define RG_AUD4ADC1STSTAGEVOW_MASK_SFT (0x1 << 3) |
| #define RG_AUDRADC1STSTAGELPEN_0_SFT 4 |
| #define RG_AUDRADC1STSTAGELPEN_0_MASK 0x1 |
| #define RG_AUDRADC1STSTAGELPEN_0_MASK_SFT (0x1 << 4) |
| #define RG_AUD3ADC1STSTAGELPEN_SFT 5 |
| #define RG_AUD3ADC1STSTAGELPEN_MASK 0x3 |
| #define RG_AUD3ADC1STSTAGELPEN_MASK_SFT (0x3 << 5) |
| #define RG_AUD3ADC2NDSTAGELPEN_SFT 7 |
| #define RG_AUD3ADC2NDSTAGELPEN_MASK 0x1 |
| #define RG_AUD3ADC2NDSTAGELPEN_MASK_SFT (0x1 << 7) |
| |
| /* AUDENC_PMU_CON41 */ |
| #define RG_AUD4ADC1STSTAGELPEN_SFT 0 |
| #define RG_AUD4ADC1STSTAGELPEN_MASK 0x3 |
| #define RG_AUD4ADC1STSTAGELPEN_MASK_SFT (0x3 << 0) |
| #define RG_AUD4ADC2NDSTAGELPEN_SFT 2 |
| #define RG_AUD4ADC2NDSTAGELPEN_MASK 0x1 |
| #define RG_AUD4ADC2NDSTAGELPEN_MASK_SFT (0x1 << 2) |
| #define RG_AUDADCRWIDECM_SFT 3 |
| #define RG_AUDADCRWIDECM_MASK 0x1 |
| #define RG_AUDADCRWIDECM_MASK_SFT (0x1 << 3) |
| #define RG_AUDADC3WIDECM_SFT 4 |
| #define RG_AUDADC3WIDECM_MASK 0x1 |
| #define RG_AUDADC3WIDECM_MASK_SFT (0x1 << 4) |
| #define RG_AUDADC4WIDECM_SFT 5 |
| #define RG_AUDADC4WIDECM_MASK 0x1 |
| #define RG_AUDADC4WIDECM_MASK_SFT (0x1 << 5) |
| #define RG_AUDRADCDACIDDTEST_SFT 6 |
| #define RG_AUDRADCDACIDDTEST_MASK 0x3 |
| #define RG_AUDRADCDACIDDTEST_MASK_SFT (0x3 << 6) |
| |
| /* AUDENC_PMU_CON42 */ |
| #define RG_AUD3ADC1STSTAGEIDDTEST_SFT 0 |
| #define RG_AUD3ADC1STSTAGEIDDTEST_MASK 0x3 |
| #define RG_AUD3ADC1STSTAGEIDDTEST_MASK_SFT (0x3 << 0) |
| #define RG_AUD3ADC2NDSTAGEIDDTEST_SFT 2 |
| #define RG_AUD3ADC2NDSTAGEIDDTEST_MASK 0x3 |
| #define RG_AUD3ADC2NDSTAGEIDDTEST_MASK_SFT (0x3 << 2) |
| #define RG_AUD3ADCDACIDDTEST_SFT 4 |
| #define RG_AUD3ADCDACIDDTEST_MASK 0x3 |
| #define RG_AUD3ADCDACIDDTEST_MASK_SFT (0x3 << 4) |
| #define RG_AUD3ADCREFBUFIDDTEST_SFT 6 |
| #define RG_AUD3ADCREFBUFIDDTEST_MASK 0x3 |
| #define RG_AUD3ADCREFBUFIDDTEST_MASK_SFT (0x3 << 6) |
| |
| /* AUDENC_PMU_CON43 */ |
| #define RG_AUD4ADC1STSTAGEIDDTEST_SFT 0 |
| #define RG_AUD4ADC1STSTAGEIDDTEST_MASK 0x3 |
| #define RG_AUD4ADC1STSTAGEIDDTEST_MASK_SFT (0x3 << 0) |
| #define RG_AUD4ADC2NDSTAGEIDDTEST_SFT 2 |
| #define RG_AUD4ADC2NDSTAGEIDDTEST_MASK 0x3 |
| #define RG_AUD4ADC2NDSTAGEIDDTEST_MASK_SFT (0x3 << 2) |
| #define RG_AUD4ADCDACIDDTEST_SFT 4 |
| #define RG_AUD4ADCDACIDDTEST_MASK 0x3 |
| #define RG_AUD4ADCDACIDDTEST_MASK_SFT (0x3 << 4) |
| #define RG_AUD4ADCREFBUFIDDTEST_SFT 6 |
| #define RG_AUD4ADCREFBUFIDDTEST_MASK 0x3 |
| #define RG_AUD4ADCREFBUFIDDTEST_MASK_SFT (0x3 << 6) |
| |
| /* AUDENC_PMU_CON44 */ |
| #define RG_AUD3ULHALFBIAS_SFT 0 |
| #define RG_AUD3ULHALFBIAS_MASK 0x1 |
| #define RG_AUD3ULHALFBIAS_MASK_SFT (0x1 << 0) |
| #define RG_AUD4ULHALFBIAS_SFT 1 |
| #define RG_AUD4ULHALFBIAS_MASK 0x1 |
| #define RG_AUD4ULHALFBIAS_MASK_SFT (0x1 << 1) |
| #define RG_AUDLADCHALFCLK_SFT 2 |
| #define RG_AUDLADCHALFCLK_MASK 0x1 |
| #define RG_AUDLADCHALFCLK_MASK_SFT (0x1 << 2) |
| #define RG_AUDRADCHALFCLK_SFT 3 |
| #define RG_AUDRADCHALFCLK_MASK 0x1 |
| #define RG_AUDRADCHALFCLK_MASK_SFT (0x1 << 3) |
| #define RG_AUD3ADCHALFCLK_SFT 4 |
| #define RG_AUD3ADCHALFCLK_MASK 0x1 |
| #define RG_AUD3ADCHALFCLK_MASK_SFT (0x1 << 4) |
| #define RG_AUD4ADCHALFCLK_SFT 5 |
| #define RG_AUD4ADCHALFCLK_MASK 0x1 |
| #define RG_AUD4ADCHALFCLK_MASK_SFT (0x1 << 5) |
| #define RG_AUDLADCDACMODE_SEL_SFT 6 |
| #define RG_AUDLADCDACMODE_SEL_MASK 0x1 |
| #define RG_AUDLADCDACMODE_SEL_MASK_SFT (0x1 << 6) |
| #define RG_AUDRADCDACMODE_SEL_SFT 7 |
| #define RG_AUDRADCDACMODE_SEL_MASK 0x1 |
| #define RG_AUDRADCDACMODE_SEL_MASK_SFT (0x1 << 7) |
| |
| /* AUDENC_PMU_CON45 */ |
| #define RG_AUD3ADCDACMODE_SEL_SFT 0 |
| #define RG_AUD3ADCDACMODE_SEL_MASK 0x1 |
| #define RG_AUD3ADCDACMODE_SEL_MASK_SFT (0x1 << 0) |
| #define RG_AUD4ADCDACMODE_SEL_SFT 1 |
| #define RG_AUD4ADCDACMODE_SEL_MASK 0x1 |
| #define RG_AUD4ADCDACMODE_SEL_MASK_SFT (0x1 << 1) |
| #define RG_AUDADCRESET_SEL_SFT 2 |
| #define RG_AUDADCRESET_SEL_MASK 0x1 |
| #define RG_AUDADCRESET_SEL_MASK_SFT (0x1 << 2) |
| #define RG_AUDADCLRINOHM_SFT 3 |
| #define RG_AUDADCLRINOHM_MASK 0x1f |
| #define RG_AUDADCLRINOHM_MASK_SFT (0x1f << 3) |
| |
| /* AUDENC_PMU_CON46 */ |
| #define RG_AUDADCRRINOHM_SFT 0 |
| #define RG_AUDADCRRINOHM_MASK 0x1f |
| #define RG_AUDADCRRINOHM_MASK_SFT (0x1f << 0) |
| |
| /* AUDENC_PMU_CON47 */ |
| #define RG_AUDADC3RINOHM_SFT 0 |
| #define RG_AUDADC3RINOHM_MASK 0x1f |
| #define RG_AUDADC3RINOHM_MASK_SFT (0x1f << 0) |
| |
| /* AUDENC_PMU_CON48 */ |
| #define RG_AUDADC4RINOHM_SFT 0 |
| #define RG_AUDADC4RINOHM_MASK 0x1f |
| #define RG_AUDADC4RINOHM_MASK_SFT (0x1f << 0) |
| |
| /* AUDENC_PMU_CON49 */ |
| #define RG_AUDADCHIGHDR_EN_SFT 0 |
| #define RG_AUDADCHIGHDR_EN_MASK 0x1 |
| #define RG_AUDADCHIGHDR_EN_MASK_SFT (0x1 << 0) |
| #define RG_AUDADCHIGHDRSW_SEL_SFT 1 |
| #define RG_AUDADCHIGHDRSW_SEL_MASK 0x1 |
| #define RG_AUDADCHIGHDRSW_SEL_MASK_SFT (0x1 << 1) |
| #define RG_AUDADCHIGHDRSW_EN_SFT 2 |
| #define RG_AUDADCHIGHDRSW_EN_MASK 0x1 |
| #define RG_AUDADCHIGHDRSW_EN_MASK_SFT (0x1 << 2) |
| #define RG_ADCHIGHDR_DEBNCSEL_SFT 3 |
| #define RG_ADCHIGHDR_DEBNCSEL_MASK 0x3 |
| #define RG_ADCHIGHDR_DEBNCSEL_MASK_SFT (0x3 << 3) |
| #define RG_AUDADCETMON_SEL_SFT 5 |
| #define RG_AUDADCETMON_SEL_MASK 0x1 |
| #define RG_AUDADCETMON_SEL_MASK_SFT (0x1 << 5) |
| #define RG_AUDRCTUNEBYP_SFT 6 |
| #define RG_AUDRCTUNEBYP_MASK 0x1 |
| #define RG_AUDRCTUNEBYP_MASK_SFT (0x1 << 6) |
| |
| /* AUDENC_PMU_CON50 */ |
| #define RG_AUDADCLFLASHVREFRES_LPM_SFT 0 |
| #define RG_AUDADCLFLASHVREFRES_LPM_MASK 0x1 |
| #define RG_AUDADCLFLASHVREFRES_LPM_MASK_SFT (0x1 << 0) |
| #define RG_AUDADCLFLASHVREFRES_LPM2_SFT 1 |
| #define RG_AUDADCLFLASHVREFRES_LPM2_MASK 0x1 |
| #define RG_AUDADCLFLASHVREFRES_LPM2_MASK_SFT (0x1 << 1) |
| #define RG_AUDADCRFLASHVREFRES_LPM_SFT 2 |
| #define RG_AUDADCRFLASHVREFRES_LPM_MASK 0x1 |
| #define RG_AUDADCRFLASHVREFRES_LPM_MASK_SFT (0x1 << 2) |
| #define RG_AUDADCRFLASHVREFRES_LPM2_SFT 3 |
| #define RG_AUDADCRFLASHVREFRES_LPM2_MASK 0x1 |
| #define RG_AUDADCRFLASHVREFRES_LPM2_MASK_SFT (0x1 << 3) |
| #define RG_AUDADC3FLASHVREFRES_LPM_SFT 4 |
| #define RG_AUDADC3FLASHVREFRES_LPM_MASK 0x1 |
| #define RG_AUDADC3FLASHVREFRES_LPM_MASK_SFT (0x1 << 4) |
| #define RG_AUDADC3FLASHVREFRES_LPM2_SFT 5 |
| #define RG_AUDADC3FLASHVREFRES_LPM2_MASK 0x1 |
| #define RG_AUDADC3FLASHVREFRES_LPM2_MASK_SFT (0x1 << 5) |
| #define RG_AUDADC4FLASHVREFRES_LPM_SFT 6 |
| #define RG_AUDADC4FLASHVREFRES_LPM_MASK 0x1 |
| #define RG_AUDADC4FLASHVREFRES_LPM_MASK_SFT (0x1 << 6) |
| #define RG_AUDADC4FLASHVREFRES_LPM2_SFT 7 |
| #define RG_AUDADC4FLASHVREFRES_LPM2_MASK 0x1 |
| #define RG_AUDADC4FLASHVREFRES_LPM2_MASK_SFT (0x1 << 7) |
| |
| /* AUDENC_PMU_CON51 */ |
| #define RG_AUDADCLIVGEN_SDHALF_SFT 0 |
| #define RG_AUDADCLIVGEN_SDHALF_MASK 0x1 |
| #define RG_AUDADCLIVGEN_SDHALF_MASK_SFT (0x1 << 0) |
| #define RG_AUDADCRIVGEN_SDHALF_SFT 1 |
| #define RG_AUDADCRIVGEN_SDHALF_MASK 0x1 |
| #define RG_AUDADCRIVGEN_SDHALF_MASK_SFT (0x1 << 1) |
| #define RG_AUDADC3IVGEN_SDHALF_SFT 2 |
| #define RG_AUDADC3IVGEN_SDHALF_MASK 0x1 |
| #define RG_AUDADC3IVGEN_SDHALF_MASK_SFT (0x1 << 2) |
| #define RG_AUDADC4IVGEN_SDHALF_SFT 3 |
| #define RG_AUDADC4IVGEN_SDHALF_MASK 0x1 |
| #define RG_AUDADC4IVGEN_SDHALF_MASK_SFT (0x1 << 3) |
| #define RG_AUDADCLINTEG2XCURRENT_SFT 4 |
| #define RG_AUDADCLINTEG2XCURRENT_MASK 0x1 |
| #define RG_AUDADCLINTEG2XCURRENT_MASK_SFT (0x1 << 4) |
| #define RG_AUDADCRINTEG2XCURRENT_SFT 5 |
| #define RG_AUDADCRINTEG2XCURRENT_MASK 0x1 |
| #define RG_AUDADCRINTEG2XCURRENT_MASK_SFT (0x1 << 5) |
| #define RG_AUDADC3INTEG2XCURRENT_SFT 6 |
| #define RG_AUDADC3INTEG2XCURRENT_MASK 0x1 |
| #define RG_AUDADC3INTEG2XCURRENT_MASK_SFT (0x1 << 6) |
| #define RG_AUDADC4INTEG2XCURRENT_SFT 7 |
| #define RG_AUDADC4INTEG2XCURRENT_MASK 0x1 |
| #define RG_AUDADC4INTEG2XCURRENT_MASK_SFT (0x1 << 7) |
| |
| /* AUDENC_PMU_CON52 */ |
| #define RG_AUDLADC1STSTAGELPEN_0_SFT 0 |
| #define RG_AUDLADC1STSTAGELPEN_0_MASK 0x1 |
| #define RG_AUDLADC1STSTAGELPEN_0_MASK_SFT (0x1 << 0) |
| #define RG_AUD3PREAMPIDDTEST_SFT 1 |
| #define RG_AUD3PREAMPIDDTEST_MASK 0x3 |
| #define RG_AUD3PREAMPIDDTEST_MASK_SFT (0x3 << 1) |
| #define RG_AUD4PREAMPIDDTEST_SFT 3 |
| #define RG_AUD4PREAMPIDDTEST_MASK 0x3 |
| #define RG_AUD4PREAMPIDDTEST_MASK_SFT (0x3 << 3) |
| #define RG_AUDPGAR_CAPRA_SFT 5 |
| #define RG_AUDPGAR_CAPRA_MASK 0x1 |
| #define RG_AUDPGAR_CAPRA_MASK_SFT (0x1 << 5) |
| #define RG_AUDPGA3_CAPRA_SFT 6 |
| #define RG_AUDPGA3_CAPRA_MASK 0x1 |
| #define RG_AUDPGA3_CAPRA_MASK_SFT (0x1 << 6) |
| #define RG_AUDPGA4_CAPRA_SFT 7 |
| #define RG_AUDPGA4_CAPRA_MASK 0x1 |
| #define RG_AUDPGA4_CAPRA_MASK_SFT (0x1 << 7) |
| |
| /* AUDENC_PMU_CON53 */ |
| #define RG_AUDSPAREVA30_SFT 0 |
| #define RG_AUDSPAREVA30_MASK 0xff |
| #define RG_AUDSPAREVA30_MASK_SFT (0xff << 0) |
| |
| /* AUDENC_PMU_CON54 */ |
| #define RG_AUDSPAREVA18_SFT 0 |
| #define RG_AUDSPAREVA18_MASK 0xff |
| #define RG_AUDSPAREVA18_MASK_SFT (0xff << 0) |
| |
| /* AUDENC_PMU_CON55 */ |
| #define RG_AUDDIGMICEN_SFT 0 |
| #define RG_AUDDIGMICEN_MASK 0x1 |
| #define RG_AUDDIGMICEN_MASK_SFT (0x1 << 0) |
| #define RG_AUDDIGMICBIAS_SFT 1 |
| #define RG_AUDDIGMICBIAS_MASK 0x3 |
| #define RG_AUDDIGMICBIAS_MASK_SFT (0x3 << 1) |
| #define RG_DMICHPCLKEN_SFT 3 |
| #define RG_DMICHPCLKEN_MASK 0x1 |
| #define RG_DMICHPCLKEN_MASK_SFT (0x1 << 3) |
| #define RG_AUDDIGMIC_PREDRVN_ENHB_SFT 4 |
| #define RG_AUDDIGMIC_PREDRVN_ENHB_MASK 0x1 |
| #define RG_AUDDIGMIC_PREDRVN_ENHB_MASK_SFT (0x1 << 4) |
| #define RG_AUDDIGMIC_PREDRVP_ENHB_SFT 5 |
| #define RG_AUDDIGMIC_PREDRVP_ENHB_MASK 0x1 |
| #define RG_AUDDIGMIC_PREDRVP_ENHB_MASK_SFT (0x1 << 5) |
| #define RG_AUDDIGMIC_DRVA_EN_SFT 6 |
| #define RG_AUDDIGMIC_DRVA_EN_MASK 0x1 |
| #define RG_AUDDIGMIC_DRVA_EN_MASK_SFT (0x1 << 6) |
| #define RG_AUDDIGMIC_DRVB_EN_SFT 7 |
| #define RG_AUDDIGMIC_DRVB_EN_MASK 0x1 |
| #define RG_AUDDIGMIC_DRVB_EN_MASK_SFT (0x1 << 7) |
| |
| /* AUDENC_PMU_CON56 */ |
| #define RG_DMICMONEN_SFT 0 |
| #define RG_DMICMONEN_MASK 0x1 |
| #define RG_DMICMONEN_MASK_SFT (0x1 << 0) |
| #define RG_DMICMONSEL_SFT 1 |
| #define RG_DMICMONSEL_MASK 0x7 |
| #define RG_DMICMONSEL_MASK_SFT (0x7 << 1) |
| #define RG_AUDSPAREVMIC_SFT 4 |
| #define RG_AUDSPAREVMIC_MASK 0xf |
| #define RG_AUDSPAREVMIC_MASK_SFT (0xf << 4) |
| |
| /* AUDENC_PMU_CON57 */ |
| #define RG_AUDDIGMIC1EN_SFT 0 |
| #define RG_AUDDIGMIC1EN_MASK 0x1 |
| #define RG_AUDDIGMIC1EN_MASK_SFT (0x1 << 0) |
| #define RG_AUDDIGMICBIAS1_SFT 1 |
| #define RG_AUDDIGMICBIAS1_MASK 0x3 |
| #define RG_AUDDIGMICBIAS1_MASK_SFT (0x3 << 1) |
| #define RG_DMIC1HPCLKEN_SFT 3 |
| #define RG_DMIC1HPCLKEN_MASK 0x1 |
| #define RG_DMIC1HPCLKEN_MASK_SFT (0x1 << 3) |
| #define RG_AUDDIGMIC1_PREDRVN_ENHB_SFT 4 |
| #define RG_AUDDIGMIC1_PREDRVN_ENHB_MASK 0x1 |
| #define RG_AUDDIGMIC1_PREDRVN_ENHB_MASK_SFT (0x1 << 4) |
| #define RG_AUDDIGMIC1_PREDRVP_ENHB_SFT 5 |
| #define RG_AUDDIGMIC1_PREDRVP_ENHB_MASK 0x1 |
| #define RG_AUDDIGMIC1_PREDRVP_ENHB_MASK_SFT (0x1 << 5) |
| #define RG_AUDDIGMIC1_DRVA_EN_SFT 6 |
| #define RG_AUDDIGMIC1_DRVA_EN_MASK 0x1 |
| #define RG_AUDDIGMIC1_DRVA_EN_MASK_SFT (0x1 << 6) |
| #define RG_AUDDIGMIC1_DRVB_EN_SFT 7 |
| #define RG_AUDDIGMIC1_DRVB_EN_MASK 0x1 |
| #define RG_AUDDIGMIC1_DRVB_EN_MASK_SFT (0x1 << 7) |
| |
| /* AUDENC_PMU_CON58 */ |
| #define RG_DMIC1MONEN_SFT 0 |
| #define RG_DMIC1MONEN_MASK 0x1 |
| #define RG_DMIC1MONEN_MASK_SFT (0x1 << 0) |
| #define RG_DMIC1MONSEL_SFT 1 |
| #define RG_DMIC1MONSEL_MASK 0x7 |
| #define RG_DMIC1MONSEL_MASK_SFT (0x7 << 1) |
| #define RG_AUDSPAREVMIC1_SFT 4 |
| #define RG_AUDSPAREVMIC1_MASK 0xf |
| #define RG_AUDSPAREVMIC1_MASK_SFT (0xf << 4) |
| |
| /* AUDENC_PMU_CON59 */ |
| #define RG_AUDPWDBMICBIAS0_SFT 0 |
| #define RG_AUDPWDBMICBIAS0_MASK 0x1 |
| #define RG_AUDPWDBMICBIAS0_MASK_SFT (0x1 << 0) |
| #define RG_AUDMICBIAS0BYPASSEN_SFT 1 |
| #define RG_AUDMICBIAS0BYPASSEN_MASK 0x1 |
| #define RG_AUDMICBIAS0BYPASSEN_MASK_SFT (0x1 << 1) |
| #define RG_AUDMICBIAS0LOWPEN_SFT 2 |
| #define RG_AUDMICBIAS0LOWPEN_MASK 0x1 |
| #define RG_AUDMICBIAS0LOWPEN_MASK_SFT (0x1 << 2) |
| #define RG_AUDMICBIAS0ULTRALOWPEN_SFT 3 |
| #define RG_AUDMICBIAS0ULTRALOWPEN_MASK 0x1 |
| #define RG_AUDMICBIAS0ULTRALOWPEN_MASK_SFT (0x1 << 3) |
| #define RG_AUDMICBIAS0VREF_SFT 4 |
| #define RG_AUDMICBIAS0VREF_MASK 0x7 |
| #define RG_AUDMICBIAS0VREF_MASK_SFT (0x7 << 4) |
| |
| /* AUDENC_PMU_CON60 */ |
| #define RG_AUDMICBIAS0DCSW0P1EN_SFT 0 |
| #define RG_AUDMICBIAS0DCSW0P1EN_MASK 0x1 |
| #define RG_AUDMICBIAS0DCSW0P1EN_MASK_SFT (0x1 << 0) |
| #define RG_AUDMICBIAS0DCSW0P2EN_SFT 1 |
| #define RG_AUDMICBIAS0DCSW0P2EN_MASK 0x1 |
| #define RG_AUDMICBIAS0DCSW0P2EN_MASK_SFT (0x1 << 1) |
| #define RG_AUDMICBIAS0DCSW0NEN_SFT 2 |
| #define RG_AUDMICBIAS0DCSW0NEN_MASK 0x1 |
| #define RG_AUDMICBIAS0DCSW0NEN_MASK_SFT (0x1 << 2) |
| #define RG_AUDMICBIAS0DCSW2P1EN_SFT 4 |
| #define RG_AUDMICBIAS0DCSW2P1EN_MASK 0x1 |
| #define RG_AUDMICBIAS0DCSW2P1EN_MASK_SFT (0x1 << 4) |
| #define RG_AUDMICBIAS0DCSW2P2EN_SFT 5 |
| #define RG_AUDMICBIAS0DCSW2P2EN_MASK 0x1 |
| #define RG_AUDMICBIAS0DCSW2P2EN_MASK_SFT (0x1 << 5) |
| #define RG_AUDMICBIAS0DCSW2NEN_SFT 6 |
| #define RG_AUDMICBIAS0DCSW2NEN_MASK 0x1 |
| #define RG_AUDMICBIAS0DCSW2NEN_MASK_SFT (0x1 << 6) |
| |
| /* AUDENC_PMU_CON61 */ |
| #define RG_AUDPWDBMICBIAS1_SFT 0 |
| #define RG_AUDPWDBMICBIAS1_MASK 0x1 |
| #define RG_AUDPWDBMICBIAS1_MASK_SFT (0x1 << 0) |
| #define RG_AUDMICBIAS1BYPASSEN_SFT 1 |
| #define RG_AUDMICBIAS1BYPASSEN_MASK 0x1 |
| #define RG_AUDMICBIAS1BYPASSEN_MASK_SFT (0x1 << 1) |
| #define RG_AUDMICBIAS1LOWPEN_SFT 2 |
| #define RG_AUDMICBIAS1LOWPEN_MASK 0x1 |
| #define RG_AUDMICBIAS1LOWPEN_MASK_SFT (0x1 << 2) |
| #define RG_AUDMICBIAS1ULTRALOWPEN_SFT 3 |
| #define RG_AUDMICBIAS1ULTRALOWPEN_MASK 0x1 |
| #define RG_AUDMICBIAS1ULTRALOWPEN_MASK_SFT (0x1 << 3) |
| #define RG_AUDMICBIAS1VREF_SFT 4 |
| #define RG_AUDMICBIAS1VREF_MASK 0x7 |
| #define RG_AUDMICBIAS1VREF_MASK_SFT (0x7 << 4) |
| |
| /* AUDENC_PMU_CON62 */ |
| #define RG_AUDMICBIAS1DCSW1PEN_SFT 0 |
| #define RG_AUDMICBIAS1DCSW1PEN_MASK 0x1 |
| #define RG_AUDMICBIAS1DCSW1PEN_MASK_SFT (0x1 << 0) |
| #define RG_AUDMICBIAS1DCSW1NEN_SFT 1 |
| #define RG_AUDMICBIAS1DCSW1NEN_MASK 0x1 |
| #define RG_AUDMICBIAS1DCSW1NEN_MASK_SFT (0x1 << 1) |
| #define RG_BANDGAPGEN_SFT 2 |
| #define RG_BANDGAPGEN_MASK 0x1 |
| #define RG_BANDGAPGEN_MASK_SFT (0x1 << 2) |
| #define RG_AUDMICBIAS1HVEN_SFT 4 |
| #define RG_AUDMICBIAS1HVEN_MASK 0x1 |
| #define RG_AUDMICBIAS1HVEN_MASK_SFT (0x1 << 4) |
| #define RG_AUDMICBIAS1HVVREF_SFT 5 |
| #define RG_AUDMICBIAS1HVVREF_MASK 0x1 |
| #define RG_AUDMICBIAS1HVVREF_MASK_SFT (0x1 << 5) |
| |
| /* AUDENC_PMU_CON63 */ |
| #define RG_AUDPWDBMICBIAS2_SFT 0 |
| #define RG_AUDPWDBMICBIAS2_MASK 0x1 |
| #define RG_AUDPWDBMICBIAS2_MASK_SFT (0x1 << 0) |
| #define RG_AUDMICBIAS2BYPASSEN_SFT 1 |
| #define RG_AUDMICBIAS2BYPASSEN_MASK 0x1 |
| #define RG_AUDMICBIAS2BYPASSEN_MASK_SFT (0x1 << 1) |
| #define RG_AUDMICBIAS2LOWPEN_SFT 2 |
| #define RG_AUDMICBIAS2LOWPEN_MASK 0x1 |
| #define RG_AUDMICBIAS2LOWPEN_MASK_SFT (0x1 << 2) |
| #define RG_AUDMICBIAS2ULTRALOWPEN_SFT 3 |
| #define RG_AUDMICBIAS2ULTRALOWPEN_MASK 0x1 |
| #define RG_AUDMICBIAS2ULTRALOWPEN_MASK_SFT (0x1 << 3) |
| #define RG_AUDMICBIAS2VREF_SFT 4 |
| #define RG_AUDMICBIAS2VREF_MASK 0x7 |
| #define RG_AUDMICBIAS2VREF_MASK_SFT (0x7 << 4) |
| |
| /* AUDENC_PMU_CON64 */ |
| #define RG_AUDMICBIAS2DCSW0P1EN_SFT 0 |
| #define RG_AUDMICBIAS2DCSW0P1EN_MASK 0x1 |
| #define RG_AUDMICBIAS2DCSW0P1EN_MASK_SFT (0x1 << 0) |
| #define RG_AUDMICBIAS2DCSW0P2EN_SFT 1 |
| #define RG_AUDMICBIAS2DCSW0P2EN_MASK 0x1 |
| #define RG_AUDMICBIAS2DCSW0P2EN_MASK_SFT (0x1 << 1) |
| #define RG_AUDMICBIAS2DCSW0NEN_SFT 2 |
| #define RG_AUDMICBIAS2DCSW0NEN_MASK 0x1 |
| #define RG_AUDMICBIAS2DCSW0NEN_MASK_SFT (0x1 << 2) |
| #define RG_AUDMICBIAS2DCSW2P1EN_SFT 4 |
| #define RG_AUDMICBIAS2DCSW2P1EN_MASK 0x1 |
| #define RG_AUDMICBIAS2DCSW2P1EN_MASK_SFT (0x1 << 4) |
| #define RG_AUDMICBIAS2DCSW2P2EN_SFT 5 |
| #define RG_AUDMICBIAS2DCSW2P2EN_MASK 0x1 |
| #define RG_AUDMICBIAS2DCSW2P2EN_MASK_SFT (0x1 << 5) |
| #define RG_AUDMICBIAS2DCSW2NEN_SFT 6 |
| #define RG_AUDMICBIAS2DCSW2NEN_MASK 0x1 |
| #define RG_AUDMICBIAS2DCSW2NEN_MASK_SFT (0x1 << 6) |
| |
| /* AUDENC_PMU_CON65 */ |
| #define RG_AUDPWDBMICBIAS3_SFT 0 |
| #define RG_AUDPWDBMICBIAS3_MASK 0x1 |
| #define RG_AUDPWDBMICBIAS3_MASK_SFT (0x1 << 0) |
| #define RG_AUDMICBIAS3BYPASSEN_SFT 1 |
| #define RG_AUDMICBIAS3BYPASSEN_MASK 0x1 |
| #define RG_AUDMICBIAS3BYPASSEN_MASK_SFT (0x1 << 1) |
| #define RG_AUDMICBIAS3LOWPEN_SFT 2 |
| #define RG_AUDMICBIAS3LOWPEN_MASK 0x1 |
| #define RG_AUDMICBIAS3LOWPEN_MASK_SFT (0x1 << 2) |
| #define RG_AUDMICBIAS3ULTRALOWPEN_SFT 3 |
| #define RG_AUDMICBIAS3ULTRALOWPEN_MASK 0x1 |
| #define RG_AUDMICBIAS3ULTRALOWPEN_MASK_SFT (0x1 << 3) |
| #define RG_AUDMICBIAS3VREF_SFT 4 |
| #define RG_AUDMICBIAS3VREF_MASK 0x7 |
| #define RG_AUDMICBIAS3VREF_MASK_SFT (0x7 << 4) |
| |
| /* AUDENC_PMU_CON66 */ |
| #define RG_AUDMICBIAS3DCSW3P1EN_SFT 0 |
| #define RG_AUDMICBIAS3DCSW3P1EN_MASK 0x1 |
| #define RG_AUDMICBIAS3DCSW3P1EN_MASK_SFT (0x1 << 0) |
| #define RG_AUDMICBIAS3DCSW3P2EN_SFT 1 |
| #define RG_AUDMICBIAS3DCSW3P2EN_MASK 0x1 |
| #define RG_AUDMICBIAS3DCSW3P2EN_MASK_SFT (0x1 << 1) |
| #define RG_AUDMICBIAS3DCSW3NEN_SFT 2 |
| #define RG_AUDMICBIAS3DCSW3NEN_MASK 0x1 |
| #define RG_AUDMICBIAS3DCSW3NEN_MASK_SFT (0x1 << 2) |
| #define RG_AUDMICBIAS3DCSW4P1EN_SFT 4 |
| #define RG_AUDMICBIAS3DCSW4P1EN_MASK 0x1 |
| #define RG_AUDMICBIAS3DCSW4P1EN_MASK_SFT (0x1 << 4) |
| #define RG_AUDMICBIAS3DCSW4P2EN_SFT 5 |
| #define RG_AUDMICBIAS3DCSW4P2EN_MASK 0x1 |
| #define RG_AUDMICBIAS3DCSW4P2EN_MASK_SFT (0x1 << 5) |
| #define RG_AUDMICBIAS3DCSW4NEN_SFT 6 |
| #define RG_AUDMICBIAS3DCSW4NEN_MASK 0x1 |
| #define RG_AUDMICBIAS3DCSW4NEN_MASK_SFT (0x1 << 6) |
| |
| /* AUDENC_PMU_CON67 */ |
| #define RG_HPL_DC_BIAS_SFT 0 |
| #define RG_HPL_DC_BIAS_MASK 0x1 |
| #define RG_HPL_DC_BIAS_MASK_SFT (0x1 << 0) |
| #define RG_HPR_DC_BIAS_SFT 1 |
| #define RG_HPR_DC_BIAS_MASK 0x1 |
| #define RG_HPR_DC_BIAS_MASK_SFT (0x1 << 1) |
| #define RG_AUDMICBIASSPARE_SFT 2 |
| #define RG_AUDMICBIASSPARE_MASK 0x3f |
| #define RG_AUDMICBIASSPARE_MASK_SFT (0x3f << 2) |
| |
| /* AUDENC_PMU_CON68 */ |
| #define RG_AUDACCDETMICBIAS0PULLLOW_SFT 0 |
| #define RG_AUDACCDETMICBIAS0PULLLOW_MASK 0x1 |
| #define RG_AUDACCDETMICBIAS0PULLLOW_MASK_SFT (0x1 << 0) |
| #define RG_AUDACCDETMICBIAS1PULLLOW_SFT 1 |
| #define RG_AUDACCDETMICBIAS1PULLLOW_MASK 0x1 |
| #define RG_AUDACCDETMICBIAS1PULLLOW_MASK_SFT (0x1 << 1) |
| #define RG_AUDACCDETMICBIAS2PULLLOW_SFT 2 |
| #define RG_AUDACCDETMICBIAS2PULLLOW_MASK 0x1 |
| #define RG_AUDACCDETMICBIAS2PULLLOW_MASK_SFT (0x1 << 2) |
| #define RG_AUDACCDETVIN1PULLLOW_SFT 3 |
| #define RG_AUDACCDETVIN1PULLLOW_MASK 0x1 |
| #define RG_AUDACCDETVIN1PULLLOW_MASK_SFT (0x1 << 3) |
| #define RG_AUDACCDETVTHACAL_SFT 4 |
| #define RG_AUDACCDETVTHACAL_MASK 0x1 |
| #define RG_AUDACCDETVTHACAL_MASK_SFT (0x1 << 4) |
| #define RG_AUDACCDETVTHBCAL_SFT 5 |
| #define RG_AUDACCDETVTHBCAL_MASK 0x1 |
| #define RG_AUDACCDETVTHBCAL_MASK_SFT (0x1 << 5) |
| #define RG_AUDACCDETTVDET_SFT 6 |
| #define RG_AUDACCDETTVDET_MASK 0x1 |
| #define RG_AUDACCDETTVDET_MASK_SFT (0x1 << 6) |
| #define RG_ACCDETSEL_SFT 7 |
| #define RG_ACCDETSEL_MASK 0x1 |
| #define RG_ACCDETSEL_MASK_SFT (0x1 << 7) |
| |
| /* AUDENC_PMU_CON69 */ |
| #define RG_SWBUFMODSEL_SFT 0 |
| #define RG_SWBUFMODSEL_MASK 0x1 |
| #define RG_SWBUFMODSEL_MASK_SFT (0x1 << 0) |
| #define RG_SWBUFSWEN_SFT 1 |
| #define RG_SWBUFSWEN_MASK 0x1 |
| #define RG_SWBUFSWEN_MASK_SFT (0x1 << 1) |
| #define RG_EINT0NOHYS_SFT 2 |
| #define RG_EINT0NOHYS_MASK 0x1 |
| #define RG_EINT0NOHYS_MASK_SFT (0x1 << 2) |
| #define RG_EINT0CONFIGACCDET_SFT 3 |
| #define RG_EINT0CONFIGACCDET_MASK 0x1 |
| #define RG_EINT0CONFIGACCDET_MASK_SFT (0x1 << 3) |
| #define RG_EINT0HIRENB_SFT 4 |
| #define RG_EINT0HIRENB_MASK 0x1 |
| #define RG_EINT0HIRENB_MASK_SFT (0x1 << 4) |
| #define RG_ACCDET2AUXRESBYPASS_SFT 5 |
| #define RG_ACCDET2AUXRESBYPASS_MASK 0x1 |
| #define RG_ACCDET2AUXRESBYPASS_MASK_SFT (0x1 << 5) |
| #define RG_ACCDET2AUXSWEN_SFT 6 |
| #define RG_ACCDET2AUXSWEN_MASK 0x1 |
| #define RG_ACCDET2AUXSWEN_MASK_SFT (0x1 << 6) |
| #define RG_AUDACCDETMICBIAS3PULLLOW_SFT 7 |
| #define RG_AUDACCDETMICBIAS3PULLLOW_MASK 0x1 |
| #define RG_AUDACCDETMICBIAS3PULLLOW_MASK_SFT (0x1 << 7) |
| |
| /* AUDENC_PMU_CON70 */ |
| #define RG_EINT1CONFIGACCDET_SFT 0 |
| #define RG_EINT1CONFIGACCDET_MASK 0x1 |
| #define RG_EINT1CONFIGACCDET_MASK_SFT (0x1 << 0) |
| #define RG_EINT1HIRENB_SFT 1 |
| #define RG_EINT1HIRENB_MASK 0x1 |
| #define RG_EINT1HIRENB_MASK_SFT (0x1 << 1) |
| #define RG_EINT1NOHYS_SFT 2 |
| #define RG_EINT1NOHYS_MASK 0x1 |
| #define RG_EINT1NOHYS_MASK_SFT (0x1 << 2) |
| #define RG_EINTCOMPVTH_SFT 4 |
| #define RG_EINTCOMPVTH_MASK 0xf |
| #define RG_EINTCOMPVTH_MASK_SFT (0xf << 4) |
| |
| /* AUDENC_PMU_CON71 */ |
| #define RG_MTEST_EN_SFT 0 |
| #define RG_MTEST_EN_MASK 0x1 |
| #define RG_MTEST_EN_MASK_SFT (0x1 << 0) |
| #define RG_MTEST_SEL_SFT 1 |
| #define RG_MTEST_SEL_MASK 0x1 |
| #define RG_MTEST_SEL_MASK_SFT (0x1 << 1) |
| #define RG_MTEST_CURRENT_SFT 2 |
| #define RG_MTEST_CURRENT_MASK 0x1 |
| #define RG_MTEST_CURRENT_MASK_SFT (0x1 << 2) |
| #define RG_ANALOGFDEN_SFT 4 |
| #define RG_ANALOGFDEN_MASK 0x1 |
| #define RG_ANALOGFDEN_MASK_SFT (0x1 << 4) |
| #define RG_FDVIN1PPULLLOW_SFT 5 |
| #define RG_FDVIN1PPULLLOW_MASK 0x1 |
| #define RG_FDVIN1PPULLLOW_MASK_SFT (0x1 << 5) |
| #define RG_FDEINT0TYPE_SFT 6 |
| #define RG_FDEINT0TYPE_MASK 0x1 |
| #define RG_FDEINT0TYPE_MASK_SFT (0x1 << 6) |
| #define RG_FDEINT1TYPE_SFT 7 |
| #define RG_FDEINT1TYPE_MASK 0x1 |
| #define RG_FDEINT1TYPE_MASK_SFT (0x1 << 7) |
| |
| /* AUDENC_PMU_CON72 */ |
| #define RG_EINT0CMPEN_SFT 0 |
| #define RG_EINT0CMPEN_MASK 0x1 |
| #define RG_EINT0CMPEN_MASK_SFT (0x1 << 0) |
| #define RG_EINT0CMPMEN_SFT 1 |
| #define RG_EINT0CMPMEN_MASK 0x1 |
| #define RG_EINT0CMPMEN_MASK_SFT (0x1 << 1) |
| #define RG_EINT0EN_SFT 2 |
| #define RG_EINT0EN_MASK 0x1 |
| #define RG_EINT0EN_MASK_SFT (0x1 << 2) |
| #define RG_EINT0CEN_SFT 3 |
| #define RG_EINT0CEN_MASK 0x1 |
| #define RG_EINT0CEN_MASK_SFT (0x1 << 3) |
| #define RG_EINT0INVEN_SFT 4 |
| #define RG_EINT0INVEN_MASK 0x1 |
| #define RG_EINT0INVEN_MASK_SFT (0x1 << 4) |
| |
| /* AUDENC_PMU_CON73 */ |
| #define RG_EINT1CMPEN_SFT 0 |
| #define RG_EINT1CMPEN_MASK 0x1 |
| #define RG_EINT1CMPEN_MASK_SFT (0x1 << 0) |
| #define RG_EINT1CMPMEN_SFT 1 |
| #define RG_EINT1CMPMEN_MASK 0x1 |
| #define RG_EINT1CMPMEN_MASK_SFT (0x1 << 1) |
| #define RG_EINT1EN_SFT 2 |
| #define RG_EINT1EN_MASK 0x1 |
| #define RG_EINT1EN_MASK_SFT (0x1 << 2) |
| #define RG_EINT1CEN_SFT 3 |
| #define RG_EINT1CEN_MASK 0x1 |
| #define RG_EINT1CEN_MASK_SFT (0x1 << 3) |
| #define RG_EINT1INVEN_SFT 4 |
| #define RG_EINT1INVEN_MASK 0x1 |
| #define RG_EINT1INVEN_MASK_SFT (0x1 << 4) |
| |
| /* AUDENC_PMU_CON74 */ |
| #define RG_ACCDET_PL_ESDMOS_SFT 0 |
| #define RG_ACCDET_PL_ESDMOS_MASK 0x1 |
| #define RG_ACCDET_PL_ESDMOS_MASK_SFT (0x1 << 0) |
| #define RG_VIN1OFFENB_SFT 1 |
| #define RG_VIN1OFFENB_MASK 0x1 |
| #define RG_VIN1OFFENB_MASK_SFT (0x1 << 1) |
| #define RG_ACC_OR_DCC_SFT 2 |
| #define RG_ACC_OR_DCC_MASK 0x1 |
| #define RG_ACC_OR_DCC_MASK_SFT (0x1 << 2) |
| #define RG_MVTH2EN_SFT 3 |
| #define RG_MVTH2EN_MASK 0x1 |
| #define RG_MVTH2EN_MASK_SFT (0x1 << 3) |
| #define RG_MVTH2SEL_SFT 4 |
| #define RG_MVTH2SEL_MASK 0xf |
| #define RG_MVTH2SEL_MASK_SFT (0xf << 4) |
| |
| /* AUDENC_PMU_CON75 */ |
| #define RG_ACCDETSPARE_SFT 0 |
| #define RG_ACCDETSPARE_MASK 0xff |
| #define RG_ACCDETSPARE_MASK_SFT (0xff << 0) |
| |
| /* AUDENC_PMU_CON76 */ |
| #define RG_ACCDETSPARE2_SFT 0 |
| #define RG_ACCDETSPARE2_MASK 0xff |
| #define RG_ACCDETSPARE2_MASK_SFT (0xff << 0) |
| |
| /* AUDENC_PMU_CON77 */ |
| #define RG_EINT0CTURBO_SFT 0 |
| #define RG_EINT0CTURBO_MASK 0x1f |
| #define RG_EINT0CTURBO_MASK_SFT (0x1f << 0) |
| |
| /* AUDENC_PMU_CON78 */ |
| #define RG_EINT1CTURBO_SFT 0 |
| #define RG_EINT1CTURBO_MASK 0x1f |
| #define RG_EINT1CTURBO_MASK_SFT (0x1f << 0) |
| |
| /* AUDENC_PMU_CON79 */ |
| #define RG_AUDENCSPAREVA30_SFT 0 |
| #define RG_AUDENCSPAREVA30_MASK 0xff |
| #define RG_AUDENCSPAREVA30_MASK_SFT (0xff << 0) |
| |
| /* AUDENC_PMU_CON80 */ |
| #define RG_AUDENCSPAREVA18_SFT 0 |
| #define RG_AUDENCSPAREVA18_MASK 0xff |
| #define RG_AUDENCSPAREVA18_MASK_SFT (0xff << 0) |
| |
| /* AUDENC_PMU_CON81 */ |
| #define RG_ADCL_CLKMODE_SFT 0 |
| #define RG_ADCL_CLKMODE_MASK 0x1 |
| #define RG_ADCL_CLKMODE_MASK_SFT (0x1 << 0) |
| #define RG_ADCR_CLKMODE_SFT 1 |
| #define RG_ADCR_CLKMODE_MASK 0x1 |
| #define RG_ADCR_CLKMODE_MASK_SFT (0x1 << 1) |
| #define RG_ADC3_CLKMODE_SFT 2 |
| #define RG_ADC3_CLKMODE_MASK 0x1 |
| #define RG_ADC3_CLKMODE_MASK_SFT (0x1 << 2) |
| #define RG_ADC4_CLKMODE_SFT 3 |
| #define RG_ADC4_CLKMODE_MASK 0x1 |
| #define RG_ADC4_CLKMODE_MASK_SFT (0x1 << 3) |
| |
| /* AUDENC_ELR_NUM */ |
| #define AUDENC_ELR_LEN_SFT 0 |
| #define AUDENC_ELR_LEN_MASK 0xff |
| #define AUDENC_ELR_LEN_MASK_SFT (0xff << 0) |
| |
| /* AUDENC_ELR_0 */ |
| #define RG_VCM_PGA_HIFI_SEL_SFT 0 |
| #define RG_VCM_PGA_HIFI_SEL_MASK 0xf |
| #define RG_VCM_PGA_HIFI_SEL_MASK_SFT (0xf << 0) |
| #define RG_VCM_PGA_LPM_SEL_SFT 4 |
| #define RG_VCM_PGA_LPM_SEL_MASK 0xf |
| #define RG_VCM_PGA_LPM_SEL_MASK_SFT (0xf << 4) |
| |
| /* AUDENC_ELR_1 */ |
| #define RG_AUDLADCFLASHFFCAPVREF_SEL_SFT 0 |
| #define RG_AUDLADCFLASHFFCAPVREF_SEL_MASK 0x3 |
| #define RG_AUDLADCFLASHFFCAPVREF_SEL_MASK_SFT (0x3 << 0) |
| #define RG_AUDRADCFLASHFFCAPVREF_SEL_SFT 2 |
| #define RG_AUDRADCFLASHFFCAPVREF_SEL_MASK 0x3 |
| #define RG_AUDRADCFLASHFFCAPVREF_SEL_MASK_SFT (0x3 << 2) |
| #define RG_AUD3ADCFLASHFFCAPVREF_SEL_SFT 4 |
| #define RG_AUD3ADCFLASHFFCAPVREF_SEL_MASK 0x3 |
| #define RG_AUD3ADCFLASHFFCAPVREF_SEL_MASK_SFT (0x3 << 4) |
| #define RG_AUD4ADCFLASHFFCAPVREF_SEL_SFT 6 |
| #define RG_AUD4ADCFLASHFFCAPVREF_SEL_MASK 0x3 |
| #define RG_AUD4ADCFLASHFFCAPVREF_SEL_MASK_SFT (0x3 << 6) |
| |
| /* AUDENC_ELR_2 */ |
| #define RG_VCMR_PGA_HIFI_SEL_SFT 0 |
| #define RG_VCMR_PGA_HIFI_SEL_MASK 0xf |
| #define RG_VCMR_PGA_HIFI_SEL_MASK_SFT (0xf << 0) |
| #define RG_VCMR_PGA_LPM_SEL_SFT 4 |
| #define RG_VCMR_PGA_LPM_SEL_MASK 0xf |
| #define RG_VCMR_PGA_LPM_SEL_MASK_SFT (0xf << 4) |
| |
| /* AUDENC_ELR_3 */ |
| #define RG_VCM3_PGA_HIFI_SEL_SFT 0 |
| #define RG_VCM3_PGA_HIFI_SEL_MASK 0xf |
| #define RG_VCM3_PGA_HIFI_SEL_MASK_SFT (0xf << 0) |
| #define RG_VCM3_PGA_LPM_SEL_SFT 4 |
| #define RG_VCM3_PGA_LPM_SEL_MASK 0xf |
| #define RG_VCM3_PGA_LPM_SEL_MASK_SFT (0xf << 4) |
| |
| /* AUDENC_ELR_4 */ |
| #define RG_VCM4_PGA_HIFI_SEL_SFT 0 |
| #define RG_VCM4_PGA_HIFI_SEL_MASK 0xf |
| #define RG_VCM4_PGA_HIFI_SEL_MASK_SFT (0xf << 0) |
| #define RG_VCM4_PGA_LPM_SEL_SFT 4 |
| #define RG_VCM4_PGA_LPM_SEL_MASK 0xf |
| #define RG_VCM4_PGA_LPM_SEL_MASK_SFT (0xf << 4) |
| |
| /* AUDDEC_ANA_ID */ |
| #define AUDDEC_ANA_ID_SFT 0 |
| #define AUDDEC_ANA_ID_MASK 0xff |
| #define AUDDEC_ANA_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDDEC_DIG_ID */ |
| #define AUDDEC_DIG_ID_SFT 0 |
| #define AUDDEC_DIG_ID_MASK 0xff |
| #define AUDDEC_DIG_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDDEC_ANA_REV */ |
| #define AUDDEC_ANA_MINOR_REV_SFT 0 |
| #define AUDDEC_ANA_MINOR_REV_MASK 0xf |
| #define AUDDEC_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDDEC_ANA_MAJOR_REV_SFT 4 |
| #define AUDDEC_ANA_MAJOR_REV_MASK 0xf |
| #define AUDDEC_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDDEC_DIG_REV */ |
| #define AUDDEC_DIG_MINOR_REV_SFT 0 |
| #define AUDDEC_DIG_MINOR_REV_MASK 0xf |
| #define AUDDEC_DIG_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDDEC_DIG_MAJOR_REV_SFT 4 |
| #define AUDDEC_DIG_MAJOR_REV_MASK 0xf |
| #define AUDDEC_DIG_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDDEC_DBI */ |
| #define AUDDEC_CBS_SFT 0 |
| #define AUDDEC_CBS_MASK 0x3 |
| #define AUDDEC_CBS_MASK_SFT (0x3 << 0) |
| #define AUDDEC_BIX_SFT 2 |
| #define AUDDEC_BIX_MASK 0x3 |
| #define AUDDEC_BIX_MASK_SFT (0x3 << 2) |
| |
| /* AUDDEC_ESP */ |
| #define AUDDEC_ESP_SFT 0 |
| #define AUDDEC_ESP_MASK 0xff |
| #define AUDDEC_ESP_MASK_SFT (0xff << 0) |
| |
| /* AUDDEC_FPI */ |
| #define AUDDEC_FPI_SFT 0 |
| #define AUDDEC_FPI_MASK 0xff |
| #define AUDDEC_FPI_MASK_SFT (0xff << 0) |
| |
| /* AUDDEC_DXI */ |
| #define AUDDEC_DXI_SFT 0 |
| #define AUDDEC_DXI_MASK 0xff |
| #define AUDDEC_DXI_MASK_SFT (0xff << 0) |
| |
| /* AUDDEC_PMU_CON0 */ |
| #define RG_AUDDACL_PWRUP_VAUDP18_SFT 0 |
| #define RG_AUDDACL_PWRUP_VAUDP18_MASK 0x1 |
| #define RG_AUDDACL_PWRUP_VAUDP18_MASK_SFT (0x1 << 0) |
| #define RG_AUDDACR_PWRUP_VAUDP18_SFT 1 |
| #define RG_AUDDACR_PWRUP_VAUDP18_MASK 0x1 |
| #define RG_AUDDACR_PWRUP_VAUDP18_MASK_SFT (0x1 << 1) |
| #define RG_AUDDACHS_PWRUP_VAUDP18_SFT 2 |
| #define RG_AUDDACHS_PWRUP_VAUDP18_MASK 0x1 |
| #define RG_AUDDACHS_PWRUP_VAUDP18_MASK_SFT (0x1 << 2) |
| #define RG_AUDDACLO_PWRUP_VAUDP18_SFT 3 |
| #define RG_AUDDACLO_PWRUP_VAUDP18_MASK 0x1 |
| #define RG_AUDDACLO_PWRUP_VAUDP18_MASK_SFT (0x1 << 3) |
| #define RG_AUDDACL_BIAS_PWRUP_VA32_SFT 4 |
| #define RG_AUDDACL_BIAS_PWRUP_VA32_MASK 0x1 |
| #define RG_AUDDACL_BIAS_PWRUP_VA32_MASK_SFT (0x1 << 4) |
| #define RG_AUDDACR_BIAS_PWRUP_VA32_SFT 5 |
| #define RG_AUDDACR_BIAS_PWRUP_VA32_MASK 0x1 |
| #define RG_AUDDACR_BIAS_PWRUP_VA32_MASK_SFT (0x1 << 5) |
| #define RG_AUDDACHS_BIAS_PWRUP_VA32_SFT 6 |
| #define RG_AUDDACHS_BIAS_PWRUP_VA32_MASK 0x1 |
| #define RG_AUDDACHS_BIAS_PWRUP_VA32_MASK_SFT (0x1 << 6) |
| #define RG_AUDDACLO_BIAS_PWRUP_VA32_SFT 7 |
| #define RG_AUDDACLO_BIAS_PWRUP_VA32_MASK 0x1 |
| #define RG_AUDDACLO_BIAS_PWRUP_VA32_MASK_SFT (0x1 << 7) |
| |
| /* AUDDEC_PMU_CON1 */ |
| #define RG_AUDDAC_L_RPWM_EN_VAUDP18_SFT 0 |
| #define RG_AUDDAC_L_RPWM_EN_VAUDP18_MASK 0x1 |
| #define RG_AUDDAC_L_RPWM_EN_VAUDP18_MASK_SFT (0x1 << 0) |
| #define RG_AUDDAC_R_RPWM_EN_VAUDP18_SFT 1 |
| #define RG_AUDDAC_R_RPWM_EN_VAUDP18_MASK 0x1 |
| #define RG_AUDDAC_R_RPWM_EN_VAUDP18_MASK_SFT (0x1 << 1) |
| #define RG_AUDDAC_IREF_LN_SEL_VA32_SFT 4 |
| #define RG_AUDDAC_IREF_LN_SEL_VA32_MASK 0x3 |
| #define RG_AUDDAC_IREF_LN_SEL_VA32_MASK_SFT (0x3 << 4) |
| #define RG_AUDDAC_IREF_LN_EN_VA32_SFT 6 |
| #define RG_AUDDAC_IREF_LN_EN_VA32_MASK 0x1 |
| #define RG_AUDDAC_IREF_LN_EN_VA32_MASK_SFT (0x1 << 6) |
| |
| /* AUDDEC_PMU_CON2 */ |
| #define RG_AUDDAC_ILOCAL_LN_SEL_VA32_SFT 0 |
| #define RG_AUDDAC_ILOCAL_LN_SEL_VA32_MASK 0x3 |
| #define RG_AUDDAC_ILOCAL_LN_SEL_VA32_MASK_SFT (0x3 << 0) |
| #define RG_AUDDAC_ILOCAL_LN_EN_VA32_SFT 2 |
| #define RG_AUDDAC_ILOCAL_LN_EN_VA32_MASK 0x1 |
| #define RG_AUDDAC_ILOCAL_LN_EN_VA32_MASK_SFT (0x1 << 2) |
| #define RG_AUDDAC_OPAMP_LN_EN_VA32_SFT 4 |
| #define RG_AUDDAC_OPAMP_LN_EN_VA32_MASK 0x1 |
| #define RG_AUDDAC_OPAMP_LN_EN_VA32_MASK_SFT (0x1 << 4) |
| |
| /* AUDDEC_PMU_CON3 */ |
| #define RG_AUDDAC_RSVD0_VAUDP18_SFT 0 |
| #define RG_AUDDAC_RSVD0_VAUDP18_MASK 0xff |
| #define RG_AUDDAC_RSVD0_VAUDP18_MASK_SFT (0xff << 0) |
| |
| /* AUDDEC_PMU_CON4 */ |
| #define RG_AUDHPLPWRUP_VAUDP18_SFT 0 |
| #define RG_AUDHPLPWRUP_VAUDP18_MASK 0x1 |
| #define RG_AUDHPLPWRUP_VAUDP18_MASK_SFT (0x1 << 0) |
| #define RG_AUDHPRPWRUP_VAUDP18_SFT 1 |
| #define RG_AUDHPRPWRUP_VAUDP18_MASK 0x1 |
| #define RG_AUDHPRPWRUP_VAUDP18_MASK_SFT (0x1 << 1) |
| #define RG_AUDHPLPWRUP_IBIAS_VAUDP18_SFT 2 |
| #define RG_AUDHPLPWRUP_IBIAS_VAUDP18_MASK 0x1 |
| #define RG_AUDHPLPWRUP_IBIAS_VAUDP18_MASK_SFT (0x1 << 2) |
| #define RG_AUDHPRPWRUP_IBIAS_VAUDP18_SFT 3 |
| #define RG_AUDHPRPWRUP_IBIAS_VAUDP18_MASK 0x1 |
| #define RG_AUDHPRPWRUP_IBIAS_VAUDP18_MASK_SFT (0x1 << 3) |
| #define RG_AUDHPLMUXINPUTSEL_VAUDP18_SFT 4 |
| #define RG_AUDHPLMUXINPUTSEL_VAUDP18_MASK 0x3 |
| #define RG_AUDHPLMUXINPUTSEL_VAUDP18_MASK_SFT (0x3 << 4) |
| #define RG_AUDHPRMUXINPUTSEL_VAUDP18_SFT 6 |
| #define RG_AUDHPRMUXINPUTSEL_VAUDP18_MASK 0x3 |
| #define RG_AUDHPRMUXINPUTSEL_VAUDP18_MASK_SFT (0x3 << 6) |
| |
| /* AUDDEC_PMU_CON5 */ |
| #define RG_AUDHPLSCDISABLE_VAUDP18_SFT 0 |
| #define RG_AUDHPLSCDISABLE_VAUDP18_MASK 0x1 |
| #define RG_AUDHPLSCDISABLE_VAUDP18_MASK_SFT (0x1 << 0) |
| #define RG_AUDHPRSCDISABLE_VAUDP18_SFT 1 |
| #define RG_AUDHPRSCDISABLE_VAUDP18_MASK 0x1 |
| #define RG_AUDHPRSCDISABLE_VAUDP18_MASK_SFT (0x1 << 1) |
| #define RG_AUDHPLBSCCURRENT_VAUDP18_SFT 2 |
| #define RG_AUDHPLBSCCURRENT_VAUDP18_MASK 0x1 |
| #define RG_AUDHPLBSCCURRENT_VAUDP18_MASK_SFT (0x1 << 2) |
| #define RG_AUDHPRBSCCURRENT_VAUDP18_SFT 3 |
| #define RG_AUDHPRBSCCURRENT_VAUDP18_MASK 0x1 |
| #define RG_AUDHPRBSCCURRENT_VAUDP18_MASK_SFT (0x1 << 3) |
| #define RG_AUDHPLOUTPWRUP_VAUDP18_SFT 4 |
| #define RG_AUDHPLOUTPWRUP_VAUDP18_MASK 0x1 |
| #define RG_AUDHPLOUTPWRUP_VAUDP18_MASK_SFT (0x1 << 4) |
| #define RG_AUDHPROUTPWRUP_VAUDP18_SFT 5 |
| #define RG_AUDHPROUTPWRUP_VAUDP18_MASK 0x1 |
| #define RG_AUDHPROUTPWRUP_VAUDP18_MASK_SFT (0x1 << 5) |
| #define RG_AUDHPLOUTAUXPWRUP_VAUDP18_SFT 6 |
| #define RG_AUDHPLOUTAUXPWRUP_VAUDP18_MASK 0x1 |
| #define RG_AUDHPLOUTAUXPWRUP_VAUDP18_MASK_SFT (0x1 << 6) |
| #define RG_AUDHPROUTAUXPWRUP_VAUDP18_SFT 7 |
| #define RG_AUDHPROUTAUXPWRUP_VAUDP18_MASK 0x1 |
| #define RG_AUDHPROUTAUXPWRUP_VAUDP18_MASK_SFT (0x1 << 7) |
| |
| /* AUDDEC_PMU_CON6 */ |
| #define RG_HPLAUXFBRSW_EN_VAUDP18_SFT 0 |
| #define RG_HPLAUXFBRSW_EN_VAUDP18_MASK 0x1 |
| #define RG_HPLAUXFBRSW_EN_VAUDP18_MASK_SFT (0x1 << 0) |
| #define RG_HPRAUXFBRSW_EN_VAUDP18_SFT 1 |
| #define RG_HPRAUXFBRSW_EN_VAUDP18_MASK 0x1 |
| #define RG_HPRAUXFBRSW_EN_VAUDP18_MASK_SFT (0x1 << 1) |
| #define RG_HPLSHORT2HPLAUX_EN_VAUDP18_SFT 2 |
| #define RG_HPLSHORT2HPLAUX_EN_VAUDP18_MASK 0x1 |
| #define RG_HPLSHORT2HPLAUX_EN_VAUDP18_MASK_SFT (0x1 << 2) |
| #define RG_HPRSHORT2HPRAUX_EN_VAUDP18_SFT 3 |
| #define RG_HPRSHORT2HPRAUX_EN_VAUDP18_MASK 0x1 |
| #define RG_HPRSHORT2HPRAUX_EN_VAUDP18_MASK_SFT (0x1 << 3) |
| #define RG_HPLOUTPUTSTBENH_VAUDP18_SFT 4 |
| #define RG_HPLOUTPUTSTBENH_VAUDP18_MASK 0x7 |
| #define RG_HPLOUTPUTSTBENH_VAUDP18_MASK_SFT (0x7 << 4) |
| |
| /* AUDDEC_PMU_CON7 */ |
| #define RG_HPROUTPUTSTBENH_VAUDP18_SFT 0 |
| #define RG_HPROUTPUTSTBENH_VAUDP18_MASK 0x7 |
| #define RG_HPROUTPUTSTBENH_VAUDP18_MASK_SFT (0x7 << 0) |
| #define RG_HPLMUTE_EN_VAUDP18_SFT 4 |
| #define RG_HPLMUTE_EN_VAUDP18_MASK 0x1 |
| #define RG_HPLMUTE_EN_VAUDP18_MASK_SFT (0x1 << 4) |
| #define RG_HPRMUTE_EN_VAUDP18_SFT 5 |
| #define RG_HPRMUTE_EN_VAUDP18_MASK 0x1 |
| #define RG_HPRMUTE_EN_VAUDP18_MASK_SFT (0x1 << 5) |
| #define RG_AUDHPLAUXCM_EN_VAUDP18_SFT 6 |
| #define RG_AUDHPLAUXCM_EN_VAUDP18_MASK 0x1 |
| #define RG_AUDHPLAUXCM_EN_VAUDP18_MASK_SFT (0x1 << 6) |
| #define RG_AUDHPRAUXCM_EN_VAUDP18_SFT 7 |
| #define RG_AUDHPRAUXCM_EN_VAUDP18_MASK 0x1 |
| #define RG_AUDHPRAUXCM_EN_VAUDP18_MASK_SFT (0x1 << 7) |
| |
| /* AUDDEC_PMU_CON8 */ |
| #define RG_AUDHPLAUXGAIN_VAUDP18_SFT 0 |
| #define RG_AUDHPLAUXGAIN_VAUDP18_MASK 0xf |
| #define RG_AUDHPLAUXGAIN_VAUDP18_MASK_SFT (0xf << 0) |
| #define RG_AUDHPRAUXGAIN_VAUDP18_SFT 4 |
| #define RG_AUDHPRAUXGAIN_VAUDP18_MASK 0xf |
| #define RG_AUDHPRAUXGAIN_VAUDP18_MASK_SFT (0xf << 4) |
| |
| /* AUDDEC_PMU_CON9 */ |
| #define RG_AUDHPLMAINCM2_EN_VAUDP18_SFT 0 |
| #define RG_AUDHPLMAINCM2_EN_VAUDP18_MASK 0x1 |
| #define RG_AUDHPLMAINCM2_EN_VAUDP18_MASK_SFT (0x1 << 0) |
| #define RG_AUDHPRMAINCM2_EN_VAUDP18_SFT 1 |
| #define RG_AUDHPRMAINCM2_EN_VAUDP18_MASK 0x1 |
| #define RG_AUDHPRMAINCM2_EN_VAUDP18_MASK_SFT (0x1 << 1) |
| #define RG_AUDHPLCMFB_RNWSEL_VAUDP18_SFT 2 |
| #define RG_AUDHPLCMFB_RNWSEL_VAUDP18_MASK 0x1 |
| #define RG_AUDHPLCMFB_RNWSEL_VAUDP18_MASK_SFT (0x1 << 2) |
| #define RG_AUDHPRCMFB_RNWSEL_VAUDP18_SFT 3 |
| #define RG_AUDHPRCMFB_RNWSEL_VAUDP18_MASK 0x1 |
| #define RG_AUDHPRCMFB_RNWSEL_VAUDP18_MASK_SFT (0x1 << 3) |
| #define RG_AUDHPLHPFB_RNWSEL_VAUDP18_SFT 4 |
| #define RG_AUDHPLHPFB_RNWSEL_VAUDP18_MASK 0x1 |
| #define RG_AUDHPLHPFB_RNWSEL_VAUDP18_MASK_SFT (0x1 << 4) |
| #define RG_AUDHPRHPFB_RNWSEL_VAUDP18_SFT 5 |
| #define RG_AUDHPRHPFB_RNWSEL_VAUDP18_MASK 0x1 |
| #define RG_AUDHPRHPFB_RNWSEL_VAUDP18_MASK_SFT (0x1 << 5) |
| #define RG_HPLHDRM_PFL_EN_VAUDP18_SFT 6 |
| #define RG_HPLHDRM_PFL_EN_VAUDP18_MASK 0x1 |
| #define RG_HPLHDRM_PFL_EN_VAUDP18_MASK_SFT (0x1 << 6) |
| #define RG_HPRHDRM_PFL_EN_VAUDP18_SFT 7 |
| #define RG_HPRHDRM_PFL_EN_VAUDP18_MASK 0x1 |
| #define RG_HPRHDRM_PFL_EN_VAUDP18_MASK_SFT (0x1 << 7) |
| |
| /* AUDDEC_PMU_CON10 */ |
| #define RG_HPLHDRMSW_ST_EN_VAUDP18_SFT 0 |
| #define RG_HPLHDRMSW_ST_EN_VAUDP18_MASK 0x1 |
| #define RG_HPLHDRMSW_ST_EN_VAUDP18_MASK_SFT (0x1 << 0) |
| #define RG_HPRHDRMSW_ST_EN_VAUDP18_SFT 1 |
| #define RG_HPRHDRMSW_ST_EN_VAUDP18_MASK 0x1 |
| #define RG_HPRHDRMSW_ST_EN_VAUDP18_MASK_SFT (0x1 << 1) |
| #define RG_AUDHPSTARTUP_VAUDP18_SFT 2 |
| #define RG_AUDHPSTARTUP_VAUDP18_MASK 0x1 |
| #define RG_AUDHPSTARTUP_VAUDP18_MASK_SFT (0x1 << 2) |
| #define RG_AUDREFN_DERES_EN_VAUDP18_SFT 3 |
| #define RG_AUDREFN_DERES_EN_VAUDP18_MASK 0x1 |
| #define RG_AUDREFN_DERES_EN_VAUDP18_MASK_SFT (0x1 << 3) |
| #define RG_HPINPUTSTBENH_VAUDP18_SFT 4 |
| #define RG_HPINPUTSTBENH_VAUDP18_MASK 0x1 |
| #define RG_HPINPUTSTBENH_VAUDP18_MASK_SFT (0x1 << 4) |
| #define RG_HPINPUTRESET0_VAUDP18_SFT 5 |
| #define RG_HPINPUTRESET0_VAUDP18_MASK 0x1 |
| #define RG_HPINPUTRESET0_VAUDP18_MASK_SFT (0x1 << 5) |
| #define RG_HPOUTPUTRESET0_VAUDP18_SFT 6 |
| #define RG_HPOUTPUTRESET0_VAUDP18_MASK 0x1 |
| #define RG_HPOUTPUTRESET0_VAUDP18_MASK_SFT (0x1 << 6) |
| |
| /* AUDDEC_PMU_CON11 */ |
| #define RG_HPPSHORT2VCM_VAUDP18_SFT 0 |
| #define RG_HPPSHORT2VCM_VAUDP18_MASK 0x7 |
| #define RG_HPPSHORT2VCM_VAUDP18_MASK_SFT (0x7 << 0) |
| #define RG_AUDHPTRIM_EN_VAUDP18_SFT 4 |
| #define RG_AUDHPTRIM_EN_VAUDP18_MASK 0x1 |
| #define RG_AUDHPTRIM_EN_VAUDP18_MASK_SFT (0x1 << 4) |
| |
| /* AUDDEC_PMU_CON12 */ |
| #define RG_AUDHPLFINETRIM_VAUDP18_SFT 0 |
| #define RG_AUDHPLFINETRIM_VAUDP18_MASK 0x7 |
| #define RG_AUDHPLFINETRIM_VAUDP18_MASK_SFT (0x7 << 0) |
| #define RG_AUDHPLTRIM_VAUDP18_SFT 3 |
| #define RG_AUDHPLTRIM_VAUDP18_MASK 0x1f |
| #define RG_AUDHPLTRIM_VAUDP18_MASK_SFT (0x1f << 3) |
| |
| /* AUDDEC_PMU_CON13 */ |
| #define RG_AUDHPRFINETRIM_VAUDP18_SFT 0 |
| #define RG_AUDHPRFINETRIM_VAUDP18_MASK 0x7 |
| #define RG_AUDHPRFINETRIM_VAUDP18_MASK_SFT (0x7 << 0) |
| #define RG_AUDHPRTRIM_VAUDP18_SFT 3 |
| #define RG_AUDHPRTRIM_VAUDP18_MASK 0x1f |
| #define RG_AUDHPRTRIM_VAUDP18_MASK_SFT (0x1f << 3) |
| |
| /* AUDDEC_PMU_CON14 */ |
| #define RG_AUDHPDIFFINPBIASADJ_VAUDP18_SFT 0 |
| #define RG_AUDHPDIFFINPBIASADJ_VAUDP18_MASK 0x3 |
| #define RG_AUDHPDIFFINPBIASADJ_VAUDP18_MASK_SFT (0x3 << 0) |
| #define RG_AUDHPDAMP_ADJ_VAUDP18_SFT 4 |
| #define RG_AUDHPDAMP_ADJ_VAUDP18_MASK 0x3 |
| #define RG_AUDHPDAMP_ADJ_VAUDP18_MASK_SFT (0x3 << 4) |
| |
| /* AUDDEC_PMU_CON15 */ |
| #define RG_AUDHPDAMP_EN_VAUDP18_SFT 0 |
| #define RG_AUDHPDAMP_EN_VAUDP18_MASK 0x1 |
| #define RG_AUDHPDAMP_EN_VAUDP18_MASK_SFT (0x1 << 0) |
| #define RG_DAMP2ND_EN_VAUDP18_SFT 1 |
| #define RG_DAMP2ND_EN_VAUDP18_MASK 0x1 |
| #define RG_DAMP2ND_EN_VAUDP18_MASK_SFT (0x1 << 1) |
| #define RG_HPMUXST_EN_VAUDP18_SFT 2 |
| #define RG_HPMUXST_EN_VAUDP18_MASK 0x1 |
| #define RG_HPMUXST_EN_VAUDP18_MASK_SFT (0x1 << 2) |
| #define RG_AUDHPHFCOMPBUFGAINSEL_VAUDP18_SFT 4 |
| #define RG_AUDHPHFCOMPBUFGAINSEL_VAUDP18_MASK 0x3 |
| #define RG_AUDHPHFCOMPBUFGAINSEL_VAUDP18_MASK_SFT (0x3 << 4) |
| |
| /* AUDDEC_PMU_CON16 */ |
| #define RG_NREGPRESET_EN_VAUDP18_SFT 0 |
| #define RG_NREGPRESET_EN_VAUDP18_MASK 0x1 |
| #define RG_NREGPRESET_EN_VAUDP18_MASK_SFT (0x1 << 0) |
| #define RG_AUDHPHIFISWST_EN_VAUDP18_SFT 1 |
| #define RG_AUDHPHIFISWST_EN_VAUDP18_MASK 0x1 |
| #define RG_AUDHPHIFISWST_EN_VAUDP18_MASK_SFT (0x1 << 1) |
| #define RG_AUDHPHFOP_EN_VAUDP18_SFT 2 |
| #define RG_AUDHPHFOP_EN_VAUDP18_MASK 0x1 |
| #define RG_AUDHPHFOP_EN_VAUDP18_MASK_SFT (0x1 << 2) |
| #define RG_AUDHPMAINCM_COMP_EN_VAUDP18_SFT 3 |
| #define RG_AUDHPMAINCM_COMP_EN_VAUDP18_MASK 0x1 |
| #define RG_AUDHPMAINCM_COMP_EN_VAUDP18_MASK_SFT (0x1 << 3) |
| |
| /* AUDDEC_PMU_CON17 */ |
| #define RG_HPL_LNATT2TRIM_MUX_VAUDP18_SFT 0 |
| #define RG_HPL_LNATT2TRIM_MUX_VAUDP18_MASK 0x7 |
| #define RG_HPL_LNATT2TRIM_MUX_VAUDP18_MASK_SFT (0x7 << 0) |
| #define RG_HPR_LNATT2TRIM_MUX_VAUDP18_SFT 4 |
| #define RG_HPR_LNATT2TRIM_MUX_VAUDP18_MASK 0x7 |
| #define RG_HPR_LNATT2TRIM_MUX_VAUDP18_MASK_SFT (0x7 << 4) |
| |
| /* AUDDEC_PMU_CON18 */ |
| #define RG_HPL_HPDET2LNATT_MUX_VAUDP18_SFT 0 |
| #define RG_HPL_HPDET2LNATT_MUX_VAUDP18_MASK 0x7 |
| #define RG_HPL_HPDET2LNATT_MUX_VAUDP18_MASK_SFT (0x7 << 0) |
| #define RG_HPR_HPDET2LNATT_MUX_VAUDP18_SFT 4 |
| #define RG_HPR_HPDET2LNATT_MUX_VAUDP18_MASK 0x7 |
| #define RG_HPR_HPDET2LNATT_MUX_VAUDP18_MASK_SFT (0x7 << 4) |
| |
| /* AUDDEC_PMU_CON19 */ |
| #define RG_AUDHP_RSVD0_VAUDP18_SFT 0 |
| #define RG_AUDHP_RSVD0_VAUDP18_MASK 0xff |
| #define RG_AUDHP_RSVD0_VAUDP18_MASK_SFT (0xff << 0) |
| |
| /* AUDDEC_PMU_CON20 */ |
| #define RG_AUDHSPWRUP_VAUDP18_SFT 0 |
| #define RG_AUDHSPWRUP_VAUDP18_MASK 0x1 |
| #define RG_AUDHSPWRUP_VAUDP18_MASK_SFT (0x1 << 0) |
| #define RG_AUDHSPWRUP_IBIAS_VAUDP18_SFT 1 |
| #define RG_AUDHSPWRUP_IBIAS_VAUDP18_MASK 0x1 |
| #define RG_AUDHSPWRUP_IBIAS_VAUDP18_MASK_SFT (0x1 << 1) |
| #define RG_AUDHSSTARTUP_VAUDP18_SFT 2 |
| #define RG_AUDHSSTARTUP_VAUDP18_MASK 0x1 |
| #define RG_AUDHSSTARTUP_VAUDP18_MASK_SFT (0x1 << 2) |
| #define RG_AUDHSSCDISABLE_VAUDP18_SFT 3 |
| #define RG_AUDHSSCDISABLE_VAUDP18_MASK 0x1 |
| #define RG_AUDHSSCDISABLE_VAUDP18_MASK_SFT (0x1 << 3) |
| #define RG_AUDHSBSCCURRENT_VAUDP18_SFT 4 |
| #define RG_AUDHSBSCCURRENT_VAUDP18_MASK 0x1 |
| #define RG_AUDHSBSCCURRENT_VAUDP18_MASK_SFT (0x1 << 4) |
| #define RG_HSOUT_SHORT2VCM_VAUDP18_SFT 5 |
| #define RG_HSOUT_SHORT2VCM_VAUDP18_MASK 0x1 |
| #define RG_HSOUT_SHORT2VCM_VAUDP18_MASK_SFT (0x1 << 5) |
| #define RG_AUDHSTRIM_EN_VAUDP18_SFT 6 |
| #define RG_AUDHSTRIM_EN_VAUDP18_MASK 0x1 |
| #define RG_AUDHSTRIM_EN_VAUDP18_MASK_SFT (0x1 << 6) |
| |
| /* AUDDEC_PMU_CON21 */ |
| #define RG_AUDHSTRIM_VAUDP18_SFT 0 |
| #define RG_AUDHSTRIM_VAUDP18_MASK 0x1f |
| #define RG_AUDHSTRIM_VAUDP18_MASK_SFT (0x1f << 0) |
| #define RG_AUDHSFINETRIM_VAUDP18_SFT 5 |
| #define RG_AUDHSFINETRIM_VAUDP18_MASK 0x7 |
| #define RG_AUDHSFINETRIM_VAUDP18_MASK_SFT (0x7 << 5) |
| |
| /* AUDDEC_PMU_CON22 */ |
| #define RG_AUDHSMUXINPUTSEL_VAUDP18_SFT 0 |
| #define RG_AUDHSMUXINPUTSEL_VAUDP18_MASK 0x3 |
| #define RG_AUDHSMUXINPUTSEL_VAUDP18_MASK_SFT (0x3 << 0) |
| #define RG_HSINPUTRESET0_VAUDP18_SFT 2 |
| #define RG_HSINPUTRESET0_VAUDP18_MASK 0x1 |
| #define RG_HSINPUTRESET0_VAUDP18_MASK_SFT (0x1 << 2) |
| #define RG_HSOUTPUTRESET0_VAUDP18_SFT 3 |
| #define RG_HSOUTPUTRESET0_VAUDP18_MASK 0x1 |
| #define RG_HSOUTPUTRESET0_VAUDP18_MASK_SFT (0x1 << 3) |
| #define RG_HSINPUTSTBENH_VAUDP18_SFT 4 |
| #define RG_HSINPUTSTBENH_VAUDP18_MASK 0x1 |
| #define RG_HSINPUTSTBENH_VAUDP18_MASK_SFT (0x1 << 4) |
| #define RG_AUDHSCMFB_RNWSEL_VAUDP18_SFT 5 |
| #define RG_AUDHSCMFB_RNWSEL_VAUDP18_MASK 0x1 |
| #define RG_AUDHSCMFB_RNWSEL_VAUDP18_MASK_SFT (0x1 << 5) |
| #define RG_AUDHSDACTEST_VAUDP18_SFT 6 |
| #define RG_AUDHSDACTEST_VAUDP18_MASK 0x1 |
| #define RG_AUDHSDACTEST_VAUDP18_MASK_SFT (0x1 << 6) |
| #define RG_AUDHSGM2BOOST_EN_VAUDP18_SFT 7 |
| #define RG_AUDHSGM2BOOST_EN_VAUDP18_MASK 0x1 |
| #define RG_AUDHSGM2BOOST_EN_VAUDP18_MASK_SFT (0x1 << 7) |
| |
| /* AUDDEC_PMU_CON23 */ |
| #define RG_HSOUTPUTSTBENH_VAUDP18_SFT 0 |
| #define RG_HSOUTPUTSTBENH_VAUDP18_MASK 0x1 |
| #define RG_HSOUTPUTSTBENH_VAUDP18_MASK_SFT (0x1 << 0) |
| #define RG_HSOUTSTGCTRL_VAUDP18_SFT 1 |
| #define RG_HSOUTSTGCTRL_VAUDP18_MASK 0x7 |
| #define RG_HSOUTSTGCTRL_VAUDP18_MASK_SFT (0x7 << 1) |
| |
| /* AUDDEC_PMU_CON24 */ |
| #define RG_AUDLOPWRUP_VAUDP18_SFT 0 |
| #define RG_AUDLOPWRUP_VAUDP18_MASK 0x1 |
| #define RG_AUDLOPWRUP_VAUDP18_MASK_SFT (0x1 << 0) |
| #define RG_AUDLOPWRUP_IBIAS_VAUDP18_SFT 1 |
| #define RG_AUDLOPWRUP_IBIAS_VAUDP18_MASK 0x1 |
| #define RG_AUDLOPWRUP_IBIAS_VAUDP18_MASK_SFT (0x1 << 1) |
| #define RG_AUDLOSTARTUP_VAUDP18_SFT 2 |
| #define RG_AUDLOSTARTUP_VAUDP18_MASK 0x1 |
| #define RG_AUDLOSTARTUP_VAUDP18_MASK_SFT (0x1 << 2) |
| #define RG_AUDLOSCDISABLE_VAUDP18_SFT 3 |
| #define RG_AUDLOSCDISABLE_VAUDP18_MASK 0x1 |
| #define RG_AUDLOSCDISABLE_VAUDP18_MASK_SFT (0x1 << 3) |
| #define RG_AUDLOBSCCURRENT_VAUDP18_SFT 4 |
| #define RG_AUDLOBSCCURRENT_VAUDP18_MASK 0x1 |
| #define RG_AUDLOBSCCURRENT_VAUDP18_MASK_SFT (0x1 << 4) |
| #define RG_LOOUT_SHORT2VCM_VAUDP18_SFT 5 |
| #define RG_LOOUT_SHORT2VCM_VAUDP18_MASK 0x1 |
| #define RG_LOOUT_SHORT2VCM_VAUDP18_MASK_SFT (0x1 << 5) |
| #define RG_AUDLOTRIM_EN_VAUDP18_SFT 6 |
| #define RG_AUDLOTRIM_EN_VAUDP18_MASK 0x1 |
| #define RG_AUDLOTRIM_EN_VAUDP18_MASK_SFT (0x1 << 6) |
| |
| /* AUDDEC_PMU_CON25 */ |
| #define RG_AUDLOTRIM_VAUDP18_SFT 0 |
| #define RG_AUDLOTRIM_VAUDP18_MASK 0x1f |
| #define RG_AUDLOTRIM_VAUDP18_MASK_SFT (0x1f << 0) |
| #define RG_AUDLOFINETRIM_VAUDP18_SFT 5 |
| #define RG_AUDLOFINETRIM_VAUDP18_MASK 0x7 |
| #define RG_AUDLOFINETRIM_VAUDP18_MASK_SFT (0x7 << 5) |
| |
| /* AUDDEC_PMU_CON26 */ |
| #define RG_AUDLOMUXINPUTSEL_VAUDP18_SFT 0 |
| #define RG_AUDLOMUXINPUTSEL_VAUDP18_MASK 0x3 |
| #define RG_AUDLOMUXINPUTSEL_VAUDP18_MASK_SFT (0x3 << 0) |
| #define RG_LOINPUTRESET0_VAUDP18_SFT 2 |
| #define RG_LOINPUTRESET0_VAUDP18_MASK 0x1 |
| #define RG_LOINPUTRESET0_VAUDP18_MASK_SFT (0x1 << 2) |
| #define RG_LOOUTPUTRESET0_VAUDP18_SFT 3 |
| #define RG_LOOUTPUTRESET0_VAUDP18_MASK 0x1 |
| #define RG_LOOUTPUTRESET0_VAUDP18_MASK_SFT (0x1 << 3) |
| #define RG_LOINPUTSTBENH_VAUDP18_SFT 4 |
| #define RG_LOINPUTSTBENH_VAUDP18_MASK 0x1 |
| #define RG_LOINPUTSTBENH_VAUDP18_MASK_SFT (0x1 << 4) |
| #define RG_AUDLOCMFB_RNWSEL_VAUDP18_SFT 5 |
| #define RG_AUDLOCMFB_RNWSEL_VAUDP18_MASK 0x1 |
| #define RG_AUDLOCMFB_RNWSEL_VAUDP18_MASK_SFT (0x1 << 5) |
| #define RG_AUDLODACTEST_VAUDP18_SFT 6 |
| #define RG_AUDLODACTEST_VAUDP18_MASK 0x1 |
| #define RG_AUDLODACTEST_VAUDP18_MASK_SFT (0x1 << 6) |
| #define RG_AUDLOGM2BOOST_EN_VAUDP18_SFT 7 |
| #define RG_AUDLOGM2BOOST_EN_VAUDP18_MASK 0x1 |
| #define RG_AUDLOGM2BOOST_EN_VAUDP18_MASK_SFT (0x1 << 7) |
| |
| /* AUDDEC_PMU_CON27 */ |
| #define RG_LOOUTPUTSTBENH_VAUDP18_SFT 0 |
| #define RG_LOOUTPUTSTBENH_VAUDP18_MASK 0x1 |
| #define RG_LOOUTPUTSTBENH_VAUDP18_MASK_SFT (0x1 << 0) |
| |
| /* AUDDEC_PMU_CON28 */ |
| #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP18_SFT 0 |
| #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP18_MASK 0xf |
| #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP18_MASK_SFT (0xf << 0) |
| #define RG_AUDTRIMBUF_GAINSEL_VAUDP18_SFT 4 |
| #define RG_AUDTRIMBUF_GAINSEL_VAUDP18_MASK 0x3 |
| #define RG_AUDTRIMBUF_GAINSEL_VAUDP18_MASK_SFT (0x3 << 4) |
| #define RG_AUDTRIMBUF_EN_VAUDP18_SFT 6 |
| #define RG_AUDTRIMBUF_EN_VAUDP18_MASK 0x1 |
| #define RG_AUDTRIMBUF_EN_VAUDP18_MASK_SFT (0x1 << 6) |
| |
| /* AUDDEC_PMU_CON29 */ |
| #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP18_SFT 0 |
| #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP18_MASK 0x3 |
| #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP18_MASK_SFT (0x3 << 0) |
| #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP18_SFT 2 |
| #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP18_MASK 0x7 |
| #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP18_MASK_SFT (0x7 << 2) |
| #define RG_AUDHPSPKDET_EN_VAUDP18_SFT 5 |
| #define RG_AUDHPSPKDET_EN_VAUDP18_MASK 0x1 |
| #define RG_AUDHPSPKDET_EN_VAUDP18_MASK_SFT (0x1 << 5) |
| |
| /* AUDDEC_PMU_CON30 */ |
| #define RG_AUDBIASADJ_0_HP_VAUDP18_SFT 0 |
| #define RG_AUDBIASADJ_0_HP_VAUDP18_MASK 0x7 |
| #define RG_AUDBIASADJ_0_HP_VAUDP18_MASK_SFT (0x7 << 0) |
| #define RG_AUDBIASADJ_0_HS_VAUDP18_SFT 4 |
| #define RG_AUDBIASADJ_0_HS_VAUDP18_MASK 0x7 |
| #define RG_AUDBIASADJ_0_HS_VAUDP18_MASK_SFT (0x7 << 4) |
| |
| /* AUDDEC_PMU_CON31 */ |
| #define RG_AUDBIASADJ_0_LO_VAUDP18_SFT 0 |
| #define RG_AUDBIASADJ_0_LO_VAUDP18_MASK 0x7 |
| #define RG_AUDBIASADJ_0_LO_VAUDP18_MASK_SFT (0x7 << 0) |
| #define RG_AUDIBIASPWRDN_VAUDP18_SFT 4 |
| #define RG_AUDIBIASPWRDN_VAUDP18_MASK 0x1 |
| #define RG_AUDIBIASPWRDN_VAUDP18_MASK_SFT (0x1 << 4) |
| |
| /* AUDDEC_PMU_CON32 */ |
| #define RG_AUDBIASADJ_1_VAUDP18_SFT 0 |
| #define RG_AUDBIASADJ_1_VAUDP18_MASK 0xff |
| #define RG_AUDBIASADJ_1_VAUDP18_MASK_SFT (0xff << 0) |
| |
| /* AUDDEC_PMU_CON33 */ |
| #define RG_AUDGLB_NVREG_DACSW_VREF_SEL_VA32_SFT 0 |
| #define RG_AUDGLB_NVREG_DACSW_VREF_SEL_VA32_MASK 0x7 |
| #define RG_AUDGLB_NVREG_DACSW_VREF_SEL_VA32_MASK_SFT (0x7 << 0) |
| #define RG_AUDGLB_NVREG_HCBUF_VREF_SEL_VA32_SFT 4 |
| #define RG_AUDGLB_NVREG_HCBUF_VREF_SEL_VA32_MASK 0x7 |
| #define RG_AUDGLB_NVREG_HCBUF_VREF_SEL_VA32_MASK_SFT (0x7 << 4) |
| |
| /* AUDDEC_PMU_CON34 */ |
| #define RG_AUDGLB_NVREG_LCBUF_VREF_SEL_VA32_SFT 0 |
| #define RG_AUDGLB_NVREG_LCBUF_VREF_SEL_VA32_MASK 0x7 |
| #define RG_AUDGLB_NVREG_LCBUF_VREF_SEL_VA32_MASK_SFT (0x7 << 0) |
| #define RG_AUDGLB_PWRDN_VA32_SFT 4 |
| #define RG_AUDGLB_PWRDN_VA32_MASK 0x1 |
| #define RG_AUDGLB_PWRDN_VA32_MASK_SFT (0x1 << 4) |
| |
| /* AUDDEC_PMU_CON35 */ |
| #define RG_LCLDO_BUF_VREF_EN_VA32_SFT 0 |
| #define RG_LCLDO_BUF_VREF_EN_VA32_MASK 0x1 |
| #define RG_LCLDO_BUF_VREF_EN_VA32_MASK_SFT (0x1 << 0) |
| #define RG_HCLDO_BUF_VREF_EN_VA32_SFT 1 |
| #define RG_HCLDO_BUF_VREF_EN_VA32_MASK 0x1 |
| #define RG_HCLDO_BUF_VREF_EN_VA32_MASK_SFT (0x1 << 1) |
| #define RG_LCLDO_DACSW_VREF_EN_VA32_SFT 2 |
| #define RG_LCLDO_DACSW_VREF_EN_VA32_MASK 0x1 |
| #define RG_LCLDO_DACSW_VREF_EN_VA32_MASK_SFT (0x1 << 2) |
| #define RG_LCLDO_BUF_VREF_SEL_VA32_SFT 4 |
| #define RG_LCLDO_BUF_VREF_SEL_VA32_MASK 0x7 |
| #define RG_LCLDO_BUF_VREF_SEL_VA32_MASK_SFT (0x7 << 4) |
| |
| /* AUDDEC_PMU_CON36 */ |
| #define RG_HCLDO_BUF_VREF_SEL_VA32_SFT 0 |
| #define RG_HCLDO_BUF_VREF_SEL_VA32_MASK 0x7 |
| #define RG_HCLDO_BUF_VREF_SEL_VA32_MASK_SFT (0x7 << 0) |
| #define RG_LCLDO_DACSW_VREF_SEL_VA32_SFT 4 |
| #define RG_LCLDO_DACSW_VREF_SEL_VA32_MASK 0x7 |
| #define RG_LCLDO_DACSW_VREF_SEL_VA32_MASK_SFT (0x7 << 4) |
| |
| /* AUDDEC_PMU_CON37 */ |
| #define RG_LCLDO_BUF_L_EN_VA18_SFT 0 |
| #define RG_LCLDO_BUF_L_EN_VA18_MASK 0x1 |
| #define RG_LCLDO_BUF_L_EN_VA18_MASK_SFT (0x1 << 0) |
| #define RG_LCLDO_BUF_R_EN_VA18_SFT 1 |
| #define RG_LCLDO_BUF_R_EN_VA18_MASK 0x1 |
| #define RG_LCLDO_BUF_R_EN_VA18_MASK_SFT (0x1 << 1) |
| #define RG_HCLDO_BUF_L_EN_VA18_SFT 2 |
| #define RG_HCLDO_BUF_L_EN_VA18_MASK 0x1 |
| #define RG_HCLDO_BUF_L_EN_VA18_MASK_SFT (0x1 << 2) |
| #define RG_HCLDO_BUF_R_EN_VA18_SFT 3 |
| #define RG_HCLDO_BUF_R_EN_VA18_MASK 0x1 |
| #define RG_HCLDO_BUF_R_EN_VA18_MASK_SFT (0x1 << 3) |
| #define RG_LCLDO_DACSW_L_EN_VA18_SFT 4 |
| #define RG_LCLDO_DACSW_L_EN_VA18_MASK 0x1 |
| #define RG_LCLDO_DACSW_L_EN_VA18_MASK_SFT (0x1 << 4) |
| #define RG_LCLDO_DACSW_R_EN_VA18_SFT 5 |
| #define RG_LCLDO_DACSW_R_EN_VA18_MASK 0x1 |
| #define RG_LCLDO_DACSW_R_EN_VA18_MASK_SFT (0x1 << 5) |
| #define RG_LCLDO_BUF_L_PDDIS_EN_VA18_SFT 6 |
| #define RG_LCLDO_BUF_L_PDDIS_EN_VA18_MASK 0x1 |
| #define RG_LCLDO_BUF_L_PDDIS_EN_VA18_MASK_SFT (0x1 << 6) |
| #define RG_LCLDO_BUF_R_PDDIS_EN_VA18_SFT 7 |
| #define RG_LCLDO_BUF_R_PDDIS_EN_VA18_MASK 0x1 |
| #define RG_LCLDO_BUF_R_PDDIS_EN_VA18_MASK_SFT (0x1 << 7) |
| |
| /* AUDDEC_PMU_CON38 */ |
| #define RG_HCLDO_BUF_L_PDDIS_EN_VA18_SFT 0 |
| #define RG_HCLDO_BUF_L_PDDIS_EN_VA18_MASK 0x1 |
| #define RG_HCLDO_BUF_L_PDDIS_EN_VA18_MASK_SFT (0x1 << 0) |
| #define RG_HCLDO_BUF_R_PDDIS_EN_VA18_SFT 1 |
| #define RG_HCLDO_BUF_R_PDDIS_EN_VA18_MASK 0x1 |
| #define RG_HCLDO_BUF_R_PDDIS_EN_VA18_MASK_SFT (0x1 << 1) |
| #define RG_LCLDO_DACSW_L_PDDIS_EN_VA18_SFT 2 |
| #define RG_LCLDO_DACSW_L_PDDIS_EN_VA18_MASK 0x1 |
| #define RG_LCLDO_DACSW_L_PDDIS_EN_VA18_MASK_SFT (0x1 << 2) |
| #define RG_LCLDO_DACSW_R_PDDIS_EN_VA18_SFT 3 |
| #define RG_LCLDO_DACSW_R_PDDIS_EN_VA18_MASK 0x1 |
| #define RG_LCLDO_DACSW_R_PDDIS_EN_VA18_MASK_SFT (0x1 << 3) |
| |
| /* AUDDEC_PMU_CON39 */ |
| #define RG_LCLDO_BUF_L_REMOTE_SENSE_VA18_SFT 0 |
| #define RG_LCLDO_BUF_L_REMOTE_SENSE_VA18_MASK 0x1 |
| #define RG_LCLDO_BUF_L_REMOTE_SENSE_VA18_MASK_SFT (0x1 << 0) |
| #define RG_LCLDO_BUF_R_REMOTE_SENSE_VA18_SFT 1 |
| #define RG_LCLDO_BUF_R_REMOTE_SENSE_VA18_MASK 0x1 |
| #define RG_LCLDO_BUF_R_REMOTE_SENSE_VA18_MASK_SFT (0x1 << 1) |
| #define RG_HCLDO_BUF_L_REMOTE_SENSE_VA18_SFT 2 |
| #define RG_HCLDO_BUF_L_REMOTE_SENSE_VA18_MASK 0x1 |
| #define RG_HCLDO_BUF_L_REMOTE_SENSE_VA18_MASK_SFT (0x1 << 2) |
| #define RG_HCLDO_BUF_R_REMOTE_SENSE_VA18_SFT 3 |
| #define RG_HCLDO_BUF_R_REMOTE_SENSE_VA18_MASK 0x1 |
| #define RG_HCLDO_BUF_R_REMOTE_SENSE_VA18_MASK_SFT (0x1 << 3) |
| #define RG_LCLDO_DACSW_L_REMOTE_SENSE_VA18_SFT 4 |
| #define RG_LCLDO_DACSW_L_REMOTE_SENSE_VA18_MASK 0x1 |
| #define RG_LCLDO_DACSW_L_REMOTE_SENSE_VA18_MASK_SFT (0x1 << 4) |
| #define RG_LCLDO_DACSW_R_REMOTE_SENSE_VA18_SFT 5 |
| #define RG_LCLDO_DACSW_R_REMOTE_SENSE_VA18_MASK 0x1 |
| #define RG_LCLDO_DACSW_R_REMOTE_SENSE_VA18_MASK_SFT (0x1 << 5) |
| #define RG_LCLDO_BUF_L_SC_EN_VA18_SFT 6 |
| #define RG_LCLDO_BUF_L_SC_EN_VA18_MASK 0x1 |
| #define RG_LCLDO_BUF_L_SC_EN_VA18_MASK_SFT (0x1 << 6) |
| #define RG_LCLDO_BUF_R_SC_EN_VA18_SFT 7 |
| #define RG_LCLDO_BUF_R_SC_EN_VA18_MASK 0x1 |
| #define RG_LCLDO_BUF_R_SC_EN_VA18_MASK_SFT (0x1 << 7) |
| |
| /* AUDDEC_PMU_CON40 */ |
| #define RG_HCLDO_BUF_L_SC_EN_VA18_SFT 0 |
| #define RG_HCLDO_BUF_L_SC_EN_VA18_MASK 0x1 |
| #define RG_HCLDO_BUF_L_SC_EN_VA18_MASK_SFT (0x1 << 0) |
| #define RG_HCLDO_BUF_R_SC_EN_VA18_SFT 1 |
| #define RG_HCLDO_BUF_R_SC_EN_VA18_MASK 0x1 |
| #define RG_HCLDO_BUF_R_SC_EN_VA18_MASK_SFT (0x1 << 1) |
| #define RG_LCLDO_DACSW_L_SC_EN_VA18_SFT 2 |
| #define RG_LCLDO_DACSW_L_SC_EN_VA18_MASK 0x1 |
| #define RG_LCLDO_DACSW_L_SC_EN_VA18_MASK_SFT (0x1 << 2) |
| #define RG_LCLDO_DACSW_R_SC_EN_VA18_SFT 3 |
| #define RG_LCLDO_DACSW_R_SC_EN_VA18_MASK 0x1 |
| #define RG_LCLDO_DACSW_R_SC_EN_VA18_MASK_SFT (0x1 << 3) |
| |
| /* AUDDEC_PMU_CON41 */ |
| #define RG_NVREG_LC_BUF_L_EN_VAUDP18_SFT 0 |
| #define RG_NVREG_LC_BUF_L_EN_VAUDP18_MASK 0x1 |
| #define RG_NVREG_LC_BUF_L_EN_VAUDP18_MASK_SFT (0x1 << 0) |
| #define RG_NVREG_LC_BUF_R_EN_VAUDP18_SFT 1 |
| #define RG_NVREG_LC_BUF_R_EN_VAUDP18_MASK 0x1 |
| #define RG_NVREG_LC_BUF_R_EN_VAUDP18_MASK_SFT (0x1 << 1) |
| #define RG_NVREG_HC_BUF_L_EN_VAUDP18_SFT 2 |
| #define RG_NVREG_HC_BUF_L_EN_VAUDP18_MASK 0x1 |
| #define RG_NVREG_HC_BUF_L_EN_VAUDP18_MASK_SFT (0x1 << 2) |
| #define RG_NVREG_HC_BUF_R_EN_VAUDP18_SFT 3 |
| #define RG_NVREG_HC_BUF_R_EN_VAUDP18_MASK 0x1 |
| #define RG_NVREG_HC_BUF_R_EN_VAUDP18_MASK_SFT (0x1 << 3) |
| #define RG_NVREG_DACSW_L_EN_VAUDP18_SFT 4 |
| #define RG_NVREG_DACSW_L_EN_VAUDP18_MASK 0x1 |
| #define RG_NVREG_DACSW_L_EN_VAUDP18_MASK_SFT (0x1 << 4) |
| #define RG_NVREG_DACSW_R_EN_VAUDP18_SFT 5 |
| #define RG_NVREG_DACSW_R_EN_VAUDP18_MASK 0x1 |
| #define RG_NVREG_DACSW_R_EN_VAUDP18_MASK_SFT (0x1 << 5) |
| #define RG_NVREG_LC_BUF_L_PULL0V_VAUDP18_SFT 6 |
| #define RG_NVREG_LC_BUF_L_PULL0V_VAUDP18_MASK 0x1 |
| #define RG_NVREG_LC_BUF_L_PULL0V_VAUDP18_MASK_SFT (0x1 << 6) |
| #define RG_NVREG_LC_BUF_R_PULL0V_VAUDP18_SFT 7 |
| #define RG_NVREG_LC_BUF_R_PULL0V_VAUDP18_MASK 0x1 |
| #define RG_NVREG_LC_BUF_R_PULL0V_VAUDP18_MASK_SFT (0x1 << 7) |
| |
| /* AUDDEC_PMU_CON42 */ |
| #define RG_NVREG_HC_BUF_L_PULL0V_VAUDP18_SFT 0 |
| #define RG_NVREG_HC_BUF_L_PULL0V_VAUDP18_MASK 0x1 |
| #define RG_NVREG_HC_BUF_L_PULL0V_VAUDP18_MASK_SFT (0x1 << 0) |
| #define RG_NVREG_HC_BUF_R_PULL0V_VAUDP18_SFT 1 |
| #define RG_NVREG_HC_BUF_R_PULL0V_VAUDP18_MASK 0x1 |
| #define RG_NVREG_HC_BUF_R_PULL0V_VAUDP18_MASK_SFT (0x1 << 1) |
| #define RG_NVREG_DACSW_L_PULL0V_VAUDP18_SFT 2 |
| #define RG_NVREG_DACSW_L_PULL0V_VAUDP18_MASK 0x1 |
| #define RG_NVREG_DACSW_L_PULL0V_VAUDP18_MASK_SFT (0x1 << 2) |
| #define RG_NVREG_DACSW_R_PULL0V_VAUDP18_SFT 3 |
| #define RG_NVREG_DACSW_R_PULL0V_VAUDP18_MASK 0x1 |
| #define RG_NVREG_DACSW_R_PULL0V_VAUDP18_MASK_SFT (0x1 << 3) |
| |
| /* AUDDEC_PMU_CON43 */ |
| #define RG_AUDPMU_RSVD0_VA18_SFT 0 |
| #define RG_AUDPMU_RSVD0_VA18_MASK 0xff |
| #define RG_AUDPMU_RSVD0_VA18_MASK_SFT (0xff << 0) |
| |
| /* AUDDEC_PMU_CON44 */ |
| #define RG_AUDNCP_PWRSW_OFFCTRL_VA18_SFT 0 |
| #define RG_AUDNCP_PWRSW_OFFCTRL_VA18_MASK 0xf |
| #define RG_AUDNCP_PWRSW_OFFCTRL_VA18_MASK_SFT (0xf << 0) |
| #define RG_AUDNCP_LB_ENB_VA18_SFT 4 |
| #define RG_AUDNCP_LB_ENB_VA18_MASK 0x1 |
| #define RG_AUDNCP_LB_ENB_VA18_MASK_SFT (0x1 << 4) |
| |
| /* AUDDEC_PMU_CON45 */ |
| #define RG_AUDZCDMUXSEL_VAUDP18_SFT 0 |
| #define RG_AUDZCDMUXSEL_VAUDP18_MASK 0x7 |
| #define RG_AUDZCDMUXSEL_VAUDP18_MASK_SFT (0x7 << 0) |
| #define RG_AUDZCDCLKSEL_VAUDP18_SFT 4 |
| #define RG_AUDZCDCLKSEL_VAUDP18_MASK 0x1 |
| #define RG_AUDZCDCLKSEL_VAUDP18_MASK_SFT (0x1 << 4) |
| |
| /* AUDDEC_PMU_CON46 */ |
| #define RG_ABIDEC_RSVD0_VA18_SFT 0 |
| #define RG_ABIDEC_RSVD0_VA18_MASK 0xff |
| #define RG_ABIDEC_RSVD0_VA18_MASK_SFT (0xff << 0) |
| |
| /* AUDDEC_PMU_CON47 */ |
| #define RG_ABIDEC_RSVD0_VA32_SFT 0 |
| #define RG_ABIDEC_RSVD0_VA32_MASK 0xff |
| #define RG_ABIDEC_RSVD0_VA32_MASK_SFT (0xff << 0) |
| |
| /* AUDDEC_PMU_CON48 */ |
| #define RG_ABIDEC_RSVD0_VAUDP18_SFT 0 |
| #define RG_ABIDEC_RSVD0_VAUDP18_MASK 0xff |
| #define RG_ABIDEC_RSVD0_VAUDP18_MASK_SFT (0xff << 0) |
| |
| /* AUDDEC_PMU_CON49 */ |
| #define RG_ABIDEC_RSVD1_VAUDP18_SFT 0 |
| #define RG_ABIDEC_RSVD1_VAUDP18_MASK 0xff |
| #define RG_ABIDEC_RSVD1_VAUDP18_MASK_SFT (0xff << 0) |
| |
| /* AUDDEC_2_PMU_CON0 */ |
| #define RG_AUDDACHPL_TRIM_EN_VAUDP18_SFT 0 |
| #define RG_AUDDACHPL_TRIM_EN_VAUDP18_MASK 0x1 |
| #define RG_AUDDACHPL_TRIM_EN_VAUDP18_MASK_SFT (0x1 << 0) |
| #define RG_AUDDACHPL_TRIM_LARGE_VAUDP18_SFT 1 |
| #define RG_AUDDACHPL_TRIM_LARGE_VAUDP18_MASK 0x7f |
| #define RG_AUDDACHPL_TRIM_LARGE_VAUDP18_MASK_SFT (0x7f << 1) |
| |
| /* AUDDEC_2_PMU_CON1 */ |
| #define RG_AUDDACHPL_TRIM_SMALL_VAUDP18_SFT 0 |
| #define RG_AUDDACHPL_TRIM_SMALL_VAUDP18_MASK 0xf |
| #define RG_AUDDACHPL_TRIM_SMALL_VAUDP18_MASK_SFT (0xf << 0) |
| #define RG_AUDDACHPL_TRIM_TINY_VAUDP18_SFT 4 |
| #define RG_AUDDACHPL_TRIM_TINY_VAUDP18_MASK 0xf |
| #define RG_AUDDACHPL_TRIM_TINY_VAUDP18_MASK_SFT (0xf << 4) |
| |
| /* AUDDEC_2_PMU_CON2 */ |
| #define RG_AUDDACHPR_TRIM_EN_VAUDP18_SFT 0 |
| #define RG_AUDDACHPR_TRIM_EN_VAUDP18_MASK 0x1 |
| #define RG_AUDDACHPR_TRIM_EN_VAUDP18_MASK_SFT (0x1 << 0) |
| #define RG_AUDDACHPR_TRIM_LARGE_VAUDP18_SFT 1 |
| #define RG_AUDDACHPR_TRIM_LARGE_VAUDP18_MASK 0x7f |
| #define RG_AUDDACHPR_TRIM_LARGE_VAUDP18_MASK_SFT (0x7f << 1) |
| |
| /* AUDDEC_2_PMU_CON3 */ |
| #define RG_AUDDACHPR_TRIM_SMALL_VAUDP18_SFT 0 |
| #define RG_AUDDACHPR_TRIM_SMALL_VAUDP18_MASK 0xf |
| #define RG_AUDDACHPR_TRIM_SMALL_VAUDP18_MASK_SFT (0xf << 0) |
| #define RG_AUDDACHPR_TRIM_TINY_VAUDP18_SFT 4 |
| #define RG_AUDDACHPR_TRIM_TINY_VAUDP18_MASK 0xf |
| #define RG_AUDDACHPR_TRIM_TINY_VAUDP18_MASK_SFT (0xf << 4) |
| |
| /* AUDDEC_2_PMU_CON4 */ |
| #define RG_AUDDACHS_TRIM_EN_VAUDP18_SFT 0 |
| #define RG_AUDDACHS_TRIM_EN_VAUDP18_MASK 0x1 |
| #define RG_AUDDACHS_TRIM_EN_VAUDP18_MASK_SFT (0x1 << 0) |
| #define RG_AUDDACHS_TRIM_LARGE_VAUDP18_SFT 1 |
| #define RG_AUDDACHS_TRIM_LARGE_VAUDP18_MASK 0x7f |
| #define RG_AUDDACHS_TRIM_LARGE_VAUDP18_MASK_SFT (0x7f << 1) |
| |
| /* AUDDEC_2_PMU_CON5 */ |
| #define RG_AUDDACHS_TRIM_SMALL_VAUDP18_SFT 0 |
| #define RG_AUDDACHS_TRIM_SMALL_VAUDP18_MASK 0xf |
| #define RG_AUDDACHS_TRIM_SMALL_VAUDP18_MASK_SFT (0xf << 0) |
| #define RG_AUDDACHS_TRIM_TINY_VAUDP18_SFT 4 |
| #define RG_AUDDACHS_TRIM_TINY_VAUDP18_MASK 0xf |
| #define RG_AUDDACHS_TRIM_TINY_VAUDP18_MASK_SFT (0xf << 4) |
| |
| /* AUDDEC_2_PMU_CON6 */ |
| #define RG_AUDDACLO_TRIM_EN_VAUDP18_SFT 0 |
| #define RG_AUDDACLO_TRIM_EN_VAUDP18_MASK 0x1 |
| #define RG_AUDDACLO_TRIM_EN_VAUDP18_MASK_SFT (0x1 << 0) |
| #define RG_AUDDACLO_TRIM_LARGE_VAUDP18_SFT 1 |
| #define RG_AUDDACLO_TRIM_LARGE_VAUDP18_MASK 0x7f |
| #define RG_AUDDACLO_TRIM_LARGE_VAUDP18_MASK_SFT (0x7f << 1) |
| |
| /* AUDDEC_2_PMU_CON7 */ |
| #define RG_AUDDACLO_TRIM_SMALL_VAUDP18_SFT 0 |
| #define RG_AUDDACLO_TRIM_SMALL_VAUDP18_MASK 0xf |
| #define RG_AUDDACLO_TRIM_SMALL_VAUDP18_MASK_SFT (0xf << 0) |
| #define RG_AUDDACLO_TRIM_TINY_VAUDP18_SFT 4 |
| #define RG_AUDDACLO_TRIM_TINY_VAUDP18_MASK 0xf |
| #define RG_AUDDACLO_TRIM_TINY_VAUDP18_MASK_SFT (0xf << 4) |
| |
| /* AUDDEC_2_PMU_CON8 */ |
| #define RG_AUDDAC_DAC_RSVD0_VAUDP18_SFT 0 |
| #define RG_AUDDAC_DAC_RSVD0_VAUDP18_MASK 0xf |
| #define RG_AUDDAC_DAC_RSVD0_VAUDP18_MASK_SFT (0xf << 0) |
| #define RG_AUDDACHP_HOLD_SW_EN_VAUDP18_SFT 6 |
| #define RG_AUDDACHP_HOLD_SW_EN_VAUDP18_MASK 0x1 |
| #define RG_AUDDACHP_HOLD_SW_EN_VAUDP18_MASK_SFT (0x1 << 6) |
| #define RG_AUDDACHP_HOLD_SW_CLK_SEL_VAUDP18_SFT 7 |
| #define RG_AUDDACHP_HOLD_SW_CLK_SEL_VAUDP18_MASK 0x1 |
| #define RG_AUDDACHP_HOLD_SW_CLK_SEL_VAUDP18_MASK_SFT (0x1 << 7) |
| |
| /* AUDDEC_2_PMU_CON9 */ |
| #define RG_ABIDEC_RSVD2_VAUDP18_SFT 0 |
| #define RG_ABIDEC_RSVD2_VAUDP18_MASK 0xff |
| #define RG_ABIDEC_RSVD2_VAUDP18_MASK_SFT (0xff << 0) |
| |
| /* AUDDEC_2_PMU_CON10 */ |
| #define RG_ABIDEC_RSVD3_VAUDP18_SFT 0 |
| #define RG_ABIDEC_RSVD3_VAUDP18_MASK 0xff |
| #define RG_ABIDEC_RSVD3_VAUDP18_MASK_SFT (0xff << 0) |
| |
| /* AUDDEC_2_PMU_CON11 */ |
| #define RG_ABIDEC_RSVD4_VAUDP18_SFT 0 |
| #define RG_ABIDEC_RSVD4_VAUDP18_MASK 0xff |
| #define RG_ABIDEC_RSVD4_VAUDP18_MASK_SFT (0xff << 0) |
| |
| /* AUDDEC_2_PMU_CON12 */ |
| #define RG_ABIDEC_RSVD5_VAUDP18_SFT 0 |
| #define RG_ABIDEC_RSVD5_VAUDP18_MASK 0xff |
| #define RG_ABIDEC_RSVD5_VAUDP18_MASK_SFT (0xff << 0) |
| |
| /* AUDZCD_DSN_ID */ |
| #define AUDZCD_ANA_ID_SFT 0 |
| #define AUDZCD_ANA_ID_MASK 0xff |
| #define AUDZCD_ANA_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDZCD_DSN_ID_H */ |
| #define AUDZCD_DIG_ID_SFT 0 |
| #define AUDZCD_DIG_ID_MASK 0xff |
| #define AUDZCD_DIG_ID_MASK_SFT (0xff << 0) |
| |
| /* AUDZCD_DSN_REV0 */ |
| #define AUDZCD_ANA_MINOR_REV_SFT 0 |
| #define AUDZCD_ANA_MINOR_REV_MASK 0xf |
| #define AUDZCD_ANA_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDZCD_ANA_MAJOR_REV_SFT 4 |
| #define AUDZCD_ANA_MAJOR_REV_MASK 0xf |
| #define AUDZCD_ANA_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDZCD_DSN_REV0_H */ |
| #define AUDZCD_DIG_MINOR_REV_SFT 0 |
| #define AUDZCD_DIG_MINOR_REV_MASK 0xf |
| #define AUDZCD_DIG_MINOR_REV_MASK_SFT (0xf << 0) |
| #define AUDZCD_DIG_MAJOR_REV_SFT 4 |
| #define AUDZCD_DIG_MAJOR_REV_MASK 0xf |
| #define AUDZCD_DIG_MAJOR_REV_MASK_SFT (0xf << 4) |
| |
| /* AUDZCD_DSN_DBI */ |
| #define AUDZCD_DSN_CBS_SFT 0 |
| #define AUDZCD_DSN_CBS_MASK 0x3 |
| #define AUDZCD_DSN_CBS_MASK_SFT (0x3 << 0) |
| #define AUDZCD_DSN_BIX_SFT 2 |
| #define AUDZCD_DSN_BIX_MASK 0x3 |
| #define AUDZCD_DSN_BIX_MASK_SFT (0x3 << 2) |
| |
| /* AUDZCD_DSN_DBI_H */ |
| #define AUDZCD_DSN_ESP_SFT 0 |
| #define AUDZCD_DSN_ESP_MASK 0xff |
| #define AUDZCD_DSN_ESP_MASK_SFT (0xff << 0) |
| |
| /* AUDZCD_DSN_FPI */ |
| #define AUDZCD_DSN_FPI_SFT 0 |
| #define AUDZCD_DSN_FPI_MASK 0xff |
| #define AUDZCD_DSN_FPI_MASK_SFT (0xff << 0) |
| |
| /* ZCD_CON0 */ |
| #define RG_AUDZCDENABLE_SFT 0 |
| #define RG_AUDZCDENABLE_MASK 0x1 |
| #define RG_AUDZCDENABLE_MASK_SFT (0x1 << 0) |
| #define RG_AUDZCDGAINSTEPTIME_SFT 1 |
| #define RG_AUDZCDGAINSTEPTIME_MASK 0x7 |
| #define RG_AUDZCDGAINSTEPTIME_MASK_SFT (0x7 << 1) |
| #define RG_AUDZCDGAINSTEPSIZE_SFT 4 |
| #define RG_AUDZCDGAINSTEPSIZE_MASK 0x3 |
| #define RG_AUDZCDGAINSTEPSIZE_MASK_SFT (0x3 << 4) |
| #define RG_AUDZCDTIMEOUTMODESEL_SFT 6 |
| #define RG_AUDZCDTIMEOUTMODESEL_MASK 0x1 |
| #define RG_AUDZCDTIMEOUTMODESEL_MASK_SFT (0x1 << 6) |
| |
| /* ZCD_CON1 */ |
| #define RG_AUDLOLGAIN_SFT 0 |
| #define RG_AUDLOLGAIN_MASK 0x1f |
| #define RG_AUDLOLGAIN_MASK_SFT (0x1f << 0) |
| |
| /* ZCD_CON1_H */ |
| #define RG_AUDLORGAIN_SFT 0 |
| #define RG_AUDLORGAIN_MASK 0x1f |
| #define RG_AUDLORGAIN_MASK_SFT (0x1f << 0) |
| |
| /* ZCD_CON2 */ |
| #define RG_AUDHPLGAIN_SFT 0 |
| #define RG_AUDHPLGAIN_MASK 0x1f |
| #define RG_AUDHPLGAIN_MASK_SFT (0x1f << 0) |
| |
| /* ZCD_CON2_H */ |
| #define RG_AUDHPRGAIN_SFT 0 |
| #define RG_AUDHPRGAIN_MASK 0x1f |
| #define RG_AUDHPRGAIN_MASK_SFT (0x1f << 0) |
| |
| /* ZCD_CON3 */ |
| #define RG_AUDHSGAIN_SFT 0 |
| #define RG_AUDHSGAIN_MASK 0x1f |
| #define RG_AUDHSGAIN_MASK_SFT (0x1f << 0) |
| |
| /* ZCD_CON4 */ |
| #define RG_AUDIVLGAIN_SFT 0 |
| #define RG_AUDIVLGAIN_MASK 0x7 |
| #define RG_AUDIVLGAIN_MASK_SFT (0x7 << 0) |
| |
| /* ZCD_CON4_H */ |
| #define RG_AUDIVRGAIN_SFT 0 |
| #define RG_AUDIVRGAIN_MASK 0x7 |
| #define RG_AUDIVRGAIN_MASK_SFT (0x7 << 0) |
| |
| /* ZCD_CON5 */ |
| #define RG_AUDINTGAIN1_SFT 0 |
| #define RG_AUDINTGAIN1_MASK 0x1f |
| #define RG_AUDINTGAIN1_MASK_SFT (0x1f << 0) |
| |
| /* ZCD_CON5_H */ |
| #define RG_AUDINTGAIN2_SFT 0 |
| #define RG_AUDINTGAIN2_MASK 0x1f |
| #define RG_AUDINTGAIN2_MASK_SFT (0x1f << 0) |
| |
| /*************AUXADC Register Bit Define*************/ |
| //mask is HEX; shift is Integer |
| #define MT6338_AUXADC_RQST_CH5_ADDR \ |
| MT6338_AUXADC_RQST0 |
| #define MT6338_AUXADC_RQST_CH5_MASK 0x1 |
| #define MT6338_AUXADC_RQST_CH5_SHIFT 1 |
| #define MT6338_AUXADC_ACCDET_DIG0_RSV0_ADDR \ |
| MT6338_AUXADC_ACCDET0 |
| #define MT6338_AUXADC_ACCDET_DIG0_RSV0_MASK 0xFF |
| #define MT6338_AUXADC_ACCDET_DIG0_RSV0_SHIFT 0 |
| #define MT6338_AUXADC_ACCDET_AUTO_SPL_ADDR \ |
| MT6338_AUXADC_ACCDET1 |
| #define MT6338_AUXADC_ACCDET_AUTO_SPL_MASK 0x1 |
| #define MT6338_AUXADC_ACCDET_AUTO_SPL_SHIFT 0 |
| #define MT6338_AUXADC_ACCDET_AUTO_RQST_CLR_ADDR \ |
| MT6338_AUXADC_ACCDET1 |
| #define MT6338_AUXADC_ACCDET_AUTO_RQST_CLR_MASK 0x1 |
| #define MT6338_AUXADC_ACCDET_AUTO_RQST_CLR_SHIFT 1 |
| #define MT6338_AUXADC_ACCDET_DIG1_RSV0_ADDR \ |
| MT6338_AUXADC_ACCDET1 |
| #define MT6338_AUXADC_ACCDET_DIG1_RSV0_MASK 0x3F |
| #define MT6338_AUXADC_ACCDET_DIG1_RSV0_SHIFT 2 |
| #define MT6338_AUD_TOP_ANA_ID_ADDR \ |
| MT6338_AUD_TOP_ID |
| #define MT6338_AUD_TOP_ANA_ID_MASK 0xFF |
| #define MT6338_AUD_TOP_ANA_ID_SHIFT 0 |
| #define MT6338_AUD_TOP_DIG_ID_ADDR \ |
| MT6338_AUD_TOP_ID_H |
| #define MT6338_AUD_TOP_DIG_ID_MASK 0xFF |
| #define MT6338_AUD_TOP_DIG_ID_SHIFT 0 |
| #define MT6338_AUD_TOP_ANA_MINOR_REV_ADDR \ |
| MT6338_AUD_TOP_REV0 |
| #define MT6338_AUD_TOP_ANA_MINOR_REV_MASK 0xF |
| #define MT6338_AUD_TOP_ANA_MINOR_REV_SHIFT 0 |
| #define MT6338_AUD_TOP_ANA_MAJOR_REV_ADDR \ |
| MT6338_AUD_TOP_REV0 |
| #define MT6338_AUD_TOP_ANA_MAJOR_REV_MASK 0xF |
| #define MT6338_AUD_TOP_ANA_MAJOR_REV_SHIFT 4 |
| #define MT6338_AUD_TOP_DIG_MINOR_REV_ADDR \ |
| MT6338_AUD_TOP_REV0_H |
| #define MT6338_AUD_TOP_DIG_MINOR_REV_MASK 0xF |
| #define MT6338_AUD_TOP_DIG_MINOR_REV_SHIFT 0 |
| #define MT6338_AUD_TOP_DIG_MAJOR_REV_ADDR \ |
| MT6338_AUD_TOP_REV0_H |
| #define MT6338_AUD_TOP_DIG_MAJOR_REV_MASK 0xF |
| #define MT6338_AUD_TOP_DIG_MAJOR_REV_SHIFT 4 |
| #define MT6338_AUD_TOP_CBS_ADDR \ |
| MT6338_AUD_TOP_DBI |
| #define MT6338_AUD_TOP_CBS_MASK 0x3 |
| #define MT6338_AUD_TOP_CBS_SHIFT 0 |
| #define MT6338_AUD_TOP_BIX_ADDR \ |
| MT6338_AUD_TOP_DBI |
| #define MT6338_AUD_TOP_BIX_MASK 0x3 |
| #define MT6338_AUD_TOP_BIX_SHIFT 2 |
| #define MT6338_AUD_TOP_ESP_ADDR \ |
| MT6338_AUD_TOP_DBI_H |
| #define MT6338_AUD_TOP_ESP_MASK 0xFF |
| #define MT6338_AUD_TOP_ESP_SHIFT 0 |
| #define MT6338_AUD_TOP_FPI_ADDR \ |
| MT6338_AUD_TOP_DXI |
| #define MT6338_AUD_TOP_FPI_MASK 0xFF |
| #define MT6338_AUD_TOP_FPI_SHIFT 0 |
| #define MT6338_AUD_TOP_CLK_OFFSET_ADDR \ |
| MT6338_AUD_TOP_CKPDN_TPM0 |
| #define MT6338_AUD_TOP_CLK_OFFSET_MASK 0xFF |
| #define MT6338_AUD_TOP_CLK_OFFSET_SHIFT 0 |
| #define MT6338_AUD_TOP_RST_OFFSET_ADDR \ |
| MT6338_AUD_TOP_CKPDN_TPM0_H |
| #define MT6338_AUD_TOP_RST_OFFSET_MASK 0xFF |
| #define MT6338_AUD_TOP_RST_OFFSET_SHIFT 0 |
| #define MT6338_AUD_TOP_INT_OFFSET_ADDR \ |
| MT6338_AUD_TOP_CKPDN_TPM1 |
| #define MT6338_AUD_TOP_INT_OFFSET_MASK 0xFF |
| #define MT6338_AUD_TOP_INT_OFFSET_SHIFT 0 |
| #define MT6338_AUD_TOP_INT_LEN_ADDR \ |
| MT6338_AUD_TOP_CKPDN_TPM1_H |
| #define MT6338_AUD_TOP_INT_LEN_MASK 0xFF |
| #define MT6338_AUD_TOP_INT_LEN_SHIFT 0 |
| #define MT6338_RG_ACCDET_CK_PDN_ADDR \ |
| MT6338_AUD_TOP_CKPDN_CON0 |
| #define MT6338_RG_ACCDET_CK_PDN_MASK 0x1 |
| #define MT6338_RG_ACCDET_CK_PDN_SHIFT 0 |
| #define MT6338_RG_AUD_CK_PDN_ADDR \ |
| MT6338_AUD_TOP_CKPDN_CON0 |
| #define MT6338_RG_AUD_CK_PDN_MASK 0x1 |
| #define MT6338_RG_AUD_CK_PDN_SHIFT 1 |
| #define MT6338_RG_AUDIF_CK_PDN_ADDR \ |
| MT6338_AUD_TOP_CKPDN_CON0 |
| #define MT6338_RG_AUDIF_CK_PDN_MASK 0x1 |
| #define MT6338_RG_AUDIF_CK_PDN_SHIFT 2 |
| #define MT6338_RG_ZCD13M_CK_PDN_ADDR \ |
| MT6338_AUD_TOP_CKPDN_CON0 |
| #define MT6338_RG_ZCD13M_CK_PDN_MASK 0x1 |
| #define MT6338_RG_ZCD13M_CK_PDN_SHIFT 5 |
| #define MT6338_RG_AUDNCP_CK_PDN_ADDR \ |
| MT6338_AUD_TOP_CKPDN_CON0 |
| #define MT6338_RG_AUDNCP_CK_PDN_MASK 0x1 |
| #define MT6338_RG_AUDNCP_CK_PDN_SHIFT 6 |
| #define MT6338_RG_PAD_AUD_CLK_MISO_CK_PDN_ADDR \ |
| MT6338_AUD_TOP_CKPDN_CON0 |
| #define MT6338_RG_PAD_AUD_CLK_MISO_CK_PDN_MASK 0x1 |
| #define MT6338_RG_PAD_AUD_CLK_MISO_CK_PDN_SHIFT 7 |
| #define MT6338_RG_AUD_TOP_CKPDN_CON0_SET_ADDR \ |
| MT6338_AUD_TOP_CKPDN_CON0_SET |
| #define MT6338_RG_AUD_TOP_CKPDN_CON0_SET_MASK 0xFF |
| #define MT6338_RG_AUD_TOP_CKPDN_CON0_SET_SHIFT 0 |
| #define MT6338_RG_AUD_TOP_CKPDN_CON0_CLR_ADDR \ |
| MT6338_AUD_TOP_CKPDN_CON0_CLR |
| #define MT6338_RG_AUD_TOP_CKPDN_CON0_CLR_MASK 0xFF |
| #define MT6338_RG_AUD_TOP_CKPDN_CON0_CLR_SHIFT 0 |
| #define MT6338_RG_AUD_INTRP_CK_PDN_ADDR \ |
| MT6338_AUD_TOP_CKPDN_CON0_H |
| #define MT6338_RG_AUD_INTRP_CK_PDN_MASK 0x1 |
| #define MT6338_RG_AUD_INTRP_CK_PDN_SHIFT 0 |
| #define MT6338_RG_SCK32K_CK_PDN_ADDR \ |
| MT6338_AUD_TOP_CKPDN_CON0_H |
| #define MT6338_RG_SCK32K_CK_PDN_MASK 0x1 |
| #define MT6338_RG_SCK32K_CK_PDN_SHIFT 3 |
| #define MT6338_RG_VOW32K_CK_PDN_ADDR \ |
| MT6338_AUD_TOP_CKPDN_CON0_H |
| #define MT6338_RG_VOW32K_CK_PDN_MASK 0x1 |
| #define MT6338_RG_VOW32K_CK_PDN_SHIFT 4 |
| #define MT6338_RG_VOW13M_CK_PDN_ADDR \ |
| MT6338_AUD_TOP_CKPDN_CON0_H |
| #define MT6338_RG_VOW13M_CK_PDN_MASK 0x1 |
| #define MT6338_RG_VOW13M_CK_PDN_SHIFT 5 |
| #define MT6338_RG_AUD208M_CK_PDN_ADDR \ |
| MT6338_AUD_TOP_CKPDN_CON0_H |
| #define MT6338_RG_AUD208M_CK_PDN_MASK 0x1 |
| #define MT6338_RG_AUD208M_CK_PDN_SHIFT 6 |
| #define MT6338_RG_AUD_TOP_CKPDN_CON0_SET_H_ADDR \ |
| MT6338_AUD_TOP_CKPDN_CON0_H_SET |
| #define MT6338_RG_AUD_TOP_CKPDN_CON0_SET_H_MASK 0xFF |
| #define MT6338_RG_AUD_TOP_CKPDN_CON0_SET_H_SHIFT 0 |
| #define MT6338_RG_AUD_TOP_CKPDN_CON0_CLR_H_ADDR \ |
| MT6338_AUD_TOP_CKPDN_CON0_H_CLR |
| #define MT6338_RG_AUD_TOP_CKPDN_CON0_CLR_H_MASK 0xFF |
| #define MT6338_RG_AUD_TOP_CKPDN_CON0_CLR_H_SHIFT 0 |
| #define MT6338_RG_AUD_CK_CKSEL_ADDR \ |
| MT6338_AUD_TOP_CKSEL_CON0 |
| #define MT6338_RG_AUD_CK_CKSEL_MASK 0x1 |
| #define MT6338_RG_AUD_CK_CKSEL_SHIFT 2 |
| #define MT6338_RG_AUDIF_CK_CKSEL_ADDR \ |
| MT6338_AUD_TOP_CKSEL_CON0 |
| #define MT6338_RG_AUDIF_CK_CKSEL_MASK 0x1 |
| #define MT6338_RG_AUDIF_CK_CKSEL_SHIFT 3 |
| #define MT6338_RG_AUD_TOP_CKSEL_CON0_SET_ADDR \ |
| MT6338_AUD_TOP_CKSEL_CON0_SET |
| #define MT6338_RG_AUD_TOP_CKSEL_CON0_SET_MASK 0xF |
| #define MT6338_RG_AUD_TOP_CKSEL_CON0_SET_SHIFT 0 |
| #define MT6338_RG_AUD_TOP_CKSEL_CON0_CLR_ADDR \ |
| MT6338_AUD_TOP_CKSEL_CON0_CLR |
| #define MT6338_RG_AUD_TOP_CKSEL_CON0_CLR_MASK 0xF |
| #define MT6338_RG_AUD_TOP_CKSEL_CON0_CLR_SHIFT 0 |
| #define MT6338_RG_AUD26M_CK_TST_DIS_ADDR \ |
| MT6338_AUD_TOP_CKTST_CON0 |
| #define MT6338_RG_AUD26M_CK_TST_DIS_MASK 0x1 |
| #define MT6338_RG_AUD26M_CK_TST_DIS_SHIFT 0 |
| #define MT6338_RG_AUD_CK_TSTSEL_ADDR \ |
| MT6338_AUD_TOP_CKTST_CON0 |
| #define MT6338_RG_AUD_CK_TSTSEL_MASK 0x1 |
| #define MT6338_RG_AUD_CK_TSTSEL_SHIFT 2 |
| #define MT6338_RG_AUDIF_CK_TSTSEL_ADDR \ |
| MT6338_AUD_TOP_CKTST_CON0 |
| #define MT6338_RG_AUDIF_CK_TSTSEL_MASK 0x1 |
| #define MT6338_RG_AUDIF_CK_TSTSEL_SHIFT 3 |
| #define MT6338_RG_AUD26M_CK_TSTSEL_ADDR \ |
| MT6338_AUD_TOP_CKTST_CON0 |
| #define MT6338_RG_AUD26M_CK_TSTSEL_MASK 0x1 |
| #define MT6338_RG_AUD26M_CK_TSTSEL_SHIFT 4 |
| #define MT6338_RG_VOW13M_CK_TST_DIS_ADDR \ |
| MT6338_AUD_TOP_CKTST_CON0_H |
| #define MT6338_RG_VOW13M_CK_TST_DIS_MASK 0x1 |
| #define MT6338_RG_VOW13M_CK_TST_DIS_SHIFT 0 |
| #define MT6338_RG_VOW13M_CK_TSTSEL_ADDR \ |
| MT6338_AUD_TOP_CKTST_CON0_H |
| #define MT6338_RG_VOW13M_CK_TSTSEL_MASK 0x1 |
| #define MT6338_RG_VOW13M_CK_TSTSEL_SHIFT 1 |
| #define MT6338_RG_AUD208M_CK_TST_DIS_ADDR \ |
| MT6338_AUD_TOP_CKTST_CON0_H |
| #define MT6338_RG_AUD208M_CK_TST_DIS_MASK 0x1 |
| #define MT6338_RG_AUD208M_CK_TST_DIS_SHIFT 2 |
| #define MT6338_RG_AUD208M_CK_TSTSEL_ADDR \ |
| MT6338_AUD_TOP_CKTST_CON0_H |
| #define MT6338_RG_AUD208M_CK_TSTSEL_MASK 0x1 |
| #define MT6338_RG_AUD208M_CK_TSTSEL_SHIFT 3 |
| #define MT6338_RG_SCK_32K_CK_TST_DIS_ADDR \ |
| MT6338_AUD_TOP_CKTST_CON0_H |
| #define MT6338_RG_SCK_32K_CK_TST_DIS_MASK 0x1 |
| #define MT6338_RG_SCK_32K_CK_TST_DIS_SHIFT 4 |
| #define MT6338_RG_SCK_32K_CK_TSTSEL_ADDR \ |
| MT6338_AUD_TOP_CKTST_CON0_H |
| #define MT6338_RG_SCK_32K_CK_TSTSEL_MASK 0x1 |
| #define MT6338_RG_SCK_32K_CK_TSTSEL_SHIFT 5 |
| #define MT6338_RG_AUD_INTRP_CK_PDN_HWEN_ADDR \ |
| MT6338_AUD_TOP_CLK_HWEN_CON0 |
| #define MT6338_RG_AUD_INTRP_CK_PDN_HWEN_MASK 0x1 |
| #define MT6338_RG_AUD_INTRP_CK_PDN_HWEN_SHIFT 0 |
| #define MT6338_RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_ADDR \ |
| MT6338_AUD_TOP_CLK_HWEN_CON0_SET |
| #define MT6338_RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK 0xFF |
| #define MT6338_RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_SHIFT 0 |
| #define MT6338_RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_ADDR \ |
| MT6338_AUD_TOP_CLK_HWEN_CON0_CLR |
| #define MT6338_RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK 0xFF |
| #define MT6338_RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_SHIFT 0 |
| #define MT6338_RG_AUDIO_RST_ADDR \ |
| MT6338_AUD_TOP_RST_CON0 |
| #define MT6338_RG_AUDIO_RST_MASK 0x1 |
| #define MT6338_RG_AUDIO_RST_SHIFT 0 |
| #define MT6338_RG_ACCDET_RST_ADDR \ |
| MT6338_AUD_TOP_RST_CON0 |
| #define MT6338_RG_ACCDET_RST_MASK 0x1 |
| #define MT6338_RG_ACCDET_RST_SHIFT 1 |
| #define MT6338_RG_ZCD_RST_ADDR \ |
| MT6338_AUD_TOP_RST_CON0 |
| #define MT6338_RG_ZCD_RST_MASK 0x1 |
| #define MT6338_RG_ZCD_RST_SHIFT 2 |
| #define MT6338_RG_AUDNCP_RST_ADDR \ |
| MT6338_AUD_TOP_RST_CON0 |
| #define MT6338_RG_AUDNCP_RST_MASK 0x1 |
| #define MT6338_RG_AUDNCP_RST_SHIFT 3 |
| #define MT6338_RG_AUD_TOP_RST_CON0_SET_ADDR \ |
| MT6338_AUD_TOP_RST_CON0_SET |
| #define MT6338_RG_AUD_TOP_RST_CON0_SET_MASK 0xF |
| #define MT6338_RG_AUD_TOP_RST_CON0_SET_SHIFT 0 |
| #define MT6338_RG_AUD_TOP_RST_CON0_CLR_ADDR \ |
| MT6338_AUD_TOP_RST_CON0_CLR |
| #define MT6338_RG_AUD_TOP_RST_CON0_CLR_MASK 0xF |
| #define MT6338_RG_AUD_TOP_RST_CON0_CLR_SHIFT 0 |
| #define MT6338_BANK_ACCDET_SWRST_ADDR \ |
| MT6338_AUD_TOP_RST_BANK_CON0 |
| #define MT6338_BANK_ACCDET_SWRST_MASK 0x1 |
| #define MT6338_BANK_ACCDET_SWRST_SHIFT 0 |
| #define MT6338_BANK_AUDIO_SWRST_ADDR \ |
| MT6338_AUD_TOP_RST_BANK_CON0 |
| #define MT6338_BANK_AUDIO_SWRST_MASK 0x1 |
| #define MT6338_BANK_AUDIO_SWRST_SHIFT 1 |
| #define MT6338_BANK_AUDZCD_SWRST_ADDR \ |
| MT6338_AUD_TOP_RST_BANK_CON0 |
| #define MT6338_BANK_AUDZCD_SWRST_MASK 0x1 |
| #define MT6338_BANK_AUDZCD_SWRST_SHIFT 2 |
| #define MT6338_RG_INT_EN_AUDIO_ADDR \ |
| MT6338_AUD_TOP_INT_CON0 |
| #define MT6338_RG_INT_EN_AUDIO_MASK 0x1 |
| #define MT6338_RG_INT_EN_AUDIO_SHIFT 0 |
| #define MT6338_RG_INT_EN_VOW_ADDR \ |
| MT6338_AUD_TOP_INT_CON0 |
| #define MT6338_RG_INT_EN_VOW_MASK 0x1 |
| #define MT6338_RG_INT_EN_VOW_SHIFT 1 |
| #define MT6338_RG_INT_EN_ACCDET_ADDR \ |
| MT6338_AUD_TOP_INT_CON0 |
| #define MT6338_RG_INT_EN_ACCDET_MASK 0x1 |
| #define MT6338_RG_INT_EN_ACCDET_SHIFT 5 |
| #define MT6338_RG_INT_EN_ACCDET_EINT0_ADDR \ |
| MT6338_AUD_TOP_INT_CON0 |
| #define MT6338_RG_INT_EN_ACCDET_EINT0_MASK 0x1 |
| #define MT6338_RG_INT_EN_ACCDET_EINT0_SHIFT 6 |
| #define MT6338_RG_INT_EN_ACCDET_EINT1_ADDR \ |
| MT6338_AUD_TOP_INT_CON0 |
| #define MT6338_RG_INT_EN_ACCDET_EINT1_MASK 0x1 |
| #define MT6338_RG_INT_EN_ACCDET_EINT1_SHIFT 7 |
| #define MT6338_RG_AUD_INT_CON0_SET_ADDR \ |
| MT6338_AUD_TOP_INT_CON0_SET |
| #define MT6338_RG_AUD_INT_CON0_SET_MASK 0xFF |
| #define MT6338_RG_AUD_INT_CON0_SET_SHIFT 0 |
| #define MT6338_RG_AUD_INT_CON0_CLR_ADDR \ |
| MT6338_AUD_TOP_INT_CON0_CLR |
| #define MT6338_RG_AUD_INT_CON0_CLR_MASK 0xFF |
| #define MT6338_RG_AUD_INT_CON0_CLR_SHIFT 0 |
| #define MT6338_RG_INT_MASK_AUDIO_ADDR \ |
| MT6338_AUD_TOP_INT_MASK_CON0 |
| #define MT6338_RG_INT_MASK_AUDIO_MASK 0x1 |
| #define MT6338_RG_INT_MASK_AUDIO_SHIFT 0 |
| #define MT6338_RG_INT_MASK_VOW_ADDR \ |
| MT6338_AUD_TOP_INT_MASK_CON0 |
| #define MT6338_RG_INT_MASK_VOW_MASK 0x1 |
| #define MT6338_RG_INT_MASK_VOW_SHIFT 1 |
| #define MT6338_RG_INT_MASK_ACCDET_ADDR \ |
| MT6338_AUD_TOP_INT_MASK_CON0 |
| #define MT6338_RG_INT_MASK_ACCDET_MASK 0x1 |
| #define MT6338_RG_INT_MASK_ACCDET_SHIFT 5 |
| #define MT6338_RG_INT_MASK_ACCDET_EINT0_ADDR \ |
| MT6338_AUD_TOP_INT_MASK_CON0 |
| #define MT6338_RG_INT_MASK_ACCDET_EINT0_MASK 0x1 |
| #define MT6338_RG_INT_MASK_ACCDET_EINT0_SHIFT 6 |
| #define MT6338_RG_INT_MASK_ACCDET_EINT1_ADDR \ |
| MT6338_AUD_TOP_INT_MASK_CON0 |
| #define MT6338_RG_INT_MASK_ACCDET_EINT1_MASK 0x1 |
| #define MT6338_RG_INT_MASK_ACCDET_EINT1_SHIFT 7 |
| #define MT6338_RG_AUD_INT_MASK_CON0_SET_ADDR \ |
| MT6338_AUD_TOP_INT_MASK_CON0_SET |
| #define MT6338_RG_AUD_INT_MASK_CON0_SET_MASK 0xFF |
| #define MT6338_RG_AUD_INT_MASK_CON0_SET_SHIFT 0 |
| #define MT6338_RG_AUD_INT_MASK_CON0_CLR_ADDR \ |
| MT6338_AUD_TOP_INT_MASK_CON0_CLR |
| #define MT6338_RG_AUD_INT_MASK_CON0_CLR_MASK 0xFF |
| #define MT6338_RG_AUD_INT_MASK_CON0_CLR_SHIFT 0 |
| #define MT6338_RG_INT_STATUS_AUDIO_ADDR \ |
| MT6338_AUD_TOP_INT_STATUS0 |
| #define MT6338_RG_INT_STATUS_AUDIO_MASK 0x1 |
| #define MT6338_RG_INT_STATUS_AUDIO_SHIFT 0 |
| #define MT6338_RG_INT_STATUS_VOW_ADDR \ |
| MT6338_AUD_TOP_INT_STATUS0 |
| #define MT6338_RG_INT_STATUS_VOW_MASK 0x1 |
| #define MT6338_RG_INT_STATUS_VOW_SHIFT 1 |
| #define MT6338_RG_INT_STATUS_ACCDET_ADDR \ |
| MT6338_AUD_TOP_INT_STATUS0 |
| #define MT6338_RG_INT_STATUS_ACCDET_MASK 0x1 |
| #define MT6338_RG_INT_STATUS_ACCDET_SHIFT 5 |
| #define MT6338_RG_INT_STATUS_ACCDET_EINT0_ADDR \ |
| MT6338_AUD_TOP_INT_STATUS0 |
| #define MT6338_RG_INT_STATUS_ACCDET_EINT0_MASK 0x1 |
| #define MT6338_RG_INT_STATUS_ACCDET_EINT0_SHIFT 6 |
| #define MT6338_RG_INT_STATUS_ACCDET_EINT1_ADDR \ |
| MT6338_AUD_TOP_INT_STATUS0 |
| #define MT6338_RG_INT_STATUS_ACCDET_EINT1_MASK 0x1 |
| #define MT6338_RG_INT_STATUS_ACCDET_EINT1_SHIFT 7 |
| #define MT6338_RG_INT_RAW_STATUS_AUDIO_ADDR \ |
| MT6338_AUD_TOP_INT_RAW_STATUS0 |
| #define MT6338_RG_INT_RAW_STATUS_AUDIO_MASK 0x1 |
| #define MT6338_RG_INT_RAW_STATUS_AUDIO_SHIFT 0 |
| #define MT6338_RG_INT_RAW_STATUS_VOW_ADDR \ |
| MT6338_AUD_TOP_INT_RAW_STATUS0 |
| #define MT6338_RG_INT_RAW_STATUS_VOW_MASK 0x1 |
| #define MT6338_RG_INT_RAW_STATUS_VOW_SHIFT 1 |
| #define MT6338_RG_INT_RAW_STATUS_ACCDET_ADDR \ |
| MT6338_AUD_TOP_INT_RAW_STATUS0 |
| #define MT6338_RG_INT_RAW_STATUS_ACCDET_MASK 0x1 |
| #define MT6338_RG_INT_RAW_STATUS_ACCDET_SHIFT 5 |
| #define MT6338_RG_INT_RAW_STATUS_ACCDET_EINT0_ADDR \ |
| MT6338_AUD_TOP_INT_RAW_STATUS0 |
| #define MT6338_RG_INT_RAW_STATUS_ACCDET_EINT0_MASK 0x1 |
| #define MT6338_RG_INT_RAW_STATUS_ACCDET_EINT0_SHIFT 6 |
| #define MT6338_RG_INT_RAW_STATUS_ACCDET_EINT1_ADDR \ |
| MT6338_AUD_TOP_INT_RAW_STATUS0 |
| #define MT6338_RG_INT_RAW_STATUS_ACCDET_EINT1_MASK 0x1 |
| #define MT6338_RG_INT_RAW_STATUS_ACCDET_EINT1_SHIFT 7 |
| #define MT6338_RG_AUD_TOP_INT_POLARITY_ADDR \ |
| MT6338_AUD_TOP_INT_MISC_CON0 |
| #define MT6338_RG_AUD_TOP_INT_POLARITY_MASK 0x1 |
| #define MT6338_RG_AUD_TOP_INT_POLARITY_SHIFT 0 |
| #define MT6338_RG_AUD_TOP_MON_SEL_ADDR \ |
| MT6338_AUD_TOP_MON_CON0 |
| #define MT6338_RG_AUD_TOP_MON_SEL_MASK 0x7 |
| #define MT6338_RG_AUD_TOP_MON_SEL_SHIFT 0 |
| #define MT6338_RG_AUD_CLK_INT_MON_FLAG_EN_ADDR \ |
| MT6338_AUD_TOP_MON_CON0 |
| #define MT6338_RG_AUD_CLK_INT_MON_FLAG_EN_MASK 0x1 |
| #define MT6338_RG_AUD_CLK_INT_MON_FLAG_EN_SHIFT 3 |
| #define MT6338_RG_AUD_CLK_INT_MON_FLAG_SEL_ADDR \ |
| MT6338_AUD_TOP_MON_CON0_H |
| #define MT6338_RG_AUD_CLK_INT_MON_FLAG_SEL_MASK 0xFF |
| #define MT6338_RG_AUD_CLK_INT_MON_FLAG_SEL_SHIFT 0 |
| #define MT6338_RG_AUD_PAD_TOP_PHASE_MODE_ADDR \ |
| MT6338_AUDIO_DIG_CFG |
| #define MT6338_RG_AUD_PAD_TOP_PHASE_MODE_MASK 0x7F |
| #define MT6338_RG_AUD_PAD_TOP_PHASE_MODE_SHIFT 0 |
| #define MT6338_RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_ADDR \ |
| MT6338_AUDIO_DIG_CFG |
| #define MT6338_RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK 0x1 |
| #define MT6338_RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SHIFT 7 |
| #define MT6338_RG_AUD_PAD_TOP_PHASE_MODE2_ADDR \ |
| MT6338_AUDIO_DIG_CFG_H |
| #define MT6338_RG_AUD_PAD_TOP_PHASE_MODE2_MASK 0x7F |
| #define MT6338_RG_AUD_PAD_TOP_PHASE_MODE2_SHIFT 0 |
| #define MT6338_RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_ADDR \ |
| MT6338_AUDIO_DIG_CFG_H |
| #define MT6338_RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK 0x1 |
| #define MT6338_RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SHIFT 7 |
| #define MT6338_RG_AUD_PAD_TOP_PHASE_MODE3_ADDR \ |
| MT6338_AUDIO_DIG_CFG1 |
| #define MT6338_RG_AUD_PAD_TOP_PHASE_MODE3_MASK 0x7F |
| #define MT6338_RG_AUD_PAD_TOP_PHASE_MODE3_SHIFT 0 |
| #define MT6338_RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_ADDR \ |
| MT6338_AUDIO_DIG_CFG1 |
| #define MT6338_RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK 0x1 |
| #define MT6338_RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_SHIFT 7 |
| #define MT6338_RG_AUD_PAD_TOP_TX_FIFO_ON_ADDR \ |
| MT6338_AFE_AUD_PAD_TOP |
| #define MT6338_RG_AUD_PAD_TOP_TX_FIFO_ON_MASK 0x1 |
| #define MT6338_RG_AUD_PAD_TOP_TX_FIFO_ON_SHIFT 0 |
| #define MT6338_RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_ADDR \ |
| MT6338_AFE_AUD_PAD_TOP |
| #define MT6338_RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK 0x1 |
| #define MT6338_RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_SHIFT 3 |
| #define MT6338_RG_AUD_PAD_TOP_TX_FIFO_RSP_ADDR \ |
| MT6338_AFE_AUD_PAD_TOP |
| #define MT6338_RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK 0x7 |
| #define MT6338_RG_AUD_PAD_TOP_TX_FIFO_RSP_SHIFT 4 |
| #define MT6338_ADDA_AUD_PAD_TOP_MON_L_ADDR \ |
| MT6338_AFE_AUD_PAD_TOP_MON |
| #define MT6338_ADDA_AUD_PAD_TOP_MON_L_MASK 0xFF |
| #define MT6338_ADDA_AUD_PAD_TOP_MON_L_SHIFT 0 |
| #define MT6338_ADDA_AUD_PAD_TOP_MON_H_ADDR \ |
| MT6338_AFE_AUD_PAD_TOP_MON_H |
| #define MT6338_ADDA_AUD_PAD_TOP_MON_H_MASK 0xFF |
| #define MT6338_ADDA_AUD_PAD_TOP_MON_H_SHIFT 0 |
| #define MT6338_ADDA_AUD_PAD_TOP_MON1_L_ADDR \ |
| MT6338_AFE_AUD_PAD_TOP_MON1 |
| #define MT6338_ADDA_AUD_PAD_TOP_MON1_L_MASK 0xFF |
| #define MT6338_ADDA_AUD_PAD_TOP_MON1_L_SHIFT 0 |
| #define MT6338_ADDA_AUD_PAD_TOP_MON1_H_ADDR \ |
| MT6338_AFE_AUD_PAD_TOP_MON1_H |
| #define MT6338_ADDA_AUD_PAD_TOP_MON1_H_MASK 0xFF |
| #define MT6338_ADDA_AUD_PAD_TOP_MON1_H_SHIFT 0 |
| #define MT6338_ADDA_AUD_PAD_TOP_MON2_L_ADDR \ |
| MT6338_AFE_AUD_PAD_TOP_MON2 |
| #define MT6338_ADDA_AUD_PAD_TOP_MON2_L_MASK 0xFF |
| #define MT6338_ADDA_AUD_PAD_TOP_MON2_L_SHIFT 0 |
| #define MT6338_AUDIO_MEM_PDN_ADDR \ |
| MT6338_AUD_TOP_SRAM_CON |
| #define MT6338_AUDIO_MEM_PDN_MASK 0x1 |
| #define MT6338_AUDIO_MEM_PDN_SHIFT 0 |
| #define MT6338_AUDIO_CO_MEM_PDN_ADDR \ |
| MT6338_AUD_TOP_SRAM_CON |
| #define MT6338_AUDIO_CO_MEM_PDN_MASK 0x1 |
| #define MT6338_AUDIO_CO_MEM_PDN_SHIFT 1 |
| #define MT6338_AUDIO_CO_MEM_PDN_SEL_ADDR \ |
| MT6338_AUD_TOP_SRAM_CON |
| #define MT6338_AUDIO_CO_MEM_PDN_SEL_MASK 0x1 |
| #define MT6338_AUDIO_CO_MEM_PDN_SEL_SHIFT 2 |
| #define MT6338_DCCLK1_GEN_ON_ADDR \ |
| MT6338_AFE_DCCLK1_CFG0 |
| #define MT6338_DCCLK1_GEN_ON_MASK 0x1 |
| #define MT6338_DCCLK1_GEN_ON_SHIFT 0 |
| #define MT6338_DCCLK1_PDN_ADDR \ |
| MT6338_AFE_DCCLK1_CFG0 |
| #define MT6338_DCCLK1_PDN_MASK 0x1 |
| #define MT6338_DCCLK1_PDN_SHIFT 1 |
| #define MT6338_DCCLK1_REF_CK_SEL_ADDR \ |
| MT6338_AFE_DCCLK1_CFG0 |
| #define MT6338_DCCLK1_REF_CK_SEL_MASK 0x3 |
| #define MT6338_DCCLK1_REF_CK_SEL_SHIFT 2 |
| #define MT6338_DCCLK1_INV_ADDR \ |
| MT6338_AFE_DCCLK1_CFG0 |
| #define MT6338_DCCLK1_INV_MASK 0x1 |
| #define MT6338_DCCLK1_INV_SHIFT 4 |
| #define MT6338_DCCLK1_DIV_L_ADDR \ |
| MT6338_AFE_DCCLK1_CFG0 |
| #define MT6338_DCCLK1_DIV_L_MASK 0x7 |
| #define MT6338_DCCLK1_DIV_L_SHIFT 5 |
| #define MT6338_DCCLK1_DIV_H_ADDR \ |
| MT6338_AFE_DCCLK1_CFG1 |
| #define MT6338_DCCLK1_DIV_H_MASK 0xFF |
| #define MT6338_DCCLK1_DIV_H_SHIFT 0 |
| #define MT6338_DCCLK1_PHASE_SEL_ADDR \ |
| MT6338_AFE_DCCLK1_CFG2 |
| #define MT6338_DCCLK1_PHASE_SEL_MASK 0xF |
| #define MT6338_DCCLK1_PHASE_SEL_SHIFT 0 |
| #define MT6338_DCCLK1_RESYNC_BYPASS_ADDR \ |
| MT6338_AFE_DCCLK1_CFG2 |
| #define MT6338_DCCLK1_RESYNC_BYPASS_MASK 0x1 |
| #define MT6338_DCCLK1_RESYNC_BYPASS_SHIFT 4 |
| #define MT6338_DCCLK1_RESYNC_SRC_CK_INV_ADDR \ |
| MT6338_AFE_DCCLK1_CFG2 |
| #define MT6338_DCCLK1_RESYNC_SRC_CK_INV_MASK 0x1 |
| #define MT6338_DCCLK1_RESYNC_SRC_CK_INV_SHIFT 5 |
| #define MT6338_DCCLK1_RESYNC_SRC_SEL_ADDR \ |
| MT6338_AFE_DCCLK1_CFG2 |
| #define MT6338_DCCLK1_RESYNC_SRC_SEL_MASK 0x3 |
| #define MT6338_DCCLK1_RESYNC_SRC_SEL_SHIFT 6 |
| #define MT6338_DCCLK2_GEN_ON_ADDR \ |
| MT6338_AFE_DCCLK2_CFG0 |
| #define MT6338_DCCLK2_GEN_ON_MASK 0x1 |
| #define MT6338_DCCLK2_GEN_ON_SHIFT 0 |
| #define MT6338_DCCLK2_PDN_ADDR \ |
| MT6338_AFE_DCCLK2_CFG0 |
| #define MT6338_DCCLK2_PDN_MASK 0x1 |
| #define MT6338_DCCLK2_PDN_SHIFT 1 |
| #define MT6338_DCCLK2_REF_CK_SEL_ADDR \ |
| MT6338_AFE_DCCLK2_CFG0 |
| #define MT6338_DCCLK2_REF_CK_SEL_MASK 0x3 |
| #define MT6338_DCCLK2_REF_CK_SEL_SHIFT 2 |
| #define MT6338_DCCLK2_INV_ADDR \ |
| MT6338_AFE_DCCLK2_CFG0 |
| #define MT6338_DCCLK2_INV_MASK 0x1 |
| #define MT6338_DCCLK2_INV_SHIFT 4 |
| #define MT6338_DCCLK2_DIV_L_ADDR \ |
| MT6338_AFE_DCCLK2_CFG0 |
| #define MT6338_DCCLK2_DIV_L_MASK 0x7 |
| #define MT6338_DCCLK2_DIV_L_SHIFT 5 |
| #define MT6338_DCCLK2_DIV_H_ADDR \ |
| MT6338_AFE_DCCLK2_CFG1 |
| #define MT6338_DCCLK2_DIV_H_MASK 0xFF |
| #define MT6338_DCCLK2_DIV_H_SHIFT 0 |
| #define MT6338_DCCLK2_PHASE_SEL_ADDR \ |
| MT6338_AFE_DCCLK2_CFG2 |
| #define MT6338_DCCLK2_PHASE_SEL_MASK 0xF |
| #define MT6338_DCCLK2_PHASE_SEL_SHIFT 0 |
| #define MT6338_DCCLK2_RESYNC_BYPASS_ADDR \ |
| MT6338_AFE_DCCLK2_CFG2 |
| #define MT6338_DCCLK2_RESYNC_BYPASS_MASK 0x1 |
| #define MT6338_DCCLK2_RESYNC_BYPASS_SHIFT 4 |
| #define MT6338_DCCLK2_RESYNC_SRC_CK_INV_ADDR \ |
| MT6338_AFE_DCCLK2_CFG2 |
| #define MT6338_DCCLK2_RESYNC_SRC_CK_INV_MASK 0x1 |
| #define MT6338_DCCLK2_RESYNC_SRC_CK_INV_SHIFT 5 |
| #define MT6338_DCCLK2_RESYNC_SRC_SEL_ADDR \ |
| MT6338_AFE_DCCLK2_CFG2 |
| #define MT6338_DCCLK2_RESYNC_SRC_SEL_MASK 0x3 |
| #define MT6338_DCCLK2_RESYNC_SRC_SEL_SHIFT 6 |
| #define MT6338_DCCLK3_GEN_ON_ADDR \ |
| MT6338_AFE_DCCLK3_CFG0 |
| #define MT6338_DCCLK3_GEN_ON_MASK 0x1 |
| #define MT6338_DCCLK3_GEN_ON_SHIFT 0 |
| #define MT6338_DCCLK3_PDN_ADDR \ |
| MT6338_AFE_DCCLK3_CFG0 |
| #define MT6338_DCCLK3_PDN_MASK 0x1 |
| #define MT6338_DCCLK3_PDN_SHIFT 1 |
| #define MT6338_DCCLK3_REF_CK_SEL_ADDR \ |
| MT6338_AFE_DCCLK3_CFG0 |
| #define MT6338_DCCLK3_REF_CK_SEL_MASK 0x3 |
| #define MT6338_DCCLK3_REF_CK_SEL_SHIFT 2 |
| #define MT6338_DCCLK3_INV_ADDR \ |
| MT6338_AFE_DCCLK3_CFG0 |
| #define MT6338_DCCLK3_INV_MASK 0x1 |
| #define MT6338_DCCLK3_INV_SHIFT 4 |
| #define MT6338_DCCLK3_DIV_L_ADDR \ |
| MT6338_AFE_DCCLK3_CFG0 |
| #define MT6338_DCCLK3_DIV_L_MASK 0x7 |
| #define MT6338_DCCLK3_DIV_L_SHIFT 5 |
| #define MT6338_DCCLK3_DIV_H_ADDR \ |
| MT6338_AFE_DCCLK3_CFG1 |
| #define MT6338_DCCLK3_DIV_H_MASK 0xFF |
| #define MT6338_DCCLK3_DIV_H_SHIFT 0 |
| #define MT6338_DCCLK3_PHASE_SEL_ADDR \ |
| MT6338_AFE_DCCLK3_CFG2 |
| #define MT6338_DCCLK3_PHASE_SEL_MASK 0xF |
| #define MT6338_DCCLK3_PHASE_SEL_SHIFT 0 |
| #define MT6338_DCCLK3_RESYNC_BYPASS_ADDR \ |
| MT6338_AFE_DCCLK3_CFG2 |
| #define MT6338_DCCLK3_RESYNC_BYPASS_MASK 0x1 |
| #define MT6338_DCCLK3_RESYNC_BYPASS_SHIFT 4 |
| #define MT6338_DCCLK3_RESYNC_SRC_CK_INV_ADDR \ |
| MT6338_AFE_DCCLK3_CFG2 |
| #define MT6338_DCCLK3_RESYNC_SRC_CK_INV_MASK 0x1 |
| #define MT6338_DCCLK3_RESYNC_SRC_CK_INV_SHIFT 5 |
| #define MT6338_DCCLK3_RESYNC_SRC_SEL_ADDR \ |
| MT6338_AFE_DCCLK3_CFG2 |
| #define MT6338_DCCLK3_RESYNC_SRC_SEL_MASK 0x3 |
| #define MT6338_DCCLK3_RESYNC_SRC_SEL_SHIFT 6 |
| #define MT6338_DCCLK4_GEN_ON_ADDR \ |
| MT6338_AFE_DCCLK4_CFG0 |
| #define MT6338_DCCLK4_GEN_ON_MASK 0x1 |
| #define MT6338_DCCLK4_GEN_ON_SHIFT 0 |
| #define MT6338_DCCLK4_PDN_ADDR \ |
| MT6338_AFE_DCCLK4_CFG0 |
| #define MT6338_DCCLK4_PDN_MASK 0x1 |
| #define MT6338_DCCLK4_PDN_SHIFT 1 |
| #define MT6338_DCCLK4_REF_CK_SEL_ADDR \ |
| MT6338_AFE_DCCLK4_CFG0 |
| #define MT6338_DCCLK4_REF_CK_SEL_MASK 0x3 |
| #define MT6338_DCCLK4_REF_CK_SEL_SHIFT 2 |
| #define MT6338_DCCLK4_INV_ADDR \ |
| MT6338_AFE_DCCLK4_CFG0 |
| #define MT6338_DCCLK4_INV_MASK 0x1 |
| #define MT6338_DCCLK4_INV_SHIFT 4 |
| #define MT6338_DCCLK4_DIV_L_ADDR \ |
| MT6338_AFE_DCCLK4_CFG0 |
| #define MT6338_DCCLK4_DIV_L_MASK 0x7 |
| #define MT6338_DCCLK4_DIV_L_SHIFT 5 |
| #define MT6338_DCCLK4_DIV_H_ADDR \ |
| MT6338_AFE_DCCLK4_CFG1 |
| #define MT6338_DCCLK4_DIV_H_MASK 0xFF |
| #define MT6338_DCCLK4_DIV_H_SHIFT 0 |
| #define MT6338_DCCLK4_PHASE_SEL_ADDR \ |
| MT6338_AFE_DCCLK4_CFG2 |
| #define MT6338_DCCLK4_PHASE_SEL_MASK 0xF |
| #define MT6338_DCCLK4_PHASE_SEL_SHIFT 0 |
| #define MT6338_DCCLK4_RESYNC_BYPASS_ADDR \ |
| MT6338_AFE_DCCLK4_CFG2 |
| #define MT6338_DCCLK4_RESYNC_BYPASS_MASK 0x1 |
| #define MT6338_DCCLK4_RESYNC_BYPASS_SHIFT 4 |
| #define MT6338_DCCLK4_RESYNC_SRC_CK_INV_ADDR \ |
| MT6338_AFE_DCCLK4_CFG2 |
| #define MT6338_DCCLK4_RESYNC_SRC_CK_INV_MASK 0x1 |
| #define MT6338_DCCLK4_RESYNC_SRC_CK_INV_SHIFT 5 |
| #define MT6338_DCCLK4_RESYNC_SRC_SEL_ADDR \ |
| MT6338_AFE_DCCLK4_CFG2 |
| #define MT6338_DCCLK4_RESYNC_SRC_SEL_MASK 0x3 |
| #define MT6338_DCCLK4_RESYNC_SRC_SEL_SHIFT 6 |
| #define MT6338_DIGMIC_TESTCK_SEL_ADDR \ |
| MT6338_AO_AFUNC_AUD_CON3_L |
| #define MT6338_DIGMIC_TESTCK_SEL_MASK 0x1 |
| #define MT6338_DIGMIC_TESTCK_SEL_SHIFT 0 |
| #define MT6338_DIGMIC_TESTCK_SRC_SEL_ADDR \ |
| MT6338_AO_AFUNC_AUD_CON3_L |
| #define MT6338_DIGMIC_TESTCK_SRC_SEL_MASK 0x7 |
| #define MT6338_DIGMIC_TESTCK_SRC_SEL_SHIFT 4 |
| #define MT6338_UL_FIFO_TESTIN_ADDR \ |
| MT6338_AO_AFUNC_AUD_CON4_H |
| #define MT6338_UL_FIFO_TESTIN_MASK 0x1F |
| #define MT6338_UL_FIFO_TESTIN_SHIFT 1 |
| #define MT6338_UL_FIFO_WDATA_TESTSRC_SEL_ADDR \ |
| MT6338_AO_AFUNC_AUD_CON4_L |
| #define MT6338_UL_FIFO_WDATA_TESTSRC_SEL_MASK 0x1 |
| #define MT6338_UL_FIFO_WDATA_TESTSRC_SEL_SHIFT 4 |
| #define MT6338_UL_FIFO_WDATA_TESTEN_ADDR \ |
| MT6338_AO_AFUNC_AUD_CON4_L |
| #define MT6338_UL_FIFO_WDATA_TESTEN_MASK 0x1 |
| #define MT6338_UL_FIFO_WDATA_TESTEN_SHIFT 5 |
| #define MT6338_UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_ADDR \ |
| MT6338_AO_AFUNC_AUD_CON4_L |
| #define MT6338_UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK 0x1 |
| #define MT6338_UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_SHIFT 6 |
| #define MT6338_UL2_DIGMIC_TESTCK_SEL_ADDR \ |
| MT6338_AO_AFUNC_AUD_CON7_H |
| #define MT6338_UL2_DIGMIC_TESTCK_SEL_MASK 0x1 |
| #define MT6338_UL2_DIGMIC_TESTCK_SEL_SHIFT 1 |
| #define MT6338_UL2_DIGMIC_TESTCK_SRC_SEL_ADDR \ |
| MT6338_AO_AFUNC_AUD_CON7_H |
| #define MT6338_UL2_DIGMIC_TESTCK_SRC_SEL_MASK 0x7 |
| #define MT6338_UL2_DIGMIC_TESTCK_SRC_SEL_SHIFT 2 |
| #define MT6338_UL2_FIFO_WDATA_TESTSRC_SEL_ADDR \ |
| MT6338_AO_AFUNC_AUD_CON7_L |
| #define MT6338_UL2_FIFO_WDATA_TESTSRC_SEL_MASK 0x1 |
| #define MT6338_UL2_FIFO_WDATA_TESTSRC_SEL_SHIFT 4 |
| #define MT6338_UL2_FIFO_WDATA_TESTEN_ADDR \ |
| MT6338_AO_AFUNC_AUD_CON7_L |
| #define MT6338_UL2_FIFO_WDATA_TESTEN_MASK 0x1 |
| #define MT6338_UL2_FIFO_WDATA_TESTEN_SHIFT 5 |
| #define MT6338_UL2_FIFO_DIGMIC_WDATA_TESTSRC_SEL_ADDR \ |
| MT6338_AO_AFUNC_AUD_CON7_L |
| #define MT6338_UL2_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK 0x1 |
| #define MT6338_UL2_FIFO_DIGMIC_WDATA_TESTSRC_SEL_SHIFT 6 |
| #define MT6338_RG_DMIC_ADC3_SOURCE_SEL_ADDR \ |
| MT6338_AO_AFE_DMIC_ARRAY_CFG |
| #define MT6338_RG_DMIC_ADC3_SOURCE_SEL_MASK 0x3 |
| #define MT6338_RG_DMIC_ADC3_SOURCE_SEL_SHIFT 0 |
| #define MT6338_RG_DMIC_ADC2_SOURCE_SEL_ADDR \ |
| MT6338_AO_AFE_DMIC_ARRAY_CFG |
| #define MT6338_RG_DMIC_ADC2_SOURCE_SEL_MASK 0x3 |
| #define MT6338_RG_DMIC_ADC2_SOURCE_SEL_SHIFT 2 |
| #define MT6338_RG_DMIC_ADC1_SOURCE_SEL_ADDR \ |
| MT6338_AO_AFE_DMIC_ARRAY_CFG |
| #define MT6338_RG_DMIC_ADC1_SOURCE_SEL_MASK 0x3 |
| #define MT6338_RG_DMIC_ADC1_SOURCE_SEL_SHIFT 4 |
| #define MT6338_RG_DMIC_ADC0_SOURCE_SEL_ADDR \ |
| MT6338_AO_AFE_DMIC_ARRAY_CFG |
| #define MT6338_RG_DMIC_ADC0_SOURCE_SEL_MASK 0x3 |
| #define MT6338_RG_DMIC_ADC0_SOURCE_SEL_SHIFT 6 |
| #define MT6338_RG_AMIC_UL_ADC_CLK_SEL_ADDR \ |
| MT6338_AO_AFE_ADC_ASYNC_FIFO_CFG |
| #define MT6338_RG_AMIC_UL_ADC_CLK_SEL_MASK 0x1 |
| #define MT6338_RG_AMIC_UL_ADC_CLK_SEL_SHIFT 3 |
| #define MT6338_PDN_ADC_CTL_ADDR \ |
| MT6338_AO_AUDIO_TOP_CON0 |
| #define MT6338_PDN_ADC_CTL_MASK 0x1 |
| #define MT6338_PDN_ADC_CTL_SHIFT 5 |
| #define MT6338_AUDIO_DIG_ANA_ID_ADDR \ |
| MT6338_AUDIO_DIG_DSN_ID |
| #define MT6338_AUDIO_DIG_ANA_ID_MASK 0xFF |
| #define MT6338_AUDIO_DIG_ANA_ID_SHIFT 0 |
| #define MT6338_AUDIO_DIG_DIG_ID_ADDR \ |
| MT6338_AUDIO_DIG_DSN_ID_H |
| #define MT6338_AUDIO_DIG_DIG_ID_MASK 0xFF |
| #define MT6338_AUDIO_DIG_DIG_ID_SHIFT 0 |
| #define MT6338_AUDIO_DIG_ANA_MINOR_REV_ADDR \ |
| MT6338_AUDIO_DIG_DSN_REV0 |
| #define MT6338_AUDIO_DIG_ANA_MINOR_REV_MASK 0xF |
| #define MT6338_AUDIO_DIG_ANA_MINOR_REV_SHIFT 0 |
| #define MT6338_AUDIO_DIG_ANA_MAJOR_REV_ADDR \ |
| MT6338_AUDIO_DIG_DSN_REV0 |
| #define MT6338_AUDIO_DIG_ANA_MAJOR_REV_MASK 0xF |
| #define MT6338_AUDIO_DIG_ANA_MAJOR_REV_SHIFT 4 |
| #define MT6338_AUDIO_DIG_DIG_MINOR_REV_ADDR \ |
| MT6338_AUDIO_DIG_DSN_REV0_H |
| #define MT6338_AUDIO_DIG_DIG_MINOR_REV_MASK 0xF |
| #define MT6338_AUDIO_DIG_DIG_MINOR_REV_SHIFT 0 |
| #define MT6338_AUDIO_DIG_DIG_MAJOR_REV_ADDR \ |
| MT6338_AUDIO_DIG_DSN_REV0_H |
| #define MT6338_AUDIO_DIG_DIG_MAJOR_REV_MASK 0xF |
| #define MT6338_AUDIO_DIG_DIG_MAJOR_REV_SHIFT 4 |
| #define MT6338_AUDIO_DIG_DSN_CBS_ADDR \ |
| MT6338_AUDIO_DIG_DSN_DBI |
| #define MT6338_AUDIO_DIG_DSN_CBS_MASK 0x3 |
| #define MT6338_AUDIO_DIG_DSN_CBS_SHIFT 0 |
| #define MT6338_AUDIO_DIG_DSN_BIX_ADDR \ |
| MT6338_AUDIO_DIG_DSN_DBI |
| #define MT6338_AUDIO_DIG_DSN_BIX_MASK 0x3 |
| #define MT6338_AUDIO_DIG_DSN_BIX_SHIFT 2 |
| #define MT6338_AUDIO_DIG_1_ESP_ADDR \ |
| MT6338_AUDIO_DIG_DSN_DBI_H |
| #define MT6338_AUDIO_DIG_1_ESP_MASK 0xFF |
| #define MT6338_AUDIO_DIG_1_ESP_SHIFT 0 |
| #define MT6338_AUDIO_DIG_DSN_FPI_ADDR \ |
| MT6338_AUDIO_DIG_DSN_DXI |
| #define MT6338_AUDIO_DIG_DSN_FPI_MASK 0xFF |
| #define MT6338_AUDIO_DIG_DSN_FPI_SHIFT 0 |
| #define MT6338_PDN_RESERVED_ADDR \ |
| MT6338_AUDIO_TOP_CON0 |
| #define MT6338_PDN_RESERVED_MASK 0x1 |
| #define MT6338_PDN_RESERVED_SHIFT 0 |
| #define MT6338_PDN_AFE_TESTMODEL_CTL_ADDR \ |
| MT6338_AUDIO_TOP_CON0 |
| #define MT6338_PDN_AFE_TESTMODEL_CTL_MASK 0x1 |
| #define MT6338_PDN_AFE_TESTMODEL_CTL_SHIFT 1 |
| #define MT6338_PWR_CLK_DIS_CTL_ADDR \ |
| MT6338_AUDIO_TOP_CON0 |
| #define MT6338_PWR_CLK_DIS_CTL_MASK 0x1 |
| #define MT6338_PWR_CLK_DIS_CTL_SHIFT 2 |
| #define MT6338_PDN_I2S_DL_CTL_ADDR \ |
| MT6338_AUDIO_TOP_CON0 |
| #define MT6338_PDN_I2S_DL_CTL_MASK 0x1 |
| #define MT6338_PDN_I2S_DL_CTL_SHIFT 3 |
| #define MT6338_PDN_ADDA6_ADC_CTL_ADDR \ |
| MT6338_AUDIO_TOP_CON0 |
| #define MT6338_PDN_ADDA6_ADC_CTL_MASK 0x1 |
| #define MT6338_PDN_ADDA6_ADC_CTL_SHIFT 4 |
| #define MT6338_PDN_DAC_CTL_ADDR \ |
| MT6338_AUDIO_TOP_CON0 |
| #define MT6338_PDN_DAC_CTL_MASK 0x1 |
| #define MT6338_PDN_DAC_CTL_SHIFT 6 |
| #define MT6338_PDN_AFE_CTL_ADDR \ |
| MT6338_AUDIO_TOP_CON0 |
| #define MT6338_PDN_AFE_CTL_MASK 0x1 |
| #define MT6338_PDN_AFE_CTL_SHIFT 7 |
| #define MT6338_PDN_GASRC1_CTL_ADDR \ |
| MT6338_AUDIO_TOP_CON1 |
| #define MT6338_PDN_GASRC1_CTL_MASK 0x1 |
| #define MT6338_PDN_GASRC1_CTL_SHIFT 0 |
| #define MT6338_PDN_GASRC2_CTL_ADDR \ |
| MT6338_AUDIO_TOP_CON1 |
| #define MT6338_PDN_GASRC2_CTL_MASK 0x1 |
| #define MT6338_PDN_GASRC2_CTL_SHIFT 1 |
| #define MT6338_PDN_GASRC3_CTL_ADDR \ |
| MT6338_AUDIO_TOP_CON1 |
| #define MT6338_PDN_GASRC3_CTL_MASK 0x1 |
| #define MT6338_PDN_GASRC3_CTL_SHIFT 2 |
| #define MT6338_PDN_GASRC4_CTL_ADDR \ |
| MT6338_AUDIO_TOP_CON1 |
| #define MT6338_PDN_GASRC4_CTL_MASK 0x1 |
| #define MT6338_PDN_GASRC4_CTL_SHIFT 3 |
| #define MT6338_PDN_ADDA6_ADC_HIRES_CTL_ADDR \ |
| MT6338_AUDIO_TOP_CON1 |
| #define MT6338_PDN_ADDA6_ADC_HIRES_CTL_MASK 0x1 |
| #define MT6338_PDN_ADDA6_ADC_HIRES_CTL_SHIFT 4 |
| #define MT6338_PDN_ADC_HIRES_CTL_ADDR \ |
| MT6338_AUDIO_TOP_CON1 |
| #define MT6338_PDN_ADC_HIRES_CTL_MASK 0x1 |
| #define MT6338_PDN_ADC_HIRES_CTL_SHIFT 5 |
| #define MT6338_PDN_TDM_CTL_ADDR \ |
| MT6338_AUDIO_TOP_CON1 |
| #define MT6338_PDN_TDM_CTL_MASK 0x1 |
| #define MT6338_PDN_TDM_CTL_SHIFT 6 |
| #define MT6338_PDN_STF_CTL_ADDR \ |
| MT6338_AUDIO_TOP_CON1 |
| #define MT6338_PDN_STF_CTL_MASK 0x1 |
| #define MT6338_PDN_STF_CTL_SHIFT 7 |
| #define MT6338_PDN_DAC2_CTL_ADDR \ |
| MT6338_AUDIO_TOP_CON2 |
| #define MT6338_PDN_DAC2_CTL_MASK 0x1 |
| #define MT6338_PDN_DAC2_CTL_SHIFT 0 |
| #define MT6338_PDN_DAC_HIRES_CTL_ADDR \ |
| MT6338_AUDIO_TOP_CON2 |
| #define MT6338_PDN_DAC_HIRES_CTL_MASK 0x1 |
| #define MT6338_PDN_DAC_HIRES_CTL_SHIFT 1 |
| #define MT6338_PDN_DAC2_HIRES_CTL_ADDR \ |
| MT6338_AUDIO_TOP_CON2 |
| #define MT6338_PDN_DAC2_HIRES_CTL_MASK 0x1 |
| #define MT6338_PDN_DAC2_HIRES_CTL_SHIFT 2 |
| #define MT6338_PDN_DAC_TML_CTL_ADDR \ |
| MT6338_AUDIO_TOP_CON2 |
| #define MT6338_PDN_DAC_TML_CTL_MASK 0x1 |
| #define MT6338_PDN_DAC_TML_CTL_SHIFT 3 |
| #define MT6338_PDN_DAC2_TML_CTL_ADDR \ |
| MT6338_AUDIO_TOP_CON2 |
| #define MT6338_PDN_DAC2_TML_CTL_MASK 0x1 |
| #define MT6338_PDN_DAC2_TML_CTL_SHIFT 4 |
| #define MT6338_PDN_DAC_PREDIS_CTL_ADDR \ |
| MT6338_AUDIO_TOP_CON2 |
| #define MT6338_PDN_DAC_PREDIS_CTL_MASK 0x1 |
| #define MT6338_PDN_DAC_PREDIS_CTL_SHIFT 5 |
| #define MT6338_PDN_DAC2_PREDIS_CTL_ADDR \ |
| MT6338_AUDIO_TOP_CON2 |
| #define MT6338_PDN_DAC2_PREDIS_CTL_MASK 0x1 |
| #define MT6338_PDN_DAC2_PREDIS_CTL_SHIFT 6 |
| #define MT6338_PDN_DAC_NLE_CTL_ADDR \ |
| MT6338_AUDIO_TOP_CON2 |
| #define MT6338_PDN_DAC_NLE_CTL_MASK 0x1 |
| #define MT6338_PDN_DAC_NLE_CTL_SHIFT 7 |
| #define MT6338_PDN_NCP_CTL_ADDR \ |
| MT6338_AUDIO_TOP_CON3 |
| #define MT6338_PDN_NCP_CTL_MASK 0x1 |
| #define MT6338_PDN_NCP_CTL_SHIFT 0 |
| #define MT6338_PDN_HW_GAIN_CTL_ADDR \ |
| MT6338_AUDIO_TOP_CON3 |
| #define MT6338_PDN_HW_GAIN_CTL_MASK 0x1 |
| #define MT6338_PDN_HW_GAIN_CTL_SHIFT 1 |
| #define MT6338_AFE_ON_ADDR \ |
| MT6338_AFE_TOP_CON0 |
| #define MT6338_AFE_ON_MASK 0x1 |
| #define MT6338_AFE_ON_SHIFT 0 |
| #define MT6338_DL_SINE_ON_ADDR \ |
| MT6338_AFE_TOP_CON0 |
| #define MT6338_DL_SINE_ON_MASK 0x1 |
| #define MT6338_DL_SINE_ON_SHIFT 1 |
| #define MT6338_AFE_MON_SEL_ADDR \ |
| MT6338_AFE_MON_DEBUG0 |
| #define MT6338_AFE_MON_SEL_MASK 0xFF |
| #define MT6338_AFE_MON_SEL_SHIFT 0 |
| #define MT6338_AUDIO_SYS_TOP_MON_SEL_ADDR \ |
| MT6338_AFE_MON_DEBUG1 |
| #define MT6338_AUDIO_SYS_TOP_MON_SEL_MASK 0x3F |
| #define MT6338_AUDIO_SYS_TOP_MON_SEL_SHIFT 0 |
| #define MT6338_AUDIO_SYS_TOP_MON_SWAP_ADDR \ |
| MT6338_AFE_MON_DEBUG1 |
| #define MT6338_AUDIO_SYS_TOP_MON_SWAP_MASK 0x3 |
| #define MT6338_AUDIO_SYS_TOP_MON_SWAP_SHIFT 6 |
| #define MT6338_AUDENC_ANA_ID_ADDR \ |
| MT6338_AUDENC_ANA_ID |
| #define MT6338_AUDENC_ANA_ID_MASK 0xFF |
| #define MT6338_AUDENC_ANA_ID_SHIFT 0 |
| #define MT6338_AUDENC_DIG_ID_ADDR \ |
| MT6338_AUDENC_DIG_ID |
| #define MT6338_AUDENC_DIG_ID_MASK 0xFF |
| #define MT6338_AUDENC_DIG_ID_SHIFT 0 |
| #define MT6338_AUDENC_ANA_MINOR_REV_ADDR \ |
| MT6338_AUDENC_ANA_REV |
| #define MT6338_AUDENC_ANA_MINOR_REV_MASK 0xF |
| #define MT6338_AUDENC_ANA_MINOR_REV_SHIFT 0 |
| #define MT6338_AUDENC_ANA_MAJOR_REV_ADDR \ |
| MT6338_AUDENC_ANA_REV |
| #define MT6338_AUDENC_ANA_MAJOR_REV_MASK 0xF |
| #define MT6338_AUDENC_ANA_MAJOR_REV_SHIFT 4 |
| #define MT6338_AUDENC_DIG_MINOR_REV_ADDR \ |
| MT6338_AUDENC_DIG_REV |
| #define MT6338_AUDENC_DIG_MINOR_REV_MASK 0xF |
| #define MT6338_AUDENC_DIG_MINOR_REV_SHIFT 0 |
| #define MT6338_AUDENC_DIG_MAJOR_REV_ADDR \ |
| MT6338_AUDENC_DIG_REV |
| #define MT6338_AUDENC_DIG_MAJOR_REV_MASK 0xF |
| #define MT6338_AUDENC_DIG_MAJOR_REV_SHIFT 4 |
| #define MT6338_AUDENC_CBS_ADDR \ |
| MT6338_AUDENC_DBI |
| #define MT6338_AUDENC_CBS_MASK 0x3 |
| #define MT6338_AUDENC_CBS_SHIFT 0 |
| #define MT6338_AUDENC_BIX_ADDR \ |
| MT6338_AUDENC_DBI |
| #define MT6338_AUDENC_BIX_MASK 0x3 |
| #define MT6338_AUDENC_BIX_SHIFT 2 |
| #define MT6338_AUDENC_ESP_ADDR \ |
| MT6338_AUDENC_ESP |
| #define MT6338_AUDENC_ESP_MASK 0xFF |
| #define MT6338_AUDENC_ESP_SHIFT 0 |
| #define MT6338_AUDENC_FPI_ADDR \ |
| MT6338_AUDENC_FPI |
| #define MT6338_AUDENC_FPI_MASK 0xFF |
| #define MT6338_AUDENC_FPI_SHIFT 0 |
| #define MT6338_AUDENC_DXI_ADDR \ |
| MT6338_AUDENC_DXI |
| #define MT6338_AUDENC_DXI_MASK 0xFF |
| #define MT6338_AUDENC_DXI_SHIFT 0 |
| #define MT6338_RG_AUDPREAMPLON_ADDR \ |
| MT6338_AUDENC_PMU_CON0 |
| #define MT6338_RG_AUDPREAMPLON_MASK 0x1 |
| #define MT6338_RG_AUDPREAMPLON_SHIFT 0 |
| #define MT6338_RG_AUDPREAMPLDCCEN_ADDR \ |
| MT6338_AUDENC_PMU_CON0 |
| #define MT6338_RG_AUDPREAMPLDCCEN_MASK 0x1 |
| #define MT6338_RG_AUDPREAMPLDCCEN_SHIFT 1 |
| #define MT6338_RG_AUDPREAMPLDCPRECHARGE_ADDR \ |
| MT6338_AUDENC_PMU_CON0 |
| #define MT6338_RG_AUDPREAMPLDCPRECHARGE_MASK 0x1 |
| #define MT6338_RG_AUDPREAMPLDCPRECHARGE_SHIFT 2 |
| #define MT6338_RG_AUDPREAMPLPGATEST_ADDR \ |
| MT6338_AUDENC_PMU_CON0 |
| #define MT6338_RG_AUDPREAMPLPGATEST_MASK 0x1 |
| #define MT6338_RG_AUDPREAMPLPGATEST_SHIFT 3 |
| #define MT6338_RG_AUDPREAMPLVSCALE_ADDR \ |
| MT6338_AUDENC_PMU_CON0 |
| #define MT6338_RG_AUDPREAMPLVSCALE_MASK 0x3 |
| #define MT6338_RG_AUDPREAMPLVSCALE_SHIFT 4 |
| #define MT6338_RG_AUDPREAMPLINPUTSEL_ADDR \ |
| MT6338_AUDENC_PMU_CON0 |
| #define MT6338_RG_AUDPREAMPLINPUTSEL_MASK 0x3 |
| #define MT6338_RG_AUDPREAMPLINPUTSEL_SHIFT 6 |
| #define MT6338_RG_AUDPREAMPLGAIN_ADDR \ |
| MT6338_AUDENC_PMU_CON1 |
| #define MT6338_RG_AUDPREAMPLGAIN_MASK 0xF |
| #define MT6338_RG_AUDPREAMPLGAIN_SHIFT 0 |
| #define MT6338_RG_AUDADCLPWRUP_ADDR \ |
| MT6338_AUDENC_PMU_CON1 |
| #define MT6338_RG_AUDADCLPWRUP_MASK 0x1 |
| #define MT6338_RG_AUDADCLPWRUP_SHIFT 4 |
| #define MT6338_RG_AUDADCLINPUTSEL_ADDR \ |
| MT6338_AUDENC_PMU_CON1 |
| #define MT6338_RG_AUDADCLINPUTSEL_MASK 0x3 |
| #define MT6338_RG_AUDADCLINPUTSEL_SHIFT 5 |
| #define MT6338_RG_AUDPREAMPRON_ADDR \ |
| MT6338_AUDENC_PMU_CON2 |
| #define MT6338_RG_AUDPREAMPRON_MASK 0x1 |
| #define MT6338_RG_AUDPREAMPRON_SHIFT 0 |
| #define MT6338_RG_AUDPREAMPRDCCEN_ADDR \ |
| MT6338_AUDENC_PMU_CON2 |
| #define MT6338_RG_AUDPREAMPRDCCEN_MASK 0x1 |
| #define MT6338_RG_AUDPREAMPRDCCEN_SHIFT 1 |
| #define MT6338_RG_AUDPREAMPRDCPRECHARGE_ADDR \ |
| MT6338_AUDENC_PMU_CON2 |
| #define MT6338_RG_AUDPREAMPRDCPRECHARGE_MASK 0x1 |
| #define MT6338_RG_AUDPREAMPRDCPRECHARGE_SHIFT 2 |
| #define MT6338_RG_AUDPREAMPRPGATEST_ADDR \ |
| MT6338_AUDENC_PMU_CON2 |
| #define MT6338_RG_AUDPREAMPRPGATEST_MASK 0x1 |
| #define MT6338_RG_AUDPREAMPRPGATEST_SHIFT 3 |
| #define MT6338_RG_AUDPREAMPRVSCALE_ADDR \ |
| MT6338_AUDENC_PMU_CON2 |
| #define MT6338_RG_AUDPREAMPRVSCALE_MASK 0x3 |
| #define MT6338_RG_AUDPREAMPRVSCALE_SHIFT 4 |
| #define MT6338_RG_AUDPREAMPRINPUTSEL_ADDR \ |
| MT6338_AUDENC_PMU_CON2 |
| #define MT6338_RG_AUDPREAMPRINPUTSEL_MASK 0x3 |
| #define MT6338_RG_AUDPREAMPRINPUTSEL_SHIFT 6 |
| #define MT6338_RG_AUDPREAMPRGAIN_ADDR \ |
| MT6338_AUDENC_PMU_CON3 |
| #define MT6338_RG_AUDPREAMPRGAIN_MASK 0xF |
| #define MT6338_RG_AUDPREAMPRGAIN_SHIFT 0 |
| #define MT6338_RG_AUDADCRPWRUP_ADDR \ |
| MT6338_AUDENC_PMU_CON3 |
| #define MT6338_RG_AUDADCRPWRUP_MASK 0x1 |
| #define MT6338_RG_AUDADCRPWRUP_SHIFT 4 |
| #define MT6338_RG_AUDADCRINPUTSEL_ADDR \ |
| MT6338_AUDENC_PMU_CON3 |
| #define MT6338_RG_AUDADCRINPUTSEL_MASK 0x3 |
| #define MT6338_RG_AUDADCRINPUTSEL_SHIFT 5 |
| #define MT6338_RG_AUDPREAMP3ON_ADDR \ |
| MT6338_AUDENC_PMU_CON4 |
| #define MT6338_RG_AUDPREAMP3ON_MASK 0x1 |
| #define MT6338_RG_AUDPREAMP3ON_SHIFT 0 |
| #define MT6338_RG_AUDPREAMP3DCCEN_ADDR \ |
| MT6338_AUDENC_PMU_CON4 |
| #define MT6338_RG_AUDPREAMP3DCCEN_MASK 0x1 |
| #define MT6338_RG_AUDPREAMP3DCCEN_SHIFT 1 |
| #define MT6338_RG_AUDPREAMP3DCPRECHARGE_ADDR \ |
| MT6338_AUDENC_PMU_CON4 |
| #define MT6338_RG_AUDPREAMP3DCPRECHARGE_MASK 0x1 |
| #define MT6338_RG_AUDPREAMP3DCPRECHARGE_SHIFT 2 |
| #define MT6338_RG_AUDPREAMP3PGATEST_ADDR \ |
| MT6338_AUDENC_PMU_CON4 |
| #define MT6338_RG_AUDPREAMP3PGATEST_MASK 0x1 |
| #define MT6338_RG_AUDPREAMP3PGATEST_SHIFT 3 |
| #define MT6338_RG_AUDPREAMP3VSCALE_ADDR \ |
| MT6338_AUDENC_PMU_CON4 |
| #define MT6338_RG_AUDPREAMP3VSCALE_MASK 0x3 |
| #define MT6338_RG_AUDPREAMP3VSCALE_SHIFT 4 |
| #define MT6338_RG_AUDPREAMP3INPUTSEL_ADDR \ |
| MT6338_AUDENC_PMU_CON4 |
| #define MT6338_RG_AUDPREAMP3INPUTSEL_MASK 0x3 |
| #define MT6338_RG_AUDPREAMP3INPUTSEL_SHIFT 6 |
| #define MT6338_RG_AUDPREAMP3GAIN_ADDR \ |
| MT6338_AUDENC_PMU_CON5 |
| #define MT6338_RG_AUDPREAMP3GAIN_MASK 0xF |
| #define MT6338_RG_AUDPREAMP3GAIN_SHIFT 0 |
| #define MT6338_RG_AUDADC3PWRUP_ADDR \ |
| MT6338_AUDENC_PMU_CON5 |
| #define MT6338_RG_AUDADC3PWRUP_MASK 0x1 |
| #define MT6338_RG_AUDADC3PWRUP_SHIFT 4 |
| #define MT6338_RG_AUDADC3INPUTSEL_ADDR \ |
| MT6338_AUDENC_PMU_CON5 |
| #define MT6338_RG_AUDADC3INPUTSEL_MASK 0x3 |
| #define MT6338_RG_AUDADC3INPUTSEL_SHIFT 5 |
| #define MT6338_RG_AUDPREAMP4ON_ADDR \ |
| MT6338_AUDENC_PMU_CON6 |
| #define MT6338_RG_AUDPREAMP4ON_MASK 0x1 |
| #define MT6338_RG_AUDPREAMP4ON_SHIFT 0 |
| #define MT6338_RG_AUDPREAMP4DCCEN_ADDR \ |
| MT6338_AUDENC_PMU_CON6 |
| #define MT6338_RG_AUDPREAMP4DCCEN_MASK 0x1 |
| #define MT6338_RG_AUDPREAMP4DCCEN_SHIFT 1 |
| #define MT6338_RG_AUDPREAMP4DCPRECHARGE_ADDR \ |
| MT6338_AUDENC_PMU_CON6 |
| #define MT6338_RG_AUDPREAMP4DCPRECHARGE_MASK 0x1 |
| #define MT6338_RG_AUDPREAMP4DCPRECHARGE_SHIFT 2 |
| #define MT6338_RG_AUDPREAMP4PGATEST_ADDR \ |
| MT6338_AUDENC_PMU_CON6 |
| #define MT6338_RG_AUDPREAMP4PGATEST_MASK 0x1 |
| #define MT6338_RG_AUDPREAMP4PGATEST_SHIFT 3 |
| #define MT6338_RG_AUDPREAMP4VSCALE_ADDR \ |
| MT6338_AUDENC_PMU_CON6 |
| #define MT6338_RG_AUDPREAMP4VSCALE_MASK 0x3 |
| #define MT6338_RG_AUDPREAMP4VSCALE_SHIFT 4 |
| #define MT6338_RG_AUDPREAMP4INPUTSEL_ADDR \ |
| MT6338_AUDENC_PMU_CON6 |
| #define MT6338_RG_AUDPREAMP4INPUTSEL_MASK 0x3 |
| #define MT6338_RG_AUDPREAMP4INPUTSEL_SHIFT 6 |
| #define MT6338_RG_AUDPREAMP4GAIN_ADDR \ |
| MT6338_AUDENC_PMU_CON7 |
| #define MT6338_RG_AUDPREAMP4GAIN_MASK 0xF |
| #define MT6338_RG_AUDPREAMP4GAIN_SHIFT 0 |
| #define MT6338_RG_AUDADC4PWRUP_ADDR \ |
| MT6338_AUDENC_PMU_CON7 |
| #define MT6338_RG_AUDADC4PWRUP_MASK 0x1 |
| #define MT6338_RG_AUDADC4PWRUP_SHIFT 4 |
| #define MT6338_RG_AUDADC4INPUTSEL_ADDR \ |
| MT6338_AUDENC_PMU_CON7 |
| #define MT6338_RG_AUDADC4INPUTSEL_MASK 0x3 |
| #define MT6338_RG_AUDADC4INPUTSEL_SHIFT 5 |
| #define MT6338_RG_AUDULHALFBIAS_ADDR \ |
| MT6338_AUDENC_PMU_CON8 |
| #define MT6338_RG_AUDULHALFBIAS_MASK 0x1 |
| #define MT6338_RG_AUDULHALFBIAS_SHIFT 0 |
| #define MT6338_RG_AUDGLBVOWLPWEN_ADDR \ |
| MT6338_AUDENC_PMU_CON8 |
| #define MT6338_RG_AUDGLBVOWLPWEN_MASK 0x1 |
| #define MT6338_RG_AUDGLBVOWLPWEN_SHIFT 1 |
| #define MT6338_RG_AUDPREAMPLPEN_ADDR \ |
| MT6338_AUDENC_PMU_CON8 |
| #define MT6338_RG_AUDPREAMPLPEN_MASK 0x1 |
| #define MT6338_RG_AUDPREAMPLPEN_SHIFT 2 |
| #define MT6338_RG_AUDADC1STSTAGELPEN_ADDR \ |
| MT6338_AUDENC_PMU_CON8 |
| #define MT6338_RG_AUDADC1STSTAGELPEN_MASK 0x1 |
| #define MT6338_RG_AUDADC1STSTAGELPEN_SHIFT 3 |
| #define MT6338_RG_AUDADC2NDSTAGELPEN_ADDR \ |
| MT6338_AUDENC_PMU_CON8 |
| #define MT6338_RG_AUDADC2NDSTAGELPEN_MASK 0x1 |
| #define MT6338_RG_AUDADC2NDSTAGELPEN_SHIFT 4 |
| #define MT6338_RG_AUDADCFLASHLPEN_ADDR \ |
| MT6338_AUDENC_PMU_CON8 |
| #define MT6338_RG_AUDADCFLASHLPEN_MASK 0x1 |
| #define MT6338_RG_AUDADCFLASHLPEN_SHIFT 5 |
| #define MT6338_RG_AUDPREAMPIDDTEST_ADDR \ |
| MT6338_AUDENC_PMU_CON8 |
| #define MT6338_RG_AUDPREAMPIDDTEST_MASK 0x3 |
| #define MT6338_RG_AUDPREAMPIDDTEST_SHIFT 6 |
| #define MT6338_RG_AUDADC1STSTAGEIDDTEST_ADDR \ |
| MT6338_AUDENC_PMU_CON9 |
| #define MT6338_RG_AUDADC1STSTAGEIDDTEST_MASK 0x3 |
| #define MT6338_RG_AUDADC1STSTAGEIDDTEST_SHIFT 0 |
| #define MT6338_RG_AUDADC2NDSTAGEIDDTEST_ADDR \ |
| MT6338_AUDENC_PMU_CON9 |
| #define MT6338_RG_AUDADC2NDSTAGEIDDTEST_MASK 0x3 |
| #define MT6338_RG_AUDADC2NDSTAGEIDDTEST_SHIFT 2 |
| #define MT6338_RG_AUDADCREFBUFIDDTEST_ADDR \ |
| MT6338_AUDENC_PMU_CON9 |
| #define MT6338_RG_AUDADCREFBUFIDDTEST_MASK 0x3 |
| #define MT6338_RG_AUDADCREFBUFIDDTEST_SHIFT 4 |
| #define MT6338_RG_AUDADCFLASHIDDTEST_ADDR \ |
| MT6338_AUDENC_PMU_CON9 |
| #define MT6338_RG_AUDADCFLASHIDDTEST_MASK 0x3 |
| #define MT6338_RG_AUDADCFLASHIDDTEST_SHIFT 6 |
| #define MT6338_RG_AUDPREAMPLNEGGAIN_ADDR \ |
| MT6338_AUDENC_PMU_CON10 |
| #define MT6338_RG_AUDPREAMPLNEGGAIN_MASK 0x3 |
| #define MT6338_RG_AUDPREAMPLNEGGAIN_SHIFT 0 |
| #define MT6338_RG_AUDPREAMPRNEGGAIN_ADDR \ |
| MT6338_AUDENC_PMU_CON10 |
| #define MT6338_RG_AUDPREAMPRNEGGAIN_MASK 0x3 |
| #define MT6338_RG_AUDPREAMPRNEGGAIN_SHIFT 2 |
| #define MT6338_RG_AUDPREAMP3NEGGAIN_ADDR \ |
| MT6338_AUDENC_PMU_CON10 |
| #define MT6338_RG_AUDPREAMP3NEGGAIN_MASK 0x3 |
| #define MT6338_RG_AUDPREAMP3NEGGAIN_SHIFT 4 |
| #define MT6338_RG_AUDPREAMP4NEGGAIN_ADDR \ |
| MT6338_AUDENC_PMU_CON10 |
| #define MT6338_RG_AUDPREAMP4NEGGAIN_MASK 0x3 |
| #define MT6338_RG_AUDPREAMP4NEGGAIN_SHIFT 6 |
| #define MT6338_RG_AUDPREAMPL_CARA_18_ADDR \ |
| MT6338_AUDENC_PMU_CON11 |
| #define MT6338_RG_AUDPREAMPL_CARA_18_MASK 0x1 |
| #define MT6338_RG_AUDPREAMPL_CARA_18_SHIFT 0 |
| #define MT6338_RG_AUDPREAMPL_CARA_24_ADDR \ |
| MT6338_AUDENC_PMU_CON11 |
| #define MT6338_RG_AUDPREAMPL_CARA_24_MASK 0x1 |
| #define MT6338_RG_AUDPREAMPL_CARA_24_SHIFT 1 |
| #define MT6338_RG_AUDPREAMPR_CARA_18_ADDR \ |
| MT6338_AUDENC_PMU_CON11 |
| #define MT6338_RG_AUDPREAMPR_CARA_18_MASK 0x1 |
| #define MT6338_RG_AUDPREAMPR_CARA_18_SHIFT 2 |
| #define MT6338_RG_AUDPREAMPR_CARA_24_ADDR \ |
| MT6338_AUDENC_PMU_CON11 |
| #define MT6338_RG_AUDPREAMPR_CARA_24_MASK 0x1 |
| #define MT6338_RG_AUDPREAMPR_CARA_24_SHIFT 3 |
| #define MT6338_RG_AUDPREAMP3_CARA_18_ADDR \ |
| MT6338_AUDENC_PMU_CON11 |
| #define MT6338_RG_AUDPREAMP3_CARA_18_MASK 0x1 |
| #define MT6338_RG_AUDPREAMP3_CARA_18_SHIFT 4 |
| #define MT6338_RG_AUDPREAMP3_CARA_24_ADDR \ |
| MT6338_AUDENC_PMU_CON11 |
| #define MT6338_RG_AUDPREAMP3_CARA_24_MASK 0x1 |
| #define MT6338_RG_AUDPREAMP3_CARA_24_SHIFT 5 |
| #define MT6338_RG_AUDPREAMP4_CARA_18_ADDR \ |
| MT6338_AUDENC_PMU_CON11 |
| #define MT6338_RG_AUDPREAMP4_CARA_18_MASK 0x1 |
| #define MT6338_RG_AUDPREAMP4_CARA_18_SHIFT 6 |
| #define MT6338_RG_AUDPREAMP4_CARA_24_ADDR \ |
| MT6338_AUDENC_PMU_CON11 |
| #define MT6338_RG_AUDPREAMP4_CARA_24_MASK 0x1 |
| #define MT6338_RG_AUDPREAMP4_CARA_24_SHIFT 7 |
| #define MT6338_RG_AUDPREAMPLMODE_ADDR \ |
| MT6338_AUDENC_PMU_CON12 |
| #define MT6338_RG_AUDPREAMPLMODE_MASK 0x7 |
| #define MT6338_RG_AUDPREAMPLMODE_SHIFT 0 |
| #define MT6338_RG_AUDPREAMPRMODE_ADDR \ |
| MT6338_AUDENC_PMU_CON12 |
| #define MT6338_RG_AUDPREAMPRMODE_MASK 0x7 |
| #define MT6338_RG_AUDPREAMPRMODE_SHIFT 4 |
| #define MT6338_RG_AUDPREAMP3MODE_ADDR \ |
| MT6338_AUDENC_PMU_CON13 |
| #define MT6338_RG_AUDPREAMP3MODE_MASK 0x7 |
| #define MT6338_RG_AUDPREAMP3MODE_SHIFT 0 |
| #define MT6338_RG_AUDPREAMP4MODE_ADDR \ |
| MT6338_AUDENC_PMU_CON13 |
| #define MT6338_RG_AUDPREAMP4MODE_MASK 0x7 |
| #define MT6338_RG_AUDPREAMP4MODE_SHIFT 4 |
| #define MT6338_RG_AUDADCLMODE_ADDR \ |
| MT6338_AUDENC_PMU_CON14 |
| #define MT6338_RG_AUDADCLMODE_MASK 0x7 |
| #define MT6338_RG_AUDADCLMODE_SHIFT 0 |
| #define MT6338_RG_AUDADCL_VOW_ADDR \ |
| MT6338_AUDENC_PMU_CON14 |
| #define MT6338_RG_AUDADCL_VOW_MASK 0x1 |
| #define MT6338_RG_AUDADCL_VOW_SHIFT 3 |
| #define MT6338_RG_AUDADCRMODE_ADDR \ |
| MT6338_AUDENC_PMU_CON14 |
| #define MT6338_RG_AUDADCRMODE_MASK 0x7 |
| #define MT6338_RG_AUDADCRMODE_SHIFT 4 |
| #define MT6338_RG_AUDADCR_VOW_ADDR \ |
| MT6338_AUDENC_PMU_CON14 |
| #define MT6338_RG_AUDADCR_VOW_MASK 0x1 |
| #define MT6338_RG_AUDADCR_VOW_SHIFT 7 |
| #define MT6338_RG_AUDADC3MODE_ADDR \ |
| MT6338_AUDENC_PMU_CON15 |
| #define MT6338_RG_AUDADC3MODE_MASK 0x7 |
| #define MT6338_RG_AUDADC3MODE_SHIFT 0 |
| #define MT6338_RG_AUDADC3_VOW_ADDR \ |
| MT6338_AUDENC_PMU_CON15 |
| #define MT6338_RG_AUDADC3_VOW_MASK 0x1 |
| #define MT6338_RG_AUDADC3_VOW_SHIFT 3 |
| #define MT6338_RG_AUDADC4MODE_ADDR \ |
| MT6338_AUDENC_PMU_CON15 |
| #define MT6338_RG_AUDADC4MODE_MASK 0x7 |
| #define MT6338_RG_AUDADC4MODE_SHIFT 4 |
| #define MT6338_RG_AUDADC4_VOW_ADDR \ |
| MT6338_AUDENC_PMU_CON15 |
| #define MT6338_RG_AUDADC4_VOW_MASK 0x1 |
| #define MT6338_RG_AUDADC4_VOW_SHIFT 7 |
| #define MT6338_RG_AUDRULHALFBIAS_ADDR \ |
| MT6338_AUDENC_PMU_CON16 |
| #define MT6338_RG_AUDRULHALFBIAS_MASK 0x1 |
| #define MT6338_RG_AUDRULHALFBIAS_SHIFT 0 |
| #define MT6338_RG_AUDGLBRVOWLPWEN_ADDR \ |
| MT6338_AUDENC_PMU_CON16 |
| #define MT6338_RG_AUDGLBRVOWLPWEN_MASK 0x1 |
| #define MT6338_RG_AUDGLBRVOWLPWEN_SHIFT 1 |
| #define MT6338_RG_AUDRPREAMPLPEN_ADDR \ |
| MT6338_AUDENC_PMU_CON16 |
| #define MT6338_RG_AUDRPREAMPLPEN_MASK 0x1 |
| #define MT6338_RG_AUDRPREAMPLPEN_SHIFT 2 |
| #define MT6338_RG_AUDRADC1STSTAGELPEN_ADDR \ |
| MT6338_AUDENC_PMU_CON16 |
| #define MT6338_RG_AUDRADC1STSTAGELPEN_MASK 0x1 |
| #define MT6338_RG_AUDRADC1STSTAGELPEN_SHIFT 3 |
| #define MT6338_RG_AUDRADC2NDSTAGELPEN_ADDR \ |
| MT6338_AUDENC_PMU_CON16 |
| #define MT6338_RG_AUDRADC2NDSTAGELPEN_MASK 0x1 |
| #define MT6338_RG_AUDRADC2NDSTAGELPEN_SHIFT 4 |
| #define MT6338_RG_AUDRADCFLASHLPEN_ADDR \ |
| MT6338_AUDENC_PMU_CON16 |
| #define MT6338_RG_AUDRADCFLASHLPEN_MASK 0x1 |
| #define MT6338_RG_AUDRADCFLASHLPEN_SHIFT 5 |
| #define MT6338_RG_AUDRPREAMPIDDTEST_ADDR \ |
| MT6338_AUDENC_PMU_CON16 |
| #define MT6338_RG_AUDRPREAMPIDDTEST_MASK 0x3 |
| #define MT6338_RG_AUDRPREAMPIDDTEST_SHIFT 6 |
| #define MT6338_RG_AUDRADC1STSTAGEIDDTEST_ADDR \ |
| MT6338_AUDENC_PMU_CON17 |
| #define MT6338_RG_AUDRADC1STSTAGEIDDTEST_MASK 0x3 |
| #define MT6338_RG_AUDRADC1STSTAGEIDDTEST_SHIFT 0 |
| #define MT6338_RG_AUDRADC2NDSTAGEIDDTEST_ADDR \ |
| MT6338_AUDENC_PMU_CON17 |
| #define MT6338_RG_AUDRADC2NDSTAGEIDDTEST_MASK 0x3 |
| #define MT6338_RG_AUDRADC2NDSTAGEIDDTEST_SHIFT 2 |
| #define MT6338_RG_AUDRADCREFBUFIDDTEST_ADDR \ |
| MT6338_AUDENC_PMU_CON17 |
| #define MT6338_RG_AUDRADCREFBUFIDDTEST_MASK 0x3 |
| #define MT6338_RG_AUDRADCREFBUFIDDTEST_SHIFT 4 |
| #define MT6338_RG_AUDRADCFLASHIDDTEST_ADDR \ |
| MT6338_AUDENC_PMU_CON17 |
| #define MT6338_RG_AUDRADCFLASHIDDTEST_MASK 0x3 |
| #define MT6338_RG_AUDRADCFLASHIDDTEST_SHIFT 6 |
| #define MT6338_RG_AUDADCLCLKRSTB_ADDR \ |
| MT6338_AUDENC_PMU_CON18 |
| #define MT6338_RG_AUDADCLCLKRSTB_MASK 0x1 |
| #define MT6338_RG_AUDADCLCLKRSTB_SHIFT 0 |
| #define MT6338_RG_AUDADCLCLKSEL_ADDR \ |
| MT6338_AUDENC_PMU_CON18 |
| #define MT6338_RG_AUDADCLCLKSEL_MASK 0x3 |
| #define MT6338_RG_AUDADCLCLKSEL_SHIFT 1 |
| #define MT6338_RG_AUDADCLCLKSOURCE_ADDR \ |
| MT6338_AUDENC_PMU_CON18 |
| #define MT6338_RG_AUDADCLCLKSOURCE_MASK 0x3 |
| #define MT6338_RG_AUDADCLCLKSOURCE_SHIFT 3 |
| #define MT6338_RG_AUDADCLCLKGENMODE_ADDR \ |
| MT6338_AUDENC_PMU_CON18 |
| #define MT6338_RG_AUDADCLCLKGENMODE_MASK 0x3 |
| #define MT6338_RG_AUDADCLCLKGENMODE_SHIFT 5 |
| #define MT6338_RG_AUDADCRCLKRSTB_ADDR \ |
| MT6338_AUDENC_PMU_CON19 |
| #define MT6338_RG_AUDADCRCLKRSTB_MASK 0x1 |
| #define MT6338_RG_AUDADCRCLKRSTB_SHIFT 0 |
| #define MT6338_RG_AUDADCRCLKSEL_ADDR \ |
| MT6338_AUDENC_PMU_CON19 |
| #define MT6338_RG_AUDADCRCLKSEL_MASK 0x3 |
| #define MT6338_RG_AUDADCRCLKSEL_SHIFT 1 |
| #define MT6338_RG_AUDADCRCLKSOURCE_ADDR \ |
| MT6338_AUDENC_PMU_CON19 |
| #define MT6338_RG_AUDADCRCLKSOURCE_MASK 0x3 |
| #define MT6338_RG_AUDADCRCLKSOURCE_SHIFT 3 |
| #define MT6338_RG_AUDADCRCLKGENMODE_ADDR \ |
| MT6338_AUDENC_PMU_CON19 |
| #define MT6338_RG_AUDADCRCLKGENMODE_MASK 0x3 |
| #define MT6338_RG_AUDADCRCLKGENMODE_SHIFT 5 |
| #define MT6338_RG_AUDADC3CLKRSTB_ADDR \ |
| MT6338_AUDENC_PMU_CON20 |
| #define MT6338_RG_AUDADC3CLKRSTB_MASK 0x1 |
| #define MT6338_RG_AUDADC3CLKRSTB_SHIFT 0 |
| #define MT6338_RG_AUDADC3CLKSEL_ADDR \ |
| MT6338_AUDENC_PMU_CON20 |
| #define MT6338_RG_AUDADC3CLKSEL_MASK 0x3 |
| #define MT6338_RG_AUDADC3CLKSEL_SHIFT 1 |
| #define MT6338_RG_AUDADC3CLKSOURCE_ADDR \ |
| MT6338_AUDENC_PMU_CON20 |
| #define MT6338_RG_AUDADC3CLKSOURCE_MASK 0x3 |
| #define MT6338_RG_AUDADC3CLKSOURCE_SHIFT 3 |
| #define MT6338_RG_AUDADC3CLKGENMODE_ADDR \ |
| MT6338_AUDENC_PMU_CON20 |
| #define MT6338_RG_AUDADC3CLKGENMODE_MASK 0x3 |
| #define MT6338_RG_AUDADC3CLKGENMODE_SHIFT 5 |
| #define MT6338_RG_AUDADC4CLKRSTB_ADDR \ |
| MT6338_AUDENC_PMU_CON21 |
| #define MT6338_RG_AUDADC4CLKRSTB_MASK 0x1 |
| #define MT6338_RG_AUDADC4CLKRSTB_SHIFT 0 |
| #define MT6338_RG_AUDADC4CLKSEL_ADDR \ |
| MT6338_AUDENC_PMU_CON21 |
| #define MT6338_RG_AUDADC4CLKSEL_MASK 0x3 |
| #define MT6338_RG_AUDADC4CLKSEL_SHIFT 1 |
| #define MT6338_RG_AUDADC4CLKSOURCE_ADDR \ |
| MT6338_AUDENC_PMU_CON21 |
| #define MT6338_RG_AUDADC4CLKSOURCE_MASK 0x3 |
| #define MT6338_RG_AUDADC4CLKSOURCE_SHIFT 3 |
| #define MT6338_RG_AUDADC4CLKGENMODE_ADDR \ |
| MT6338_AUDENC_PMU_CON21 |
| #define MT6338_RG_AUDADC4CLKGENMODE_MASK 0x3 |
| #define MT6338_RG_AUDADC4CLKGENMODE_SHIFT 5 |
| #define MT6338_RG_AUDPREAMPL_ACCFS_ADDR \ |
| MT6338_AUDENC_PMU_CON22 |
| #define MT6338_RG_AUDPREAMPL_ACCFS_MASK 0x1 |
| #define MT6338_RG_AUDPREAMPL_ACCFS_SHIFT 0 |
| #define MT6338_RG_AUDPREAMPR_ACCFS_ADDR \ |
| MT6338_AUDENC_PMU_CON22 |
| #define MT6338_RG_AUDPREAMPR_ACCFS_MASK 0x1 |
| #define MT6338_RG_AUDPREAMPR_ACCFS_SHIFT 1 |
| #define MT6338_RG_AUDPREAMP3_ACCFS_ADDR \ |
| MT6338_AUDENC_PMU_CON22 |
| #define MT6338_RG_AUDPREAMP3_ACCFS_MASK 0x1 |
| #define MT6338_RG_AUDPREAMP3_ACCFS_SHIFT 2 |
| #define MT6338_RG_AUDPREAMP4_ACCFS_ADDR \ |
| MT6338_AUDENC_PMU_CON22 |
| #define MT6338_RG_AUDPREAMP4_ACCFS_MASK 0x1 |
| #define MT6338_RG_AUDPREAMP4_ACCFS_SHIFT 3 |
| #define MT6338_RG_AUDSPAREPGA1_ADDR \ |
| MT6338_AUDENC_PMU_CON22 |
| #define MT6338_RG_AUDSPAREPGA1_MASK 0xF |
| #define MT6338_RG_AUDSPAREPGA1_SHIFT 4 |
| #define MT6338_RG_AUDSPAREPGA2_ADDR \ |
| MT6338_AUDENC_PMU_CON23 |
| #define MT6338_RG_AUDSPAREPGA2_MASK 0xFF |
| #define MT6338_RG_AUDSPAREPGA2_SHIFT 0 |
| #define MT6338_RG_AUDADC1STSTAGESDENB_ADDR \ |
| MT6338_AUDENC_PMU_CON24 |
| #define MT6338_RG_AUDADC1STSTAGESDENB_MASK 0x1 |
| #define MT6338_RG_AUDADC1STSTAGESDENB_SHIFT 0 |
| #define MT6338_RG_AUDADC2NDSTAGERESET_ADDR \ |
| MT6338_AUDENC_PMU_CON24 |
| #define MT6338_RG_AUDADC2NDSTAGERESET_MASK 0x1 |
| #define MT6338_RG_AUDADC2NDSTAGERESET_SHIFT 1 |
| #define MT6338_RG_AUDADC3RDSTAGERESET_ADDR \ |
| MT6338_AUDENC_PMU_CON24 |
| #define MT6338_RG_AUDADC3RDSTAGERESET_MASK 0x1 |
| #define MT6338_RG_AUDADC3RDSTAGERESET_SHIFT 2 |
| #define MT6338_RG_AUDADCFSRESET_ADDR \ |
| MT6338_AUDENC_PMU_CON24 |
| #define MT6338_RG_AUDADCFSRESET_MASK 0x1 |
| #define MT6338_RG_AUDADCFSRESET_SHIFT 3 |
| #define MT6338_RG_AUDADCWIDECM_ADDR \ |
| MT6338_AUDENC_PMU_CON24 |
| #define MT6338_RG_AUDADCWIDECM_MASK 0x1 |
| #define MT6338_RG_AUDADCWIDECM_SHIFT 4 |
| #define MT6338_RG_AUDADCNOPATEST_ADDR \ |
| MT6338_AUDENC_PMU_CON24 |
| #define MT6338_RG_AUDADCNOPATEST_MASK 0x1 |
| #define MT6338_RG_AUDADCNOPATEST_SHIFT 5 |
| #define MT6338_RG_AUDADCBYPASS_ADDR \ |
| MT6338_AUDENC_PMU_CON24 |
| #define MT6338_RG_AUDADCBYPASS_MASK 0x1 |
| #define MT6338_RG_AUDADCBYPASS_SHIFT 6 |
| #define MT6338_RG_AUDADCFFBYPASS_ADDR \ |
| MT6338_AUDENC_PMU_CON24 |
| #define MT6338_RG_AUDADCFFBYPASS_MASK 0x1 |
| #define MT6338_RG_AUDADCFFBYPASS_SHIFT 7 |
| #define MT6338_RG_AUDADCDACFBCURRENT_ADDR \ |
| MT6338_AUDENC_PMU_CON25 |
| #define MT6338_RG_AUDADCDACFBCURRENT_MASK 0x1 |
| #define MT6338_RG_AUDADCDACFBCURRENT_SHIFT 0 |
| #define MT6338_RG_AUDADCDACIDDTEST_ADDR \ |
| MT6338_AUDENC_PMU_CON25 |
| #define MT6338_RG_AUDADCDACIDDTEST_MASK 0x3 |
| #define MT6338_RG_AUDADCDACIDDTEST_SHIFT 1 |
| #define MT6338_RG_AUDADCDACNRZ_ADDR \ |
| MT6338_AUDENC_PMU_CON25 |
| #define MT6338_RG_AUDADCDACNRZ_MASK 0x1 |
| #define MT6338_RG_AUDADCDACNRZ_SHIFT 3 |
| #define MT6338_RG_AUDADCNODEM_ADDR \ |
| MT6338_AUDENC_PMU_CON25 |
| #define MT6338_RG_AUDADCNODEM_MASK 0x1 |
| #define MT6338_RG_AUDADCNODEM_SHIFT 4 |
| #define MT6338_RG_AUDADCDACTEST_ADDR \ |
| MT6338_AUDENC_PMU_CON25 |
| #define MT6338_RG_AUDADCDACTEST_MASK 0x1 |
| #define MT6338_RG_AUDADCDACTEST_SHIFT 5 |
| #define MT6338_RG_AUDADCDAC0P25FS_ADDR \ |
| MT6338_AUDENC_PMU_CON25 |
| #define MT6338_RG_AUDADCDAC0P25FS_MASK 0x1 |
| #define MT6338_RG_AUDADCDAC0P25FS_SHIFT 6 |
| #define MT6338_RG_AUDADCRDAC0P25FS_ADDR \ |
| MT6338_AUDENC_PMU_CON25 |
| #define MT6338_RG_AUDADCRDAC0P25FS_MASK 0x1 |
| #define MT6338_RG_AUDADCRDAC0P25FS_SHIFT 7 |
| #define MT6338_RG_AUDADCTESTDATA1_ADDR \ |
| MT6338_AUDENC_PMU_CON26 |
| #define MT6338_RG_AUDADCTESTDATA1_MASK 0xFF |
| #define MT6338_RG_AUDADCTESTDATA1_SHIFT 0 |
| #define MT6338_RG_AUDADCTESTDATA2_ADDR \ |
| MT6338_AUDENC_PMU_CON27 |
| #define MT6338_RG_AUDADCTESTDATA2_MASK 0xFF |
| #define MT6338_RG_AUDADCTESTDATA2_SHIFT 0 |
| #define MT6338_RG_AUDRCTUNEL_ADDR \ |
| MT6338_AUDENC_PMU_CON28 |
| #define MT6338_RG_AUDRCTUNEL_MASK 0x1F |
| #define MT6338_RG_AUDRCTUNEL_SHIFT 0 |
| #define MT6338_RG_AUDRCTUNELSEL_ADDR \ |
| MT6338_AUDENC_PMU_CON28 |
| #define MT6338_RG_AUDRCTUNELSEL_MASK 0x1 |
| #define MT6338_RG_AUDRCTUNELSEL_SHIFT 5 |
| #define MT6338_RG_AUDRCTUNER_ADDR \ |
| MT6338_AUDENC_PMU_CON29 |
| #define MT6338_RG_AUDRCTUNER_MASK 0x1F |
| #define MT6338_RG_AUDRCTUNER_SHIFT 0 |
| #define MT6338_RG_AUDRCTUNERSEL_ADDR \ |
| MT6338_AUDENC_PMU_CON29 |
| #define MT6338_RG_AUDRCTUNERSEL_MASK 0x1 |
| #define MT6338_RG_AUDRCTUNERSEL_SHIFT 5 |
| #define MT6338_RG_AUDRCTUNE3_ADDR \ |
| MT6338_AUDENC_PMU_CON30 |
| #define MT6338_RG_AUDRCTUNE3_MASK 0x1F |
| #define MT6338_RG_AUDRCTUNE3_SHIFT 0 |
| #define MT6338_RG_AUDRCTUNE3SEL_ADDR \ |
| MT6338_AUDENC_PMU_CON30 |
| #define MT6338_RG_AUDRCTUNE3SEL_MASK 0x1 |
| #define MT6338_RG_AUDRCTUNE3SEL_SHIFT 5 |
| #define MT6338_RG_AUDRCTUNE4_ADDR \ |
| MT6338_AUDENC_PMU_CON31 |
| #define MT6338_RG_AUDRCTUNE4_MASK 0x1F |
| #define MT6338_RG_AUDRCTUNE4_SHIFT 0 |
| #define MT6338_RG_AUDRCTUNE4SEL_ADDR \ |
| MT6338_AUDENC_PMU_CON31 |
| #define MT6338_RG_AUDRCTUNE4SEL_MASK 0x1 |
| #define MT6338_RG_AUDRCTUNE4SEL_SHIFT 5 |
| #define MT6338_RGS_AUDRCTUNELREAD_ADDR \ |
| MT6338_AUDENC_PMU_CON32 |
| #define MT6338_RGS_AUDRCTUNELREAD_MASK 0x1F |
| #define MT6338_RGS_AUDRCTUNELREAD_SHIFT 0 |
| #define MT6338_RGS_AUDRCTUNERREAD_ADDR \ |
| MT6338_AUDENC_PMU_CON33 |
| #define MT6338_RGS_AUDRCTUNERREAD_MASK 0x1F |
| #define MT6338_RGS_AUDRCTUNERREAD_SHIFT 0 |
| #define MT6338_RGS_AUDRCTUNE3READ_ADDR \ |
| MT6338_AUDENC_PMU_CON34 |
| #define MT6338_RGS_AUDRCTUNE3READ_MASK 0x1F |
| #define MT6338_RGS_AUDRCTUNE3READ_SHIFT 0 |
| #define MT6338_RGS_AUDRCTUNE4READ_ADDR \ |
| MT6338_AUDENC_PMU_CON35 |
| #define MT6338_RGS_AUDRCTUNE4READ_MASK 0x1F |
| #define MT6338_RGS_AUDRCTUNE4READ_SHIFT 0 |
| #define MT6338_RG_AUDPGA_DECAP_ADDR \ |
| MT6338_AUDENC_PMU_CON36 |
| #define MT6338_RG_AUDPGA_DECAP_MASK 0x1 |
| #define MT6338_RG_AUDPGA_DECAP_SHIFT 0 |
| #define MT6338_RG_AUDPGA_CAPRA_ADDR \ |
| MT6338_AUDENC_PMU_CON36 |
| #define MT6338_RG_AUDPGA_CAPRA_MASK 0x1 |
| #define MT6338_RG_AUDPGA_CAPRA_SHIFT 1 |
| #define MT6338_RG_AUDPGA_ACCCMP_ADDR \ |
| MT6338_AUDENC_PMU_CON36 |
| #define MT6338_RG_AUDPGA_ACCCMP_MASK 0x1 |
| #define MT6338_RG_AUDPGA_ACCCMP_SHIFT 2 |
| #define MT6338_RG_AUDENC_SPARE2_ADDR \ |
| MT6338_AUDENC_PMU_CON36 |
| #define MT6338_RG_AUDENC_SPARE2_MASK 0x1F |
| #define MT6338_RG_AUDENC_SPARE2_SHIFT 3 |
| #define MT6338_RG_AUDENC_SPARE3_ADDR \ |
| MT6338_AUDENC_PMU_CON37 |
| #define MT6338_RG_AUDENC_SPARE3_MASK 0xFF |
| #define MT6338_RG_AUDENC_SPARE3_SHIFT 0 |
| #define MT6338_RG_AUDPREAMPLACCGAIN_ADDR \ |
| MT6338_AUDENC_PMU_CON38 |
| #define MT6338_RG_AUDPREAMPLACCGAIN_MASK 0x7 |
| #define MT6338_RG_AUDPREAMPLACCGAIN_SHIFT 0 |
| #define MT6338_RG_AUDPREAMPRACCGAIN_ADDR \ |
| MT6338_AUDENC_PMU_CON38 |
| #define MT6338_RG_AUDPREAMPRACCGAIN_MASK 0x7 |
| #define MT6338_RG_AUDPREAMPRACCGAIN_SHIFT 4 |
| #define MT6338_RG_AUDPREAMP3ACCGAIN_ADDR \ |
| MT6338_AUDENC_PMU_CON39 |
| #define MT6338_RG_AUDPREAMP3ACCGAIN_MASK 0x7 |
| #define MT6338_RG_AUDPREAMP3ACCGAIN_SHIFT 0 |
| #define MT6338_RG_AUDPREAMP4ACCGAIN_ADDR \ |
| MT6338_AUDENC_PMU_CON39 |
| #define MT6338_RG_AUDPREAMP4ACCGAIN_MASK 0x7 |
| #define MT6338_RG_AUDPREAMP4ACCGAIN_SHIFT 4 |
| #define MT6338_RG_AUDLADC1STSTAGEVOW_ADDR \ |
| MT6338_AUDENC_PMU_CON40 |
| #define MT6338_RG_AUDLADC1STSTAGEVOW_MASK 0x1 |
| #define MT6338_RG_AUDLADC1STSTAGEVOW_SHIFT 0 |
| #define MT6338_RG_AUDRADC1STSTAGEVOW_ADDR \ |
| MT6338_AUDENC_PMU_CON40 |
| #define MT6338_RG_AUDRADC1STSTAGEVOW_MASK 0x1 |
| #define MT6338_RG_AUDRADC1STSTAGEVOW_SHIFT 1 |
| #define MT6338_RG_AUD3ADC1STSTAGEVOW_ADDR \ |
| MT6338_AUDENC_PMU_CON40 |
| #define MT6338_RG_AUD3ADC1STSTAGEVOW_MASK 0x1 |
| #define MT6338_RG_AUD3ADC1STSTAGEVOW_SHIFT 2 |
| #define MT6338_RG_AUD4ADC1STSTAGEVOW_ADDR \ |
| MT6338_AUDENC_PMU_CON40 |
| #define MT6338_RG_AUD4ADC1STSTAGEVOW_MASK 0x1 |
| #define MT6338_RG_AUD4ADC1STSTAGEVOW_SHIFT 3 |
| #define MT6338_RG_AUDRADC1STSTAGELPEN_0_ADDR \ |
| MT6338_AUDENC_PMU_CON40 |
| #define MT6338_RG_AUDRADC1STSTAGELPEN_0_MASK 0x1 |
| #define MT6338_RG_AUDRADC1STSTAGELPEN_0_SHIFT 4 |
| #define MT6338_RG_AUD3ADC1STSTAGELPEN_ADDR \ |
| MT6338_AUDENC_PMU_CON40 |
| #define MT6338_RG_AUD3ADC1STSTAGELPEN_MASK 0x3 |
| #define MT6338_RG_AUD3ADC1STSTAGELPEN_SHIFT 5 |
| #define MT6338_RG_AUD3ADC2NDSTAGELPEN_ADDR \ |
| MT6338_AUDENC_PMU_CON40 |
| #define MT6338_RG_AUD3ADC2NDSTAGELPEN_MASK 0x1 |
| #define MT6338_RG_AUD3ADC2NDSTAGELPEN_SHIFT 7 |
| #define MT6338_RG_AUD4ADC1STSTAGELPEN_ADDR \ |
| MT6338_AUDENC_PMU_CON41 |
| #define MT6338_RG_AUD4ADC1STSTAGELPEN_MASK 0x3 |
| #define MT6338_RG_AUD4ADC1STSTAGELPEN_SHIFT 0 |
| #define MT6338_RG_AUD4ADC2NDSTAGELPEN_ADDR \ |
| MT6338_AUDENC_PMU_CON41 |
| #define MT6338_RG_AUD4ADC2NDSTAGELPEN_MASK 0x1 |
| #define MT6338_RG_AUD4ADC2NDSTAGELPEN_SHIFT 2 |
| #define MT6338_RG_AUDADCRWIDECM_ADDR \ |
| MT6338_AUDENC_PMU_CON41 |
| #define MT6338_RG_AUDADCRWIDECM_MASK 0x1 |
| #define MT6338_RG_AUDADCRWIDECM_SHIFT 3 |
| #define MT6338_RG_AUDADC3WIDECM_ADDR \ |
| MT6338_AUDENC_PMU_CON41 |
| #define MT6338_RG_AUDADC3WIDECM_MASK 0x1 |
| #define MT6338_RG_AUDADC3WIDECM_SHIFT 4 |
| #define MT6338_RG_AUDADC4WIDECM_ADDR \ |
| MT6338_AUDENC_PMU_CON41 |
| #define MT6338_RG_AUDADC4WIDECM_MASK 0x1 |
| #define MT6338_RG_AUDADC4WIDECM_SHIFT 5 |
| #define MT6338_RG_AUDRADCDACIDDTEST_ADDR \ |
| MT6338_AUDENC_PMU_CON41 |
| #define MT6338_RG_AUDRADCDACIDDTEST_MASK 0x3 |
| #define MT6338_RG_AUDRADCDACIDDTEST_SHIFT 6 |
| #define MT6338_RG_AUD3ADC1STSTAGEIDDTEST_ADDR \ |
| MT6338_AUDENC_PMU_CON42 |
| #define MT6338_RG_AUD3ADC1STSTAGEIDDTEST_MASK 0x3 |
| #define MT6338_RG_AUD3ADC1STSTAGEIDDTEST_SHIFT 0 |
| #define MT6338_RG_AUD3ADC2NDSTAGEIDDTEST_ADDR \ |
| MT6338_AUDENC_PMU_CON42 |
| #define MT6338_RG_AUD3ADC2NDSTAGEIDDTEST_MASK 0x3 |
| #define MT6338_RG_AUD3ADC2NDSTAGEIDDTEST_SHIFT 2 |
| #define MT6338_RG_AUD3ADCDACIDDTEST_ADDR \ |
| MT6338_AUDENC_PMU_CON42 |
| #define MT6338_RG_AUD3ADCDACIDDTEST_MASK 0x3 |
| #define MT6338_RG_AUD3ADCDACIDDTEST_SHIFT 4 |
| #define MT6338_RG_AUD3ADCREFBUFIDDTEST_ADDR \ |
| MT6338_AUDENC_PMU_CON42 |
| #define MT6338_RG_AUD3ADCREFBUFIDDTEST_MASK 0x3 |
| #define MT6338_RG_AUD3ADCREFBUFIDDTEST_SHIFT 6 |
| #define MT6338_RG_AUD4ADC1STSTAGEIDDTEST_ADDR \ |
| MT6338_AUDENC_PMU_CON43 |
| #define MT6338_RG_AUD4ADC1STSTAGEIDDTEST_MASK 0x3 |
| #define MT6338_RG_AUD4ADC1STSTAGEIDDTEST_SHIFT 0 |
| #define MT6338_RG_AUD4ADC2NDSTAGEIDDTEST_ADDR \ |
| MT6338_AUDENC_PMU_CON43 |
| #define MT6338_RG_AUD4ADC2NDSTAGEIDDTEST_MASK 0x3 |
| #define MT6338_RG_AUD4ADC2NDSTAGEIDDTEST_SHIFT 2 |
| #define MT6338_RG_AUD4ADCDACIDDTEST_ADDR \ |
| MT6338_AUDENC_PMU_CON43 |
| #define MT6338_RG_AUD4ADCDACIDDTEST_MASK 0x3 |
| #define MT6338_RG_AUD4ADCDACIDDTEST_SHIFT 4 |
| #define MT6338_RG_AUD4ADCREFBUFIDDTEST_ADDR \ |
| MT6338_AUDENC_PMU_CON43 |
| #define MT6338_RG_AUD4ADCREFBUFIDDTEST_MASK 0x3 |
| #define MT6338_RG_AUD4ADCREFBUFIDDTEST_SHIFT 6 |
| #define MT6338_RG_AUD3ULHALFBIAS_ADDR \ |
| MT6338_AUDENC_PMU_CON44 |
| #define MT6338_RG_AUD3ULHALFBIAS_MASK 0x1 |
| #define MT6338_RG_AUD3ULHALFBIAS_SHIFT 0 |
| #define MT6338_RG_AUD4ULHALFBIAS_ADDR \ |
| MT6338_AUDENC_PMU_CON44 |
| #define MT6338_RG_AUD4ULHALFBIAS_MASK 0x1 |
| #define MT6338_RG_AUD4ULHALFBIAS_SHIFT 1 |
| #define MT6338_RG_AUDLADCHALFCLK_ADDR \ |
| MT6338_AUDENC_PMU_CON44 |
| #define MT6338_RG_AUDLADCHALFCLK_MASK 0x1 |
| #define MT6338_RG_AUDLADCHALFCLK_SHIFT 2 |
| #define MT6338_RG_AUDRADCHALFCLK_ADDR \ |
| MT6338_AUDENC_PMU_CON44 |
| #define MT6338_RG_AUDRADCHALFCLK_MASK 0x1 |
| #define MT6338_RG_AUDRADCHALFCLK_SHIFT 3 |
| #define MT6338_RG_AUD3ADCHALFCLK_ADDR \ |
| MT6338_AUDENC_PMU_CON44 |
| #define MT6338_RG_AUD3ADCHALFCLK_MASK 0x1 |
| #define MT6338_RG_AUD3ADCHALFCLK_SHIFT 4 |
| #define MT6338_RG_AUD4ADCHALFCLK_ADDR \ |
| MT6338_AUDENC_PMU_CON44 |
| #define MT6338_RG_AUD4ADCHALFCLK_MASK 0x1 |
| #define MT6338_RG_AUD4ADCHALFCLK_SHIFT 5 |
| #define MT6338_RG_AUDLADCDACMODE_SEL_ADDR \ |
| MT6338_AUDENC_PMU_CON44 |
| #define MT6338_RG_AUDLADCDACMODE_SEL_MASK 0x1 |
| #define MT6338_RG_AUDLADCDACMODE_SEL_SHIFT 6 |
| #define MT6338_RG_AUDRADCDACMODE_SEL_ADDR \ |
| MT6338_AUDENC_PMU_CON44 |
| #define MT6338_RG_AUDRADCDACMODE_SEL_MASK 0x1 |
| #define MT6338_RG_AUDRADCDACMODE_SEL_SHIFT 7 |
| #define MT6338_RG_AUD3ADCDACMODE_SEL_ADDR \ |
| MT6338_AUDENC_PMU_CON45 |
| #define MT6338_RG_AUD3ADCDACMODE_SEL_MASK 0x1 |
| #define MT6338_RG_AUD3ADCDACMODE_SEL_SHIFT 0 |
| #define MT6338_RG_AUD4ADCDACMODE_SEL_ADDR \ |
| MT6338_AUDENC_PMU_CON45 |
| #define MT6338_RG_AUD4ADCDACMODE_SEL_MASK 0x1 |
| #define MT6338_RG_AUD4ADCDACMODE_SEL_SHIFT 1 |
| #define MT6338_RG_AUDADCRESET_SEL_ADDR \ |
| MT6338_AUDENC_PMU_CON45 |
| #define MT6338_RG_AUDADCRESET_SEL_MASK 0x1 |
| #define MT6338_RG_AUDADCRESET_SEL_SHIFT 2 |
| #define MT6338_RG_AUDADCLRINOHM_ADDR \ |
| MT6338_AUDENC_PMU_CON45 |
| #define MT6338_RG_AUDADCLRINOHM_MASK 0x1F |
| #define MT6338_RG_AUDADCLRINOHM_SHIFT 3 |
| #define MT6338_RG_AUDADCRRINOHM_ADDR \ |
| MT6338_AUDENC_PMU_CON46 |
| #define MT6338_RG_AUDADCRRINOHM_MASK 0x1F |
| #define MT6338_RG_AUDADCRRINOHM_SHIFT 0 |
| #define MT6338_RG_AUDADC3RINOHM_ADDR \ |
| MT6338_AUDENC_PMU_CON47 |
| #define MT6338_RG_AUDADC3RINOHM_MASK 0x1F |
| #define MT6338_RG_AUDADC3RINOHM_SHIFT 0 |
| #define MT6338_RG_AUDADC4RINOHM_ADDR \ |
| MT6338_AUDENC_PMU_CON48 |
| #define MT6338_RG_AUDADC4RINOHM_MASK 0x1F |
| #define MT6338_RG_AUDADC4RINOHM_SHIFT 0 |
| #define MT6338_RG_AUDADCHIGHDR_EN_ADDR \ |
| MT6338_AUDENC_PMU_CON49 |
| #define MT6338_RG_AUDADCHIGHDR_EN_MASK 0x1 |
| #define MT6338_RG_AUDADCHIGHDR_EN_SHIFT 0 |
| #define MT6338_RG_AUDADCHIGHDRSW_SEL_ADDR \ |
| MT6338_AUDENC_PMU_CON49 |
| #define MT6338_RG_AUDADCHIGHDRSW_SEL_MASK 0x1 |
| #define MT6338_RG_AUDADCHIGHDRSW_SEL_SHIFT 1 |
| #define MT6338_RG_AUDADCHIGHDRSW_EN_ADDR \ |
| MT6338_AUDENC_PMU_CON49 |
| #define MT6338_RG_AUDADCHIGHDRSW_EN_MASK 0x1 |
| #define MT6338_RG_AUDADCHIGHDRSW_EN_SHIFT 2 |
| #define MT6338_RG_ADCHIGHDR_DEBNCSEL_ADDR \ |
| MT6338_AUDENC_PMU_CON49 |
| #define MT6338_RG_ADCHIGHDR_DEBNCSEL_MASK 0x3 |
| #define MT6338_RG_ADCHIGHDR_DEBNCSEL_SHIFT 3 |
| #define MT6338_RG_AUDADCETMON_SEL_ADDR \ |
| MT6338_AUDENC_PMU_CON49 |
| #define MT6338_RG_AUDADCETMON_SEL_MASK 0x1 |
| #define MT6338_RG_AUDADCETMON_SEL_SHIFT 5 |
| #define MT6338_RG_AUDRCTUNEBYP_ADDR \ |
| MT6338_AUDENC_PMU_CON49 |
| #define MT6338_RG_AUDRCTUNEBYP_MASK 0x1 |
| #define MT6338_RG_AUDRCTUNEBYP_SHIFT 6 |
| #define MT6338_RG_AUDADCLFLASHVREFRES_LPM_ADDR \ |
| MT6338_AUDENC_PMU_CON50 |
| #define MT6338_RG_AUDADCLFLASHVREFRES_LPM_MASK 0x1 |
| #define MT6338_RG_AUDADCLFLASHVREFRES_LPM_SHIFT 0 |
| #define MT6338_RG_AUDADCLFLASHVREFRES_LPM2_ADDR \ |
| MT6338_AUDENC_PMU_CON50 |
| #define MT6338_RG_AUDADCLFLASHVREFRES_LPM2_MASK 0x1 |
| #define MT6338_RG_AUDADCLFLASHVREFRES_LPM2_SHIFT 1 |
| #define MT6338_RG_AUDADCRFLASHVREFRES_LPM_ADDR \ |
| MT6338_AUDENC_PMU_CON50 |
| #define MT6338_RG_AUDADCRFLASHVREFRES_LPM_MASK 0x1 |
| #define MT6338_RG_AUDADCRFLASHVREFRES_LPM_SHIFT 2 |
| #define MT6338_RG_AUDADCRFLASHVREFRES_LPM2_ADDR \ |
| MT6338_AUDENC_PMU_CON50 |
| #define MT6338_RG_AUDADCRFLASHVREFRES_LPM2_MASK 0x1 |
| #define MT6338_RG_AUDADCRFLASHVREFRES_LPM2_SHIFT 3 |
| #define MT6338_RG_AUDADC3FLASHVREFRES_LPM_ADDR \ |
| MT6338_AUDENC_PMU_CON50 |
| #define MT6338_RG_AUDADC3FLASHVREFRES_LPM_MASK 0x1 |
| #define MT6338_RG_AUDADC3FLASHVREFRES_LPM_SHIFT 4 |
| #define MT6338_RG_AUDADC3FLASHVREFRES_LPM2_ADDR \ |
| MT6338_AUDENC_PMU_CON50 |
| #define MT6338_RG_AUDADC3FLASHVREFRES_LPM2_MASK 0x1 |
| #define MT6338_RG_AUDADC3FLASHVREFRES_LPM2_SHIFT 5 |
| #define MT6338_RG_AUDADC4FLASHVREFRES_LPM_ADDR \ |
| MT6338_AUDENC_PMU_CON50 |
| #define MT6338_RG_AUDADC4FLASHVREFRES_LPM_MASK 0x1 |
| #define MT6338_RG_AUDADC4FLASHVREFRES_LPM_SHIFT 6 |
| #define MT6338_RG_AUDADC4FLASHVREFRES_LPM2_ADDR \ |
| MT6338_AUDENC_PMU_CON50 |
| #define MT6338_RG_AUDADC4FLASHVREFRES_LPM2_MASK 0x1 |
| #define MT6338_RG_AUDADC4FLASHVREFRES_LPM2_SHIFT 7 |
| #define MT6338_RG_AUDADCLIVGEN_SDHALF_ADDR \ |
| MT6338_AUDENC_PMU_CON51 |
| #define MT6338_RG_AUDADCLIVGEN_SDHALF_MASK 0x1 |
| #define MT6338_RG_AUDADCLIVGEN_SDHALF_SHIFT 0 |
| #define MT6338_RG_AUDADCRIVGEN_SDHALF_ADDR \ |
| MT6338_AUDENC_PMU_CON51 |
| #define MT6338_RG_AUDADCRIVGEN_SDHALF_MASK 0x1 |
| #define MT6338_RG_AUDADCRIVGEN_SDHALF_SHIFT 1 |
| #define MT6338_RG_AUDADC3IVGEN_SDHALF_ADDR \ |
| MT6338_AUDENC_PMU_CON51 |
| #define MT6338_RG_AUDADC3IVGEN_SDHALF_MASK 0x1 |
| #define MT6338_RG_AUDADC3IVGEN_SDHALF_SHIFT 2 |
| #define MT6338_RG_AUDADC4IVGEN_SDHALF_ADDR \ |
| MT6338_AUDENC_PMU_CON51 |
| #define MT6338_RG_AUDADC4IVGEN_SDHALF_MASK 0x1 |
| #define MT6338_RG_AUDADC4IVGEN_SDHALF_SHIFT 3 |
| #define MT6338_RG_AUDADCLINTEG2XCURRENT_ADDR \ |
| MT6338_AUDENC_PMU_CON51 |
| #define MT6338_RG_AUDADCLINTEG2XCURRENT_MASK 0x1 |
| #define MT6338_RG_AUDADCLINTEG2XCURRENT_SHIFT 4 |
| #define MT6338_RG_AUDADCRINTEG2XCURRENT_ADDR \ |
| MT6338_AUDENC_PMU_CON51 |
| #define MT6338_RG_AUDADCRINTEG2XCURRENT_MASK 0x1 |
| #define MT6338_RG_AUDADCRINTEG2XCURRENT_SHIFT 5 |
| #define MT6338_RG_AUDADC3INTEG2XCURRENT_ADDR \ |
| MT6338_AUDENC_PMU_CON51 |
| #define MT6338_RG_AUDADC3INTEG2XCURRENT_MASK 0x1 |
| #define MT6338_RG_AUDADC3INTEG2XCURRENT_SHIFT 6 |
| #define MT6338_RG_AUDADC4INTEG2XCURRENT_ADDR \ |
| MT6338_AUDENC_PMU_CON51 |
| #define MT6338_RG_AUDADC4INTEG2XCURRENT_MASK 0x1 |
| #define MT6338_RG_AUDADC4INTEG2XCURRENT_SHIFT 7 |
| #define MT6338_RG_AUDLADC1STSTAGELPEN_0_ADDR \ |
| MT6338_AUDENC_PMU_CON52 |
| #define MT6338_RG_AUDLADC1STSTAGELPEN_0_MASK 0x1 |
| #define MT6338_RG_AUDLADC1STSTAGELPEN_0_SHIFT 0 |
| #define MT6338_RG_AUD3PREAMPIDDTEST_ADDR \ |
| MT6338_AUDENC_PMU_CON52 |
| #define MT6338_RG_AUD3PREAMPIDDTEST_MASK 0x3 |
| #define MT6338_RG_AUD3PREAMPIDDTEST_SHIFT 1 |
| #define MT6338_RG_AUD4PREAMPIDDTEST_ADDR \ |
| MT6338_AUDENC_PMU_CON52 |
| #define MT6338_RG_AUD4PREAMPIDDTEST_MASK 0x3 |
| #define MT6338_RG_AUD4PREAMPIDDTEST_SHIFT 3 |
| #define MT6338_RG_AUDPGAR_CAPRA_ADDR \ |
| MT6338_AUDENC_PMU_CON52 |
| #define MT6338_RG_AUDPGAR_CAPRA_MASK 0x1 |
| #define MT6338_RG_AUDPGAR_CAPRA_SHIFT 5 |
| #define MT6338_RG_AUDPGA3_CAPRA_ADDR \ |
| MT6338_AUDENC_PMU_CON52 |
| #define MT6338_RG_AUDPGA3_CAPRA_MASK 0x1 |
| #define MT6338_RG_AUDPGA3_CAPRA_SHIFT 6 |
| #define MT6338_RG_AUDPGA4_CAPRA_ADDR \ |
| MT6338_AUDENC_PMU_CON52 |
| #define MT6338_RG_AUDPGA4_CAPRA_MASK 0x1 |
| #define MT6338_RG_AUDPGA4_CAPRA_SHIFT 7 |
| #define MT6338_RG_AUDSPAREVA30_ADDR \ |
| MT6338_AUDENC_PMU_CON53 |
| #define MT6338_RG_AUDSPAREVA30_MASK 0xFF |
| #define MT6338_RG_AUDSPAREVA30_SHIFT 0 |
| #define MT6338_RG_AUDSPAREVA18_ADDR \ |
| MT6338_AUDENC_PMU_CON54 |
| #define MT6338_RG_AUDSPAREVA18_MASK 0xFF |
| #define MT6338_RG_AUDSPAREVA18_SHIFT 0 |
| #define MT6338_RG_AUDDIGMICEN_ADDR \ |
| MT6338_AUDENC_PMU_CON55 |
| #define MT6338_RG_AUDDIGMICEN_MASK 0x1 |
| #define MT6338_RG_AUDDIGMICEN_SHIFT 0 |
| #define MT6338_RG_AUDDIGMICBIAS_ADDR \ |
| MT6338_AUDENC_PMU_CON55 |
| #define MT6338_RG_AUDDIGMICBIAS_MASK 0x3 |
| #define MT6338_RG_AUDDIGMICBIAS_SHIFT 1 |
| #define MT6338_RG_DMICHPCLKEN_ADDR \ |
| MT6338_AUDENC_PMU_CON55 |
| #define MT6338_RG_DMICHPCLKEN_MASK 0x1 |
| #define MT6338_RG_DMICHPCLKEN_SHIFT 3 |
| #define MT6338_RG_AUDDIGMIC_PREDRVN_ENHB_ADDR \ |
| MT6338_AUDENC_PMU_CON55 |
| #define MT6338_RG_AUDDIGMIC_PREDRVN_ENHB_MASK 0x1 |
| #define MT6338_RG_AUDDIGMIC_PREDRVN_ENHB_SHIFT 4 |
| #define MT6338_RG_AUDDIGMIC_PREDRVP_ENHB_ADDR \ |
| MT6338_AUDENC_PMU_CON55 |
| #define MT6338_RG_AUDDIGMIC_PREDRVP_ENHB_MASK 0x1 |
| #define MT6338_RG_AUDDIGMIC_PREDRVP_ENHB_SHIFT 5 |
| #define MT6338_RG_AUDDIGMIC_DRVA_EN_ADDR \ |
| MT6338_AUDENC_PMU_CON55 |
| #define MT6338_RG_AUDDIGMIC_DRVA_EN_MASK 0x1 |
| #define MT6338_RG_AUDDIGMIC_DRVA_EN_SHIFT 6 |
| #define MT6338_RG_AUDDIGMIC_DRVB_EN_ADDR \ |
| MT6338_AUDENC_PMU_CON55 |
| #define MT6338_RG_AUDDIGMIC_DRVB_EN_MASK 0x1 |
| #define MT6338_RG_AUDDIGMIC_DRVB_EN_SHIFT 7 |
| #define MT6338_RG_DMICMONEN_ADDR \ |
| MT6338_AUDENC_PMU_CON56 |
| #define MT6338_RG_DMICMONEN_MASK 0x1 |
| #define MT6338_RG_DMICMONEN_SHIFT 0 |
| #define MT6338_RG_DMICMONSEL_ADDR \ |
| MT6338_AUDENC_PMU_CON56 |
| #define MT6338_RG_DMICMONSEL_MASK 0x7 |
| #define MT6338_RG_DMICMONSEL_SHIFT 1 |
| #define MT6338_RG_AUDSPAREVMIC_ADDR \ |
| MT6338_AUDENC_PMU_CON56 |
| #define MT6338_RG_AUDSPAREVMIC_MASK 0xF |
| #define MT6338_RG_AUDSPAREVMIC_SHIFT 4 |
| #define MT6338_RG_AUDDIGMIC1EN_ADDR \ |
| MT6338_AUDENC_PMU_CON57 |
| #define MT6338_RG_AUDDIGMIC1EN_MASK 0x1 |
| #define MT6338_RG_AUDDIGMIC1EN_SHIFT 0 |
| #define MT6338_RG_AUDDIGMICBIAS1_ADDR \ |
| MT6338_AUDENC_PMU_CON57 |
| #define MT6338_RG_AUDDIGMICBIAS1_MASK 0x3 |
| #define MT6338_RG_AUDDIGMICBIAS1_SHIFT 1 |
| #define MT6338_RG_DMIC1HPCLKEN_ADDR \ |
| MT6338_AUDENC_PMU_CON57 |
| #define MT6338_RG_DMIC1HPCLKEN_MASK 0x1 |
| #define MT6338_RG_DMIC1HPCLKEN_SHIFT 3 |
| #define MT6338_RG_AUDDIGMIC1_PREDRVN_ENHB_ADDR \ |
| MT6338_AUDENC_PMU_CON57 |
| #define MT6338_RG_AUDDIGMIC1_PREDRVN_ENHB_MASK 0x1 |
| #define MT6338_RG_AUDDIGMIC1_PREDRVN_ENHB_SHIFT 4 |
| #define MT6338_RG_AUDDIGMIC1_PREDRVP_ENHB_ADDR \ |
| MT6338_AUDENC_PMU_CON57 |
| #define MT6338_RG_AUDDIGMIC1_PREDRVP_ENHB_MASK 0x1 |
| #define MT6338_RG_AUDDIGMIC1_PREDRVP_ENHB_SHIFT 5 |
| #define MT6338_RG_AUDDIGMIC1_DRVA_EN_ADDR \ |
| MT6338_AUDENC_PMU_CON57 |
| #define MT6338_RG_AUDDIGMIC1_DRVA_EN_MASK 0x1 |
| #define MT6338_RG_AUDDIGMIC1_DRVA_EN_SHIFT 6 |
| #define MT6338_RG_AUDDIGMIC1_DRVB_EN_ADDR \ |
| MT6338_AUDENC_PMU_CON57 |
| #define MT6338_RG_AUDDIGMIC1_DRVB_EN_MASK 0x1 |
| #define MT6338_RG_AUDDIGMIC1_DRVB_EN_SHIFT 7 |
| #define MT6338_RG_DMIC1MONEN_ADDR \ |
| MT6338_AUDENC_PMU_CON58 |
| #define MT6338_RG_DMIC1MONEN_MASK 0x1 |
| #define MT6338_RG_DMIC1MONEN_SHIFT 0 |
| #define MT6338_RG_DMIC1MONSEL_ADDR \ |
| MT6338_AUDENC_PMU_CON58 |
| #define MT6338_RG_DMIC1MONSEL_MASK 0x7 |
| #define MT6338_RG_DMIC1MONSEL_SHIFT 1 |
| #define MT6338_RG_AUDSPAREVMIC1_ADDR \ |
| MT6338_AUDENC_PMU_CON58 |
| #define MT6338_RG_AUDSPAREVMIC1_MASK 0xF |
| #define MT6338_RG_AUDSPAREVMIC1_SHIFT 4 |
| #define MT6338_RG_AUDPWDBMICBIAS0_ADDR \ |
| MT6338_AUDENC_PMU_CON59 |
| #define MT6338_RG_AUDPWDBMICBIAS0_MASK 0x1 |
| #define MT6338_RG_AUDPWDBMICBIAS0_SHIFT 0 |
| #define MT6338_RG_AUDMICBIAS0BYPASSEN_ADDR \ |
| MT6338_AUDENC_PMU_CON59 |
| #define MT6338_RG_AUDMICBIAS0BYPASSEN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS0BYPASSEN_SHIFT 1 |
| #define MT6338_RG_AUDMICBIAS0LOWPEN_ADDR \ |
| MT6338_AUDENC_PMU_CON59 |
| #define MT6338_RG_AUDMICBIAS0LOWPEN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS0LOWPEN_SHIFT 2 |
| #define MT6338_RG_AUDMICBIAS0ULTRALOWPEN_ADDR \ |
| MT6338_AUDENC_PMU_CON59 |
| #define MT6338_RG_AUDMICBIAS0ULTRALOWPEN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS0ULTRALOWPEN_SHIFT 3 |
| #define MT6338_RG_AUDMICBIAS0VREF_ADDR \ |
| MT6338_AUDENC_PMU_CON59 |
| #define MT6338_RG_AUDMICBIAS0VREF_MASK 0x7 |
| #define MT6338_RG_AUDMICBIAS0VREF_SHIFT 4 |
| #define MT6338_RG_AUDMICBIAS0DCSW0P1EN_ADDR \ |
| MT6338_AUDENC_PMU_CON60 |
| #define MT6338_RG_AUDMICBIAS0DCSW0P1EN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS0DCSW0P1EN_SHIFT 0 |
| #define MT6338_RG_AUDMICBIAS0DCSW0P2EN_ADDR \ |
| MT6338_AUDENC_PMU_CON60 |
| #define MT6338_RG_AUDMICBIAS0DCSW0P2EN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS0DCSW0P2EN_SHIFT 1 |
| #define MT6338_RG_AUDMICBIAS0DCSW0NEN_ADDR \ |
| MT6338_AUDENC_PMU_CON60 |
| #define MT6338_RG_AUDMICBIAS0DCSW0NEN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS0DCSW0NEN_SHIFT 2 |
| #define MT6338_RG_AUDMICBIAS0DCSW2P1EN_ADDR \ |
| MT6338_AUDENC_PMU_CON60 |
| #define MT6338_RG_AUDMICBIAS0DCSW2P1EN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS0DCSW2P1EN_SHIFT 4 |
| #define MT6338_RG_AUDMICBIAS0DCSW2P2EN_ADDR \ |
| MT6338_AUDENC_PMU_CON60 |
| #define MT6338_RG_AUDMICBIAS0DCSW2P2EN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS0DCSW2P2EN_SHIFT 5 |
| #define MT6338_RG_AUDMICBIAS0DCSW2NEN_ADDR \ |
| MT6338_AUDENC_PMU_CON60 |
| #define MT6338_RG_AUDMICBIAS0DCSW2NEN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS0DCSW2NEN_SHIFT 6 |
| #define MT6338_RG_AUDPWDBMICBIAS1_ADDR \ |
| MT6338_AUDENC_PMU_CON61 |
| #define MT6338_RG_AUDPWDBMICBIAS1_MASK 0x1 |
| #define MT6338_RG_AUDPWDBMICBIAS1_SHIFT 0 |
| #define MT6338_RG_AUDMICBIAS1BYPASSEN_ADDR \ |
| MT6338_AUDENC_PMU_CON61 |
| #define MT6338_RG_AUDMICBIAS1BYPASSEN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS1BYPASSEN_SHIFT 1 |
| #define MT6338_RG_AUDMICBIAS1LOWPEN_ADDR \ |
| MT6338_AUDENC_PMU_CON61 |
| #define MT6338_RG_AUDMICBIAS1LOWPEN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS1LOWPEN_SHIFT 2 |
| #define MT6338_RG_AUDMICBIAS1ULTRALOWPEN_ADDR \ |
| MT6338_AUDENC_PMU_CON61 |
| #define MT6338_RG_AUDMICBIAS1ULTRALOWPEN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS1ULTRALOWPEN_SHIFT 3 |
| #define MT6338_RG_AUDMICBIAS1VREF_ADDR \ |
| MT6338_AUDENC_PMU_CON61 |
| #define MT6338_RG_AUDMICBIAS1VREF_MASK 0x7 |
| #define MT6338_RG_AUDMICBIAS1VREF_SHIFT 4 |
| #define MT6338_RG_AUDMICBIAS1DCSW1PEN_ADDR \ |
| MT6338_AUDENC_PMU_CON62 |
| #define MT6338_RG_AUDMICBIAS1DCSW1PEN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS1DCSW1PEN_SHIFT 0 |
| #define MT6338_RG_AUDMICBIAS1DCSW1NEN_ADDR \ |
| MT6338_AUDENC_PMU_CON62 |
| #define MT6338_RG_AUDMICBIAS1DCSW1NEN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS1DCSW1NEN_SHIFT 1 |
| #define MT6338_RG_BANDGAPGEN_ADDR \ |
| MT6338_AUDENC_PMU_CON62 |
| #define MT6338_RG_BANDGAPGEN_MASK 0x1 |
| #define MT6338_RG_BANDGAPGEN_SHIFT 2 |
| #define MT6338_RG_AUDMICBIAS1HVEN_ADDR \ |
| MT6338_AUDENC_PMU_CON62 |
| #define MT6338_RG_AUDMICBIAS1HVEN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS1HVEN_SHIFT 4 |
| #define MT6338_RG_AUDMICBIAS1HVVREF_ADDR \ |
| MT6338_AUDENC_PMU_CON62 |
| #define MT6338_RG_AUDMICBIAS1HVVREF_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS1HVVREF_SHIFT 5 |
| #define MT6338_RG_AUDPWDBMICBIAS2_ADDR \ |
| MT6338_AUDENC_PMU_CON63 |
| #define MT6338_RG_AUDPWDBMICBIAS2_MASK 0x1 |
| #define MT6338_RG_AUDPWDBMICBIAS2_SHIFT 0 |
| #define MT6338_RG_AUDMICBIAS2BYPASSEN_ADDR \ |
| MT6338_AUDENC_PMU_CON63 |
| #define MT6338_RG_AUDMICBIAS2BYPASSEN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS2BYPASSEN_SHIFT 1 |
| #define MT6338_RG_AUDMICBIAS2LOWPEN_ADDR \ |
| MT6338_AUDENC_PMU_CON63 |
| #define MT6338_RG_AUDMICBIAS2LOWPEN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS2LOWPEN_SHIFT 2 |
| #define MT6338_RG_AUDMICBIAS2ULTRALOWPEN_ADDR \ |
| MT6338_AUDENC_PMU_CON63 |
| #define MT6338_RG_AUDMICBIAS2ULTRALOWPEN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS2ULTRALOWPEN_SHIFT 3 |
| #define MT6338_RG_AUDMICBIAS2VREF_ADDR \ |
| MT6338_AUDENC_PMU_CON63 |
| #define MT6338_RG_AUDMICBIAS2VREF_MASK 0x7 |
| #define MT6338_RG_AUDMICBIAS2VREF_SHIFT 4 |
| #define MT6338_RG_AUDMICBIAS2DCSW0P1EN_ADDR \ |
| MT6338_AUDENC_PMU_CON64 |
| #define MT6338_RG_AUDMICBIAS2DCSW0P1EN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS2DCSW0P1EN_SHIFT 0 |
| #define MT6338_RG_AUDMICBIAS2DCSW0P2EN_ADDR \ |
| MT6338_AUDENC_PMU_CON64 |
| #define MT6338_RG_AUDMICBIAS2DCSW0P2EN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS2DCSW0P2EN_SHIFT 1 |
| #define MT6338_RG_AUDMICBIAS2DCSW0NEN_ADDR \ |
| MT6338_AUDENC_PMU_CON64 |
| #define MT6338_RG_AUDMICBIAS2DCSW0NEN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS2DCSW0NEN_SHIFT 2 |
| #define MT6338_RG_AUDMICBIAS2DCSW2P1EN_ADDR \ |
| MT6338_AUDENC_PMU_CON64 |
| #define MT6338_RG_AUDMICBIAS2DCSW2P1EN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS2DCSW2P1EN_SHIFT 4 |
| #define MT6338_RG_AUDMICBIAS2DCSW2P2EN_ADDR \ |
| MT6338_AUDENC_PMU_CON64 |
| #define MT6338_RG_AUDMICBIAS2DCSW2P2EN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS2DCSW2P2EN_SHIFT 5 |
| #define MT6338_RG_AUDMICBIAS2DCSW2NEN_ADDR \ |
| MT6338_AUDENC_PMU_CON64 |
| #define MT6338_RG_AUDMICBIAS2DCSW2NEN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS2DCSW2NEN_SHIFT 6 |
| #define MT6338_RG_AUDPWDBMICBIAS3_ADDR \ |
| MT6338_AUDENC_PMU_CON65 |
| #define MT6338_RG_AUDPWDBMICBIAS3_MASK 0x1 |
| #define MT6338_RG_AUDPWDBMICBIAS3_SHIFT 0 |
| #define MT6338_RG_AUDMICBIAS3BYPASSEN_ADDR \ |
| MT6338_AUDENC_PMU_CON65 |
| #define MT6338_RG_AUDMICBIAS3BYPASSEN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS3BYPASSEN_SHIFT 1 |
| #define MT6338_RG_AUDMICBIAS3LOWPEN_ADDR \ |
| MT6338_AUDENC_PMU_CON65 |
| #define MT6338_RG_AUDMICBIAS3LOWPEN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS3LOWPEN_SHIFT 2 |
| #define MT6338_RG_AUDMICBIAS3ULTRALOWPEN_ADDR \ |
| MT6338_AUDENC_PMU_CON65 |
| #define MT6338_RG_AUDMICBIAS3ULTRALOWPEN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS3ULTRALOWPEN_SHIFT 3 |
| #define MT6338_RG_AUDMICBIAS3VREF_ADDR \ |
| MT6338_AUDENC_PMU_CON65 |
| #define MT6338_RG_AUDMICBIAS3VREF_MASK 0x7 |
| #define MT6338_RG_AUDMICBIAS3VREF_SHIFT 4 |
| #define MT6338_RG_AUDMICBIAS3DCSW3P1EN_ADDR \ |
| MT6338_AUDENC_PMU_CON66 |
| #define MT6338_RG_AUDMICBIAS3DCSW3P1EN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS3DCSW3P1EN_SHIFT 0 |
| #define MT6338_RG_AUDMICBIAS3DCSW3P2EN_ADDR \ |
| MT6338_AUDENC_PMU_CON66 |
| #define MT6338_RG_AUDMICBIAS3DCSW3P2EN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS3DCSW3P2EN_SHIFT 1 |
| #define MT6338_RG_AUDMICBIAS3DCSW3NEN_ADDR \ |
| MT6338_AUDENC_PMU_CON66 |
| #define MT6338_RG_AUDMICBIAS3DCSW3NEN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS3DCSW3NEN_SHIFT 2 |
| #define MT6338_RG_AUDMICBIAS3DCSW4P1EN_ADDR \ |
| MT6338_AUDENC_PMU_CON66 |
| #define MT6338_RG_AUDMICBIAS3DCSW4P1EN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS3DCSW4P1EN_SHIFT 4 |
| #define MT6338_RG_AUDMICBIAS3DCSW4P2EN_ADDR \ |
| MT6338_AUDENC_PMU_CON66 |
| #define MT6338_RG_AUDMICBIAS3DCSW4P2EN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS3DCSW4P2EN_SHIFT 5 |
| #define MT6338_RG_AUDMICBIAS3DCSW4NEN_ADDR \ |
| MT6338_AUDENC_PMU_CON66 |
| #define MT6338_RG_AUDMICBIAS3DCSW4NEN_MASK 0x1 |
| #define MT6338_RG_AUDMICBIAS3DCSW4NEN_SHIFT 6 |
| #define MT6338_RG_HPL_DC_BIAS_ADDR \ |
| MT6338_AUDENC_PMU_CON67 |
| #define MT6338_RG_HPL_DC_BIAS_MASK 0x1 |
| #define MT6338_RG_HPL_DC_BIAS_SHIFT 0 |
| #define MT6338_RG_HPR_DC_BIAS_ADDR \ |
| MT6338_AUDENC_PMU_CON67 |
| #define MT6338_RG_HPR_DC_BIAS_MASK 0x1 |
| #define MT6338_RG_HPR_DC_BIAS_SHIFT 1 |
| #define MT6338_RG_AUDMICBIASSPARE_ADDR \ |
| MT6338_AUDENC_PMU_CON67 |
| #define MT6338_RG_AUDMICBIASSPARE_MASK 0x3F |
| #define MT6338_RG_AUDMICBIASSPARE_SHIFT 2 |
| #define MT6338_RG_AUDACCDETMICBIAS0PULLLOW_ADDR \ |
| MT6338_AUDENC_PMU_CON68 |
| #define MT6338_RG_AUDACCDETMICBIAS0PULLLOW_MASK 0x1 |
| #define MT6338_RG_AUDACCDETMICBIAS0PULLLOW_SHIFT 0 |
| #define MT6338_RG_AUDACCDETMICBIAS1PULLLOW_ADDR \ |
| MT6338_AUDENC_PMU_CON68 |
| #define MT6338_RG_AUDACCDETMICBIAS1PULLLOW_MASK 0x1 |
| #define MT6338_RG_AUDACCDETMICBIAS1PULLLOW_SHIFT 1 |
| #define MT6338_RG_AUDACCDETMICBIAS2PULLLOW_ADDR \ |
| MT6338_AUDENC_PMU_CON68 |
| #define MT6338_RG_AUDACCDETMICBIAS2PULLLOW_MASK 0x1 |
| #define MT6338_RG_AUDACCDETMICBIAS2PULLLOW_SHIFT 2 |
| #define MT6338_RG_AUDACCDETVIN1PULLLOW_ADDR \ |
| MT6338_AUDENC_PMU_CON68 |
| #define MT6338_RG_AUDACCDETVIN1PULLLOW_MASK 0x1 |
| #define MT6338_RG_AUDACCDETVIN1PULLLOW_SHIFT 3 |
| #define MT6338_RG_AUDACCDETVTHACAL_ADDR \ |
| MT6338_AUDENC_PMU_CON68 |
| #define MT6338_RG_AUDACCDETVTHACAL_MASK 0x1 |
| #define MT6338_RG_AUDACCDETVTHACAL_SHIFT 4 |
| #define MT6338_RG_AUDACCDETVTHBCAL_ADDR \ |
| MT6338_AUDENC_PMU_CON68 |
| #define MT6338_RG_AUDACCDETVTHBCAL_MASK 0x1 |
| #define MT6338_RG_AUDACCDETVTHBCAL_SHIFT 5 |
| #define MT6338_RG_AUDACCDETTVDET_ADDR \ |
| MT6338_AUDENC_PMU_CON68 |
| #define MT6338_RG_AUDACCDETTVDET_MASK 0x1 |
| #define MT6338_RG_AUDACCDETTVDET_SHIFT 6 |
| #define MT6338_RG_ACCDETSEL_ADDR \ |
| MT6338_AUDENC_PMU_CON68 |
| #define MT6338_RG_ACCDETSEL_MASK 0x1 |
| #define MT6338_RG_ACCDETSEL_SHIFT 7 |
| #define MT6338_RG_SWBUFMODSEL_ADDR \ |
| MT6338_AUDENC_PMU_CON69 |
| #define MT6338_RG_SWBUFMODSEL_MASK 0x1 |
| #define MT6338_RG_SWBUFMODSEL_SHIFT 0 |
| #define MT6338_RG_SWBUFSWEN_ADDR \ |
| MT6338_AUDENC_PMU_CON69 |
| #define MT6338_RG_SWBUFSWEN_MASK 0x1 |
| #define MT6338_RG_SWBUFSWEN_SHIFT 1 |
| #define MT6338_RG_EINT0NOHYS_ADDR \ |
| MT6338_AUDENC_PMU_CON69 |
| #define MT6338_RG_EINT0NOHYS_MASK 0x1 |
| #define MT6338_RG_EINT0NOHYS_SHIFT 2 |
| #define MT6338_RG_EINT0CONFIGACCDET_ADDR \ |
| MT6338_AUDENC_PMU_CON69 |
| #define MT6338_RG_EINT0CONFIGACCDET_MASK 0x1 |
| #define MT6338_RG_EINT0CONFIGACCDET_SHIFT 3 |
| #define MT6338_RG_EINT0HIRENB_ADDR \ |
| MT6338_AUDENC_PMU_CON69 |
| #define MT6338_RG_EINT0HIRENB_MASK 0x1 |
| #define MT6338_RG_EINT0HIRENB_SHIFT 4 |
| #define MT6338_RG_ACCDET2AUXRESBYPASS_ADDR \ |
| MT6338_AUDENC_PMU_CON69 |
| #define MT6338_RG_ACCDET2AUXRESBYPASS_MASK 0x1 |
| #define MT6338_RG_ACCDET2AUXRESBYPASS_SHIFT 5 |
| #define MT6338_RG_ACCDET2AUXSWEN_ADDR \ |
| MT6338_AUDENC_PMU_CON69 |
| #define MT6338_RG_ACCDET2AUXSWEN_MASK 0x1 |
| #define MT6338_RG_ACCDET2AUXSWEN_SHIFT 6 |
| #define MT6338_RG_AUDACCDETMICBIAS3PULLLOW_ADDR \ |
| MT6338_AUDENC_PMU_CON69 |
| #define MT6338_RG_AUDACCDETMICBIAS3PULLLOW_MASK 0x1 |
| #define MT6338_RG_AUDACCDETMICBIAS3PULLLOW_SHIFT 7 |
| #define MT6338_RG_EINT1CONFIGACCDET_ADDR \ |
| MT6338_AUDENC_PMU_CON70 |
| #define MT6338_RG_EINT1CONFIGACCDET_MASK 0x1 |
| #define MT6338_RG_EINT1CONFIGACCDET_SHIFT 0 |
| #define MT6338_RG_EINT1HIRENB_ADDR \ |
| MT6338_AUDENC_PMU_CON70 |
| #define MT6338_RG_EINT1HIRENB_MASK 0x1 |
| #define MT6338_RG_EINT1HIRENB_SHIFT 1 |
| #define MT6338_RG_EINT1NOHYS_ADDR \ |
| MT6338_AUDENC_PMU_CON70 |
| #define MT6338_RG_EINT1NOHYS_MASK 0x1 |
| #define MT6338_RG_EINT1NOHYS_SHIFT 2 |
| #define MT6338_RG_EINTCOMPVTH_ADDR \ |
| MT6338_AUDENC_PMU_CON70 |
| #define MT6338_RG_EINTCOMPVTH_MASK 0xF |
| #define MT6338_RG_EINTCOMPVTH_SHIFT 4 |
| #define MT6338_RG_MTEST_EN_ADDR \ |
| MT6338_AUDENC_PMU_CON71 |
| #define MT6338_RG_MTEST_EN_MASK 0x1 |
| #define MT6338_RG_MTEST_EN_SHIFT 0 |
| #define MT6338_RG_MTEST_SEL_ADDR \ |
| MT6338_AUDENC_PMU_CON71 |
| #define MT6338_RG_MTEST_SEL_MASK 0x1 |
| #define MT6338_RG_MTEST_SEL_SHIFT 1 |
| #define MT6338_RG_MTEST_CURRENT_ADDR \ |
| MT6338_AUDENC_PMU_CON71 |
| #define MT6338_RG_MTEST_CURRENT_MASK 0x1 |
| #define MT6338_RG_MTEST_CURRENT_SHIFT 2 |
| #define MT6338_RG_ANALOGFDEN_ADDR \ |
| MT6338_AUDENC_PMU_CON71 |
| #define MT6338_RG_ANALOGFDEN_MASK 0x1 |
| #define MT6338_RG_ANALOGFDEN_SHIFT 4 |
| #define MT6338_RG_FDVIN1PPULLLOW_ADDR \ |
| MT6338_AUDENC_PMU_CON71 |
| #define MT6338_RG_FDVIN1PPULLLOW_MASK 0x1 |
| #define MT6338_RG_FDVIN1PPULLLOW_SHIFT 5 |
| #define MT6338_RG_FDEINT0TYPE_ADDR \ |
| MT6338_AUDENC_PMU_CON71 |
| #define MT6338_RG_FDEINT0TYPE_MASK 0x1 |
| #define MT6338_RG_FDEINT0TYPE_SHIFT 6 |
| #define MT6338_RG_FDEINT1TYPE_ADDR \ |
| MT6338_AUDENC_PMU_CON71 |
| #define MT6338_RG_FDEINT1TYPE_MASK 0x1 |
| #define MT6338_RG_FDEINT1TYPE_SHIFT 7 |
| #define MT6338_RG_EINT0CMPEN_ADDR \ |
| MT6338_AUDENC_PMU_CON72 |
| #define MT6338_RG_EINT0CMPEN_MASK 0x1 |
| #define MT6338_RG_EINT0CMPEN_SHIFT 0 |
| #define MT6338_RG_EINT0CMPMEN_ADDR \ |
| MT6338_AUDENC_PMU_CON72 |
| #define MT6338_RG_EINT0CMPMEN_MASK 0x1 |
| #define MT6338_RG_EINT0CMPMEN_SHIFT 1 |
| #define MT6338_RG_EINT0EN_ADDR \ |
| MT6338_AUDENC_PMU_CON72 |
| #define MT6338_RG_EINT0EN_MASK 0x1 |
| #define MT6338_RG_EINT0EN_SHIFT 2 |
| #define MT6338_RG_EINT0CEN_ADDR \ |
| MT6338_AUDENC_PMU_CON72 |
| #define MT6338_RG_EINT0CEN_MASK 0x1 |
| #define MT6338_RG_EINT0CEN_SHIFT 3 |
| #define MT6338_RG_EINT0INVEN_ADDR \ |
| MT6338_AUDENC_PMU_CON72 |
| #define MT6338_RG_EINT0INVEN_MASK 0x1 |
| #define MT6338_RG_EINT0INVEN_SHIFT 4 |
| #define MT6338_RG_EINT1CMPEN_ADDR \ |
| MT6338_AUDENC_PMU_CON73 |
| #define MT6338_RG_EINT1CMPEN_MASK 0x1 |
| #define MT6338_RG_EINT1CMPEN_SHIFT 0 |
| #define MT6338_RG_EINT1CMPMEN_ADDR \ |
| MT6338_AUDENC_PMU_CON73 |
| #define MT6338_RG_EINT1CMPMEN_MASK 0x1 |
| #define MT6338_RG_EINT1CMPMEN_SHIFT 1 |
| #define MT6338_RG_EINT1EN_ADDR \ |
| MT6338_AUDENC_PMU_CON73 |
| #define MT6338_RG_EINT1EN_MASK 0x1 |
| #define MT6338_RG_EINT1EN_SHIFT 2 |
| #define MT6338_RG_EINT1CEN_ADDR \ |
| MT6338_AUDENC_PMU_CON73 |
| #define MT6338_RG_EINT1CEN_MASK 0x1 |
| #define MT6338_RG_EINT1CEN_SHIFT 3 |
| #define MT6338_RG_EINT1INVEN_ADDR \ |
| MT6338_AUDENC_PMU_CON73 |
| #define MT6338_RG_EINT1INVEN_MASK 0x1 |
| #define MT6338_RG_EINT1INVEN_SHIFT 4 |
| #define MT6338_RG_ACCDET_PL_ESDMOS_ADDR \ |
| MT6338_AUDENC_PMU_CON74 |
| #define MT6338_RG_ACCDET_PL_ESDMOS_MASK 0x1 |
| #define MT6338_RG_ACCDET_PL_ESDMOS_SHIFT 0 |
| #define MT6338_RG_VIN1OFFENB_ADDR \ |
| MT6338_AUDENC_PMU_CON74 |
| #define MT6338_RG_VIN1OFFENB_MASK 0x1 |
| #define MT6338_RG_VIN1OFFENB_SHIFT 1 |
| #define MT6338_RG_ACC_OR_DCC_ADDR \ |
| MT6338_AUDENC_PMU_CON74 |
| #define MT6338_RG_ACC_OR_DCC_MASK 0x1 |
| #define MT6338_RG_ACC_OR_DCC_SHIFT 2 |
| #define MT6338_RG_MVTH2EN_ADDR \ |
| MT6338_AUDENC_PMU_CON74 |
| #define MT6338_RG_MVTH2EN_MASK 0x1 |
| #define MT6338_RG_MVTH2EN_SHIFT 3 |
| #define MT6338_RG_MVTH2SEL_ADDR \ |
| MT6338_AUDENC_PMU_CON74 |
| #define MT6338_RG_MVTH2SEL_MASK 0xF |
| #define MT6338_RG_MVTH2SEL_SHIFT 4 |
| #define MT6338_RG_ACCDETSPARE_ADDR \ |
| MT6338_AUDENC_PMU_CON75 |
| #define MT6338_RG_ACCDETSPARE_MASK 0xFF |
| #define MT6338_RG_ACCDETSPARE_SHIFT 0 |
| #define MT6338_RG_ACCDETSPARE2_ADDR \ |
| MT6338_AUDENC_PMU_CON76 |
| #define MT6338_RG_ACCDETSPARE2_MASK 0xFF |
| #define MT6338_RG_ACCDETSPARE2_SHIFT 0 |
| #define MT6338_RG_EINT0CTURBO_ADDR \ |
| MT6338_AUDENC_PMU_CON77 |
| #define MT6338_RG_EINT0CTURBO_MASK 0x1F |
| #define MT6338_RG_EINT0CTURBO_SHIFT 0 |
| #define MT6338_RG_EINT1CTURBO_ADDR \ |
| MT6338_AUDENC_PMU_CON78 |
| #define MT6338_RG_EINT1CTURBO_MASK 0x1F |
| #define MT6338_RG_EINT1CTURBO_SHIFT 0 |
| #define MT6338_RG_AUDENCSPAREVA30_ADDR \ |
| MT6338_AUDENC_PMU_CON79 |
| #define MT6338_RG_AUDENCSPAREVA30_MASK 0xFF |
| #define MT6338_RG_AUDENCSPAREVA30_SHIFT 0 |
| #define MT6338_RG_AUDENCSPAREVA18_ADDR \ |
| MT6338_AUDENC_PMU_CON80 |
| #define MT6338_RG_AUDENCSPAREVA18_MASK 0xFF |
| #define MT6338_RG_AUDENCSPAREVA18_SHIFT 0 |
| #define MT6338_RG_ADCL_CLKMODE_ADDR \ |
| MT6338_AUDENC_PMU_CON81 |
| #define MT6338_RG_ADCL_CLKMODE_MASK 0x1 |
| #define MT6338_RG_ADCL_CLKMODE_SHIFT 0 |
| #define MT6338_RG_ADCR_CLKMODE_ADDR \ |
| MT6338_AUDENC_PMU_CON81 |
| #define MT6338_RG_ADCR_CLKMODE_MASK 0x1 |
| #define MT6338_RG_ADCR_CLKMODE_SHIFT 1 |
| #define MT6338_RG_ADC3_CLKMODE_ADDR \ |
| MT6338_AUDENC_PMU_CON81 |
| #define MT6338_RG_ADC3_CLKMODE_MASK 0x1 |
| #define MT6338_RG_ADC3_CLKMODE_SHIFT 2 |
| #define MT6338_RG_ADC4_CLKMODE_ADDR \ |
| MT6338_AUDENC_PMU_CON81 |
| #define MT6338_RG_ADC4_CLKMODE_MASK 0x1 |
| #define MT6338_RG_ADC4_CLKMODE_SHIFT 3 |
| #define MT6338_AUDENC_ELR_LEN_ADDR \ |
| MT6338_AUDENC_ELR_NUM |
| #define MT6338_AUDENC_ELR_LEN_MASK 0xFF |
| #define MT6338_AUDENC_ELR_LEN_SHIFT 0 |
| #define MT6338_RG_VCM_PGA_HIFI_SEL_ADDR \ |
| MT6338_AUDENC_ELR_0 |
| #define MT6338_RG_VCM_PGA_HIFI_SEL_MASK 0xF |
| #define MT6338_RG_VCM_PGA_HIFI_SEL_SHIFT 0 |
| #define MT6338_RG_VCM_PGA_LPM_SEL_ADDR \ |
| MT6338_AUDENC_ELR_0 |
| #define MT6338_RG_VCM_PGA_LPM_SEL_MASK 0xF |
| #define MT6338_RG_VCM_PGA_LPM_SEL_SHIFT 4 |
| #define MT6338_RG_AUDLADCFLASHFFCAPVREF_SEL_ADDR \ |
| MT6338_AUDENC_ELR_1 |
| #define MT6338_RG_AUDLADCFLASHFFCAPVREF_SEL_MASK 0x3 |
| #define MT6338_RG_AUDLADCFLASHFFCAPVREF_SEL_SHIFT 0 |
| #define MT6338_RG_AUDRADCFLASHFFCAPVREF_SEL_ADDR \ |
| MT6338_AUDENC_ELR_1 |
| #define MT6338_RG_AUDRADCFLASHFFCAPVREF_SEL_MASK 0x3 |
| #define MT6338_RG_AUDRADCFLASHFFCAPVREF_SEL_SHIFT 2 |
| #define MT6338_RG_AUD3ADCFLASHFFCAPVREF_SEL_ADDR \ |
| MT6338_AUDENC_ELR_1 |
| #define MT6338_RG_AUD3ADCFLASHFFCAPVREF_SEL_MASK 0x3 |
| #define MT6338_RG_AUD3ADCFLASHFFCAPVREF_SEL_SHIFT 4 |
| #define MT6338_RG_AUD4ADCFLASHFFCAPVREF_SEL_ADDR \ |
| MT6338_AUDENC_ELR_1 |
| #define MT6338_RG_AUD4ADCFLASHFFCAPVREF_SEL_MASK 0x3 |
| #define MT6338_RG_AUD4ADCFLASHFFCAPVREF_SEL_SHIFT 6 |
| #define MT6338_RG_VCMR_PGA_HIFI_SEL_ADDR \ |
| MT6338_AUDENC_ELR_2 |
| #define MT6338_RG_VCMR_PGA_HIFI_SEL_MASK 0xF |
| #define MT6338_RG_VCMR_PGA_HIFI_SEL_SHIFT 0 |
| #define MT6338_RG_VCMR_PGA_LPM_SEL_ADDR \ |
| MT6338_AUDENC_ELR_2 |
| #define MT6338_RG_VCMR_PGA_LPM_SEL_MASK 0xF |
| #define MT6338_RG_VCMR_PGA_LPM_SEL_SHIFT 4 |
| #define MT6338_RG_VCM3_PGA_HIFI_SEL_ADDR \ |
| MT6338_AUDENC_ELR_3 |
| #define MT6338_RG_VCM3_PGA_HIFI_SEL_MASK 0xF |
| #define MT6338_RG_VCM3_PGA_HIFI_SEL_SHIFT 0 |
| #define MT6338_RG_VCM3_PGA_LPM_SEL_ADDR \ |
| MT6338_AUDENC_ELR_3 |
| #define MT6338_RG_VCM3_PGA_LPM_SEL_MASK 0xF |
| #define MT6338_RG_VCM3_PGA_LPM_SEL_SHIFT 4 |
| #define MT6338_RG_VCM4_PGA_HIFI_SEL_ADDR \ |
| MT6338_AUDENC_ELR_4 |
| #define MT6338_RG_VCM4_PGA_HIFI_SEL_MASK 0xF |
| #define MT6338_RG_VCM4_PGA_HIFI_SEL_SHIFT 0 |
| #define MT6338_RG_VCM4_PGA_LPM_SEL_ADDR \ |
| MT6338_AUDENC_ELR_4 |
| #define MT6338_RG_VCM4_PGA_LPM_SEL_MASK 0xF |
| #define MT6338_RG_VCM4_PGA_LPM_SEL_SHIFT 4 |
| #define MT6338_AUDDEC_ANA_ID_ADDR \ |
| MT6338_AUDDEC_ANA_ID |
| #define MT6338_AUDDEC_ANA_ID_MASK 0xFF |
| #define MT6338_AUDDEC_ANA_ID_SHIFT 0 |
| #define MT6338_AUDDEC_DIG_ID_ADDR \ |
| MT6338_AUDDEC_DIG_ID |
| #define MT6338_AUDDEC_DIG_ID_MASK 0xFF |
| #define MT6338_AUDDEC_DIG_ID_SHIFT 0 |
| #define MT6338_AUDDEC_ANA_MINOR_REV_ADDR \ |
| MT6338_AUDDEC_ANA_REV |
| #define MT6338_AUDDEC_ANA_MINOR_REV_MASK 0xF |
| #define MT6338_AUDDEC_ANA_MINOR_REV_SHIFT 0 |
| #define MT6338_AUDDEC_ANA_MAJOR_REV_ADDR \ |
| MT6338_AUDDEC_ANA_REV |
| #define MT6338_AUDDEC_ANA_MAJOR_REV_MASK 0xF |
| #define MT6338_AUDDEC_ANA_MAJOR_REV_SHIFT 4 |
| #define MT6338_AUDDEC_DIG_MINOR_REV_ADDR \ |
| MT6338_AUDDEC_DIG_REV |
| #define MT6338_AUDDEC_DIG_MINOR_REV_MASK 0xF |
| #define MT6338_AUDDEC_DIG_MINOR_REV_SHIFT 0 |
| #define MT6338_AUDDEC_DIG_MAJOR_REV_ADDR \ |
| MT6338_AUDDEC_DIG_REV |
| #define MT6338_AUDDEC_DIG_MAJOR_REV_MASK 0xF |
| #define MT6338_AUDDEC_DIG_MAJOR_REV_SHIFT 4 |
| #define MT6338_AUDDEC_CBS_ADDR \ |
| MT6338_AUDDEC_DBI |
| #define MT6338_AUDDEC_CBS_MASK 0x3 |
| #define MT6338_AUDDEC_CBS_SHIFT 0 |
| #define MT6338_AUDDEC_BIX_ADDR \ |
| MT6338_AUDDEC_DBI |
| #define MT6338_AUDDEC_BIX_MASK 0x3 |
| #define MT6338_AUDDEC_BIX_SHIFT 2 |
| #define MT6338_AUDDEC_ESP_ADDR \ |
| MT6338_AUDDEC_ESP |
| #define MT6338_AUDDEC_ESP_MASK 0xFF |
| #define MT6338_AUDDEC_ESP_SHIFT 0 |
| #define MT6338_AUDDEC_FPI_ADDR \ |
| MT6338_AUDDEC_FPI |
| #define MT6338_AUDDEC_FPI_MASK 0xFF |
| #define MT6338_AUDDEC_FPI_SHIFT 0 |
| #define MT6338_AUDDEC_DXI_ADDR \ |
| MT6338_AUDDEC_DXI |
| #define MT6338_AUDDEC_DXI_MASK 0xFF |
| #define MT6338_AUDDEC_DXI_SHIFT 0 |
| #define MT6338_RG_AUDDACL_PWRUP_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON0 |
| #define MT6338_RG_AUDDACL_PWRUP_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDDACL_PWRUP_VAUDP18_SHIFT 0 |
| #define MT6338_RG_AUDDACR_PWRUP_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON0 |
| #define MT6338_RG_AUDDACR_PWRUP_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDDACR_PWRUP_VAUDP18_SHIFT 1 |
| #define MT6338_RG_AUDDACHS_PWRUP_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON0 |
| #define MT6338_RG_AUDDACHS_PWRUP_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDDACHS_PWRUP_VAUDP18_SHIFT 2 |
| #define MT6338_RG_AUDDACLO_PWRUP_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON0 |
| #define MT6338_RG_AUDDACLO_PWRUP_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDDACLO_PWRUP_VAUDP18_SHIFT 3 |
| #define MT6338_RG_AUDDACL_BIAS_PWRUP_VA32_ADDR \ |
| MT6338_AUDDEC_PMU_CON0 |
| #define MT6338_RG_AUDDACL_BIAS_PWRUP_VA32_MASK 0x1 |
| #define MT6338_RG_AUDDACL_BIAS_PWRUP_VA32_SHIFT 4 |
| #define MT6338_RG_AUDDACR_BIAS_PWRUP_VA32_ADDR \ |
| MT6338_AUDDEC_PMU_CON0 |
| #define MT6338_RG_AUDDACR_BIAS_PWRUP_VA32_MASK 0x1 |
| #define MT6338_RG_AUDDACR_BIAS_PWRUP_VA32_SHIFT 5 |
| #define MT6338_RG_AUDDACHS_BIAS_PWRUP_VA32_ADDR \ |
| MT6338_AUDDEC_PMU_CON0 |
| #define MT6338_RG_AUDDACHS_BIAS_PWRUP_VA32_MASK 0x1 |
| #define MT6338_RG_AUDDACHS_BIAS_PWRUP_VA32_SHIFT 6 |
| #define MT6338_RG_AUDDACLO_BIAS_PWRUP_VA32_ADDR \ |
| MT6338_AUDDEC_PMU_CON0 |
| #define MT6338_RG_AUDDACLO_BIAS_PWRUP_VA32_MASK 0x1 |
| #define MT6338_RG_AUDDACLO_BIAS_PWRUP_VA32_SHIFT 7 |
| #define MT6338_RG_AUDDAC_L_RPWM_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON1 |
| #define MT6338_RG_AUDDAC_L_RPWM_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDDAC_L_RPWM_EN_VAUDP18_SHIFT 0 |
| #define MT6338_RG_AUDDAC_R_RPWM_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON1 |
| #define MT6338_RG_AUDDAC_R_RPWM_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDDAC_R_RPWM_EN_VAUDP18_SHIFT 1 |
| #define MT6338_RG_AUDDAC_IREF_LN_SEL_VA32_ADDR \ |
| MT6338_AUDDEC_PMU_CON1 |
| #define MT6338_RG_AUDDAC_IREF_LN_SEL_VA32_MASK 0x3 |
| #define MT6338_RG_AUDDAC_IREF_LN_SEL_VA32_SHIFT 4 |
| #define MT6338_RG_AUDDAC_IREF_LN_EN_VA32_ADDR \ |
| MT6338_AUDDEC_PMU_CON1 |
| #define MT6338_RG_AUDDAC_IREF_LN_EN_VA32_MASK 0x1 |
| #define MT6338_RG_AUDDAC_IREF_LN_EN_VA32_SHIFT 6 |
| #define MT6338_RG_AUDDAC_ILOCAL_LN_SEL_VA32_ADDR \ |
| MT6338_AUDDEC_PMU_CON2 |
| #define MT6338_RG_AUDDAC_ILOCAL_LN_SEL_VA32_MASK 0x3 |
| #define MT6338_RG_AUDDAC_ILOCAL_LN_SEL_VA32_SHIFT 0 |
| #define MT6338_RG_AUDDAC_ILOCAL_LN_EN_VA32_ADDR \ |
| MT6338_AUDDEC_PMU_CON2 |
| #define MT6338_RG_AUDDAC_ILOCAL_LN_EN_VA32_MASK 0x1 |
| #define MT6338_RG_AUDDAC_ILOCAL_LN_EN_VA32_SHIFT 2 |
| #define MT6338_RG_AUDDAC_OPAMP_LN_EN_VA32_ADDR \ |
| MT6338_AUDDEC_PMU_CON2 |
| #define MT6338_RG_AUDDAC_OPAMP_LN_EN_VA32_MASK 0x1 |
| #define MT6338_RG_AUDDAC_OPAMP_LN_EN_VA32_SHIFT 4 |
| #define MT6338_RG_AUDDAC_RSVD0_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON3 |
| #define MT6338_RG_AUDDAC_RSVD0_VAUDP18_MASK 0xFF |
| #define MT6338_RG_AUDDAC_RSVD0_VAUDP18_SHIFT 0 |
| #define MT6338_RG_AUDHPLPWRUP_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON4 |
| #define MT6338_RG_AUDHPLPWRUP_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPLPWRUP_VAUDP18_SHIFT 0 |
| #define MT6338_RG_AUDHPRPWRUP_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON4 |
| #define MT6338_RG_AUDHPRPWRUP_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPRPWRUP_VAUDP18_SHIFT 1 |
| #define MT6338_RG_AUDHPLPWRUP_IBIAS_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON4 |
| #define MT6338_RG_AUDHPLPWRUP_IBIAS_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPLPWRUP_IBIAS_VAUDP18_SHIFT 2 |
| #define MT6338_RG_AUDHPRPWRUP_IBIAS_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON4 |
| #define MT6338_RG_AUDHPRPWRUP_IBIAS_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPRPWRUP_IBIAS_VAUDP18_SHIFT 3 |
| #define MT6338_RG_AUDHPLMUXINPUTSEL_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON4 |
| #define MT6338_RG_AUDHPLMUXINPUTSEL_VAUDP18_MASK 0x3 |
| #define MT6338_RG_AUDHPLMUXINPUTSEL_VAUDP18_SHIFT 4 |
| #define MT6338_RG_AUDHPRMUXINPUTSEL_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON4 |
| #define MT6338_RG_AUDHPRMUXINPUTSEL_VAUDP18_MASK 0x3 |
| #define MT6338_RG_AUDHPRMUXINPUTSEL_VAUDP18_SHIFT 6 |
| #define MT6338_RG_AUDHPLSCDISABLE_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON5 |
| #define MT6338_RG_AUDHPLSCDISABLE_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPLSCDISABLE_VAUDP18_SHIFT 0 |
| #define MT6338_RG_AUDHPRSCDISABLE_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON5 |
| #define MT6338_RG_AUDHPRSCDISABLE_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPRSCDISABLE_VAUDP18_SHIFT 1 |
| #define MT6338_RG_AUDHPLBSCCURRENT_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON5 |
| #define MT6338_RG_AUDHPLBSCCURRENT_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPLBSCCURRENT_VAUDP18_SHIFT 2 |
| #define MT6338_RG_AUDHPRBSCCURRENT_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON5 |
| #define MT6338_RG_AUDHPRBSCCURRENT_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPRBSCCURRENT_VAUDP18_SHIFT 3 |
| #define MT6338_RG_AUDHPLOUTPWRUP_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON5 |
| #define MT6338_RG_AUDHPLOUTPWRUP_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPLOUTPWRUP_VAUDP18_SHIFT 4 |
| #define MT6338_RG_AUDHPROUTPWRUP_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON5 |
| #define MT6338_RG_AUDHPROUTPWRUP_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPROUTPWRUP_VAUDP18_SHIFT 5 |
| #define MT6338_RG_AUDHPLOUTAUXPWRUP_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON5 |
| #define MT6338_RG_AUDHPLOUTAUXPWRUP_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPLOUTAUXPWRUP_VAUDP18_SHIFT 6 |
| #define MT6338_RG_AUDHPROUTAUXPWRUP_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON5 |
| #define MT6338_RG_AUDHPROUTAUXPWRUP_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPROUTAUXPWRUP_VAUDP18_SHIFT 7 |
| #define MT6338_RG_HPLAUXFBRSW_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON6 |
| #define MT6338_RG_HPLAUXFBRSW_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_HPLAUXFBRSW_EN_VAUDP18_SHIFT 0 |
| #define MT6338_RG_HPRAUXFBRSW_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON6 |
| #define MT6338_RG_HPRAUXFBRSW_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_HPRAUXFBRSW_EN_VAUDP18_SHIFT 1 |
| #define MT6338_RG_HPLSHORT2HPLAUX_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON6 |
| #define MT6338_RG_HPLSHORT2HPLAUX_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_HPLSHORT2HPLAUX_EN_VAUDP18_SHIFT 2 |
| #define MT6338_RG_HPRSHORT2HPRAUX_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON6 |
| #define MT6338_RG_HPRSHORT2HPRAUX_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_HPRSHORT2HPRAUX_EN_VAUDP18_SHIFT 3 |
| #define MT6338_RG_HPLOUTPUTSTBENH_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON6 |
| #define MT6338_RG_HPLOUTPUTSTBENH_VAUDP18_MASK 0x7 |
| #define MT6338_RG_HPLOUTPUTSTBENH_VAUDP18_SHIFT 4 |
| #define MT6338_RG_HPROUTPUTSTBENH_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON7 |
| #define MT6338_RG_HPROUTPUTSTBENH_VAUDP18_MASK 0x7 |
| #define MT6338_RG_HPROUTPUTSTBENH_VAUDP18_SHIFT 0 |
| #define MT6338_RG_HPLMUTE_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON7 |
| #define MT6338_RG_HPLMUTE_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_HPLMUTE_EN_VAUDP18_SHIFT 4 |
| #define MT6338_RG_HPRMUTE_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON7 |
| #define MT6338_RG_HPRMUTE_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_HPRMUTE_EN_VAUDP18_SHIFT 5 |
| #define MT6338_RG_AUDHPLAUXCM_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON7 |
| #define MT6338_RG_AUDHPLAUXCM_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPLAUXCM_EN_VAUDP18_SHIFT 6 |
| #define MT6338_RG_AUDHPRAUXCM_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON7 |
| #define MT6338_RG_AUDHPRAUXCM_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPRAUXCM_EN_VAUDP18_SHIFT 7 |
| #define MT6338_RG_AUDHPLAUXGAIN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON8 |
| #define MT6338_RG_AUDHPLAUXGAIN_VAUDP18_MASK 0xF |
| #define MT6338_RG_AUDHPLAUXGAIN_VAUDP18_SHIFT 0 |
| #define MT6338_RG_AUDHPRAUXGAIN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON8 |
| #define MT6338_RG_AUDHPRAUXGAIN_VAUDP18_MASK 0xF |
| #define MT6338_RG_AUDHPRAUXGAIN_VAUDP18_SHIFT 4 |
| #define MT6338_RG_AUDHPLMAINCM2_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON9 |
| #define MT6338_RG_AUDHPLMAINCM2_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPLMAINCM2_EN_VAUDP18_SHIFT 0 |
| #define MT6338_RG_AUDHPRMAINCM2_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON9 |
| #define MT6338_RG_AUDHPRMAINCM2_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPRMAINCM2_EN_VAUDP18_SHIFT 1 |
| #define MT6338_RG_AUDHPLCMFB_RNWSEL_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON9 |
| #define MT6338_RG_AUDHPLCMFB_RNWSEL_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPLCMFB_RNWSEL_VAUDP18_SHIFT 2 |
| #define MT6338_RG_AUDHPRCMFB_RNWSEL_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON9 |
| #define MT6338_RG_AUDHPRCMFB_RNWSEL_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPRCMFB_RNWSEL_VAUDP18_SHIFT 3 |
| #define MT6338_RG_AUDHPLHPFB_RNWSEL_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON9 |
| #define MT6338_RG_AUDHPLHPFB_RNWSEL_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPLHPFB_RNWSEL_VAUDP18_SHIFT 4 |
| #define MT6338_RG_AUDHPRHPFB_RNWSEL_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON9 |
| #define MT6338_RG_AUDHPRHPFB_RNWSEL_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPRHPFB_RNWSEL_VAUDP18_SHIFT 5 |
| #define MT6338_RG_HPLHDRM_PFL_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON9 |
| #define MT6338_RG_HPLHDRM_PFL_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_HPLHDRM_PFL_EN_VAUDP18_SHIFT 6 |
| #define MT6338_RG_HPRHDRM_PFL_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON9 |
| #define MT6338_RG_HPRHDRM_PFL_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_HPRHDRM_PFL_EN_VAUDP18_SHIFT 7 |
| #define MT6338_RG_HPLHDRMSW_ST_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON10 |
| #define MT6338_RG_HPLHDRMSW_ST_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_HPLHDRMSW_ST_EN_VAUDP18_SHIFT 0 |
| #define MT6338_RG_HPRHDRMSW_ST_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON10 |
| #define MT6338_RG_HPRHDRMSW_ST_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_HPRHDRMSW_ST_EN_VAUDP18_SHIFT 1 |
| #define MT6338_RG_AUDHPSTARTUP_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON10 |
| #define MT6338_RG_AUDHPSTARTUP_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPSTARTUP_VAUDP18_SHIFT 2 |
| #define MT6338_RG_AUDREFN_DERES_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON10 |
| #define MT6338_RG_AUDREFN_DERES_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDREFN_DERES_EN_VAUDP18_SHIFT 3 |
| #define MT6338_RG_HPINPUTSTBENH_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON10 |
| #define MT6338_RG_HPINPUTSTBENH_VAUDP18_MASK 0x1 |
| #define MT6338_RG_HPINPUTSTBENH_VAUDP18_SHIFT 4 |
| #define MT6338_RG_HPINPUTRESET0_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON10 |
| #define MT6338_RG_HPINPUTRESET0_VAUDP18_MASK 0x1 |
| #define MT6338_RG_HPINPUTRESET0_VAUDP18_SHIFT 5 |
| #define MT6338_RG_HPOUTPUTRESET0_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON10 |
| #define MT6338_RG_HPOUTPUTRESET0_VAUDP18_MASK 0x1 |
| #define MT6338_RG_HPOUTPUTRESET0_VAUDP18_SHIFT 6 |
| #define MT6338_RG_HPPSHORT2VCM_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON11 |
| #define MT6338_RG_HPPSHORT2VCM_VAUDP18_MASK 0x7 |
| #define MT6338_RG_HPPSHORT2VCM_VAUDP18_SHIFT 0 |
| #define MT6338_RG_AUDHPTRIM_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON11 |
| #define MT6338_RG_AUDHPTRIM_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPTRIM_EN_VAUDP18_SHIFT 4 |
| #define MT6338_RG_AUDHPLFINETRIM_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON12 |
| #define MT6338_RG_AUDHPLFINETRIM_VAUDP18_MASK 0x7 |
| #define MT6338_RG_AUDHPLFINETRIM_VAUDP18_SHIFT 0 |
| #define MT6338_RG_AUDHPLTRIM_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON12 |
| #define MT6338_RG_AUDHPLTRIM_VAUDP18_MASK 0x1F |
| #define MT6338_RG_AUDHPLTRIM_VAUDP18_SHIFT 3 |
| #define MT6338_RG_AUDHPRFINETRIM_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON13 |
| #define MT6338_RG_AUDHPRFINETRIM_VAUDP18_MASK 0x7 |
| #define MT6338_RG_AUDHPRFINETRIM_VAUDP18_SHIFT 0 |
| #define MT6338_RG_AUDHPRTRIM_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON13 |
| #define MT6338_RG_AUDHPRTRIM_VAUDP18_MASK 0x1F |
| #define MT6338_RG_AUDHPRTRIM_VAUDP18_SHIFT 3 |
| #define MT6338_RG_AUDHPDIFFINPBIASADJ_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON14 |
| #define MT6338_RG_AUDHPDIFFINPBIASADJ_VAUDP18_MASK 0x3 |
| #define MT6338_RG_AUDHPDIFFINPBIASADJ_VAUDP18_SHIFT 0 |
| #define MT6338_RG_AUDHPDAMP_ADJ_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON14 |
| #define MT6338_RG_AUDHPDAMP_ADJ_VAUDP18_MASK 0x3 |
| #define MT6338_RG_AUDHPDAMP_ADJ_VAUDP18_SHIFT 4 |
| #define MT6338_RG_AUDHPDAMP_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON15 |
| #define MT6338_RG_AUDHPDAMP_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPDAMP_EN_VAUDP18_SHIFT 0 |
| #define MT6338_RG_DAMP2ND_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON15 |
| #define MT6338_RG_DAMP2ND_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_DAMP2ND_EN_VAUDP18_SHIFT 1 |
| #define MT6338_RG_HPMUXST_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON15 |
| #define MT6338_RG_HPMUXST_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_HPMUXST_EN_VAUDP18_SHIFT 2 |
| #define MT6338_RG_AUDHPHFCOMPBUFGAINSEL_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON15 |
| #define MT6338_RG_AUDHPHFCOMPBUFGAINSEL_VAUDP18_MASK 0x3 |
| #define MT6338_RG_AUDHPHFCOMPBUFGAINSEL_VAUDP18_SHIFT 4 |
| #define MT6338_RG_NREGPRESET_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON16 |
| #define MT6338_RG_NREGPRESET_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_NREGPRESET_EN_VAUDP18_SHIFT 0 |
| #define MT6338_RG_AUDHPHIFISWST_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON16 |
| #define MT6338_RG_AUDHPHIFISWST_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPHIFISWST_EN_VAUDP18_SHIFT 1 |
| #define MT6338_RG_AUDHPHFOP_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON16 |
| #define MT6338_RG_AUDHPHFOP_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPHFOP_EN_VAUDP18_SHIFT 2 |
| #define MT6338_RG_AUDHPMAINCM_COMP_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON16 |
| #define MT6338_RG_AUDHPMAINCM_COMP_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPMAINCM_COMP_EN_VAUDP18_SHIFT 3 |
| #define MT6338_RG_HPL_LNATT2TRIM_MUX_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON17 |
| #define MT6338_RG_HPL_LNATT2TRIM_MUX_VAUDP18_MASK 0x7 |
| #define MT6338_RG_HPL_LNATT2TRIM_MUX_VAUDP18_SHIFT 0 |
| #define MT6338_RG_HPR_LNATT2TRIM_MUX_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON17 |
| #define MT6338_RG_HPR_LNATT2TRIM_MUX_VAUDP18_MASK 0x7 |
| #define MT6338_RG_HPR_LNATT2TRIM_MUX_VAUDP18_SHIFT 4 |
| #define MT6338_RG_HPL_HPDET2LNATT_MUX_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON18 |
| #define MT6338_RG_HPL_HPDET2LNATT_MUX_VAUDP18_MASK 0x7 |
| #define MT6338_RG_HPL_HPDET2LNATT_MUX_VAUDP18_SHIFT 0 |
| #define MT6338_RG_HPR_HPDET2LNATT_MUX_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON18 |
| #define MT6338_RG_HPR_HPDET2LNATT_MUX_VAUDP18_MASK 0x7 |
| #define MT6338_RG_HPR_HPDET2LNATT_MUX_VAUDP18_SHIFT 4 |
| #define MT6338_RG_AUDHP_RSVD0_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON19 |
| #define MT6338_RG_AUDHP_RSVD0_VAUDP18_MASK 0xFF |
| #define MT6338_RG_AUDHP_RSVD0_VAUDP18_SHIFT 0 |
| #define MT6338_RG_AUDHSPWRUP_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON20 |
| #define MT6338_RG_AUDHSPWRUP_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHSPWRUP_VAUDP18_SHIFT 0 |
| #define MT6338_RG_AUDHSPWRUP_IBIAS_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON20 |
| #define MT6338_RG_AUDHSPWRUP_IBIAS_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHSPWRUP_IBIAS_VAUDP18_SHIFT 1 |
| #define MT6338_RG_AUDHSSTARTUP_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON20 |
| #define MT6338_RG_AUDHSSTARTUP_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHSSTARTUP_VAUDP18_SHIFT 2 |
| #define MT6338_RG_AUDHSSCDISABLE_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON20 |
| #define MT6338_RG_AUDHSSCDISABLE_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHSSCDISABLE_VAUDP18_SHIFT 3 |
| #define MT6338_RG_AUDHSBSCCURRENT_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON20 |
| #define MT6338_RG_AUDHSBSCCURRENT_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHSBSCCURRENT_VAUDP18_SHIFT 4 |
| #define MT6338_RG_HSOUT_SHORT2VCM_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON20 |
| #define MT6338_RG_HSOUT_SHORT2VCM_VAUDP18_MASK 0x1 |
| #define MT6338_RG_HSOUT_SHORT2VCM_VAUDP18_SHIFT 5 |
| #define MT6338_RG_AUDHSTRIM_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON20 |
| #define MT6338_RG_AUDHSTRIM_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHSTRIM_EN_VAUDP18_SHIFT 6 |
| #define MT6338_RG_AUDHSTRIM_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON21 |
| #define MT6338_RG_AUDHSTRIM_VAUDP18_MASK 0x1F |
| #define MT6338_RG_AUDHSTRIM_VAUDP18_SHIFT 0 |
| #define MT6338_RG_AUDHSFINETRIM_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON21 |
| #define MT6338_RG_AUDHSFINETRIM_VAUDP18_MASK 0x7 |
| #define MT6338_RG_AUDHSFINETRIM_VAUDP18_SHIFT 5 |
| #define MT6338_RG_AUDHSMUXINPUTSEL_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON22 |
| #define MT6338_RG_AUDHSMUXINPUTSEL_VAUDP18_MASK 0x3 |
| #define MT6338_RG_AUDHSMUXINPUTSEL_VAUDP18_SHIFT 0 |
| #define MT6338_RG_HSINPUTRESET0_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON22 |
| #define MT6338_RG_HSINPUTRESET0_VAUDP18_MASK 0x1 |
| #define MT6338_RG_HSINPUTRESET0_VAUDP18_SHIFT 2 |
| #define MT6338_RG_HSOUTPUTRESET0_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON22 |
| #define MT6338_RG_HSOUTPUTRESET0_VAUDP18_MASK 0x1 |
| #define MT6338_RG_HSOUTPUTRESET0_VAUDP18_SHIFT 3 |
| #define MT6338_RG_HSINPUTSTBENH_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON22 |
| #define MT6338_RG_HSINPUTSTBENH_VAUDP18_MASK 0x1 |
| #define MT6338_RG_HSINPUTSTBENH_VAUDP18_SHIFT 4 |
| #define MT6338_RG_AUDHSCMFB_RNWSEL_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON22 |
| #define MT6338_RG_AUDHSCMFB_RNWSEL_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHSCMFB_RNWSEL_VAUDP18_SHIFT 5 |
| #define MT6338_RG_AUDHSDACTEST_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON22 |
| #define MT6338_RG_AUDHSDACTEST_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHSDACTEST_VAUDP18_SHIFT 6 |
| #define MT6338_RG_AUDHSGM2BOOST_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON22 |
| #define MT6338_RG_AUDHSGM2BOOST_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHSGM2BOOST_EN_VAUDP18_SHIFT 7 |
| #define MT6338_RG_HSOUTPUTSTBENH_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON23 |
| #define MT6338_RG_HSOUTPUTSTBENH_VAUDP18_MASK 0x1 |
| #define MT6338_RG_HSOUTPUTSTBENH_VAUDP18_SHIFT 0 |
| #define MT6338_RG_HSOUTSTGCTRL_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON23 |
| #define MT6338_RG_HSOUTSTGCTRL_VAUDP18_MASK 0x7 |
| #define MT6338_RG_HSOUTSTGCTRL_VAUDP18_SHIFT 1 |
| #define MT6338_RG_AUDLOPWRUP_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON24 |
| #define MT6338_RG_AUDLOPWRUP_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDLOPWRUP_VAUDP18_SHIFT 0 |
| #define MT6338_RG_AUDLOPWRUP_IBIAS_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON24 |
| #define MT6338_RG_AUDLOPWRUP_IBIAS_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDLOPWRUP_IBIAS_VAUDP18_SHIFT 1 |
| #define MT6338_RG_AUDLOSTARTUP_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON24 |
| #define MT6338_RG_AUDLOSTARTUP_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDLOSTARTUP_VAUDP18_SHIFT 2 |
| #define MT6338_RG_AUDLOSCDISABLE_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON24 |
| #define MT6338_RG_AUDLOSCDISABLE_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDLOSCDISABLE_VAUDP18_SHIFT 3 |
| #define MT6338_RG_AUDLOBSCCURRENT_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON24 |
| #define MT6338_RG_AUDLOBSCCURRENT_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDLOBSCCURRENT_VAUDP18_SHIFT 4 |
| #define MT6338_RG_LOOUT_SHORT2VCM_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON24 |
| #define MT6338_RG_LOOUT_SHORT2VCM_VAUDP18_MASK 0x1 |
| #define MT6338_RG_LOOUT_SHORT2VCM_VAUDP18_SHIFT 5 |
| #define MT6338_RG_AUDLOTRIM_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON24 |
| #define MT6338_RG_AUDLOTRIM_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDLOTRIM_EN_VAUDP18_SHIFT 6 |
| #define MT6338_RG_AUDLOTRIM_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON25 |
| #define MT6338_RG_AUDLOTRIM_VAUDP18_MASK 0x1F |
| #define MT6338_RG_AUDLOTRIM_VAUDP18_SHIFT 0 |
| #define MT6338_RG_AUDLOFINETRIM_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON25 |
| #define MT6338_RG_AUDLOFINETRIM_VAUDP18_MASK 0x7 |
| #define MT6338_RG_AUDLOFINETRIM_VAUDP18_SHIFT 5 |
| #define MT6338_RG_AUDLOMUXINPUTSEL_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON26 |
| #define MT6338_RG_AUDLOMUXINPUTSEL_VAUDP18_MASK 0x3 |
| #define MT6338_RG_AUDLOMUXINPUTSEL_VAUDP18_SHIFT 0 |
| #define MT6338_RG_LOINPUTRESET0_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON26 |
| #define MT6338_RG_LOINPUTRESET0_VAUDP18_MASK 0x1 |
| #define MT6338_RG_LOINPUTRESET0_VAUDP18_SHIFT 2 |
| #define MT6338_RG_LOOUTPUTRESET0_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON26 |
| #define MT6338_RG_LOOUTPUTRESET0_VAUDP18_MASK 0x1 |
| #define MT6338_RG_LOOUTPUTRESET0_VAUDP18_SHIFT 3 |
| #define MT6338_RG_LOINPUTSTBENH_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON26 |
| #define MT6338_RG_LOINPUTSTBENH_VAUDP18_MASK 0x1 |
| #define MT6338_RG_LOINPUTSTBENH_VAUDP18_SHIFT 4 |
| #define MT6338_RG_AUDLOCMFB_RNWSEL_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON26 |
| #define MT6338_RG_AUDLOCMFB_RNWSEL_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDLOCMFB_RNWSEL_VAUDP18_SHIFT 5 |
| #define MT6338_RG_AUDLODACTEST_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON26 |
| #define MT6338_RG_AUDLODACTEST_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDLODACTEST_VAUDP18_SHIFT 6 |
| #define MT6338_RG_AUDLOGM2BOOST_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON26 |
| #define MT6338_RG_AUDLOGM2BOOST_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDLOGM2BOOST_EN_VAUDP18_SHIFT 7 |
| #define MT6338_RG_LOOUTPUTSTBENH_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON27 |
| #define MT6338_RG_LOOUTPUTSTBENH_VAUDP18_MASK 0x1 |
| #define MT6338_RG_LOOUTPUTSTBENH_VAUDP18_SHIFT 0 |
| #define MT6338_RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON28 |
| #define MT6338_RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP18_MASK 0xF |
| #define MT6338_RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP18_SHIFT 0 |
| #define MT6338_RG_AUDTRIMBUF_GAINSEL_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON28 |
| #define MT6338_RG_AUDTRIMBUF_GAINSEL_VAUDP18_MASK 0x3 |
| #define MT6338_RG_AUDTRIMBUF_GAINSEL_VAUDP18_SHIFT 4 |
| #define MT6338_RG_AUDTRIMBUF_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON28 |
| #define MT6338_RG_AUDTRIMBUF_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDTRIMBUF_EN_VAUDP18_SHIFT 6 |
| #define MT6338_RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON29 |
| #define MT6338_RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP18_MASK 0x3 |
| #define MT6338_RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP18_SHIFT 0 |
| #define MT6338_RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON29 |
| #define MT6338_RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP18_MASK 0x7 |
| #define MT6338_RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP18_SHIFT 2 |
| #define MT6338_RG_AUDHPSPKDET_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON29 |
| #define MT6338_RG_AUDHPSPKDET_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDHPSPKDET_EN_VAUDP18_SHIFT 5 |
| #define MT6338_RG_AUDBIASADJ_0_HP_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON30 |
| #define MT6338_RG_AUDBIASADJ_0_HP_VAUDP18_MASK 0x7 |
| #define MT6338_RG_AUDBIASADJ_0_HP_VAUDP18_SHIFT 0 |
| #define MT6338_RG_AUDBIASADJ_0_HS_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON30 |
| #define MT6338_RG_AUDBIASADJ_0_HS_VAUDP18_MASK 0x7 |
| #define MT6338_RG_AUDBIASADJ_0_HS_VAUDP18_SHIFT 4 |
| #define MT6338_RG_AUDBIASADJ_0_LO_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON31 |
| #define MT6338_RG_AUDBIASADJ_0_LO_VAUDP18_MASK 0x7 |
| #define MT6338_RG_AUDBIASADJ_0_LO_VAUDP18_SHIFT 0 |
| #define MT6338_RG_AUDIBIASPWRDN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON31 |
| #define MT6338_RG_AUDIBIASPWRDN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDIBIASPWRDN_VAUDP18_SHIFT 4 |
| #define MT6338_RG_AUDBIASADJ_1_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON32 |
| #define MT6338_RG_AUDBIASADJ_1_VAUDP18_MASK 0xFF |
| #define MT6338_RG_AUDBIASADJ_1_VAUDP18_SHIFT 0 |
| #define MT6338_RG_AUDGLB_NVREG_DACSW_VREF_SEL_VA32_ADDR \ |
| MT6338_AUDDEC_PMU_CON33 |
| #define MT6338_RG_AUDGLB_NVREG_DACSW_VREF_SEL_VA32_MASK 0x7 |
| #define MT6338_RG_AUDGLB_NVREG_DACSW_VREF_SEL_VA32_SHIFT 0 |
| #define MT6338_RG_AUDGLB_NVREG_HCBUF_VREF_SEL_VA32_ADDR \ |
| MT6338_AUDDEC_PMU_CON33 |
| #define MT6338_RG_AUDGLB_NVREG_HCBUF_VREF_SEL_VA32_MASK 0x7 |
| #define MT6338_RG_AUDGLB_NVREG_HCBUF_VREF_SEL_VA32_SHIFT 4 |
| #define MT6338_RG_AUDGLB_NVREG_LCBUF_VREF_SEL_VA32_ADDR \ |
| MT6338_AUDDEC_PMU_CON34 |
| #define MT6338_RG_AUDGLB_NVREG_LCBUF_VREF_SEL_VA32_MASK 0x7 |
| #define MT6338_RG_AUDGLB_NVREG_LCBUF_VREF_SEL_VA32_SHIFT 0 |
| #define MT6338_RG_AUDGLB_PWRDN_VA32_ADDR \ |
| MT6338_AUDDEC_PMU_CON34 |
| #define MT6338_RG_AUDGLB_PWRDN_VA32_MASK 0x1 |
| #define MT6338_RG_AUDGLB_PWRDN_VA32_SHIFT 4 |
| #define MT6338_RG_LCLDO_BUF_VREF_EN_VA32_ADDR \ |
| MT6338_AUDDEC_PMU_CON35 |
| #define MT6338_RG_LCLDO_BUF_VREF_EN_VA32_MASK 0x1 |
| #define MT6338_RG_LCLDO_BUF_VREF_EN_VA32_SHIFT 0 |
| #define MT6338_RG_HCLDO_BUF_VREF_EN_VA32_ADDR \ |
| MT6338_AUDDEC_PMU_CON35 |
| #define MT6338_RG_HCLDO_BUF_VREF_EN_VA32_MASK 0x1 |
| #define MT6338_RG_HCLDO_BUF_VREF_EN_VA32_SHIFT 1 |
| #define MT6338_RG_LCLDO_DACSW_VREF_EN_VA32_ADDR \ |
| MT6338_AUDDEC_PMU_CON35 |
| #define MT6338_RG_LCLDO_DACSW_VREF_EN_VA32_MASK 0x1 |
| #define MT6338_RG_LCLDO_DACSW_VREF_EN_VA32_SHIFT 2 |
| #define MT6338_RG_LCLDO_BUF_VREF_SEL_VA32_ADDR \ |
| MT6338_AUDDEC_PMU_CON35 |
| #define MT6338_RG_LCLDO_BUF_VREF_SEL_VA32_MASK 0x7 |
| #define MT6338_RG_LCLDO_BUF_VREF_SEL_VA32_SHIFT 4 |
| #define MT6338_RG_HCLDO_BUF_VREF_SEL_VA32_ADDR \ |
| MT6338_AUDDEC_PMU_CON36 |
| #define MT6338_RG_HCLDO_BUF_VREF_SEL_VA32_MASK 0x7 |
| #define MT6338_RG_HCLDO_BUF_VREF_SEL_VA32_SHIFT 0 |
| #define MT6338_RG_LCLDO_DACSW_VREF_SEL_VA32_ADDR \ |
| MT6338_AUDDEC_PMU_CON36 |
| #define MT6338_RG_LCLDO_DACSW_VREF_SEL_VA32_MASK 0x7 |
| #define MT6338_RG_LCLDO_DACSW_VREF_SEL_VA32_SHIFT 4 |
| #define MT6338_RG_LCLDO_BUF_L_EN_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON37 |
| #define MT6338_RG_LCLDO_BUF_L_EN_VA18_MASK 0x1 |
| #define MT6338_RG_LCLDO_BUF_L_EN_VA18_SHIFT 0 |
| #define MT6338_RG_LCLDO_BUF_R_EN_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON37 |
| #define MT6338_RG_LCLDO_BUF_R_EN_VA18_MASK 0x1 |
| #define MT6338_RG_LCLDO_BUF_R_EN_VA18_SHIFT 1 |
| #define MT6338_RG_HCLDO_BUF_L_EN_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON37 |
| #define MT6338_RG_HCLDO_BUF_L_EN_VA18_MASK 0x1 |
| #define MT6338_RG_HCLDO_BUF_L_EN_VA18_SHIFT 2 |
| #define MT6338_RG_HCLDO_BUF_R_EN_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON37 |
| #define MT6338_RG_HCLDO_BUF_R_EN_VA18_MASK 0x1 |
| #define MT6338_RG_HCLDO_BUF_R_EN_VA18_SHIFT 3 |
| #define MT6338_RG_LCLDO_DACSW_L_EN_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON37 |
| #define MT6338_RG_LCLDO_DACSW_L_EN_VA18_MASK 0x1 |
| #define MT6338_RG_LCLDO_DACSW_L_EN_VA18_SHIFT 4 |
| #define MT6338_RG_LCLDO_DACSW_R_EN_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON37 |
| #define MT6338_RG_LCLDO_DACSW_R_EN_VA18_MASK 0x1 |
| #define MT6338_RG_LCLDO_DACSW_R_EN_VA18_SHIFT 5 |
| #define MT6338_RG_LCLDO_BUF_L_PDDIS_EN_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON37 |
| #define MT6338_RG_LCLDO_BUF_L_PDDIS_EN_VA18_MASK 0x1 |
| #define MT6338_RG_LCLDO_BUF_L_PDDIS_EN_VA18_SHIFT 6 |
| #define MT6338_RG_LCLDO_BUF_R_PDDIS_EN_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON37 |
| #define MT6338_RG_LCLDO_BUF_R_PDDIS_EN_VA18_MASK 0x1 |
| #define MT6338_RG_LCLDO_BUF_R_PDDIS_EN_VA18_SHIFT 7 |
| #define MT6338_RG_HCLDO_BUF_L_PDDIS_EN_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON38 |
| #define MT6338_RG_HCLDO_BUF_L_PDDIS_EN_VA18_MASK 0x1 |
| #define MT6338_RG_HCLDO_BUF_L_PDDIS_EN_VA18_SHIFT 0 |
| #define MT6338_RG_HCLDO_BUF_R_PDDIS_EN_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON38 |
| #define MT6338_RG_HCLDO_BUF_R_PDDIS_EN_VA18_MASK 0x1 |
| #define MT6338_RG_HCLDO_BUF_R_PDDIS_EN_VA18_SHIFT 1 |
| #define MT6338_RG_LCLDO_DACSW_L_PDDIS_EN_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON38 |
| #define MT6338_RG_LCLDO_DACSW_L_PDDIS_EN_VA18_MASK 0x1 |
| #define MT6338_RG_LCLDO_DACSW_L_PDDIS_EN_VA18_SHIFT 2 |
| #define MT6338_RG_LCLDO_DACSW_R_PDDIS_EN_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON38 |
| #define MT6338_RG_LCLDO_DACSW_R_PDDIS_EN_VA18_MASK 0x1 |
| #define MT6338_RG_LCLDO_DACSW_R_PDDIS_EN_VA18_SHIFT 3 |
| #define MT6338_RG_LCLDO_BUF_L_REMOTE_SENSE_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON39 |
| #define MT6338_RG_LCLDO_BUF_L_REMOTE_SENSE_VA18_MASK 0x1 |
| #define MT6338_RG_LCLDO_BUF_L_REMOTE_SENSE_VA18_SHIFT 0 |
| #define MT6338_RG_LCLDO_BUF_R_REMOTE_SENSE_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON39 |
| #define MT6338_RG_LCLDO_BUF_R_REMOTE_SENSE_VA18_MASK 0x1 |
| #define MT6338_RG_LCLDO_BUF_R_REMOTE_SENSE_VA18_SHIFT 1 |
| #define MT6338_RG_HCLDO_BUF_L_REMOTE_SENSE_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON39 |
| #define MT6338_RG_HCLDO_BUF_L_REMOTE_SENSE_VA18_MASK 0x1 |
| #define MT6338_RG_HCLDO_BUF_L_REMOTE_SENSE_VA18_SHIFT 2 |
| #define MT6338_RG_HCLDO_BUF_R_REMOTE_SENSE_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON39 |
| #define MT6338_RG_HCLDO_BUF_R_REMOTE_SENSE_VA18_MASK 0x1 |
| #define MT6338_RG_HCLDO_BUF_R_REMOTE_SENSE_VA18_SHIFT 3 |
| #define MT6338_RG_LCLDO_DACSW_L_REMOTE_SENSE_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON39 |
| #define MT6338_RG_LCLDO_DACSW_L_REMOTE_SENSE_VA18_MASK 0x1 |
| #define MT6338_RG_LCLDO_DACSW_L_REMOTE_SENSE_VA18_SHIFT 4 |
| #define MT6338_RG_LCLDO_DACSW_R_REMOTE_SENSE_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON39 |
| #define MT6338_RG_LCLDO_DACSW_R_REMOTE_SENSE_VA18_MASK 0x1 |
| #define MT6338_RG_LCLDO_DACSW_R_REMOTE_SENSE_VA18_SHIFT 5 |
| #define MT6338_RG_LCLDO_BUF_L_SC_EN_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON39 |
| #define MT6338_RG_LCLDO_BUF_L_SC_EN_VA18_MASK 0x1 |
| #define MT6338_RG_LCLDO_BUF_L_SC_EN_VA18_SHIFT 6 |
| #define MT6338_RG_LCLDO_BUF_R_SC_EN_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON39 |
| #define MT6338_RG_LCLDO_BUF_R_SC_EN_VA18_MASK 0x1 |
| #define MT6338_RG_LCLDO_BUF_R_SC_EN_VA18_SHIFT 7 |
| #define MT6338_RG_HCLDO_BUF_L_SC_EN_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON40 |
| #define MT6338_RG_HCLDO_BUF_L_SC_EN_VA18_MASK 0x1 |
| #define MT6338_RG_HCLDO_BUF_L_SC_EN_VA18_SHIFT 0 |
| #define MT6338_RG_HCLDO_BUF_R_SC_EN_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON40 |
| #define MT6338_RG_HCLDO_BUF_R_SC_EN_VA18_MASK 0x1 |
| #define MT6338_RG_HCLDO_BUF_R_SC_EN_VA18_SHIFT 1 |
| #define MT6338_RG_LCLDO_DACSW_L_SC_EN_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON40 |
| #define MT6338_RG_LCLDO_DACSW_L_SC_EN_VA18_MASK 0x1 |
| #define MT6338_RG_LCLDO_DACSW_L_SC_EN_VA18_SHIFT 2 |
| #define MT6338_RG_LCLDO_DACSW_R_SC_EN_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON40 |
| #define MT6338_RG_LCLDO_DACSW_R_SC_EN_VA18_MASK 0x1 |
| #define MT6338_RG_LCLDO_DACSW_R_SC_EN_VA18_SHIFT 3 |
| #define MT6338_RG_NVREG_LC_BUF_L_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON41 |
| #define MT6338_RG_NVREG_LC_BUF_L_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_NVREG_LC_BUF_L_EN_VAUDP18_SHIFT 0 |
| #define MT6338_RG_NVREG_LC_BUF_R_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON41 |
| #define MT6338_RG_NVREG_LC_BUF_R_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_NVREG_LC_BUF_R_EN_VAUDP18_SHIFT 1 |
| #define MT6338_RG_NVREG_HC_BUF_L_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON41 |
| #define MT6338_RG_NVREG_HC_BUF_L_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_NVREG_HC_BUF_L_EN_VAUDP18_SHIFT 2 |
| #define MT6338_RG_NVREG_HC_BUF_R_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON41 |
| #define MT6338_RG_NVREG_HC_BUF_R_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_NVREG_HC_BUF_R_EN_VAUDP18_SHIFT 3 |
| #define MT6338_RG_NVREG_DACSW_L_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON41 |
| #define MT6338_RG_NVREG_DACSW_L_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_NVREG_DACSW_L_EN_VAUDP18_SHIFT 4 |
| #define MT6338_RG_NVREG_DACSW_R_EN_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON41 |
| #define MT6338_RG_NVREG_DACSW_R_EN_VAUDP18_MASK 0x1 |
| #define MT6338_RG_NVREG_DACSW_R_EN_VAUDP18_SHIFT 5 |
| #define MT6338_RG_NVREG_LC_BUF_L_PULL0V_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON41 |
| #define MT6338_RG_NVREG_LC_BUF_L_PULL0V_VAUDP18_MASK 0x1 |
| #define MT6338_RG_NVREG_LC_BUF_L_PULL0V_VAUDP18_SHIFT 6 |
| #define MT6338_RG_NVREG_LC_BUF_R_PULL0V_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON41 |
| #define MT6338_RG_NVREG_LC_BUF_R_PULL0V_VAUDP18_MASK 0x1 |
| #define MT6338_RG_NVREG_LC_BUF_R_PULL0V_VAUDP18_SHIFT 7 |
| #define MT6338_RG_NVREG_HC_BUF_L_PULL0V_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON42 |
| #define MT6338_RG_NVREG_HC_BUF_L_PULL0V_VAUDP18_MASK 0x1 |
| #define MT6338_RG_NVREG_HC_BUF_L_PULL0V_VAUDP18_SHIFT 0 |
| #define MT6338_RG_NVREG_HC_BUF_R_PULL0V_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON42 |
| #define MT6338_RG_NVREG_HC_BUF_R_PULL0V_VAUDP18_MASK 0x1 |
| #define MT6338_RG_NVREG_HC_BUF_R_PULL0V_VAUDP18_SHIFT 1 |
| #define MT6338_RG_NVREG_DACSW_L_PULL0V_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON42 |
| #define MT6338_RG_NVREG_DACSW_L_PULL0V_VAUDP18_MASK 0x1 |
| #define MT6338_RG_NVREG_DACSW_L_PULL0V_VAUDP18_SHIFT 2 |
| #define MT6338_RG_NVREG_DACSW_R_PULL0V_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON42 |
| #define MT6338_RG_NVREG_DACSW_R_PULL0V_VAUDP18_MASK 0x1 |
| #define MT6338_RG_NVREG_DACSW_R_PULL0V_VAUDP18_SHIFT 3 |
| #define MT6338_RG_AUDPMU_RSVD0_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON43 |
| #define MT6338_RG_AUDPMU_RSVD0_VA18_MASK 0xFF |
| #define MT6338_RG_AUDPMU_RSVD0_VA18_SHIFT 0 |
| #define MT6338_RG_AUDNCP_PWRSW_OFFCTRL_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON44 |
| #define MT6338_RG_AUDNCP_PWRSW_OFFCTRL_VA18_MASK 0xF |
| #define MT6338_RG_AUDNCP_PWRSW_OFFCTRL_VA18_SHIFT 0 |
| #define MT6338_RG_AUDNCP_LB_ENB_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON44 |
| #define MT6338_RG_AUDNCP_LB_ENB_VA18_MASK 0x1 |
| #define MT6338_RG_AUDNCP_LB_ENB_VA18_SHIFT 4 |
| #define MT6338_RG_AUDZCDMUXSEL_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON45 |
| #define MT6338_RG_AUDZCDMUXSEL_VAUDP18_MASK 0x7 |
| #define MT6338_RG_AUDZCDMUXSEL_VAUDP18_SHIFT 0 |
| #define MT6338_RG_AUDZCDCLKSEL_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON45 |
| #define MT6338_RG_AUDZCDCLKSEL_VAUDP18_MASK 0x1 |
| #define MT6338_RG_AUDZCDCLKSEL_VAUDP18_SHIFT 4 |
| #define MT6338_RG_ABIDEC_RSVD0_VA18_ADDR \ |
| MT6338_AUDDEC_PMU_CON46 |
| #define MT6338_RG_ABIDEC_RSVD0_VA18_MASK 0xFF |
| #define MT6338_RG_ABIDEC_RSVD0_VA18_SHIFT 0 |
| #define MT6338_RG_ABIDEC_RSVD0_VA32_ADDR \ |
| MT6338_AUDDEC_PMU_CON47 |
| #define MT6338_RG_ABIDEC_RSVD0_VA32_MASK 0xFF |
| #define MT6338_RG_ABIDEC_RSVD0_VA32_SHIFT 0 |
| #define MT6338_RG_ABIDEC_RSVD0_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON48 |
| #define MT6338_RG_ABIDEC_RSVD0_VAUDP18_MASK 0xFF |
| #define MT6338_RG_ABIDEC_RSVD0_VAUDP18_SHIFT 0 |
| #define MT6338_RG_ABIDEC_RSVD1_VAUDP18_ADDR \ |
| MT6338_AUDDEC_PMU_CON49 |
| #define MT6338_RG_ABIDEC_RSVD1_VAUDP18_MASK 0xFF |
| #define MT6338_RG_ABIDEC_RSVD1_VAUDP18_SHIFT 0 |
| #define MT6338_AUDZCD_ANA_ID_ADDR \ |
| MT6338_AUDZCD_DSN_ID |
| #define MT6338_AUDZCD_ANA_ID_MASK 0xFF |
| #define MT6338_AUDZCD_ANA_ID_SHIFT 0 |
| #define MT6338_AUDZCD_DIG_ID_ADDR \ |
| MT6338_AUDZCD_DSN_ID_H |
| #define MT6338_AUDZCD_DIG_ID_MASK 0xFF |
| #define MT6338_AUDZCD_DIG_ID_SHIFT 0 |
| #define MT6338_AUDZCD_ANA_MINOR_REV_ADDR \ |
| MT6338_AUDZCD_DSN_REV0 |
| #define MT6338_AUDZCD_ANA_MINOR_REV_MASK 0xF |
| #define MT6338_AUDZCD_ANA_MINOR_REV_SHIFT 0 |
| #define MT6338_AUDZCD_ANA_MAJOR_REV_ADDR \ |
| MT6338_AUDZCD_DSN_REV0 |
| #define MT6338_AUDZCD_ANA_MAJOR_REV_MASK 0xF |
| #define MT6338_AUDZCD_ANA_MAJOR_REV_SHIFT 4 |
| #define MT6338_AUDZCD_DIG_MINOR_REV_ADDR \ |
| MT6338_AUDZCD_DSN_REV0_H |
| #define MT6338_AUDZCD_DIG_MINOR_REV_MASK 0xF |
| #define MT6338_AUDZCD_DIG_MINOR_REV_SHIFT 0 |
| #define MT6338_AUDZCD_DIG_MAJOR_REV_ADDR \ |
| MT6338_AUDZCD_DSN_REV0_H |
| #define MT6338_AUDZCD_DIG_MAJOR_REV_MASK 0xF |
| #define MT6338_AUDZCD_DIG_MAJOR_REV_SHIFT 4 |
| #define MT6338_AUDZCD_DSN_CBS_ADDR \ |
| MT6338_AUDZCD_DSN_DBI |
| #define MT6338_AUDZCD_DSN_CBS_MASK 0x3 |
| #define MT6338_AUDZCD_DSN_CBS_SHIFT 0 |
| #define MT6338_AUDZCD_DSN_BIX_ADDR \ |
| MT6338_AUDZCD_DSN_DBI |
| #define MT6338_AUDZCD_DSN_BIX_MASK 0x3 |
| #define MT6338_AUDZCD_DSN_BIX_SHIFT 2 |
| #define MT6338_AUDZCD_DSN_ESP_ADDR \ |
| MT6338_AUDZCD_DSN_DBI_H |
| #define MT6338_AUDZCD_DSN_ESP_MASK 0xFF |
| #define MT6338_AUDZCD_DSN_ESP_SHIFT 0 |
| #define MT6338_AUDZCD_DSN_FPI_ADDR \ |
| MT6338_AUDZCD_DSN_FPI |
| #define MT6338_AUDZCD_DSN_FPI_MASK 0xFF |
| #define MT6338_AUDZCD_DSN_FPI_SHIFT 0 |
| #define MT6338_RG_AUDZCDENABLE_ADDR \ |
| MT6338_ZCD_CON0 |
| #define MT6338_RG_AUDZCDENABLE_MASK 0x1 |
| #define MT6338_RG_AUDZCDENABLE_SHIFT 0 |
| #define MT6338_RG_AUDZCDGAINSTEPTIME_ADDR \ |
| MT6338_ZCD_CON0 |
| #define MT6338_RG_AUDZCDGAINSTEPTIME_MASK 0x7 |
| #define MT6338_RG_AUDZCDGAINSTEPTIME_SHIFT 1 |
| #define MT6338_RG_AUDZCDGAINSTEPSIZE_ADDR \ |
| MT6338_ZCD_CON0 |
| #define MT6338_RG_AUDZCDGAINSTEPSIZE_MASK 0x3 |
| #define MT6338_RG_AUDZCDGAINSTEPSIZE_SHIFT 4 |
| #define MT6338_RG_AUDZCDTIMEOUTMODESEL_ADDR \ |
| MT6338_ZCD_CON0 |
| #define MT6338_RG_AUDZCDTIMEOUTMODESEL_MASK 0x1 |
| #define MT6338_RG_AUDZCDTIMEOUTMODESEL_SHIFT 6 |
| #define MT6338_RG_AUDLOLGAIN_ADDR \ |
| MT6338_ZCD_CON1 |
| #define MT6338_RG_AUDLOLGAIN_MASK 0x1F |
| #define MT6338_RG_AUDLOLGAIN_SHIFT 0 |
| #define MT6338_RG_AUDLORGAIN_ADDR \ |
| MT6338_ZCD_CON1_H |
| #define MT6338_RG_AUDLORGAIN_MASK 0x1F |
| #define MT6338_RG_AUDLORGAIN_SHIFT 0 |
| #define MT6338_RG_AUDHPLGAIN_ADDR \ |
| MT6338_ZCD_CON2 |
| #define MT6338_RG_AUDHPLGAIN_MASK 0x1F |
| #define MT6338_RG_AUDHPLGAIN_SHIFT 0 |
| #define MT6338_RG_AUDHPRGAIN_ADDR \ |
| MT6338_ZCD_CON2_H |
| #define MT6338_RG_AUDHPRGAIN_MASK 0x1F |
| #define MT6338_RG_AUDHPRGAIN_SHIFT 0 |
| #define MT6338_RG_AUDHSGAIN_ADDR \ |
| MT6338_ZCD_CON3 |
| #define MT6338_RG_AUDHSGAIN_MASK 0x1F |
| #define MT6338_RG_AUDHSGAIN_SHIFT 0 |
| #define MT6338_RG_AUDIVLGAIN_ADDR \ |
| MT6338_ZCD_CON4 |
| #define MT6338_RG_AUDIVLGAIN_MASK 0x7 |
| #define MT6338_RG_AUDIVLGAIN_SHIFT 0 |
| #define MT6338_RG_AUDIVRGAIN_ADDR \ |
| MT6338_ZCD_CON4_H |
| #define MT6338_RG_AUDIVRGAIN_MASK 0x7 |
| #define MT6338_RG_AUDIVRGAIN_SHIFT 0 |
| #define MT6338_RG_AUDINTGAIN1_ADDR \ |
| MT6338_ZCD_CON5 |
| #define MT6338_RG_AUDINTGAIN1_MASK 0x1F |
| #define MT6338_RG_AUDINTGAIN1_SHIFT 0 |
| #define MT6338_RG_AUDINTGAIN2_ADDR \ |
| MT6338_ZCD_CON5_H |
| #define MT6338_RG_AUDINTGAIN2_MASK 0x1F |
| #define MT6338_RG_AUDINTGAIN2_SHIFT 0 |
| #define MT6338_ACCDET_ANA_ID_ADDR \ |
| MT6338_ACCDET_DSN_DIG_ID |
| #define MT6338_ACCDET_ANA_ID_MASK 0xFF |
| #define MT6338_ACCDET_ANA_ID_SHIFT 0 |
| #define MT6338_ACCDET_DIG_ID_ADDR \ |
| MT6338_ACCDET_DSN_DIG_ID_H |
| #define MT6338_ACCDET_DIG_ID_MASK 0xFF |
| #define MT6338_ACCDET_DIG_ID_SHIFT 0 |
| #define MT6338_ACCDET_ANA_MINOR_REV_ADDR \ |
| MT6338_ACCDET_DSN_DIG_REV0 |
| #define MT6338_ACCDET_ANA_MINOR_REV_MASK 0xF |
| #define MT6338_ACCDET_ANA_MINOR_REV_SHIFT 0 |
| #define MT6338_ACCDET_ANA_MAJOR_REV_ADDR \ |
| MT6338_ACCDET_DSN_DIG_REV0 |
| #define MT6338_ACCDET_ANA_MAJOR_REV_MASK 0xF |
| #define MT6338_ACCDET_ANA_MAJOR_REV_SHIFT 4 |
| #define MT6338_ACCDET_DIG_MINOR_REV_ADDR \ |
| MT6338_ACCDET_DSN_DIG_REV0_H |
| #define MT6338_ACCDET_DIG_MINOR_REV_MASK 0xF |
| #define MT6338_ACCDET_DIG_MINOR_REV_SHIFT 0 |
| #define MT6338_ACCDET_DIG_MAJOR_REV_ADDR \ |
| MT6338_ACCDET_DSN_DIG_REV0_H |
| #define MT6338_ACCDET_DIG_MAJOR_REV_MASK 0xF |
| #define MT6338_ACCDET_DIG_MAJOR_REV_SHIFT 4 |
| #define MT6338_ACCDET_DSN_CBS_ADDR \ |
| MT6338_ACCDET_DSN_DBI |
| #define MT6338_ACCDET_DSN_CBS_MASK 0x3 |
| #define MT6338_ACCDET_DSN_CBS_SHIFT 0 |
| #define MT6338_ACCDET_DSN_BIX_ADDR \ |
| MT6338_ACCDET_DSN_DBI |
| #define MT6338_ACCDET_DSN_BIX_MASK 0x3 |
| #define MT6338_ACCDET_DSN_BIX_SHIFT 2 |
| #define MT6338_ACCDET_ESP_ADDR \ |
| MT6338_ACCDET_DSN_DBI_H |
| #define MT6338_ACCDET_ESP_MASK 0xFF |
| #define MT6338_ACCDET_ESP_SHIFT 0 |
| #define MT6338_ACCDET_DSN_FPI_ADDR \ |
| MT6338_ACCDET_DSN_FPI |
| #define MT6338_ACCDET_DSN_FPI_MASK 0xFF |
| #define MT6338_ACCDET_DSN_FPI_SHIFT 0 |
| #define MT6338_ACCDET_AUXADC_SEL_ADDR \ |
| MT6338_ACCDET_CON0_L |
| #define MT6338_ACCDET_AUXADC_SEL_MASK 0x1 |
| #define MT6338_ACCDET_AUXADC_SEL_SHIFT 0 |
| #define MT6338_ACCDET_AUXADC_SW_ADDR \ |
| MT6338_ACCDET_CON0_L |
| #define MT6338_ACCDET_AUXADC_SW_MASK 0x1 |
| #define MT6338_ACCDET_AUXADC_SW_SHIFT 1 |
| #define MT6338_ACCDET_TEST_AUXADC_ADDR \ |
| MT6338_ACCDET_CON0_L |
| #define MT6338_ACCDET_TEST_AUXADC_MASK 0x1 |
| #define MT6338_ACCDET_TEST_AUXADC_SHIFT 2 |
| #define MT6338_ACCDET_AUXADC_ANASWCTRL_SEL_ADDR \ |
| MT6338_ACCDET_CON0_H |
| #define MT6338_ACCDET_AUXADC_ANASWCTRL_SEL_MASK 0x1 |
| #define MT6338_ACCDET_AUXADC_ANASWCTRL_SEL_SHIFT 0 |
| #define MT6338_AUDACCDETAUXADCSWCTRL_SEL_ADDR \ |
| MT6338_ACCDET_CON0_H |
| #define MT6338_AUDACCDETAUXADCSWCTRL_SEL_MASK 0x1 |
| #define MT6338_AUDACCDETAUXADCSWCTRL_SEL_SHIFT 1 |
| #define MT6338_AUDACCDETAUXADCSWCTRL_SW_ADDR \ |
| MT6338_ACCDET_CON0_H |
| #define MT6338_AUDACCDETAUXADCSWCTRL_SW_MASK 0x1 |
| #define MT6338_AUDACCDETAUXADCSWCTRL_SW_SHIFT 2 |
| #define MT6338_ACCDET_TEST_ANA_ADDR \ |
| MT6338_ACCDET_CON0_H |
| #define MT6338_ACCDET_TEST_ANA_MASK 0x1 |
| #define MT6338_ACCDET_TEST_ANA_SHIFT 3 |
| #define MT6338_RG_AUDACCDETRSV_ADDR \ |
| MT6338_ACCDET_CON0_H |
| #define MT6338_RG_AUDACCDETRSV_MASK 0x3 |
| #define MT6338_RG_AUDACCDETRSV_SHIFT 4 |
| #define MT6338_ACCDET_SW_EN_ADDR \ |
| MT6338_ACCDET_CON1_L |
| #define MT6338_ACCDET_SW_EN_MASK 0x1 |
| #define MT6338_ACCDET_SW_EN_SHIFT 0 |
| #define MT6338_ACCDET_SEQ_INIT_ADDR \ |
| MT6338_ACCDET_CON1_L |
| #define MT6338_ACCDET_SEQ_INIT_MASK 0x1 |
| #define MT6338_ACCDET_SEQ_INIT_SHIFT 1 |
| #define MT6338_ACCDET_EINT0_SW_EN_ADDR \ |
| MT6338_ACCDET_CON1_L |
| #define MT6338_ACCDET_EINT0_SW_EN_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_SW_EN_SHIFT 2 |
| #define MT6338_ACCDET_EINT0_SEQ_INIT_ADDR \ |
| MT6338_ACCDET_CON1_L |
| #define MT6338_ACCDET_EINT0_SEQ_INIT_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_SEQ_INIT_SHIFT 3 |
| #define MT6338_ACCDET_EINT1_SW_EN_ADDR \ |
| MT6338_ACCDET_CON1_L |
| #define MT6338_ACCDET_EINT1_SW_EN_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_SW_EN_SHIFT 4 |
| #define MT6338_ACCDET_EINT1_SEQ_INIT_ADDR \ |
| MT6338_ACCDET_CON1_L |
| #define MT6338_ACCDET_EINT1_SEQ_INIT_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_SEQ_INIT_SHIFT 5 |
| #define MT6338_ACCDET_EINT0_INVERTER_SW_EN_ADDR \ |
| MT6338_ACCDET_CON1_L |
| #define MT6338_ACCDET_EINT0_INVERTER_SW_EN_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_INVERTER_SW_EN_SHIFT 6 |
| #define MT6338_ACCDET_EINT0_INVERTER_SEQ_INIT_ADDR \ |
| MT6338_ACCDET_CON1_L |
| #define MT6338_ACCDET_EINT0_INVERTER_SEQ_INIT_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_INVERTER_SEQ_INIT_SHIFT 7 |
| #define MT6338_ACCDET_EINT1_INVERTER_SW_EN_ADDR \ |
| MT6338_ACCDET_CON1_H |
| #define MT6338_ACCDET_EINT1_INVERTER_SW_EN_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_INVERTER_SW_EN_SHIFT 0 |
| #define MT6338_ACCDET_EINT1_INVERTER_SEQ_INIT_ADDR \ |
| MT6338_ACCDET_CON1_H |
| #define MT6338_ACCDET_EINT1_INVERTER_SEQ_INIT_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_INVERTER_SEQ_INIT_SHIFT 1 |
| #define MT6338_ACCDET_EINT0_M_SW_EN_ADDR \ |
| MT6338_ACCDET_CON1_H |
| #define MT6338_ACCDET_EINT0_M_SW_EN_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_M_SW_EN_SHIFT 2 |
| #define MT6338_ACCDET_EINT1_M_SW_EN_ADDR \ |
| MT6338_ACCDET_CON1_H |
| #define MT6338_ACCDET_EINT1_M_SW_EN_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_M_SW_EN_SHIFT 3 |
| #define MT6338_ACCDET_EINT_M_DETECT_EN_ADDR \ |
| MT6338_ACCDET_CON1_H |
| #define MT6338_ACCDET_EINT_M_DETECT_EN_MASK 0x1 |
| #define MT6338_ACCDET_EINT_M_DETECT_EN_SHIFT 4 |
| #define MT6338_ACCDET_CMP_PWM_EN_ADDR \ |
| MT6338_ACCDET_CON2_L |
| #define MT6338_ACCDET_CMP_PWM_EN_MASK 0x1 |
| #define MT6338_ACCDET_CMP_PWM_EN_SHIFT 0 |
| #define MT6338_ACCDET_VTH_PWM_EN_ADDR \ |
| MT6338_ACCDET_CON2_L |
| #define MT6338_ACCDET_VTH_PWM_EN_MASK 0x1 |
| #define MT6338_ACCDET_VTH_PWM_EN_SHIFT 1 |
| #define MT6338_ACCDET_MBIAS_PWM_EN_ADDR \ |
| MT6338_ACCDET_CON2_L |
| #define MT6338_ACCDET_MBIAS_PWM_EN_MASK 0x1 |
| #define MT6338_ACCDET_MBIAS_PWM_EN_SHIFT 2 |
| #define MT6338_ACCDET_EINT_EN_PWM_EN_ADDR \ |
| MT6338_ACCDET_CON2_L |
| #define MT6338_ACCDET_EINT_EN_PWM_EN_MASK 0x1 |
| #define MT6338_ACCDET_EINT_EN_PWM_EN_SHIFT 3 |
| #define MT6338_ACCDET_EINT_CMPEN_PWM_EN_ADDR \ |
| MT6338_ACCDET_CON2_L |
| #define MT6338_ACCDET_EINT_CMPEN_PWM_EN_MASK 0x1 |
| #define MT6338_ACCDET_EINT_CMPEN_PWM_EN_SHIFT 4 |
| #define MT6338_ACCDET_EINT_CMPMEN_PWM_EN_ADDR \ |
| MT6338_ACCDET_CON2_L |
| #define MT6338_ACCDET_EINT_CMPMEN_PWM_EN_MASK 0x1 |
| #define MT6338_ACCDET_EINT_CMPMEN_PWM_EN_SHIFT 5 |
| #define MT6338_ACCDET_EINT_CTURBO_PWM_EN_ADDR \ |
| MT6338_ACCDET_CON2_L |
| #define MT6338_ACCDET_EINT_CTURBO_PWM_EN_MASK 0x1 |
| #define MT6338_ACCDET_EINT_CTURBO_PWM_EN_SHIFT 6 |
| #define MT6338_ACCDET_CMP_PWM_IDLE_ADDR \ |
| MT6338_ACCDET_CON2_H |
| #define MT6338_ACCDET_CMP_PWM_IDLE_MASK 0x1 |
| #define MT6338_ACCDET_CMP_PWM_IDLE_SHIFT 0 |
| #define MT6338_ACCDET_VTH_PWM_IDLE_ADDR \ |
| MT6338_ACCDET_CON2_H |
| #define MT6338_ACCDET_VTH_PWM_IDLE_MASK 0x1 |
| #define MT6338_ACCDET_VTH_PWM_IDLE_SHIFT 1 |
| #define MT6338_ACCDET_MBIAS_PWM_IDLE_ADDR \ |
| MT6338_ACCDET_CON2_H |
| #define MT6338_ACCDET_MBIAS_PWM_IDLE_MASK 0x1 |
| #define MT6338_ACCDET_MBIAS_PWM_IDLE_SHIFT 2 |
| #define MT6338_ACCDET_EINT0_CMPEN_PWM_IDLE_ADDR \ |
| MT6338_ACCDET_CON2_H |
| #define MT6338_ACCDET_EINT0_CMPEN_PWM_IDLE_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_CMPEN_PWM_IDLE_SHIFT 3 |
| #define MT6338_ACCDET_EINT1_CMPEN_PWM_IDLE_ADDR \ |
| MT6338_ACCDET_CON2_H |
| #define MT6338_ACCDET_EINT1_CMPEN_PWM_IDLE_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_CMPEN_PWM_IDLE_SHIFT 4 |
| #define MT6338_ACCDET_PWM_EN_SW_ADDR \ |
| MT6338_ACCDET_CON2_H |
| #define MT6338_ACCDET_PWM_EN_SW_MASK 0x1 |
| #define MT6338_ACCDET_PWM_EN_SW_SHIFT 5 |
| #define MT6338_ACCDET_PWM_EN_SEL_ADDR \ |
| MT6338_ACCDET_CON2_H |
| #define MT6338_ACCDET_PWM_EN_SEL_MASK 0x3 |
| #define MT6338_ACCDET_PWM_EN_SEL_SHIFT 6 |
| #define MT6338_ACCDET_PWM_WIDTH_L_ADDR \ |
| MT6338_ACCDET_CON3_L |
| #define MT6338_ACCDET_PWM_WIDTH_L_MASK 0xFF |
| #define MT6338_ACCDET_PWM_WIDTH_L_SHIFT 0 |
| #define MT6338_ACCDET_PWM_WIDTH_H_ADDR \ |
| MT6338_ACCDET_CON3_H |
| #define MT6338_ACCDET_PWM_WIDTH_H_MASK 0xFF |
| #define MT6338_ACCDET_PWM_WIDTH_H_SHIFT 0 |
| #define MT6338_ACCDET_PWM_THRESH_L_ADDR \ |
| MT6338_ACCDET_CON4_L |
| #define MT6338_ACCDET_PWM_THRESH_L_MASK 0xFF |
| #define MT6338_ACCDET_PWM_THRESH_L_SHIFT 0 |
| #define MT6338_ACCDET_PWM_THRESH_H_ADDR \ |
| MT6338_ACCDET_CON4_H |
| #define MT6338_ACCDET_PWM_THRESH_H_MASK 0xFF |
| #define MT6338_ACCDET_PWM_THRESH_H_SHIFT 0 |
| #define MT6338_ACCDET_RISE_DELAY_L_ADDR \ |
| MT6338_ACCDET_CON5_L |
| #define MT6338_ACCDET_RISE_DELAY_L_MASK 0xFF |
| #define MT6338_ACCDET_RISE_DELAY_L_SHIFT 0 |
| #define MT6338_ACCDET_RISE_DELAY_H_ADDR \ |
| MT6338_ACCDET_CON5_H |
| #define MT6338_ACCDET_RISE_DELAY_H_MASK 0x7F |
| #define MT6338_ACCDET_RISE_DELAY_H_SHIFT 0 |
| #define MT6338_ACCDET_FALL_DELAY_ADDR \ |
| MT6338_ACCDET_CON5_H |
| #define MT6338_ACCDET_FALL_DELAY_MASK 0x1 |
| #define MT6338_ACCDET_FALL_DELAY_SHIFT 7 |
| #define MT6338_ACCDET_EINT_CMPMEN_PWM_THRESH_ADDR \ |
| MT6338_ACCDET_CON6 |
| #define MT6338_ACCDET_EINT_CMPMEN_PWM_THRESH_MASK 0x7 |
| #define MT6338_ACCDET_EINT_CMPMEN_PWM_THRESH_SHIFT 0 |
| #define MT6338_ACCDET_EINT_CMPMEN_PWM_WIDTH_ADDR \ |
| MT6338_ACCDET_CON6 |
| #define MT6338_ACCDET_EINT_CMPMEN_PWM_WIDTH_MASK 0x7 |
| #define MT6338_ACCDET_EINT_CMPMEN_PWM_WIDTH_SHIFT 4 |
| #define MT6338_ACCDET_EINT_EN_PWM_THRESH_ADDR \ |
| MT6338_ACCDET_CON7_L |
| #define MT6338_ACCDET_EINT_EN_PWM_THRESH_MASK 0x7 |
| #define MT6338_ACCDET_EINT_EN_PWM_THRESH_SHIFT 0 |
| #define MT6338_ACCDET_EINT_EN_PWM_WIDTH_ADDR \ |
| MT6338_ACCDET_CON7_L |
| #define MT6338_ACCDET_EINT_EN_PWM_WIDTH_MASK 0x3 |
| #define MT6338_ACCDET_EINT_EN_PWM_WIDTH_SHIFT 4 |
| #define MT6338_ACCDET_EINT_CMPEN_PWM_THRESH_ADDR \ |
| MT6338_ACCDET_CON7_H |
| #define MT6338_ACCDET_EINT_CMPEN_PWM_THRESH_MASK 0x7 |
| #define MT6338_ACCDET_EINT_CMPEN_PWM_THRESH_SHIFT 0 |
| #define MT6338_ACCDET_EINT_CMPEN_PWM_WIDTH_ADDR \ |
| MT6338_ACCDET_CON7_H |
| #define MT6338_ACCDET_EINT_CMPEN_PWM_WIDTH_MASK 0x3 |
| #define MT6338_ACCDET_EINT_CMPEN_PWM_WIDTH_SHIFT 4 |
| #define MT6338_ACCDET_DEBOUNCE0_L_ADDR \ |
| MT6338_ACCDET_CON8_L |
| #define MT6338_ACCDET_DEBOUNCE0_L_MASK 0xFF |
| #define MT6338_ACCDET_DEBOUNCE0_L_SHIFT 0 |
| #define MT6338_ACCDET_DEBOUNCE0_H_ADDR \ |
| MT6338_ACCDET_CON8_H |
| #define MT6338_ACCDET_DEBOUNCE0_H_MASK 0xFF |
| #define MT6338_ACCDET_DEBOUNCE0_H_SHIFT 0 |
| #define MT6338_ACCDET_DEBOUNCE1_L_ADDR \ |
| MT6338_ACCDET_CON9_L |
| #define MT6338_ACCDET_DEBOUNCE1_L_MASK 0xFF |
| #define MT6338_ACCDET_DEBOUNCE1_L_SHIFT 0 |
| #define MT6338_ACCDET_DEBOUNCE1_H_ADDR \ |
| MT6338_ACCDET_CON9_H |
| #define MT6338_ACCDET_DEBOUNCE1_H_MASK 0xFF |
| #define MT6338_ACCDET_DEBOUNCE1_H_SHIFT 0 |
| #define MT6338_ACCDET_DEBOUNCE2_L_ADDR \ |
| MT6338_ACCDET_CON10_L |
| #define MT6338_ACCDET_DEBOUNCE2_L_MASK 0xFF |
| #define MT6338_ACCDET_DEBOUNCE2_L_SHIFT 0 |
| #define MT6338_ACCDET_DEBOUNCE2_H_ADDR \ |
| MT6338_ACCDET_CON10_H |
| #define MT6338_ACCDET_DEBOUNCE2_H_MASK 0xFF |
| #define MT6338_ACCDET_DEBOUNCE2_H_SHIFT 0 |
| #define MT6338_ACCDET_DEBOUNCE3_L_ADDR \ |
| MT6338_ACCDET_CON11_L |
| #define MT6338_ACCDET_DEBOUNCE3_L_MASK 0xFF |
| #define MT6338_ACCDET_DEBOUNCE3_L_SHIFT 0 |
| #define MT6338_ACCDET_DEBOUNCE3_H_ADDR \ |
| MT6338_ACCDET_CON11_H |
| #define MT6338_ACCDET_DEBOUNCE3_H_MASK 0xFF |
| #define MT6338_ACCDET_DEBOUNCE3_H_SHIFT 0 |
| #define MT6338_ACCDET_CONNECT_AUXADC_TIME_DIG_L_ADDR \ |
| MT6338_ACCDET_CON12_L |
| #define MT6338_ACCDET_CONNECT_AUXADC_TIME_DIG_L_MASK 0xFF |
| #define MT6338_ACCDET_CONNECT_AUXADC_TIME_DIG_L_SHIFT 0 |
| #define MT6338_ACCDET_CONNECT_AUXADC_TIME_DIG_H_ADDR \ |
| MT6338_ACCDET_CON12_H |
| #define MT6338_ACCDET_CONNECT_AUXADC_TIME_DIG_H_MASK 0xFF |
| #define MT6338_ACCDET_CONNECT_AUXADC_TIME_DIG_H_SHIFT 0 |
| #define MT6338_ACCDET_CONNECT_AUXADC_TIME_ANA_L_ADDR \ |
| MT6338_ACCDET_CON13_L |
| #define MT6338_ACCDET_CONNECT_AUXADC_TIME_ANA_L_MASK 0xFF |
| #define MT6338_ACCDET_CONNECT_AUXADC_TIME_ANA_L_SHIFT 0 |
| #define MT6338_ACCDET_CONNECT_AUXADC_TIME_ANA_H_ADDR \ |
| MT6338_ACCDET_CON13_H |
| #define MT6338_ACCDET_CONNECT_AUXADC_TIME_ANA_H_MASK 0xFF |
| #define MT6338_ACCDET_CONNECT_AUXADC_TIME_ANA_H_SHIFT 0 |
| #define MT6338_ACCDET_EINT_DEBOUNCE0_ADDR \ |
| MT6338_ACCDET_CON14_L |
| #define MT6338_ACCDET_EINT_DEBOUNCE0_MASK 0xF |
| #define MT6338_ACCDET_EINT_DEBOUNCE0_SHIFT 0 |
| #define MT6338_ACCDET_EINT_DEBOUNCE1_ADDR \ |
| MT6338_ACCDET_CON14_L |
| #define MT6338_ACCDET_EINT_DEBOUNCE1_MASK 0xF |
| #define MT6338_ACCDET_EINT_DEBOUNCE1_SHIFT 4 |
| #define MT6338_ACCDET_EINT_DEBOUNCE2_ADDR \ |
| MT6338_ACCDET_CON14_H |
| #define MT6338_ACCDET_EINT_DEBOUNCE2_MASK 0xF |
| #define MT6338_ACCDET_EINT_DEBOUNCE2_SHIFT 0 |
| #define MT6338_ACCDET_EINT_DEBOUNCE3_ADDR \ |
| MT6338_ACCDET_CON14_H |
| #define MT6338_ACCDET_EINT_DEBOUNCE3_MASK 0xF |
| #define MT6338_ACCDET_EINT_DEBOUNCE3_SHIFT 4 |
| #define MT6338_ACCDET_EINT_INVERTER_DEBOUNCE_ADDR \ |
| MT6338_ACCDET_CON15 |
| #define MT6338_ACCDET_EINT_INVERTER_DEBOUNCE_MASK 0xF |
| #define MT6338_ACCDET_EINT_INVERTER_DEBOUNCE_SHIFT 0 |
| #define MT6338_ACCDET_IVAL_CUR_IN_ADDR \ |
| MT6338_ACCDET_CON16_L |
| #define MT6338_ACCDET_IVAL_CUR_IN_MASK 0x3 |
| #define MT6338_ACCDET_IVAL_CUR_IN_SHIFT 0 |
| #define MT6338_ACCDET_IVAL_SAM_IN_ADDR \ |
| MT6338_ACCDET_CON16_L |
| #define MT6338_ACCDET_IVAL_SAM_IN_MASK 0x3 |
| #define MT6338_ACCDET_IVAL_SAM_IN_SHIFT 2 |
| #define MT6338_ACCDET_IVAL_MEM_IN_ADDR \ |
| MT6338_ACCDET_CON16_L |
| #define MT6338_ACCDET_IVAL_MEM_IN_MASK 0x3 |
| #define MT6338_ACCDET_IVAL_MEM_IN_SHIFT 4 |
| #define MT6338_ACCDET_EINT_IVAL_CUR_IN_ADDR \ |
| MT6338_ACCDET_CON16_L |
| #define MT6338_ACCDET_EINT_IVAL_CUR_IN_MASK 0x3 |
| #define MT6338_ACCDET_EINT_IVAL_CUR_IN_SHIFT 6 |
| #define MT6338_ACCDET_EINT_IVAL_SAM_IN_ADDR \ |
| MT6338_ACCDET_CON16_H |
| #define MT6338_ACCDET_EINT_IVAL_SAM_IN_MASK 0x3 |
| #define MT6338_ACCDET_EINT_IVAL_SAM_IN_SHIFT 0 |
| #define MT6338_ACCDET_EINT_IVAL_MEM_IN_ADDR \ |
| MT6338_ACCDET_CON16_H |
| #define MT6338_ACCDET_EINT_IVAL_MEM_IN_MASK 0x3 |
| #define MT6338_ACCDET_EINT_IVAL_MEM_IN_SHIFT 2 |
| #define MT6338_ACCDET_IVAL_SEL_ADDR \ |
| MT6338_ACCDET_CON16_H |
| #define MT6338_ACCDET_IVAL_SEL_MASK 0x1 |
| #define MT6338_ACCDET_IVAL_SEL_SHIFT 4 |
| #define MT6338_ACCDET_EINT_IVAL_SEL_ADDR \ |
| MT6338_ACCDET_CON16_H |
| #define MT6338_ACCDET_EINT_IVAL_SEL_MASK 0x1 |
| #define MT6338_ACCDET_EINT_IVAL_SEL_SHIFT 5 |
| #define MT6338_ACCDET_EINT_INVERTER_IVAL_CUR_IN_ADDR \ |
| MT6338_ACCDET_CON17 |
| #define MT6338_ACCDET_EINT_INVERTER_IVAL_CUR_IN_MASK 0x1 |
| #define MT6338_ACCDET_EINT_INVERTER_IVAL_CUR_IN_SHIFT 0 |
| #define MT6338_ACCDET_EINT_INVERTER_IVAL_SAM_IN_ADDR \ |
| MT6338_ACCDET_CON17 |
| #define MT6338_ACCDET_EINT_INVERTER_IVAL_SAM_IN_MASK 0x1 |
| #define MT6338_ACCDET_EINT_INVERTER_IVAL_SAM_IN_SHIFT 1 |
| #define MT6338_ACCDET_EINT_INVERTER_IVAL_MEM_IN_ADDR \ |
| MT6338_ACCDET_CON17 |
| #define MT6338_ACCDET_EINT_INVERTER_IVAL_MEM_IN_MASK 0x1 |
| #define MT6338_ACCDET_EINT_INVERTER_IVAL_MEM_IN_SHIFT 2 |
| #define MT6338_ACCDET_EINT_INVERTER_IVAL_SEL_ADDR \ |
| MT6338_ACCDET_CON17 |
| #define MT6338_ACCDET_EINT_INVERTER_IVAL_SEL_MASK 0x1 |
| #define MT6338_ACCDET_EINT_INVERTER_IVAL_SEL_SHIFT 3 |
| #define MT6338_ACCDET_IRQ_ADDR \ |
| MT6338_ACCDET_CON18_L |
| #define MT6338_ACCDET_IRQ_MASK 0x1 |
| #define MT6338_ACCDET_IRQ_SHIFT 0 |
| #define MT6338_ACCDET_EINT0_IRQ_ADDR \ |
| MT6338_ACCDET_CON18_L |
| #define MT6338_ACCDET_EINT0_IRQ_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_IRQ_SHIFT 2 |
| #define MT6338_ACCDET_EINT1_IRQ_ADDR \ |
| MT6338_ACCDET_CON18_L |
| #define MT6338_ACCDET_EINT1_IRQ_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_IRQ_SHIFT 3 |
| #define MT6338_ACCDET_EINT_IN_INVERSE_ADDR \ |
| MT6338_ACCDET_CON18_L |
| #define MT6338_ACCDET_EINT_IN_INVERSE_MASK 0x1 |
| #define MT6338_ACCDET_EINT_IN_INVERSE_SHIFT 4 |
| #define MT6338_ACCDET_IRQ_CLR_ADDR \ |
| MT6338_ACCDET_CON18_H |
| #define MT6338_ACCDET_IRQ_CLR_MASK 0x1 |
| #define MT6338_ACCDET_IRQ_CLR_SHIFT 0 |
| #define MT6338_ACCDET_EINT0_IRQ_CLR_ADDR \ |
| MT6338_ACCDET_CON18_H |
| #define MT6338_ACCDET_EINT0_IRQ_CLR_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_IRQ_CLR_SHIFT 2 |
| #define MT6338_ACCDET_EINT1_IRQ_CLR_ADDR \ |
| MT6338_ACCDET_CON18_H |
| #define MT6338_ACCDET_EINT1_IRQ_CLR_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_IRQ_CLR_SHIFT 3 |
| #define MT6338_ACCDET_EINT_M_PLUG_IN_NUM_ADDR \ |
| MT6338_ACCDET_CON18_H |
| #define MT6338_ACCDET_EINT_M_PLUG_IN_NUM_MASK 0x7 |
| #define MT6338_ACCDET_EINT_M_PLUG_IN_NUM_SHIFT 4 |
| #define MT6338_ACCDET_DA_STABLE_ADDR \ |
| MT6338_ACCDET_CON19_L |
| #define MT6338_ACCDET_DA_STABLE_MASK 0x1 |
| #define MT6338_ACCDET_DA_STABLE_SHIFT 0 |
| #define MT6338_ACCDET_EINT0_EN_STABLE_ADDR \ |
| MT6338_ACCDET_CON19_L |
| #define MT6338_ACCDET_EINT0_EN_STABLE_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_EN_STABLE_SHIFT 1 |
| #define MT6338_ACCDET_EINT0_CMPEN_STABLE_ADDR \ |
| MT6338_ACCDET_CON19_L |
| #define MT6338_ACCDET_EINT0_CMPEN_STABLE_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_CMPEN_STABLE_SHIFT 2 |
| #define MT6338_ACCDET_EINT0_CMPMEN_STABLE_ADDR \ |
| MT6338_ACCDET_CON19_L |
| #define MT6338_ACCDET_EINT0_CMPMEN_STABLE_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_CMPMEN_STABLE_SHIFT 3 |
| #define MT6338_ACCDET_EINT0_CTURBO_STABLE_ADDR \ |
| MT6338_ACCDET_CON19_L |
| #define MT6338_ACCDET_EINT0_CTURBO_STABLE_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_CTURBO_STABLE_SHIFT 4 |
| #define MT6338_ACCDET_EINT0_CEN_STABLE_ADDR \ |
| MT6338_ACCDET_CON19_L |
| #define MT6338_ACCDET_EINT0_CEN_STABLE_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_CEN_STABLE_SHIFT 5 |
| #define MT6338_ACCDET_EINT1_EN_STABLE_ADDR \ |
| MT6338_ACCDET_CON19_L |
| #define MT6338_ACCDET_EINT1_EN_STABLE_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_EN_STABLE_SHIFT 6 |
| #define MT6338_ACCDET_EINT1_CMPEN_STABLE_ADDR \ |
| MT6338_ACCDET_CON19_L |
| #define MT6338_ACCDET_EINT1_CMPEN_STABLE_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_CMPEN_STABLE_SHIFT 7 |
| #define MT6338_ACCDET_EINT1_CMPMEN_STABLE_ADDR \ |
| MT6338_ACCDET_CON19_H |
| #define MT6338_ACCDET_EINT1_CMPMEN_STABLE_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_CMPMEN_STABLE_SHIFT 0 |
| #define MT6338_ACCDET_EINT1_CTURBO_STABLE_ADDR \ |
| MT6338_ACCDET_CON19_H |
| #define MT6338_ACCDET_EINT1_CTURBO_STABLE_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_CTURBO_STABLE_SHIFT 1 |
| #define MT6338_ACCDET_EINT1_CEN_STABLE_ADDR \ |
| MT6338_ACCDET_CON19_H |
| #define MT6338_ACCDET_EINT1_CEN_STABLE_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_CEN_STABLE_SHIFT 2 |
| #define MT6338_ACCDET_HWMODE_EN_ADDR \ |
| MT6338_ACCDET_CON20_L |
| #define MT6338_ACCDET_HWMODE_EN_MASK 0x1 |
| #define MT6338_ACCDET_HWMODE_EN_SHIFT 0 |
| #define MT6338_ACCDET_HWMODE_SEL_ADDR \ |
| MT6338_ACCDET_CON20_L |
| #define MT6338_ACCDET_HWMODE_SEL_MASK 0x3 |
| #define MT6338_ACCDET_HWMODE_SEL_SHIFT 1 |
| #define MT6338_ACCDET_PLUG_OUT_DETECT_ADDR \ |
| MT6338_ACCDET_CON20_L |
| #define MT6338_ACCDET_PLUG_OUT_DETECT_MASK 0x1 |
| #define MT6338_ACCDET_PLUG_OUT_DETECT_SHIFT 3 |
| #define MT6338_ACCDET_EINT0_REVERSE_ADDR \ |
| MT6338_ACCDET_CON20_L |
| #define MT6338_ACCDET_EINT0_REVERSE_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_REVERSE_SHIFT 4 |
| #define MT6338_ACCDET_EINT1_REVERSE_ADDR \ |
| MT6338_ACCDET_CON20_L |
| #define MT6338_ACCDET_EINT1_REVERSE_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_REVERSE_SHIFT 5 |
| #define MT6338_ACCDET_EINT_HWMODE_EN_ADDR \ |
| MT6338_ACCDET_CON20_H |
| #define MT6338_ACCDET_EINT_HWMODE_EN_MASK 0x1 |
| #define MT6338_ACCDET_EINT_HWMODE_EN_SHIFT 0 |
| #define MT6338_ACCDET_EINT_PLUG_OUT_BYPASS_DEB_ADDR \ |
| MT6338_ACCDET_CON20_H |
| #define MT6338_ACCDET_EINT_PLUG_OUT_BYPASS_DEB_MASK 0x1 |
| #define MT6338_ACCDET_EINT_PLUG_OUT_BYPASS_DEB_SHIFT 1 |
| #define MT6338_ACCDET_EINT_M_PLUG_IN_EN_ADDR \ |
| MT6338_ACCDET_CON20_H |
| #define MT6338_ACCDET_EINT_M_PLUG_IN_EN_MASK 0x1 |
| #define MT6338_ACCDET_EINT_M_PLUG_IN_EN_SHIFT 2 |
| #define MT6338_ACCDET_EINT_M_HWMODE_EN_ADDR \ |
| MT6338_ACCDET_CON20_H |
| #define MT6338_ACCDET_EINT_M_HWMODE_EN_MASK 0x1 |
| #define MT6338_ACCDET_EINT_M_HWMODE_EN_SHIFT 3 |
| #define MT6338_ACCDET_TEST_CMPEN_ADDR \ |
| MT6338_ACCDET_CON21_L |
| #define MT6338_ACCDET_TEST_CMPEN_MASK 0x1 |
| #define MT6338_ACCDET_TEST_CMPEN_SHIFT 0 |
| #define MT6338_ACCDET_TEST_VTHEN_ADDR \ |
| MT6338_ACCDET_CON21_L |
| #define MT6338_ACCDET_TEST_VTHEN_MASK 0x1 |
| #define MT6338_ACCDET_TEST_VTHEN_SHIFT 1 |
| #define MT6338_ACCDET_TEST_MBIASEN_ADDR \ |
| MT6338_ACCDET_CON21_L |
| #define MT6338_ACCDET_TEST_MBIASEN_MASK 0x1 |
| #define MT6338_ACCDET_TEST_MBIASEN_SHIFT 2 |
| #define MT6338_ACCDET_EINT_TEST_EN_ADDR \ |
| MT6338_ACCDET_CON21_L |
| #define MT6338_ACCDET_EINT_TEST_EN_MASK 0x1 |
| #define MT6338_ACCDET_EINT_TEST_EN_SHIFT 3 |
| #define MT6338_ACCDET_EINT_TEST_INVEN_ADDR \ |
| MT6338_ACCDET_CON21_L |
| #define MT6338_ACCDET_EINT_TEST_INVEN_MASK 0x1 |
| #define MT6338_ACCDET_EINT_TEST_INVEN_SHIFT 4 |
| #define MT6338_ACCDET_EINT_TEST_CMPEN_ADDR \ |
| MT6338_ACCDET_CON21_L |
| #define MT6338_ACCDET_EINT_TEST_CMPEN_MASK 0x1 |
| #define MT6338_ACCDET_EINT_TEST_CMPEN_SHIFT 5 |
| #define MT6338_ACCDET_EINT_TEST_CMPMEN_ADDR \ |
| MT6338_ACCDET_CON21_L |
| #define MT6338_ACCDET_EINT_TEST_CMPMEN_MASK 0x1 |
| #define MT6338_ACCDET_EINT_TEST_CMPMEN_SHIFT 6 |
| #define MT6338_ACCDET_EINT_TEST_CTURBO_ADDR \ |
| MT6338_ACCDET_CON21_L |
| #define MT6338_ACCDET_EINT_TEST_CTURBO_MASK 0x1 |
| #define MT6338_ACCDET_EINT_TEST_CTURBO_SHIFT 7 |
| #define MT6338_ACCDET_EINT_TEST_CEN_ADDR \ |
| MT6338_ACCDET_CON21_H |
| #define MT6338_ACCDET_EINT_TEST_CEN_MASK 0x1 |
| #define MT6338_ACCDET_EINT_TEST_CEN_SHIFT 0 |
| #define MT6338_ACCDET_TEST_B_ADDR \ |
| MT6338_ACCDET_CON21_H |
| #define MT6338_ACCDET_TEST_B_MASK 0x1 |
| #define MT6338_ACCDET_TEST_B_SHIFT 1 |
| #define MT6338_ACCDET_TEST_A_ADDR \ |
| MT6338_ACCDET_CON21_H |
| #define MT6338_ACCDET_TEST_A_MASK 0x1 |
| #define MT6338_ACCDET_TEST_A_SHIFT 2 |
| #define MT6338_ACCDET_EINT_TEST_CMPOUT_ADDR \ |
| MT6338_ACCDET_CON21_H |
| #define MT6338_ACCDET_EINT_TEST_CMPOUT_MASK 0x1 |
| #define MT6338_ACCDET_EINT_TEST_CMPOUT_SHIFT 3 |
| #define MT6338_ACCDET_EINT_TEST_CMPMOUT_ADDR \ |
| MT6338_ACCDET_CON21_H |
| #define MT6338_ACCDET_EINT_TEST_CMPMOUT_MASK 0x1 |
| #define MT6338_ACCDET_EINT_TEST_CMPMOUT_SHIFT 4 |
| #define MT6338_ACCDET_EINT_TEST_INVOUT_ADDR \ |
| MT6338_ACCDET_CON21_H |
| #define MT6338_ACCDET_EINT_TEST_INVOUT_MASK 0x1 |
| #define MT6338_ACCDET_EINT_TEST_INVOUT_SHIFT 5 |
| #define MT6338_ACCDET_CMPEN_SEL_ADDR \ |
| MT6338_ACCDET_CON22_L |
| #define MT6338_ACCDET_CMPEN_SEL_MASK 0x1 |
| #define MT6338_ACCDET_CMPEN_SEL_SHIFT 0 |
| #define MT6338_ACCDET_VTHEN_SEL_ADDR \ |
| MT6338_ACCDET_CON22_L |
| #define MT6338_ACCDET_VTHEN_SEL_MASK 0x1 |
| #define MT6338_ACCDET_VTHEN_SEL_SHIFT 1 |
| #define MT6338_ACCDET_MBIASEN_SEL_ADDR \ |
| MT6338_ACCDET_CON22_L |
| #define MT6338_ACCDET_MBIASEN_SEL_MASK 0x1 |
| #define MT6338_ACCDET_MBIASEN_SEL_SHIFT 2 |
| #define MT6338_ACCDET_EINT_EN_SEL_ADDR \ |
| MT6338_ACCDET_CON22_L |
| #define MT6338_ACCDET_EINT_EN_SEL_MASK 0x1 |
| #define MT6338_ACCDET_EINT_EN_SEL_SHIFT 3 |
| #define MT6338_ACCDET_EINT_INVEN_SEL_ADDR \ |
| MT6338_ACCDET_CON22_L |
| #define MT6338_ACCDET_EINT_INVEN_SEL_MASK 0x1 |
| #define MT6338_ACCDET_EINT_INVEN_SEL_SHIFT 4 |
| #define MT6338_ACCDET_EINT_CMPEN_SEL_ADDR \ |
| MT6338_ACCDET_CON22_L |
| #define MT6338_ACCDET_EINT_CMPEN_SEL_MASK 0x1 |
| #define MT6338_ACCDET_EINT_CMPEN_SEL_SHIFT 5 |
| #define MT6338_ACCDET_EINT_CMPMEN_SEL_ADDR \ |
| MT6338_ACCDET_CON22_L |
| #define MT6338_ACCDET_EINT_CMPMEN_SEL_MASK 0x1 |
| #define MT6338_ACCDET_EINT_CMPMEN_SEL_SHIFT 6 |
| #define MT6338_ACCDET_EINT_CTURBO_SEL_ADDR \ |
| MT6338_ACCDET_CON22_L |
| #define MT6338_ACCDET_EINT_CTURBO_SEL_MASK 0x1 |
| #define MT6338_ACCDET_EINT_CTURBO_SEL_SHIFT 7 |
| #define MT6338_ACCDET_B_SEL_ADDR \ |
| MT6338_ACCDET_CON22_H |
| #define MT6338_ACCDET_B_SEL_MASK 0x1 |
| #define MT6338_ACCDET_B_SEL_SHIFT 1 |
| #define MT6338_ACCDET_A_SEL_ADDR \ |
| MT6338_ACCDET_CON22_H |
| #define MT6338_ACCDET_A_SEL_MASK 0x1 |
| #define MT6338_ACCDET_A_SEL_SHIFT 2 |
| #define MT6338_ACCDET_EINT_CMPOUT_SEL_ADDR \ |
| MT6338_ACCDET_CON22_H |
| #define MT6338_ACCDET_EINT_CMPOUT_SEL_MASK 0x1 |
| #define MT6338_ACCDET_EINT_CMPOUT_SEL_SHIFT 3 |
| #define MT6338_ACCDET_EINT_CMPMOUT_SEL_ADDR \ |
| MT6338_ACCDET_CON22_H |
| #define MT6338_ACCDET_EINT_CMPMOUT_SEL_MASK 0x1 |
| #define MT6338_ACCDET_EINT_CMPMOUT_SEL_SHIFT 4 |
| #define MT6338_ACCDET_EINT_INVOUT_SEL_ADDR \ |
| MT6338_ACCDET_CON22_H |
| #define MT6338_ACCDET_EINT_INVOUT_SEL_MASK 0x1 |
| #define MT6338_ACCDET_EINT_INVOUT_SEL_SHIFT 5 |
| #define MT6338_ACCDET_CMPEN_SW_ADDR \ |
| MT6338_ACCDET_CON23_L |
| #define MT6338_ACCDET_CMPEN_SW_MASK 0x1 |
| #define MT6338_ACCDET_CMPEN_SW_SHIFT 0 |
| #define MT6338_ACCDET_VTHEN_SW_ADDR \ |
| MT6338_ACCDET_CON23_L |
| #define MT6338_ACCDET_VTHEN_SW_MASK 0x1 |
| #define MT6338_ACCDET_VTHEN_SW_SHIFT 1 |
| #define MT6338_ACCDET_MBIASEN_SW_ADDR \ |
| MT6338_ACCDET_CON23_L |
| #define MT6338_ACCDET_MBIASEN_SW_MASK 0x1 |
| #define MT6338_ACCDET_MBIASEN_SW_SHIFT 2 |
| #define MT6338_ACCDET_EINT0_EN_SW_ADDR \ |
| MT6338_ACCDET_CON23_L |
| #define MT6338_ACCDET_EINT0_EN_SW_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_EN_SW_SHIFT 3 |
| #define MT6338_ACCDET_EINT0_INVEN_SW_ADDR \ |
| MT6338_ACCDET_CON23_L |
| #define MT6338_ACCDET_EINT0_INVEN_SW_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_INVEN_SW_SHIFT 4 |
| #define MT6338_ACCDET_EINT0_CMPEN_SW_ADDR \ |
| MT6338_ACCDET_CON23_L |
| #define MT6338_ACCDET_EINT0_CMPEN_SW_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_CMPEN_SW_SHIFT 5 |
| #define MT6338_ACCDET_EINT0_CMPMEN_SW_ADDR \ |
| MT6338_ACCDET_CON23_L |
| #define MT6338_ACCDET_EINT0_CMPMEN_SW_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_CMPMEN_SW_SHIFT 6 |
| #define MT6338_ACCDET_EINT0_CTURBO_SW_ADDR \ |
| MT6338_ACCDET_CON23_L |
| #define MT6338_ACCDET_EINT0_CTURBO_SW_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_CTURBO_SW_SHIFT 7 |
| #define MT6338_ACCDET_EINT1_EN_SW_ADDR \ |
| MT6338_ACCDET_CON23_H |
| #define MT6338_ACCDET_EINT1_EN_SW_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_EN_SW_SHIFT 0 |
| #define MT6338_ACCDET_EINT1_INVEN_SW_ADDR \ |
| MT6338_ACCDET_CON23_H |
| #define MT6338_ACCDET_EINT1_INVEN_SW_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_INVEN_SW_SHIFT 1 |
| #define MT6338_ACCDET_EINT1_CMPEN_SW_ADDR \ |
| MT6338_ACCDET_CON23_H |
| #define MT6338_ACCDET_EINT1_CMPEN_SW_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_CMPEN_SW_SHIFT 2 |
| #define MT6338_ACCDET_EINT1_CMPMEN_SW_ADDR \ |
| MT6338_ACCDET_CON23_H |
| #define MT6338_ACCDET_EINT1_CMPMEN_SW_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_CMPMEN_SW_SHIFT 3 |
| #define MT6338_ACCDET_EINT1_CTURBO_SW_ADDR \ |
| MT6338_ACCDET_CON23_H |
| #define MT6338_ACCDET_EINT1_CTURBO_SW_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_CTURBO_SW_SHIFT 4 |
| #define MT6338_ACCDET_B_SW_ADDR \ |
| MT6338_ACCDET_CON24 |
| #define MT6338_ACCDET_B_SW_MASK 0x1 |
| #define MT6338_ACCDET_B_SW_SHIFT 0 |
| #define MT6338_ACCDET_A_SW_ADDR \ |
| MT6338_ACCDET_CON24 |
| #define MT6338_ACCDET_A_SW_MASK 0x1 |
| #define MT6338_ACCDET_A_SW_SHIFT 1 |
| #define MT6338_ACCDET_EINT0_CMPOUT_SW_ADDR \ |
| MT6338_ACCDET_CON24 |
| #define MT6338_ACCDET_EINT0_CMPOUT_SW_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_CMPOUT_SW_SHIFT 2 |
| #define MT6338_ACCDET_EINT0_CMPMOUT_SW_ADDR \ |
| MT6338_ACCDET_CON24 |
| #define MT6338_ACCDET_EINT0_CMPMOUT_SW_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_CMPMOUT_SW_SHIFT 3 |
| #define MT6338_ACCDET_EINT0_INVOUT_SW_ADDR \ |
| MT6338_ACCDET_CON24 |
| #define MT6338_ACCDET_EINT0_INVOUT_SW_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_INVOUT_SW_SHIFT 4 |
| #define MT6338_ACCDET_EINT1_CMPOUT_SW_ADDR \ |
| MT6338_ACCDET_CON24 |
| #define MT6338_ACCDET_EINT1_CMPOUT_SW_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_CMPOUT_SW_SHIFT 5 |
| #define MT6338_ACCDET_EINT1_CMPMOUT_SW_ADDR \ |
| MT6338_ACCDET_CON24 |
| #define MT6338_ACCDET_EINT1_CMPMOUT_SW_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_CMPMOUT_SW_SHIFT 6 |
| #define MT6338_ACCDET_EINT1_INVOUT_SW_ADDR \ |
| MT6338_ACCDET_CON24 |
| #define MT6338_ACCDET_EINT1_INVOUT_SW_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_INVOUT_SW_SHIFT 7 |
| #define MT6338_AD_AUDACCDETCMPOB_ADDR \ |
| MT6338_ACCDET_CON25_L |
| #define MT6338_AD_AUDACCDETCMPOB_MASK 0x1 |
| #define MT6338_AD_AUDACCDETCMPOB_SHIFT 0 |
| #define MT6338_AD_AUDACCDETCMPOA_ADDR \ |
| MT6338_ACCDET_CON25_L |
| #define MT6338_AD_AUDACCDETCMPOA_MASK 0x1 |
| #define MT6338_AD_AUDACCDETCMPOA_SHIFT 1 |
| #define MT6338_ACCDET_CUR_IN_ADDR \ |
| MT6338_ACCDET_CON25_L |
| #define MT6338_ACCDET_CUR_IN_MASK 0x3 |
| #define MT6338_ACCDET_CUR_IN_SHIFT 2 |
| #define MT6338_ACCDET_SAM_IN_ADDR \ |
| MT6338_ACCDET_CON25_L |
| #define MT6338_ACCDET_SAM_IN_MASK 0x3 |
| #define MT6338_ACCDET_SAM_IN_SHIFT 4 |
| #define MT6338_ACCDET_MEM_IN_ADDR \ |
| MT6338_ACCDET_CON25_L |
| #define MT6338_ACCDET_MEM_IN_MASK 0x3 |
| #define MT6338_ACCDET_MEM_IN_SHIFT 6 |
| #define MT6338_ACCDET_STATE_ADDR \ |
| MT6338_ACCDET_CON25_H |
| #define MT6338_ACCDET_STATE_MASK 0x7 |
| #define MT6338_ACCDET_STATE_SHIFT 0 |
| #define MT6338_DA_AUDACCDETMBIASCLK_ADDR \ |
| MT6338_ACCDET_CON25_H |
| #define MT6338_DA_AUDACCDETMBIASCLK_MASK 0x1 |
| #define MT6338_DA_AUDACCDETMBIASCLK_SHIFT 4 |
| #define MT6338_DA_AUDACCDETVTHCLK_ADDR \ |
| MT6338_ACCDET_CON25_H |
| #define MT6338_DA_AUDACCDETVTHCLK_MASK 0x1 |
| #define MT6338_DA_AUDACCDETVTHCLK_SHIFT 5 |
| #define MT6338_DA_AUDACCDETCMPCLK_ADDR \ |
| MT6338_ACCDET_CON25_H |
| #define MT6338_DA_AUDACCDETCMPCLK_MASK 0x1 |
| #define MT6338_DA_AUDACCDETCMPCLK_SHIFT 6 |
| #define MT6338_DA_AUDACCDETAUXADCSWCTRL_ADDR \ |
| MT6338_ACCDET_CON25_H |
| #define MT6338_DA_AUDACCDETAUXADCSWCTRL_MASK 0x1 |
| #define MT6338_DA_AUDACCDETAUXADCSWCTRL_SHIFT 7 |
| #define MT6338_AD_EINT0CMPMOUT_ADDR \ |
| MT6338_ACCDET_CON26_L |
| #define MT6338_AD_EINT0CMPMOUT_MASK 0x1 |
| #define MT6338_AD_EINT0CMPMOUT_SHIFT 0 |
| #define MT6338_AD_EINT0CMPOUT_ADDR \ |
| MT6338_ACCDET_CON26_L |
| #define MT6338_AD_EINT0CMPOUT_MASK 0x1 |
| #define MT6338_AD_EINT0CMPOUT_SHIFT 1 |
| #define MT6338_ACCDET_EINT0_CUR_IN_ADDR \ |
| MT6338_ACCDET_CON26_L |
| #define MT6338_ACCDET_EINT0_CUR_IN_MASK 0x3 |
| #define MT6338_ACCDET_EINT0_CUR_IN_SHIFT 2 |
| #define MT6338_ACCDET_EINT0_SAM_IN_ADDR \ |
| MT6338_ACCDET_CON26_L |
| #define MT6338_ACCDET_EINT0_SAM_IN_MASK 0x3 |
| #define MT6338_ACCDET_EINT0_SAM_IN_SHIFT 4 |
| #define MT6338_ACCDET_EINT0_MEM_IN_ADDR \ |
| MT6338_ACCDET_CON26_L |
| #define MT6338_ACCDET_EINT0_MEM_IN_MASK 0x3 |
| #define MT6338_ACCDET_EINT0_MEM_IN_SHIFT 6 |
| #define MT6338_ACCDET_EINT0_STATE_ADDR \ |
| MT6338_ACCDET_CON26_H |
| #define MT6338_ACCDET_EINT0_STATE_MASK 0x7 |
| #define MT6338_ACCDET_EINT0_STATE_SHIFT 0 |
| #define MT6338_DA_EINT0CMPEN_ADDR \ |
| MT6338_ACCDET_CON26_H |
| #define MT6338_DA_EINT0CMPEN_MASK 0x1 |
| #define MT6338_DA_EINT0CMPEN_SHIFT 5 |
| #define MT6338_DA_EINT0CMPMEN_ADDR \ |
| MT6338_ACCDET_CON26_H |
| #define MT6338_DA_EINT0CMPMEN_MASK 0x1 |
| #define MT6338_DA_EINT0CMPMEN_SHIFT 6 |
| #define MT6338_DA_EINT0CTURBO_ADDR \ |
| MT6338_ACCDET_CON26_H |
| #define MT6338_DA_EINT0CTURBO_MASK 0x1 |
| #define MT6338_DA_EINT0CTURBO_SHIFT 7 |
| #define MT6338_AD_EINT1CMPMOUT_ADDR \ |
| MT6338_ACCDET_CON27_L |
| #define MT6338_AD_EINT1CMPMOUT_MASK 0x1 |
| #define MT6338_AD_EINT1CMPMOUT_SHIFT 0 |
| #define MT6338_AD_EINT1CMPOUT_ADDR \ |
| MT6338_ACCDET_CON27_L |
| #define MT6338_AD_EINT1CMPOUT_MASK 0x1 |
| #define MT6338_AD_EINT1CMPOUT_SHIFT 1 |
| #define MT6338_ACCDET_EINT1_CUR_IN_ADDR \ |
| MT6338_ACCDET_CON27_L |
| #define MT6338_ACCDET_EINT1_CUR_IN_MASK 0x3 |
| #define MT6338_ACCDET_EINT1_CUR_IN_SHIFT 2 |
| #define MT6338_ACCDET_EINT1_SAM_IN_ADDR \ |
| MT6338_ACCDET_CON27_L |
| #define MT6338_ACCDET_EINT1_SAM_IN_MASK 0x3 |
| #define MT6338_ACCDET_EINT1_SAM_IN_SHIFT 4 |
| #define MT6338_ACCDET_EINT1_MEM_IN_ADDR \ |
| MT6338_ACCDET_CON27_L |
| #define MT6338_ACCDET_EINT1_MEM_IN_MASK 0x3 |
| #define MT6338_ACCDET_EINT1_MEM_IN_SHIFT 6 |
| #define MT6338_ACCDET_EINT1_STATE_ADDR \ |
| MT6338_ACCDET_CON27_H |
| #define MT6338_ACCDET_EINT1_STATE_MASK 0x7 |
| #define MT6338_ACCDET_EINT1_STATE_SHIFT 0 |
| #define MT6338_DA_EINT1CMPEN_ADDR \ |
| MT6338_ACCDET_CON27_H |
| #define MT6338_DA_EINT1CMPEN_MASK 0x1 |
| #define MT6338_DA_EINT1CMPEN_SHIFT 5 |
| #define MT6338_DA_EINT1CMPMEN_ADDR \ |
| MT6338_ACCDET_CON27_H |
| #define MT6338_DA_EINT1CMPMEN_MASK 0x1 |
| #define MT6338_DA_EINT1CMPMEN_SHIFT 6 |
| #define MT6338_DA_EINT1CTURBO_ADDR \ |
| MT6338_ACCDET_CON27_H |
| #define MT6338_DA_EINT1CTURBO_MASK 0x1 |
| #define MT6338_DA_EINT1CTURBO_SHIFT 7 |
| #define MT6338_AD_EINT0INVOUT_ADDR \ |
| MT6338_ACCDET_CON28_L |
| #define MT6338_AD_EINT0INVOUT_MASK 0x1 |
| #define MT6338_AD_EINT0INVOUT_SHIFT 0 |
| #define MT6338_ACCDET_EINT0_INVERTER_CUR_IN_ADDR \ |
| MT6338_ACCDET_CON28_L |
| #define MT6338_ACCDET_EINT0_INVERTER_CUR_IN_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_INVERTER_CUR_IN_SHIFT 1 |
| #define MT6338_ACCDET_EINT0_INVERTER_SAM_IN_ADDR \ |
| MT6338_ACCDET_CON28_L |
| #define MT6338_ACCDET_EINT0_INVERTER_SAM_IN_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_INVERTER_SAM_IN_SHIFT 2 |
| #define MT6338_ACCDET_EINT0_INVERTER_MEM_IN_ADDR \ |
| MT6338_ACCDET_CON28_L |
| #define MT6338_ACCDET_EINT0_INVERTER_MEM_IN_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_INVERTER_MEM_IN_SHIFT 3 |
| #define MT6338_ACCDET_EINT0_INVERTER_STATE_ADDR \ |
| MT6338_ACCDET_CON28_H |
| #define MT6338_ACCDET_EINT0_INVERTER_STATE_MASK 0x7 |
| #define MT6338_ACCDET_EINT0_INVERTER_STATE_SHIFT 0 |
| #define MT6338_DA_EINT0EN_ADDR \ |
| MT6338_ACCDET_CON28_H |
| #define MT6338_DA_EINT0EN_MASK 0x1 |
| #define MT6338_DA_EINT0EN_SHIFT 4 |
| #define MT6338_DA_EINT0INVEN_ADDR \ |
| MT6338_ACCDET_CON28_H |
| #define MT6338_DA_EINT0INVEN_MASK 0x1 |
| #define MT6338_DA_EINT0INVEN_SHIFT 5 |
| #define MT6338_DA_EINT0CEN_ADDR \ |
| MT6338_ACCDET_CON28_H |
| #define MT6338_DA_EINT0CEN_MASK 0x1 |
| #define MT6338_DA_EINT0CEN_SHIFT 6 |
| #define MT6338_AD_EINT1INVOUT_ADDR \ |
| MT6338_ACCDET_CON29_L |
| #define MT6338_AD_EINT1INVOUT_MASK 0x1 |
| #define MT6338_AD_EINT1INVOUT_SHIFT 0 |
| #define MT6338_ACCDET_EINT1_INVERTER_CUR_IN_ADDR \ |
| MT6338_ACCDET_CON29_L |
| #define MT6338_ACCDET_EINT1_INVERTER_CUR_IN_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_INVERTER_CUR_IN_SHIFT 1 |
| #define MT6338_ACCDET_EINT1_INVERTER_SAM_IN_ADDR \ |
| MT6338_ACCDET_CON29_L |
| #define MT6338_ACCDET_EINT1_INVERTER_SAM_IN_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_INVERTER_SAM_IN_SHIFT 2 |
| #define MT6338_ACCDET_EINT1_INVERTER_MEM_IN_ADDR \ |
| MT6338_ACCDET_CON29_L |
| #define MT6338_ACCDET_EINT1_INVERTER_MEM_IN_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_INVERTER_MEM_IN_SHIFT 3 |
| #define MT6338_ACCDET_EINT1_INVERTER_STATE_ADDR \ |
| MT6338_ACCDET_CON29_H |
| #define MT6338_ACCDET_EINT1_INVERTER_STATE_MASK 0x7 |
| #define MT6338_ACCDET_EINT1_INVERTER_STATE_SHIFT 0 |
| #define MT6338_DA_EINT1EN_ADDR \ |
| MT6338_ACCDET_CON29_H |
| #define MT6338_DA_EINT1EN_MASK 0x1 |
| #define MT6338_DA_EINT1EN_SHIFT 3 |
| #define MT6338_DA_EINT1INVEN_ADDR \ |
| MT6338_ACCDET_CON29_H |
| #define MT6338_DA_EINT1INVEN_MASK 0x1 |
| #define MT6338_DA_EINT1INVEN_SHIFT 4 |
| #define MT6338_DA_EINT1CEN_ADDR \ |
| MT6338_ACCDET_CON29_H |
| #define MT6338_DA_EINT1CEN_MASK 0x1 |
| #define MT6338_DA_EINT1CEN_SHIFT 5 |
| #define MT6338_ACCDET_EN_ADDR \ |
| MT6338_ACCDET_CON30_L |
| #define MT6338_ACCDET_EN_MASK 0x1 |
| #define MT6338_ACCDET_EN_SHIFT 0 |
| #define MT6338_ACCDET_EINT0_EN_ADDR \ |
| MT6338_ACCDET_CON30_L |
| #define MT6338_ACCDET_EINT0_EN_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_EN_SHIFT 1 |
| #define MT6338_ACCDET_EINT1_EN_ADDR \ |
| MT6338_ACCDET_CON30_L |
| #define MT6338_ACCDET_EINT1_EN_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_EN_SHIFT 2 |
| #define MT6338_ACCDET_EINT0_M_EN_ADDR \ |
| MT6338_ACCDET_CON30_L |
| #define MT6338_ACCDET_EINT0_M_EN_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_M_EN_SHIFT 3 |
| #define MT6338_ACCDET_EINT0_DETECT_MOISTURE_ADDR \ |
| MT6338_ACCDET_CON30_L |
| #define MT6338_ACCDET_EINT0_DETECT_MOISTURE_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_DETECT_MOISTURE_SHIFT 4 |
| #define MT6338_ACCDET_EINT0_PLUG_IN_ADDR \ |
| MT6338_ACCDET_CON30_L |
| #define MT6338_ACCDET_EINT0_PLUG_IN_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_PLUG_IN_SHIFT 5 |
| #define MT6338_ACCDET_EINT0_M_PLUG_IN_ADDR \ |
| MT6338_ACCDET_CON30_L |
| #define MT6338_ACCDET_EINT0_M_PLUG_IN_MASK 0x1 |
| #define MT6338_ACCDET_EINT0_M_PLUG_IN_SHIFT 6 |
| #define MT6338_ACCDET_EINT1_M_EN_ADDR \ |
| MT6338_ACCDET_CON30_L |
| #define MT6338_ACCDET_EINT1_M_EN_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_M_EN_SHIFT 7 |
| #define MT6338_ACCDET_EINT1_DETECT_MOISTURE_ADDR \ |
| MT6338_ACCDET_CON30_H |
| #define MT6338_ACCDET_EINT1_DETECT_MOISTURE_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_DETECT_MOISTURE_SHIFT 0 |
| #define MT6338_ACCDET_EINT1_PLUG_IN_ADDR \ |
| MT6338_ACCDET_CON30_H |
| #define MT6338_ACCDET_EINT1_PLUG_IN_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_PLUG_IN_SHIFT 1 |
| #define MT6338_ACCDET_EINT1_M_PLUG_IN_ADDR \ |
| MT6338_ACCDET_CON30_H |
| #define MT6338_ACCDET_EINT1_M_PLUG_IN_MASK 0x1 |
| #define MT6338_ACCDET_EINT1_M_PLUG_IN_SHIFT 2 |
| #define MT6338_ACCDET_CUR_DEB_L_ADDR \ |
| MT6338_ACCDET_CON31_L |
| #define MT6338_ACCDET_CUR_DEB_L_MASK 0xFF |
| #define MT6338_ACCDET_CUR_DEB_L_SHIFT 0 |
| #define MT6338_ACCDET_CUR_DEB_H_ADDR \ |
| MT6338_ACCDET_CON31_H |
| #define MT6338_ACCDET_CUR_DEB_H_MASK 0xFF |
| #define MT6338_ACCDET_CUR_DEB_H_SHIFT 0 |
| #define MT6338_ACCDET_EINT0_CUR_DEB_L_ADDR \ |
| MT6338_ACCDET_CON32_L |
| #define MT6338_ACCDET_EINT0_CUR_DEB_L_MASK 0xFF |
| #define MT6338_ACCDET_EINT0_CUR_DEB_L_SHIFT 0 |
| #define MT6338_ACCDET_EINT0_CUR_DEB_H_ADDR \ |
| MT6338_ACCDET_CON32_H |
| #define MT6338_ACCDET_EINT0_CUR_DEB_H_MASK 0x7F |
| #define MT6338_ACCDET_EINT0_CUR_DEB_H_SHIFT 0 |
| #define MT6338_ACCDET_EINT1_CUR_DEB_L_ADDR \ |
| MT6338_ACCDET_CON33_L |
| #define MT6338_ACCDET_EINT1_CUR_DEB_L_MASK 0xFF |
| #define MT6338_ACCDET_EINT1_CUR_DEB_L_SHIFT 0 |
| #define MT6338_ACCDET_EINT1_CUR_DEB_H_ADDR \ |
| MT6338_ACCDET_CON33_H |
| #define MT6338_ACCDET_EINT1_CUR_DEB_H_MASK 0x7F |
| #define MT6338_ACCDET_EINT1_CUR_DEB_H_SHIFT 0 |
| #define MT6338_ACCDET_EINT0_INVERTER_CUR_DEB_L_ADDR \ |
| MT6338_ACCDET_CON34_L |
| #define MT6338_ACCDET_EINT0_INVERTER_CUR_DEB_L_MASK 0xFF |
| #define MT6338_ACCDET_EINT0_INVERTER_CUR_DEB_L_SHIFT 0 |
| #define MT6338_ACCDET_EINT0_INVERTER_CUR_DEB_H_ADDR \ |
| MT6338_ACCDET_CON34_H |
| #define MT6338_ACCDET_EINT0_INVERTER_CUR_DEB_H_MASK 0x7F |
| #define MT6338_ACCDET_EINT0_INVERTER_CUR_DEB_H_SHIFT 0 |
| #define MT6338_ACCDET_EINT1_INVERTER_CUR_DEB_L_ADDR \ |
| MT6338_ACCDET_CON35_L |
| #define MT6338_ACCDET_EINT1_INVERTER_CUR_DEB_L_MASK 0xFF |
| #define MT6338_ACCDET_EINT1_INVERTER_CUR_DEB_L_SHIFT 0 |
| #define MT6338_ACCDET_EINT1_INVERTER_CUR_DEB_H_ADDR \ |
| MT6338_ACCDET_CON35_H |
| #define MT6338_ACCDET_EINT1_INVERTER_CUR_DEB_H_MASK 0x7F |
| #define MT6338_ACCDET_EINT1_INVERTER_CUR_DEB_H_SHIFT 0 |
| #define MT6338_AD_AUDACCDETCMPOB_MON_ADDR \ |
| MT6338_ACCDET_CON36 |
| #define MT6338_AD_AUDACCDETCMPOB_MON_MASK 0x1 |
| #define MT6338_AD_AUDACCDETCMPOB_MON_SHIFT 0 |
| #define MT6338_AD_AUDACCDETCMPOA_MON_ADDR \ |
| MT6338_ACCDET_CON36 |
| #define MT6338_AD_AUDACCDETCMPOA_MON_MASK 0x1 |
| #define MT6338_AD_AUDACCDETCMPOA_MON_SHIFT 1 |
| #define MT6338_AD_EINT0CMPMOUT_MON_ADDR \ |
| MT6338_ACCDET_CON36 |
| #define MT6338_AD_EINT0CMPMOUT_MON_MASK 0x1 |
| #define MT6338_AD_EINT0CMPMOUT_MON_SHIFT 2 |
| #define MT6338_AD_EINT0CMPOUT_MON_ADDR \ |
| MT6338_ACCDET_CON36 |
| #define MT6338_AD_EINT0CMPOUT_MON_MASK 0x1 |
| #define MT6338_AD_EINT0CMPOUT_MON_SHIFT 3 |
| #define MT6338_AD_EINT0INVOUT_MON_ADDR \ |
| MT6338_ACCDET_CON36 |
| #define MT6338_AD_EINT0INVOUT_MON_MASK 0x1 |
| #define MT6338_AD_EINT0INVOUT_MON_SHIFT 4 |
| #define MT6338_AD_EINT1CMPMOUT_MON_ADDR \ |
| MT6338_ACCDET_CON36 |
| #define MT6338_AD_EINT1CMPMOUT_MON_MASK 0x1 |
| #define MT6338_AD_EINT1CMPMOUT_MON_SHIFT 5 |
| #define MT6338_AD_EINT1CMPOUT_MON_ADDR \ |
| MT6338_ACCDET_CON36 |
| #define MT6338_AD_EINT1CMPOUT_MON_MASK 0x1 |
| #define MT6338_AD_EINT1CMPOUT_MON_SHIFT 6 |
| #define MT6338_AD_EINT1INVOUT_MON_ADDR \ |
| MT6338_ACCDET_CON36 |
| #define MT6338_AD_EINT1INVOUT_MON_MASK 0x1 |
| #define MT6338_AD_EINT1INVOUT_MON_SHIFT 7 |
| #define MT6338_DA_AUDACCDETCMPCLK_MON_ADDR \ |
| MT6338_ACCDET_CON37 |
| #define MT6338_DA_AUDACCDETCMPCLK_MON_MASK 0x1 |
| #define MT6338_DA_AUDACCDETCMPCLK_MON_SHIFT 0 |
| #define MT6338_DA_AUDACCDETVTHCLK_MON_ADDR \ |
| MT6338_ACCDET_CON37 |
| #define MT6338_DA_AUDACCDETVTHCLK_MON_MASK 0x1 |
| #define MT6338_DA_AUDACCDETVTHCLK_MON_SHIFT 1 |
| #define MT6338_DA_AUDACCDETMBIASCLK_MON_ADDR \ |
| MT6338_ACCDET_CON37 |
| #define MT6338_DA_AUDACCDETMBIASCLK_MON_MASK 0x1 |
| #define MT6338_DA_AUDACCDETMBIASCLK_MON_SHIFT 2 |
| #define MT6338_DA_AUDACCDETAUXADCSWCTRL_MON_ADDR \ |
| MT6338_ACCDET_CON37 |
| #define MT6338_DA_AUDACCDETAUXADCSWCTRL_MON_MASK 0x1 |
| #define MT6338_DA_AUDACCDETAUXADCSWCTRL_MON_SHIFT 3 |
| #define MT6338_DA_EINT0CTURBO_MON_ADDR \ |
| MT6338_ACCDET_CON38_L |
| #define MT6338_DA_EINT0CTURBO_MON_MASK 0x1 |
| #define MT6338_DA_EINT0CTURBO_MON_SHIFT 0 |
| #define MT6338_DA_EINT0CMPMEN_MON_ADDR \ |
| MT6338_ACCDET_CON38_L |
| #define MT6338_DA_EINT0CMPMEN_MON_MASK 0x1 |
| #define MT6338_DA_EINT0CMPMEN_MON_SHIFT 1 |
| #define MT6338_DA_EINT0CMPEN_MON_ADDR \ |
| MT6338_ACCDET_CON38_L |
| #define MT6338_DA_EINT0CMPEN_MON_MASK 0x1 |
| #define MT6338_DA_EINT0CMPEN_MON_SHIFT 2 |
| #define MT6338_DA_EINT0INVEN_MON_ADDR \ |
| MT6338_ACCDET_CON38_L |
| #define MT6338_DA_EINT0INVEN_MON_MASK 0x1 |
| #define MT6338_DA_EINT0INVEN_MON_SHIFT 3 |
| #define MT6338_DA_EINT0CEN_MON_ADDR \ |
| MT6338_ACCDET_CON38_L |
| #define MT6338_DA_EINT0CEN_MON_MASK 0x1 |
| #define MT6338_DA_EINT0CEN_MON_SHIFT 4 |
| #define MT6338_DA_EINT0EN_MON_ADDR \ |
| MT6338_ACCDET_CON38_L |
| #define MT6338_DA_EINT0EN_MON_MASK 0x1 |
| #define MT6338_DA_EINT0EN_MON_SHIFT 5 |
| #define MT6338_DA_EINT1CTURBO_MON_ADDR \ |
| MT6338_ACCDET_CON38_H |
| #define MT6338_DA_EINT1CTURBO_MON_MASK 0x1 |
| #define MT6338_DA_EINT1CTURBO_MON_SHIFT 0 |
| #define MT6338_DA_EINT1CMPMEN_MON_ADDR \ |
| MT6338_ACCDET_CON38_H |
| #define MT6338_DA_EINT1CMPMEN_MON_MASK 0x1 |
| #define MT6338_DA_EINT1CMPMEN_MON_SHIFT 1 |
| #define MT6338_DA_EINT1CMPEN_MON_ADDR \ |
| MT6338_ACCDET_CON38_H |
| #define MT6338_DA_EINT1CMPEN_MON_MASK 0x1 |
| #define MT6338_DA_EINT1CMPEN_MON_SHIFT 2 |
| #define MT6338_DA_EINT1INVEN_MON_ADDR \ |
| MT6338_ACCDET_CON38_H |
| #define MT6338_DA_EINT1INVEN_MON_MASK 0x1 |
| #define MT6338_DA_EINT1INVEN_MON_SHIFT 3 |
| #define MT6338_DA_EINT1CEN_MON_ADDR \ |
| MT6338_ACCDET_CON38_H |
| #define MT6338_DA_EINT1CEN_MON_MASK 0x1 |
| #define MT6338_DA_EINT1CEN_MON_SHIFT 4 |
| #define MT6338_DA_EINT1EN_MON_ADDR \ |
| MT6338_ACCDET_CON38_H |
| #define MT6338_DA_EINT1EN_MON_MASK 0x1 |
| #define MT6338_DA_EINT1EN_MON_SHIFT 5 |
| #define MT6338_ACCDET_EINT0_M_PLUG_IN_COUNT_ADDR \ |
| MT6338_ACCDET_CON39 |
| #define MT6338_ACCDET_EINT0_M_PLUG_IN_COUNT_MASK 0x7 |
| #define MT6338_ACCDET_EINT0_M_PLUG_IN_COUNT_SHIFT 0 |
| #define MT6338_ACCDET_EINT1_M_PLUG_IN_COUNT_ADDR \ |
| MT6338_ACCDET_CON39 |
| #define MT6338_ACCDET_EINT1_M_PLUG_IN_COUNT_MASK 0x7 |
| #define MT6338_ACCDET_EINT1_M_PLUG_IN_COUNT_SHIFT 4 |
| #define MT6338_ACCDET_MON_FLAG_EN_ADDR \ |
| MT6338_ACCDET_CON40 |
| #define MT6338_ACCDET_MON_FLAG_EN_MASK 0x1 |
| #define MT6338_ACCDET_MON_FLAG_EN_SHIFT 0 |
| #define MT6338_ACCDET_MON_FLAG_SEL_ADDR \ |
| MT6338_ACCDET_CON40 |
| #define MT6338_ACCDET_MON_FLAG_SEL_MASK 0xF |
| #define MT6338_ACCDET_MON_FLAG_SEL_SHIFT 4 |
| /*************Register Bit Define*************/ |
| /* AUDENC_ANA_CON16: */ |
| #define RG_AUD_MICBIAS1_LOWP_EN (1<<MT6338_RG_AUDMICBIAS1LOWPEN_SHIFT) |
| /* AUDENC_ANA_CON18: */ |
| #define RG_ACCDET_MODE_ANA11_MODE1 (0x000F) |
| #define RG_ACCDET_MODE_ANA11_MODE2 (0x008F) |
| #define RG_ACCDET_MODE_ANA11_MODE6 (0x008F) |
| |
| /* ------Register_AUXADC_REG Bit Define------ */ |
| /* AUXADC_ADC5: Auxadc CH5 read data */ |
| #define AUXADC_DATA_RDY_CH5 (1<<15) |
| #define AUXADC_DATA_PROCEED_CH5 (0<<15) |
| #define AUXADC_DATA_MASK (0x0FFF) |
| |
| /* AUXADC_RQST0_SET: Auxadc CH5 request, relevant 0x07EC */ |
| #define AUXADC_RQST_CH5_SET (1<<5) |
| /* AUXADC_RQST0_CLR: Auxadc CH5 request, relevant 0x07EC */ |
| #define AUXADC_RQST_CH5_CLR (1<<5) |
| |
| /* -----Register_EFUSE_REG Bit Define-------- */ |
| #define ACCDET_CALI_MASK0 (0xFF) |
| #define ACCDET_CALI_MASK1 (0xFF<<8) |
| #define ACCDET_CALI_MASK2 (0xFF) |
| #define ACCDET_CALI_MASK3 (0xFF<<8) |
| #define ACCDET_CALI_MASK4 (0xFF) |
| /* -----Register_ACCDET_REG Bit Define------- */ |
| #define ACCDET_EINT1_IRQ_CLR_B11 (0x01<<MT6338_ACCDET_EINT1_IRQ_CLR_SHIFT) |
| #define ACCDET_EINT0_IRQ_CLR_B10 (0x01<<MT6338_ACCDET_EINT0_IRQ_CLR_SHIFT) |
| #define ACCDET_EINT_IRQ_CLR_B10_11 (0x03<<MT6338_ACCDET_EINT0_IRQ_CLR_SHIFT) |
| #define ACCDET_IRQ_CLR_B8 (0x01<<MT6338_ACCDET_IRQ_CLR_SHIFT) |
| #define ACCDET_EINT1_IRQ_B3 (0x01<<MT6338_ACCDET_EINT1_IRQ_SHIFT) |
| #define ACCDET_EINT0_IRQ_B2 (0x01<<MT6338_ACCDET_EINT0_IRQ_SHIFT) |
| #define ACCDET_EINT_IRQ_B2_B3 (0x03<<MT6338_ACCDET_EINT0_IRQ_SHIFT) |
| #define ACCDET_IRQ_B0 (0x01<<MT6338_ACCDET_IRQ_SHIFT) |
| /* ACCDET_CON25: RO, accdet FSM state,etc.*/ |
| #define ACCDET_STATE_MEM_IN_OFFSET (MT6338_ACCDET_MEM_IN_SHIFT) |
| #define ACCDET_STATE_AB_MASK (0x03) |
| #define ACCDET_STATE_AB_00 (0x00) |
| #define ACCDET_STATE_AB_01 (0x01) |
| #define ACCDET_STATE_AB_10 (0x02) |
| #define ACCDET_STATE_AB_11 (0x03) |
| /* ACCDET_CON19 */ |
| #define ACCDET_EINT0_STABLE_VAL ((1<<MT6338_ACCDET_DA_STABLE_SHIFT) | \ |
| (1<<MT6338_ACCDET_EINT0_EN_STABLE_SHIFT) | \ |
| (1<<MT6338_ACCDET_EINT0_CMPEN_STABLE_SHIFT) | \ |
| (1<<MT6338_ACCDET_EINT0_CEN_STABLE_SHIFT)) |
| #define ACCDET_EINT1_STABLE_VAL ((1<<MT6338_ACCDET_DA_STABLE_SHIFT) | \ |
| (1<<MT6338_ACCDET_EINT1_EN_STABLE_SHIFT) | \ |
| (1<<MT6338_ACCDET_EINT1_CMPEN_STABLE_SHIFT) | \ |
| (1<<MT6338_ACCDET_EINT1_CEN_STABLE_SHIFT)) |
| #define MT6338_NLE_GAIN_STAGE 8 |
| enum { |
| MT6338_MTKAIF_PROTOCOL_1 = 0, |
| MT6338_MTKAIF_PROTOCOL_2, |
| MT6338_MTKAIF_PROTOCOL_2_CLK_P2, |
| }; |
| |
| enum { |
| MT6338_AIF_1 = 0, /* dl: hp, rcv, hp+lo */ |
| MT6338_AIF_2, /* dl: lo only */ |
| MT6338_AIF_VOW, |
| MT6338_AIF_NUM, |
| }; |
| |
| enum { |
| AUDIO_ANALOG_VOLUME_HSOUTL, |
| AUDIO_ANALOG_VOLUME_HSOUTR, |
| AUDIO_ANALOG_VOLUME_HPOUTL, |
| AUDIO_ANALOG_VOLUME_HPOUTR, |
| AUDIO_ANALOG_VOLUME_LINEOUTL, |
| AUDIO_ANALOG_VOLUME_LINEOUTR, |
| AUDIO_ANALOG_VOLUME_MICAMP1, |
| AUDIO_ANALOG_VOLUME_MICAMP2, |
| AUDIO_ANALOG_VOLUME_MICAMP3, |
| AUDIO_ANALOG_VOLUME_MICAMP4, |
| AUDIO_ANALOG_NEG_VOLUME_MICAMP1, |
| AUDIO_ANALOG_NEG_VOLUME_MICAMP2, |
| AUDIO_ANALOG_NEG_VOLUME_MICAMP3, |
| AUDIO_ANALOG_NEG_VOLUME_MICAMP4, |
| AUDIO_ANALOG_VOLUME_TYPE_MAX |
| }; |
| |
| enum { |
| MUX_MIC_TYPE_0, /* ain0, micbias 0 */ |
| MUX_MIC_TYPE_1, /* ain1, micbias 1 */ |
| MUX_MIC_TYPE_2, /* ain2/3, micbias 2 */ |
| MUX_MIC_TYPE_3, /* ain3/4, micbias 3 */ |
| MUX_PGA_L, |
| MUX_PGA_R, |
| MUX_PGA_3, |
| MUX_PGA_4, |
| MUX_HP_L, |
| MUX_HP_R, |
| MUX_NUM, |
| }; |
| |
| enum { |
| DEVICE_HP, |
| DEVICE_LO, |
| DEVICE_RCV, |
| DEVICE_MIC1, |
| DEVICE_MIC2, |
| DEVICE_NUM |
| }; |
| |
| enum { |
| HP_GAIN_CTL_ZCD = 0, |
| HP_GAIN_CTL_NLE, |
| HP_GAIN_CTL_NUM, |
| }; |
| |
| enum { |
| MT6338_AFE_ETDM_NONE = -1, |
| MT6338_AFE_ETDM_8000HZ = 0, |
| MT6338_AFE_ETDM_11025HZ = 1, |
| MT6338_AFE_ETDM_12000HZ = 2, |
| MT6338_AFE_ETDM_384000HZ = 3, |
| MT6338_AFE_ETDM_16000HZ = 4, |
| MT6338_AFE_ETDM_22050HZ = 5, |
| MT6338_AFE_ETDM_24000HZ = 6, |
| MT6338_AFE_ETDM_32000HZ = 8, |
| MT6338_AFE_ETDM_44100HZ = 9, |
| MT6338_AFE_ETDM_48000HZ = 10, |
| MT6338_AFE_ETDM_88200HZ = 11, |
| MT6338_AFE_ETDM_96000HZ = 12, |
| MT6338_AFE_ETDM_176400HZ = 13, |
| MT6338_AFE_ETDM_192000HZ = 14, |
| }; |
| enum { |
| MT6338_ADDA_NONE = -1, |
| MT6338_ADDA_8000HZ = 0x0, |
| MT6338_ADDA_12000HZ = 0x1, |
| MT6338_ADDA_16000HZ = 0x2, |
| MT6338_ADDA_24000HZ = 0x3, |
| MT6338_ADDA_32000HZ = 0x4, |
| MT6338_ADDA_48000HZ = 0x5, |
| MT6338_ADDA_64000HZ = 0x6, |
| MT6338_ADDA_96000HZ = 0x7, |
| MT6338_ADDA_128000HZ = 0x8, |
| MT6338_ADDA_192000HZ = 0x9, |
| MT6338_ADDA_25600HZ = 0xa, |
| MT6338_ADDA_384000HZ = 0xb, |
| MT6338_ADDA_11000HZ = 0x10, |
| MT6338_ADDA_22000HZ = 0x11, |
| MT6338_ADDA_44000HZ = 0x12, |
| MT6338_ADDA_88000HZ = 0x13, |
| MT6338_ADDA_176000HZ = 0x14, |
| MT6338_ADDA_35200HZ = 0x15, |
| }; |
| |
| enum { |
| MT6338_DLSRC_NONE = -1, |
| MT6338_DLSRC_8000HZ = 0x0, |
| MT6338_DLSRC_11025HZ = 0x1, |
| MT6338_DLSRC_12000HZ = 0x2, |
| MT6338_DLSRC_16000HZ = 0x3, |
| MT6338_DLSRC_22050HZ = 0x4, |
| MT6338_DLSRC_24000HZ = 0x5, |
| MT6338_DLSRC_32000HZ = 0x6, |
| MT6338_DLSRC_44100HZ = 0x7, |
| MT6338_DLSRC_48000HZ = 0x8, |
| MT6338_DLSRC_96000HZ = 0x9, |
| MT6338_DLSRC_192000HZ = 0xa, |
| MT6338_DLSRC_384000HZ = 0xb, |
| }; |
| |
| enum { |
| MT6338_VOICE_NONE = -1, |
| MT6338_VOICE_8000HZ = 0x0, |
| MT6338_VOICE_16000HZ = 0x1, |
| MT6338_VOICE_32000HZ = 0x2, |
| MT6338_VOICE_48000HZ = 0x3, |
| MT6338_VOICE_96000HZ = 0x4, |
| MT6338_VOICE_192000HZ = 0x5, |
| }; |
| |
| /* Supply widget subseq */ |
| enum { |
| /* common */ |
| SUPPLY_SEQ_CLK_BUF, |
| SUPPLY_SEQ_CKTST, |
| SUPPLY_SEQ_LDO_VAUD18, |
| SUPPLY_SEQ_AUD_GLB, |
| SUPPLY_SEQ_AUD_GLB_VOW, |
| SUPPLY_SEQ_PLL_208M, |
| SUPPLY_SEQ_DL_GPIO, |
| SUPPLY_SEQ_UL_GPIO, |
| SUPPLY_SEQ_HP_PULL_DOWN, |
| SUPPLY_SEQ_CLKSQ, |
| SUPPLY_SEQ_ADC_CLKGEN, |
| SUPPLY_SEQ_TOP_CK, |
| SUPPLY_SEQ_TOP_SRAM, |
| SUPPLY_SEQ_TOP_CK_LAST, |
| SUPPLY_SEQ_MIC_BIAS, |
| SUPPLY_SEQ_DCC_CLK, |
| SUPPLY_SEQ_DMIC, |
| SUPPLY_SEQ_AUD_TOP, |
| SUPPLY_SEQ_AUD_TOP_LAST, |
| SUPPLY_SEQ_DL_SDM_FIFO_CLK, |
| SUPPLY_SEQ_DL_SDM, |
| SUPPLY_SEQ_DL_NLE, |
| SUPPLY_SEQ_DL_NCP, |
| SUPPLY_SEQ_AFE, |
| /* playback */ |
| SUPPLY_SEQ_DL_SRC, |
| SUPPLY_SEQ_DL_ESD_RESIST, |
| SUPPLY_SEQ_HP_DAMPING_OFF_RESET_CMFB, |
| SUPPLY_SEQ_HP_MUTE, |
| SUPPLY_SEQ_DL_LDO_REMOTE_SENSE, |
| SUPPLY_SEQ_DL_LDO, |
| SUPPLY_SEQ_DL_NV, |
| SUPPLY_SEQ_HP_ANA_TRIM, |
| SUPPLY_SEQ_DL_IBIST, |
| /* capture */ |
| SUPPLY_SEQ_UL_PGA, |
| SUPPLY_SEQ_UL_ADC, |
| SUPPLY_SEQ_UL_MTKAIF, |
| SUPPLY_SEQ_UL_SRC_DMIC, |
| SUPPLY_SEQ_UL_SRC, |
| #if IS_ENABLED(CONFIG_MTK_VOW_SUPPORT) |
| SUPPLY_SEQ_VOW_DIG_CFG, |
| #endif |
| }; |
| |
| enum { |
| CH_L = 0, |
| CH_R, |
| NUM_CH, |
| }; |
| |
| enum { |
| DRBIAS_4UA = 0, |
| DRBIAS_5UA, |
| DRBIAS_6UA, |
| DRBIAS_7UA, |
| DRBIAS_8UA, |
| DRBIAS_9UA, |
| DRBIAS_10UA, |
| DRBIAS_11UA, |
| }; |
| |
| enum { |
| IBIAS_4UA = 0, |
| IBIAS_5UA, |
| IBIAS_6UA, |
| IBIAS_7UA, |
| }; |
| |
| enum { |
| IBIAS_ZCD_3UA = 0, |
| IBIAS_ZCD_4UA, |
| IBIAS_ZCD_5UA, |
| IBIAS_ZCD_6UA, |
| }; |
| |
| enum { |
| MIC_BIAS_1P7 = 0, |
| MIC_BIAS_1P8, |
| MIC_BIAS_1P9, |
| MIC_BIAS_2P0, |
| MIC_BIAS_2P1, |
| MIC_BIAS_2P5, |
| MIC_BIAS_2P6, |
| MIC_BIAS_2P7, |
| }; |
| |
| enum { |
| DL_GAIN_8DB = 0, |
| DL_GAIN_0DB = 8, |
| DL_GAIN_N_1DB = 9, |
| DL_GAIN_N_10DB = 18, |
| DL_GAIN_N_22DB = 30, |
| DL_GAIN_N_40DB = 0x1f, |
| }; |
| |
| enum { |
| HP_GAIN_9DB = 0, |
| HP_GAIN_6DB = 1, |
| HP_GAIN_3DB = 2, |
| HP_GAIN_0DB = 3, |
| }; |
| |
| enum { |
| MIC_TYPE_MUX_IDLE = 0, |
| MIC_TYPE_MUX_ACC, |
| MIC_TYPE_MUX_DMIC, |
| MIC_TYPE_MUX_DCC, |
| MIC_TYPE_MUX_DCC_ECM_DIFF, |
| MIC_TYPE_MUX_DCC_ECM_SINGLE, |
| }; |
| |
| enum { |
| MIC_INDEX_IDLE = 0, |
| MIC_INDEX_MAIN, |
| MIC_INDEX_REF, |
| MIC_INDEX_THIRD, |
| MIC_INDEX_HEADSET, |
| }; |
| |
| enum { |
| LO_MUX_OPEN = 0, |
| LO_MUX_L_DAC, |
| LO_MUX_3RD_DAC, |
| LO_MUX_TEST_MODE, |
| LO_MUX_MASK = 0x3, |
| }; |
| |
| enum { |
| HP_MUX_OPEN = 0, |
| HP_MUX_HPSPK, |
| HP_MUX_HP, |
| HP_MUX_TEST_MODE, |
| HP_MUX_HP_IMPEDANCE, |
| HP_MUX_MASK = 0x7, |
| }; |
| |
| /* Test mode */ |
| enum { |
| HP_MUX_TEST = 0, |
| HP_MUX_HS, |
| HP_MUX_LOL = 0x2, |
| }; |
| |
| enum { |
| RCV_MUX_OPEN = 0, |
| RCV_MUX_MUTE, |
| RCV_MUX_VOICE_PLAYBACK, |
| RCV_MUX_TEST_MODE, |
| RCV_MUX_MASK = 0x3, |
| }; |
| |
| enum { |
| PGA_MUX_AIN0 = 0, |
| PGA_MUX_AIN1, |
| PGA_MUX_AIN2, |
| PGA_MUX_NONE, |
| }; |
| |
| enum { |
| PGA_3_MUX_AIN0 = 0, |
| PGA_3_MUX_AIN2, |
| PGA_3_MUX_AIN3, |
| PGA_3_MUX_AIN5, |
| }; |
| |
| enum { |
| PGA_4_MUX_AIN2 = 0, |
| PGA_4_MUX_AIN3, |
| PGA_4_MUX_AIN4, |
| PGA_4_MUX_AIN6, |
| }; |
| |
| enum { |
| UL_SRC_MUX_AMIC = 0, |
| UL_SRC_MUX_DMIC, |
| }; |
| |
| enum { |
| MISO_MUX_UL1_CH1 = 0, |
| MISO_MUX_UL1_CH2, |
| MISO_MUX_UL2_CH1, |
| MISO_MUX_UL2_CH2, |
| }; |
| |
| enum { |
| VOW_AMIC_MUX_ADC_DATA_0 = 0, |
| VOW_AMIC_MUX_ADC_DATA_1, |
| VOW_AMIC_MUX_ADC_DATA_2, |
| VOW_AMIC_MUX_ADC_DATA_3 |
| }; |
| |
| enum { |
| DMIC_MUX_DMIC_DATA0 = 0, |
| DMIC_MUX_DMIC_DATA1, |
| DMIC_MUX_DMIC_DATA2, |
| DMIC_MUX_DMIC_DATA3, |
| }; |
| |
| enum { |
| VOW_PBUF_MUX_CH_0 = 0, |
| VOW_PBUF_MUX_CH_1, |
| VOW_PBUF_MUX_CH_2, |
| VOW_PBUF_MUX_CH_3 |
| }; |
| |
| enum { |
| ADC_MUX_IDLE = 0, |
| ADC_MUX_AIN0, |
| ADC_MUX_PREAMPLIFIER, |
| ADC_MUX_IDLE1, |
| }; |
| |
| enum { |
| TRIM_BUF_MUX_OPEN = 0, |
| TRIM_BUF_MUX_HPL, |
| TRIM_BUF_MUX_HPR, |
| TRIM_BUF_MUX_HSP, |
| TRIM_BUF_MUX_HSN, |
| TRIM_BUF_MUX_LOLP, |
| TRIM_BUF_MUX_LOLN, |
| TRIM_BUF_MUX_AU_REFN, |
| TRIM_BUF_MUX_AVSS32, |
| TRIM_BUF_MUX_UNUSED, |
| }; |
| |
| enum { |
| TRIM_BUF_GAIN_0DB = 0, |
| TRIM_BUF_GAIN_6DB, |
| TRIM_BUF_GAIN_12DB, |
| TRIM_BUF_GAIN_18DB, |
| }; |
| |
| enum { |
| TRIM_STEP0 = 0, |
| TRIM_STEP1, |
| TRIM_STEP2, |
| TRIM_STEP3, |
| TRIM_STEP_NUM, |
| }; |
| |
| enum { |
| AUXADC_AVG_1 = 0, |
| AUXADC_AVG_4, |
| AUXADC_AVG_8, |
| AUXADC_AVG_16, |
| AUXADC_AVG_32, |
| AUXADC_AVG_64, |
| AUXADC_AVG_128, |
| AUXADC_AVG_256, |
| }; |
| |
| enum { |
| MT6338_DL_GAIN_MUTE = 0, |
| MT6338_DL_GAIN_NORMAL = 0xf74f, |
| /* SA suggest apply -0.3db to audio/speech path */ |
| }; |
| struct dc_trim_data { |
| bool calibrated; |
| int mic_vinp_mv; |
| }; |
| |
| struct hp_trim_data { |
| unsigned int hp_trim_l; |
| unsigned int hp_trim_r; |
| unsigned int hp_fine_trim_l; |
| unsigned int hp_fine_trim_r; |
| }; |
| |
| struct nle_trim_data { |
| int L_LN[MT6338_NLE_GAIN_STAGE]; |
| int R_LN[MT6338_NLE_GAIN_STAGE]; |
| int L_GS[MT6338_NLE_GAIN_STAGE]; |
| int R_GS[MT6338_NLE_GAIN_STAGE]; |
| }; |
| |
| struct mt6338_vow_periodic_on_off_data { |
| unsigned long long pga_on; |
| unsigned long long precg_on; |
| unsigned long long adc_on; |
| unsigned long long micbias0_on; |
| unsigned long long micbias1_on; |
| unsigned long long dcxo_on; |
| unsigned long long audglb_on; |
| unsigned long long vow_on; |
| unsigned long long pga_off; |
| unsigned long long precg_off; |
| unsigned long long adc_off; |
| unsigned long long micbias0_off; |
| unsigned long long micbias1_off; |
| unsigned long long dcxo_off; |
| unsigned long long audglb_off; |
| unsigned long long vow_off; |
| }; |
| |
| struct mt6338_codec_ops { |
| int (*enable_dc_compensation)(bool enable); |
| int (*set_lch_dc_compensation)(int value); |
| int (*set_rch_dc_compensation)(int value); |
| int (*adda_dl_gain_control)(bool mute); |
| }; |
| |
| struct mt6338_priv { |
| struct device *dev; |
| struct regmap *regmap; |
| struct nvmem_device *efuse; |
| unsigned int dl_rate[MT6338_AIF_NUM]; |
| unsigned int ul_rate[MT6338_AIF_NUM]; |
| int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX]; |
| unsigned int mux_select[MUX_NUM]; |
| int dev_counter[DEVICE_NUM]; |
| int hp_gain_ctl; |
| int hp_hifi_mode; |
| int hp_plugged; |
| int mtkaif_protocol; |
| int dmic_one_wire_mode; |
| int mic_hifi_mode; |
| int mic_ulcf_en; |
| unsigned int vd105; |
| |
| /* hw version */ |
| int hw_ver; |
| |
| /* dc trim */ |
| struct dc_trim_data dc_trim; |
| struct hp_trim_data hp_trim_3_pole; |
| struct hp_trim_data hp_trim_4_pole; |
| struct iio_channel *hpofs_cal_auxadc; |
| |
| /* headphone impedence */ |
| struct nvmem_device *hp_efuse; |
| int hp_impedance; |
| int hp_current_calibrate_val; |
| struct mt6338_codec_ops ops; |
| |
| /* NLE */ |
| struct nle_trim_data nle_trim; |
| |
| /* debugfs */ |
| struct dentry *debugfs; |
| |
| /* vow control */ |
| int vow_enable; |
| int vow_setup; |
| int reg_afe_vow_vad_cfg0; |
| int reg_afe_vow_vad_cfg1; |
| int reg_afe_vow_vad_cfg2; |
| int reg_afe_vow_vad_cfg3; |
| int reg_afe_vow_vad_cfg4; |
| int reg_afe_vow_vad_cfg5; |
| int reg_afe_vow_periodic; |
| unsigned int vow_channel; |
| unsigned int vow_pbuf_active_bit; |
| struct mt6338_vow_periodic_on_off_data vow_periodic_param; |
| /* vow dmic low power mode, 1: enable, 0: disable */ |
| int vow_dmic_lp; |
| int vow_single_mic_select; |
| }; |
| |
| #define MT_SOC_ENUM_EXT_ID(xname, xenum, xhandler_get, xhandler_put, id) \ |
| { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .device = id,\ |
| .info = snd_soc_info_enum_double, \ |
| .get = xhandler_get, .put = xhandler_put, \ |
| .private_value = (unsigned long)&xenum } |
| |
| |
| /* dl bias */ |
| #define IBIAS_MASK 0x3 |
| #define IBIAS_HP_SFT (RG_AUDBIASADJ_1_VAUDP18_SFT + 0) |
| #define IBIAS_HP_MASK_SFT (IBIAS_MASK << IBIAS_HP_SFT) |
| #define IBIAS_HS_SFT (RG_AUDBIASADJ_1_VAUDP18_SFT + 2) |
| #define IBIAS_HS_MASK_SFT (IBIAS_MASK << IBIAS_HS_SFT) |
| #define IBIAS_LO_SFT (RG_AUDBIASADJ_1_VAUDP18_SFT + 4) |
| #define IBIAS_LO_MASK_SFT (IBIAS_MASK << IBIAS_LO_SFT) |
| #define IBIAS_ZCD_SFT (RG_AUDBIASADJ_1_VAUDP18_SFT + 6) |
| #define IBIAS_ZCD_MASK_SFT (IBIAS_MASK << IBIAS_ZCD_SFT) |
| |
| /* dl pga gain */ |
| #define DL_GAIN_N_10DB_REG (DL_GAIN_N_10DB) |
| #define DL_GAIN_N_22DB_REG (DL_GAIN_N_22DB) |
| #define DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB) |
| #define DL_GAIN_REG_MASK 0x0f9f |
| |
| /* mic type */ |
| |
| #define IS_DCC_BASE(x) (x == MIC_TYPE_MUX_DCC || \ |
| x == MIC_TYPE_MUX_DCC_ECM_DIFF || \ |
| x == MIC_TYPE_MUX_DCC_ECM_SINGLE) |
| |
| #define IS_AMIC_BASE(x) (x == MIC_TYPE_MUX_ACC || IS_DCC_BASE(x)) |
| |
| /* reg idx for -40dB */ |
| #define PGA_MINUS_40_DB_REG_VAL 0x1f |
| #define HP_PGA_MINUS_40_DB_REG_VAL 0x3f |
| |
| /* dc trim */ |
| #define TRIM_TIMES 26 |
| #define TRIM_DISCARD_NUM 3 |
| #define TRIM_USEFUL_NUM (TRIM_TIMES - (TRIM_DISCARD_NUM * 2)) |
| |
| /* headphone impedance detection */ |
| #define PARALLEL_OHM 0 |
| |
| /* codec name */ |
| #define CODEC_MT6338_NAME "mtk-codec-mt6338" |
| #define DEVICE_MT6338_NAME "mt6338-sound" |
| |
| int mt6338_set_codec_ops(struct snd_soc_component *cmpnt, |
| struct mt6338_codec_ops *ops); |
| int mt6338_set_mtkaif_protocol(struct snd_soc_component *cmpnt, |
| int mtkaif_protocol); |
| void mt6338_mtkaif_calibration_enable(struct snd_soc_component *cmpnt); |
| void mt6338_mtkaif_calibration_disable(struct snd_soc_component *cmpnt); |
| void mt6338_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt, |
| int phase_1, int phase_2, int phase_3); |
| extern bool mt6338_probe_done; |
| |
| #endif/* end _MT6338_H_ */ |
