| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* |
| * Copyright (c) 2020 MediaTek Inc. |
| * Author: Chao Hao <chao.hao@mediatek.com> |
| */ |
| |
| #ifndef _DTS_IOMMU_PORT_MT6983_H_ |
| #define _DTS_IOMMU_PORT_MT6983_H_ |
| |
| #include <dt-bindings/memory/mtk-memory-port.h> |
| |
| /* table id must be the same as mtk_iommu.h */ |
| #define MM_TAB (0) |
| #define APU_TAB (1) |
| |
| /* iova region definition */ |
| #define NORMAL_DOM (0) |
| #define VDEC_DOM (1) |
| #define LK_RESV_DOM (2) |
| #define CCU0_DOM (3) |
| #define CCU1_DOM (4) |
| #define VDO_REGION1 (5) |
| #define VDO_REGION2 (6) |
| #define VDO_REGION3 (7) |
| #define VDO_REGION4 (8) |
| |
| #define APU_DATA_DOM (0) |
| #define APU_SEC_DOM (1) |
| #define APU_CODE_DOM (2) |
| |
| |
| /* larb0 */ |
| #define M4U_PORT_L0_DISP_POSTMASK0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 0) |
| #define M4U_PORT_L0_DMDP_RDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 1) |
| #define M4U_PORT_L0_DISP_OVL0_HDR MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 2) |
| #define M4U_PORT_L0_DISP_OVL0_2L_HDR MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 3) |
| #define M4U_PORT_L0_DISP_OVL1_2L_HDR MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 4) |
| #define M4U_PORT_L0_DISP_OVL0_2L_NWCG_HDR MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 5) |
| #define M4U_PORT_L0_DISP_OVL1_2L_NWCG_HDR MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 6) |
| #define M4U_PORT_L0_DISP_OVL0_0_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 7) |
| #define M4U_PORT_L0_DISP_OVL0_2L_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 8) |
| #define M4U_PORT_L0_DISP_OVL1_2L_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 9) |
| #define M4U_PORT_L0_DISP_OVL0_2L_NWCG_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 10) |
| #define M4U_PORT_L0_DISP_OVL1_2L_NWCG_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 11) |
| #define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 12) |
| #define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 13) |
| #define M4U_PORT_L0_DISP_UFBC_WDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 14) |
| #define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 0, 15) |
| |
| /* larb1 */ |
| #define M4U_PORT_L1_DISP_OVL0_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 1, 0) |
| #define M4U_PORT_L1_DISP_OVL0_2L_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 1, 1) |
| #define M4U_PORT_L1_DISP_OVL1_2L_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 1, 2) |
| #define M4U_PORT_L1_DISP_OVL0_2L_NWCG_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 1, 3) |
| #define M4U_PORT_L1_DISP_OVL1_2L_NWCG_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 1, 4) |
| #define M4U_PORT_L1_DISP_RDMA1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 1, 5) |
| #define M4U_PORT_L1_DISP_WDMA1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 1, 6) |
| #define M4U_PORT_L1_DISP_FAKE1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 1, 7) |
| |
| /* larb2 */ |
| #define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 2, 0) |
| #define M4U_PORT_L2_MDP_RDMA2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 2, 1) |
| #define M4U_PORT_L2_MDP_WROT0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 2, 2) |
| #define M4U_PORT_L2_MDP_WROT2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 2, 3) |
| #define M4U_PORT_L2_MDP_DISP_FAKE0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 2, 4) |
| #define M4U_PORT_L2_MDP_FILMGRAIN0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 2, 5) |
| #define M4U_PORT_L2_MDP_FILMGRAIN2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 2, 6) |
| #define M4U_PORT_L2_MDP_WDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 2, 7) |
| #define M4U_PORT_L2_MDP_WDMA2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 2, 8) |
| |
| /* larb3 */ |
| #define M4U_PORT_L3_MDP_RDMA1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 3, 0) |
| #define M4U_PORT_L3_MDP_RDMA3 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 3, 1) |
| #define M4U_PORT_L3_MDP_WROT1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 3, 2) |
| #define M4U_PORT_L3_MDP_WROT3 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 3, 3) |
| #define M4U_PORT_L3_MDP_DISP_FAKE1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 3, 4) |
| #define M4U_PORT_L3_MDP_FILMGRAIN1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 3, 5) |
| #define M4U_PORT_L3_MDP_FILMGRAIN3 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 3, 6) |
| #define M4U_PORT_L3_MDP_WDMA1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 3, 7) |
| #define M4U_PORT_L3_MDP_WDMA3 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 3, 8) |
| |
| /* larb4 */ |
| #define M4U_PORT_L4_VDEC_MC_EXT MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 4, 0) |
| #define M4U_PORT_L4_VDEC_UFO_EXT MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 4, 1) |
| #define M4U_PORT_L4_VDEC_PP_EXT MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 4, 2) |
| #define M4U_PORT_L4_VDEC_PRED_RD_EXT MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 4, 3) |
| #define M4U_PORT_L4_VDEC_PRED_WR_EXT MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 4, 4) |
| #define M4U_PORT_L4_VDEC_PPWRAP_EXT MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 4, 5) |
| #define M4U_PORT_L4_VDEC_TILE_EXT MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 4, 6) |
| #define M4U_PORT_L4_VDEC_VLD_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_DOM, 4, 7) |
| #define M4U_PORT_L4_VDEC_VLD2_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_DOM, 4, 8) |
| #define M4U_PORT_L4_VDEC_AVC_MV_EXT MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 4, 9) |
| #define M4U_PORT_L4_VDEC_UFO_EXT_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 4, 10) |
| |
| /* larb5 */ |
| #define M4U_PORT_L5_VDEC_LAT0_VLD_EXT MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 5, 0) |
| #define M4U_PORT_L5_VDEC_LAT0_VLD2_EXT MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 5, 1) |
| #define M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 5, 2) |
| #define M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 5, 3) |
| #define M4U_PORT_L5_VDEC_LAT0_TILE_EXT MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 5, 4) |
| #define M4U_PORT_L5_VDEC_LAT0_WDMA_EXT MTK_M4U_PORT_ID(MM_TAB, VDEC_DOM, 5, 5) |
| #define M4U_PORT_L5_VDEC_UFO_ENC_EXT MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 5, 6) |
| #define M4U_PORT_L5_VDEC_UFO_ENC_EXT_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 5, 7) |
| #define M4U_PORT_L5_VDEC_MC_EXT_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 5, 8) |
| |
| /* larb6 */ |
| #define M4U_PORT_L6_VDEC_MINI_MDP_R0_EXT MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 6, 0) |
| #define M4U_PORT_L6_VDEC_MINI_MDP_W0_EXT MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 6, 1) |
| #define M4U_PORT_L6_VDEC_MINI_MDP_R1_EXT MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 6, 2) |
| #define M4U_PORT_L6_VDEC_MINI_MDP_W1_EXT MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 6, 3) |
| |
| /* larb7 */ |
| #define M4U_PORT_L7_VENC_RCPU_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 0) |
| #define M4U_PORT_L7_VENC_REC_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 1) |
| #define M4U_PORT_L7_VENC_BSDMA_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 2) |
| #define M4U_PORT_L7_VENC_SV_COMV_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 3) |
| #define M4U_PORT_L7_VENC_RD_COMV_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 4) |
| #define M4U_PORT_L7_VENC_NBM_RDMA_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 5) |
| #define M4U_PORT_L7_VENC_NBM_RDMA_LITE_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 6) |
| #define M4U_PORT_L7_JPGENC_Y_RDMA_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 7) |
| #define M4U_PORT_L7_JPGENC_C_RDMA_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 8) |
| #define M4U_PORT_L7_JPGENC_Q_TABLE_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 9) |
| #define M4U_PORT_L7_VENC_SUB_W_LUMA_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 10) |
| #define M4U_PORT_L7_VENC_FCS_NBM_RDMA_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 11) |
| #define M4U_PORT_L7_VENC_EC_WPP_BSDMA_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 12) |
| #define M4U_PORT_L7_VENC_EC_WPP_RDMA_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 13) |
| #define M4U_PORT_L7_VENC_DB_SYSRAM_WDMA_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 14) |
| #define M4U_PORT_L7_VENC_DB_SYSRAM_RDMA_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 15) |
| #define M4U_PORT_L7_JPGENC_BSDMA_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 16) |
| #define M4U_PORT_L7_JPGDEC_WDMA_0_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 17) |
| #define M4U_PORT_L7_JPGDEC_BSDMA_0_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 18) |
| #define M4U_PORT_L7_VENC_NBM_WDMA_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 19) |
| #define M4U_PORT_L7_VENC_NBM_WDMA_LITE_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 20) |
| #define M4U_PORT_L7_VENC_CUR_LUMA_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 21) |
| #define M4U_PORT_L7_VENC_CUR_CHROMA_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 22) |
| #define M4U_PORT_L7_VENC_REF_LUMA_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 23) |
| #define M4U_PORT_L7_VENC_REF_CHROMA_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 24) |
| #define M4U_PORT_L7_VENC_SUB_R_LUMA_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 25) |
| #define M4U_PORT_L7_VENC_FCS_NBM_WDMA_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 26) |
| #define M4U_PORT_L7_JPGDEC_WDMA_1_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 27) |
| #define M4U_PORT_L7_JPGDEC_BSDMA_1_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 28) |
| #define M4U_PORT_L7_JPGDEC_HUFF_OFFSET_1_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 29) |
| #define M4U_PORT_L7_JPGDEC_HUFF_OFFSET_0_DISP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 7, 30) |
| |
| /* larb8 */ |
| #define M4U_PORT_L8_VENC_RCPU_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 0) |
| #define M4U_PORT_L8_VENC_REC_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 1) |
| #define M4U_PORT_L8_VENC_BSDMA_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 2) |
| #define M4U_PORT_L8_VENC_SV_COMV_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 3) |
| #define M4U_PORT_L8_VENC_RD_COMV_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 4) |
| #define M4U_PORT_L8_VENC_NBM_RDMA_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 5) |
| #define M4U_PORT_L8_VENC_NBM_RDMA_LITE_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 6) |
| #define M4U_PORT_L8_JPGENC_Y_RDMA_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 7) |
| #define M4U_PORT_L8_JPGENC_C_RDMA_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 8) |
| #define M4U_PORT_L8_JPGENC_Q_TABLE_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 9) |
| #define M4U_PORT_L8_VENC_SUB_W_LUMA_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 10) |
| #define M4U_PORT_L8_VENC_FCS_NBM_RDMA_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 11) |
| #define M4U_PORT_L8_VENC_EC_WPP_BSDMA_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 12) |
| #define M4U_PORT_L8_VENC_EC_WPP_RDMA_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 13) |
| #define M4U_PORT_L8_VENC_DB_SYSRAM_WDMA_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 14) |
| #define M4U_PORT_L8_VENC_DB_SYSRAM_RDMA_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 15) |
| #define M4U_PORT_L8_JPGENC_BSDMA_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 16) |
| #define M4U_PORT_L8_JPGDEC_WDMA_0_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 17) |
| #define M4U_PORT_L8_JPGDEC_BSDMA_0_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 18) |
| #define M4U_PORT_L8_VENC_NBM_WDMA_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 19) |
| #define M4U_PORT_L8_VENC_NBM_WDMA_LITE_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 20) |
| #define M4U_PORT_L8_VENC_CUR_LUMA_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 21) |
| #define M4U_PORT_L8_VENC_CUR_CHROMA_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 22) |
| #define M4U_PORT_L8_VENC_REF_LUMA_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 23) |
| #define M4U_PORT_L8_VENC_REF_CHROMA_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 24) |
| #define M4U_PORT_L8_VENC_SUB_R_LUMA_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 25) |
| #define M4U_PORT_L8_VENC_FCS_NBM_WDMA_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 26) |
| #define M4U_PORT_L8_JPGDEC_WDMA_1_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 27) |
| #define M4U_PORT_L8_JPGDEC_BSDMA_1_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 28) |
| #define M4U_PORT_L8_JPGDEC_HUFF_OFFSET_1_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 29) |
| #define M4U_PORT_L8_JPGDEC_HUFF_OFFSET_0_MDP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 8, 30) |
| |
| /* larb9 */ |
| #define M4U_PORT_L9_IMG1_IMGI_T1_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 0) |
| #define M4U_PORT_L9_IMG1_UFDI_T1_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 1) |
| #define M4U_PORT_L9_IMG1_IMGBI_T1_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 2) |
| #define M4U_PORT_L9_IMG1_IMGCI_T1_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 3) |
| #define M4U_PORT_L9_IMG1_SMTI_T1_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 4) |
| #define M4U_PORT_L9_IMG1_SMTI_T4_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 5) |
| #define M4U_PORT_L9_IMG1_TNCSTI_T1_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 6) |
| #define M4U_PORT_L9_IMG1_TNCSTI_T4_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 7) |
| #define M4U_PORT_L9_IMG1_YUVO_T1_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 8) |
| #define M4U_PORT_L9_IMG1_YUVBO_T1_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 9) |
| #define M4U_PORT_L9_IMG1_YUVCO_T1_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 10) |
| #define M4U_PORT_L9_IMG1_TIMGO_T1_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 11) |
| #define M4U_PORT_L9_IMG1_YUVO_T2_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 12) |
| #define M4U_PORT_L9_IMG1_YUVO_T5_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 13) |
| #define M4U_PORT_L9_IMG1_IMGI_T1_B MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 14) |
| #define M4U_PORT_L9_IMG1_IMGBI_T1_B MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 15) |
| #define M4U_PORT_L9_IMG1_IMGCI_T1_B MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 16) |
| #define M4U_PORT_L9_IMG1_SMTI_T4_B MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 17) |
| #define M4U_PORT_L9_IMG1_TNCSO_T1_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 18) |
| #define M4U_PORT_L9_IMG1_SMTO_T1_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 19) |
| #define M4U_PORT_L9_IMG1_SMTO_T4_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 20) |
| #define M4U_PORT_L9_IMG1_TNCSTO_T1_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 21) |
| #define M4U_PORT_L9_IMG1_YUVO_T2_B MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 22) |
| #define M4U_PORT_L9_IMG1_YUVO_T5_B MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 23) |
| #define M4U_PORT_L9_IMG1_SMTO_T4_B MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 9, 24) |
| |
| /* larb10 */ |
| #define M4U_PORT_L10_IMG2_IMGI_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 0) |
| #define M4U_PORT_L10_IMG2_IMGBI_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 1) |
| #define M4U_PORT_L10_IMG2_IMGCI_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 2) |
| #define M4U_PORT_L10_IMG2_IMGDI_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 3) |
| #define M4U_PORT_L10_IMG2_DEPI_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 4) |
| #define M4U_PORT_L10_IMG2_DMGI_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 5) |
| #define M4U_PORT_L10_IMG2_SMTI_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 6) |
| #define M4U_PORT_L10_IMG2_RECI_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 7) |
| #define M4U_PORT_L10_IMG2_RECI_D1_N MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 8) |
| #define M4U_PORT_L10_IMG2_TNRWI_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 9) |
| #define M4U_PORT_L10_IMG2_TNRCI_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 10) |
| #define M4U_PORT_L10_IMG2_TNRCI_D1_N MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 11) |
| #define M4U_PORT_L10_IMG2_IMG4O_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 12) |
| #define M4U_PORT_L10_IMG2_IMG4BO_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 13) |
| #define M4U_PORT_L10_IMG2_SMTI_D8 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 14) |
| #define M4U_PORT_L10_IMG2_SMTO_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 15) |
| #define M4U_PORT_L10_IMG2_TNRMO_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 16) |
| #define M4U_PORT_L10_IMG2_TNRMO_D1_N MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 17) |
| #define M4U_PORT_L10_IMG2_SMTO_D8 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 18) |
| #define M4U_PORT_L10_IMG2_DBGO_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 10, 19) |
| |
| /* Larb11 */ |
| #define M4U_PORT_L11_IMG2_WPE_RDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 0) |
| #define M4U_PORT_L11_IMG2_WPE_RDMA1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 1) |
| #define M4U_PORT_L11_IMG2_WPE_RDMA_4P0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 2) |
| #define M4U_PORT_L11_IMG2_WPE_RDMA_4P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 3) |
| #define M4U_PORT_L11_IMG2_WPE_CQ0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 4) |
| #define M4U_PORT_L11_IMG2_WPE_CQ1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 5) |
| #define M4U_PORT_L11_IMG2_PIMGI_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 6) |
| #define M4U_PORT_L11_IMG2_PIMGBI_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 7) |
| #define M4U_PORT_L11_IMG2_PIMGCI_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 8) |
| #define M4U_PORT_L11_IMG2_IMGI_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 9) |
| #define M4U_PORT_L11_IMG2_IMGBI_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 10) |
| #define M4U_PORT_L11_IMG2_IMGCI_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 11) |
| #define M4U_PORT_L11_IMG2_SMTI_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 12) |
| #define M4U_PORT_L11_IMG2_SMTI_T4_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 13) |
| #define M4U_PORT_L11_IMG2_SMTI_T6_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 14) |
| #define M4U_PORT_L11_IMG2_YUVO_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 15) |
| #define M4U_PORT_L11_IMG2_YUVBO_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 16) |
| #define M4U_PORT_L11_IMG2_YUVCO_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 17) |
| #define M4U_PORT_L11_IMG2_WPE_WDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 18) |
| #define M4U_PORT_L11_IMG2_WPE_WDMA_4P0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 19) |
| #define M4U_PORT_L11_IMG2_WROT_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 20) |
| #define M4U_PORT_L11_IMG2_TCCSO_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 21) |
| #define M4U_PORT_L11_IMG2_TCCSI_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 22) |
| #define M4U_PORT_L11_IMG2_TIMGO_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 23) |
| #define M4U_PORT_L11_IMG2_YUVO_T2_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 24) |
| #define M4U_PORT_L11_IMG2_YUVO_T5_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 25) |
| #define M4U_PORT_L11_IMG2_SMTO_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 26) |
| #define M4U_PORT_L11_IMG2_SMTO_T4_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 27) |
| #define M4U_PORT_L11_IMG2_SMTO_T6_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 28) |
| #define M4U_PORT_L11_IMG2_DBGO_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 11, 29) |
| |
| /* larb12 */ |
| #define M4U_PORT_L12_IPE_FDVT_RDA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 12, 0) |
| #define M4U_PORT_L12_IPE_FDVT_RDB0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 12, 1) |
| #define M4U_PORT_L12_IPE_FDVT_WRA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 12, 2) |
| #define M4U_PORT_L12_IPE_FDVT_WR0B MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 12, 3) |
| #define M4U_PORT_L12_IPE_ME_RDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 12, 4) |
| #define M4U_PORT_L12_IPE_ME_WDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 12, 5) |
| #define M4U_PORT_L12_IPE_DVS_RDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 12, 6) |
| #define M4U_PORT_L12_IPE_DVS_WDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 12, 7) |
| #define M4U_PORT_L12_IPE_DVP_RDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 12, 8) |
| #define M4U_PORT_L12_IPE_DVP_WDMA MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 12, 9) |
| #define M4U_PORT_L12_IPE_FDVT_2ND_RDA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 12, 10) |
| #define M4U_PORT_L12_IPE_FDVT_2ND_RDB0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 12, 11) |
| #define M4U_PORT_L12_IPE_FDVT_2ND_WRA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 12, 12) |
| #define M4U_PORT_L12_IPE_FDVT_2ND_WRB0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 12, 13) |
| #define M4U_PORT_L12_IPE_DHZEI_E1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 12, 14) |
| #define M4U_PORT_L12_IPE_DHZEO_E1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 12, 15) |
| |
| /* larb13 */ |
| #define M4U_PORT_L13_CAM1_CAMSV_CQI_E1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 0) |
| #define M4U_PORT_L13_CAM1_CAMSV_CQI_E2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 1) |
| #define M4U_PORT_L13_CAM1_GCAMSV_A_IMGO_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 2) |
| #define M4U_PORT_L13_CAM1_GCAMSV_C_IMGO_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 3) |
| #define M4U_PORT_L13_CAM1_GCAMSV_A_IMGO_2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 4) |
| #define M4U_PORT_L13_CAM1_GCAMSV_C_IMGO_2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 5) |
| #define M4U_PORT_L13_CAM1_PDAI_A_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 6) |
| #define M4U_PORT_L13_CAM1_PDAI_A_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 7) |
| #define M4U_PORT_L13_CAM1_CAMSV_CQI_B_E1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 8) |
| #define M4U_PORT_L13_CAM1_CAMSV_CQI_B_E2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 9) |
| #define M4U_PORT_L13_CAM1_CAMSV_CQI_C_E1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 10) |
| #define M4U_PORT_L13_CAM1_CAMSV_CQI_C_E2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 11) |
| #define M4U_PORT_L13_CAM1_GCAMSV_E_IMGO_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 12) |
| #define M4U_PORT_L13_CAM1_GCAMSV_E_IMGO_2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 13) |
| #define M4U_PORT_L13_CAM1_GCAMSV_A_UFEO_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 14) |
| #define M4U_PORT_L13_CAM1_GCAMSV_C_UFEO_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 15) |
| #define M4U_PORT_L13_CAM1_GCAMSV_A_UFEO_2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 16) |
| #define M4U_PORT_L13_CAM1_GCAMSV_C_UFEO_2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 17) |
| #define M4U_PORT_L13_CAM1_GCAMSV_E_UFEO_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 18) |
| #define M4U_PORT_L13_CAM1_GCAMSV_E_UFEO_2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 19) |
| #define M4U_PORT_L13_CAM1_GCAMSV_G_IMGO_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 20) |
| #define M4U_PORT_L13_CAM1_GCAMSV_G_IMGO_2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 21) |
| #define M4U_PORT_L13_CAM1_PDAO_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 22) |
| #define M4U_PORT_L13_CAM1_PDAO_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 13, 23) |
| |
| /* larb14 */ |
| #define M4U_PORT_L14_CAM1_GCAMSV_B_IMGO_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 0) |
| #define M4U_PORT_L14_CAM1_GCAMSV_B_IMGO_2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 1) |
| #define M4U_PORT_L14_CAM1_SCAMSV_A_IMGO_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 2) |
| #define M4U_PORT_L14_CAM1_SCAMSV_A_IMGO_2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 3) |
| #define M4U_PORT_L14_CAM1_SCAMSV_B_IMGO_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 4) |
| #define M4U_PORT_L14_CAM1_SCAMSV_B_IMGO_2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 5) |
| #define M4U_PORT_L14_CAM1_PDAI_B_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 6) |
| #define M4U_PORT_L14_CAM1_PDAI_B_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 7) |
| #define M4U_PORT_L14_CAM1_GCAMSV_D_IMGO_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 8) |
| #define M4U_PORT_L14_CAM1_GCAMSV_D_IMGO_2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 9) |
| #define M4U_PORT_L14_CAM1_GCAMSV_F_IMGO_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 10) |
| #define M4U_PORT_L14_CAM1_GCAMSV_F_IMGO_2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 11) |
| #define M4U_PORT_L14_CAM1_GCAMSV_H_IMGO_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 12) |
| #define M4U_PORT_L14_CAM1_GCAMSV_H_IMGO_2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 13) |
| #define M4U_PORT_L14_CAM1_GCAMSV_B_UFEO_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 14) |
| #define M4U_PORT_L14_CAM1_GCAMSV_B_UFEO_2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 15) |
| #define M4U_PORT_L14_CAM1_GCAMSV_D_UFEO_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 16) |
| #define M4U_PORT_L14_CAM1_GCAMSV_D_UFEO_2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 17) |
| #define M4U_PORT_L14_CAM1_PDAO_B MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 18) |
| #define M4U_PORT_L14_CAM1_IPUI MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 19) |
| #define M4U_PORT_L14_CAM1_IPUO MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 20) |
| #define M4U_PORT_L14_CAM1_IPU3O MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 21) |
| #define M4U_PORT_L14_CAM1_FAKE MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 14, 22) |
| |
| /* Larb15 */ |
| #define M4U_PORT_L15_IMG2_VIP1_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 0) |
| #define M4U_PORT_L15_IMG2_VIPBI_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 1) |
| #define M4U_PORT_L15_IMG2_SMTI_D6 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 2) |
| #define M4U_PORT_L15_IMG2_TNCSTI_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 3) |
| #define M4U_PORT_L15_IMG2_TNCSTI_D4 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 4) |
| #define M4U_PORT_L15_IMG2_SMTI_D4 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 5) |
| #define M4U_PORT_L15_IMG2_IMG3O_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 6) |
| #define M4U_PORT_L15_IMG2_IMG3BO_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 7) |
| #define M4U_PORT_L15_IMG2_IMG3CO_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 8) |
| #define M4U_PORT_L15_IMG2_IMG2O_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 9) |
| #define M4U_PORT_L15_IMG2_SMTI_D9 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 10) |
| #define M4U_PORT_L15_IMG2_SMTO_D4 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 11) |
| #define M4U_PORT_L15_IMG2_FEO_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 12) |
| #define M4U_PORT_L15_IMG2_TNCSO_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 13) |
| #define M4U_PORT_L15_IMG2_TNCSTO_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 14) |
| #define M4U_PORT_L15_IMG2_SMTO_D6 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 15) |
| #define M4U_PORT_L15_IMG2_SMTO_D9 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 16) |
| #define M4U_PORT_L15_IMG2_TNCO_D1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 17) |
| #define M4U_PORT_L15_IMG2_TNCO_D1_N MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 15, 18) |
| |
| /* larb16 */ |
| #define M4U_PORT_L16_CAM2_IMGP_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 0) |
| #define M4U_PORT_L16_CAM2_CQI_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 1) |
| #define M4U_PORT_L16_CAM2_CQI_R2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 2) |
| #define M4U_PORT_L16_CAM2_BPCI_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 3) |
| #define M4U_PORT_L16_CAM2_LSCI_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 4) |
| #define M4U_PORT_L16_CAM2_RAWI_R2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 5) |
| #define M4U_PORT_L16_CAM2_RAWI_R3 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 6) |
| #define M4U_PORT_L16_CAM2_UFDI_R2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 7) |
| #define M4U_PORT_L16_CAM2_UFDI_R3 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 8) |
| #define M4U_PORT_L16_CAM2_RAWI_R4 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 9) |
| #define M4U_PORT_L16_CAM2_RAWI_R5 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 10) |
| #define M4U_PORT_L16_CAM2_AAI_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 11) |
| #define M4U_PORT_L16_CAM2_UFDI_R5 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 12) |
| #define M4U_PORT_L16_CAM2_FHO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 13) |
| #define M4U_PORT_L16_CAM2_AAO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 14) |
| #define M4U_PORT_L16_CAM2_TSFSO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 15) |
| #define M4U_PORT_L16_CAM2_FLKO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 16, 16) |
| |
| /* larb17 */ |
| #define M4U_PORT_L17_CAM3_YUVO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 17, 0) |
| #define M4U_PORT_L17_CAM3_YUVO_R3 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 17, 1) |
| #define M4U_PORT_L17_CAM3_YUVCO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 17, 2) |
| #define M4U_PORT_L17_CAM3_YUVO_R2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 17, 3) |
| #define M4U_PORT_L17_CAM3_RZH1N2TO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 17, 4) |
| #define M4U_PORT_L17_CAM3_DRZS4NO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 17, 5) |
| #define M4U_PORT_L17_CAM3_TNCSO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 17, 6) |
| |
| /* larb18 */ |
| #define M4U_PORT_L18_IMGADL0_CQI_E1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 18, 0) |
| #define M4U_PORT_L18_IMGADL0_CQI_E2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 18, 1) |
| #define M4U_PORT_L18_IMGADL0_IPUI_E1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 18, 2) |
| #define M4U_PORT_L18_IMGADL0_IPUO_E1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 18, 3) |
| #define M4U_PORT_L18_IMGADL1_CQI_E1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 18, 4) |
| #define M4U_PORT_L18_IMGADL1_CQI_E2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 18, 5) |
| #define M4U_PORT_L18_IMGADL1_IPUI_E1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 18, 6) |
| #define M4U_PORT_L18_IMGADL1_IPUO_E1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 18, 7) |
| |
| /* larb19 */ |
| #define M4U_PORT_L19_CAM_CCUI MTK_M4U_PORT_ID(MM_TAB, CCU0_DOM, 19, 0) |
| #define M4U_PORT_L19_CAM_CCUO MTK_M4U_PORT_ID(MM_TAB, CCU0_DOM, 19, 1) |
| #define M4U_PORT_L19_CAM_CCUI2 MTK_M4U_PORT_ID(MM_TAB, CCU1_DOM, 19, 2) |
| #define M4U_PORT_L19_CAM_CCUO2 MTK_M4U_PORT_ID(MM_TAB, CCU1_DOM, 19, 3) |
| |
| /* larb20 */ |
| #define M4U_PORT_L20_DISP_POSTMASK0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 20, 0) |
| #define M4U_PORT_L20_DMDP_RDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 20, 1) |
| #define M4U_PORT_L20_DISP_OVL0_HDR MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 20, 2) |
| #define M4U_PORT_L20_DISP_OVL0_2L_HDR MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 20, 3) |
| #define M4U_PORT_L20_DISP_OVL1_2L_HDR MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 20, 4) |
| #define M4U_PORT_L20_DISP_OVL0_2L_NWCG_HDR MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 20, 5) |
| #define M4U_PORT_L20_DISP_OVL1_2L_NWCG_HDR MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 20, 6) |
| #define M4U_PORT_L20_DISP_OVL0_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 20, 7) |
| #define M4U_PORT_L20_DISP_OVL0_2L_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 20, 8) |
| #define M4U_PORT_L20_DISP_OVL1_2L_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 20, 9) |
| #define M4U_PORT_L20_DISP_OVL0_2L_NWCG_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 20, 10) |
| #define M4U_PORT_L20_DISP_OVL1_2L_NWCG_0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 20, 11) |
| #define M4U_PORT_L20_DISP_RDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 20, 12) |
| #define M4U_PORT_L20_DISP_WDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 20, 13) |
| #define M4U_PORT_L20_DISP_UFBC_WDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 20, 14) |
| #define M4U_PORT_L20_DISP_FAKE0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 20, 15) |
| |
| /* larb21 */ |
| #define M4U_PORT_L21_DISP_OVL0_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 21, 0) |
| #define M4U_PORT_L21_DISP_OVL0_2L_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 21, 1) |
| #define M4U_PORT_L21_DISP_OVL1_2L_1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 21, 2) |
| #define M4U_PORT_L21_DISP_OVL0_2L_NWCG1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 21, 3) |
| #define M4U_PORT_L21_DISP_OVL1_2L_NWCG1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 21, 4) |
| #define M4U_PORT_L21_DISP_RDMA1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 21, 5) |
| #define M4U_PORT_L21_DISP_WDMA1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 21, 6) |
| #define M4U_PORT_L21_DISP_FAKE1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 21, 7) |
| |
| /* Larb22 */ |
| #define M4U_PORT_L22_IMG2_WPE_RDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 0) |
| #define M4U_PORT_L22_IMG2_WPE_RDMA1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 1) |
| #define M4U_PORT_L22_IMG2_WPE_RDMA_4P0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 2) |
| #define M4U_PORT_L22_IMG2_WPE_RDMA_4P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 3) |
| #define M4U_PORT_L22_IMG2_WPE_CQ0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 4) |
| #define M4U_PORT_L22_IMG2_WPE_CQ1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 5) |
| #define M4U_PORT_L22_IMG2_PIMGI_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 6) |
| #define M4U_PORT_L22_IMG2_PIMGBI_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 7) |
| #define M4U_PORT_L22_IMG2_PIMGCI_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 8) |
| #define M4U_PORT_L22_IMG2_IMGI_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 9) |
| #define M4U_PORT_L22_IMG2_IMGBI_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 10) |
| #define M4U_PORT_L22_IMG2_IMGCI_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 11) |
| #define M4U_PORT_L22_IMG2_SMTI_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 12) |
| #define M4U_PORT_L22_IMG2_SMTI_T4_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 13) |
| #define M4U_PORT_L22_IMG2_SMTI_T6_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 14) |
| #define M4U_PORT_L22_IMG2_YUVO_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 15) |
| #define M4U_PORT_L22_IMG2_YUVBO_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 16) |
| #define M4U_PORT_L22_IMG2_YUVCO_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 17) |
| #define M4U_PORT_L22_IMG2_WPE_WDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 18) |
| #define M4U_PORT_L22_IMG2_WPE_WDMA_4P0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 19) |
| #define M4U_PORT_L22_IMG2_WROT_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 20) |
| #define M4U_PORT_L22_IMG2_TCCSO_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 21) |
| #define M4U_PORT_L22_IMG2_TCCSI_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 22) |
| #define M4U_PORT_L22_IMG2_TIMGO_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 23) |
| #define M4U_PORT_L22_IMG2_YUVO_T2_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 24) |
| #define M4U_PORT_L22_IMG2_YUVO_T5_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 25) |
| #define M4U_PORT_L22_IMG2_SMTO_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 26) |
| #define M4U_PORT_L22_IMG2_SMTO_T4_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 27) |
| #define M4U_PORT_L22_IMG2_SMTO_T6_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 28) |
| #define M4U_PORT_L22_IMG2_DBGO_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 22, 29) |
| |
| /* Larb23 */ |
| #define M4U_PORT_L23_IMG2_WPE_RDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 0) |
| #define M4U_PORT_L23_IMG2_WPE_RDMA1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 1) |
| #define M4U_PORT_L23_IMG2_WPE_RDMA_4P0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 2) |
| #define M4U_PORT_L23_IMG2_WPE_RDMA_4P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 3) |
| #define M4U_PORT_L23_IMG2_WPE_CQ0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 4) |
| #define M4U_PORT_L23_IMG2_WPE_CQ1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 5) |
| #define M4U_PORT_L23_IMG2_PIMGI_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 6) |
| #define M4U_PORT_L23_IMG2_PIMGBI_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 7) |
| #define M4U_PORT_L23_IMG2_PIMGCI_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 8) |
| #define M4U_PORT_L23_IMG2_IMGI_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 9) |
| #define M4U_PORT_L23_IMG2_IMGBI_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 10) |
| #define M4U_PORT_L23_IMG2_IMGCI_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 11) |
| #define M4U_PORT_L23_IMG2_SMTI_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 12) |
| #define M4U_PORT_L23_IMG2_SMTI_T4_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 13) |
| #define M4U_PORT_L23_IMG2_SMTI_T6_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 14) |
| #define M4U_PORT_L23_IMG2_YUVO_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 15) |
| #define M4U_PORT_L23_IMG2_YUVBO_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 16) |
| #define M4U_PORT_L23_IMG2_YUVCO_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 17) |
| #define M4U_PORT_L23_IMG2_WPE_WDMA0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 18) |
| #define M4U_PORT_L23_IMG2_WPE_WDMA_4P0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 19) |
| #define M4U_PORT_L23_IMG2_WROT_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 20) |
| #define M4U_PORT_L23_IMG2_TCCSO_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 21) |
| #define M4U_PORT_L23_IMG2_TCCSI_P1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 22) |
| #define M4U_PORT_L23_IMG2_TIMGO_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 23) |
| #define M4U_PORT_L23_IMG2_YUVO_T2_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 24) |
| #define M4U_PORT_L23_IMG2_YUVO_T5_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 25) |
| #define M4U_PORT_L23_IMG2_SMTO_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 26) |
| #define M4U_PORT_L23_IMG2_SMTO_T4_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 27) |
| #define M4U_PORT_L23_IMG2_SMTO_T6_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 28) |
| #define M4U_PORT_L23_IMG2_DBGO_T1_C MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 23, 29) |
| |
| /* larb24--dummy */ |
| |
| /* larb25 */ |
| #define M4U_PORT_L25_CAM_MRAW0_LSCI_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 0) |
| #define M4U_PORT_L25_CAM_MRAW0_CQI_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 1) |
| #define M4U_PORT_L25_CAM_MRAW0_CQI_M2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 2) |
| #define M4U_PORT_L25_CAM_MRAW0_IMGO_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 3) |
| #define M4U_PORT_L25_CAM_MRAW0_IMGBO_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 4) |
| #define M4U_PORT_L25_CAM_MRAW2_LSCI_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 5) |
| #define M4U_PORT_L25_CAM_MRAW2_CQI_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 6) |
| #define M4U_PORT_L25_CAM_MRAW2_CQI_M2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 7) |
| #define M4U_PORT_L25_CAM_MRAW2_IMGO_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 8) |
| #define M4U_PORT_L25_CAM_MRAW2_IMGBO_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 9) |
| #define M4U_PORT_L25_CAM_MRAW0_AFO_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 10) |
| #define M4U_PORT_L25_CAM_PDAI_A0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 11) |
| #define M4U_PORT_L25_CAM_PDAI_A1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 12) |
| #define M4U_PORT_L25_CAM_PDAO_A MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 25, 13) |
| |
| /* larb26 */ |
| #define M4U_PORT_L26_CAM_MRAW1_LSCI_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 26, 0) |
| #define M4U_PORT_L26_CAM_MRAW1_CQI_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 26, 1) |
| #define M4U_PORT_L26_CAM_MRAW1_CQI_M2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 26, 2) |
| #define M4U_PORT_L26_CAM_MRAW1_IMGO_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 26, 3) |
| #define M4U_PORT_L26_CAM_MRAW1_IMGBO_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 26, 4) |
| #define M4U_PORT_L26_CAM_MRAW3_LSCI_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 26, 5) |
| #define M4U_PORT_L26_CAM_MRAW3_CQI_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 26, 6) |
| #define M4U_PORT_L26_CAM_MRAW3_CQI_M2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 26, 7) |
| #define M4U_PORT_L26_CAM_MRAW3_IMGO_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 26, 8) |
| #define M4U_PORT_L26_CAM_MRAW3_IMGBO_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 26, 9) |
| #define M4U_PORT_L26_CAM_MRAW1_AFO_M1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 26, 10) |
| #define M4U_PORT_L26_CAM_PDAI_B0 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 26, 11) |
| #define M4U_PORT_L26_CAM_PDAI_B1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 26, 12) |
| #define M4U_PORT_L26_CAM_PDAO_B MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 26, 13) |
| |
| /* larb27 */ |
| #define M4U_PORT_L27_CAM2_IMGP_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 27, 0) |
| #define M4U_PORT_L27_CAM2_CQI_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 27, 1) |
| #define M4U_PORT_L27_CAM2_CQI_R2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 27, 2) |
| #define M4U_PORT_L27_CAM2_BPCI_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 27, 3) |
| #define M4U_PORT_L27_CAM2_LSCI_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 27, 4) |
| #define M4U_PORT_L27_CAM2_RAWI_R2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 27, 5) |
| #define M4U_PORT_L27_CAM2_RAWI_R3 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 27, 6) |
| #define M4U_PORT_L27_CAM2_UFDI_R2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 27, 7) |
| #define M4U_PORT_L27_CAM2_UFDI_R3 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 27, 8) |
| #define M4U_PORT_L27_CAM2_RAWI_R4 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 27, 9) |
| #define M4U_PORT_L27_CAM2_RAWI_R5 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 27, 10) |
| #define M4U_PORT_L27_CAM2_AAI_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 27, 11) |
| #define M4U_PORT_L27_CAM2_UFDI_R5 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 27, 12) |
| #define M4U_PORT_L27_CAM2_FHO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 27, 13) |
| #define M4U_PORT_L27_CAM2_AAO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 27, 14) |
| #define M4U_PORT_L27_CAM2_TSFSO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 27, 15) |
| #define M4U_PORT_L27_CAM2_FLKO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 27, 16) |
| |
| /* larb28 */ |
| #define M4U_PORT_L28_CAM2_IMGP_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 0) |
| #define M4U_PORT_L28_CAM2_CQI_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 1) |
| #define M4U_PORT_L28_CAM2_CQI_R2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 2) |
| #define M4U_PORT_L28_CAM2_BPCI_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 3) |
| #define M4U_PORT_L28_CAM2_LSCI_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 4) |
| #define M4U_PORT_L28_CAM2_RAWI_R2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 5) |
| #define M4U_PORT_L28_CAM2_RAWI_R3 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 6) |
| #define M4U_PORT_L28_CAM2_UFDI_R2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 7) |
| #define M4U_PORT_L28_CAM2_UFDI_R3 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 8) |
| #define M4U_PORT_L28_CAM2_RAWI_R4 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 9) |
| #define M4U_PORT_L28_CAM2_RAWI_R5 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 10) |
| #define M4U_PORT_L28_CAM2_AAI_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 11) |
| #define M4U_PORT_L28_CAM2_UFDI_R5 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 12) |
| #define M4U_PORT_L28_CAM2_FHO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 13) |
| #define M4U_PORT_L28_CAM2_AAO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 14) |
| #define M4U_PORT_L28_CAM2_TSFSO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 15) |
| #define M4U_PORT_L28_CAM2_FLKO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 28, 16) |
| |
| /* larb29 */ |
| #define M4U_PORT_L29_CAM3_YUVO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 29, 0) |
| #define M4U_PORT_L29_CAM3_YUVO_R3 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 29, 1) |
| #define M4U_PORT_L29_CAM3_YUVCO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 29, 2) |
| #define M4U_PORT_L29_CAM3_YUVO_R2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 29, 3) |
| #define M4U_PORT_L29_CAM3_RZH1N2TO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 29, 4) |
| #define M4U_PORT_L29_CAM3_DRZS4NO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 29, 5) |
| #define M4U_PORT_L29_CAM3_TNCSO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 29, 6) |
| |
| /* larb30 */ |
| #define M4U_PORT_L30_CAM3_YUVO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 30, 0) |
| #define M4U_PORT_L30_CAM3_YUVO_R3 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 30, 1) |
| #define M4U_PORT_L30_CAM3_YUVCO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 30, 2) |
| #define M4U_PORT_L30_CAM3_YUVO_R2 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 30, 3) |
| #define M4U_PORT_L30_CAM3_RZH1N2TO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 30, 4) |
| #define M4U_PORT_L30_CAM3_DRZS4NO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 30, 5) |
| #define M4U_PORT_L30_CAM3_TNCSO_R1 MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 30, 6) |
| |
| /* fake larb31 */ |
| #define M4U_PORT_L31_CCU0 MTK_M4U_PORT_ID(MM_TAB, CCU0_DOM, 31, 0) |
| #define M4U_PORT_L31_CCU1 MTK_M4U_PORT_ID(MM_TAB, CCU1_DOM, 31, 1) |
| |
| /* fake larb32 */ |
| #define M4U_PORT_L32_VIDEO_UP MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 32, 0) |
| #define M4U_PORT_L32_GCE_DM MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 32, 1) |
| #define M4U_PORT_L32_GCE_MM MTK_M4U_PORT_ID(MM_TAB, NORMAL_DOM, 32, 2) |
| |
| /* fake larb33 reserved */ |
| #define M4U_PORT_L33_VIDEO_UP_512MB1 MTK_M4U_PORT_ID(MM_TAB, VDO_REGION1, 33, 0) |
| #define M4U_PORT_L33_VIDEO_UP_512MB2 MTK_M4U_PORT_ID(MM_TAB, VDO_REGION2, 33, 1) |
| #define M4U_PORT_L33_VIDEO_UP_256MB1 MTK_M4U_PORT_ID(MM_TAB, VDO_REGION3, 33, 2) |
| #define M4U_PORT_L33_VIDEO_UP_256MB2 MTK_M4U_PORT_ID(MM_TAB, VDO_REGION4, 33, 3) |
| |
| /* fake larb34 */ |
| #define M4U_PORT_L34_APU_SECURE MTK_M4U_PORT_ID(APU_TAB, APU_SEC_DOM, 34, 0) |
| #define M4U_PORT_L34_APU_CODE MTK_M4U_PORT_ID(APU_TAB, APU_CODE_DOM, 34, 1) |
| #define M4U_PORT_L34_APU_DATA MTK_M4U_PORT_ID(APU_TAB, APU_DATA_DOM, 34, 2) |
| |
| #endif |
