| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Copyright (c) 2019 MediaTek Inc. |
| * Author: Ming-Fan Chen <ming-fan.chen@mediatek.com> |
| */ |
| #include <dt-bindings/interconnect/mtk,mmqos.h> |
| #include <dt-bindings/interconnect/mtk,mt6873-emi.h> |
| #include <dt-bindings/memory/mt6983-larb-port.h> |
| #include <linux/module.h> |
| #include <linux/of_platform.h> |
| #include "mmqos-mtk.h" |
| static const struct mtk_node_desc node_descs_mt6983[] = { |
| DEFINE_MNODE(common0, |
| SLAVE_COMMON(0), 0, false, 0x0, MMQOS_NO_LINK), //DISP |
| DEFINE_MNODE(mdp_common0, |
| SLAVE_COMMON(1), 0, false, 0x0, MMQOS_NO_LINK), //MDP |
| DEFINE_MNODE(common0_port0, |
| MASTER_COMMON_PORT(0, 0), 0, false, 0x0, SLAVE_COMMON(0)), |
| DEFINE_MNODE(common0_port1, |
| MASTER_COMMON_PORT(0, 1), 0, false, 0x0, SLAVE_COMMON(0)), |
| DEFINE_MNODE(common0_port2, |
| MASTER_COMMON_PORT(0, 2), 0, false, 0x0, SLAVE_COMMON(0)), |
| DEFINE_MNODE(common0_port3, |
| MASTER_COMMON_PORT(0, 3), 0, false, 0x0, SLAVE_COMMON(0)), |
| DEFINE_MNODE(common0_port4, |
| MASTER_COMMON_PORT(0, 4), 0, false, 0x0, SLAVE_COMMON(0)), |
| DEFINE_MNODE(common0_port5, |
| MASTER_COMMON_PORT(0, 5), 0, false, 0x0, SLAVE_COMMON(0)), |
| DEFINE_MNODE(common0_port6, |
| MASTER_COMMON_PORT(0, 6), 0, false, 0x0, SLAVE_COMMON(0)), |
| DEFINE_MNODE(common0_port7, |
| MASTER_COMMON_PORT(0, 7), 0, false, 0x0, SLAVE_COMMON(0)), |
| DEFINE_MNODE(common0_port8, |
| MASTER_COMMON_PORT(0, 8), 0, false, 0x0, SLAVE_COMMON(0)), |
| DEFINE_MNODE(mdp_common0_port0, |
| MASTER_COMMON_PORT(1, 0), 0, false, 0x0, SLAVE_COMMON(1)), |
| DEFINE_MNODE(mdp_common0_port1, |
| MASTER_COMMON_PORT(1, 1), 0, false, 0x0, SLAVE_COMMON(1)), |
| DEFINE_MNODE(mdp_common0_port2, |
| MASTER_COMMON_PORT(1, 2), 0, false, 0x0, SLAVE_COMMON(1)), |
| DEFINE_MNODE(mdp_common0_port3, |
| MASTER_COMMON_PORT(1, 3), 0, false, 0x0, SLAVE_COMMON(1)), |
| DEFINE_MNODE(mdp_common0_port4, |
| MASTER_COMMON_PORT(1, 4), 0, false, 0x0, SLAVE_COMMON(1)), |
| DEFINE_MNODE(mdp_common0_port5, |
| MASTER_COMMON_PORT(1, 5), 0, false, 0x0, SLAVE_COMMON(1)), |
| DEFINE_MNODE(mdp_common0_port6, |
| MASTER_COMMON_PORT(1, 6), 0, false, 0x0, SLAVE_COMMON(1)), |
| DEFINE_MNODE(mdp_common0_port7, |
| MASTER_COMMON_PORT(1, 7), 0, false, 0x0, SLAVE_COMMON(1)), |
| DEFINE_MNODE(mdp_common0_port8, |
| MASTER_COMMON_PORT(1, 8), 0, false, 0x0, SLAVE_COMMON(1)), |
| /* SMI COMMON */ |
| DEFINE_MNODE(larb0, SLAVE_LARB(0), 0, false, 0x0, MASTER_COMMON_PORT(0, 0)), |
| DEFINE_MNODE(larb21, SLAVE_LARB(21), 0, false, 0x0, MASTER_COMMON_PORT(0, 1)), |
| DEFINE_MNODE(larb2, SLAVE_LARB(2), 0, false, 0x0, MASTER_COMMON_PORT(0, 2)), |
| DEFINE_MNODE(larb5, SLAVE_LARB(5), 0, false, 0x0, MASTER_COMMON_PORT(0, 3)), |
| DEFINE_MNODE(larb7, SLAVE_LARB(7), 0, false, 0x0, MASTER_COMMON_PORT(0, 4)), |
| DEFINE_MNODE(larb9, SLAVE_LARB(9), 0, false, 0x2, MASTER_COMMON_PORT(0, 5)), |
| DEFINE_MNODE(larb10, SLAVE_LARB(10), 0, true, 0x2, MASTER_COMMON_PORT(0, 5)), |
| DEFINE_MNODE(larb11, SLAVE_LARB(11), 0, false, 0x0, MASTER_COMMON_PORT(0, 5)), //LARB11_u0 |
| DEFINE_MNODE(larb23, SLAVE_LARB(23), 0, false, 0x0, MASTER_COMMON_PORT(0, 5)), //LARB11_u2 |
| DEFINE_MNODE(larb25, SLAVE_LARB(25), 0, false, 0x0, MASTER_COMMON_PORT(0, 6)), |
| DEFINE_MNODE(larb29, SLAVE_LARB(29), 0, false, 0x0, MASTER_COMMON_PORT(0, 6)), //LARB17_u1 |
| DEFINE_MNODE(larb30, SLAVE_LARB(30), 0, false, 0x0, MASTER_COMMON_PORT(0, 6)), //LARB17_u2 |
| DEFINE_MNODE(larb27, SLAVE_LARB(27), 0, false, 0x0, MASTER_COMMON_PORT(0, 6)), //LARB16_u1 |
| DEFINE_MNODE(larb13, SLAVE_LARB(13), 0, false, 0x0, MASTER_COMMON_PORT(0, 6)), |
| DEFINE_MNODE(larb6, SLAVE_LARB(6), 0, false, 0x0, MASTER_COMMON_PORT(0, 7)), |
| /* MDP COMMON */ |
| DEFINE_MNODE(larb1, SLAVE_LARB(1), 0, false, 0x0, MASTER_COMMON_PORT(1, 0)), |
| DEFINE_MNODE(larb20, SLAVE_LARB(20), 0, false, 0x0, MASTER_COMMON_PORT(1, 1)), |
| DEFINE_MNODE(larb3, SLAVE_LARB(3), 0, false, 0x0, MASTER_COMMON_PORT(1, 2)), |
| DEFINE_MNODE(larb4, SLAVE_LARB(4), 0, false, 0x0, MASTER_COMMON_PORT(1, 3)), |
| DEFINE_MNODE(larb8, SLAVE_LARB(8), 0, false, 0x0, MASTER_COMMON_PORT(1, 4)), |
| DEFINE_MNODE(larb18, SLAVE_LARB(18), 0, false, 0x0, MASTER_COMMON_PORT(1, 5)), |
| DEFINE_MNODE(larb15, SLAVE_LARB(15), 0, true, 0x12, MASTER_COMMON_PORT(1, 5)), |
| DEFINE_MNODE(larb12, SLAVE_LARB(12), 0, false, 0x12, MASTER_COMMON_PORT(1, 5)), |
| DEFINE_MNODE(larb22, SLAVE_LARB(22), 0, false, 0x0, MASTER_COMMON_PORT(1, 5)), //LARB11_u1 |
| DEFINE_MNODE(larb14, SLAVE_LARB(14), 0, false, 0x0, MASTER_COMMON_PORT(1, 6)), |
| DEFINE_MNODE(larb26, SLAVE_LARB(26), 0, false, 0x0, MASTER_COMMON_PORT(1, 6)), |
| DEFINE_MNODE(larb17, SLAVE_LARB(17), 0, false, 0x0, MASTER_COMMON_PORT(1, 6)), //LARB17_u0 |
| DEFINE_MNODE(larb16, SLAVE_LARB(16), 0, false, 0x0, MASTER_COMMON_PORT(1, 6)), //LARB16_u0 |
| DEFINE_MNODE(larb28, SLAVE_LARB(28), 0, false, 0x0, MASTER_COMMON_PORT(1, 6)), //LARB16_u2 |
| DEFINE_MNODE(larb19, SLAVE_LARB(19), 0, false, 0x0, MASTER_COMMON_PORT(1, 6)), |
| DEFINE_MNODE(larb31, SLAVE_LARB(31), 0, false, 0x1, MASTER_COMMON_PORT(0, 8)), //virt DISP |
| DEFINE_MNODE(larb32, SLAVE_LARB(32), 0, true, 0x11, MASTER_COMMON_PORT(1, 6)), //virt CCU0 |
| DEFINE_MNODE(larb33, SLAVE_LARB(33), 0, true, 0x11, MASTER_COMMON_PORT(1, 6)), //virt CCU1 |
| DEFINE_MNODE(disp_postmask0, |
| MASTER_LARB_PORT(M4U_PORT_L0_DISP_POSTMASK0), 8, false, 0x1, SLAVE_LARB(0)), |
| DEFINE_MNODE(dmdp_rdma0, |
| MASTER_LARB_PORT(M4U_PORT_L0_DMDP_RDMA0), 8, false, 0x1, SLAVE_LARB(0)), |
| DEFINE_MNODE(disp_ovl0_hdr, |
| MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL0_HDR), 7, false, 0x1, SLAVE_LARB(0)), |
| DEFINE_MNODE(disp_ovl0_2L_hdr, |
| MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL0_2L_HDR), 7, false, 0x1, SLAVE_LARB(0)), |
| DEFINE_MNODE(disp_ovl1_2L_hdr, |
| MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL1_2L_HDR), 8, true, 0x1, SLAVE_LARB(0)), |
| DEFINE_MNODE(disp_ovl0_2L_NWCG_hdr, |
| MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL0_2L_NWCG_HDR), 7, false, 0x1, SLAVE_LARB(0)), |
| DEFINE_MNODE(disp_ovl1_2L_NWCG_hdr, |
| MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL1_2L_NWCG_HDR), 7, false, 0x1, SLAVE_LARB(0)), |
| DEFINE_MNODE(disp_ovl0_0, |
| MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL0_0_DISP), 8, false, 0x1, SLAVE_LARB(0)), |
| DEFINE_MNODE(disp_ovl0_2L_0, |
| MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL0_2L_0), 8, false, 0x1, SLAVE_LARB(0)), |
| DEFINE_MNODE(disp_ovl1_2L_0, |
| MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL1_2L_0), 8, false, 0x1, SLAVE_LARB(0)), |
| DEFINE_MNODE(disp_ovl0_2L_NWCG_0, |
| MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL0_2L_NWCG_0), 8, false, 0x1, SLAVE_LARB(0)), |
| DEFINE_MNODE(disp_ovl1_2L_NWCG_0, |
| MASTER_LARB_PORT(M4U_PORT_L0_DISP_OVL1_2L_NWCG_0), 8, false, 0x1, SLAVE_LARB(0)), |
| DEFINE_MNODE(disp_rdma0, |
| MASTER_LARB_PORT(M4U_PORT_L0_DISP_RDMA0), 8, false, 0x1, SLAVE_LARB(0)), |
| DEFINE_MNODE(disp_wdma0, |
| MASTER_LARB_PORT(M4U_PORT_L0_DISP_WDMA0), 9, true, 0x1, SLAVE_LARB(0)), |
| DEFINE_MNODE(disp_ufbc_wdma0, |
| MASTER_LARB_PORT(M4U_PORT_L0_DISP_UFBC_WDMA0), 9, true, 0x1, SLAVE_LARB(0)), |
| DEFINE_MNODE(disp_fake0, |
| MASTER_LARB_PORT(M4U_PORT_L0_DISP_FAKE0), 8, false, 0x1, SLAVE_LARB(0)), |
| DEFINE_MNODE(disp_ovl0_1, |
| MASTER_LARB_PORT(M4U_PORT_L21_DISP_OVL0_1), 8, false, 0x2, SLAVE_LARB(21)), |
| DEFINE_MNODE(disp_ovl0_2L_1, |
| MASTER_LARB_PORT(M4U_PORT_L21_DISP_OVL0_2L_1), 8, false, 0x2, SLAVE_LARB(21)), |
| DEFINE_MNODE(disp_ovl1_2L_1, |
| MASTER_LARB_PORT(M4U_PORT_L21_DISP_OVL1_2L_1), 8, false, 0x2, SLAVE_LARB(21)), |
| DEFINE_MNODE(disp_ovl0_2L_NWCG_1, |
| MASTER_LARB_PORT(M4U_PORT_L21_DISP_OVL0_2L_NWCG1), 8, false, 0x2, SLAVE_LARB(21)), |
| DEFINE_MNODE(disp_ovl1_2L_NWCG_1, |
| MASTER_LARB_PORT(M4U_PORT_L21_DISP_OVL1_2L_NWCG1), 9, true, 0x2, SLAVE_LARB(21)), |
| DEFINE_MNODE(disp_rdma1, |
| MASTER_LARB_PORT(M4U_PORT_L21_DISP_RDMA1), 8, false, 0x2, SLAVE_LARB(21)), |
| DEFINE_MNODE(disp_wdma1, |
| MASTER_LARB_PORT(M4U_PORT_L21_DISP_WDMA1), 9, true, 0x2, SLAVE_LARB(21)), |
| DEFINE_MNODE(disp_fake1, |
| MASTER_LARB_PORT(M4U_PORT_L21_DISP_FAKE1), 8, false, 0x2, SLAVE_LARB(21)), |
| DEFINE_MNODE(mdp_rdma0, |
| MASTER_LARB_PORT(M4U_PORT_L2_MDP_RDMA0), 8, false, 0x2, SLAVE_LARB(2)), |
| DEFINE_MNODE(mdp_rdma2, |
| MASTER_LARB_PORT(M4U_PORT_L2_MDP_RDMA2), 8, false, 0x2, SLAVE_LARB(2)), |
| DEFINE_MNODE(mdp_wrot0, |
| MASTER_LARB_PORT(M4U_PORT_L2_MDP_WROT0), 9, true, 0x2, SLAVE_LARB(2)), |
| DEFINE_MNODE(mdp_wrot2, |
| MASTER_LARB_PORT(M4U_PORT_L2_MDP_WROT2), 9, true, 0x2, SLAVE_LARB(2)), |
| DEFINE_MNODE(disp_fake0, |
| MASTER_LARB_PORT(M4U_PORT_L2_MDP_DISP_FAKE0), 8, false, 0x2, SLAVE_LARB(2)), |
| DEFINE_MNODE(mdp_filmgrain0, |
| MASTER_LARB_PORT(M4U_PORT_L2_MDP_FILMGRAIN0), 8, false, 0x2, SLAVE_LARB(2)), |
| DEFINE_MNODE(mdp_filmgrain2, |
| MASTER_LARB_PORT(M4U_PORT_L2_MDP_FILMGRAIN2), 8, false, 0x2, SLAVE_LARB(2)), |
| DEFINE_MNODE(mdp_wdma0, |
| MASTER_LARB_PORT(M4U_PORT_L2_MDP_WDMA0), 9, true, 0x2, SLAVE_LARB(2)), |
| DEFINE_MNODE(mdp_wdma2, |
| MASTER_LARB_PORT(M4U_PORT_L2_MDP_WDMA2), 9, true, 0x2, SLAVE_LARB(2)), |
| DEFINE_MNODE(hw_vdec_lat0_vld_ext, |
| MASTER_LARB_PORT(M4U_PORT_L5_VDEC_LAT0_VLD_EXT), 7, false, 0x2, SLAVE_LARB(5)), |
| DEFINE_MNODE(hw_vdec_lat0_vld2_ext, |
| MASTER_LARB_PORT(M4U_PORT_L5_VDEC_LAT0_VLD2_EXT), 7, false, 0x2, SLAVE_LARB(5)), |
| DEFINE_MNODE(hw_vdec_lat0_avc_mv_ext, |
| MASTER_LARB_PORT(M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT), 6, false, 0x2, SLAVE_LARB(5)), |
| DEFINE_MNODE(hw_vdec_lat0_pred_rd_ext, |
| MASTER_LARB_PORT(M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT), 7, false, 0x2, SLAVE_LARB(5)), |
| DEFINE_MNODE(hw_vdec_lat0_tile_ext, |
| MASTER_LARB_PORT(M4U_PORT_L5_VDEC_LAT0_TILE_EXT), 7, false, 0x2, SLAVE_LARB(5)), |
| DEFINE_MNODE(hw_vdec_lat0_wdma_ext, |
| MASTER_LARB_PORT(M4U_PORT_L5_VDEC_LAT0_WDMA_EXT), 8, true, 0x2, SLAVE_LARB(5)), |
| DEFINE_MNODE(hw_vdec_ufo_enc_ext, |
| MASTER_LARB_PORT(M4U_PORT_L5_VDEC_UFO_ENC_EXT), 7, true, 0x2, SLAVE_LARB(5)), |
| DEFINE_MNODE(hw_vdec_ufo_enc_ext_c, |
| MASTER_LARB_PORT(M4U_PORT_L5_VDEC_UFO_ENC_EXT_C), 7, true, 0x2, SLAVE_LARB(5)), |
| DEFINE_MNODE(hw_vdec_mc_ext_c, |
| MASTER_LARB_PORT(M4U_PORT_L5_VDEC_MC_EXT_C), 6, false, 0x2, SLAVE_LARB(5)), |
| DEFINE_MNODE(l7_venc_rcpu, |
| MASTER_LARB_PORT(M4U_PORT_L7_VENC_RCPU_DISP), 7, false, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_venc_rec, |
| MASTER_LARB_PORT(M4U_PORT_L7_VENC_REC_DISP), 8, true, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_venc_bsdma, |
| MASTER_LARB_PORT(M4U_PORT_L7_VENC_BSDMA_DISP), 8, true, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_venc_sv_comv, |
| MASTER_LARB_PORT(M4U_PORT_L7_VENC_SV_COMV_DISP), 8, true, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_venc_rd_comv, |
| MASTER_LARB_PORT(M4U_PORT_L7_VENC_RD_COMV_DISP), 7, false, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_venc_nbm_rdma, |
| MASTER_LARB_PORT(M4U_PORT_L7_VENC_NBM_RDMA_DISP), 7, false, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_venc_nbm_rdma_lite, |
| MASTER_LARB_PORT(M4U_PORT_L7_VENC_NBM_RDMA_LITE_DISP), 7, false, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_jpgenc_y_rdma, |
| MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_Y_RDMA_DISP), 7, false, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_jpgenc_c_rdma, |
| MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_C_RDMA_DISP), 7, false, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_jpgenc_q_table, |
| MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_Q_TABLE_DISP), 7, false, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_venc_sub_w_luma, |
| MASTER_LARB_PORT(M4U_PORT_L7_VENC_SUB_W_LUMA_DISP), 7, false, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_venc_fcs_nbm_rdma, |
| MASTER_LARB_PORT(M4U_PORT_L7_VENC_FCS_NBM_RDMA_DISP), 7, false, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_venc_ec_wpp_bsdma, |
| MASTER_LARB_PORT(M4U_PORT_L7_VENC_EC_WPP_BSDMA_DISP), 7, false, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_venc_ec_wpp_rdma, |
| MASTER_LARB_PORT(M4U_PORT_L7_VENC_EC_WPP_RDMA_DISP), 7, false, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_venc_db_sysram_wdma, |
| MASTER_LARB_PORT(M4U_PORT_L7_VENC_DB_SYSRAM_WDMA_DISP), 7, false, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_venc_db_sysram_rdma, |
| MASTER_LARB_PORT(M4U_PORT_L7_VENC_DB_SYSRAM_RDMA_DISP), 7, false, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_jpgenc_bsdma, |
| MASTER_LARB_PORT(M4U_PORT_L7_JPGENC_BSDMA_DISP), 8, true, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_jpgdec_wdma_0, |
| MASTER_LARB_PORT(M4U_PORT_L7_JPGDEC_WDMA_0_DISP), 8, true, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_jpgdec_bsdma_0, |
| MASTER_LARB_PORT(M4U_PORT_L7_JPGDEC_BSDMA_0_DISP), 7, false, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_venc_nbm_wdma, |
| MASTER_LARB_PORT(M4U_PORT_L7_VENC_NBM_WDMA_DISP), 8, true, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_venc_nbm_wdma_lite, |
| MASTER_LARB_PORT(M4U_PORT_L7_VENC_NBM_WDMA_LITE_DISP), 8, true, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_venc_cur_luma, |
| MASTER_LARB_PORT(M4U_PORT_L7_VENC_CUR_LUMA_DISP), 7, false, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_venc_cur_chroma, |
| MASTER_LARB_PORT(M4U_PORT_L7_VENC_CUR_CHROMA_DISP), 7, false, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_venc_ref_luma, |
| MASTER_LARB_PORT(M4U_PORT_L7_VENC_REF_LUMA_DISP), 7, false, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_venc_ref_chroma, |
| MASTER_LARB_PORT(M4U_PORT_L7_VENC_REF_CHROMA_DISP), 7, false, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_venc_sub_r_luma, |
| MASTER_LARB_PORT(M4U_PORT_L7_VENC_SUB_R_LUMA_DISP), 7, false, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_venc_fcs_nbm_wdma, |
| MASTER_LARB_PORT(M4U_PORT_L7_VENC_FCS_NBM_WDMA_DISP), 8, true, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_jpgdec_wdma_1, |
| MASTER_LARB_PORT(M4U_PORT_L7_JPGDEC_WDMA_1_DISP), 8, true, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_jpgdec_bsdma_1, |
| MASTER_LARB_PORT(M4U_PORT_L7_JPGDEC_BSDMA_1_DISP), 7, false, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_jpgdec_huff_offset_1, |
| MASTER_LARB_PORT(M4U_PORT_L7_JPGDEC_HUFF_OFFSET_1_DISP), 8, true, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(l7_jpgdec_huff_offset_0, |
| MASTER_LARB_PORT(M4U_PORT_L7_JPGDEC_HUFF_OFFSET_0_DISP), 8, true, 0x1, SLAVE_LARB(7)), |
| DEFINE_MNODE(imgi_t1_a, |
| MASTER_LARB_PORT(M4U_PORT_L9_IMG1_IMGI_T1_A), 7, false, 0x2, SLAVE_LARB(9)), |
| DEFINE_MNODE(ufdi_t1_a, |
| MASTER_LARB_PORT(M4U_PORT_L9_IMG1_UFDI_T1_A), 7, false, 0x2, SLAVE_LARB(9)), |
| DEFINE_MNODE(imgbi_t1_a, |
| MASTER_LARB_PORT(M4U_PORT_L9_IMG1_IMGBI_T1_A), 7, false, 0x2, SLAVE_LARB(9)), |
| DEFINE_MNODE(imgci_t1_a, |
| MASTER_LARB_PORT(M4U_PORT_L9_IMG1_IMGCI_T1_A), 7, false, 0x2, SLAVE_LARB(9)), |
| DEFINE_MNODE(smti_t1_a, |
| MASTER_LARB_PORT(M4U_PORT_L9_IMG1_SMTI_T1_A), 7, false, 0x2, SLAVE_LARB(9)), |
| DEFINE_MNODE(smti_t4_a, |
| MASTER_LARB_PORT(M4U_PORT_L9_IMG1_SMTI_T4_A), 7, false, 0x2, SLAVE_LARB(9)), |
| DEFINE_MNODE(tncsti_t1_a, |
| MASTER_LARB_PORT(M4U_PORT_L9_IMG1_TNCSTI_T1_A), 7, false, 0x2, SLAVE_LARB(9)), |
| DEFINE_MNODE(tncsti_t4_a, |
| MASTER_LARB_PORT(M4U_PORT_L9_IMG1_TNCSTI_T4_A), 7, false, 0x2, SLAVE_LARB(9)), |
| DEFINE_MNODE(yuvo_t1_a, |
| MASTER_LARB_PORT(M4U_PORT_L9_IMG1_YUVO_T1_A), 8, true, 0x2, SLAVE_LARB(9)), |
| DEFINE_MNODE(yuvbo_t1_a, |
| MASTER_LARB_PORT(M4U_PORT_L9_IMG1_YUVBO_T1_A), 8, true, 0x2, SLAVE_LARB(9)), |
| DEFINE_MNODE(yuvco_t1_a, |
| MASTER_LARB_PORT(M4U_PORT_L9_IMG1_YUVCO_T1_A), 8, true, 0x2, SLAVE_LARB(9)), |
| DEFINE_MNODE(timgo_t1_a, |
| MASTER_LARB_PORT(M4U_PORT_L9_IMG1_TIMGO_T1_A), 8, true, 0x2, SLAVE_LARB(9)), |
| DEFINE_MNODE(yuvo_t2_a, |
| MASTER_LARB_PORT(M4U_PORT_L9_IMG1_YUVO_T2_A), 8, true, 0x2, SLAVE_LARB(9)), |
| DEFINE_MNODE(yuvo_t5_a, |
| MASTER_LARB_PORT(M4U_PORT_L9_IMG1_YUVO_T5_A), 8, true, 0x2, SLAVE_LARB(9)), |
| DEFINE_MNODE(imgi_t1_b, |
| MASTER_LARB_PORT(M4U_PORT_L9_IMG1_IMGI_T1_B), 7, false, 0x2, SLAVE_LARB(9)), |
| DEFINE_MNODE(imgbi_t1_b, |
| MASTER_LARB_PORT(M4U_PORT_L9_IMG1_IMGBI_T1_B), 7, false, 0x2, SLAVE_LARB(9)), |
| DEFINE_MNODE(imgci_t1_b, |
| MASTER_LARB_PORT(M4U_PORT_L9_IMG1_IMGCI_T1_B), 7, false, 0x2, SLAVE_LARB(9)), |
| DEFINE_MNODE(smti_t4_b, |
| MASTER_LARB_PORT(M4U_PORT_L9_IMG1_SMTI_T4_B), 7, false, 0x2, SLAVE_LARB(9)), |
| DEFINE_MNODE(tncso_t1_a, |
| MASTER_LARB_PORT(M4U_PORT_L9_IMG1_TNCSO_T1_A), 8, true, 0x2, SLAVE_LARB(9)), |
| DEFINE_MNODE(smto_t1_a, |
| MASTER_LARB_PORT(M4U_PORT_L9_IMG1_SMTO_T1_A), 8, true, 0x2, SLAVE_LARB(9)), |
| DEFINE_MNODE(smto_t4_a, |
| MASTER_LARB_PORT(M4U_PORT_L9_IMG1_SMTO_T4_A), 8, true, 0x2, SLAVE_LARB(9)), |
| DEFINE_MNODE(tncsto_t1_a, |
| MASTER_LARB_PORT(M4U_PORT_L9_IMG1_TNCSTO_T1_A), 8, true, 0x2, SLAVE_LARB(9)), |
| DEFINE_MNODE(yuvo_t2_b, |
| MASTER_LARB_PORT(M4U_PORT_L9_IMG1_YUVO_T2_B), 8, true, 0x2, SLAVE_LARB(9)), |
| DEFINE_MNODE(yuvo_t5_b, |
| MASTER_LARB_PORT(M4U_PORT_L9_IMG1_YUVO_T5_B), 8, true, 0x2, SLAVE_LARB(9)), |
| DEFINE_MNODE(smto_t4_b, |
| MASTER_LARB_PORT(M4U_PORT_L9_IMG1_SMTO_T4_B), 8, true, 0x2, SLAVE_LARB(9)), |
| DEFINE_MNODE(imgi_d1, |
| MASTER_LARB_PORT(M4U_PORT_L10_IMG2_IMGI_D1), 7, false, 0x2, SLAVE_LARB(10)), |
| DEFINE_MNODE(imgbi_d1, |
| MASTER_LARB_PORT(M4U_PORT_L10_IMG2_IMGBI_D1), 7, false, 0x2, SLAVE_LARB(10)), |
| DEFINE_MNODE(imgci_d1, |
| MASTER_LARB_PORT(M4U_PORT_L10_IMG2_IMGCI_D1), 7, false, 0x2, SLAVE_LARB(10)), |
| DEFINE_MNODE(imgdi_d1, |
| MASTER_LARB_PORT(M4U_PORT_L10_IMG2_IMGDI_D1), 7, false, 0x2, SLAVE_LARB(10)), |
| DEFINE_MNODE(depi_d1, |
| MASTER_LARB_PORT(M4U_PORT_L10_IMG2_DEPI_D1), 7, false, 0x2, SLAVE_LARB(10)), |
| DEFINE_MNODE(dmgi_d1, |
| MASTER_LARB_PORT(M4U_PORT_L10_IMG2_DMGI_D1), 7, false, 0x2, SLAVE_LARB(10)), |
| DEFINE_MNODE(smti_d1, |
| MASTER_LARB_PORT(M4U_PORT_L10_IMG2_SMTI_D1), 7, false, 0x2, SLAVE_LARB(10)), |
| DEFINE_MNODE(reci_d1, |
| MASTER_LARB_PORT(M4U_PORT_L10_IMG2_RECI_D1), 7, false, 0x2, SLAVE_LARB(10)), |
| DEFINE_MNODE(reci_d1_n, |
| MASTER_LARB_PORT(M4U_PORT_L10_IMG2_RECI_D1_N), 7, false, 0x2, SLAVE_LARB(10)), |
| DEFINE_MNODE(tnrwi_d1, |
| MASTER_LARB_PORT(M4U_PORT_L10_IMG2_TNRWI_D1), 7, false, 0x2, SLAVE_LARB(10)), |
| DEFINE_MNODE(tnrci_d1, |
| MASTER_LARB_PORT(M4U_PORT_L10_IMG2_TNRCI_D1), 7, false, 0x2, SLAVE_LARB(10)), |
| DEFINE_MNODE(tnrci_d1_n, |
| MASTER_LARB_PORT(M4U_PORT_L10_IMG2_TNRCI_D1_N), 7, false, 0x2, SLAVE_LARB(10)), |
| DEFINE_MNODE(img4o_d1, |
| MASTER_LARB_PORT(M4U_PORT_L10_IMG2_IMG4O_D1), 8, true, 0x2, SLAVE_LARB(10)), |
| DEFINE_MNODE(img4bo_d1, |
| MASTER_LARB_PORT(M4U_PORT_L10_IMG2_IMG4BO_D1), 8, true, 0x2, SLAVE_LARB(10)), |
| DEFINE_MNODE(smti_d8, |
| MASTER_LARB_PORT(M4U_PORT_L10_IMG2_SMTI_D8), 7, false, 0x2, SLAVE_LARB(10)), |
| DEFINE_MNODE(smto_d1, |
| MASTER_LARB_PORT(M4U_PORT_L10_IMG2_SMTO_D1), 8, true, 0x2, SLAVE_LARB(10)), |
| DEFINE_MNODE(tnrmo_d1, |
| MASTER_LARB_PORT(M4U_PORT_L10_IMG2_TNRMO_D1), 8, true, 0x2, SLAVE_LARB(10)), |
| DEFINE_MNODE(tnrmo_d1_n, |
| MASTER_LARB_PORT(M4U_PORT_L10_IMG2_TNRMO_D1_N), 8, true, 0x2, SLAVE_LARB(10)), |
| DEFINE_MNODE(smto_d8, |
| MASTER_LARB_PORT(M4U_PORT_L10_IMG2_SMTO_D8), 8, true, 0x2, SLAVE_LARB(10)), |
| DEFINE_MNODE(dbgo_d1, |
| MASTER_LARB_PORT(M4U_PORT_L10_IMG2_DBGO_D1), 8, true, 0x2, SLAVE_LARB(10)), |
| DEFINE_MNODE(l11_wpe_rdma_0, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_WPE_RDMA0), 7, false, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_wpe_rdma_1, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_WPE_RDMA1), 6, false, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_wpe_rdma_4p_0, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_WPE_RDMA_4P0), 7, false, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_wpe_rdma_4p_1, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_WPE_RDMA_4P1), 6, false, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_wpe_cq0, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_WPE_CQ0), 7, false, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_wpe_cq1, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_WPE_CQ1), 7, false, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_pimgi_p1, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_PIMGI_P1), 7, false, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_pimgbi_p1, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_PIMGBI_P1), 7, false, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_pimgci_p1, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_PIMGCI_P1), 7, false, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_imgi_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_IMGI_T1_C), 7, false, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_imgbi_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_IMGBI_T1_C), 7, false, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_imgci_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_IMGCI_T1_C), 7, false, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_smti_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_SMTI_T1_C), 7, false, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_smti_t4_c, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_SMTI_T4_C), 7, false, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_smti_t6_c, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_SMTI_T6_C), 7, false, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_yuvo_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_YUVO_T1_C), 8, true, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_yuvbo_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_YUVBO_T1_C), 8, true, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_yuvco_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_YUVCO_T1_C), 8, true, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_wpe_wdma_0, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_WPE_WDMA0), 8, true, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_wpe_wdma_4p_0, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_WPE_WDMA_4P0), 8, true, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_wrot_p1, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_WROT_P1), 8, true, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_tccso_p1, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_TCCSO_P1), 8, true, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_tccsi_p1, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_TCCSI_P1), 7, false, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_timgo_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_TIMGO_T1_C), 8, true, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_yuvo_t2_c, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_YUVO_T2_C), 8, true, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_yuvo_t5_c, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_YUVO_T5_C), 8, true, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_smto_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_SMTO_T1_C), 8, true, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_smto_t4_c, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_SMTO_T4_C), 8, true, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_smto_t6_c, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_SMTO_T6_C), 8, true, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l11_dbgo_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L11_IMG2_DBGO_T1_C), 8, true, 0x2, SLAVE_LARB(11)), |
| DEFINE_MNODE(l23_wpe_rdma_0, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_WPE_RDMA0), 7, false, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_wpe_rdma_1, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_WPE_RDMA1), 6, false, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_wpe_rdma_4p_0, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_WPE_RDMA_4P0), 7, false, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_wpe_rdma_4p_1, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_WPE_RDMA_4P1), 6, false, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_wpe_cq0, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_WPE_CQ0), 7, false, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_wpe_cq1, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_WPE_CQ1), 7, false, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_pimgi_p1, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_PIMGI_P1), 7, false, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_pimgbi_p1, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_PIMGBI_P1), 7, false, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_pimgci_p1, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_PIMGCI_P1), 7, false, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_imgi_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_IMGI_T1_C), 7, false, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_imgbi_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_IMGBI_T1_C), 7, false, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_imgci_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_IMGCI_T1_C), 7, false, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_smti_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_SMTI_T1_C), 7, false, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_smti_t4_c, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_SMTI_T4_C), 7, false, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_smti_t6_c, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_SMTI_T6_C), 7, false, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_yuvo_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_YUVO_T1_C), 8, true, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_yuvbo_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_YUVBO_T1_C), 8, true, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_yuvco_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_YUVCO_T1_C), 8, true, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_wpe_wdma_0, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_WPE_WDMA0), 8, true, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_wpe_wdma_4p_0, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_WPE_WDMA_4P0), 8, true, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_wrot_p1, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_WROT_P1), 8, true, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_tccso_p1, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_TCCSO_P1), 8, true, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_tccsi_p1, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_TCCSI_P1), 7, false, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_timgo_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_TIMGO_T1_C), 8, true, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_yuvo_t2_c, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_YUVO_T2_C), 8, true, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_yuvo_t5_c, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_YUVO_T5_C), 8, true, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_smto_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_SMTO_T1_C), 8, true, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_smto_t4_c, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_SMTO_T4_C), 8, true, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_smto_t6_c, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_SMTO_T6_C), 8, true, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(l23_dbgo_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L23_IMG2_DBGO_T1_C), 8, true, 0x2, SLAVE_LARB(23)), |
| DEFINE_MNODE(mraw0_lsci_m1, |
| MASTER_LARB_PORT(M4U_PORT_L25_CAM_MRAW0_LSCI_M1), 8, false, 0x1, SLAVE_LARB(25)), |
| DEFINE_MNODE(mraw0_cqi_m1, |
| MASTER_LARB_PORT(M4U_PORT_L25_CAM_MRAW0_CQI_M1), 8, false, 0x1, SLAVE_LARB(25)), |
| DEFINE_MNODE(mraw0_cqi_m2, |
| MASTER_LARB_PORT(M4U_PORT_L25_CAM_MRAW0_CQI_M2), 8, false, 0x1, SLAVE_LARB(25)), |
| DEFINE_MNODE(mraw0_imgo_m1, |
| MASTER_LARB_PORT(M4U_PORT_L25_CAM_MRAW0_IMGO_M1), 9, true, 0x1, SLAVE_LARB(25)), |
| DEFINE_MNODE(mraw0_imgbo_m1, |
| MASTER_LARB_PORT(M4U_PORT_L25_CAM_MRAW0_IMGBO_M1), 9, true, 0x1, SLAVE_LARB(25)), |
| DEFINE_MNODE(mraw2_lsci_m1, |
| MASTER_LARB_PORT(M4U_PORT_L25_CAM_MRAW2_LSCI_M1), 8, false, 0x1, SLAVE_LARB(25)), |
| DEFINE_MNODE(mraw2_cqi_m1, |
| MASTER_LARB_PORT(M4U_PORT_L25_CAM_MRAW2_CQI_M1), 8, false, 0x1, SLAVE_LARB(25)), |
| DEFINE_MNODE(mraw2_cqi_m2, |
| MASTER_LARB_PORT(M4U_PORT_L25_CAM_MRAW2_CQI_M2), 8, false, 0x1, SLAVE_LARB(25)), |
| DEFINE_MNODE(mraw2_imgo_m1, |
| MASTER_LARB_PORT(M4U_PORT_L25_CAM_MRAW2_IMGO_M1), 9, true, 0x1, SLAVE_LARB(25)), |
| DEFINE_MNODE(mraw2_imgbo_m1, |
| MASTER_LARB_PORT(M4U_PORT_L25_CAM_MRAW2_IMGBO_M1), 9, true, 0x1, SLAVE_LARB(25)), |
| DEFINE_MNODE(mraw0_afo_m1, |
| MASTER_LARB_PORT(M4U_PORT_L25_CAM_MRAW0_AFO_M1), 9, true, 0x1, SLAVE_LARB(25)), |
| DEFINE_MNODE(pdai_a_0, |
| MASTER_LARB_PORT(M4U_PORT_L25_CAM_PDAI_A0), 8, false, 0x1, SLAVE_LARB(25)), |
| DEFINE_MNODE(pdai_a_1, |
| MASTER_LARB_PORT(M4U_PORT_L25_CAM_PDAI_A1), 8, false, 0x1, SLAVE_LARB(25)), |
| DEFINE_MNODE(pdao_a, |
| MASTER_LARB_PORT(M4U_PORT_L25_CAM_PDAO_A), 9, true, 0x1, SLAVE_LARB(25)), |
| DEFINE_MNODE(l29_yuvo_r1, |
| MASTER_LARB_PORT(M4U_PORT_L29_CAM3_YUVO_R1), 9, true, 0x1, SLAVE_LARB(29)), |
| DEFINE_MNODE(l29_yuvo_r3, |
| MASTER_LARB_PORT(M4U_PORT_L29_CAM3_YUVO_R3), 9, true, 0x1, SLAVE_LARB(29)), |
| DEFINE_MNODE(l29_yuvco_r1, |
| MASTER_LARB_PORT(M4U_PORT_L29_CAM3_YUVCO_R1), 9, true, 0x1, SLAVE_LARB(29)), |
| DEFINE_MNODE(l29_yuvo_r2, |
| MASTER_LARB_PORT(M4U_PORT_L29_CAM3_YUVO_R2), 9, true, 0x1, SLAVE_LARB(29)), |
| DEFINE_MNODE(l29_rzh1n2to_r1, |
| MASTER_LARB_PORT(M4U_PORT_L29_CAM3_RZH1N2TO_R1), 9, true, 0x1, SLAVE_LARB(29)), |
| DEFINE_MNODE(l29_drzs4no_r1, |
| MASTER_LARB_PORT(M4U_PORT_L29_CAM3_DRZS4NO_R1), 9, true, 0x1, SLAVE_LARB(29)), |
| DEFINE_MNODE(l29_tncso_r1, |
| MASTER_LARB_PORT(M4U_PORT_L29_CAM3_TNCSO_R1), 9, true, 0x1, SLAVE_LARB(29)), |
| DEFINE_MNODE(l30_yuvo_r1, |
| MASTER_LARB_PORT(M4U_PORT_L30_CAM3_YUVO_R1), 9, true, 0x1, SLAVE_LARB(30)), |
| DEFINE_MNODE(l30_yuvo_r3, |
| MASTER_LARB_PORT(M4U_PORT_L30_CAM3_YUVO_R3), 9, true, 0x1, SLAVE_LARB(30)), |
| DEFINE_MNODE(l30_yuvco_r1, |
| MASTER_LARB_PORT(M4U_PORT_L30_CAM3_YUVCO_R1), 9, true, 0x1, SLAVE_LARB(30)), |
| DEFINE_MNODE(l30_yuvo_r2, |
| MASTER_LARB_PORT(M4U_PORT_L30_CAM3_YUVO_R2), 9, true, 0x1, SLAVE_LARB(30)), |
| DEFINE_MNODE(l30_rzh1n2to_r1, |
| MASTER_LARB_PORT(M4U_PORT_L30_CAM3_RZH1N2TO_R1), 9, true, 0x1, SLAVE_LARB(30)), |
| DEFINE_MNODE(l30_drzs4no_r1, |
| MASTER_LARB_PORT(M4U_PORT_L30_CAM3_DRZS4NO_R1), 9, true, 0x1, SLAVE_LARB(30)), |
| DEFINE_MNODE(l30_tncso_r1, |
| MASTER_LARB_PORT(M4U_PORT_L30_CAM3_TNCSO_R1), 9, true, 0x1, SLAVE_LARB(30)), |
| DEFINE_MNODE(l27_imgo_r1, |
| MASTER_LARB_PORT(M4U_PORT_L27_CAM2_IMGP_R1), 9, true, 0x1, SLAVE_LARB(27)), |
| DEFINE_MNODE(l27_cqi_r1, |
| MASTER_LARB_PORT(M4U_PORT_L27_CAM2_CQI_R1), 8, false, 0x1, SLAVE_LARB(27)), |
| DEFINE_MNODE(l27_cqi_r2, |
| MASTER_LARB_PORT(M4U_PORT_L27_CAM2_CQI_R2), 8, false, 0x1, SLAVE_LARB(27)), |
| DEFINE_MNODE(l27_bpci_r1, |
| MASTER_LARB_PORT(M4U_PORT_L27_CAM2_BPCI_R1), 8, false, 0x1, SLAVE_LARB(27)), |
| DEFINE_MNODE(l27_lsci_r1, |
| MASTER_LARB_PORT(M4U_PORT_L27_CAM2_LSCI_R1), 8, false, 0x1, SLAVE_LARB(27)), |
| DEFINE_MNODE(l27_rawi_r2, |
| MASTER_LARB_PORT(M4U_PORT_L27_CAM2_RAWI_R2), 8, false, 0x1, SLAVE_LARB(27)), |
| DEFINE_MNODE(l27_rawi_r3, |
| MASTER_LARB_PORT(M4U_PORT_L27_CAM2_RAWI_R3), 8, false, 0x1, SLAVE_LARB(27)), |
| DEFINE_MNODE(l27_ufdi_r2, |
| MASTER_LARB_PORT(M4U_PORT_L27_CAM2_UFDI_R2), 8, false, 0x1, SLAVE_LARB(27)), |
| DEFINE_MNODE(l27_ufdi_r3, |
| MASTER_LARB_PORT(M4U_PORT_L27_CAM2_UFDI_R3), 8, false, 0x1, SLAVE_LARB(27)), |
| DEFINE_MNODE(l27_rawi_r4, |
| MASTER_LARB_PORT(M4U_PORT_L27_CAM2_RAWI_R4), 8, false, 0x1, SLAVE_LARB(27)), |
| DEFINE_MNODE(l27_rawi_r5, |
| MASTER_LARB_PORT(M4U_PORT_L27_CAM2_RAWI_R5), 8, false, 0x1, SLAVE_LARB(27)), |
| DEFINE_MNODE(l27_aai_r1, |
| MASTER_LARB_PORT(M4U_PORT_L27_CAM2_AAI_R1), 8, false, 0x1, SLAVE_LARB(27)), |
| DEFINE_MNODE(l27_ufdi_r5, |
| MASTER_LARB_PORT(M4U_PORT_L27_CAM2_UFDI_R5), 8, false, 0x1, SLAVE_LARB(27)), |
| DEFINE_MNODE(l27_fho_r1, |
| MASTER_LARB_PORT(M4U_PORT_L27_CAM2_FHO_R1), 9, true, 0x1, SLAVE_LARB(27)), |
| DEFINE_MNODE(l27_aao_r1, |
| MASTER_LARB_PORT(M4U_PORT_L27_CAM2_AAO_R1), 9, true, 0x1, SLAVE_LARB(27)), |
| DEFINE_MNODE(l27_tsfso_r1, |
| MASTER_LARB_PORT(M4U_PORT_L27_CAM2_TSFSO_R1), 9, true, 0x1, SLAVE_LARB(27)), |
| DEFINE_MNODE(l27_flko_r1, |
| MASTER_LARB_PORT(M4U_PORT_L27_CAM2_FLKO_R1), 9, true, 0x1, SLAVE_LARB(27)), |
| DEFINE_MNODE(camsv_cqi_e1, |
| MASTER_LARB_PORT(M4U_PORT_L13_CAM1_CAMSV_CQI_E1), 8, false, 0x1, SLAVE_LARB(13)), |
| DEFINE_MNODE(camsv_cqi_e2, |
| MASTER_LARB_PORT(M4U_PORT_L13_CAM1_CAMSV_CQI_E2), 8, false, 0x1, SLAVE_LARB(13)), |
| DEFINE_MNODE(gcamsv_a_imgo_1, |
| MASTER_LARB_PORT(M4U_PORT_L13_CAM1_GCAMSV_A_IMGO_1), 9, true, 0x1, SLAVE_LARB(13)), |
| DEFINE_MNODE(gcamsv_c_imgo_1, |
| MASTER_LARB_PORT(M4U_PORT_L13_CAM1_GCAMSV_C_IMGO_1), 9, true, 0x1, SLAVE_LARB(13)), |
| DEFINE_MNODE(gcamsv_a_imgo_2, |
| MASTER_LARB_PORT(M4U_PORT_L13_CAM1_GCAMSV_A_IMGO_2), 9, true, 0x1, SLAVE_LARB(13)), |
| DEFINE_MNODE(gcamsv_c_imgo_2, |
| MASTER_LARB_PORT(M4U_PORT_L13_CAM1_GCAMSV_C_IMGO_2), 9, true, 0x1, SLAVE_LARB(13)), |
| DEFINE_MNODE(pdai_a_0, |
| MASTER_LARB_PORT(M4U_PORT_L13_CAM1_PDAI_A_0), 8, false, 0x1, SLAVE_LARB(13)), |
| DEFINE_MNODE(pdai_a_1, |
| MASTER_LARB_PORT(M4U_PORT_L13_CAM1_PDAI_A_1), 8, false, 0x1, SLAVE_LARB(13)), |
| DEFINE_MNODE(camsv_cqi_b_e1, |
| MASTER_LARB_PORT(M4U_PORT_L13_CAM1_CAMSV_CQI_B_E1), 8, false, 0x1, SLAVE_LARB(13)), |
| DEFINE_MNODE(camsv_cqi_b_e2, |
| MASTER_LARB_PORT(M4U_PORT_L13_CAM1_CAMSV_CQI_B_E2), 8, false, 0x1, SLAVE_LARB(13)), |
| DEFINE_MNODE(camsv_cqi_c_e1, |
| MASTER_LARB_PORT(M4U_PORT_L13_CAM1_CAMSV_CQI_C_E1), 8, false, 0x1, SLAVE_LARB(13)), |
| DEFINE_MNODE(camsv_cqi_c_e2, |
| MASTER_LARB_PORT(M4U_PORT_L13_CAM1_CAMSV_CQI_C_E2), 8, false, 0x1, SLAVE_LARB(13)), |
| DEFINE_MNODE(gcamsv_e_imgo_1, |
| MASTER_LARB_PORT(M4U_PORT_L13_CAM1_GCAMSV_E_IMGO_1), 9, true, 0x1, SLAVE_LARB(13)), |
| DEFINE_MNODE(gcamsv_e_imgo_2, |
| MASTER_LARB_PORT(M4U_PORT_L13_CAM1_GCAMSV_E_IMGO_2), 9, true, 0x1, SLAVE_LARB(13)), |
| DEFINE_MNODE(gcamsv_a_ufeo_1, |
| MASTER_LARB_PORT(M4U_PORT_L13_CAM1_GCAMSV_A_UFEO_1), 9, true, 0x1, SLAVE_LARB(13)), |
| DEFINE_MNODE(gcamsv_c_ufeo_1, |
| MASTER_LARB_PORT(M4U_PORT_L13_CAM1_GCAMSV_C_UFEO_1), 9, true, 0x1, SLAVE_LARB(13)), |
| DEFINE_MNODE(gcamsv_a_ufeo_2, |
| MASTER_LARB_PORT(M4U_PORT_L13_CAM1_GCAMSV_A_UFEO_2), 9, true, 0x1, SLAVE_LARB(13)), |
| DEFINE_MNODE(gcamsv_c_ufeo_2, |
| MASTER_LARB_PORT(M4U_PORT_L13_CAM1_GCAMSV_C_UFEO_2), 9, true, 0x1, SLAVE_LARB(13)), |
| DEFINE_MNODE(gcamsv_e_ufeo_1, |
| MASTER_LARB_PORT(M4U_PORT_L13_CAM1_GCAMSV_E_UFEO_1), 9, true, 0x1, SLAVE_LARB(13)), |
| DEFINE_MNODE(gcamsv_e_ufeo_2, |
| MASTER_LARB_PORT(M4U_PORT_L13_CAM1_GCAMSV_E_UFEO_2), 9, true, 0x1, SLAVE_LARB(13)), |
| DEFINE_MNODE(gcamsv_g_imgo_1, |
| MASTER_LARB_PORT(M4U_PORT_L13_CAM1_GCAMSV_G_IMGO_1), 9, true, 0x1, SLAVE_LARB(13)), |
| DEFINE_MNODE(gcamsv_g_imgo_2, |
| MASTER_LARB_PORT(M4U_PORT_L13_CAM1_GCAMSV_G_IMGO_2), 9, true, 0x1, SLAVE_LARB(13)), |
| DEFINE_MNODE(pdao_a, |
| MASTER_LARB_PORT(M4U_PORT_L13_CAM1_PDAO_A), 9, true, 0x1, SLAVE_LARB(13)), |
| DEFINE_MNODE(pdao_c, |
| MASTER_LARB_PORT(M4U_PORT_L13_CAM1_PDAO_C), 9, true, 0x1, SLAVE_LARB(13)), |
| DEFINE_MNODE(hw_mini_mdp_r0_ext, |
| MASTER_LARB_PORT(M4U_PORT_L6_VDEC_MINI_MDP_R0_EXT), 8, false, 0x1, SLAVE_LARB(6)), |
| DEFINE_MNODE(hw_mini_mdp_w0_ext, |
| MASTER_LARB_PORT(M4U_PORT_L6_VDEC_MINI_MDP_W0_EXT), 9, true, 0x1, SLAVE_LARB(6)), |
| DEFINE_MNODE(hw_mini_mdp_r1_ext, |
| MASTER_LARB_PORT(M4U_PORT_L6_VDEC_MINI_MDP_R1_EXT), 8, false, 0x1, SLAVE_LARB(6)), |
| DEFINE_MNODE(hw_mini_mdp_w1_ext, |
| MASTER_LARB_PORT(M4U_PORT_L6_VDEC_MINI_MDP_W1_EXT), 9, true, 0x1, SLAVE_LARB(6)), |
| DEFINE_MNODE(l1_disp_ovl0_1, |
| MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL0_1), 8, false, 0x12, SLAVE_LARB(1)), |
| DEFINE_MNODE(l1_disp_ovl0_2L_1, |
| MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL0_2L_1), 8, false, 0x12, SLAVE_LARB(1)), |
| DEFINE_MNODE(l1_disp_ovl1_2L_1, |
| MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL1_2L_1), 8, false, 0x12, SLAVE_LARB(1)), |
| DEFINE_MNODE(l1_disp_ovl0_2L_NWCG_1, |
| MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL0_2L_NWCG_1), 8, false, 0x12, SLAVE_LARB(1)), |
| DEFINE_MNODE(l1_disp_ovl1_2L_NWCG_1, |
| MASTER_LARB_PORT(M4U_PORT_L1_DISP_OVL1_2L_NWCG_1), 9, true, 0x12, SLAVE_LARB(1)), |
| DEFINE_MNODE(l1_disp_rdma1, |
| MASTER_LARB_PORT(M4U_PORT_L1_DISP_RDMA1), 8, false, 0x12, SLAVE_LARB(1)), |
| DEFINE_MNODE(l1_disp_wdma1, |
| MASTER_LARB_PORT(M4U_PORT_L1_DISP_WDMA1), 9, true, 0x12, SLAVE_LARB(1)), |
| DEFINE_MNODE(l1_disp_fake1, |
| MASTER_LARB_PORT(M4U_PORT_L1_DISP_FAKE1), 8, false, 0x12, SLAVE_LARB(1)), |
| DEFINE_MNODE(l20_disp_postmask0, |
| MASTER_LARB_PORT(M4U_PORT_L20_DISP_POSTMASK0), 8, false, 0x12, SLAVE_LARB(20)), |
| DEFINE_MNODE(l20_dmdp_rdma0, |
| MASTER_LARB_PORT(M4U_PORT_L20_DMDP_RDMA0), 8, false, 0x12, SLAVE_LARB(20)), |
| DEFINE_MNODE(l20_disp_ovl0_hdr, |
| MASTER_LARB_PORT(M4U_PORT_L20_DISP_OVL0_HDR), 7, false, 0x12, SLAVE_LARB(20)), |
| DEFINE_MNODE(l20_disp_ovl0_2L_hdr, |
| MASTER_LARB_PORT(M4U_PORT_L20_DISP_OVL0_2L_HDR), 7, false, 0x12, SLAVE_LARB(20)), |
| DEFINE_MNODE(l20_disp_ovl1_2L_hdr, |
| MASTER_LARB_PORT(M4U_PORT_L20_DISP_OVL1_2L_HDR), 8, true, 0x12, SLAVE_LARB(20)), |
| DEFINE_MNODE(l20_disp_ovl0_2L_NWCG_hdr, |
| MASTER_LARB_PORT(M4U_PORT_L20_DISP_OVL0_2L_NWCG_HDR), 7, false, 0x12, SLAVE_LARB(20)), |
| DEFINE_MNODE(l20_disp_ovl1_2L_NWCG_hdr, |
| MASTER_LARB_PORT(M4U_PORT_L20_DISP_OVL1_2L_NWCG_HDR), 7, false, 0x12, SLAVE_LARB(20)), |
| DEFINE_MNODE(l20_disp_ovl0_0, |
| MASTER_LARB_PORT(M4U_PORT_L20_DISP_OVL0_0), 8, false, 0x12, SLAVE_LARB(20)), |
| DEFINE_MNODE(l20_disp_ovl0_2L_0, |
| MASTER_LARB_PORT(M4U_PORT_L20_DISP_OVL0_2L_0), 8, false, 0x12, SLAVE_LARB(20)), |
| DEFINE_MNODE(l20_disp_ovl1_2L_0, |
| MASTER_LARB_PORT(M4U_PORT_L20_DISP_OVL1_2L_0), 8, false, 0x12, SLAVE_LARB(20)), |
| DEFINE_MNODE(l20_disp_ovl0_2L_NWCG_0, |
| MASTER_LARB_PORT(M4U_PORT_L20_DISP_OVL0_2L_NWCG_0), 8, false, 0x12, SLAVE_LARB(20)), |
| DEFINE_MNODE(l20_disp_ovl1_2L_NWCG_0, |
| MASTER_LARB_PORT(M4U_PORT_L20_DISP_OVL1_2L_NWCG_0), 8, false, 0x12, SLAVE_LARB(20)), |
| DEFINE_MNODE(l20_disp_rdma0, |
| MASTER_LARB_PORT(M4U_PORT_L20_DISP_RDMA0), 8, false, 0x12, SLAVE_LARB(20)), |
| DEFINE_MNODE(l20_disp_wdma0, |
| MASTER_LARB_PORT(M4U_PORT_L20_DISP_WDMA0), 9, true, 0x12, SLAVE_LARB(20)), |
| DEFINE_MNODE(l20_disp_ufbc_wdma0, |
| MASTER_LARB_PORT(M4U_PORT_L20_DISP_UFBC_WDMA0), 9, true, 0x12, SLAVE_LARB(20)), |
| DEFINE_MNODE(l20_disp_fake0, |
| MASTER_LARB_PORT(M4U_PORT_L20_DISP_FAKE0), 8, false, 0x12, SLAVE_LARB(20)), |
| DEFINE_MNODE(mdp_rdma1, |
| MASTER_LARB_PORT(M4U_PORT_L3_MDP_RDMA1), 8, false, 0x11, SLAVE_LARB(3)), |
| DEFINE_MNODE(mdp_rdma3, |
| MASTER_LARB_PORT(M4U_PORT_L3_MDP_RDMA3), 8, false, 0x11, SLAVE_LARB(3)), |
| DEFINE_MNODE(mdp_wrot1, |
| MASTER_LARB_PORT(M4U_PORT_L3_MDP_WROT1), 9, true, 0x11, SLAVE_LARB(3)), |
| DEFINE_MNODE(mdp_wrot3, |
| MASTER_LARB_PORT(M4U_PORT_L3_MDP_WROT3), 9, true, 0x11, SLAVE_LARB(3)), |
| DEFINE_MNODE(l3_disp_fake1, |
| MASTER_LARB_PORT(M4U_PORT_L3_MDP_DISP_FAKE1), 8, false, 0x11, SLAVE_LARB(3)), |
| DEFINE_MNODE(mdp_filmgrain1, |
| MASTER_LARB_PORT(M4U_PORT_L3_MDP_FILMGRAIN1), 8, false, 0x11, SLAVE_LARB(3)), |
| DEFINE_MNODE(mdp_filmgrain3, |
| MASTER_LARB_PORT(M4U_PORT_L3_MDP_FILMGRAIN3), 8, false, 0x11, SLAVE_LARB(3)), |
| DEFINE_MNODE(mdp_wdma1, |
| MASTER_LARB_PORT(M4U_PORT_L3_MDP_WDMA1), 9, true, 0x11, SLAVE_LARB(3)), |
| DEFINE_MNODE(mdp_wdma3, |
| MASTER_LARB_PORT(M4U_PORT_L3_MDP_WDMA3), 9, true, 0x11, SLAVE_LARB(3)), |
| DEFINE_MNODE(hw_vdec_mc_ext, |
| MASTER_LARB_PORT(M4U_PORT_L4_VDEC_MC_EXT), 6, false, 0x11, SLAVE_LARB(4)), |
| DEFINE_MNODE(hw_vdec_ufo_ext, |
| MASTER_LARB_PORT(M4U_PORT_L4_VDEC_UFO_EXT), 7, false, 0x11, SLAVE_LARB(4)), |
| DEFINE_MNODE(hw_vdec_pp_ext, |
| MASTER_LARB_PORT(M4U_PORT_L4_VDEC_PP_EXT), 8, true, 0x11, SLAVE_LARB(4)), |
| DEFINE_MNODE(hw_vdec_pred_rd_ext, |
| MASTER_LARB_PORT(M4U_PORT_L4_VDEC_PRED_RD_EXT), 7, false, 0x11, SLAVE_LARB(4)), |
| DEFINE_MNODE(hw_vdec_pred_wr_ext, |
| MASTER_LARB_PORT(M4U_PORT_L4_VDEC_PRED_WR_EXT), 7, false, 0x11, SLAVE_LARB(4)), |
| DEFINE_MNODE(hw_vdec_ppwrap_ext, |
| MASTER_LARB_PORT(M4U_PORT_L4_VDEC_PPWRAP_EXT), 7, false, 0x11, SLAVE_LARB(4)), |
| DEFINE_MNODE(hw_vdec_tile_ext, |
| MASTER_LARB_PORT(M4U_PORT_L4_VDEC_TILE_EXT), 7, false, 0x11, SLAVE_LARB(4)), |
| DEFINE_MNODE(hw_vdec_vld_ext, |
| MASTER_LARB_PORT(M4U_PORT_L4_VDEC_VLD_EXT), 7, false, 0x11, SLAVE_LARB(4)), |
| DEFINE_MNODE(hw_vdec_vld2_ext, |
| MASTER_LARB_PORT(M4U_PORT_L4_VDEC_VLD2_EXT), 7, false, 0x11, SLAVE_LARB(4)), |
| DEFINE_MNODE(hw_vdec_avc_mv_ext, |
| MASTER_LARB_PORT(M4U_PORT_L4_VDEC_AVC_MV_EXT), 6, false, 0x11, SLAVE_LARB(4)), |
| DEFINE_MNODE(hw_vdec_ufo_ext_c, |
| MASTER_LARB_PORT(M4U_PORT_L4_VDEC_UFO_EXT_C), 7, false, 0x11, SLAVE_LARB(4)), |
| DEFINE_MNODE(l8_venc_rcpu, |
| MASTER_LARB_PORT(M4U_PORT_L8_VENC_RCPU_MDP), 7, false, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_venc_rec, |
| MASTER_LARB_PORT(M4U_PORT_L8_VENC_REC_MDP), 8, true, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_venc_bsdma, |
| MASTER_LARB_PORT(M4U_PORT_L8_VENC_BSDMA_MDP), 8, true, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_venc_sv_comv, |
| MASTER_LARB_PORT(M4U_PORT_L8_VENC_SV_COMV_MDP), 8, true, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_venc_rd_comv, |
| MASTER_LARB_PORT(M4U_PORT_L8_VENC_RD_COMV_MDP), 7, false, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_venc_nbm_rdma, |
| MASTER_LARB_PORT(M4U_PORT_L8_VENC_NBM_RDMA_MDP), 7, false, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_venc_nbm_rdma_lite, |
| MASTER_LARB_PORT(M4U_PORT_L8_VENC_NBM_RDMA_LITE_MDP), 7, false, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_jpgenc_y_rdma, |
| MASTER_LARB_PORT(M4U_PORT_L8_JPGENC_Y_RDMA_MDP), 7, false, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_jpgenc_c_rdma, |
| MASTER_LARB_PORT(M4U_PORT_L8_JPGENC_C_RDMA_MDP), 7, false, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_jpgenc_q_table, |
| MASTER_LARB_PORT(M4U_PORT_L8_JPGENC_Q_TABLE_MDP), 7, false, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_venc_sub_w_luma, |
| MASTER_LARB_PORT(M4U_PORT_L8_VENC_SUB_W_LUMA_MDP), 7, false, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_venc_fcs_nbm_rdma, |
| MASTER_LARB_PORT(M4U_PORT_L8_VENC_FCS_NBM_RDMA_MDP), 7, false, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_venc_ec_wpp_bsdma, |
| MASTER_LARB_PORT(M4U_PORT_L8_VENC_EC_WPP_BSDMA_MDP), 7, false, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_venc_ec_wpp_rdma, |
| MASTER_LARB_PORT(M4U_PORT_L8_VENC_EC_WPP_RDMA_MDP), 7, false, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_venc_db_sysram_wdma, |
| MASTER_LARB_PORT(M4U_PORT_L8_VENC_DB_SYSRAM_WDMA_MDP), 7, false, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_venc_db_sysram_rdma, |
| MASTER_LARB_PORT(M4U_PORT_L8_VENC_DB_SYSRAM_RDMA_MDP), 7, false, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_jpgenc_bsdma, |
| MASTER_LARB_PORT(M4U_PORT_L8_JPGENC_BSDMA_MDP), 8, true, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_jpgdec_wdma_0, |
| MASTER_LARB_PORT(M4U_PORT_L8_JPGDEC_WDMA_0_MDP), 8, true, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_jpgdec_bsdma_0, |
| MASTER_LARB_PORT(M4U_PORT_L8_JPGDEC_BSDMA_0_MDP), 7, false, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_venc_nbm_wdma, |
| MASTER_LARB_PORT(M4U_PORT_L8_VENC_NBM_WDMA_MDP), 8, true, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_venc_nbm_wdma_lite, |
| MASTER_LARB_PORT(M4U_PORT_L8_VENC_NBM_WDMA_LITE_MDP), 8, true, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_venc_cur_luma, |
| MASTER_LARB_PORT(M4U_PORT_L8_VENC_CUR_LUMA_MDP), 7, false, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_venc_cur_chroma, |
| MASTER_LARB_PORT(M4U_PORT_L8_VENC_CUR_CHROMA_MDP), 7, false, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_venc_ref_luma, |
| MASTER_LARB_PORT(M4U_PORT_L8_VENC_REF_LUMA_MDP), 7, false, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_venc_ref_chroma, |
| MASTER_LARB_PORT(M4U_PORT_L8_VENC_REF_CHROMA_MDP), 7, false, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_venc_sub_r_luma, |
| MASTER_LARB_PORT(M4U_PORT_L8_VENC_SUB_R_LUMA_MDP), 7, false, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_venc_fcs_nbm_wdma, |
| MASTER_LARB_PORT(M4U_PORT_L8_VENC_FCS_NBM_WDMA_MDP), 8, true, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_jpgdec_wdma_1, |
| MASTER_LARB_PORT(M4U_PORT_L8_JPGDEC_WDMA_1_MDP), 8, true, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_jpgdec_bsdma_1, |
| MASTER_LARB_PORT(M4U_PORT_L8_JPGDEC_BSDMA_1_MDP), 7, false, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_jpgdec_huff_offset_1, |
| MASTER_LARB_PORT(M4U_PORT_L8_JPGDEC_HUFF_OFFSET_1_MDP), 8, true, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(l8_jpgdec_huff_offset_0, |
| MASTER_LARB_PORT(M4U_PORT_L8_JPGDEC_HUFF_OFFSET_0_MDP), 8, true, 0x11, SLAVE_LARB(8)), |
| DEFINE_MNODE(imgadl_0_cqi_e1, |
| MASTER_LARB_PORT(M4U_PORT_L18_IMGADL0_CQI_E1), 7, false, 0x12, SLAVE_LARB(18)), |
| DEFINE_MNODE(imgadl_0_cqi_e2, |
| MASTER_LARB_PORT(M4U_PORT_L18_IMGADL0_CQI_E2), 7, false, 0x12, SLAVE_LARB(18)), |
| DEFINE_MNODE(imgadl_0_ipui_e1, |
| MASTER_LARB_PORT(M4U_PORT_L18_IMGADL0_IPUI_E1), 7, false, 0x12, SLAVE_LARB(18)), |
| DEFINE_MNODE(imgadl_0_ipuo_e1, |
| MASTER_LARB_PORT(M4U_PORT_L18_IMGADL0_IPUO_E1), 8, true, 0x12, SLAVE_LARB(18)), |
| DEFINE_MNODE(imgadl_1_cqi_e1, |
| MASTER_LARB_PORT(M4U_PORT_L18_IMGADL1_CQI_E1), 7, false, 0x12, SLAVE_LARB(18)), |
| DEFINE_MNODE(imgadl_1_cqi_e2, |
| MASTER_LARB_PORT(M4U_PORT_L18_IMGADL1_CQI_E2), 7, false, 0x12, SLAVE_LARB(18)), |
| DEFINE_MNODE(imgadl_1_ipui_e1, |
| MASTER_LARB_PORT(M4U_PORT_L18_IMGADL1_IPUI_E1), 7, false, 0x12, SLAVE_LARB(18)), |
| DEFINE_MNODE(imgadl_1_ipuo_e1, |
| MASTER_LARB_PORT(M4U_PORT_L18_IMGADL1_IPUO_E1), 8, true, 0x12, SLAVE_LARB(18)), |
| DEFINE_MNODE(vipi_d1, |
| MASTER_LARB_PORT(M4U_PORT_L15_IMG2_VIP1_D1), 7, false, 0x12, SLAVE_LARB(15)), |
| DEFINE_MNODE(vipbi_d1, |
| MASTER_LARB_PORT(M4U_PORT_L15_IMG2_VIPBI_D1), 7, false, 0x12, SLAVE_LARB(15)), |
| DEFINE_MNODE(smti_d6, |
| MASTER_LARB_PORT(M4U_PORT_L15_IMG2_SMTI_D6), 7, false, 0x12, SLAVE_LARB(15)), |
| DEFINE_MNODE(tncsti_d1, |
| MASTER_LARB_PORT(M4U_PORT_L15_IMG2_TNCSTI_D1), 7, false, 0x12, SLAVE_LARB(15)), |
| DEFINE_MNODE(tncsti_d4, |
| MASTER_LARB_PORT(M4U_PORT_L15_IMG2_TNCSTI_D4), 7, false, 0x12, SLAVE_LARB(15)), |
| DEFINE_MNODE(smti_d4, |
| MASTER_LARB_PORT(M4U_PORT_L15_IMG2_SMTI_D4), 7, false, 0x12, SLAVE_LARB(15)), |
| DEFINE_MNODE(img3o_d1, |
| MASTER_LARB_PORT(M4U_PORT_L15_IMG2_IMG3O_D1), 8, true, 0x12, SLAVE_LARB(15)), |
| DEFINE_MNODE(img3bo_d1, |
| MASTER_LARB_PORT(M4U_PORT_L15_IMG2_IMG3BO_D1), 8, true, 0x12, SLAVE_LARB(15)), |
| DEFINE_MNODE(img3co_d1, |
| MASTER_LARB_PORT(M4U_PORT_L15_IMG2_IMG3CO_D1), 8, true, 0x12, SLAVE_LARB(15)), |
| DEFINE_MNODE(img2o_d1, |
| MASTER_LARB_PORT(M4U_PORT_L15_IMG2_IMG2O_D1), 8, true, 0x12, SLAVE_LARB(15)), |
| DEFINE_MNODE(smti_d9, |
| MASTER_LARB_PORT(M4U_PORT_L15_IMG2_SMTI_D9), 7, false, 0x12, SLAVE_LARB(15)), |
| DEFINE_MNODE(smto_d4, |
| MASTER_LARB_PORT(M4U_PORT_L15_IMG2_SMTO_D4), 8, true, 0x12, SLAVE_LARB(15)), |
| DEFINE_MNODE(feo_d1, |
| MASTER_LARB_PORT(M4U_PORT_L15_IMG2_FEO_D1), 8, true, 0x12, SLAVE_LARB(15)), |
| DEFINE_MNODE(tncso_d1, |
| MASTER_LARB_PORT(M4U_PORT_L15_IMG2_TNCSO_D1), 8, true, 0x12, SLAVE_LARB(15)), |
| DEFINE_MNODE(tncsto_d1, |
| MASTER_LARB_PORT(M4U_PORT_L15_IMG2_TNCSTO_D1), 8, true, 0x12, SLAVE_LARB(15)), |
| DEFINE_MNODE(smto_d6, |
| MASTER_LARB_PORT(M4U_PORT_L15_IMG2_SMTO_D6), 8, true, 0x12, SLAVE_LARB(15)), |
| DEFINE_MNODE(smto_d9, |
| MASTER_LARB_PORT(M4U_PORT_L15_IMG2_SMTO_D9), 8, true, 0x12, SLAVE_LARB(15)), |
| DEFINE_MNODE(tnco_d1, |
| MASTER_LARB_PORT(M4U_PORT_L15_IMG2_TNCO_D1), 8, true, 0x12, SLAVE_LARB(15)), |
| DEFINE_MNODE(tnco_d1_n, |
| MASTER_LARB_PORT(M4U_PORT_L15_IMG2_TNCO_D1_N), 8, true, 0x12, SLAVE_LARB(15)), |
| DEFINE_MNODE(fdvt_rda_0, |
| MASTER_LARB_PORT(M4U_PORT_L12_IPE_FDVT_RDA0), 7, false, 0x12, SLAVE_LARB(12)), |
| DEFINE_MNODE(fdvt_rdb_0, |
| MASTER_LARB_PORT(M4U_PORT_L12_IPE_FDVT_RDB0), 7, false, 0x12, SLAVE_LARB(12)), |
| DEFINE_MNODE(fdvt_wra_0, |
| MASTER_LARB_PORT(M4U_PORT_L12_IPE_FDVT_WRA0), 8, true, 0x12, SLAVE_LARB(12)), |
| DEFINE_MNODE(fdvt_wrb_0, |
| MASTER_LARB_PORT(M4U_PORT_L12_IPE_FDVT_WR0B), 8, true, 0x12, SLAVE_LARB(12)), |
| DEFINE_MNODE(me_rdma, |
| MASTER_LARB_PORT(M4U_PORT_L12_IPE_ME_RDMA), 7, false, 0x12, SLAVE_LARB(12)), |
| DEFINE_MNODE(me_wdma, |
| MASTER_LARB_PORT(M4U_PORT_L12_IPE_ME_WDMA), 8, true, 0x12, SLAVE_LARB(12)), |
| DEFINE_MNODE(dvs_rdma, |
| MASTER_LARB_PORT(M4U_PORT_L12_IPE_DVS_RDMA), 7, false, 0x12, SLAVE_LARB(12)), |
| DEFINE_MNODE(dvs_wdma, |
| MASTER_LARB_PORT(M4U_PORT_L12_IPE_DVS_WDMA), 8, true, 0x12, SLAVE_LARB(12)), |
| DEFINE_MNODE(dvp_rdma, |
| MASTER_LARB_PORT(M4U_PORT_L12_IPE_DVP_RDMA), 7, false, 0x12, SLAVE_LARB(12)), |
| DEFINE_MNODE(dvp_wdma, |
| MASTER_LARB_PORT(M4U_PORT_L12_IPE_DVP_WDMA), 8, true, 0x12, SLAVE_LARB(12)), |
| DEFINE_MNODE(fdvt_2nd_rda_0, |
| MASTER_LARB_PORT(M4U_PORT_L12_IPE_FDVT_2ND_RDA0), 7, false, 0x12, SLAVE_LARB(12)), |
| DEFINE_MNODE(fdvt_2nd_rdb_0, |
| MASTER_LARB_PORT(M4U_PORT_L12_IPE_FDVT_2ND_RDB0), 7, false, 0x12, SLAVE_LARB(12)), |
| DEFINE_MNODE(fdvt_2nd_wra_0, |
| MASTER_LARB_PORT(M4U_PORT_L12_IPE_FDVT_2ND_WRA0), 8, true, 0x12, SLAVE_LARB(12)), |
| DEFINE_MNODE(fdvt_2nd_wrb_0, |
| MASTER_LARB_PORT(M4U_PORT_L12_IPE_FDVT_2ND_WRB0), 8, true, 0x12, SLAVE_LARB(12)), |
| DEFINE_MNODE(dhzei_e1, |
| MASTER_LARB_PORT(M4U_PORT_L12_IPE_DHZEI_E1), 7, false, 0x12, SLAVE_LARB(12)), |
| DEFINE_MNODE(dhzeo_e1, |
| MASTER_LARB_PORT(M4U_PORT_L12_IPE_DHZEO_E1), 8, true, 0x12, SLAVE_LARB(12)), |
| DEFINE_MNODE(l22_wpe_rdma_0, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_WPE_RDMA0), 7, false, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_wpe_rdma_1, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_WPE_RDMA1), 6, false, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_wpe_rdma_4p_0, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_WPE_RDMA_4P0), 7, false, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_wpe_rdma_4p_1, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_WPE_RDMA_4P1), 6, false, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_wpe_cq0, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_WPE_CQ0), 7, false, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_wpe_cq1, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_WPE_CQ1), 7, false, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_pimgi_p1, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_PIMGI_P1), 7, false, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_pimgbi_p1, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_PIMGBI_P1), 7, false, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_pimgci_p1, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_PIMGCI_P1), 7, false, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_imgi_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_IMGI_T1_C), 7, false, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_imgbi_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_IMGBI_T1_C), 7, false, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_imgci_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_IMGCI_T1_C), 7, false, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_smti_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_SMTI_T1_C), 7, false, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_smti_t4_c, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_SMTI_T4_C), 7, false, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_smti_t6_c, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_SMTI_T6_C), 7, false, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_yuvo_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_YUVO_T1_C), 8, true, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_yuvbo_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_YUVBO_T1_C), 8, true, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_yuvco_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_YUVCO_T1_C), 8, true, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_wpe_wdma_0, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_WPE_WDMA0), 8, true, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_wpe_wdma_4p_0, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_WPE_WDMA_4P0), 8, true, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_wrot_p1, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_WROT_P1), 8, true, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_tccso_p1, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_TCCSO_P1), 8, true, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_tccsi_p1, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_TCCSI_P1), 7, false, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_timgo_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_TIMGO_T1_C), 8, true, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_yuvo_t2_c, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_YUVO_T2_C), 8, true, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_yuvo_t5_c, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_YUVO_T5_C), 8, true, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_smto_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_SMTO_T1_C), 8, true, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_smto_t4_c, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_SMTO_T4_C), 8, true, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_smto_t6_c, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_SMTO_T6_C), 8, true, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l22_dbgo_t1_c, |
| MASTER_LARB_PORT(M4U_PORT_L22_IMG2_DBGO_T1_C), 8, true, 0x12, SLAVE_LARB(22)), |
| DEFINE_MNODE(l14_gcamsv_b_imgo_1, |
| MASTER_LARB_PORT(M4U_PORT_L14_CAM1_GCAMSV_B_IMGO_1), 9, true, 0x11, SLAVE_LARB(14)), |
| DEFINE_MNODE(l14_gcamsv_b_imgo_2, |
| MASTER_LARB_PORT(M4U_PORT_L14_CAM1_GCAMSV_B_IMGO_2), 9, true, 0x11, SLAVE_LARB(14)), |
| DEFINE_MNODE(l14_scamsv_a_imgo_1, |
| MASTER_LARB_PORT(M4U_PORT_L14_CAM1_SCAMSV_A_IMGO_1), 9, true, 0x11, SLAVE_LARB(14)), |
| DEFINE_MNODE(l14_scamsv_a_imgo_2, |
| MASTER_LARB_PORT(M4U_PORT_L14_CAM1_SCAMSV_A_IMGO_2), 9, true, 0x11, SLAVE_LARB(14)), |
| DEFINE_MNODE(l14_scamsv_b_imgo_1, |
| MASTER_LARB_PORT(M4U_PORT_L14_CAM1_SCAMSV_B_IMGO_1), 9, true, 0x11, SLAVE_LARB(14)), |
| DEFINE_MNODE(l14_scamsv_b_imgo_2, |
| MASTER_LARB_PORT(M4U_PORT_L14_CAM1_SCAMSV_B_IMGO_2), 9, true, 0x11, SLAVE_LARB(14)), |
| DEFINE_MNODE(l14_pdai_b_0, |
| MASTER_LARB_PORT(M4U_PORT_L14_CAM1_PDAI_B_0), 8, false, 0x11, SLAVE_LARB(14)), |
| DEFINE_MNODE(l14_pdai_b_1, |
| MASTER_LARB_PORT(M4U_PORT_L14_CAM1_PDAI_B_1), 8, false, 0x11, SLAVE_LARB(14)), |
| DEFINE_MNODE(l14_gcamsv_d_imgo_1, |
| MASTER_LARB_PORT(M4U_PORT_L14_CAM1_GCAMSV_D_IMGO_1), 9, true, 0x11, SLAVE_LARB(14)), |
| DEFINE_MNODE(l14_gcamsv_d_imgo_2, |
| MASTER_LARB_PORT(M4U_PORT_L14_CAM1_GCAMSV_D_IMGO_2), 9, true, 0x11, SLAVE_LARB(14)), |
| DEFINE_MNODE(l14_gcamsv_f_imgo_1, |
| MASTER_LARB_PORT(M4U_PORT_L14_CAM1_GCAMSV_F_IMGO_1), 9, true, 0x11, SLAVE_LARB(14)), |
| DEFINE_MNODE(l14_gcamsv_f_imgo_2, |
| MASTER_LARB_PORT(M4U_PORT_L14_CAM1_GCAMSV_F_IMGO_2), 9, true, 0x11, SLAVE_LARB(14)), |
| DEFINE_MNODE(l14_gcamsv_h_imgo_1, |
| MASTER_LARB_PORT(M4U_PORT_L14_CAM1_GCAMSV_H_IMGO_1), 9, true, 0x11, SLAVE_LARB(14)), |
| DEFINE_MNODE(l14_gcamsv_h_imgo_2, |
| MASTER_LARB_PORT(M4U_PORT_L14_CAM1_GCAMSV_H_IMGO_2), 9, true, 0x11, SLAVE_LARB(14)), |
| DEFINE_MNODE(l14_gcamsv_b_ufeo_1, |
| MASTER_LARB_PORT(M4U_PORT_L14_CAM1_GCAMSV_B_UFEO_1), 9, true, 0x11, SLAVE_LARB(14)), |
| DEFINE_MNODE(l14_gcamsv_b_ufeo_2, |
| MASTER_LARB_PORT(M4U_PORT_L14_CAM1_GCAMSV_B_UFEO_2), 9, true, 0x11, SLAVE_LARB(14)), |
| DEFINE_MNODE(l14_gcamsv_d_ufeo_1, |
| MASTER_LARB_PORT(M4U_PORT_L14_CAM1_GCAMSV_D_UFEO_1), 9, true, 0x11, SLAVE_LARB(14)), |
| DEFINE_MNODE(l14_gcamsv_d_ufeo_2, |
| MASTER_LARB_PORT(M4U_PORT_L14_CAM1_GCAMSV_D_UFEO_2), 9, true, 0x11, SLAVE_LARB(14)), |
| DEFINE_MNODE(l14_pdao_b, |
| MASTER_LARB_PORT(M4U_PORT_L14_CAM1_PDAO_B), 9, true, 0x11, SLAVE_LARB(14)), |
| DEFINE_MNODE(l14_ipui, |
| MASTER_LARB_PORT(M4U_PORT_L14_CAM1_IPUI), 8, false, 0x11, SLAVE_LARB(14)), |
| DEFINE_MNODE(l14_ipuo, |
| MASTER_LARB_PORT(M4U_PORT_L14_CAM1_IPUO), 9, true, 0x11, SLAVE_LARB(14)), |
| DEFINE_MNODE(l14_ipu3o, |
| MASTER_LARB_PORT(M4U_PORT_L14_CAM1_IPU3O), 9, true, 0x11, SLAVE_LARB(14)), |
| DEFINE_MNODE(l14_fake, |
| MASTER_LARB_PORT(M4U_PORT_L14_CAM1_FAKE), 9, true, 0x11, SLAVE_LARB(14)), |
| DEFINE_MNODE(l26_mraw1_lsci_m1, |
| MASTER_LARB_PORT(M4U_PORT_L26_CAM_MRAW1_LSCI_M1), 8, false, 0x11, SLAVE_LARB(26)), |
| DEFINE_MNODE(l26_mraw1_cqi_m1, |
| MASTER_LARB_PORT(M4U_PORT_L26_CAM_MRAW1_CQI_M1), 8, false, 0x11, SLAVE_LARB(26)), |
| DEFINE_MNODE(l26_mraw1_cqi_m2, |
| MASTER_LARB_PORT(M4U_PORT_L26_CAM_MRAW1_CQI_M2), 8, false, 0x11, SLAVE_LARB(26)), |
| DEFINE_MNODE(l26_mraw1_imgo_m1, |
| MASTER_LARB_PORT(M4U_PORT_L26_CAM_MRAW1_IMGO_M1), 9, true, 0x11, SLAVE_LARB(26)), |
| DEFINE_MNODE(l26_mraw1_imgbo_m1, |
| MASTER_LARB_PORT(M4U_PORT_L26_CAM_MRAW1_IMGBO_M1), 9, true, 0x11, SLAVE_LARB(26)), |
| DEFINE_MNODE(l26_mraw3_lsci_m1, |
| MASTER_LARB_PORT(M4U_PORT_L26_CAM_MRAW3_LSCI_M1), 8, false, 0x11, SLAVE_LARB(26)), |
| DEFINE_MNODE(l26_mraw3_cqi_m1, |
| MASTER_LARB_PORT(M4U_PORT_L26_CAM_MRAW3_CQI_M1), 8, false, 0x11, SLAVE_LARB(26)), |
| DEFINE_MNODE(l26_mraw3_cqi_m2, |
| MASTER_LARB_PORT(M4U_PORT_L26_CAM_MRAW3_CQI_M2), 8, false, 0x11, SLAVE_LARB(26)), |
| DEFINE_MNODE(l26_mraw3_imgo_m1, |
| MASTER_LARB_PORT(M4U_PORT_L26_CAM_MRAW3_IMGO_M1), 9, true, 0x11, SLAVE_LARB(26)), |
| DEFINE_MNODE(l26_mraw3_imgbo_m1, |
| MASTER_LARB_PORT(M4U_PORT_L26_CAM_MRAW3_IMGBO_M1), 9, true, 0x11, SLAVE_LARB(26)), |
| DEFINE_MNODE(l26_mraw1_afo_m1, |
| MASTER_LARB_PORT(M4U_PORT_L26_CAM_MRAW1_AFO_M1), 9, true, 0x11, SLAVE_LARB(26)), |
| DEFINE_MNODE(l26_pdai_b_0, |
| MASTER_LARB_PORT(M4U_PORT_L26_CAM_PDAI_B0), 8, false, 0x11, SLAVE_LARB(26)), |
| DEFINE_MNODE(l26_pdai_b_1, |
| MASTER_LARB_PORT(M4U_PORT_L26_CAM_PDAI_B1), 8, false, 0x11, SLAVE_LARB(26)), |
| DEFINE_MNODE(l26_pdao_b, |
| MASTER_LARB_PORT(M4U_PORT_L26_CAM_PDAO_B), 9, true, 0x11, SLAVE_LARB(26)), |
| DEFINE_MNODE(l17_yuvo_r1, |
| MASTER_LARB_PORT(M4U_PORT_L17_CAM3_YUVO_R1), 9, true, 0x11, SLAVE_LARB(17)), |
| DEFINE_MNODE(l17_yuvo_r3, |
| MASTER_LARB_PORT(M4U_PORT_L17_CAM3_YUVO_R3), 9, true, 0x11, SLAVE_LARB(17)), |
| DEFINE_MNODE(l17_yuvco_r1, |
| MASTER_LARB_PORT(M4U_PORT_L17_CAM3_YUVCO_R1), 9, true, 0x11, SLAVE_LARB(17)), |
| DEFINE_MNODE(l17_yuvo_r2, |
| MASTER_LARB_PORT(M4U_PORT_L17_CAM3_YUVO_R2), 9, true, 0x11, SLAVE_LARB(17)), |
| DEFINE_MNODE(l17_rzh1n2to_r1, |
| MASTER_LARB_PORT(M4U_PORT_L17_CAM3_RZH1N2TO_R1), 9, true, 0x11, SLAVE_LARB(17)), |
| DEFINE_MNODE(l17_drzs4no_r1, |
| MASTER_LARB_PORT(M4U_PORT_L17_CAM3_DRZS4NO_R1), 9, true, 0x11, SLAVE_LARB(17)), |
| DEFINE_MNODE(l17_tncso_r1, |
| MASTER_LARB_PORT(M4U_PORT_L17_CAM3_TNCSO_R1), 9, true, 0x11, SLAVE_LARB(17)), |
| DEFINE_MNODE(l16_imgo_r1, |
| MASTER_LARB_PORT(M4U_PORT_L16_CAM2_IMGP_R1), 9, true, 0x11, SLAVE_LARB(16)), |
| DEFINE_MNODE(l16_cqi_r1, |
| MASTER_LARB_PORT(M4U_PORT_L16_CAM2_CQI_R1), 8, false, 0x11, SLAVE_LARB(16)), |
| DEFINE_MNODE(l16_cqi_r2, |
| MASTER_LARB_PORT(M4U_PORT_L16_CAM2_CQI_R2), 8, false, 0x11, SLAVE_LARB(16)), |
| DEFINE_MNODE(l16_bpci_r1, |
| MASTER_LARB_PORT(M4U_PORT_L16_CAM2_BPCI_R1), 8, false, 0x11, SLAVE_LARB(16)), |
| DEFINE_MNODE(l16_lsci_r1, |
| MASTER_LARB_PORT(M4U_PORT_L16_CAM2_LSCI_R1), 8, false, 0x11, SLAVE_LARB(16)), |
| DEFINE_MNODE(l16_rawi_r2, |
| MASTER_LARB_PORT(M4U_PORT_L16_CAM2_RAWI_R2), 8, false, 0x11, SLAVE_LARB(16)), |
| DEFINE_MNODE(l16_rawi_r3, |
| MASTER_LARB_PORT(M4U_PORT_L16_CAM2_RAWI_R3), 8, false, 0x11, SLAVE_LARB(16)), |
| DEFINE_MNODE(l16_ufdi_r2, |
| MASTER_LARB_PORT(M4U_PORT_L16_CAM2_UFDI_R2), 8, false, 0x11, SLAVE_LARB(16)), |
| DEFINE_MNODE(l16_ufdi_r3, |
| MASTER_LARB_PORT(M4U_PORT_L16_CAM2_UFDI_R3), 8, false, 0x11, SLAVE_LARB(16)), |
| DEFINE_MNODE(l16_rawi_r4, |
| MASTER_LARB_PORT(M4U_PORT_L16_CAM2_RAWI_R4), 8, false, 0x11, SLAVE_LARB(16)), |
| DEFINE_MNODE(l16_rawi_r5, |
| MASTER_LARB_PORT(M4U_PORT_L16_CAM2_RAWI_R5), 8, false, 0x11, SLAVE_LARB(16)), |
| DEFINE_MNODE(l16_aai_r1, |
| MASTER_LARB_PORT(M4U_PORT_L16_CAM2_AAI_R1), 8, false, 0x11, SLAVE_LARB(16)), |
| DEFINE_MNODE(l16_ufdi_r5, |
| MASTER_LARB_PORT(M4U_PORT_L16_CAM2_UFDI_R5), 8, false, 0x11, SLAVE_LARB(16)), |
| DEFINE_MNODE(l16_fho_r1, |
| MASTER_LARB_PORT(M4U_PORT_L16_CAM2_FHO_R1), 9, true, 0x11, SLAVE_LARB(16)), |
| DEFINE_MNODE(l16_aao_r1, |
| MASTER_LARB_PORT(M4U_PORT_L16_CAM2_AAO_R1), 9, true, 0x11, SLAVE_LARB(16)), |
| DEFINE_MNODE(l16_tsfso_r1, |
| MASTER_LARB_PORT(M4U_PORT_L16_CAM2_TSFSO_R1), 9, true, 0x11, SLAVE_LARB(16)), |
| DEFINE_MNODE(l16_flko_r1, |
| MASTER_LARB_PORT(M4U_PORT_L16_CAM2_FLKO_R1), 9, true, 0x11, SLAVE_LARB(16)), |
| DEFINE_MNODE(l28_imgo_r1, |
| MASTER_LARB_PORT(M4U_PORT_L28_CAM2_IMGP_R1), 9, true, 0x11, SLAVE_LARB(28)), |
| DEFINE_MNODE(l28_cqi_r1, |
| MASTER_LARB_PORT(M4U_PORT_L28_CAM2_CQI_R1), 8, false, 0x11, SLAVE_LARB(28)), |
| DEFINE_MNODE(l28_cqi_r2, |
| MASTER_LARB_PORT(M4U_PORT_L28_CAM2_CQI_R2), 8, false, 0x11, SLAVE_LARB(28)), |
| DEFINE_MNODE(l28_bpci_r1, |
| MASTER_LARB_PORT(M4U_PORT_L28_CAM2_BPCI_R1), 8, false, 0x11, SLAVE_LARB(28)), |
| DEFINE_MNODE(l28_lsci_r1, |
| MASTER_LARB_PORT(M4U_PORT_L28_CAM2_LSCI_R1), 8, false, 0x11, SLAVE_LARB(28)), |
| DEFINE_MNODE(l28_rawi_r2, |
| MASTER_LARB_PORT(M4U_PORT_L28_CAM2_RAWI_R2), 8, false, 0x11, SLAVE_LARB(28)), |
| DEFINE_MNODE(l28_rawi_r3, |
| MASTER_LARB_PORT(M4U_PORT_L28_CAM2_RAWI_R3), 8, false, 0x11, SLAVE_LARB(28)), |
| DEFINE_MNODE(l28_ufdi_r2, |
| MASTER_LARB_PORT(M4U_PORT_L28_CAM2_UFDI_R2), 8, false, 0x11, SLAVE_LARB(28)), |
| DEFINE_MNODE(l28_ufdi_r3, |
| MASTER_LARB_PORT(M4U_PORT_L28_CAM2_UFDI_R3), 8, false, 0x11, SLAVE_LARB(28)), |
| DEFINE_MNODE(l28_rawi_r4, |
| MASTER_LARB_PORT(M4U_PORT_L28_CAM2_RAWI_R4), 8, false, 0x11, SLAVE_LARB(28)), |
| DEFINE_MNODE(l28_rawi_r5, |
| MASTER_LARB_PORT(M4U_PORT_L28_CAM2_RAWI_R5), 8, false, 0x11, SLAVE_LARB(28)), |
| DEFINE_MNODE(l28_aai_r1, |
| MASTER_LARB_PORT(M4U_PORT_L28_CAM2_AAI_R1), 8, false, 0x11, SLAVE_LARB(28)), |
| DEFINE_MNODE(l28_ufdi_r5, |
| MASTER_LARB_PORT(M4U_PORT_L28_CAM2_UFDI_R5), 8, false, 0x11, SLAVE_LARB(28)), |
| DEFINE_MNODE(l28_fho_r1, |
| MASTER_LARB_PORT(M4U_PORT_L28_CAM2_FHO_R1), 9, true, 0x11, SLAVE_LARB(28)), |
| DEFINE_MNODE(l28_aao_r1, |
| MASTER_LARB_PORT(M4U_PORT_L28_CAM2_AAO_R1), 9, true, 0x11, SLAVE_LARB(28)), |
| DEFINE_MNODE(l28_tsfso_r1, |
| MASTER_LARB_PORT(M4U_PORT_L28_CAM2_TSFSO_R1), 9, true, 0x11, SLAVE_LARB(28)), |
| DEFINE_MNODE(l28_flko_r1, |
| MASTER_LARB_PORT(M4U_PORT_L28_CAM2_FLKO_R1), 9, true, 0x11, SLAVE_LARB(28)), |
| DEFINE_MNODE(ccui, |
| MASTER_LARB_PORT(M4U_PORT_L19_CAM_CCUI), 8, true, 0x11, SLAVE_LARB(19)), |
| DEFINE_MNODE(ccuo, |
| MASTER_LARB_PORT(M4U_PORT_L19_CAM_CCUO), 9, true, 0x11, SLAVE_LARB(19)), |
| DEFINE_MNODE(ccui2, |
| MASTER_LARB_PORT(M4U_PORT_L19_CAM_CCUI2), 8, true, 0x11, SLAVE_LARB(19)), |
| DEFINE_MNODE(ccuo2, |
| MASTER_LARB_PORT(M4U_PORT_L19_CAM_CCUO2), 9, true, 0x11, SLAVE_LARB(19)), |
| }; |
| static const char * const comm_muxes_mt6983[] = { "mm", "mdp" }; |
| static const char * const comm_icc_path_names_mt6983[] = { "icc-bw", "icc-bw" }; |
| static const char * const comm_icc_hrt_path_names_mt6983[] = { "icc-hrt-bw", "icc-hrt-bw" }; |
| static const struct mtk_mmqos_desc mmqos_desc_mt6983 = { |
| .nodes = node_descs_mt6983, |
| .num_nodes = ARRAY_SIZE(node_descs_mt6983), |
| .comm_muxes = comm_muxes_mt6983, |
| .comm_icc_path_names = comm_icc_path_names_mt6983, |
| .comm_icc_hrt_path_names = comm_icc_hrt_path_names_mt6983, |
| .max_ratio = 64, |
| .hrt = { |
| .hrt_bw = {5640, 0, 0}, |
| .hrt_total_bw = 51200, /* Todo: Use DRAMC API 6400*4(channel)*2(io width)*/ |
| .md_speech_bw = { 6265, 5640}, |
| .hrt_ratio = {1000, 860, 880, 880}, /* MD, CAM, DISP, MML */ |
| .blocking = true, |
| .emi_ratio = 680, |
| }, |
| .comm_port_channels = { |
| { 0x1, 0x2, 0x2, 0x2, 0x1, 0x2, 0x1, 0x1, 0x3 }, |
| { 0x2, 0x2, 0x1, 0x1, 0x1, 0x2, 0x1, 0x2, 0x3 } |
| }, |
| .comm_port_hrt_types = { |
| { HRT_MAX_BWL, HRT_MAX_BWL, HRT_NONE, HRT_NONE, HRT_NONE, |
| HRT_NONE, HRT_CAM, HRT_NONE, HRT_DISP }, |
| { HRT_MAX_BWL, HRT_MAX_BWL, HRT_MML, HRT_NONE, HRT_NONE, |
| HRT_NONE, HRT_CAM, HRT_NONE, HRT_NONE }, |
| }, |
| .dual_pipe_larbs = { SLAVE_LARB(1), SLAVE_LARB(20) }, |
| .mmqos_state = MMQOS_ENABLE | P2_COMM_OSTDL_ENABLE, |
| .p2_larbs = { SLAVE_LARB(9), SLAVE_LARB(10), |
| SLAVE_LARB(12), SLAVE_LARB(15) }, |
| }; |
| static const struct of_device_id mtk_mmqos_mt6983_of_ids[] = { |
| { |
| .compatible = "mediatek,mt6983-mmqos", |
| .data = &mmqos_desc_mt6983, |
| }, |
| {} |
| }; |
| MODULE_DEVICE_TABLE(of, mtk_mmqos_mt6983_of_ids); |
| static struct platform_driver mtk_mmqos_mt6983_driver = { |
| .probe = mtk_mmqos_probe, |
| .remove = mtk_mmqos_remove, |
| .driver = { |
| .name = "mtk-mt6983-mmqos", |
| .of_match_table = mtk_mmqos_mt6983_of_ids, |
| }, |
| }; |
| module_platform_driver(mtk_mmqos_mt6983_driver); |
| MODULE_LICENSE("GPL v2"); |
| |
| |
| |
