| /* SPDX-License-Identifier: GPL-2.0-only */ |
| /* |
| * Copyright (c) 2020 MediaTek Inc. |
| * Author: Owen Chen <owen.chen@mediatek.com> |
| */ |
| |
| #ifndef _DT_BINDINGS_CLK_MT6853_H |
| #define _DT_BINDINGS_CLK_MT6853_H |
| |
| /* TOPCKGEN */ |
| #define CLK_TOP_ARMPLL_BL0_CK_VRPOC 0 |
| #define CLK_TOP_ARMPLL_LL_CK_VRPOC 1 |
| #define CLK_TOP_CCIPLL_CK_VRPOC_CCI 2 |
| #define CLK_TOP_MFGPLL 3 |
| #define CLK_TOP_MAINPLL 4 |
| #define CLK_TOP_MAINPLL_D3 5 |
| #define CLK_TOP_MAINPLL_D4 6 |
| #define CLK_TOP_MAINPLL_D4_D2 7 |
| #define CLK_TOP_MAINPLL_D4_D4 8 |
| #define CLK_TOP_MAINPLL_D4_D8 9 |
| #define CLK_TOP_MAINPLL_D4_D16 10 |
| #define CLK_TOP_MAINPLL_D5 11 |
| #define CLK_TOP_MAINPLL_D5_D2 12 |
| #define CLK_TOP_MAINPLL_D5_D4 13 |
| #define CLK_TOP_MAINPLL_D5_D8 14 |
| #define CLK_TOP_MAINPLL_D6 15 |
| #define CLK_TOP_MAINPLL_D6_D2 16 |
| #define CLK_TOP_MAINPLL_D6_D4 17 |
| #define CLK_TOP_MAINPLL_D6_D8 18 |
| #define CLK_TOP_MAINPLL_D7 19 |
| #define CLK_TOP_MAINPLL_D7_D2 20 |
| #define CLK_TOP_MAINPLL_D7_D4 21 |
| #define CLK_TOP_MAINPLL_D7_D8 22 |
| #define CLK_TOP_MAINPLL_D9 23 |
| #define CLK_TOP_UNIVPLL 24 |
| #define CLK_TOP_UNIVPLL_D2 25 |
| #define CLK_TOP_UNIVPLL_D3 26 |
| #define CLK_TOP_UNIVPLL_D4 27 |
| #define CLK_TOP_UNIVPLL_D4_D2 28 |
| #define CLK_TOP_UNIVPLL_D4_D4 29 |
| #define CLK_TOP_UNIVPLL_D4_D8 30 |
| #define CLK_TOP_UNIVPLL_D5 31 |
| #define CLK_TOP_UNIVPLL_D5_D2 32 |
| #define CLK_TOP_UNIVPLL_D5_D4 33 |
| #define CLK_TOP_UNIVPLL_D5_D8 34 |
| #define CLK_TOP_UNIVPLL_D5_D16 35 |
| #define CLK_TOP_UNIVPLL_D6 36 |
| #define CLK_TOP_UNIVPLL_D6_D2 37 |
| #define CLK_TOP_UNIVPLL_D6_D4 38 |
| #define CLK_TOP_UNIVPLL_D6_D8 39 |
| #define CLK_TOP_UNIVPLL_D6_D16 40 |
| #define CLK_TOP_UNIVPLL_D7 41 |
| #define CLK_TOP_UNIVPLL_D7_D2 42 |
| #define CLK_TOP_UNIVPLL_192M_D2 43 |
| #define CLK_TOP_UNIVPLL_192M_D4 44 |
| #define CLK_TOP_UNIVPLL_192M_D8 45 |
| #define CLK_TOP_UNIVPLL_192M_D16 46 |
| #define CLK_TOP_UNIVPLL_192M_D32 47 |
| #define CLK_TOP_USB20_192M 48 |
| #define CLK_TOP_USB20_PLL_D2 49 |
| #define CLK_TOP_USB20_PLL_D4 50 |
| #define CLK_TOP_MPLL_208M 51 |
| #define CLK_TOP_MPLL_D2 52 |
| #define CLK_TOP_MPLL_D4 53 |
| #define CLK_TOP_APLL1 54 |
| #define CLK_TOP_APLL1_D2 55 |
| #define CLK_TOP_APLL1_D4 56 |
| #define CLK_TOP_APLL1_D8 57 |
| #define CLK_TOP_APLL2 58 |
| #define CLK_TOP_APLL2_D2 59 |
| #define CLK_TOP_APLL2_D4 60 |
| #define CLK_TOP_APLL2_D8 61 |
| #define CLK_TOP_CLK26M_BYP 62 |
| #define CLK_TOP_ADSPPLL 63 |
| #define CLK_TOP_MMPLL 64 |
| #define CLK_TOP_MMPLL_D3 65 |
| #define CLK_TOP_MMPLL_D4 66 |
| #define CLK_TOP_MMPLL_D4_D2 67 |
| #define CLK_TOP_MMPLL_D4_D4 68 |
| #define CLK_TOP_MMPLL_D5 69 |
| #define CLK_TOP_MMPLL_D5_D2 70 |
| #define CLK_TOP_MMPLL_D5_D4 71 |
| #define CLK_TOP_MMPLL_D6 72 |
| #define CLK_TOP_MMPLL_D6_D2 73 |
| #define CLK_TOP_MMPLL_D7 74 |
| #define CLK_TOP_MMPLL_D9 75 |
| #define CLK_TOP_NPUPLL 76 |
| #define CLK_TOP_TVDPLL 77 |
| #define CLK_TOP_TVDPLL_D2 78 |
| #define CLK_TOP_TVDPLL_D4 79 |
| #define CLK_TOP_TVDPLL_D8 80 |
| #define CLK_TOP_TVDPLL_D16 81 |
| #define CLK_TOP_MSDCPLL 82 |
| #define CLK_TOP_MSDCPLL_D2 83 |
| #define CLK_TOP_MSDCPLL_D4 84 |
| #define CLK_TOP_MSDCPLL_D8 85 |
| #define CLK_TOP_MSDCPLL_D16 86 |
| #define CLK_TOP_MIPI_26M 87 |
| #define CLK_TOP_MEM_26M 88 |
| #define CLK_TOP_ARMPLL_26M 89 |
| #define CLK_TOP_SSUBS_26M 90 |
| #define CLK_TOP_PLLGP_TST 91 |
| #define CLK_TOP_CLKRTC 92 |
| #define CLK_TOP_TCK_26M_MX8 93 |
| #define CLK_TOP_TCK_26M_MX9 94 |
| #define CLK_TOP_TCK_26M_MX10 95 |
| #define CLK_TOP_TCK_26M_MX11 96 |
| #define CLK_TOP_TCK_26M_MX12 97 |
| #define CLK_TOP_CSW_FAXI 98 |
| #define CLK_TOP_CSW_F26M_CK_D52 99 |
| #define CLK_TOP_CSW_F26M_CK_D2 100 |
| #define CLK_TOP_OSC 101 |
| #define CLK_TOP_OSC_D2 102 |
| #define CLK_TOP_OSC_D4 103 |
| #define CLK_TOP_OSC_D8 104 |
| #define CLK_TOP_OSC_D16 105 |
| #define CLK_TOP_OSC_D10 106 |
| #define CLK_TOP_OSC_D20 107 |
| #define CLK_TOP_F26M 108 |
| #define CLK_TOP_FRTC 109 |
| #define CLK_TOP_AXI 110 |
| #define CLK_TOP_SPM 111 |
| #define CLK_TOP_SCP 112 |
| #define CLK_TOP_BUS 113 |
| #define CLK_TOP_DISP 114 |
| #define CLK_TOP_MDP 115 |
| #define CLK_TOP_IMG1 116 |
| #define CLK_TOP_IMG2 117 |
| #define CLK_TOP_IPE 118 |
| #define CLK_TOP_DPE 119 |
| #define CLK_TOP_CAM 120 |
| #define CLK_TOP_CCU 121 |
| #define CLK_TOP_DSP 122 |
| #define CLK_TOP_DSP1 123 |
| #define CLK_TOP_DSP1_SEL_CK 124 |
| #define CLK_TOP_DSP2 125 |
| #define CLK_TOP_DSP2_SEL_CK 126 |
| #define CLK_TOP_IPU_IF 127 |
| #define CLK_TOP_MFG_REF 128 |
| #define CLK_TOP_MFG_REF_SEL_CK 129 |
| #define CLK_TOP_FCAMTG 130 |
| #define CLK_TOP_FCAMTG2 131 |
| #define CLK_TOP_FCAMTG3 132 |
| #define CLK_TOP_FCAMTG4 133 |
| #define CLK_TOP_FCAMTG5 134 |
| #define CLK_TOP_FUART 135 |
| #define CLK_TOP_SPI 136 |
| #define CLK_TOP_MSDC50_0_HCLK 137 |
| #define CLK_TOP_MSDC50_0 138 |
| #define CLK_TOP_MSDC30_1 139 |
| #define CLK_TOP_AUDIO 140 |
| #define CLK_TOP_AUD_INTBUS 141 |
| #define CLK_TOP_FPWRAP_ULPOSC 142 |
| #define CLK_TOP_ATB 143 |
| #define CLK_TOP_SSPM 144 |
| #define CLK_TOP_SCAM 145 |
| #define CLK_TOP_FDISP_PWM 146 |
| #define CLK_TOP_FUSB_TOP 147 |
| #define CLK_TOP_FSSUSB_XHCI 148 |
| #define CLK_TOP_I2C 149 |
| #define CLK_TOP_FSENINF 150 |
| #define CLK_TOP_FSENINF1 151 |
| #define CLK_TOP_FSENINF2 152 |
| #define CLK_TOP_DXCC 153 |
| #define CLK_TOP_AUD_ENGEN1 154 |
| #define CLK_TOP_AUD_ENGEN2 155 |
| #define CLK_TOP_AES_UFSFDE 156 |
| #define CLK_TOP_UFS 157 |
| #define CLK_TOP_AUD_1 158 |
| #define CLK_TOP_AUD_2 159 |
| #define CLK_TOP_ADSP 160 |
| #define CLK_TOP_DPMAIF_MAIN 161 |
| #define CLK_TOP_VENC 162 |
| #define CLK_TOP_VDEC 163 |
| #define CLK_TOP_CAMTM 164 |
| #define CLK_TOP_PWM 165 |
| #define CLK_TOP_AUDIO_H 166 |
| #define CLK_TOP_SPMI_MST 167 |
| #define CLK_TOP_DVFSRC 168 |
| #define CLK_TOP_AES_MSDCFDE 169 |
| #define CLK_TOP_MCUPM 170 |
| #define CLK_TOP_SFLASH 171 |
| #define CLK_TOP_F_ULPOSC 172 |
| #define CLK_TOP_SRCK 173 |
| #define CLK_TOP_SYS_26M 174 |
| #define CLK_TOP_F_UFS_MP_SAP_CFG 175 |
| #define CLK_TOP_APDMA_PSEUDO 176 |
| #define CLK_TOP_F_UFS_TICK1US 177 |
| #define CLK_TOP_I2C_PSEUDO 178 |
| #define CLK_TOP_AXI_SEL 179 |
| #define CLK_TOP_SPM_SEL 180 |
| #define CLK_TOP_SCP_SEL 181 |
| #define CLK_TOP_BUS_AXIMEM_SEL 182 |
| #define CLK_TOP_DISP_SEL 183 |
| #define CLK_TOP_MDP_SEL 184 |
| #define CLK_TOP_IMG1_SEL 185 |
| #define CLK_TOP_IMG2_SEL 186 |
| #define CLK_TOP_IPE_SEL 187 |
| #define CLK_TOP_DPE_SEL 188 |
| #define CLK_TOP_CAM_SEL 189 |
| #define CLK_TOP_CCU_SEL 190 |
| #define CLK_TOP_DSP_SEL 191 |
| #define CLK_TOP_DSP1_SEL 192 |
| #define CLK_TOP_DSP1_NPUPLL_SEL 193 |
| #define CLK_TOP_DSP2_SEL 194 |
| #define CLK_TOP_DSP2_NPUPLL_SEL 195 |
| #define CLK_TOP_IPU_IF_SEL 196 |
| #define CLK_TOP_MFG_REF_SEL 197 |
| #define CLK_TOP_MFG_PLL_SEL 198 |
| #define CLK_TOP_CAMTG_SEL 199 |
| #define CLK_TOP_CAMTG2_SEL 200 |
| #define CLK_TOP_CAMTG3_SEL 201 |
| #define CLK_TOP_CAMTG4_SEL 202 |
| #define CLK_TOP_CAMTG5_SEL 203 |
| #define CLK_TOP_UART_SEL 204 |
| #define CLK_TOP_SPI_SEL 205 |
| #define CLK_TOP_MSDC50_0_HCLK_SEL 206 |
| #define CLK_TOP_MSDC50_0_SEL 207 |
| #define CLK_TOP_MSDC30_1_SEL 208 |
| #define CLK_TOP_AUDIO_SEL 209 |
| #define CLK_TOP_AUD_INTBUS_SEL 210 |
| #define CLK_TOP_PWRAP_ULPOSC_SEL 211 |
| #define CLK_TOP_ATB_SEL 212 |
| #define CLK_TOP_SSPM_SEL 213 |
| #define CLK_TOP_SCAM_SEL 214 |
| #define CLK_TOP_DISP_PWM_SEL 215 |
| #define CLK_TOP_USB_TOP_SEL 216 |
| #define CLK_TOP_SSUSB_XHCI_SEL 217 |
| #define CLK_TOP_I2C_SEL 218 |
| #define CLK_TOP_SENINF_SEL 219 |
| #define CLK_TOP_SENINF1_SEL 220 |
| #define CLK_TOP_SENINF2_SEL 221 |
| #define CLK_TOP_DXCC_SEL 222 |
| #define CLK_TOP_AUD_ENGEN1_SEL 223 |
| #define CLK_TOP_AUD_ENGEN2_SEL 224 |
| #define CLK_TOP_AES_UFSFDE_SEL 225 |
| #define CLK_TOP_UFS_SEL 226 |
| #define CLK_TOP_AUD_1_SEL 227 |
| #define CLK_TOP_AUD_2_SEL 228 |
| #define CLK_TOP_ADSP_SEL 229 |
| #define CLK_TOP_DPMAIF_MAIN_SEL 230 |
| #define CLK_TOP_VENC_SEL 231 |
| #define CLK_TOP_VDEC_SEL 232 |
| #define CLK_TOP_CAMTM_SEL 233 |
| #define CLK_TOP_PWM_SEL 234 |
| #define CLK_TOP_AUDIO_H_SEL 235 |
| #define CLK_TOP_SPMI_MST_SEL 236 |
| #define CLK_TOP_DVFSRC_SEL 237 |
| #define CLK_TOP_AES_MSDCFDE_SEL 238 |
| #define CLK_TOP_MCUPM_SEL 239 |
| #define CLK_TOP_SFLASH_SEL 240 |
| #define CLK_TOP_APLL_I2S0_MCK_SEL 241 |
| #define CLK_TOP_APLL_I2S1_MCK_SEL 242 |
| #define CLK_TOP_APLL_I2S2_MCK_SEL 243 |
| #define CLK_TOP_APLL_I2S3_MCK_SEL 244 |
| #define CLK_TOP_APLL_I2S4_MCK_SEL 245 |
| #define CLK_TOP_APLL_I2S5_MCK_SEL 246 |
| #define CLK_TOP_APLL_I2S6_MCK_SEL 247 |
| #define CLK_TOP_APLL_I2S7_MCK_SEL 248 |
| #define CLK_TOP_APLL_I2S8_MCK_SEL 249 |
| #define CLK_TOP_APLL_I2S9_MCK_SEL 250 |
| #define CLK_TOP_APLL12_CK_DIV0 251 |
| #define CLK_TOP_APLL12_CK_DIV1 252 |
| #define CLK_TOP_APLL12_CK_DIV2 253 |
| #define CLK_TOP_APLL12_CK_DIV3 254 |
| #define CLK_TOP_APLL12_CK_DIV4 255 |
| #define CLK_TOP_APLL12_CK_DIVB 256 |
| #define CLK_TOP_APLL12_CK_DIV5 257 |
| #define CLK_TOP_APLL12_CK_DIV6 258 |
| #define CLK_TOP_APLL12_CK_DIV7 259 |
| #define CLK_TOP_APLL12_CK_DIV8 260 |
| #define CLK_TOP_APLL12_CK_DIV9 261 |
| #define CLK_TOP_NR_CLK 262 |
| |
| /* INFRACFG_AO */ |
| #define CLK_IFRAO_PMIC_TMR_SET 0 |
| #define CLK_IFRAO_PMIC_AP_SET 1 |
| #define CLK_IFRAO_GCE 2 |
| #define CLK_IFRAO_GCE2 3 |
| #define CLK_IFRAO_THERM 4 |
| #define CLK_IFRAO_I2C0 5 |
| #define CLK_IFRAO_I2C1 6 |
| #define CLK_IFRAO_I2C2 7 |
| #define CLK_IFRAO_I2C3 8 |
| #define CLK_IFRAO_PWM_HCLK 9 |
| #define CLK_IFRAO_PWM1 10 |
| #define CLK_IFRAO_PWM2 11 |
| #define CLK_IFRAO_PWM3 12 |
| #define CLK_IFRAO_PWM4 13 |
| #define CLK_IFRAO_PWM 14 |
| #define CLK_IFRAO_UART0 15 |
| #define CLK_IFRAO_UART1 16 |
| #define CLK_IFRAO_UART2 17 |
| #define CLK_IFRAO_UART3 18 |
| #define CLK_IFRAO_GCE_26M_SET 19 |
| #define CLK_IFRAO_CQ_DMA_FPC 20 |
| #define CLK_IFRAO_BTIF 21 |
| #define CLK_IFRAO_SPI0 22 |
| #define CLK_IFRAO_MSDC0 23 |
| #define CLK_IFRAO_MSDC1 24 |
| #define CLK_IFRAO_MSDC0_SRC 25 |
| #define CLK_IFRAO_AUXADC 26 |
| #define CLK_IFRAO_CPUM 27 |
| #define CLK_IFRAO_CCIF1_AP 28 |
| #define CLK_IFRAO_CCIF1_MD 29 |
| #define CLK_IFRAO_PCIE_TL_26M 30 |
| #define CLK_IFRAO_MSDC1_SRC 31 |
| #define CLK_IFRAO_MSDC0_AES 32 |
| #define CLK_IFRAO_PCIE_TL_96M 33 |
| #define CLK_IFRAO_PCIE_PL_PCLK_250M 34 |
| #define CLK_IFRAO_DEVICE_APC 35 |
| #define CLK_IFRAO_CCIF_AP 36 |
| #define CLK_IFRAO_AUDIO 37 |
| #define CLK_IFRAO_CCIF_MD 38 |
| #define CLK_IFRAO_DXCC_SEC_CORE 39 |
| #define CLK_IFRAO_SSUSB 40 |
| #define CLK_IFRAO_DISP_PWM 41 |
| #define CLK_IFRAO_CLDMA_BCLK 42 |
| #define CLK_IFRAO_AUDIO_26M_BCLK 43 |
| #define CLK_IFRAO_SPI1 44 |
| #define CLK_IFRAO_I2C4 45 |
| #define CLK_IFRAO_SPI2 46 |
| #define CLK_IFRAO_SPI3 47 |
| #define CLK_IFRAO_UNIPRO_SYSCLK 48 |
| #define CLK_IFRAO_UFS_MP_SAP_BCLK 49 |
| #define CLK_IFRAO_I2C5 50 |
| #define CLK_IFRAO_I2C5_ARBITER 51 |
| #define CLK_IFRAO_I2C5_IMM 52 |
| #define CLK_IFRAO_I2C1_ARBITER 53 |
| #define CLK_IFRAO_I2C1_IMM 54 |
| #define CLK_IFRAO_I2C2_ARBITER 55 |
| #define CLK_IFRAO_I2C2_IMM 56 |
| #define CLK_IFRAO_SPI4 57 |
| #define CLK_IFRAO_SPI5 58 |
| #define CLK_IFRAO_CQ_DMA 59 |
| #define CLK_IFRAO_UFS 60 |
| #define CLK_IFRAO_UFS_AES 61 |
| #define CLK_IFRAO_SSUSB_XHCI 62 |
| #define CLK_IFRAO_MSDC0_SELF 63 |
| #define CLK_IFRAO_MSDC1_SELF 64 |
| #define CLK_IFRAO_MSDC2_SELF 65 |
| #define CLK_IFRAO_I2C6 66 |
| #define CLK_IFRAO_AP_MSDC0 67 |
| #define CLK_IFRAO_MD_MSDC0 68 |
| #define CLK_IFRAO_CCIF5_AP 69 |
| #define CLK_IFRAO_CCIF5_MD 70 |
| #define CLK_IFRAO_FLASHIF_TOP_HCLK_133M 71 |
| #define CLK_IFRAO_CCIF2_AP 72 |
| #define CLK_IFRAO_CCIF2_MD 73 |
| #define CLK_IFRAO_I2C7 74 |
| #define CLK_IFRAO_I2C8 75 |
| #define CLK_IFRAO_FBIST2FPC 76 |
| #define CLK_IFRAO_DEVICE_APC_SYNC 77 |
| #define CLK_IFRAO_DPMAIF_MAIN 78 |
| #define CLK_IFRAO_CCIF4_AP 79 |
| #define CLK_IFRAO_CCIF4_MD 80 |
| #define CLK_IFRAO_SPI6_CK 81 |
| #define CLK_IFRAO_SPI7_CK 82 |
| #define CLK_IFRAO_66M_PERI_BUS_MCLK_CK 83 |
| #define CLK_IFRAO_INFRA_FREE_DCM_133M 84 |
| #define CLK_IFRAO_INFRA_FREE_DCM_66M 85 |
| #define CLK_IFRAO_PERI_BUS_DCM_133M 86 |
| #define CLK_IFRAO_PERI_BUS_DCM_66M 87 |
| #define CLK_IFRAO_RG_FLASHIF_PERI_26M_CK 88 |
| #define CLK_IFRAO_RG_FLASHIF_SFLASH_CK 89 |
| #define CLK_IFRAO_AP_DMA 90 |
| #define CLK_IFRAO_NR_CLK 91 |
| |
| /* APMIXEDSYS */ |
| #define CLK_APMIXED_ARMPLL_LL 0 |
| #define CLK_APMIXED_ARMPLL_BL0 1 |
| #define CLK_APMIXED_CCIPLL 2 |
| #define CLK_APMIXED_MPLL 3 |
| #define CLK_APMIXED_MAINPLL 4 |
| #define CLK_APMIXED_UNIVPLL 5 |
| #define CLK_APMIXED_MSDCPLL 6 |
| #define CLK_APMIXED_MMPLL 7 |
| #define CLK_APMIXED_ADSPPLL 8 |
| #define CLK_APMIXED_MFGPLL 9 |
| #define CLK_APMIXED_TVDPLL 10 |
| #define CLK_APMIXED_APLL1 11 |
| #define CLK_APMIXED_APLL2 12 |
| #define CLK_APMIXED_NPUPLL 13 |
| #define CLK_APMIXED_USBPLL 14 |
| #define CLK_APMIXED_PLL_MIPIC0_26M_EN 15 |
| #define CLK_APMIXED_PLL_MIPIC1_26M_EN 16 |
| #define CLK_APMIXED_PLL_MIPID26M_0_EN 17 |
| #define CLK_APMIXED_NR_CLK 18 |
| |
| /* SCP_ADSP */ |
| #define CLK_SCP_PAR_RG_AUDIODSP 0 |
| #define CLK_SCP_PAR_NR_CLK 1 |
| |
| /* IMP_IIC_WRAP_C */ |
| #define CLK_IMPC_AP_CLOCK_RO_I2C10 0 |
| #define CLK_IMPC_AP_CLOCK_RO_I2C11 1 |
| #define CLK_IMPC_NR_CLK 2 |
| |
| /* AUDIOSYS */ |
| #define CLK_AUDSYS_AFE 0 |
| #define CLK_AUDSYS_22M 1 |
| #define CLK_AUDSYS_24M 2 |
| #define CLK_AUDSYS_APLL2_TUNER 3 |
| #define CLK_AUDSYS_APLL_TUNER 4 |
| #define CLK_AUDSYS_TDM 5 |
| #define CLK_AUDSYS_ADC 6 |
| #define CLK_AUDSYS_DAC 7 |
| #define CLK_AUDSYS_DAC_PREDIS 8 |
| #define CLK_AUDSYS_TML 9 |
| #define CLK_AUDSYS_NLE 10 |
| #define CLK_AUDSYS_I2S1_BCLK 11 |
| #define CLK_AUDSYS_I2S2_BCLK 12 |
| #define CLK_AUDSYS_I2S3_BCLK 13 |
| #define CLK_AUDSYS_I2S4_BCLK 14 |
| #define CLK_AUDSYS_CONNSYS_I2S_ASRC 15 |
| #define CLK_AUDSYS_GENERAL1_ASRC 16 |
| #define CLK_AUDSYS_GENERAL2_ASRC 17 |
| #define CLK_AUDSYS_DAC_HIRES 18 |
| #define CLK_AUDSYS_ADC_HIRES 19 |
| #define CLK_AUDSYS_ADC_HIRES_TML 20 |
| #define CLK_AUDSYS_ADDA6_ADC 21 |
| #define CLK_AUDSYS_ADDA6_ADC_HIRES 22 |
| #define CLK_AUDSYS_3RD_DAC 23 |
| #define CLK_AUDSYS_3RD_DAC_PREDIS 24 |
| #define CLK_AUDSYS_3RD_DAC_TML 25 |
| #define CLK_AUDSYS_3RD_DAC_HIRES 26 |
| #define CLK_AUDSYS_I2S5_BCLK 27 |
| #define CLK_AUDSYS_I2S6_BCLK 28 |
| #define CLK_AUDSYS_I2S7_BCLK 29 |
| #define CLK_AUDSYS_I2S8_BCLK 30 |
| #define CLK_AUDSYS_I2S9_BCLK 31 |
| #define CLK_AUDSYS_NR_CLK 32 |
| |
| /* IMP_IIC_WRAP_E */ |
| #define CLK_IMPE_AP_CLOCK_RO_I2C3 0 |
| #define CLK_IMPE_NR_CLK 1 |
| |
| /* IMP_IIC_WRAP_S */ |
| #define CLK_IMPS_AP_CLOCK_RO_I2C5 0 |
| #define CLK_IMPS_AP_CLOCK_RO_I2C7 1 |
| #define CLK_IMPS_AP_CLOCK_RO_I2C8 2 |
| #define CLK_IMPS_AP_CLOCK_RO_I2C9 3 |
| #define CLK_IMPS_NR_CLK 4 |
| |
| /* IMP_IIC_WRAP_WS */ |
| #define CLK_IMPWS_AP_CLOCK_RO_I2C1 0 |
| #define CLK_IMPWS_AP_CLOCK_RO_I2C2 1 |
| #define CLK_IMPWS_AP_CLOCK_RO_I2C4 2 |
| #define CLK_IMPWS_NR_CLK 3 |
| |
| /* IMP_IIC_WRAP_W */ |
| #define CLK_IMPW_AP_CLOCK_RO_I2C0 0 |
| #define CLK_IMPW_NR_CLK 1 |
| |
| /* IMP_IIC_WRAP_N */ |
| #define CLK_IMPN_AP_CLOCK_RO_I2C6 0 |
| #define CLK_IMPN_NR_CLK 1 |
| |
| /* MFGCFG */ |
| #define CLK_MFG_BG3D 0 |
| #define CLK_MFG_NR_CLK 1 |
| |
| /* MMSYS_CONFIG */ |
| #define CLK_MM_DISP_MUTEX0 0 |
| #define CLK_MM_APB_BUS 1 |
| #define CLK_MM_DISP_OVL0 2 |
| #define CLK_MM_DISP_RDMA0 3 |
| #define CLK_MM_DISP_OVL0_2L 4 |
| #define CLK_MM_DISP_WDMA0 5 |
| #define CLK_MM_DISP_CCORR1 6 |
| #define CLK_MM_DISP_RSZ0 7 |
| #define CLK_MM_DISP_AAL0 8 |
| #define CLK_MM_DISP_CCORR0 9 |
| #define CLK_MM_DISP_COLOR0 10 |
| #define CLK_MM_SMI_INFRA 11 |
| #define CLK_MM_DISP_DSC_WRAP 12 |
| #define CLK_MM_DISP_GAMMA0 13 |
| #define CLK_MM_DISP_POSTMASK0 14 |
| #define CLK_MM_DISP_SPR0 15 |
| #define CLK_MM_DISP_DITHER0 16 |
| #define CLK_MM_SMI_COMMON 17 |
| #define CLK_MM_DISP_CM0 18 |
| #define CLK_MM_DSI0 19 |
| #define CLK_MM_DISP_FAKE_ENG0 20 |
| #define CLK_MM_DISP_FAKE_ENG1 21 |
| #define CLK_MM_SMI_GALS 22 |
| #define CLK_MM_SMI_IOMMU 23 |
| #define CLK_MM_DSI0_DSI_CK_DOMAIN 24 |
| #define CLK_MM_DISP_26M 25 |
| #define CLK_MM_NR_CLK 26 |
| |
| /* IMGSYS1 */ |
| #define CLK_IMGSYS1_LARB9 0 |
| #define CLK_IMGSYS1_LARB10 1 |
| #define CLK_IMGSYS1_DIP 2 |
| #define CLK_IMGSYS1_GALS 3 |
| #define CLK_IMGSYS1_NR_CLK 4 |
| |
| /* IMGSYS2 */ |
| #define CLK_IMGSYS2_LARB9 0 |
| #define CLK_IMGSYS2_LARB10 1 |
| #define CLK_IMGSYS2_MFB 2 |
| #define CLK_IMGSYS2_WPE 3 |
| #define CLK_IMGSYS2_MSS 4 |
| #define CLK_IMGSYS2_GALS 5 |
| #define CLK_IMGSYS2_NR_CLK 6 |
| |
| /* VDEC_GCON */ |
| #define CLK_VDEC_LARB1_CKEN 0 |
| #define CLK_VDEC_CKEN 1 |
| #define CLK_VDEC_ACTIVE 2 |
| #define CLK_VDEC_NR_CLK 3 |
| |
| /* VENC_GCON */ |
| #define CLK_VENC_CKE0_LARB 0 |
| #define CLK_VENC_CKE1_VENC 1 |
| #define CLK_VENC_CKE2_JPGENC 2 |
| #define CLK_VENC_CKE5_GALS 3 |
| #define CLK_VENC_NR_CLK 4 |
| |
| /* APU_CONN */ |
| #define CLK_APUC_APU 0 |
| #define CLK_APUC_AHB 1 |
| #define CLK_APUC_AXI 2 |
| #define CLK_APUC_ISP 3 |
| #define CLK_APUC_CAM_ADL 4 |
| #define CLK_APUC_IMG_ADL 5 |
| #define CLK_APUC_EMI_26M 6 |
| #define CLK_APUC_VPU_UDI 7 |
| #define CLK_APUC_EDMA_0 8 |
| #define CLK_APUC_EDMA_1 9 |
| #define CLK_APUC_EDMAL_0 10 |
| #define CLK_APUC_EDMAL_1 11 |
| #define CLK_APUC_MNOC 12 |
| #define CLK_APUC_TCM 13 |
| #define CLK_APUC_MD32 14 |
| #define CLK_APUC_IOMMU_0 15 |
| #define CLK_APUC_MD32_32K 16 |
| #define CLK_APUC_NR_CLK 17 |
| |
| /* APU_VCORE */ |
| #define CLK_APUV_AHB 0 |
| #define CLK_APUV_AXI 1 |
| #define CLK_APUV_ADL 2 |
| #define CLK_APUV_QOS 3 |
| #define CLK_APUV_NR_CLK 4 |
| |
| /* APU0 */ |
| #define CLK_APU0_APU 0 |
| #define CLK_APU0_AXI_M 1 |
| #define CLK_APU0_JTAG 2 |
| #define CLK_APU0_PCLK 3 |
| #define CLK_APU0_NR_CLK 4 |
| |
| /* APU1 */ |
| #define CLK_APU1_APU 0 |
| #define CLK_APU1_AXI_M 1 |
| #define CLK_APU1_JTAG 2 |
| #define CLK_APU1_PCLK 3 |
| #define CLK_APU1_NR_CLK 4 |
| |
| /* CAMSYS_MAIN */ |
| #define CLK_CAM_M_LARB13 0 |
| #define CLK_CAM_M_LARB14 1 |
| #define CLK_CAM_M_RESERVED0 2 |
| #define CLK_CAM_M_CAM 3 |
| #define CLK_CAM_M_CAMTG 4 |
| #define CLK_CAM_M_SENINF 5 |
| #define CLK_CAM_M_CAMSV1 6 |
| #define CLK_CAM_M_CAMSV2 7 |
| #define CLK_CAM_M_CAMSV3 8 |
| #define CLK_CAM_M_CCU0 9 |
| #define CLK_CAM_M_CCU1 10 |
| #define CLK_CAM_M_MRAW0 11 |
| #define CLK_CAM_M_RESERVED2 12 |
| #define CLK_CAM_M_FAKE_ENG 13 |
| #define CLK_CAM_M_CCU_GALS 14 |
| #define CLK_CAM_M_CAM2MM_GALS 15 |
| #define CLK_CAM_M_NR_CLK 16 |
| |
| /* CAMSYS_RAWA */ |
| #define CLK_CAM_RA_LARBX 0 |
| #define CLK_CAM_RA_CAM 1 |
| #define CLK_CAM_RA_CAMTG 2 |
| #define CLK_CAM_RA_NR_CLK 3 |
| |
| /* CAMSYS_RAWB */ |
| #define CLK_CAM_RB_LARBX 0 |
| #define CLK_CAM_RB_CAM 1 |
| #define CLK_CAM_RB_CAMTG 2 |
| #define CLK_CAM_RB_NR_CLK 3 |
| |
| /* IPESYS */ |
| #define CLK_IPE_LARB19 0 |
| #define CLK_IPE_LARB20 1 |
| #define CLK_IPE_SMI_SUBCOM 2 |
| #define CLK_IPE_FD 3 |
| #define CLK_IPE_FE 4 |
| #define CLK_IPE_RSC 5 |
| #define CLK_IPE_DPE 6 |
| #define CLK_IPE_GALS 7 |
| #define CLK_IPE_NR_CLK 8 |
| |
| /* MDPSYS_CONFIG */ |
| #define CLK_MDP_RDMA0 0 |
| #define CLK_MDP_TDSHP0 1 |
| #define CLK_MDP_IMG_DL_ASYNC0 2 |
| #define CLK_MDP_IMG_DL_ASYNC1 3 |
| #define CLK_MDP_RDMA1 4 |
| #define CLK_MDP_TDSHP1 5 |
| #define CLK_MDP_SMI0 6 |
| #define CLK_MDP_APB_BUS 7 |
| #define CLK_MDP_WROT0 8 |
| #define CLK_MDP_RSZ0 9 |
| #define CLK_MDP_HDR0 10 |
| #define CLK_MDP_MUTEX0 11 |
| #define CLK_MDP_WROT1 12 |
| #define CLK_MDP_RSZ1 13 |
| #define CLK_MDP_FAKE_ENG0 14 |
| #define CLK_MDP_AAL0 15 |
| #define CLK_MDP_AAL1 16 |
| #define CLK_MDP_COLOR0 17 |
| #define CLK_MDP_IMG_DL_RELAY0_ASYNC0 18 |
| #define CLK_MDP_IMG_DL_RELAY1_ASYNC1 19 |
| #define CLK_MDP_NR_CLK 20 |
| |
| #endif /* _DT_BINDINGS_CLK_MT6853_H */ |
