| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* |
| * Copyright (c) 2020 MediaTek Inc. |
| * Author: Owen Chen <owen.chen@mediatek.com> |
| */ |
| |
| #ifndef _DT_BINDINGS_CLK_MT6983_H |
| #define _DT_BINDINGS_CLK_MT6983_H |
| |
| #define CLK_APMIXEDSYS_MAINPLL (0) |
| #define CLK_APMIXEDSYS_UNIVPLL (1) |
| #define CLK_APMIXEDSYS_MSDCPLL (2) |
| #define CLK_APMIXEDSYS_MMPLL (3) |
| #define CLK_APMIXEDSYS_ADSPPLL (4) |
| #define CLK_APMIXEDSYS_TVDPLL (5) |
| #define CLK_APMIXEDSYS_APLL1 (6) |
| #define CLK_APMIXEDSYS_APLL2 (7) |
| #define CLK_APMIXEDSYS_MPLL (8) |
| #define CLK_APMIXEDSYS_IMGPLL (9) |
| #define CLK_APMIXEDSYS_NR_CLK 10 |
| |
| #define CLK_MFG_MFGPLL (0) |
| #define CLK_MFG_MFGSCPLL (1) |
| #define CLK_MFG_GPUEBPLL (2) |
| #define CLK_MFG_NR_CLK 3 |
| |
| #define CLK_APU_APUPLL (0) |
| #define CLK_APU_NPUPLL (1) |
| #define CLK_APU_APUPLL1 (2) |
| #define CLK_APU_APUPLL2 (3) |
| #define CLK_APU_NR_CLK 4 |
| |
| #define CLK_TOP_ADSPPLL (0) |
| #define CLK_TOP_APLL1 (1) |
| #define CLK_TOP_APLL1_D2 (2) |
| #define CLK_TOP_APLL1_D4 (3) |
| #define CLK_TOP_APLL1_D8 (4) |
| #define CLK_TOP_APLL2 (5) |
| #define CLK_TOP_APLL2_D2 (6) |
| #define CLK_TOP_APLL2_D4 (7) |
| #define CLK_TOP_APLL2_D8 (8) |
| #define CLK_TOP_EMIPLL (9) |
| #define CLK_TOP_IMGPLL_D2 (10) |
| #define CLK_TOP_IMGPLL_D5 (11) |
| #define CLK_TOP_MAINPLL_D3 (12) |
| #define CLK_TOP_MAINPLL_D4 (13) |
| #define CLK_TOP_MAINPLL_D4_D16 (14) |
| #define CLK_TOP_MAINPLL_D4_D2 (15) |
| #define CLK_TOP_MAINPLL_D4_D4 (16) |
| #define CLK_TOP_MAINPLL_D4_D8 (17) |
| #define CLK_TOP_MAINPLL_D5 (18) |
| #define CLK_TOP_MAINPLL_D5_D2 (19) |
| #define CLK_TOP_MAINPLL_D5_D4 (20) |
| #define CLK_TOP_MAINPLL_D5_D8 (21) |
| #define CLK_TOP_MAINPLL_D6 (22) |
| #define CLK_TOP_MAINPLL_D6_D2 (23) |
| #define CLK_TOP_MAINPLL_D6_D4 (24) |
| #define CLK_TOP_MAINPLL_D6_D8 (25) |
| #define CLK_TOP_MAINPLL_D7 (26) |
| #define CLK_TOP_MAINPLL_D7_D2 (27) |
| #define CLK_TOP_MAINPLL_D7_D4 (28) |
| #define CLK_TOP_MAINPLL_D7_D8 (29) |
| #define CLK_TOP_MAINPLL_D9 (30) |
| #define CLK_TOP_MFGPLL (31) |
| #define CLK_TOP_MFGSCPLL (32) |
| #define CLK_TOP_MMPLL_D4 (33) |
| #define CLK_TOP_MMPLL_D4_D2 (34) |
| #define CLK_TOP_MMPLL_D5 (35) |
| #define CLK_TOP_MMPLL_D5_D2 (36) |
| #define CLK_TOP_MMPLL_D6 (37) |
| #define CLK_TOP_MMPLL_D6_D2 (38) |
| #define CLK_TOP_MMPLL_D7 (39) |
| #define CLK_TOP_MMPLL_D9 (40) |
| #define CLK_TOP_MSDCPLL (41) |
| #define CLK_TOP_MSDCPLL_D2 (42) |
| #define CLK_TOP_TVDPLL (43) |
| #define CLK_TOP_TVDPLL_D16 (44) |
| #define CLK_TOP_TVDPLL_D2 (45) |
| #define CLK_TOP_TVDPLL_D4 (46) |
| #define CLK_TOP_TVDPLL_D8 (47) |
| #define CLK_TOP_UNIVPLL_192M_D10 (48) |
| #define CLK_TOP_UNIVPLL_192M_D16 (49) |
| #define CLK_TOP_UNIVPLL_192M_D2 (50) |
| #define CLK_TOP_UNIVPLL_192M_D32 (51) |
| #define CLK_TOP_UNIVPLL_192M_D8 (52) |
| #define CLK_TOP_UNIVPLL_D3 (53) |
| #define CLK_TOP_UNIVPLL_D4 (54) |
| #define CLK_TOP_UNIVPLL_D4_D2 (55) |
| #define CLK_TOP_UNIVPLL_D4_D4 (56) |
| #define CLK_TOP_UNIVPLL_D4_D8 (57) |
| #define CLK_TOP_UNIVPLL_D5 (58) |
| #define CLK_TOP_UNIVPLL_D5_D2 (59) |
| #define CLK_TOP_UNIVPLL_D5_D4 (60) |
| #define CLK_TOP_UNIVPLL_D6 (61) |
| #define CLK_TOP_UNIVPLL_D6_D16 (62) |
| #define CLK_TOP_UNIVPLL_D6_D2 (63) |
| #define CLK_TOP_UNIVPLL_D6_D4 (64) |
| #define CLK_TOP_UNIVPLL_D6_D8 (65) |
| #define CLK_TOP_UNIVPLL_D7 (66) |
| #define CLK_TOP_AD_OSC (67) |
| #define CLK_TOP_CLKRTC (68) |
| #define CLK_TOP_F26M (69) |
| #define CLK_TOP_F26M_CK_D2 (70) |
| #define CLK_TOP_OSC_D10 (71) |
| #define CLK_TOP_OSC_D16 (72) |
| #define CLK_TOP_OSC_D2 (73) |
| #define CLK_TOP_OSC_D4 (74) |
| #define CLK_TOP_OSC_D7 (75) |
| #define CLK_TOP_OSC_D8 (76) |
| #define CLK_TOP_TCK_26M_MX9 (77) |
| #define CLK_TOP_ULPOSC (78) |
| #define CLK_TOP_FADSP (79) |
| #define CLK_TOP_FAUDIO (80) |
| #define CLK_TOP_FAUD_ENGEN1 (81) |
| #define CLK_TOP_FAUD_ENGEN2 (82) |
| #define CLK_TOP_FAUD_1 (83) |
| #define CLK_TOP_FAUDIO_H (84) |
| #define CLK_TOP_FDSP (85) |
| #define CLK_TOP_FDSP4 (86) |
| #define CLK_TOP_FDSP7 (87) |
| #define CLK_TOP_FIPU_IF (88) |
| #define CLK_TOP_FCAM (89) |
| #define CLK_TOP_FCAMTM (90) |
| #define CLK_TOP_FCCUSYS (91) |
| #define CLK_TOP_FCCU_AHB (92) |
| #define CLK_TOP_FIMG1 (93) |
| #define CLK_TOP_FDISP0 (94) |
| #define CLK_TOP_FDISP1 (249) |
| #define CLK_TOP_FI2C (95) |
| #define CLK_TOP_FAXI (96) |
| #define CLK_TOP_FDXCC (97) |
| #define CLK_TOP_FMSDC_MACRO (98) |
| #define CLK_TOP_FDPMAIF_MAIN (99) |
| #define CLK_TOP_FMEM_SUB (100) |
| #define CLK_TOP_FIPE (101) |
| #define CLK_TOP_FMDP1 (102) |
| #define CLK_TOP_FMDP0 (103) |
| #define CLK_TOP_FMFG_REF (104) |
| #define CLK_TOP_FMMINFRA (105) |
| #define CLK_TOP_FRTC (106) |
| #define CLK_TOP_FVDEC (107) |
| #define CLK_TOP_FVENC (108) |
| #define CLK_TOP_FUART (109) |
| #define CLK_TOP_FPERI_HD_AXI (110) |
| #define CLK_TOP_FPWM (111) |
| #define CLK_TOP_FDISP_PWM (112) |
| #define CLK_TOP_FSPI (113) |
| #define CLK_TOP_FSFLASH (114) |
| #define CLK_TOP_FUSB_TOP (115) |
| #define CLK_TOP_FSSUSB_XHCI (116) |
| #define CLK_TOP_FUSB_TOP_1P (117) |
| #define CLK_TOP_FSSUSB_XHCI_1P (118) |
| #define CLK_TOP_FMSDC30_1 (119) |
| #define CLK_TOP_FMSDC30_2 (120) |
| #define CLK_TOP_FTL (121) |
| #define CLK_TOP_PERI_HD_FAXI_SEL (246) |
| #define CLK_TOP_UFS_HD_HAXI_SEL (247) |
| #define CLK_TOP_BUS_AXIMEM_SEL (248) |
| #define CLK_TOP_AXI_SEL (122) |
| #define CLK_TOP_DISP0_SEL (123) |
| #define CLK_TOP_DISP1_SEL (124) |
| #define CLK_TOP_MDP0_SEL (125) |
| #define CLK_TOP_MDP1_SEL (126) |
| #define CLK_TOP_MMINFRA_SEL (127) |
| #define CLK_TOP_MMUP_SEL (128) |
| #define CLK_TOP_DSP_SEL (129) |
| #define CLK_TOP_DSP1_SEL (130) |
| #define CLK_TOP_DSP2_SEL (131) |
| #define CLK_TOP_DSP3_SEL (132) |
| #define CLK_TOP_DSP4_SEL (133) |
| #define CLK_TOP_DSP5_SEL (134) |
| #define CLK_TOP_DSP6_SEL (135) |
| #define CLK_TOP_DSP7_SEL (136) |
| #define CLK_TOP_IPU_IF_SEL (137) |
| #define CLK_TOP_MFG_REF_SEL (138) |
| #define CLK_TOP_MFGSC_REF_SEL (139) |
| #define CLK_TOP_CAMTG_SEL (140) |
| #define CLK_TOP_CAMTG2_SEL (141) |
| #define CLK_TOP_CAMTG3_SEL (142) |
| #define CLK_TOP_CAMTG4_SEL (143) |
| #define CLK_TOP_CAMTG5_SEL (144) |
| #define CLK_TOP_CAMTG6_SEL (145) |
| #define CLK_TOP_CAMTG7_SEL (146) |
| #define CLK_TOP_CAMTG8_SEL (147) |
| #define CLK_TOP_UART_SEL (148) |
| #define CLK_TOP_SPI_SEL (149) |
| #define CLK_TOP_MSDC50_0_HCLK_SEL (150) |
| #define CLK_TOP_MSDC_MACRO_SEL (151) |
| #define CLK_TOP_MSDC30_1_SEL (152) |
| #define CLK_TOP_MSDC30_2_SEL (153) |
| #define CLK_TOP_AUDIO_SEL (154) |
| #define CLK_TOP_AUD_INTBUS_SEL (155) |
| #define CLK_TOP_PWRAP_ULPOSC_SEL (156) |
| #define CLK_TOP_ATB_SEL (157) |
| #define CLK_TOP_DP_SEL (158) |
| #define CLK_TOP_DISP_PWM_SEL (159) |
| #define CLK_TOP_USB_TOP_SEL (160) |
| #define CLK_TOP_SSUSB_XHCI_SEL (161) |
| #define CLK_TOP_USB_TOP_1P_SEL (162) |
| #define CLK_TOP_SSUSB_XHCI_1P_SEL (163) |
| #define CLK_TOP_I2C_SEL (164) |
| #define CLK_TOP_SENINF_SEL (165) |
| #define CLK_TOP_SENINF1_SEL (166) |
| #define CLK_TOP_SENINF2_SEL (167) |
| #define CLK_TOP_SENINF3_SEL (168) |
| #define CLK_TOP_SENINF4_SEL (169) |
| #define CLK_TOP_SENINF5_SEL (170) |
| #define CLK_TOP_DXCC_SEL (171) |
| #define CLK_TOP_AUD_ENGEN1_SEL (172) |
| #define CLK_TOP_AUD_ENGEN2_SEL (173) |
| #define CLK_TOP_AES_UFSFDE_SEL (174) |
| #define CLK_TOP_UFS_SEL (175) |
| #define CLK_TOP_UFS_MBIST_SEL (176) |
| #define CLK_TOP_PEXTP_MBIST_SEL (177) |
| #define CLK_TOP_AUD_1_SEL (178) |
| #define CLK_TOP_VENC_SEL (179) |
| #define CLK_TOP_AUD_2_SEL (180) |
| #define CLK_TOP_ADSP_SEL (181) |
| #define CLK_TOP_DPMAIF_MAIN_SEL (182) |
| #define CLK_TOP_VDEC_SEL (183) |
| #define CLK_TOP_PWM_SEL (184) |
| #define CLK_TOP_AUDIO_H_SEL (185) |
| #define CLK_TOP_MCUPM_SEL (186) |
| #define CLK_TOP_SPMI_P_MST_SEL (187) |
| #define CLK_TOP_SPMI_M_MST_SEL (188) |
| #define CLK_TOP_TL_SEL (189) |
| #define CLK_TOP_MEM_SUB_SEL (190) |
| #define CLK_TOP_PERI_HF_FMEM_SEL (191) |
| #define CLK_TOP_UFS_HF_FMEM_SEL (192) |
| #define CLK_TOP_AES_MSDCFDE_SEL (193) |
| #define CLK_TOP_EMI_N_SEL (194) |
| #define CLK_TOP_EMI_S_SEL (195) |
| #define CLK_TOP_DSI_OCC_SEL (196) |
| #define CLK_TOP_DPTX_SEL (197) |
| #define CLK_TOP_CCU_AHB_SEL (198) |
| #define CLK_TOP_AP2CONN_HOST_SEL (199) |
| #define CLK_TOP_IMG1_SEL (200) |
| #define CLK_TOP_IPE_SEL (201) |
| #define CLK_TOP_CAM_SEL (202) |
| #define CLK_TOP_CCUSYS_SEL (203) |
| #define CLK_TOP_CAMTM_SEL (204) |
| #define CLK_TOP_SFLASH_SEL (205) |
| #define CLK_TOP_MCU_ACP_SEL (206) |
| #define CLK_TOP_TL_CK_SEL (207) |
| #define CLK_TOP_MFG_SEL_0 (208) |
| #define CLK_TOP_MFG_SEL_1 (209) |
| #define CLK_TOP_APLL_I2S0_MCK_SEL (210) |
| #define CLK_TOP_APLL_I2S1_MCK_SEL (211) |
| #define CLK_TOP_APLL_I2S2_MCK_SEL (212) |
| #define CLK_TOP_APLL_I2S3_MCK_SEL (213) |
| #define CLK_TOP_APLL_I2S4_MCK_SEL (214) |
| #define CLK_TOP_APLL_I2S5_MCK_SEL (215) |
| #define CLK_TOP_APLL_I2S6_MCK_SEL (216) |
| #define CLK_TOP_APLL_I2S7_MCK_SEL (217) |
| #define CLK_TOP_APLL_I2S8_MCK_SEL (218) |
| #define CLK_TOP_APLL_I2S9_MCK_SEL (219) |
| #define CLK_TOP_APLL12_CK_DIV0 (220) |
| #define CLK_TOP_APLL12_CK_DIV1 (221) |
| #define CLK_TOP_APLL12_CK_DIV2 (222) |
| #define CLK_TOP_APLL12_CK_DIV3 (223) |
| #define CLK_TOP_APLL12_CK_DIV4 (224) |
| #define CLK_TOP_APLL12_CK_DIV5 (225) |
| #define CLK_TOP_APLL12_CK_DIV6 (226) |
| #define CLK_TOP_APLL12_CK_DIV7 (227) |
| #define CLK_TOP_APLL12_CK_DIV8 (228) |
| #define CLK_TOP_APLL12_CK_DIV9 (229) |
| #define CLK_TOP_APLL12_CK_DIVB (230) |
| #define CLK_TOP_MD_32K (231) |
| #define CLK_TOP_MD_26M (232) |
| #define CLK_TOP_CONN_32K (233) |
| #define CLK_TOP_CONN_26M (234) |
| #define CLK_TOP_APLL12_DIV0_PDN (235) |
| #define CLK_TOP_APLL12_DIV1_PDN (236) |
| #define CLK_TOP_APLL12_DIV2_PDN (237) |
| #define CLK_TOP_APLL12_DIV3_PDN (238) |
| #define CLK_TOP_APLL12_DIV4_PDN (239) |
| #define CLK_TOP_APLL12_DIVB_PDN (240) |
| #define CLK_TOP_APLL12_DIV5_PDN (241) |
| #define CLK_TOP_APLL12_DIV6_PDN (242) |
| #define CLK_TOP_APLL12_DIV7_PDN (243) |
| #define CLK_TOP_APLL12_DIV8_PDN (244) |
| #define CLK_TOP_APLL12_DIV9_PDN (245) |
| #define CLK_TOP_NR_CLK 250 |
| |
| |
| #define CLK_ADSP_CORE0_CLK_EN (0) |
| #define CLK_ADSP_CORE0_DBG_EN (1) |
| #define CLK_ADSP_TIMER_EN (2) |
| #define CLK_ADSP_DMA0_EN (3) |
| #define CLK_ADSP_UART_EN (4) |
| #define CLK_ADSP_UART_BCLK (5) |
| #define CLK_ADSP_NR_CLK 6 |
| |
| #define CLK_AFE_AFE (0) |
| #define CLK_AFE_22M (1) |
| #define CLK_AFE_24M (2) |
| #define CLK_AFE_APLL2_TUNER (3) |
| #define CLK_AFE_APLL_TUNER (4) |
| #define CLK_AFE_TDM (5) |
| #define CLK_AFE_ADC (6) |
| #define CLK_AFE_DAC (7) |
| #define CLK_AFE_DAC_PREDIS (8) |
| #define CLK_AFE_TML (9) |
| #define CLK_AFE_NLE (10) |
| #define CLK_AFE_GENERAL3_ASRC (11) |
| #define CLK_AFE_CONNSYS_I2S_ASRC (12) |
| #define CLK_AFE_GENERAL1_ASRC (13) |
| #define CLK_AFE_GENERAL2_ASRC (14) |
| #define CLK_AFE_DAC_HIRES (15) |
| #define CLK_AFE_ADC_HIRES (16) |
| #define CLK_AFE_ADC_HIRES_TML (17) |
| #define CLK_AFE_ADDA6_ADC (18) |
| #define CLK_AFE_ADDA6_ADC_HIRES (19) |
| #define CLK_AFE_ADDA7_ADC (20) |
| #define CLK_AFE_ADDA7_ADC_HIRES (21) |
| #define CLK_AFE_3RD_DAC (22) |
| #define CLK_AFE_3RD_DAC_PREDIS (23) |
| #define CLK_AFE_3RD_DAC_TML (24) |
| #define CLK_AFE_3RD_DAC_HIRES (25) |
| #define CLK_AFE_I2S5_BCLK (26) |
| #define CLK_AFE_I2S6_BCLK (27) |
| #define CLK_AFE_I2S7_BCLK (28) |
| #define CLK_AFE_I2S8_BCLK (29) |
| #define CLK_AFE_I2S9_BCLK (30) |
| #define CLK_AFE_ETDM_IN0_BCLK (31) |
| #define CLK_AFE_ETDM_OUT0_BCLK (32) |
| #define CLK_AFE_I2S1_BCLK (33) |
| #define CLK_AFE_I2S2_BCLK (34) |
| #define CLK_AFE_I2S3_BCLK (35) |
| #define CLK_AFE_I2S4_BCLK (36) |
| #define CLK_AFE_ETDM_IN1_BCLK (37) |
| #define CLK_AFE_ETDM_OUT1_BCLK (38) |
| #define CLK_AFE_NR_CLK 39 |
| |
| #define CLK_APU_ACX_CONFIG_AHB (0) |
| #define CLK_APU_ACX_CONFIG_AXI (1) |
| #define CLK_APU_ACX_CONFIG_ISP (2) |
| #define CLK_APU_ACX_CONFIG_CAM_ADL (3) |
| #define CLK_APU_ACX_CONFIG_IMG_ADL (4) |
| #define CLK_APU_ACX_CONFIG_EMI_26M (5) |
| #define CLK_APU_ACX_CONFIG_VPU_UDI (6) |
| #define CLK_APU_ACX_CONFIG_EDMA_0 (7) |
| #define CLK_APU_ACX_CONFIG_EDMA_1 (8) |
| #define CLK_APU_ACX_CONFIG_EDMAL_0 (9) |
| #define CLK_APU_ACX_CONFIG_EDMAL_1 (10) |
| #define CLK_APU_ACX_CONFIG_MNOC (11) |
| #define CLK_APU_ACX_CONFIG_TCM (12) |
| #define CLK_APU_ACX_CONFIG_MD32 (13) |
| #define CLK_APU_ACX_CONFIG_IOMMU_0 (14) |
| #define CLK_APU_ACX_CONFIG_IOMMU_1 (15) |
| #define CLK_APU_ACX_CONFIG_MD32_32K (16) |
| #define CLK_APU_ACX_CONFIG_CPE (17) |
| #define CLK_APU_ACX_CONFIG_NR_CLK 18 |
| |
| #define CLK_APU_DLA_0_CONFIG_MDLA_CG0 (0) |
| #define CLK_APU_DLA_0_CONFIG_MDLA_CG1 (1) |
| #define CLK_APU_DLA_0_CONFIG_MDLA_CG2 (2) |
| #define CLK_APU_DLA_0_CONFIG_MDLA_CG3 (3) |
| #define CLK_APU_DLA_0_CONFIG_MDLA_CG4 (4) |
| #define CLK_APU_DLA_0_CONFIG_MDLA_CG5 (5) |
| #define CLK_APU_DLA_0_CONFIG_MDLA_CG6 (6) |
| #define CLK_APU_DLA_0_CONFIG_MDLA_CG7 (7) |
| #define CLK_APU_DLA_0_CONFIG_MDLA_CG8 (8) |
| #define CLK_APU_DLA_0_CONFIG_MDLA_CG9 (9) |
| #define CLK_APU_DLA_0_CONFIG_MDLA_CG10 (10) |
| #define CLK_APU_DLA_0_CONFIG_MDLA_CG11 (11) |
| #define CLK_APU_DLA_0_CONFIG_MDLA_CG12 (12) |
| #define CLK_APU_DLA_0_CONFIG_MDLA_CG13 (13) |
| #define CLK_APU_DLA_0_CONFIG_MDLA_CG14 (14) |
| #define CLK_APU_DLA_0_CONFIG_MDLA_CG15 (15) |
| #define CLK_APU_DLA_0_CONFIG_MDLA_CG16 (16) |
| #define CLK_APU_DLA_0_CONFIG_MDLA_CG17 (17) |
| #define CLK_APU_DLA_0_CONFIG_MDLA_CG18 (18) |
| #define CLK_APU_DLA_0_CONFIG_MDLA_CG19 (19) |
| #define CLK_APU_DLA_0_CONFIG_MDLA_CG20 (20) |
| #define CLK_APU_DLA_0_CONFIG_APB (21) |
| #define CLK_APU_DLA_0_CONFIG_AXI_M (22) |
| #define CLK_APU_DLA_0_CONFIG_JTAG (23) |
| #define CLK_APU_DLA_0_CONFIG_NR_CLK 24 |
| |
| #define CLK_APU_DLA_1_CONFIG_MDLA_CG0 (0) |
| #define CLK_APU_DLA_1_CONFIG_MDLA_CG1 (1) |
| #define CLK_APU_DLA_1_CONFIG_MDLA_CG2 (2) |
| #define CLK_APU_DLA_1_CONFIG_MDLA_CG3 (3) |
| #define CLK_APU_DLA_1_CONFIG_MDLA_CG4 (4) |
| #define CLK_APU_DLA_1_CONFIG_MDLA_CG5 (5) |
| #define CLK_APU_DLA_1_CONFIG_MDLA_CG6 (6) |
| #define CLK_APU_DLA_1_CONFIG_MDLA_CG7 (7) |
| #define CLK_APU_DLA_1_CONFIG_MDLA_CG8 (8) |
| #define CLK_APU_DLA_1_CONFIG_MDLA_CG9 (9) |
| #define CLK_APU_DLA_1_CONFIG_MDLA_CG10 (10) |
| #define CLK_APU_DLA_1_CONFIG_MDLA_CG11 (11) |
| #define CLK_APU_DLA_1_CONFIG_MDLA_CG12 (12) |
| #define CLK_APU_DLA_1_CONFIG_MDLA_CG13 (13) |
| #define CLK_APU_DLA_1_CONFIG_MDLA_CG14 (14) |
| #define CLK_APU_DLA_1_CONFIG_MDLA_CG15 (15) |
| #define CLK_APU_DLA_1_CONFIG_MDLA_CG16 (16) |
| #define CLK_APU_DLA_1_CONFIG_MDLA_CG17 (17) |
| #define CLK_APU_DLA_1_CONFIG_MDLA_CG18 (18) |
| #define CLK_APU_DLA_1_CONFIG_MDLA_CG19 (19) |
| #define CLK_APU_DLA_1_CONFIG_MDLA_CG20 (20) |
| #define CLK_APU_DLA_1_CONFIG_APB (21) |
| #define CLK_APU_DLA_1_CONFIG_AXI_M (22) |
| #define CLK_APU_DLA_1_CONFIG_JTAG (23) |
| #define CLK_APU_DLA_1_CONFIG_NR_CLK 24 |
| |
| #define CLK_APU_DLA_2_CONFIG_MDLA_CG0 (0) |
| #define CLK_APU_DLA_2_CONFIG_MDLA_CG1 (1) |
| #define CLK_APU_DLA_2_CONFIG_MDLA_CG2 (2) |
| #define CLK_APU_DLA_2_CONFIG_MDLA_CG3 (3) |
| #define CLK_APU_DLA_2_CONFIG_MDLA_CG4 (4) |
| #define CLK_APU_DLA_2_CONFIG_MDLA_CG5 (5) |
| #define CLK_APU_DLA_2_CONFIG_MDLA_CG6 (6) |
| #define CLK_APU_DLA_2_CONFIG_MDLA_CG7 (7) |
| #define CLK_APU_DLA_2_CONFIG_MDLA_CG8 (8) |
| #define CLK_APU_DLA_2_CONFIG_MDLA_CG9 (9) |
| #define CLK_APU_DLA_2_CONFIG_MDLA_CG10 (10) |
| #define CLK_APU_DLA_2_CONFIG_MDLA_CG11 (11) |
| #define CLK_APU_DLA_2_CONFIG_MDLA_CG12 (12) |
| #define CLK_APU_DLA_2_CONFIG_MDLA_CG13 (13) |
| #define CLK_APU_DLA_2_CONFIG_MDLA_CG14 (14) |
| #define CLK_APU_DLA_2_CONFIG_MDLA_CG15 (15) |
| #define CLK_APU_DLA_2_CONFIG_MDLA_CG16 (16) |
| #define CLK_APU_DLA_2_CONFIG_MDLA_CG17 (17) |
| #define CLK_APU_DLA_2_CONFIG_MDLA_CG18 (18) |
| #define CLK_APU_DLA_2_CONFIG_MDLA_CG19 (19) |
| #define CLK_APU_DLA_2_CONFIG_MDLA_CG20 (20) |
| #define CLK_APU_DLA_2_CONFIG_APB (21) |
| #define CLK_APU_DLA_2_CONFIG_AXI_M (22) |
| #define CLK_APU_DLA_2_CONFIG_JTAG (23) |
| #define CLK_APU_DLA_2_CONFIG_NR_CLK 24 |
| |
| #define CLK_APU_DLA_3_CONFIG_MDLA_CG0 (0) |
| #define CLK_APU_DLA_3_CONFIG_MDLA_CG1 (1) |
| #define CLK_APU_DLA_3_CONFIG_MDLA_CG2 (2) |
| #define CLK_APU_DLA_3_CONFIG_MDLA_CG3 (3) |
| #define CLK_APU_DLA_3_CONFIG_MDLA_CG4 (4) |
| #define CLK_APU_DLA_3_CONFIG_MDLA_CG5 (5) |
| #define CLK_APU_DLA_3_CONFIG_MDLA_CG6 (6) |
| #define CLK_APU_DLA_3_CONFIG_MDLA_CG7 (7) |
| #define CLK_APU_DLA_3_CONFIG_MDLA_CG8 (8) |
| #define CLK_APU_DLA_3_CONFIG_MDLA_CG9 (9) |
| #define CLK_APU_DLA_3_CONFIG_MDLA_CG10 (10) |
| #define CLK_APU_DLA_3_CONFIG_MDLA_CG11 (11) |
| #define CLK_APU_DLA_3_CONFIG_MDLA_CG12 (12) |
| #define CLK_APU_DLA_3_CONFIG_MDLA_CG13 (13) |
| #define CLK_APU_DLA_3_CONFIG_MDLA_CG14 (14) |
| #define CLK_APU_DLA_3_CONFIG_MDLA_CG15 (15) |
| #define CLK_APU_DLA_3_CONFIG_MDLA_CG16 (16) |
| #define CLK_APU_DLA_3_CONFIG_MDLA_CG17 (17) |
| #define CLK_APU_DLA_3_CONFIG_MDLA_CG18 (18) |
| #define CLK_APU_DLA_3_CONFIG_MDLA_CG19 (19) |
| #define CLK_APU_DLA_3_CONFIG_MDLA_CG20 (20) |
| #define CLK_APU_DLA_3_CONFIG_APB (21) |
| #define CLK_APU_DLA_3_CONFIG_AXI_M (22) |
| #define CLK_APU_DLA_3_CONFIG_JTAG (23) |
| #define CLK_APU_DLA_3_CONFIG_NR_CLK 24 |
| |
| #define CLK_APU_RCX_CONFIG_AXI (0) |
| #define CLK_APU_RCX_CONFIG_MNOC (1) |
| #define CLK_APU_RCX_CONFIG_UP (2) |
| #define CLK_APU_RCX_CONFIG_IOMMU_0 (3) |
| #define CLK_APU_RCX_CONFIG_IOMMU_1 (4) |
| #define CLK_APU_RCX_CONFIG_CPE_26M (5) |
| #define CLK_APU_RCX_CONFIG_EMI_26M (6) |
| #define CLK_APU_RCX_CONFIG_MD32 (7) |
| #define CLK_APU_RCX_CONFIG_MD32_32K (8) |
| #define CLK_APU_RCX_CONFIG_NR_CLK 9 |
| |
| #define CLK_APU_RCX_VCORE_CONFIG_AHB (0) |
| #define CLK_APU_RCX_VCORE_CONFIG_AXI (1) |
| #define CLK_APU_RCX_VCORE_CONFIG_ADL (2) |
| #define CLK_APU_RCX_VCORE_CONFIG_QOS (3) |
| #define CLK_APU_RCX_VCORE_CONFIG_NR_CLK 4 |
| |
| #define CLK_CAMSYS_MRAW_LARBX (0) |
| #define CLK_CAMSYS_MRAW_CAMTG (1) |
| #define CLK_CAMSYS_MRAW_MRAW0 (2) |
| #define CLK_CAMSYS_MRAW_MRAW1 (3) |
| #define CLK_CAMSYS_MRAW_MRAW2 (4) |
| #define CLK_CAMSYS_MRAW_MRAW3 (5) |
| #define CLK_CAMSYS_MRAW_PDA0 (6) |
| #define CLK_CAMSYS_MRAW_PDA1 (7) |
| #define CLK_CAMSYS_MRAW_LARBXT (8) |
| #define CLK_CAMSYS_MRAW_NR_CLK 9 |
| |
| #define CLK_CAM_RA_LARBX (0) |
| #define CLK_CAM_RA_CAM (1) |
| #define CLK_CAM_RA_CAMTG (2) |
| #define CLK_CAM_RA_LARBXT (3) |
| #define CLK_CAM_RA_NR_CLK 4 |
| |
| #define CLK_CAM_RB_LARBX (0) |
| #define CLK_CAM_RB_CAM (1) |
| #define CLK_CAM_RB_CAMTG (2) |
| #define CLK_CAM_RB_LARBXT (3) |
| #define CLK_CAM_RB_NR_CLK 4 |
| |
| #define CLK_CAM_RC_LARBX (0) |
| #define CLK_CAM_RC_CAM (1) |
| #define CLK_CAM_RC_CAMTG (2) |
| #define CLK_CAM_RC_LARBXT (3) |
| #define CLK_CAM_RC_NR_CLK 4 |
| |
| #define CLK_CAMSYS_YUVA_LARBX (0) |
| #define CLK_CAMSYS_YUVA_CAM (1) |
| #define CLK_CAMSYS_YUVA_CAMTG (2) |
| #define CLK_CAMSYS_YUVA_LARBXT (3) |
| #define CLK_CAMSYS_YUVA_NR_CLK 4 |
| |
| #define CLK_CAMSYS_YUVB_LARBX (0) |
| #define CLK_CAMSYS_YUVB_CAM (1) |
| #define CLK_CAMSYS_YUVB_CAMTG (2) |
| #define CLK_CAMSYS_YUVB_LARBXT (3) |
| #define CLK_CAMSYS_YUVB_NR_CLK 4 |
| |
| #define CLK_CAMSYS_YUVC_LARBX (0) |
| #define CLK_CAMSYS_YUVC_CAM (1) |
| #define CLK_CAMSYS_YUVC_CAMTG (2) |
| #define CLK_CAMSYS_YUVC_LARBXT (3) |
| #define CLK_CAMSYS_YUVC_NR_CLK 4 |
| |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_LARB13_CG_CON (0) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_LARB14_CG_CON (1) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_CAM_CG_CON (2) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_CAM_SUBA_CG_CON (3) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_CAM_SUBB_CG_CON (4) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_CAM_SUBC_CG_CON (5) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_CAM_MRAW_CG_CON (6) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_CAMTG_CG_CON (7) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_SENINF_CG_CON (8) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_GCAMSVA_CG_CON (9) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_GCAMSVB_CG_CON (10) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_GCAMSVC_CG_CON (11) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_GCAMSVD_CG_CON (12) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_GCAMSVE_CG_CON (13) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_GCAMSVF_CG_CON (14) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_GCAMSVG_CG_CON (15) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_GCAMSVH_CG_CON (16) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_GCAMSVI_CG_CON (17) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_GCAMSVJ_CG_CON (18) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_CAMSV_TOP_CG_CON (19) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_CAMSV_CQ_A_CG_CON (20) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_CAMSV_CQ_B_CG_CON (21) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_CAMSV_CQ_C_CG_CON (22) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_ADL_CG_CON (23) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_ASG_CG_CON (24) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_PDA0_CG_CON (25) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_PDA1_CG_CON (26) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_PDA2_CG_CON (27) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_FAKE_ENG_CG_CON (28) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_CAM2MM0_GALS_CG_CON (29) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_CAM2MM1_GALS_CG_CON (30) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_CAM2SYS_GALS_CG_CON (31) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_CAM_SUBA (32) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_CAM_SUBB (33) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_CAM_SUBC (34) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_CAM_MRAW (35) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_LARB13R_CG_CON (36) |
| #define CLK_CAM_MAIN_R1A_CAM_MAIN_LARB14R_CG_CON (37) |
| #define CLK_CAM_MAIN_R1A_NR_CLK 38 |
| |
| #define CLK_CCU_MAIN_LARB19 (0) |
| #define CLK_CCU_MAIN_AHB (1) |
| #define CLK_CCU_MAIN_CCUSYS_CCU0 (2) |
| #define CLK_CCU_MAIN_CCUSYS_CCU1 (3) |
| #define CLK_CCU_MAIN_NR_CLK 4 |
| |
| #define CLK_DIP_NR_DIP1_LARB15 (0) |
| #define CLK_DIP_NR_DIP1_DIP_NR (1) |
| #define CLK_DIP_NR_DIP1_NR_CLK 2 |
| |
| #define CLK_DIP_TOP_DIP1_LARB10 (0) |
| #define CLK_DIP_TOP_DIP1_DIP_TOP (1) |
| #define CLK_DIP_TOP_DIP1_NR_CLK 2 |
| |
| #define CLK_DISPSYS1_CONFIG_DISP_MUTEX (0) |
| #define CLK_DISPSYS1_CONFIG_DISP_OVL0 (1) |
| #define CLK_DISPSYS1_CONFIG_DISP_MERGE0 (2) |
| #define CLK_DISPSYS1_CONFIG_DISP_FAKE_ENG0 (3) |
| #define CLK_DISPSYS1_CONFIG_INLINEROT (4) |
| #define CLK_DISPSYS1_CONFIG_DISP_WDMA0 (5) |
| #define CLK_DISPSYS1_CONFIG_DISP_FAKE_ENG1 (6) |
| #define CLK_DISPSYS1_CONFIG_DISP_DPI0 (7) |
| #define CLK_DISPSYS1_CONFIG_DISP_OVL0_2L_NWCG (8) |
| #define CLK_DISPSYS1_CONFIG_DISP_RDMA0 (9) |
| #define CLK_DISPSYS1_CONFIG_DISP_RDMA1 (10) |
| #define CLK_DISPSYS1_CONFIG_DISP_DLI_ASYNC0 (11) |
| #define CLK_DISPSYS1_CONFIG_DISP_DLI_ASYNC1 (12) |
| #define CLK_DISPSYS1_CONFIG_DISP_DLI_ASYNC2 (13) |
| #define CLK_DISPSYS1_CONFIG_DISP_DLO_ASYNC0 (14) |
| #define CLK_DISPSYS1_CONFIG_DISP_DLO_ASYNC1 (15) |
| #define CLK_DISPSYS1_CONFIG_DISP_DLO_ASYNC2 (16) |
| #define CLK_DISPSYS1_CONFIG_DISP_RSZ0 (17) |
| #define CLK_DISPSYS1_CONFIG_DISP_COLOR0 (18) |
| #define CLK_DISPSYS1_CONFIG_DISP_CCORR0 (19) |
| #define CLK_DISPSYS1_CONFIG_DISP_CCORR1 (20) |
| #define CLK_DISPSYS1_CONFIG_DISP_AAL0 (21) |
| #define CLK_DISPSYS1_CONFIG_DISP_GAMMA0 (22) |
| #define CLK_DISPSYS1_CONFIG_DISP_POSTMASK0 (23) |
| #define CLK_DISPSYS1_CONFIG_DISP_DITHER0 (24) |
| #define CLK_DISPSYS1_CONFIG_DISP_CM0 (25) |
| #define CLK_DISPSYS1_CONFIG_DISP_SPR0 (26) |
| #define CLK_DISPSYS1_CONFIG_DISP_DSC_WRAP0 (27) |
| #define CLK_DISPSYS1_CONFIG_DISP_DSI0 (28) |
| #define CLK_DISPSYS1_CONFIG_DISP_UFBC_WDMA0 (29) |
| #define CLK_DISPSYS1_CONFIG_DISP_WDMA1 (30) |
| #define CLK_DISPSYS1_CONFIG_DISP_DP_INTF0 (31) |
| #define CLK_DISPSYS1_CONFIG_APB_BUS (32) |
| #define CLK_DISPSYS1_CONFIG_DISP_TDSHP0 (33) |
| #define CLK_DISPSYS1_CONFIG_DISP_C3D0 (34) |
| #define CLK_DISPSYS1_CONFIG_DISP_Y2R0 (35) |
| #define CLK_DISPSYS1_CONFIG_DISP_MDP_AAL0 (36) |
| #define CLK_DISPSYS1_CONFIG_DISP_CHIST0 (37) |
| #define CLK_DISPSYS1_CONFIG_DISP_CHIST1 (38) |
| #define CLK_DISPSYS1_CONFIG_DISP_OVL0_2L (39) |
| #define CLK_DISPSYS1_CONFIG_DISP_DLI_ASYNC3 (40) |
| #define CLK_DISPSYS1_CONFIG_DISP_DLO_ASYNC3 (41) |
| #define CLK_DISPSYS1_CONFIG_DISP_OVL1_2L (42) |
| #define CLK_DISPSYS1_CONFIG_DISP_OVL1_2L_NWCG (43) |
| #define CLK_DISPSYS1_CONFIG_SMI_SUB_COMM (44) |
| #define CLK_DISPSYS1_CONFIG_DSI_CLK (45) |
| #define CLK_DISPSYS1_CONFIG_DP_CLK (46) |
| #define CLK_DISPSYS1_CONFIG_26M_CLK (47) |
| #define CLK_DISPSYS1_CONFIG_NR_CLK 48 |
| |
| #define CLK_DISPSYS_CONFIG_DISP_MUTEX (0) |
| #define CLK_DISPSYS_CONFIG_DISP_OVL0 (1) |
| #define CLK_DISPSYS_CONFIG_DISP_MERGE0 (2) |
| #define CLK_DISPSYS_CONFIG_DISP_FAKE_ENG0 (3) |
| #define CLK_DISPSYS_CONFIG_INLINEROT (4) |
| #define CLK_DISPSYS_CONFIG_DISP_WDMA0 (5) |
| #define CLK_DISPSYS_CONFIG_DISP_FAKE_ENG1 (6) |
| #define CLK_DISPSYS_CONFIG_DISP_DPI0 (7) |
| #define CLK_DISPSYS_CONFIG_DISP_OVL0_2L_NWCG (8) |
| #define CLK_DISPSYS_CONFIG_DISP_RDMA0 (9) |
| #define CLK_DISPSYS_CONFIG_DISP_RDMA1 (10) |
| #define CLK_DISPSYS_CONFIG_DISP_DLI_ASYNC0 (11) |
| #define CLK_DISPSYS_CONFIG_DISP_DLI_ASYNC1 (12) |
| #define CLK_DISPSYS_CONFIG_DISP_DLI_ASYNC2 (13) |
| #define CLK_DISPSYS_CONFIG_DISP_DLO_ASYNC0 (14) |
| #define CLK_DISPSYS_CONFIG_DISP_DLO_ASYNC1 (15) |
| #define CLK_DISPSYS_CONFIG_DISP_DLO_ASYNC2 (16) |
| #define CLK_DISPSYS_CONFIG_DISP_RSZ0 (17) |
| #define CLK_DISPSYS_CONFIG_DISP_COLOR0 (18) |
| #define CLK_DISPSYS_CONFIG_DISP_CCORR0 (19) |
| #define CLK_DISPSYS_CONFIG_DISP_CCORR1 (20) |
| #define CLK_DISPSYS_CONFIG_DISP_AAL0 (21) |
| #define CLK_DISPSYS_CONFIG_DISP_GAMMA0 (22) |
| #define CLK_DISPSYS_CONFIG_DISP_POSTMASK0 (23) |
| #define CLK_DISPSYS_CONFIG_DISP_DITHER0 (24) |
| #define CLK_DISPSYS_CONFIG_DISP_CM0 (25) |
| #define CLK_DISPSYS_CONFIG_DISP_SPR0 (26) |
| #define CLK_DISPSYS_CONFIG_DISP_DSC_WRAP0 (27) |
| #define CLK_DISPSYS_CONFIG_DISP_DSI0 (28) |
| #define CLK_DISPSYS_CONFIG_DISP_UFBC_WDMA0 (29) |
| #define CLK_DISPSYS_CONFIG_DISP_WDMA1 (30) |
| #define CLK_DISPSYS_CONFIG_DISP_DP_INTF0 (31) |
| #define CLK_DISPSYS_CONFIG_APB_BUS (32) |
| #define CLK_DISPSYS_CONFIG_DISP_TDSHP0 (33) |
| #define CLK_DISPSYS_CONFIG_DISP_C3D0 (34) |
| #define CLK_DISPSYS_CONFIG_DISP_Y2R0 (35) |
| #define CLK_DISPSYS_CONFIG_DISP_MDP_AAL0 (36) |
| #define CLK_DISPSYS_CONFIG_DISP_CHIST0 (37) |
| #define CLK_DISPSYS_CONFIG_DISP_CHIST1 (38) |
| #define CLK_DISPSYS_CONFIG_DISP_OVL0_2L (39) |
| #define CLK_DISPSYS_CONFIG_DISP_DLI_ASYNC3 (40) |
| #define CLK_DISPSYS_CONFIG_DISP_DLO_ASYNC3 (41) |
| #define CLK_DISPSYS_CONFIG_DISP_OVL1_2L (42) |
| #define CLK_DISPSYS_CONFIG_DISP_OVL1_2L_NWCG (43) |
| #define CLK_DISPSYS_CONFIG_SMI_SUB_COMM (44) |
| #define CLK_DISPSYS_CONFIG_DSI_CLK (45) |
| #define CLK_DISPSYS_CONFIG_DP_CLK (46) |
| #define CLK_DISPSYS_CONFIG_26M_CLK (47) |
| #define CLK_DISPSYS_CONFIG_NR_CLK 48 |
| |
| #define CLK_IMGSYS_MAIN_LARB9 (0) |
| #define CLK_IMGSYS_MAIN_TRAW0 (1) |
| #define CLK_IMGSYS_MAIN_TRAW1 (2) |
| #define CLK_IMGSYS_MAIN_VCORE_GALS (3) |
| #define CLK_IMGSYS_MAIN_DIP0 (4) |
| #define CLK_IMGSYS_MAIN_WPE0 (5) |
| #define CLK_IMGSYS_MAIN_IPE (6) |
| #define CLK_IMGSYS_MAIN_WPE1 (7) |
| #define CLK_IMGSYS_MAIN_WPE2 (8) |
| #define CLK_IMGSYS_MAIN_ADL_LARB (9) |
| #define CLK_IMGSYS_MAIN_ADL_TOP0 (10) |
| #define CLK_IMGSYS_MAIN_ADL_TOP1 (11) |
| #define CLK_IMGSYS_MAIN_GALS (12) |
| #define CLK_IMGSYS_MAIN_DIP0T (13) |
| #define CLK_IMGSYS_MAIN_WPE0T (14) |
| #define CLK_IMGSYS_MAIN_IPET (15) |
| #define CLK_IMGSYS_MAIN_WPE1T (16) |
| #define CLK_IMGSYS_MAIN_WPE2T (17) |
| #define CLK_IMGSYS_MAIN_NR_CLK 18 |
| |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C10 (0) |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C11 (1) |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C12 (2) |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C13 (3) |
| #define CLK_IMP_IIC_WRAP0_NR_CLK 4 |
| |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1 (0) |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2 (1) |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3 (2) |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4 (3) |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7 (4) |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8 (5) |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9 (6) |
| #define CLK_IMP_IIC_WRAP1_NR_CLK 7 |
| |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0 (0) |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5 (1) |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6 (2) |
| #define CLK_IMP_IIC_WRAP2_NR_CLK 3 |
| |
| #define CLK_IFR_AO_CGEN_PRE_INFRA_BUS_HRE_SYS_CLK (0) |
| #define CLK_IFR_AO_INFRA_DCM_RG_FORCE (1) |
| #define CLK_IFR_AO_THERM (2) |
| #define CLK_IFR_AO_CQ_DMA_FPC (3) |
| #define CLK_IFR_AO_TRNG (4) |
| #define CLK_IFR_AO_CPUM (5) |
| #define CLK_IFR_AO_CCIF1_AP (6) |
| #define CLK_IFR_AO_CCIF1_MD (7) |
| #define CLK_IFR_AO_CCIF_AP (8) |
| #define CLK_IFR_AO_DEBUGSYS (9) |
| #define CLK_IFR_AO_CCIF_MD (10) |
| #define CLK_IFR_AO_DXCC_SEC_CORE (11) |
| #define CLK_IFR_AO_DXCC_AO (12) |
| #define CLK_IFR_AO_DBG_TRACE (13) |
| #define CLK_IFR_AO_CLDMA_BCLK (14) |
| #define CLK_IFR_AO_CQ_DMA (15) |
| #define CLK_IFR_AO_CCIF5_AP (16) |
| #define CLK_IFR_AO_CCIF5_MD (17) |
| #define CLK_IFR_AO_CCIF2_AP (18) |
| #define CLK_IFR_AO_CCIF2_MD (19) |
| #define CLK_IFR_AO_CCIF3_AP (20) |
| #define CLK_IFR_AO_CCIF3_MD (21) |
| #define CLK_IFR_AO_FBIST2FPC (22) |
| #define CLK_IFR_AO_DEVICE_APC_SYNC (23) |
| #define CLK_IFR_AO_DPMAIF_MAIN (24) |
| #define CLK_IFR_AO_CCIF4_AP (25) |
| #define CLK_IFR_AO_CCIF4_MD (26) |
| #define CLK_IFR_AO_RG_MMW_DPMAIF_F26M_CK (27) |
| #define CLK_IFR_AO_RG_HF_FMEM_SUB_CK (28) |
| #define CLK_IFR_AO_NR_CLK 29 |
| |
| #define CLK_IPESYS_DPE (0) |
| #define CLK_IPESYS_FDVT (1) |
| #define CLK_IPESYS_ME (2) |
| #define CLK_IPESYS_IPESYS_TOP (3) |
| #define CLK_IPESYS_SMI_LARB12 (4) |
| #define CLK_IPESYS_FDVT1 (5) |
| #define CLK_IPESYS_NR_CLK 6 |
| |
| #define CLK_MDPSYS1_CONFIG_MDP_MUTEX0 (0) |
| #define CLK_MDPSYS1_CONFIG_APB_BUS (1) |
| #define CLK_MDPSYS1_CONFIG_SMI0 (2) |
| #define CLK_MDPSYS1_CONFIG_MDP_RDMA0 (3) |
| #define CLK_MDPSYS1_CONFIG_MDP_FG0 (4) |
| #define CLK_MDPSYS1_CONFIG_MDP_HDR0 (5) |
| #define CLK_MDPSYS1_CONFIG_MDP_AAL0 (6) |
| #define CLK_MDPSYS1_CONFIG_MDP_RSZ0 (7) |
| #define CLK_MDPSYS1_CONFIG_MDP_TDSHP0 (8) |
| #define CLK_MDPSYS1_CONFIG_MDP_COLOR0 (9) |
| #define CLK_MDPSYS1_CONFIG_MDP_WROT0 (10) |
| #define CLK_MDPSYS1_CONFIG_MDP_FAKE_ENG0 (11) |
| #define CLK_MDPSYS1_CONFIG_IMG_DL_RELAY0 (12) |
| #define CLK_MDPSYS1_CONFIG_IMG_DL_RELAY1 (13) |
| #define CLK_MDPSYS1_CONFIG_MDP_RDMA1 (14) |
| #define CLK_MDPSYS1_CONFIG_MDP_FG1 (15) |
| #define CLK_MDPSYS1_CONFIG_MDP_HDR1 (16) |
| #define CLK_MDPSYS1_CONFIG_MDP_AAL1 (17) |
| #define CLK_MDPSYS1_CONFIG_MDP_RSZ1 (18) |
| #define CLK_MDPSYS1_CONFIG_MDP_TDSHP1 (19) |
| #define CLK_MDPSYS1_CONFIG_MDP_COLOR1 (20) |
| #define CLK_MDPSYS1_CONFIG_MDP_WROT1 (21) |
| #define CLK_MDPSYS1_CONFIG_MDP_RSZ2 (22) |
| #define CLK_MDPSYS1_CONFIG_MDP_WROT2 (23) |
| #define CLK_MDPSYS1_CONFIG_MDP_DLO_ASYNC0 (24) |
| #define CLK_MDPSYS1_CONFIG_MDP_RSZ3 (25) |
| #define CLK_MDPSYS1_CONFIG_MDP_WROT3 (26) |
| #define CLK_MDPSYS1_CONFIG_MDP_DLO_ASYNC1 (27) |
| #define CLK_MDPSYS1_CONFIG_HRE_TOP_MDPSYS (28) |
| #define CLK_MDPSYS1_CONFIG_NR_CLK 29 |
| |
| #define CLK_MDP_MDP_MUTEX0 (0) |
| #define CLK_MDP_APB_BUS (1) |
| #define CLK_MDP_SMI0 (2) |
| #define CLK_MDP_MDP_RDMA0 (3) |
| #define CLK_MDP_MDP_FG0 (4) |
| #define CLK_MDP_MDP_HDR0 (5) |
| #define CLK_MDP_MDP_AAL0 (6) |
| #define CLK_MDP_MDP_RSZ0 (7) |
| #define CLK_MDP_MDP_TDSHP0 (8) |
| #define CLK_MDP_MDP_COLOR0 (9) |
| #define CLK_MDP_MDP_WROT0 (10) |
| #define CLK_MDP_MDP_FAKE_ENG0 (11) |
| #define CLK_MDP_IMG_DL_RELAY0 (12) |
| #define CLK_MDP_IMG_DL_RELAY1 (13) |
| #define CLK_MDP_MDP_RDMA1 (14) |
| #define CLK_MDP_MDP_FG1 (15) |
| #define CLK_MDP_MDP_HDR1 (16) |
| #define CLK_MDP_MDP_AAL1 (17) |
| #define CLK_MDP_MDP_RSZ1 (18) |
| #define CLK_MDP_MDP_TDSHP1 (19) |
| #define CLK_MDP_MDP_COLOR1 (20) |
| #define CLK_MDP_MDP_WROT1 (21) |
| #define CLK_MDP_MDP_RSZ2 (22) |
| #define CLK_MDP_MDP_WROT2 (23) |
| #define CLK_MDP_MDP_DLO_ASYNC0 (24) |
| #define CLK_MDP_MDP_RSZ3 (25) |
| #define CLK_MDP_MDP_WROT3 (26) |
| #define CLK_MDP_MDP_DLO_ASYNC1 (27) |
| #define CLK_MDP_HRE_TOP_MDPSYS (28) |
| #define CLK_MDP_NR_CLK 29 |
| |
| #define CLK_MFG_TOP_CONFIG_BG3D_PDN (0) |
| #define CLK_MFG_TOP_CONFIG_NR_CLK 1 |
| |
| #define CLK_MMINFRA_CONFIG_GCE_D (0) |
| #define CLK_MMINFRA_CONFIG_GCE_M (1) |
| #define CLK_MMINFRA_CONFIG_SMI (2) |
| #define CLK_MMINFRA_CONFIG_GCE_26M (3) |
| #define CLK_MMINFRA_CONFIG_NR_CLK 4 |
| |
| #define CLK_PERI_AO_PERI_UART0 (0) |
| #define CLK_PERI_AO_PERI_UART1 (1) |
| #define CLK_PERI_AO_PERI_UART2 (2) |
| #define CLK_PERI_AO_PERI_UART3 (3) |
| #define CLK_PERI_AO_PERI_PWM_HCLK (4) |
| #define CLK_PERI_AO_PERI_PWM_BCLK (5) |
| #define CLK_PERI_AO_PERI_PWM_FBCLK1 (6) |
| #define CLK_PERI_AO_PERI_PWM_FBCLK2 (7) |
| #define CLK_PERI_AO_PERI_PWM_FBCLK3 (8) |
| #define CLK_PERI_AO_PERI_PWM_FBCLK4 (9) |
| #define CLK_PERI_AO_PERI_BTIF_BCLK (10) |
| #define CLK_PERI_AO_PERI_DISP_PWM0 (11) |
| #define CLK_PERI_AO_PERI_DISP_PWM1 (12) |
| #define CLK_PERI_AO_PERI_SPI0_BCLK (13) |
| #define CLK_PERI_AO_PERI_SPI1_BCLK (14) |
| #define CLK_PERI_AO_PERI_SPI2_BCLK (15) |
| #define CLK_PERI_AO_PERI_SPI3_BCLK (16) |
| #define CLK_PERI_AO_PERI_SPI4_BCLK (17) |
| #define CLK_PERI_AO_PERI_SPI5_BCLK (18) |
| #define CLK_PERI_AO_PERI_SPI6_BCLK (19) |
| #define CLK_PERI_AO_PERI_SPI7_BCLK (20) |
| #define CLK_PERI_AO_PERI_SPI0_HCLK (21) |
| #define CLK_PERI_AO_PERI_SPI1_HCLK (22) |
| #define CLK_PERI_AO_PERI_SPI2_HCLK (23) |
| #define CLK_PERI_AO_PERI_SPI3_HCLK (24) |
| #define CLK_PERI_AO_PERI_SPI4_HCLK (25) |
| #define CLK_PERI_AO_PERI_SPI5_HCLK (26) |
| #define CLK_PERI_AO_PERI_SPI6_HCLK (27) |
| #define CLK_PERI_AO_PERI_SPI7_HCLK (28) |
| #define CLK_PERI_AO_PERI_FSFLASH (29) |
| #define CLK_PERI_AO_PERI_FSFLASH_FCLK (30) |
| #define CLK_PERI_AO_PERI_FSFLASH_HCLK (31) |
| #define CLK_PERI_AO_PERI_IIC (32) |
| #define CLK_PERI_AO_PERI_APDMA (33) |
| #define CLK_PERI_AO_PERI_SSUSB_PCLK (34) |
| #define CLK_PERI_AO_PERI_SSUSB_REF (35) |
| #define CLK_PERI_AO_PERI_SSUSB_FRMCNT (36) |
| #define CLK_PERI_AO_PERI_SSUSB_PHY (37) |
| #define CLK_PERI_AO_PERI_SSUSB_SYS (38) |
| #define CLK_PERI_AO_PERI_SSUSB_XHCI (39) |
| #define CLK_PERI_AO_PERI_SSUSB_DMA_BUS (40) |
| #define CLK_PERI_AO_PERI_SSUSB_MCU_BUS (41) |
| #define CLK_PERI_AO_PERI_SSUSB1_REF (42) |
| #define CLK_PERI_AO_PERI_SSUSB1_FRMCNT (43) |
| #define CLK_PERI_AO_PERI_SSUSB1_PHY (44) |
| #define CLK_PERI_AO_PERI_SSUSB1_SYS (45) |
| #define CLK_PERI_AO_PERI_SSUSB1_XHCI (46) |
| #define CLK_PERI_AO_PERI_SSUSB1_DMA_BUS (47) |
| #define CLK_PERI_AO_PERI_SSUSB1_MCU_BUS (48) |
| #define CLK_PERI_AO_PERI_MSDC1_S (49) |
| #define CLK_PERI_AO_PERI_MSDC1_H (50) |
| #define CLK_PERI_AO_PERI_MSDC2_S (51) |
| #define CLK_PERI_AO_PERI_MSDC2_H (52) |
| #define CLK_PERI_AO_PERI_PCIE0_26M (53) |
| #define CLK_PERI_AO_PERI_PCIE0_250M (54) |
| #define CLK_PERI_AO_PERI_PCIE0_GFMUX (55) |
| #define CLK_PERI_AO_PERI_PCIE1_26M (56) |
| #define CLK_PERI_AO_PERI_PCIE1_250M (57) |
| #define CLK_PERI_AO_PERI_PCIE1_GFMUX (58) |
| #define CLK_PERI_AO_PERI_PCIE0_MEM (59) |
| #define CLK_PERI_AO_PERI_PCIE1_MEM_CLR (60) |
| #define CLK_PERI_AO_PERI_PCIE0_PCIE1_HCLK_CLR (61) |
| #define CLK_PERI_AO_NR_CLK 62 |
| |
| #define CLK_VDE2_BASE_VDEC_CKEN (0) |
| #define CLK_VDE2_BASE_VDEC_ACTIVE (1) |
| #define CLK_VDE2_BASE_VDEC_CKEN_ENG (2) |
| #define CLK_VDE2_BASE_LAT_CKEN (3) |
| #define CLK_VDE2_BASE_LAT_ACTIVE (4) |
| #define CLK_VDE2_BASE_LAT_CKEN_ENG (5) |
| #define CLK_VDE2_BASE_LARB1_CKEN (6) |
| #define CLK_VDE2_BASE_NR_CLK 7 |
| |
| #define CLK_VDE1_BASE_VDEC_CKEN (0) |
| #define CLK_VDE1_BASE_VDEC_ACTIVE (1) |
| #define CLK_VDE1_BASE_VDEC_CKEN_ENG (2) |
| #define CLK_VDE1_BASE_MINI_MDP_CKEN (3) |
| #define CLK_VDE1_BASE_LAT_CKEN (4) |
| #define CLK_VDE1_BASE_LAT_ACTIVE (5) |
| #define CLK_VDE1_BASE_LAT_CKEN_ENG (6) |
| #define CLK_VDE1_BASE_LARB1_CKEN (7) |
| #define CLK_VDE1_BASE_NR_CLK 8 |
| |
| #define CLK_VEN1_CKE0_LARB (0) |
| #define CLK_VEN1_CKE1_VENC (1) |
| #define CLK_VEN1_CKE2_JPGENC (2) |
| #define CLK_VEN1_CKE3_JPGDEC (3) |
| #define CLK_VEN1_CKE4_JPGDEC_C1 (4) |
| #define CLK_VEN1_CKE5_GALS (5) |
| #define CLK_VEN1_CKE6_GALS_SRAM (6) |
| #define CLK_VEN1_NR_CLK 7 |
| |
| #define CLK_VEN1_CORE1_CKE0_LARB (0) |
| #define CLK_VEN1_CORE1_CKE1_VENC (1) |
| #define CLK_VEN1_CORE1_CKE2_JPGENC (2) |
| #define CLK_VEN1_CORE1_CKE3_JPGDEC (3) |
| #define CLK_VEN1_CORE1_CKE4_JPGDEC_C1 (4) |
| #define CLK_VEN1_CORE1_CKE5_GALS (5) |
| #define CLK_VEN1_CORE1_CKE6_GALS_SRAM (6) |
| #define CLK_VEN1_CORE1_NR_CLK 7 |
| |
| #define CLK_WPE1_DIP1_LARB11 (0) |
| #define CLK_WPE1_DIP1_WPE (1) |
| #define CLK_WPE1_DIP1_NR_CLK 2 |
| |
| #define CLK_WPE2_DIP1_LARB11 (0) |
| #define CLK_WPE2_DIP1_WPE (1) |
| #define CLK_WPE2_DIP1_NR_CLK 2 |
| |
| #define CLK_WPE3_DIP1_LARB11 (0) |
| #define CLK_WPE3_DIP1_WPE (1) |
| #define CLK_WPE3_DIP1_NR_CLK 2 |
| |
| |
| #define CLK_VLP_CKSYS_APXGPT66M_BCLK_SEL (0) |
| #define CLK_VLP_CKSYS_DXCC_VLP_SEL (1) |
| #define CLK_VLP_CKSYS_SCP_SEL (2) |
| #define CLK_VLP_CKSYS_DVFSRC_SEL (3) |
| #define CLK_VLP_CKSYS_PWM_VLP_SEL (4) |
| #define CLK_VLP_CKSYS_AXI_VLP_SEL (5) |
| #define CLK_VLP_CKSYS_DBGAO_26M_SEL (6) |
| #define CLK_VLP_CKSYS_SYSTIMER_26M_SEL (7) |
| #define CLK_VLP_CKSYS_SSPM_SEL (8) |
| #define CLK_VLP_CKSYS_SSPM_F26M_SEL (9) |
| #define CLK_VLP_CKSYS_APEINT_66M_SEL (10) |
| #define CLK_VLP_CKSYS_SRCK_SEL (11) |
| #define CLK_VLP_CKSYS_SRAMRC_SEL (12) |
| #define CLK_VLP_CKSYS_SPMI_P_MST_SEL (13) |
| #define CLK_VLP_CKSYS_SPMI_M_MST_SEL (14) |
| #define CLK_VLP_CKSYS_PWRAP_ULPOSC_SEL (15) |
| #define CLK_VLP_CKSYS_NR_CLK 16 |
| |
| #define CLK_TOPCKGEN_ADSPPLL_CK CLK_TOP_ADSPPLL |
| #define CLK_TOPCKGEN_APLL1_CK CLK_TOP_APLL1 |
| #define CLK_TOPCKGEN_APLL1_D2 CLK_TOP_APLL1_D2 |
| #define CLK_TOPCKGEN_APLL1_D4 CLK_TOP_APLL1_D4 |
| #define CLK_TOPCKGEN_APLL1_D8 CLK_TOP_APLL1_D8 |
| #define CLK_TOPCKGEN_APLL2_CK CLK_TOP_APLL2 |
| #define CLK_TOPCKGEN_APLL2_D2 CLK_TOP_APLL2_D2 |
| #define CLK_TOPCKGEN_APLL2_D4 CLK_TOP_APLL2_D4 |
| #define CLK_TOPCKGEN_APLL2_D8 CLK_TOP_APLL2_D8 |
| #define CLK_TOPCKGEN_EMIPLL_CK CLK_TOP_EMIPLL |
| #define CLK_TOPCKGEN_IMGPLL_D2 CLK_TOP_IMGPLL_D2 |
| #define CLK_TOPCKGEN_IMGPLL_D5 CLK_TOP_IMGPLL_D5 |
| #define CLK_TOPCKGEN_MAINPLL_D3 CLK_TOP_MAINPLL_D3 |
| #define CLK_TOPCKGEN_MAINPLL_D4 CLK_TOP_MAINPLL_D4 |
| #define CLK_TOPCKGEN_MAINPLL_D4_D16 CLK_TOP_MAINPLL_D4_D16 |
| #define CLK_TOPCKGEN_MAINPLL_D4_D2 CLK_TOP_MAINPLL_D4_D2 |
| #define CLK_TOPCKGEN_MAINPLL_D4_D4 CLK_TOP_MAINPLL_D4_D4 |
| #define CLK_TOPCKGEN_MAINPLL_D4_D8 CLK_TOP_MAINPLL_D4_D8 |
| #define CLK_TOPCKGEN_MAINPLL_D5 CLK_TOP_MAINPLL_D5 |
| #define CLK_TOPCKGEN_MAINPLL_D5_D2 CLK_TOP_MAINPLL_D5_D2 |
| #define CLK_TOPCKGEN_MAINPLL_D5_D4 CLK_TOP_MAINPLL_D5_D4 |
| #define CLK_TOPCKGEN_MAINPLL_D5_D8 CLK_TOP_MAINPLL_D5_D8 |
| #define CLK_TOPCKGEN_MAINPLL_D6 CLK_TOP_MAINPLL_D6 |
| #define CLK_TOPCKGEN_MAINPLL_D6_D2 CLK_TOP_MAINPLL_D6_D2 |
| #define CLK_TOPCKGEN_MAINPLL_D6_D4 CLK_TOP_MAINPLL_D6_D4 |
| #define CLK_TOPCKGEN_MAINPLL_D6_D8 CLK_TOP_MAINPLL_D6_D8 |
| #define CLK_TOPCKGEN_MAINPLL_D7_D2 CLK_TOP_MAINPLL_D7_D2 |
| #define CLK_TOPCKGEN_MAINPLL_D7_D4 CLK_TOP_MAINPLL_D7_D4 |
| #define CLK_TOPCKGEN_MAINPLL_D7_D8 CLK_TOP_MAINPLL_D7_D8 |
| #define CLK_TOPCKGEN_MAINPLL_D9 CLK_TOP_MAINPLL_D9 |
| #define CLK_TOPCKGEN_MFGPLL_CK CLK_TOP_MFGPLL |
| #define CLK_TOPCKGEN_MFGSCPLL_CK CLK_TOP_MFGSCPLL |
| #define CLK_TOPCKGEN_MMPLL_D4 CLK_TOP_MMPLL_D4 |
| #define CLK_TOPCKGEN_MMPLL_D4_D2 CLK_TOP_MMPLL_D4_D2 |
| #define CLK_TOPCKGEN_MMPLL_D5 CLK_TOP_MMPLL_D5 |
| #define CLK_TOPCKGEN_MMPLL_D5_D2 CLK_TOP_MMPLL_D5_D2 |
| #define CLK_TOPCKGEN_MMPLL_D6 CLK_TOP_MMPLL_D6 |
| #define CLK_TOPCKGEN_MMPLL_D6_D2 CLK_TOP_MMPLL_D6_D2 |
| #define CLK_TOPCKGEN_MMPLL_D7 CLK_TOP_MMPLL_D7 |
| #define CLK_TOPCKGEN_MMPLL_D9 CLK_TOP_MMPLL_D9 |
| #define CLK_TOPCKGEN_MSDCPLL_CK CLK_TOP_MSDCPLL |
| #define CLK_TOPCKGEN_MSDCPLL_D2 CLK_TOP_MSDCPLL_D2 |
| #define CLK_TOPCKGEN_TVDPLL_CK CLK_TOP_TVDPLL |
| #define CLK_TOPCKGEN_TVDPLL_D16 CLK_TOP_TVDPLL_D16 |
| #define CLK_TOPCKGEN_TVDPLL_D2 CLK_TOP_TVDPLL_D2 |
| #define CLK_TOPCKGEN_TVDPLL_D4 CLK_TOP_TVDPLL_D4 |
| #define CLK_TOPCKGEN_TVDPLL_D8 CLK_TOP_TVDPLL_D8 |
| #define CLK_TOPCKGEN_UNIVPLL_192M_D10 CLK_TOP_UNIVPLL_192M_D10 |
| #define CLK_TOPCKGEN_UNIVPLL_192M_D16 CLK_TOP_UNIVPLL_192M_D16 |
| #define CLK_TOPCKGEN_UNIVPLL_192M_D2 CLK_TOP_UNIVPLL_192M_D2 |
| #define CLK_TOPCKGEN_UNIVPLL_192M_D32 CLK_TOP_UNIVPLL_192M_D32 |
| #define CLK_TOPCKGEN_UNIVPLL_192M_D8 CLK_TOP_UNIVPLL_192M_D8 |
| #define CLK_TOPCKGEN_UNIVPLL_D3 CLK_TOP_UNIVPLL_D3 |
| #define CLK_TOPCKGEN_UNIVPLL_D4 CLK_TOP_UNIVPLL_D4 |
| #define CLK_TOPCKGEN_UNIVPLL_D4_D2 CLK_TOP_UNIVPLL_D4_D2 |
| #define CLK_TOPCKGEN_UNIVPLL_D4_D4 CLK_TOP_UNIVPLL_D4_D4 |
| #define CLK_TOPCKGEN_UNIVPLL_D4_D8 CLK_TOP_UNIVPLL_D4_D8 |
| #define CLK_TOPCKGEN_UNIVPLL_D5 CLK_TOP_UNIVPLL_D5 |
| #define CLK_TOPCKGEN_UNIVPLL_D5_D2 CLK_TOP_UNIVPLL_D5_D2 |
| #define CLK_TOPCKGEN_UNIVPLL_D5_D4 CLK_TOP_UNIVPLL_D5_D4 |
| #define CLK_TOPCKGEN_UNIVPLL_D6 CLK_TOP_UNIVPLL_D6 |
| #define CLK_TOPCKGEN_UNIVPLL_D6_D16 CLK_TOP_UNIVPLL_D6_D16 |
| #define CLK_TOPCKGEN_UNIVPLL_D6_D2 CLK_TOP_UNIVPLL_D6_D2 |
| #define CLK_TOPCKGEN_UNIVPLL_D6_D4 CLK_TOP_UNIVPLL_D6_D4 |
| #define CLK_TOPCKGEN_UNIVPLL_D6_D8 CLK_TOP_UNIVPLL_D6_D8 |
| #define CLK_TOPCKGEN_UNIVPLL_D7 CLK_TOP_UNIVPLL_D7 |
| #define CLK_TOPCKGEN_CLKRTC CLK_TOP_CLKRTC |
| #define CLK_TOPCKGEN_F_F26M_CK CLK_TOP_F26M |
| #define CLK_TOPCKGEN_F_F26M_CK_D2 CLK_TOP_F26M_CK_D2 |
| #define CLK_TOPCKGEN_OSC_D10 CLK_TOP_OSC_D10 |
| #define CLK_TOPCKGEN_OSC_D16 CLK_TOP_OSC_D16 |
| #define CLK_TOPCKGEN_OSC_D2 CLK_TOP_OSC_D2 |
| #define CLK_TOPCKGEN_OSC_D4 CLK_TOP_OSC_D4 |
| #define CLK_TOPCKGEN_OSC_D7 CLK_TOP_OSC_D7 |
| #define CLK_TOPCKGEN_OSC_D8 CLK_TOP_OSC_D8 |
| #define CLK_TOPCKGEN_TCK_26M_MX9_CK CLK_TOP_TCK_26M_MX9 |
| #define CLK_TOPCKGEN_ULPOSC_CK CLK_TOP_ULPOSC |
| #define CLK_TOPCKGEN_HF_FADSP_CK CLK_TOP_FADSP |
| #define CLK_TOPCKGEN_HF_FAUDIO_CK CLK_TOP_FAUDIO |
| #define CLK_TOPCKGEN_HF_FAUD_ENGEN1_CK CLK_TOP_FAUD_ENGEN1 |
| #define CLK_TOPCKGEN_HF_FAUD_ENGEN2_CK CLK_TOP_FAUD_ENGEN2 |
| #define CLK_TOPCKGEN_HF_FAUD_1_CK CLK_TOP_FAUD_1 |
| #define CLK_TOPCKGEN_HF_FAUDIO_H_CK CLK_TOP_FAUDIO_H |
| #define CLK_TOPCKGEN_HF_FDSP_CK CLK_TOP_FDSP |
| #define CLK_TOPCKGEN_HF_FDSP4_CK CLK_TOP_FDSP4 |
| #define CLK_TOPCKGEN_HF_FDSP7_CK CLK_TOP_FDSP7 |
| #define CLK_TOPCKGEN_HF_FIPU_IF_CK CLK_TOP_FIPU_IF |
| #define CLK_TOPCKGEN_HF_FCAM_CK CLK_TOP_FCAM |
| #define CLK_TOPCKGEN_F_FCAMTM_CK CLK_TOP_FCAMTM |
| #define CLK_TOPCKGEN_HF_FCCUSYS_CK CLK_TOP_FCCUSYS |
| #define CLK_TOPCKGEN_HF_FCCU_AHB_CK CLK_TOP_FCCU_AHB |
| #define CLK_TOPCKGEN_HF_FIMG1_CK CLK_TOP_FIMG1 |
| #define CLK_TOPCKGEN_HF_FDISP0_CK CLK_TOP_FDISP0 |
| #define CLK_TOPCKGEN_F_FI2C_CK CLK_TOP_FI2C |
| #define CLK_TOPCKGEN_HD_FAXI_CK CLK_TOP_FAXI |
| #define CLK_TOPCKGEN_HF_FDXCC_CK CLK_TOP_FDXCC |
| #define CLK_TOPCKGEN_HF_FMSDC_MACRO_CK CLK_TOP_FMSDC_MACRO |
| #define CLK_TOPCKGEN_HF_FDPMAIF_MAIN_CK CLK_TOP_FDPMAIF_MAIN |
| #define CLK_TOPCKGEN_HF_FMEM_SUB_CK CLK_TOP_FMEM_SUB |
| #define CLK_TOPCKGEN_HF_FIPE_CK CLK_TOP_FIPE |
| #define CLK_TOPCKGEN_HF_FMDP1_CK CLK_TOP_FMDP1 |
| #define CLK_TOPCKGEN_HF_FMDP0_CK CLK_TOP_FMDP0 |
| #define CLK_TOPCKGEN_HF_FMFG_REF_CK CLK_TOP_FMFG_REF |
| #define CLK_TOPCKGEN_F_FRTC_CK CLK_TOP_FRTC |
| #define CLK_TOPCKGEN_HF_FVDEC_CK CLK_TOP_FVDEC |
| #define CLK_TOPCKGEN_HF_FVENC_CK CLK_TOP_FVENC |
| #define CLK_TOPCKGEN_F_FUART_CK CLK_TOP_FUART |
| #define CLK_TOPCKGEN_F_FPERI_HD_AXI_CK CLK_TOP_FPERI_HD_AXI |
| #define CLK_TOPCKGEN_HF_FPWM_CK CLK_TOP_FPWM |
| #define CLK_TOPCKGEN_F_FDISP_PWM_CK CLK_TOP_FDISP_PWM |
| #define CLK_TOPCKGEN_HF_FSPI_CK CLK_TOP_FSPI |
| #define CLK_TOPCKGEN_HF_FSFLASH_CK CLK_TOP_FSFLASH |
| #define CLK_TOPCKGEN_F_FUSB_TOP_CK CLK_TOP_FUSB_TOP |
| #define CLK_TOPCKGEN_F_FSSUSB_XHCI_CK CLK_TOP_FSSUSB_XHCI |
| #define CLK_TOPCKGEN_F_FUSB_TOP_1P_CK CLK_TOP_FUSB_TOP_1P |
| #define CLK_TOPCKGEN_F_FSSUSB_XHCI_1P_CK CLK_TOP_FSSUSB_XHCI_1P |
| #define CLK_TOPCKGEN_HF_FMSDC30_1_CK CLK_TOP_FMSDC30_1 |
| #define CLK_TOPCKGEN_HF_FMSDC30_2_CK CLK_TOP_FMSDC30_2 |
| #define CLK_TOPCKGEN_HF_FTL_CK CLK_TOP_FTL |
| #define CLK_TOPCKGEN_PERI_HD_FAXI_SEL CLK_TOP_PERI_HD_FAXI_SEL |
| #define CLK_TOPCKGEN_UFS_HD_HAXI_SEL CLK_TOP_UFS_HD_HAXI_SEL |
| #define CLK_TOPCKGEN_BUS_AXIMEM_SEL CLK_TOP_BUS_AXIMEM_SEL |
| #define CLK_TOPCKGEN_AXI_SEL CLK_TOP_AXI_SEL |
| #define CLK_TOPCKGEN_DISP0_SEL CLK_TOP_DISP0_SEL |
| #define CLK_TOPCKGEN_DISP1_SEL CLK_TOP_DISP1_SEL |
| #define CLK_TOPCKGEN_MDP0_SEL CLK_TOP_MDP0_SEL |
| #define CLK_TOPCKGEN_MDP1_SEL CLK_TOP_MDP1_SEL |
| #define CLK_TOPCKGEN_MMINFRA_SEL CLK_TOP_MMINFRA_SEL |
| #define CLK_TOPCKGEN_MMUP_SEL CLK_TOP_MMUP_SEL |
| #define CLK_TOPCKGEN_DSP_SEL CLK_TOP_DSP_SEL |
| #define CLK_TOPCKGEN_DSP1_SEL CLK_TOP_DSP1_SEL |
| #define CLK_TOPCKGEN_DSP2_SEL CLK_TOP_DSP2_SEL |
| #define CLK_TOPCKGEN_DSP3_SEL CLK_TOP_DSP3_SEL |
| #define CLK_TOPCKGEN_DSP4_SEL CLK_TOP_DSP4_SEL |
| #define CLK_TOPCKGEN_DSP5_SEL CLK_TOP_DSP5_SEL |
| #define CLK_TOPCKGEN_DSP6_SEL CLK_TOP_DSP6_SEL |
| #define CLK_TOPCKGEN_DSP7_SEL CLK_TOP_DSP7_SEL |
| #define CLK_TOPCKGEN_IPU_IF_SEL CLK_TOP_IPU_IF_SEL |
| #define CLK_TOPCKGEN_MFG_REF_SEL CLK_TOP_MFG_REF_SEL |
| #define CLK_TOPCKGEN_MFGSC_REF_SEL CLK_TOP_MFGSC_REF_SEL |
| #define CLK_TOPCKGEN_CAMTG_SEL CLK_TOP_CAMTG_SEL |
| #define CLK_TOPCKGEN_CAMTG2_SEL CLK_TOP_CAMTG2_SEL |
| #define CLK_TOPCKGEN_CAMTG3_SEL CLK_TOP_CAMTG3_SEL |
| #define CLK_TOPCKGEN_CAMTG4_SEL CLK_TOP_CAMTG4_SEL |
| #define CLK_TOPCKGEN_CAMTG5_SEL CLK_TOP_CAMTG5_SEL |
| #define CLK_TOPCKGEN_CAMTG6_SEL CLK_TOP_CAMTG6_SEL |
| #define CLK_TOPCKGEN_CAMTG7_SEL CLK_TOP_CAMTG7_SEL |
| #define CLK_TOPCKGEN_CAMTG8_SEL CLK_TOP_CAMTG8_SEL |
| #define CLK_TOPCKGEN_UART_SEL CLK_TOP_UART_SEL |
| #define CLK_TOPCKGEN_SPI_SEL CLK_TOP_SPI_SEL |
| #define CLK_TOPCKGEN_MSDC50_0_HCLK_SEL CLK_TOP_MSDC50_0_HCLK_SEL |
| #define CLK_TOPCKGEN_MSDC_MACRO_SEL CLK_TOP_MSDC_MACRO_SEL |
| #define CLK_TOPCKGEN_MSDC30_1_SEL CLK_TOP_MSDC30_1_SEL |
| #define CLK_TOPCKGEN_MSDC30_2_SEL CLK_TOP_MSDC30_2_SEL |
| #define CLK_TOPCKGEN_AUDIO_SEL CLK_TOP_AUDIO_SEL |
| #define CLK_TOPCKGEN_AUD_INTBUS_SEL CLK_TOP_AUD_INTBUS_SEL |
| #define CLK_TOPCKGEN_PWRAP_ULPOSC_SEL CLK_TOP_PWRAP_ULPOSC_SEL |
| #define CLK_TOPCKGEN_ATB_SEL CLK_TOP_ATB_SEL |
| #define CLK_TOPCKGEN_DP_SEL CLK_TOP_DP_SEL |
| #define CLK_TOPCKGEN_DISP_PWM_SEL CLK_TOP_DISP_PWM_SEL |
| #define CLK_TOPCKGEN_USB_TOP_SEL CLK_TOP_USB_TOP_SEL |
| #define CLK_TOPCKGEN_SSUSB_XHCI_SEL CLK_TOP_SSUSB_XHCI_SEL |
| #define CLK_TOPCKGEN_USB_TOP_1P_SEL CLK_TOP_USB_TOP_1P_SEL |
| #define CLK_TOPCKGEN_SSUSB_XHCI_1P_SEL CLK_TOP_SSUSB_XHCI_1P_SEL |
| #define CLK_TOPCKGEN_I2C_SEL CLK_TOP_I2C_SEL |
| #define CLK_TOPCKGEN_SENINF_SEL CLK_TOP_SENINF_SEL |
| #define CLK_TOPCKGEN_SENINF1_SEL CLK_TOP_SENINF1_SEL |
| #define CLK_TOPCKGEN_SENINF2_SEL CLK_TOP_SENINF2_SEL |
| #define CLK_TOPCKGEN_SENINF3_SEL CLK_TOP_SENINF3_SEL |
| #define CLK_TOPCKGEN_SENINF4_SEL CLK_TOP_SENINF4_SEL |
| #define CLK_TOPCKGEN_SENINF5_SEL CLK_TOP_SENINF5_SEL |
| #define CLK_TOPCKGEN_DXCC_SEL CLK_TOP_DXCC_SEL |
| #define CLK_TOPCKGEN_AUD_ENGEN1_SEL CLK_TOP_AUD_ENGEN1_SEL |
| #define CLK_TOPCKGEN_AUD_ENGEN2_SEL CLK_TOP_AUD_ENGEN2_SEL |
| #define CLK_TOPCKGEN_AES_UFSFDE_SEL CLK_TOP_AES_UFSFDE_SEL |
| #define CLK_TOPCKGEN_UFS_SEL CLK_TOP_UFS_SEL |
| #define CLK_TOPCKGEN_UFS_MBIST_SEL CLK_TOP_UFS_MBIST_SEL |
| #define CLK_TOPCKGEN_PEXTP_MBIST_SEL CLK_TOP_PEXTP_MBIST_SEL |
| #define CLK_TOPCKGEN_AUD_1_SEL CLK_TOP_AUD_1_SEL |
| #define CLK_TOPCKGEN_VENC_SEL CLK_TOP_VENC_SEL |
| #define CLK_TOPCKGEN_AUD_2_SEL CLK_TOP_AUD_2_SEL |
| #define CLK_TOPCKGEN_ADSP_SEL CLK_TOP_ADSP_SEL |
| #define CLK_TOPCKGEN_DPMAIF_MAIN_SEL CLK_TOP_DPMAIF_MAIN_SEL |
| #define CLK_TOPCKGEN_VDEC_SEL CLK_TOP_VDEC_SEL |
| #define CLK_TOPCKGEN_PWM_SEL CLK_TOP_PWM_SEL |
| #define CLK_TOPCKGEN_AUDIO_H_SEL CLK_TOP_AUDIO_H_SEL |
| #define CLK_TOPCKGEN_MCUPM_SEL CLK_TOP_MCUPM_SEL |
| #define CLK_TOPCKGEN_SPMI_P_MST_SEL CLK_TOP_SPMI_P_MST_SEL |
| #define CLK_TOPCKGEN_SPMI_M_MST_SEL CLK_TOP_SPMI_M_MST_SEL |
| #define CLK_TOPCKGEN_TL_SEL CLK_TOP_TL_SEL |
| #define CLK_TOPCKGEN_MEM_SUB_SEL CLK_TOP_MEM_SUB_SEL |
| #define CLK_TOPCKGEN_PERI_HF_FMEM_SEL CLK_TOP_PERI_HF_FMEM_SEL |
| #define CLK_TOPCKGEN_UFS_HF_FMEM_SEL CLK_TOP_UFS_HF_FMEM_SEL |
| #define CLK_TOPCKGEN_AES_MSDCFDE_SEL CLK_TOP_AES_MSDCFDE_SEL |
| #define CLK_TOPCKGEN_EMI_N_SEL CLK_TOP_EMI_N_SEL |
| #define CLK_TOPCKGEN_EMI_S_SEL CLK_TOP_EMI_S_SEL |
| #define CLK_TOPCKGEN_DSI_OCC_SEL CLK_TOP_DSI_OCC_SEL |
| #define CLK_TOPCKGEN_DPTX_SEL CLK_TOP_DPTX_SEL |
| #define CLK_TOPCKGEN_CCU_AHB_SEL CLK_TOP_CCU_AHB_SEL |
| #define CLK_TOPCKGEN_AP2CONN_HOST_SEL CLK_TOP_AP2CONN_HOST_SEL |
| #define CLK_TOPCKGEN_IMG1_SEL CLK_TOP_IMG1_SEL |
| #define CLK_TOPCKGEN_IPE_SEL CLK_TOP_IPE_SEL |
| #define CLK_TOPCKGEN_CAM_SEL CLK_TOP_CAM_SEL |
| #define CLK_TOPCKGEN_CCUSYS_SEL CLK_TOP_CCUSYS_SEL |
| #define CLK_TOPCKGEN_CAMTM_SEL CLK_TOP_CAMTM_SEL |
| #define CLK_TOPCKGEN_SFLASH_SEL CLK_TOP_SFLASH_SEL |
| #define CLK_TOPCKGEN_MCU_ACP_SEL CLK_TOP_MCU_ACP_SEL |
| #define CLK_TOPCKGEN_TL_CK_SEL CLK_TOP_TL_CK_SEL |
| #define CLK_TOPCKGEN_MFG_SEL_0 CLK_TOP_MFG_SEL_0 |
| #define CLK_TOPCKGEN_MFG_SEL_1 CLK_TOP_MFG_SEL_1 |
| #define CLK_TOPCKGEN_APLL_I2S0_MCK_SEL CLK_TOP_APLL_I2S0_MCK_SEL |
| #define CLK_TOPCKGEN_APLL_I2S1_MCK_SEL CLK_TOP_APLL_I2S1_MCK_SEL |
| #define CLK_TOPCKGEN_APLL_I2S2_MCK_SEL CLK_TOP_APLL_I2S2_MCK_SEL |
| #define CLK_TOPCKGEN_APLL_I2S3_MCK_SEL CLK_TOP_APLL_I2S3_MCK_SEL |
| #define CLK_TOPCKGEN_APLL_I2S4_MCK_SEL CLK_TOP_APLL_I2S4_MCK_SEL |
| #define CLK_TOPCKGEN_APLL_I2S5_MCK_SEL CLK_TOP_APLL_I2S5_MCK_SEL |
| #define CLK_TOPCKGEN_APLL_I2S6_MCK_SEL CLK_TOP_APLL_I2S6_MCK_SEL |
| #define CLK_TOPCKGEN_APLL_I2S7_MCK_SEL CLK_TOP_APLL_I2S7_MCK_SEL |
| #define CLK_TOPCKGEN_APLL_I2S8_MCK_SEL CLK_TOP_APLL_I2S8_MCK_SEL |
| #define CLK_TOPCKGEN_APLL_I2S9_MCK_SEL CLK_TOP_APLL_I2S9_MCK_SEL |
| #define CLK_TOPCKGEN_APLL12_CK_DIV0 CLK_TOP_APLL12_CK_DIV0 |
| #define CLK_TOPCKGEN_APLL12_CK_DIV1 CLK_TOP_APLL12_CK_DIV1 |
| #define CLK_TOPCKGEN_APLL12_CK_DIV2 CLK_TOP_APLL12_CK_DIV2 |
| #define CLK_TOPCKGEN_APLL12_CK_DIV3 CLK_TOP_APLL12_CK_DIV3 |
| #define CLK_TOPCKGEN_APLL12_CK_DIV4 CLK_TOP_APLL12_CK_DIV4 |
| #define CLK_TOPCKGEN_APLL12_CK_DIV5 CLK_TOP_APLL12_CK_DIV5 |
| #define CLK_TOPCKGEN_APLL12_CK_DIV6 CLK_TOP_APLL12_CK_DIV6 |
| #define CLK_TOPCKGEN_APLL12_CK_DIV7 CLK_TOP_APLL12_CK_DIV7 |
| #define CLK_TOPCKGEN_APLL12_CK_DIV8 CLK_TOP_APLL12_CK_DIV8 |
| #define CLK_TOPCKGEN_APLL12_CK_DIV9 CLK_TOP_APLL12_CK_DIV9 |
| #define CLK_TOPCKGEN_APLL12_CK_DIVB CLK_TOP_APLL12_CK_DIVB |
| #define CLK_TOPCKGEN_PDN_MD_32K CLK_TOP_MD_32K |
| #define CLK_TOPCKGEN_PDN_MD_26M CLK_TOP_MD_26M |
| #define CLK_TOPCKGEN_PDN_CONN_32K CLK_TOP_CONN_32K |
| #define CLK_TOPCKGEN_PDN_CONN_26M CLK_TOP_CONN_26M |
| #define CLK_TOPCKGEN_APLL12_DIV0_PDN CLK_TOP_APLL12_DIV0_PDN |
| #define CLK_TOPCKGEN_APLL12_DIV1_PDN CLK_TOP_APLL12_DIV1_PDN |
| #define CLK_TOPCKGEN_APLL12_DIV2_PDN CLK_TOP_APLL12_DIV2_PDN |
| #define CLK_TOPCKGEN_APLL12_DIV3_PDN CLK_TOP_APLL12_DIV3_PDN |
| #define CLK_TOPCKGEN_APLL12_DIV4_PDN CLK_TOP_APLL12_DIV4_PDN |
| #define CLK_TOPCKGEN_APLL12_DIVB_PDN CLK_TOP_APLL12_DIVB_PDN |
| #define CLK_TOPCKGEN_APLL12_DIV5_PDN CLK_TOP_APLL12_DIV5_PDN |
| #define CLK_TOPCKGEN_APLL12_DIV6_PDN CLK_TOP_APLL12_DIV6_PDN |
| #define CLK_TOPCKGEN_APLL12_DIV7_PDN CLK_TOP_APLL12_DIV7_PDN |
| #define CLK_TOPCKGEN_APLL12_DIV8_PDN CLK_TOP_APLL12_DIV8_PDN |
| #define CLK_TOPCKGEN_APLL12_DIV9_PDN CLK_TOP_APLL12_DIV9_PDN |
| #define CLK_TOPCKGEN_NR_CLK CLK_TOP_NR_CLK |
| #define CLK_ADSP_UART_BCLK_CG CLK_ADSP_UART_BCLK |
| #define CLK_AFE_PDN_AFE CLK_AFE_AFE |
| #define CLK_AFE_PDN_22M CLK_AFE_22M |
| #define CLK_AFE_PDN_24M CLK_AFE_24M |
| #define CLK_AFE_PDN_APLL2_TUNER CLK_AFE_APLL2_TUNER |
| #define CLK_AFE_PDN_APLL_TUNER CLK_AFE_APLL_TUNER |
| #define CLK_AFE_PDN_TDM_CK CLK_AFE_TDM |
| #define CLK_AFE_PDN_ADC CLK_AFE_ADC |
| #define CLK_AFE_PDN_DAC CLK_AFE_DAC |
| #define CLK_AFE_PDN_DAC_PREDIS CLK_AFE_DAC_PREDIS |
| #define CLK_AFE_PDN_TML CLK_AFE_TML |
| #define CLK_AFE_PDN_NLE CLK_AFE_NLE |
| #define CLK_AFE_PDN_GENERAL3_ASRC CLK_AFE_GENERAL3_ASRC |
| #define CLK_AFE_PDN_CONNSYS_I2S_ASRC CLK_AFE_CONNSYS_I2S_ASRC |
| #define CLK_AFE_PDN_GENERAL1_ASRC CLK_AFE_GENERAL1_ASRC |
| #define CLK_AFE_PDN_GENERAL2_ASRC CLK_AFE_GENERAL2_ASRC |
| #define CLK_AFE_PDN_DAC_HIRES CLK_AFE_DAC_HIRES |
| #define CLK_AFE_PDN_ADC_HIRES CLK_AFE_ADC_HIRES |
| #define CLK_AFE_PDN_ADC_HIRES_TML CLK_AFE_ADC_HIRES_TML |
| #define CLK_AFE_PDN_ADDA6_ADC CLK_AFE_ADDA6_ADC |
| #define CLK_AFE_PDN_ADDA6_ADC_HIRES CLK_AFE_ADDA6_ADC_HIRES |
| #define CLK_AFE_PDN_ADDA7_ADC CLK_AFE_ADDA7_ADC |
| #define CLK_AFE_PDN_ADDA7_ADC_HIRES CLK_AFE_ADDA7_ADC_HIRES |
| #define CLK_AFE_PDN_3RD_DAC CLK_AFE_3RD_DAC |
| #define CLK_AFE_PDN_3RD_DAC_PREDIS CLK_AFE_3RD_DAC_PREDIS |
| #define CLK_AFE_PDN_3RD_DAC_TML CLK_AFE_3RD_DAC_TML |
| #define CLK_AFE_PDN_3RD_DAC_HIRES CLK_AFE_3RD_DAC_HIRES |
| #define CLK_AFE_I2S5_BCLK_SW_CG CLK_AFE_I2S5_BCLK |
| #define CLK_AFE_I2S6_BCLK_SW_CG CLK_AFE_I2S6_BCLK |
| #define CLK_AFE_I2S7_BCLK_SW_CG CLK_AFE_I2S7_BCLK |
| #define CLK_AFE_I2S8_BCLK_SW_CG CLK_AFE_I2S8_BCLK |
| #define CLK_AFE_I2S9_BCLK_SW_CG CLK_AFE_I2S9_BCLK |
| #define CLK_AFE_ETDM_IN0_BCLK_SW_CG CLK_AFE_ETDM_IN0_BCLK |
| #define CLK_AFE_ETDM_OUT0_BCLK_SW_CG CLK_AFE_ETDM_OUT0_BCLK |
| #define CLK_AFE_I2S1_BCLK_SW_CG CLK_AFE_I2S1_BCLK |
| #define CLK_AFE_I2S2_BCLK_SW_CG CLK_AFE_I2S2_BCLK |
| #define CLK_AFE_I2S3_BCLK_SW_CG CLK_AFE_I2S3_BCLK |
| #define CLK_AFE_I2S4_BCLK_SW_CG CLK_AFE_I2S4_BCLK |
| #define CLK_AFE_ETDM_IN1_BCLK_SW_CG CLK_AFE_ETDM_IN1_BCLK |
| #define CLK_AFE_ETDM_OUT1_BCLK_SW_CG CLK_AFE_ETDM_OUT1_BCLK |
| #define CLK_CAMSYS_MRAW_LARBX_CGPDN CLK_CAMSYS_MRAW_LARBX |
| #define CLK_CAMSYS_MRAW_CAMTG_CGPDN CLK_CAMSYS_MRAW_CAMTG |
| #define CLK_CAMSYS_MRAW_MRAW0_CGPDN CLK_CAMSYS_MRAW_MRAW0 |
| #define CLK_CAMSYS_MRAW_MRAW1_CGPDN CLK_CAMSYS_MRAW_MRAW1 |
| #define CLK_CAMSYS_MRAW_MRAW2_CGPDN CLK_CAMSYS_MRAW_MRAW2 |
| #define CLK_CAMSYS_MRAW_MRAW3_CGPDN CLK_CAMSYS_MRAW_MRAW3 |
| #define CLK_CAMSYS_MRAW_PDA0_CGPDN CLK_CAMSYS_MRAW_PDA0 |
| #define CLK_CAMSYS_MRAW_PDA1_CGPDN CLK_CAMSYS_MRAW_PDA1 |
| #define CLK_CAMSYS_RAWA_LARBX_CGPDN CLK_CAM_RA_LARBX |
| #define CLK_CAMSYS_RAWA_CAM_CGPDN CLK_CAM_RA_CAM |
| #define CLK_CAMSYS_RAWA_CAMTG_CGPDN CLK_CAM_RA_CAMTG |
| #define CLK_CAMSYS_RAWB_LARBX_CGPDN CLK_CAM_RB_LARBX |
| #define CLK_CAMSYS_RAWB_CAM_CGPDN CLK_CAM_RB_CAM |
| #define CLK_CAMSYS_RAWB_CAMTG_CGPDN CLK_CAM_RB_CAMTG |
| #define CLK_CAMSYS_RAWC_LARBX_CGPDN CLK_CAM_RC_LARBX |
| #define CLK_CAMSYS_RAWC_CAM_CGPDN CLK_CAM_RC_CAM |
| #define CLK_CAMSYS_RAWC_CAMTG_CGPDN CLK_CAM_RC_CAMTG |
| #define CLK_CAMSYS_YUVA_LARBX_CGPDN CLK_CAMSYS_YUVA_LARBX |
| #define CLK_CAMSYS_YUVA_CAM_CGPDN CLK_CAMSYS_YUVA_CAM |
| #define CLK_CAMSYS_YUVA_CAMTG_CGPDN CLK_CAMSYS_YUVA_CAMTG |
| #define CLK_CAMSYS_YUVB_LARBX_CGPDN CLK_CAMSYS_YUVB_LARBX |
| #define CLK_CAMSYS_YUVB_CAM_CGPDN CLK_CAMSYS_YUVB_CAM |
| #define CLK_CAMSYS_YUVB_CAMTG_CGPDN CLK_CAMSYS_YUVB_CAMTG |
| #define CLK_CAMSYS_YUVC_LARBX_CGPDN CLK_CAMSYS_YUVC_LARBX |
| #define CLK_CAMSYS_YUVC_CAM_CGPDN CLK_CAMSYS_YUVC_CAM |
| #define CLK_CAMSYS_YUVC_CAMTG_CGPDN CLK_CAMSYS_YUVC_CAMTG |
| #define CLK_CAM_MAIN_R1A_CAMTG_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_CAMTG_CG_CON |
| #define CLK_CAM_MAIN_R1A_SENINF_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_SENINF_CG_CON |
| #define CLK_CAM_MAIN_R1A_GCAMSVA_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_GCAMSVA_CG_CON |
| #define CLK_CAM_MAIN_R1A_GCAMSVB_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_GCAMSVB_CG_CON |
| #define CLK_CAM_MAIN_R1A_GCAMSVC_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_GCAMSVC_CG_CON |
| #define CLK_CAM_MAIN_R1A_GCAMSVD_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_GCAMSVD_CG_CON |
| #define CLK_CAM_MAIN_R1A_GCAMSVE_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_GCAMSVE_CG_CON |
| #define CLK_CAM_MAIN_R1A_GCAMSVF_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_GCAMSVF_CG_CON |
| #define CLK_CAM_MAIN_R1A_GCAMSVG_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_GCAMSVG_CG_CON |
| #define CLK_CAM_MAIN_R1A_GCAMSVH_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_GCAMSVH_CG_CON |
| #define CLK_CAM_MAIN_R1A_CAMSVI_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_GCAMSVI_CG_CON |
| #define CLK_CAM_MAIN_R1A_GCAMSVJ_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_GCAMSVJ_CG_CON |
| #define CLK_CAM_MAIN_R1A_CAMSV_TOP_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_CAMSV_TOP_CG_CON |
| #define CLK_CAM_MAIN_R1A_CAMSV_CQ_A_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_CAMSV_CQ_A_CG_CON |
| #define CLK_CAM_MAIN_R1A_CAMSV_CQ_B_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_CAMSV_CQ_B_CG_CON |
| #define CLK_CAM_MAIN_R1A_CAMSV_CQ_C_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_CAMSV_CQ_C_CG_CON |
| #define CLK_CAM_MAIN_R1A_ADL_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_ADL_CG_CON |
| #define CLK_CAM_MAIN_R1A_ASG_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_ASG_CG_CON |
| #define CLK_CAM_MAIN_R1A_PDA0_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_PDA0_CG_CON |
| #define CLK_CAM_MAIN_R1A_PDA1_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_PDA1_CG_CON |
| #define CLK_CAM_MAIN_R1A_PDA2_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_PDA2_CG_CON |
| #define CLK_CAM_MAIN_R1A_FAKE_ENG_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_FAKE_ENG_CG_CON |
| #define CLK_CAM_MAIN_R1A_LARB13_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_LARB13_CG_CON |
| #define CLK_CAM_MAIN_R1A_LARB14_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_LARB14_CG_CON |
| #define CLK_CAM_MAIN_R1A_CAM_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_CAM_CG_CON |
| #define CLK_CAM_MAIN_R1A_CAM_SUBA_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_CAM_SUBA_CG_CON |
| #define CLK_CAM_MAIN_R1A_CAM_SUBB_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_CAM_SUBB_CG_CON |
| #define CLK_CAM_MAIN_R1A_CAM_SUBC_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_CAM_SUBC_CG_CON |
| #define CLK_CAM_MAIN_R1A_CAM_MRAW_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_CAM_MRAW_CG_CON |
| #define CLK_CAM_MAIN_R1A_CAM2MM0_GALS_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_CAM2MM0_GALS_CG_CON |
| #define CLK_CAM_MAIN_R1A_CAM2MM1_GALS_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_CAM2MM1_GALS_CG_CON |
| #define CLK_CAM_MAIN_R1A_CAM2SYS_GALS_CG_CON CLK_CAM_MAIN_R1A_CAM_MAIN_CAM2SYS_GALS_CG_CON |
| #define CLK_CCU_MAIN_LARB19_CGPDN CLK_CCU_MAIN_LARB19 |
| #define CLK_CCU_MAIN_AHB_CGPDN CLK_CCU_MAIN_AHB |
| #define CLK_CCU_MAIN_CCUSYS_CCU0_CGPDN CLK_CCU_MAIN_CCUSYS_CCU0 |
| #define CLK_CCU_MAIN_CCUSYS_CCU1_CGPDN CLK_CCU_MAIN_CCUSYS_CCU1 |
| #define CLK_DIP_NR_DIP1_LARB15_CGPDN CLK_DIP_NR_DIP1_LARB15 |
| #define CLK_DIP_TOP_DIP1_LARB10_CGPDN CLK_DIP_TOP_DIP1_LARB10 |
| #define CLK_DIP_TOP_DIP1_DIP_TOP_CGPDN CLK_DIP_TOP_DIP1_DIP_TOP |
| #define CLK_IMGSYS_MAIN_LARB9_CGPDN CLK_IMGSYS_MAIN_LARB9 |
| #define CLK_IMGSYS_MAIN_TRAW0_CGPDN CLK_IMGSYS_MAIN_TRAW0 |
| #define CLK_IMGSYS_MAIN_TRAW1_CGPDN CLK_IMGSYS_MAIN_TRAW1 |
| #define CLK_IMGSYS_MAIN_VCORE_GALS_CGPDN CLK_IMGSYS_MAIN_VCORE_GALS |
| #define CLK_IMGSYS_MAIN_DIP0_CGPDN CLK_IMGSYS_MAIN_DIP0 |
| #define CLK_IMGSYS_MAIN_WPE0_CGPDN CLK_IMGSYS_MAIN_WPE0 |
| #define CLK_IMGSYS_MAIN_IPE_CGPDN CLK_IMGSYS_MAIN_IPE |
| #define CLK_IMGSYS_MAIN_WPE1_CGPDN CLK_IMGSYS_MAIN_WPE1 |
| #define CLK_IMGSYS_MAIN_WPE2_CGPDN CLK_IMGSYS_MAIN_WPE2 |
| #define CLK_IMGSYS_MAIN_ADL_LARB_CGPDN CLK_IMGSYS_MAIN_ADL_LARB |
| #define CLK_IMGSYS_MAIN_ADL_TOP0_CGPDN CLK_IMGSYS_MAIN_ADL_TOP0 |
| #define CLK_IMGSYS_MAIN_ADL_TOP1_CGPDN CLK_IMGSYS_MAIN_ADL_TOP1 |
| #define CLK_IMGSYS_MAIN_GALS_CGPDN CLK_IMGSYS_MAIN_GALS |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C10_CG CLK_IMP_IIC_WRAP_AP_CLOCK_I2C10 |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C11_CG CLK_IMP_IIC_WRAP_AP_CLOCK_I2C11 |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C12_CG CLK_IMP_IIC_WRAP_AP_CLOCK_I2C12 |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C13_CG CLK_IMP_IIC_WRAP_AP_CLOCK_I2C13 |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1_CG CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1 |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2_CG CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2 |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3_CG CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3 |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4_CG CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4 |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7_CG CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7 |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8_CG CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8 |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9_CG CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9 |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0_CG CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0 |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5_CG CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5 |
| #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6_CG CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6 |
| #define CLK_INFRACFG_AO_CGEN_PRE_INFRA_BUS_HRE_SYS_CLK CLK_IFR_AO_CGEN_PRE_INFRA_BUS_HRE_SYS_CLK |
| #define CLK_INFRACFG_AO_INFRA_DCM_RG_FORCE_CLKOFF CLK_IFR_AO_INFRA_DCM_RG_FORCE |
| #define CLK_INFRACFG_AO_THERM_CG CLK_IFR_AO_THERM |
| #define CLK_INFRACFG_AO_CQ_DMA_FPC CLK_IFR_AO_CQ_DMA_FPC |
| #define CLK_INFRACFG_AO_TRNG_CG CLK_IFR_AO_TRNG |
| #define CLK_INFRACFG_AO_CPUM_CG CLK_IFR_AO_CPUM |
| #define CLK_INFRACFG_AO_CCIF1_AP_CG CLK_IFR_AO_CCIF1_AP |
| #define CLK_INFRACFG_AO_CCIF1_MD_CG CLK_IFR_AO_CCIF1_MD |
| #define CLK_INFRACFG_AO_CCIF_AP_CG CLK_IFR_AO_CCIF_AP |
| #define CLK_INFRACFG_AO_DEBUGSYS_CG CLK_IFR_AO_DEBUGSYS |
| #define CLK_INFRACFG_AO_CCIF_MD_CG CLK_IFR_AO_CCIF_MD |
| #define CLK_INFRACFG_AO_DXCC_SEC_CORE_CG CLK_IFR_AO_DXCC_SEC_CORE |
| #define CLK_INFRACFG_AO_DXCC_AO_CG CLK_IFR_AO_DXCC_AO |
| #define CLK_INFRACFG_AO_DBG_TRACE_CG CLK_IFR_AO_DBG_TRACE |
| #define CLK_INFRACFG_AO_CLDMA_BCLK_CK CLK_IFR_AO_CLDMA_BCLK |
| #define CLK_INFRACFG_AO_CQ_DMA_CG CLK_IFR_AO_CQ_DMA |
| #define CLK_INFRACFG_AO_CCIF5_AP_CG CLK_IFR_AO_CCIF5_AP |
| #define CLK_INFRACFG_AO_CCIF5_MD_CG CLK_IFR_AO_CCIF5_MD |
| #define CLK_INFRACFG_AO_CCIF2_AP_CG CLK_IFR_AO_CCIF2_AP |
| #define CLK_INFRACFG_AO_CCIF2_MD_CG CLK_IFR_AO_CCIF2_MD |
| #define CLK_INFRACFG_AO_CCIF3_AP_CG CLK_IFR_AO_CCIF3_AP |
| #define CLK_INFRACFG_AO_CCIF3_MD_CG CLK_IFR_AO_CCIF3_MD |
| #define CLK_INFRACFG_AO_FBIST2FPC_CG CLK_IFR_AO_FBIST2FPC |
| #define CLK_INFRACFG_AO_DEVICE_APC_SYNC_CG CLK_IFR_AO_DEVICE_APC_SYNC |
| #define CLK_INFRACFG_AO_DPMAIF_MAIN_CG CLK_IFR_AO_DPMAIF_MAIN |
| #define CLK_INFRACFG_AO_CCIF4_AP_CG CLK_IFR_AO_CCIF4_AP |
| #define CLK_INFRACFG_AO_CCIF4_MD_CG CLK_IFR_AO_CCIF4_MD |
| #define CLK_INFRACFG_AO_RG_MMW_DPMAIF_F26M_CK_CG CLK_IFR_AO_RG_MMW_DPMAIF_F26M_CK |
| #define CLK_INFRACFG_AO_RG_HF_FMEM_SUB_CK_CG CLK_IFR_AO_RG_HF_FMEM_SUB_CK |
| #define CLK_IPESYS_DPE_CGPDN CLK_IPESYS_DPE |
| #define CLK_IPESYS_FDVT_CGPDN CLK_IPESYS_FDVT |
| #define CLK_IPESYS_ME_CGPDN CLK_IPESYS_ME |
| #define CLK_IPESYS_IPESYS_TOP_CGPDN CLK_IPESYS_IPESYS_TOP |
| #define CLK_IPESYS_SMI_LARB12_CGPDN CLK_IPESYS_SMI_LARB12 |
| #define CLK_IPESYS_FDVT1_CGPDN CLK_IPESYS_FDVT1 |
| #define CLK_MDPSYS1_CONFIG_MDP_SMI0 CLK_MDPSYS1_CONFIG_SMI0 |
| #define CLK_MDPSYS1_CONFIG_MDP_HRE_TOP_MDPSYS CLK_MDPSYS1_CONFIG_HRE_TOP_MDPSYS |
| #define CLK_MDPSYS_CONFIG_MDP_MUTEX0 CLK_MDP_MDP_MUTEX0 |
| #define CLK_MDPSYS_CONFIG_APB_BUS CLK_MDP_APB_BUS |
| #define CLK_MDPSYS_CONFIG_MDP_SMI0 CLK_MDP_SMI0 |
| #define CLK_MDPSYS_CONFIG_MDP_RDMA0 CLK_MDP_MDP_RDMA0 |
| #define CLK_MDPSYS_CONFIG_MDP_FG0 CLK_MDP_MDP_FG0 |
| #define CLK_MDPSYS_CONFIG_MDP_HDR0 CLK_MDP_MDP_HDR0 |
| #define CLK_MDPSYS_CONFIG_MDP_AAL0 CLK_MDP_MDP_AAL0 |
| #define CLK_MDPSYS_CONFIG_MDP_RSZ0 CLK_MDP_MDP_RSZ0 |
| #define CLK_MDPSYS_CONFIG_MDP_TDSHP0 CLK_MDP_MDP_TDSHP0 |
| #define CLK_MDPSYS_CONFIG_MDP_COLOR0 CLK_MDP_MDP_COLOR0 |
| #define CLK_MDPSYS_CONFIG_MDP_WROT0 CLK_MDP_MDP_WROT0 |
| #define CLK_MDPSYS_CONFIG_MDP_FAKE_ENG0 CLK_MDP_MDP_FAKE_ENG0 |
| #define CLK_MDPSYS_CONFIG_IMG_DL_RELAY0 CLK_MDP_IMG_DL_RELAY0 |
| #define CLK_MDPSYS_CONFIG_IMG_DL_RELAY1 CLK_MDP_IMG_DL_RELAY1 |
| #define CLK_MDPSYS_CONFIG_MDP_RDMA1 CLK_MDP_MDP_RDMA1 |
| #define CLK_MDPSYS_CONFIG_MDP_FG1 CLK_MDP_MDP_FG1 |
| #define CLK_MDPSYS_CONFIG_MDP_HDR1 CLK_MDP_MDP_HDR1 |
| #define CLK_MDPSYS_CONFIG_MDP_AAL1 CLK_MDP_MDP_AAL1 |
| #define CLK_MDPSYS_CONFIG_MDP_RSZ1 CLK_MDP_MDP_RSZ1 |
| #define CLK_MDPSYS_CONFIG_MDP_TDSHP1 CLK_MDP_MDP_TDSHP1 |
| #define CLK_MDPSYS_CONFIG_MDP_COLOR1 CLK_MDP_MDP_COLOR1 |
| #define CLK_MDPSYS_CONFIG_MDP_WROT1 CLK_MDP_MDP_WROT1 |
| #define CLK_MDPSYS_CONFIG_MDP_RSZ2 CLK_MDP_MDP_RSZ2 |
| #define CLK_MDPSYS_CONFIG_MDP_WROT2 CLK_MDP_MDP_WROT2 |
| #define CLK_MDPSYS_CONFIG_MDP_DLO_ASYNC0 CLK_MDP_MDP_DLO_ASYNC0 |
| #define CLK_MDPSYS_CONFIG_MDP_RSZ3 CLK_MDP_MDP_RSZ3 |
| #define CLK_MDPSYS_CONFIG_MDP_WROT3 CLK_MDP_MDP_WROT3 |
| #define CLK_MDPSYS_CONFIG_MDP_DLO_ASYNC1 CLK_MDP_MDP_DLO_ASYNC1 |
| #define CLK_MDPSYS_CONFIG_MDP_HRE_TOP_MDPSYS CLK_MDP_HRE_TOP_MDPSYS |
| #define CLK_PERICFG_AO_PERI_UART0_CG CLK_PERI_AO_PERI_UART0 |
| #define CLK_PERICFG_AO_PERI_UART1_CG CLK_PERI_AO_PERI_UART1 |
| #define CLK_PERICFG_AO_PERI_UART2_CG CLK_PERI_AO_PERI_UART2 |
| #define CLK_PERICFG_AO_PERI_UART3_CG CLK_PERI_AO_PERI_UART3 |
| #define CLK_PERICFG_AO_PERI_PWM_HCLK_CG CLK_PERI_AO_PERI_PWM_HCLK |
| #define CLK_PERICFG_AO_PERI_PWM_BCLK_CG CLK_PERI_AO_PERI_PWM_BCLK |
| #define CLK_PERICFG_AO_PERI_PWM_FBCLK1_CG CLK_PERI_AO_PERI_PWM_FBCLK1 |
| #define CLK_PERICFG_AO_PERI_PWM_FBCLK2_CG CLK_PERI_AO_PERI_PWM_FBCLK2 |
| #define CLK_PERICFG_AO_PERI_PWM_FBCLK3_CG CLK_PERI_AO_PERI_PWM_FBCLK3 |
| #define CLK_PERICFG_AO_PERI_PWM_FBCLK4_CG CLK_PERI_AO_PERI_PWM_FBCLK4 |
| #define CLK_PERICFG_AO_PERI_BTIF_BCLK_CG CLK_PERI_AO_PERI_BTIF_BCLK |
| #define CLK_PERICFG_AO_PERI_DISP_PWM0_CG CLK_PERI_AO_PERI_DISP_PWM0 |
| #define CLK_PERICFG_AO_PERI_DISP_PWM1_CG CLK_PERI_AO_PERI_DISP_PWM1 |
| #define CLK_PERICFG_AO_PERI_SPI0_BCLK_CG CLK_PERI_AO_PERI_SPI0_BCLK |
| #define CLK_PERICFG_AO_PERI_SPI1_BCLK_CG CLK_PERI_AO_PERI_SPI1_BCLK |
| #define CLK_PERICFG_AO_PERI_SPI2_BCLK_CG CLK_PERI_AO_PERI_SPI2_BCLK |
| #define CLK_PERICFG_AO_PERI_SPI3_BCLK_CG CLK_PERI_AO_PERI_SPI3_BCLK |
| #define CLK_PERICFG_AO_PERI_SPI4_BCLK_CG CLK_PERI_AO_PERI_SPI4_BCLK |
| #define CLK_PERICFG_AO_PERI_SPI5_BCLK_CG CLK_PERI_AO_PERI_SPI5_BCLK |
| #define CLK_PERICFG_AO_PERI_SPI6_BCLK_CG CLK_PERI_AO_PERI_SPI6_BCLK |
| #define CLK_PERICFG_AO_PERI_SPI7_BCLK_CG CLK_PERI_AO_PERI_SPI7_BCLK |
| #define CLK_PERICFG_AO_PERI_SPI0_HCLK_CG CLK_PERI_AO_PERI_SPI0_HCLK |
| #define CLK_PERICFG_AO_PERI_SPI1_HCLK_CG CLK_PERI_AO_PERI_SPI1_HCLK |
| #define CLK_PERICFG_AO_PERI_SPI2_HCLK_CG CLK_PERI_AO_PERI_SPI2_HCLK |
| #define CLK_PERICFG_AO_PERI_SPI3_HCLK_CG CLK_PERI_AO_PERI_SPI3_HCLK |
| #define CLK_PERICFG_AO_PERI_SPI4_HCLK_CG CLK_PERI_AO_PERI_SPI4_HCLK |
| #define CLK_PERICFG_AO_PERI_SPI5_HCLK_CG CLK_PERI_AO_PERI_SPI5_HCLK |
| #define CLK_PERICFG_AO_PERI_SPI6_HCLK_CG CLK_PERI_AO_PERI_SPI6_HCLK |
| #define CLK_PERICFG_AO_PERI_SPI7_HCLK_CG CLK_PERI_AO_PERI_SPI7_HCLK |
| #define CLK_PERICFG_AO_PERI_FSFLASH_CG CLK_PERI_AO_PERI_FSFLASH |
| #define CLK_PERICFG_AO_PERI_FSFLASH_FCLK_CG CLK_PERI_AO_PERI_FSFLASH_FCLK |
| #define CLK_PERICFG_AO_PERI_FSFLASH_HCLK_CG CLK_PERI_AO_PERI_FSFLASH_HCLK |
| #define CLK_PERICFG_AO_PERI_IIC_CG CLK_PERI_AO_PERI_IIC |
| #define CLK_PERICFG_AO_PERI_APDMA_CG CLK_PERI_AO_PERI_APDMA |
| #define CLK_PERICFG_AO_PERI_SSUSB_PCLK_CG CLK_PERI_AO_PERI_SSUSB_PCLK |
| #define CLK_PERICFG_AO_PERI_SSUSB_REF_CG CLK_PERI_AO_PERI_SSUSB_REF |
| #define CLK_PERICFG_AO_PERI_SSUSB_FRMCNT_CG CLK_PERI_AO_PERI_SSUSB_FRMCNT |
| #define CLK_PERICFG_AO_PERI_SSUSB_PHY_CG CLK_PERI_AO_PERI_SSUSB_PHY |
| #define CLK_PERICFG_AO_PERI_SSUSB_SYS_CG CLK_PERI_AO_PERI_SSUSB_SYS |
| #define CLK_PERICFG_AO_PERI_SSUSB_XHCI_CG CLK_PERI_AO_PERI_SSUSB_XHCI |
| #define CLK_PERICFG_AO_PERI_SSUSB_DMA_BUS_CG CLK_PERI_AO_PERI_SSUSB_DMA_BUS |
| #define CLK_PERICFG_AO_PERI_SSUSB_MCU_BUS_CG CLK_PERI_AO_PERI_SSUSB_MCU_BUS |
| #define CLK_PERICFG_AO_PERI_SSUSB1_REF_CG CLK_PERI_AO_PERI_SSUSB1_REF |
| #define CLK_PERICFG_AO_PERI_SSUSB1_FRMCNT_CG CLK_PERI_AO_PERI_SSUSB1_FRMCNT |
| #define CLK_PERICFG_AO_PERI_SSUSB1_PHY_CG CLK_PERI_AO_PERI_SSUSB1_PHY |
| #define CLK_PERICFG_AO_PERI_SSUSB1_SYS_CG CLK_PERI_AO_PERI_SSUSB1_SYS |
| #define CLK_PERICFG_AO_PERI_SSUSB1_XHCI_CG CLK_PERI_AO_PERI_SSUSB1_XHCI |
| #define CLK_PERICFG_AO_PERI_SSUSB1_DMA_BUS_CG CLK_PERI_AO_PERI_SSUSB1_DMA_BUS |
| #define CLK_PERICFG_AO_PERI_SSUSB1_MCU_BUS_CG CLK_PERI_AO_PERI_SSUSB1_MCU_BUS |
| #define CLK_PERICFG_AO_PERI_MSDC1_S_CG CLK_PERI_AO_PERI_MSDC1_S |
| #define CLK_PERICFG_AO_PERI_MSDC1_H_CG CLK_PERI_AO_PERI_MSDC1_H |
| #define CLK_PERICFG_AO_PERI_MSDC2_S_CG CLK_PERI_AO_PERI_MSDC2_S |
| #define CLK_PERICFG_AO_PERI_MSDC2_H_CG CLK_PERI_AO_PERI_MSDC2_H |
| #define CLK_PERICFG_AO_PERI_PCIE0_26M_CG CLK_PERI_AO_PERI_PCIE0_26M |
| #define CLK_PERICFG_AO_PERI_PCIE0_250M_CG CLK_PERI_AO_PERI_PCIE0_250M |
| #define CLK_PERICFG_AO_PERI_PCIE0_GFMUX_CG CLK_PERI_AO_PERI_PCIE0_GFMUX |
| #define CLK_PERICFG_AO_PERI_PCIE1_26M_CG CLK_PERI_AO_PERI_PCIE1_26M |
| #define CLK_PERICFG_AO_PERI_PCIE1_250M_CG CLK_PERI_AO_PERI_PCIE1_250M |
| #define CLK_PERICFG_AO_PERI_PCIE1_GFMUX_CG CLK_PERI_AO_PERI_PCIE1_GFMUX |
| #define CLK_PERICFG_AO_PERI_PCIE0_MEM_CG CLK_PERI_AO_PERI_PCIE0_MEM |
| #define CLK_PERICFG_AO_PERI_PCIE1_MEM_CLR CLK_PERI_AO_PERI_PCIE1_MEM_CLR |
| #define CLK_PERICFG_AO_PERI_PCIE0_PCIE1_HCLK_CLR CLK_PERI_AO_PERI_PCIE0_PCIE1_HCLK_CLR |
| #define CLK_VDEC_GCON_BASE_VDEC_CKEN CLK_VDE2_BASE_VDEC_CKEN |
| #define CLK_VDEC_GCON_BASE_VDEC_ACTIVE CLK_VDE2_BASE_VDEC_ACTIVE |
| #define CLK_VDEC_GCON_BASE_VDEC_CKEN_ENG CLK_VDE2_BASE_VDEC_CKEN_ENG |
| #define CLK_VDEC_GCON_BASE_LAT_CKEN CLK_VDE2_BASE_LAT_CKEN |
| #define CLK_VDEC_GCON_BASE_LAT_ACTIVE CLK_VDE2_BASE_LAT_ACTIVE |
| #define CLK_VDEC_GCON_BASE_LAT_CKEN_ENG CLK_VDE2_BASE_LAT_CKEN_ENG |
| #define CLK_VDEC_GCON_BASE_LARB1_CKEN CLK_VDE2_BASE_LARB1_CKEN |
| #define CLK_VDEC_SOC_GCON_BASE_VDEC_CKEN CLK_VDE1_BASE_VDEC_CKEN |
| #define CLK_VDEC_SOC_GCON_BASE_VDEC_ACTIVE CLK_VDE1_BASE_VDEC_ACTIVE |
| #define CLK_VDEC_SOC_GCON_BASE_VDEC_CKEN_ENG CLK_VDE1_BASE_VDEC_CKEN_ENG |
| #define CLK_VDEC_SOC_GCON_BASE_LAT_CKEN CLK_VDE1_BASE_LAT_CKEN |
| #define CLK_VDEC_SOC_GCON_BASE_LAT_ACTIVE CLK_VDE1_BASE_LAT_ACTIVE |
| #define CLK_VDEC_SOC_GCON_BASE_LAT_CKEN_ENG CLK_VDE1_BASE_LAT_CKEN_ENG |
| #define CLK_VDEC_SOC_GCON_BASE_MINI_MDP_CKEN CLK_VDE1_BASE_MINI_MDP_CKEN |
| #define CLK_VDEC_SOC_GCON_BASE_LARB1_CKEN CLK_VDE1_BASE_LARB1_CKEN |
| |
| #define CLK_VENC_GCON_CKE1_VENC CLK_VEN1_CKE1_VENC |
| #define CLK_VENC_GCON_CKE2_JPGENC CLK_VEN1_CKE2_JPGENC |
| #define CLK_VENC_GCON_CKE3_JPGDEC CLK_VEN1_CKE3_JPGDEC |
| #define CLK_VENC_GCON_CKE4_JPGDEC_C1 CLK_VEN1_CKE4_JPGDEC_C1 |
| #define CLK_VENC_GCON_CKE0_LARB CLK_VEN1_CKE0_LARB |
| #define CLK_VENC_GCON_CKE5_GALS CLK_VEN1_CKE5_GALS |
| #define CLK_VENC_GCON_CKE6_GALS_SRAM CLK_VEN1_CKE6_GALS_SRAM |
| |
| #define CLK_VENC_GCON_CORE1_CKE1_VENC CLK_VEN1_CORE1_CKE1_VENC |
| #define CLK_VENC_GCON_CORE1_CKE2_JPGENC CLK_VEN1_CORE1_CKE2_JPGENC |
| #define CLK_VENC_GCON_CORE1_CKE3_JPGDEC CLK_VEN1_CORE1_CKE3_JPGDEC |
| #define CLK_VENC_GCON_CORE1_CKE4_JPGDEC_C1 CLK_VEN1_CORE1_CKE4_JPGDEC_C1 |
| #define CLK_VENC_GCON_CORE1_CKE0_LARB CLK_VEN1_CORE1_CKE0_LARB |
| #define CLK_VENC_GCON_CORE1_CKE5_GALS CLK_VEN1_CORE1_CKE5_GALS |
| #define CLK_VENC_GCON_CORE1_CKE6_GALS_SRAM CLK_VEN1_CORE1_CKE6_GALS_SRAM |
| |
| #define CLK_WPE1_DIP1_LARB11_CGPDN CLK_WPE1_DIP1_LARB11 |
| #define CLK_WPE1_DIP1_WPE_CGPDN CLK_WPE1_DIP1_WPE |
| #define CLK_WPE2_DIP1_LARB11_CGPDN CLK_WPE2_DIP1_LARB11 |
| #define CLK_WPE2_DIP1_WPE_CGPDN CLK_WPE2_DIP1_WPE |
| #define CLK_WPE3_DIP1_LARB11_CGPDN CLK_WPE3_DIP1_LARB11 |
| #define CLK_WPE3_DIP1_WPE_CGPDN CLK_WPE3_DIP1_WPE |
| |
| #endif /* _DT_BINDINGS_CLK_MT6983_H */ |
