| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* |
| * Copyright (c) 2022 MediaTek Inc. |
| * Author: Owen Chen <owen.chen@mediatek.com> |
| */ |
| |
| #ifndef _DT_BINDINGS_CLK_MT6985_H |
| #define _DT_BINDINGS_CLK_MT6985_H |
| |
| /* TOPCKGEN */ |
| #define CLK_TOP_AXI_SEL 0 |
| #define CLK_TOP_P_FAXI_SEL 1 |
| #define CLK_TOP_U_FAXI_SEL 2 |
| #define CLK_TOP_BUS_AXIMEM_SEL 3 |
| #define CLK_TOP_DISP0_SEL 4 |
| #define CLK_TOP_DISP1_SEL 5 |
| #define CLK_TOP_OVL0_SEL 6 |
| #define CLK_TOP_OVL1_SEL 7 |
| #define CLK_TOP_MDP0_SEL 8 |
| #define CLK_TOP_MDP1_SEL 9 |
| #define CLK_TOP_MMINFRA_SEL 10 |
| #define CLK_TOP_MMUP_SEL 11 |
| #define CLK_TOP_DSP_SEL 12 |
| #define CLK_TOP_MFG_REF_SEL 13 |
| #define CLK_TOP_MFGSC_REF_SEL 14 |
| #define CLK_TOP_UART_SEL 15 |
| #define CLK_TOP_SPI_SEL 16 |
| #define CLK_TOP_MSDC_MACRO_SEL 17 |
| #define CLK_TOP_MSDC30_1_SEL 18 |
| #define CLK_TOP_MSDC30_2_SEL 19 |
| #define CLK_TOP_AUDIO_SEL 20 |
| #define CLK_TOP_AUD_INTBUS_SEL 21 |
| #define CLK_TOP_ATB_SEL 22 |
| #define CLK_TOP_DP_SEL 23 |
| #define CLK_TOP_DISP_PWM_SEL 24 |
| #define CLK_TOP_USB_TOP_SEL 25 |
| #define CLK_TOP_USB_XHCI_SEL 26 |
| #define CLK_TOP_USB_TOP_1P_SEL 27 |
| #define CLK_TOP_USB_XHCI_1P_SEL 28 |
| #define CLK_TOP_I2C_SEL 29 |
| #define CLK_TOP_AUD_ENGEN1_SEL 30 |
| #define CLK_TOP_AUD_ENGEN2_SEL 31 |
| #define CLK_TOP_AES_UFSFDE_SEL 32 |
| #define CLK_TOP_U_SEL 33 |
| #define CLK_TOP_U_MBIST_SEL 34 |
| #define CLK_TOP_PEXTP_MBIST_SEL 35 |
| #define CLK_TOP_AUD_1_SEL 36 |
| #define CLK_TOP_AUD_2_SEL 37 |
| #define CLK_TOP_ADSP_SEL 38 |
| #define CLK_TOP_DPMAIF_MAIN_SEL 39 |
| #define CLK_TOP_VDEC_CKSYS1_SEL 40 |
| #define CLK_TOP_PWM_SEL 41 |
| #define CLK_TOP_AUDIO_H_SEL 42 |
| #define CLK_TOP_MCUPM_SEL 43 |
| #define CLK_TOP_MEM_SUB_SEL 44 |
| #define CLK_TOP_P_FMEM_SUB_SEL 45 |
| #define CLK_TOP_U_FMEM_SUB_SEL 46 |
| #define CLK_TOP_EMI_N_SEL 47 |
| #define CLK_TOP_EMI_S_SEL 48 |
| #define CLK_TOP_AP2CONN_HOST_SEL 49 |
| #define CLK_TOP_MCU_ACP_SEL 50 |
| #define CLK_TOP_SFLASH_SEL 51 |
| #define CLK_TOP_MCU_L3GIC_SEL 52 |
| #define CLK_TOP_IPSEAST_SEL 53 |
| #define CLK_TOP_IPSSOUTH_SEL 54 |
| #define CLK_TOP_IPSWEST_SEL 55 |
| #define CLK_TOP_TL_SEL 56 |
| #define CLK_TOP_PEXTP_FAXI_SEL 57 |
| #define CLK_TOP_PEXTP_FMEM_SUB_SEL 58 |
| #define CLK_TOP_AUDIO_LOCAL_BUS_SEL 59 |
| #define CLK_TOP_EMI_INTERFACE_546_SEL 60 |
| #define CLK_TOP_MFG_INT0_SEL 61 |
| #define CLK_TOP_MFG1_INT1_SEL 62 |
| #define CLK_TOP_APLL_I2S0_MCK_SEL 63 |
| #define CLK_TOP_APLL_I2S1_MCK_SEL 64 |
| #define CLK_TOP_APLL_I2S2_MCK_SEL 65 |
| #define CLK_TOP_APLL_I2S3_MCK_SEL 66 |
| #define CLK_TOP_APLL_I2S4_MCK_SEL 67 |
| #define CLK_TOP_APLL_I2S5_MCK_SEL 68 |
| #define CLK_TOP_APLL_I2S6_MCK_SEL 69 |
| #define CLK_TOP_APLL_I2S7_MCK_SEL 70 |
| #define CLK_TOP_APLL_I2S8_MCK_SEL 71 |
| #define CLK_TOP_APLL_I2S9_MCK_SEL 72 |
| #define CLK_TOP_APLL_ETDM_IN1_MCK_SEL 73 |
| #define CLK_TOP_APLL_ETDM_OUT1_MCK_SEL 74 |
| #define CLK_TOP_APLL_I2S10_MCK_SEL 75 |
| #define CLK_TOP_CAMTG_SEL 76 |
| #define CLK_TOP_CAMTG2_SEL 77 |
| #define CLK_TOP_CAMTG3_SEL 78 |
| #define CLK_TOP_CAMTG4_SEL 79 |
| #define CLK_TOP_CAMTG5_SEL 80 |
| #define CLK_TOP_CAMTG6_SEL 81 |
| #define CLK_TOP_CAMTG7_SEL 82 |
| #define CLK_TOP_CAMTG8_SEL 83 |
| #define CLK_TOP_SENINF_SEL 84 |
| #define CLK_TOP_SENINF1_SEL 85 |
| #define CLK_TOP_SENINF2_SEL 86 |
| #define CLK_TOP_SENINF3_SEL 87 |
| #define CLK_TOP_SENINF4_SEL 88 |
| #define CLK_TOP_SENINF5_SEL 89 |
| #define CLK_TOP_VENC_SEL 90 |
| #define CLK_TOP_VDEC_SEL 91 |
| #define CLK_TOP_CCU_AHB_SEL 92 |
| #define CLK_TOP_IMG1_SEL 93 |
| #define CLK_TOP_IPE_SEL 94 |
| #define CLK_TOP_CAM_SEL 95 |
| #define CLK_TOP_CCUSYS_SEL 96 |
| #define CLK_TOP_CAMTM_SEL 97 |
| #define CLK_TOP_APLL12_CK_DIV0 98 |
| #define CLK_TOP_APLL12_CK_DIV1 99 |
| #define CLK_TOP_APLL12_CK_DIV2 100 |
| #define CLK_TOP_APLL12_CK_DIV3 101 |
| #define CLK_TOP_APLL12_CK_DIV4 102 |
| #define CLK_TOP_APLL12_CK_DIVB 103 |
| #define CLK_TOP_APLL12_CK_DIV5 104 |
| #define CLK_TOP_APLL12_CK_DIV6 105 |
| #define CLK_TOP_APLL12_CK_DIV7 106 |
| #define CLK_TOP_APLL12_CK_DIV8 107 |
| #define CLK_TOP_APLL12_CK_DIV9 108 |
| #define CLK_TOP_APLL12_CK_DIV10 109 |
| #define CLK_TOP_MFGPLL 110 |
| #define CLK_TOP_MFGSCPLL 111 |
| #define CLK_TOP_MAINPLL_D3 112 |
| #define CLK_TOP_MAINPLL_D4 113 |
| #define CLK_TOP_MAINPLL_D4_D2 114 |
| #define CLK_TOP_MAINPLL_D4_D4 115 |
| #define CLK_TOP_MAINPLL_D4_D8 116 |
| #define CLK_TOP_MAINPLL_D4_D16 117 |
| #define CLK_TOP_MAINPLL_D5 118 |
| #define CLK_TOP_MAINPLL_D5_D2 119 |
| #define CLK_TOP_MAINPLL_D5_D4 120 |
| #define CLK_TOP_MAINPLL_D5_D8 121 |
| #define CLK_TOP_MAINPLL_D6 122 |
| #define CLK_TOP_MAINPLL_D6_D2 123 |
| #define CLK_TOP_MAINPLL_D7 124 |
| #define CLK_TOP_MAINPLL_D7_D2 125 |
| #define CLK_TOP_MAINPLL_D7_D4 126 |
| #define CLK_TOP_MAINPLL_D7_D8 127 |
| #define CLK_TOP_MAINPLL_D9 128 |
| #define CLK_TOP_UNIVPLL_D2 129 |
| #define CLK_TOP_UNIVPLL_D3 130 |
| #define CLK_TOP_UNIVPLL_D4 131 |
| #define CLK_TOP_UNIVPLL_D4_D2 132 |
| #define CLK_TOP_UNIVPLL_D4_D4 133 |
| #define CLK_TOP_UNIVPLL_D4_D8 134 |
| #define CLK_TOP_UNIVPLL_D5 135 |
| #define CLK_TOP_UNIVPLL_D5_D2 136 |
| #define CLK_TOP_UNIVPLL_D5_D4 137 |
| #define CLK_TOP_UNIVPLL_D6 138 |
| #define CLK_TOP_UNIVPLL_D6_D2 139 |
| #define CLK_TOP_UNIVPLL_D6_D4 140 |
| #define CLK_TOP_UNIVPLL_D6_D8 141 |
| #define CLK_TOP_UNIVPLL_D6_D16 142 |
| #define CLK_TOP_UNIVPLL_D7 143 |
| #define CLK_TOP_UNIVPLL_192M_D8 144 |
| #define CLK_TOP_UNIVPLL_192M_D10 145 |
| #define CLK_TOP_UNIVPLL_192M_D16 146 |
| #define CLK_TOP_UNIVPLL_192M_D32 147 |
| #define CLK_TOP_APLL1 148 |
| #define CLK_TOP_APLL1_D2 149 |
| #define CLK_TOP_APLL1_D4 150 |
| #define CLK_TOP_APLL1_D8 151 |
| #define CLK_TOP_APLL2 152 |
| #define CLK_TOP_APLL2_D2 153 |
| #define CLK_TOP_APLL2_D4 154 |
| #define CLK_TOP_APLL2_D8 155 |
| #define CLK_TOP_ADSPPLL 156 |
| #define CLK_TOP_EMIPLL 157 |
| #define CLK_TOP_IMGPLL_D3 158 |
| #define CLK_TOP_IMGPLL_D4 159 |
| #define CLK_TOP_IMGPLL_D5_D2 160 |
| #define CLK_TOP_MMPLL_D4 161 |
| #define CLK_TOP_MMPLL_D4_D2 162 |
| #define CLK_TOP_MMPLL_D5_D2 163 |
| #define CLK_TOP_MMPLL_D6 164 |
| #define CLK_TOP_MMPLL_D6_D2 165 |
| #define CLK_TOP_MMPLL_D7 166 |
| #define CLK_TOP_TVDPLL 167 |
| #define CLK_TOP_TVDPLL_D2 168 |
| #define CLK_TOP_TVDPLL_D4 169 |
| #define CLK_TOP_TVDPLL_D8 170 |
| #define CLK_TOP_TVDPLL_D16 171 |
| #define CLK_TOP_MSDCPLL 172 |
| #define CLK_TOP_MSDCPLL_D2 173 |
| #define CLK_TOP_CLKRTC 174 |
| #define CLK_TOP_TCK_26M_MX9 175 |
| #define CLK_TOP_F26M_CK_D2 176 |
| #define CLK_TOP_OSC_D2 177 |
| #define CLK_TOP_OSC_D3 178 |
| #define CLK_TOP_OSC_D4 179 |
| #define CLK_TOP_OSC_D5 180 |
| #define CLK_TOP_OSC_D6 181 |
| #define CLK_TOP_OSC_D7 182 |
| #define CLK_TOP_OSC_D8 183 |
| #define CLK_TOP_OSC_D10 184 |
| #define CLK_TOP_OSC_D14 185 |
| #define CLK_TOP_OSC_D16 186 |
| #define CLK_TOP_OSC_D20 187 |
| #define CLK_TOP_OSC_D32 188 |
| #define CLK_TOP_OSC_D40 189 |
| #define CLK_TOP_ULPOSC 190 |
| #define CLK_TOP_MAINPLL2_D3 191 |
| #define CLK_TOP_MAINPLL2_D4 192 |
| #define CLK_TOP_MAINPLL2_D4_D2 193 |
| #define CLK_TOP_MAINPLL2_D5 194 |
| #define CLK_TOP_MAINPLL2_D5_D2 195 |
| #define CLK_TOP_MAINPLL2_D6 196 |
| #define CLK_TOP_MAINPLL2_D6_D2 197 |
| #define CLK_TOP_MAINPLL2_D7 198 |
| #define CLK_TOP_MAINPLL2_D7_D2 199 |
| #define CLK_TOP_MAINPLL2_D9 200 |
| #define CLK_TOP_UNIVPLL2_D3 201 |
| #define CLK_TOP_UNIVPLL2_D4 202 |
| #define CLK_TOP_UNIVPLL2_D4_D2 203 |
| #define CLK_TOP_UNIVPLL2_D5 204 |
| #define CLK_TOP_UNIVPLL2_D5_D2 205 |
| #define CLK_TOP_UNIVPLL2_D6 206 |
| #define CLK_TOP_UNIVPLL2_D6_D2 207 |
| #define CLK_TOP_UNIVPLL2_D6_D4 208 |
| #define CLK_TOP_UNIVPLL2_D6_D8 209 |
| #define CLK_TOP_UNIVPLL2_D6_D16 210 |
| #define CLK_TOP_UNIVPLL2_D7 211 |
| #define CLK_TOP_MMPLL2_D4 212 |
| #define CLK_TOP_MMPLL2_D4_D2 213 |
| #define CLK_TOP_MMPLL2_D6 214 |
| #define CLK_TOP_MMPLL2_D6_D2 215 |
| #define CLK_TOP_MMPLL2_D7 216 |
| #define CLK_TOP_MMPLL2_D9 217 |
| #define CLK_TOP_UNIVPLL2_192M_D8 218 |
| #define CLK_TOP_UNIVPLL2_192M_D10 219 |
| #define CLK_TOP_UNIVPLL2_192M_D16 220 |
| #define CLK_TOP_UNIVPLL2_192M_D32 221 |
| #define CLK_TOP_F26M 222 |
| #define CLK_TOP_AXI 223 |
| #define CLK_TOP_P_FAXI 224 |
| #define CLK_TOP_DISP0 225 |
| #define CLK_TOP_DISP1 226 |
| #define CLK_TOP_OVL0 227 |
| #define CLK_TOP_OVL1 228 |
| #define CLK_TOP_MDP0 229 |
| #define CLK_TOP_MDP1 230 |
| #define CLK_TOP_MMINFRA 231 |
| #define CLK_TOP_MMUP 232 |
| #define CLK_TOP_MFG_REF 233 |
| #define CLK_TOP_UART 234 |
| #define CLK_TOP_SPI 235 |
| #define CLK_TOP_MSDC_MACRO 236 |
| #define CLK_TOP_MSDC30_1 237 |
| #define CLK_TOP_MSDC30_2 238 |
| #define CLK_TOP_AUDIO 239 |
| #define CLK_TOP_AUD_INTBUS 240 |
| #define CLK_TOP_DISP_PWM 241 |
| #define CLK_TOP_I2C 242 |
| #define CLK_TOP_AUD_ENGEN1 243 |
| #define CLK_TOP_AUD_ENGEN2 244 |
| #define CLK_TOP_AES_UFSFDE 245 |
| #define CLK_TOP_UFS 246 |
| #define CLK_TOP_PEXTP_MBIST 247 |
| #define CLK_TOP_AUD_1 248 |
| #define CLK_TOP_ADSP 249 |
| #define CLK_TOP_DPMAIF_MAIN 250 |
| #define CLK_TOP_PWM 251 |
| #define CLK_TOP_AUDIO_H 252 |
| #define CLK_TOP_SFLASH 253 |
| #define CLK_TOP_TL 254 |
| #define CLK_TOP_PEXTP_FAXI 255 |
| #define CLK_TOP_PEXTP_FMEM_SUB 256 |
| #define CLK_TOP_AUDIO_LOCAL_BUS 257 |
| #define CLK_TOP_VDEC_CKSYS1 258 |
| #define CLK_TOP_MFGSC_REF 259 |
| #define CLK_TOP_SSR_312 260 |
| #define CLK_TOP_SSR_416 261 |
| #define CLK_TOP_IMGAVS 262 |
| #define CLK_TOP_VENC 263 |
| #define CLK_TOP_VDEC 264 |
| #define CLK_TOP_CCU_AHB 265 |
| #define CLK_TOP_IMG1 266 |
| #define CLK_TOP_IPE 267 |
| #define CLK_TOP_CAM 268 |
| #define CLK_TOP_CCUSYS 269 |
| #define CLK_TOP_CAMTM 270 |
| #define CLK_TOP_I2C_PSEUDO 271 |
| #define CLK_TOP_ARMPLL_DIVIDER_PLL1 272 |
| #define CLK_TOP_ARMPLL_DIVIDER_PLL2 273 |
| #define CLK_TOP_FMEM_CK_OCC_FRC_EN 274 |
| #define CLK_TOP_MD_32K 275 |
| #define CLK_TOP_MD_26M 276 |
| #define CLK_TOP_NR_CLK 277 |
| |
| /* INFRACFG_AO */ |
| #define CLK_IFRAO_CLDMA_BCLK 0 |
| #define CLK_IFRAO_DPMAIF_MAIN 1 |
| #define CLK_IFRAO_RG_MMW_DPMAIF26M_CK 2 |
| #define CLK_IFRAO_RG_AP_I3C 3 |
| #define CLK_IFRAO_NR_CLK 4 |
| |
| /* APMIXEDSYS */ |
| #define CLK_APMIXED_MAINPLL2 0 |
| #define CLK_APMIXED_UNIVPLL2 1 |
| #define CLK_APMIXED_MMPLL2 2 |
| #define CLK_APMIXED_MAINPLL 3 |
| #define CLK_APMIXED_UNIVPLL 4 |
| #define CLK_APMIXED_MSDCPLL 5 |
| #define CLK_APMIXED_MMPLL 6 |
| #define CLK_APMIXED_ADSPPLL 7 |
| #define CLK_APMIXED_TVDPLL 8 |
| #define CLK_APMIXED_APLL1 9 |
| #define CLK_APMIXED_APLL2 10 |
| #define CLK_APMIXED_MPLL 11 |
| #define CLK_APMIXED_EMIPLL 12 |
| #define CLK_APMIXED_IMGPLL 13 |
| #define CLK_APMIXED_NR_CLK 14 |
| |
| /* PERICFG_AO */ |
| #define CLK_PERAO_UART0 0 |
| #define CLK_PERAO_UART1 1 |
| #define CLK_PERAO_UART2 2 |
| #define CLK_PERAO_UART3 3 |
| #define CLK_PERAO_PWM_H 4 |
| #define CLK_PERAO_PWM_B 5 |
| #define CLK_PERAO_PWM_FB1 6 |
| #define CLK_PERAO_PWM_FB2 7 |
| #define CLK_PERAO_PWM_FB3 8 |
| #define CLK_PERAO_PWM_FB4 9 |
| #define CLK_PERAO_DISP_PWM0 10 |
| #define CLK_PERAO_DISP_PWM1 11 |
| #define CLK_PERAO_SPI0_B 12 |
| #define CLK_PERAO_SPI1_B 13 |
| #define CLK_PERAO_SPI2_B 14 |
| #define CLK_PERAO_SPI3_B 15 |
| #define CLK_PERAO_SPI4_B 16 |
| #define CLK_PERAO_SPI5_B 17 |
| #define CLK_PERAO_SPI6_B 18 |
| #define CLK_PERAO_SPI7_B 19 |
| #define CLK_PERAO_SFLASH 20 |
| #define CLK_PERAO_SFLASH_F 21 |
| #define CLK_PERAO_SFLASH_H 22 |
| #define CLK_PERAO_SFLASH_P 23 |
| #define CLK_PERAO_DMA_B 24 |
| #define CLK_PERAO_SSUSB0_FRMCNT 25 |
| #define CLK_PERAO_SSUSB1_FRMCNT 26 |
| #define CLK_PERAO_MSDC1 27 |
| #define CLK_PERAO_MSDC1_F 28 |
| #define CLK_PERAO_MSDC1_H 29 |
| #define CLK_PERAO_MSDC2 30 |
| #define CLK_PERAO_MSDC2_F 31 |
| #define CLK_PERAO_MSDC2_H 32 |
| #define CLK_PERAO_AUDIO_SLV 33 |
| #define CLK_PERAO_AUDIO_MST 34 |
| #define CLK_PERAO_AUDIO_INTBUS 35 |
| #define CLK_PERAO_NR_CLK 36 |
| |
| /* AFE */ |
| #define CLK_AFE_AUD_PAD_TOP_CLOCK_EN 0 |
| #define CLK_AFE_AFE 1 |
| #define CLK_AFE_22M 2 |
| #define CLK_AFE_24M 3 |
| #define CLK_AFE_APLL2_TUNER 4 |
| #define CLK_AFE_APLL_TUNER 5 |
| #define CLK_AFE_TDM 6 |
| #define CLK_AFE_ADC 7 |
| #define CLK_AFE_DAC 8 |
| #define CLK_AFE_DAC_PREDIS 9 |
| #define CLK_AFE_TML 10 |
| #define CLK_AFE_NLE 11 |
| #define CLK_AFE_GENERAL3_ASRC 12 |
| #define CLK_AFE_CONNSYS_I2S_ASRC 13 |
| #define CLK_AFE_GENERAL1_ASRC 14 |
| #define CLK_AFE_GENERAL2_ASRC 15 |
| #define CLK_AFE_DAC_HIRES 16 |
| #define CLK_AFE_ADC_HIRES 17 |
| #define CLK_AFE_ADC_HIRES_TML 18 |
| #define CLK_AFE_ADDA6_ADC 19 |
| #define CLK_AFE_ADDA6_ADC_HIRES 20 |
| #define CLK_AFE_ADDA7_ADC 21 |
| #define CLK_AFE_ADDA7_ADC_HIRES 22 |
| #define CLK_AFE_3RD_DAC 23 |
| #define CLK_AFE_3RD_DAC_PREDIS 24 |
| #define CLK_AFE_3RD_DAC_TML 25 |
| #define CLK_AFE_3RD_DAC_HIRES 26 |
| #define CLK_AFE_I2S5_BCLK 27 |
| #define CLK_AFE_I2S6_BCLK 28 |
| #define CLK_AFE_I2S7_BCLK 29 |
| #define CLK_AFE_I2S8_BCLK 30 |
| #define CLK_AFE_I2S9_BCLK 31 |
| #define CLK_AFE_ETDM_IN0_BCLK 32 |
| #define CLK_AFE_ETDM_OUT0_BCLK 33 |
| #define CLK_AFE_I2S1_BCLK 34 |
| #define CLK_AFE_I2S2_BCLK 35 |
| #define CLK_AFE_I2S3_BCLK 36 |
| #define CLK_AFE_I2S4_BCLK 37 |
| #define CLK_AFE_I2S10_BCLK 38 |
| #define CLK_AFE_ETDM_IN1_BCLK 39 |
| #define CLK_AFE_ETDM_OUT1_BCLK 40 |
| #define CLK_AFE_NR_CLK 41 |
| |
| /* IMP_IIC_WRAP_C */ |
| #define CLK_IMPC_I2C5 0 |
| #define CLK_IMPC_NR_CLK 1 |
| |
| /* UFSCFG_AO */ |
| #define CLK_UFSAO_UNIPRO_TX_SYM 0 |
| #define CLK_UFSAO_UNIPRO_RX_SYM0 1 |
| #define CLK_UFSAO_UNIPRO_RX_SYM1 2 |
| #define CLK_UFSAO_UNIPRO_SYS 3 |
| #define CLK_UFSAO_NR_CLK 4 |
| |
| /* UFSCFG_PDN */ |
| #define CLK_UFSPDN_UFSHCI_UFS 0 |
| #define CLK_UFSPDN_UFSHCI_AES 1 |
| #define CLK_UFSPDN_NR_CLK 2 |
| |
| /* PEXTPCFG_AO */ |
| #define CLK_PEXT_MAC0_26M 0 |
| #define CLK_PEXT_MAC0_P1_PCLK_250M 1 |
| #define CLK_PEXT_MAC0_GFMUX_TL 2 |
| #define CLK_PEXT_MAC0_FMEM 3 |
| #define CLK_PEXT_MAC0_HCLK 4 |
| #define CLK_PEXT_PHY0_REF 5 |
| #define CLK_PEXT_MAC1_26M 6 |
| #define CLK_PEXT_MAC1_P1_PCLK_250M 7 |
| #define CLK_PEXT_MAC1_GFMUX_TL 8 |
| #define CLK_PEXT_MAC1_FMEM 9 |
| #define CLK_PEXT_MAC1_HCLK 10 |
| #define CLK_PEXT_PHY1_REF 11 |
| #define CLK_PEXT_NR_CLK 12 |
| |
| /* IMP_IIC_WRAP_S */ |
| #define CLK_IMPS_I2C1 0 |
| #define CLK_IMPS_I2C2 1 |
| #define CLK_IMPS_I2C3 2 |
| #define CLK_IMPS_I2C4 3 |
| #define CLK_IMPS_I2C7 4 |
| #define CLK_IMPS_I2C8 5 |
| #define CLK_IMPS_I2C9 6 |
| #define CLK_IMPS_NR_CLK 7 |
| |
| /* IMP_IIC_WRAP_N */ |
| #define CLK_IMPN_I2C0 0 |
| #define CLK_IMPN_I2C6 1 |
| #define CLK_IMPN_I2C10 2 |
| #define CLK_IMPN_I2C11 3 |
| #define CLK_IMPN_I2C12 4 |
| #define CLK_IMPN_I2C13 5 |
| #define CLK_IMPN_NR_CLK 6 |
| |
| /* MFGPLL_PLL_CTRL */ |
| #define CLK_MFG_AO_MFGPLL 0 |
| #define CLK_MFG_AO_NR_CLK 1 |
| |
| /* MFGSCPLL_PLL_CTRL */ |
| #define CLK_MFGSC_AO_MFGSCPLL 0 |
| #define CLK_MFGSC_AO_NR_CLK 1 |
| |
| /* DISPSYS_CONFIG */ |
| #define CLK_MM_CONFIG 0 |
| #define CLK_MM_DISP_MUTEX0 1 |
| #define CLK_MM_DISP_AAL0 2 |
| #define CLK_MM_DISP_C3D0 3 |
| #define CLK_MM_DISP_CCORR0 4 |
| #define CLK_MM_DISP_CCORR1 5 |
| #define CLK_MM_DISP_CHIST0 6 |
| #define CLK_MM_DISP_CHIST1 7 |
| #define CLK_MM_DISP_COLOR0 8 |
| #define CLK_MM_DISP_DITHER0 9 |
| #define CLK_MM_DISP_DITHER1 10 |
| #define CLK_MM_DISP_DLI_ASYNC0 11 |
| #define CLK_MM_DISP_DLI_ASYNC1 12 |
| #define CLK_MM_DISP_DLI_ASYNC2 13 |
| #define CLK_MM_DISP_DLI_ASYNC3 14 |
| #define CLK_MM_DISP_DLI_ASYNC4 15 |
| #define CLK_MM_DISP_DLI_ASYNC5 16 |
| #define CLK_MM_DISP_DLO_ASYNC0 17 |
| #define CLK_MM_DISP_DLO_ASYNC1 18 |
| #define CLK_MM_DISP_DP_INTF0 19 |
| #define CLK_MM_DISP_DSC_WRAP0 20 |
| #define CLK_MM_DISP_DSI0 21 |
| #define CLK_MM_DISP_GAMMA0 22 |
| #define CLK_MM_MDP_AAL0 23 |
| #define CLK_MM_MDP_RDMA0 24 |
| #define CLK_MM_DISP_MERGE0 25 |
| #define CLK_MM_DISP_MERGE1 26 |
| #define CLK_MM_DISP_ODDMR0 27 |
| #define CLK_MM_DISP_POSTALIGN0 28 |
| #define CLK_MM_DISP_POSTMASK0 29 |
| #define CLK_MM_DISP_RELAY0 30 |
| #define CLK_MM_DISP_RSZ0 31 |
| #define CLK_MM_DISP_SPR0 32 |
| #define CLK_MM_DISP_TDSHP0 33 |
| #define CLK_MM_DISP_TDSHP1 34 |
| #define CLK_MM_DISP_UFBC_WDMA1 35 |
| #define CLK_MM_DISP_VDCM0 36 |
| #define CLK_MM_DISP_WDMA1 37 |
| #define CLK_MM_SMI_SUB_COMM0 38 |
| #define CLK_MM_DISP_Y2R0 39 |
| #define CLK_MM_DSI_CLK 40 |
| #define CLK_MM_DP_CLK 41 |
| #define CLK_MM_26M_CLK 42 |
| #define CLK_MM_NR_CLK 43 |
| |
| /* DISPSYS1_CONFIG */ |
| #define CLK_MM1_CONFIG 0 |
| #define CLK_MM1_DISP_MUTEX0 1 |
| #define CLK_MM1_DISP_AAL0 2 |
| #define CLK_MM1_DISP_C3D0 3 |
| #define CLK_MM1_DISP_CCORR0 4 |
| #define CLK_MM1_DISP_CCORR1 5 |
| #define CLK_MM1_DISP_CHIST0 6 |
| #define CLK_MM1_DISP_CHIST1 7 |
| #define CLK_MM1_DISP_COLOR0 8 |
| #define CLK_MM1_DISP_DITHER0 9 |
| #define CLK_MM1_DISP_DITHER1 10 |
| #define CLK_MM1_DISP_DLI_ASYNC0 11 |
| #define CLK_MM1_DISP_DLI_ASYNC1 12 |
| #define CLK_MM1_DISP_DLI_ASYNC2 13 |
| #define CLK_MM1_DISP_DLI_ASYNC3 14 |
| #define CLK_MM1_DISP_DLI_ASYNC4 15 |
| #define CLK_MM1_DISP_DLI_ASYNC5 16 |
| #define CLK_MM1_DISP_DLO_ASYNC0 17 |
| #define CLK_MM1_DISP_DLO_ASYNC1 18 |
| #define CLK_MM1_DISP_DP_INTF0 19 |
| #define CLK_MM1_DISP_DSC_WRAP0 20 |
| #define CLK_MM1_DISP_DSI0 21 |
| #define CLK_MM1_DISP_GAMMA0 22 |
| #define CLK_MM1_MDP_AAL0 23 |
| #define CLK_MM1_MDP_RDMA0 24 |
| #define CLK_MM1_DISP_MERGE0 25 |
| #define CLK_MM1_DISP_MERGE1 26 |
| #define CLK_MM1_DISP_ODDMR0 27 |
| #define CLK_MM1_DISP_POSTALIGN0 28 |
| #define CLK_MM1_DISP_POSTMASK0 29 |
| #define CLK_MM1_DISP_RELAY0 30 |
| #define CLK_MM1_DISP_RSZ0 31 |
| #define CLK_MM1_DISP_SPR0 32 |
| #define CLK_MM1_DISP_TDSHP0 33 |
| #define CLK_MM1_DISP_TDSHP1 34 |
| #define CLK_MM1_DISP_UFBC_WDMA1 35 |
| #define CLK_MM1_DISP_VDCM0 36 |
| #define CLK_MM1_DISP_WDMA1 37 |
| #define CLK_MM1_SMI_SUB_COMM0 38 |
| #define CLK_MM1_DISP_Y2R0 39 |
| #define CLK_MM1_DSI_CLK 40 |
| #define CLK_MM1_DP_CLK 41 |
| #define CLK_MM1_26M_CLK 42 |
| #define CLK_MM1_NR_CLK 43 |
| |
| /* OVLSYS_CONFIG */ |
| #define CLK_OVL_CONFIG 0 |
| #define CLK_OVL_DISP_FAKE_ENG0 1 |
| #define CLK_OVL_DISP_FAKE_ENG1 2 |
| #define CLK_OVL_DISP_MUTEX0 3 |
| #define CLK_OVL_OVL0_2L 4 |
| #define CLK_OVL_OVL1_2L 5 |
| #define CLK_OVL_OVL2_2L 6 |
| #define CLK_OVL_OVL3_2L 7 |
| #define CLK_OVL_DISP_RSZ1 8 |
| #define CLK_OVL_MDP_RSZ0 9 |
| #define CLK_OVL_DISP_WDMA0 10 |
| #define CLK_OVL_DISP_UFBC_WDMA0 11 |
| #define CLK_OVL_DISP_WDMA2 12 |
| #define CLK_OVL_DISP_DLI_ASYNC0 13 |
| #define CLK_OVL_DISP_DLI_ASYNC1 14 |
| #define CLK_OVL_DISP_DLI_ASYNC2 15 |
| #define CLK_OVL_DISP_DLO_ASYNC0 16 |
| #define CLK_OVL_DISP_DLO_ASYNC1 17 |
| #define CLK_OVL_DISP_DLO_ASYNC2 18 |
| #define CLK_OVL_DISP_DLO_ASYNC3 19 |
| #define CLK_OVL_DISP_DLO_ASYNC4 20 |
| #define CLK_OVL_DISP_DLO_ASYNC5 21 |
| #define CLK_OVL_DISP_DLO_ASYNC6 22 |
| #define CLK_OVL_INLINEROT 23 |
| #define CLK_OVL_SMI_SUB_COMMON0 24 |
| #define CLK_OVL_DISP_Y2R0 25 |
| #define CLK_OVL_DISP_Y2R1 26 |
| #define CLK_OVL_NR_CLK 27 |
| |
| /* OVLSYS1_CONFIG */ |
| #define CLK_OVL1_CONFIG 0 |
| #define CLK_OVL1_DISP_FAKE_ENG0 1 |
| #define CLK_OVL1_DISP_FAKE_ENG1 2 |
| #define CLK_OVL1_DISP_MUTEX0 3 |
| #define CLK_OVL1_OVL0_2L 4 |
| #define CLK_OVL1_OVL1_2L 5 |
| #define CLK_OVL1_OVL2_2L 6 |
| #define CLK_OVL1_OVL3_2L 7 |
| #define CLK_OVL1_DISP_RSZ1 8 |
| #define CLK_OVL1_MDP_RSZ0 9 |
| #define CLK_OVL1_DISP_WDMA0 10 |
| #define CLK_OVL1_DISP_UFBC_WDMA0 11 |
| #define CLK_OVL1_DISP_WDMA2 12 |
| #define CLK_OVL1_DISP_DLI_ASYNC0 13 |
| #define CLK_OVL1_DISP_DLI_ASYNC1 14 |
| #define CLK_OVL1_DISP_DLI_ASYNC2 15 |
| #define CLK_OVL1_DISP_DLO_ASYNC0 16 |
| #define CLK_OVL1_DISP_DLO_ASYNC1 17 |
| #define CLK_OVL1_DISP_DLO_ASYNC2 18 |
| #define CLK_OVL1_DISP_DLO_ASYNC3 19 |
| #define CLK_OVL1_DISP_DLO_ASYNC4 20 |
| #define CLK_OVL1_DISP_DLO_ASYNC5 21 |
| #define CLK_OVL1_DISP_DLO_ASYNC6 22 |
| #define CLK_OVL1_INLINEROT 23 |
| #define CLK_OVL1_SMI_SUB_COMMON0 24 |
| #define CLK_OVL1_DISP_Y2R0 25 |
| #define CLK_OVL1_DISP_Y2R1 26 |
| #define CLK_OVL1_NR_CLK 27 |
| |
| /* IMGSYS_MAIN */ |
| #define CLK_IMG_FDVT 0 |
| #define CLK_IMG_ME 1 |
| #define CLK_IMG_MMG 2 |
| #define CLK_IMG_LARB12 3 |
| #define CLK_IMG_LARB9 4 |
| #define CLK_IMG_TRAW0 5 |
| #define CLK_IMG_TRAW1 6 |
| #define CLK_IMG_VCORE_GALS 7 |
| #define CLK_IMG_DIP0 8 |
| #define CLK_IMG_WPE0 9 |
| #define CLK_IMG_IPE 10 |
| #define CLK_IMG_WPE1 11 |
| #define CLK_IMG_WPE2 12 |
| #define CLK_IMG_SMI_ADL_LARB0 13 |
| #define CLK_IMG_ADL0 14 |
| #define CLK_IMG_AVS 15 |
| #define CLK_IMG_GALS 16 |
| #define CLK_IMG_NR_CLK 17 |
| |
| /* DIP_TOP_DIP1 */ |
| #define CLK_DIP_TOP_DIP1_LARB10 0 |
| #define CLK_DIP_TOP_DIP1_DIP_TOP 1 |
| #define CLK_DIP_TOP_DIP1_NR_CLK 2 |
| |
| /* DIP_NR1_DIP1 */ |
| #define CLK_DIP_NR1_DIP1_LARB 0 |
| #define CLK_DIP_NR1_DIP1_DIP_NR1 1 |
| #define CLK_DIP_NR1_DIP1_NR_CLK 2 |
| |
| /* DIP_NR2_DIP1 */ |
| #define CLK_DIP_NR2_DIP1_LARB15 0 |
| #define CLK_DIP_NR2_DIP1_DIP_NR 1 |
| #define CLK_DIP_NR2_DIP1_NR_CLK 2 |
| |
| /* WPE1_DIP1 */ |
| #define CLK_WPE1_DIP1_LARB11 0 |
| #define CLK_WPE1_DIP1_WPE 1 |
| #define CLK_WPE1_DIP1_NR_CLK 2 |
| |
| /* WPE2_DIP1 */ |
| #define CLK_WPE2_DIP1_LARB11 0 |
| #define CLK_WPE2_DIP1_WPE 1 |
| #define CLK_WPE2_DIP1_NR_CLK 2 |
| |
| /* WPE3_DIP1 */ |
| #define CLK_WPE3_DIP1_LARB11 0 |
| #define CLK_WPE3_DIP1_WPE 1 |
| #define CLK_WPE3_DIP1_NR_CLK 2 |
| |
| /* TRAW_DIP1 */ |
| #define CLK_TRAW_DIP1_LARB28 0 |
| #define CLK_TRAW_DIP1_TRAW 1 |
| #define CLK_TRAW_DIP1_NR_CLK 2 |
| |
| /* VDEC_SOC_GCON_BASE */ |
| #define CLK_VDE1_LARB1_CKEN 0 |
| #define CLK_VDE1_LAT_CKEN 1 |
| #define CLK_VDE1_LAT_ACTIVE 2 |
| #define CLK_VDE1_LAT_CKEN_ENG 3 |
| #define CLK_VDE1_MINI_MDP_EN 4 |
| #define CLK_VDE1_VDEC_CKEN 5 |
| #define CLK_VDE1_VDEC_ACTIVE 6 |
| #define CLK_VDE1_VDEC_CKEN_ENG 7 |
| #define CLK_VDE1_VDEC_SOC_IPS_EN 8 |
| #define CLK_VDE1_NR_CLK 9 |
| |
| /* VDEC_GCON_BASE */ |
| #define CLK_VDE2_LARB1_CKEN 0 |
| #define CLK_VDE2_LAT_CKEN 1 |
| #define CLK_VDE2_LAT_ACTIVE 2 |
| #define CLK_VDE2_LAT_CKEN_ENG 3 |
| #define CLK_VDE2_VDEC_CKEN 4 |
| #define CLK_VDE2_VDEC_ACTIVE 5 |
| #define CLK_VDE2_VDEC_CKEN_ENG 6 |
| #define CLK_VDE2_NR_CLK 7 |
| |
| /* VENC_GCON */ |
| #define CLK_VEN_CKE0_LARB 0 |
| #define CLK_VEN_CKE1_VENC 1 |
| #define CLK_VEN_CKE2_JPGENC 2 |
| #define CLK_VEN_CKE3_JPGDEC 3 |
| #define CLK_VEN_CKE4_JPGDEC_C1 4 |
| #define CLK_VEN_CKE5_GALS 5 |
| #define CLK_VEN_CKE6_GALS_SRAM 6 |
| #define CLK_VEN_NR_CLK 7 |
| |
| /* VENC_GCON_CORE1 */ |
| #define CLK_VEN_C1_CKE0_LARB 0 |
| #define CLK_VEN_C1_CKE1_VENC 1 |
| #define CLK_VEN_C1_CKE2_JPGENC 2 |
| #define CLK_VEN_C1_CKE3_JPGDEC 3 |
| #define CLK_VEN_C1_CKE4_JPGDEC_C1 4 |
| #define CLK_VEN_C1_CKE5_GALS 5 |
| #define CLK_VEN_C1_CKE6_GALS_SRAM 6 |
| #define CLK_VEN_C1_NR_CLK 7 |
| |
| /* VENC_GCON_CORE2 */ |
| #define CLK_VEN_C2_CKE0_LARB 0 |
| #define CLK_VEN_C2_CKE1_VENC 1 |
| #define CLK_VEN_C2_CKE2_JPGENC 2 |
| #define CLK_VEN_C2_CKE3_JPGDEC 3 |
| #define CLK_VEN_C2_CKE4_JPGDEC_C1 4 |
| #define CLK_VEN_C2_CKE5_GALS 5 |
| #define CLK_VEN_C2_CKE6_GALS_SRAM 6 |
| #define CLK_VEN_C2_NR_CLK 7 |
| |
| /* VLP_CKSYS */ |
| #define CLK_VLP_CK_SCP_SEL 0 |
| #define CLK_VLP_CK_SCP_SPI_SEL 1 |
| #define CLK_VLP_CK_SCP_IIC_SEL 2 |
| #define CLK_VLP_CK_PWRAP_ULPOSC_SEL 3 |
| #define CLK_VLP_CK_DXCC_VLP_SEL 4 |
| #define CLK_VLP_CK_DPSW_SEL 5 |
| #define CLK_VLP_CK_SPMI_M_MST_SEL 6 |
| #define CLK_VLP_CK_DVFSRC_SEL 7 |
| #define CLK_VLP_CK_PWM_VLP_SEL 8 |
| #define CLK_VLP_CK_AXI_VLP_SEL 9 |
| #define CLK_VLP_CK_DBGAO_26M_SEL 10 |
| #define CLK_VLP_CK_SYSTIMER_26M_SEL 11 |
| #define CLK_VLP_CK_SSPM_SEL 12 |
| #define CLK_VLP_CK_SRCK_SEL 13 |
| #define CLK_VLP_CK_SRAMRC_SEL 14 |
| #define CLK_VLP_CK_CAMTG_VLP_SEL 15 |
| #define CLK_VLP_CK_IPS_SEL 16 |
| #define CLK_VLP_CK_26M_SSPM_SEL 17 |
| #define CLK_VLP_CK_ULPOSC_SSPM_SEL 18 |
| #define CLK_VLP_CK_CAMTG_VLP 19 |
| #define CLK_VLP_CK_NR_CLK 20 |
| |
| /* SCP */ |
| #define CLK_SCP_SET_SPI0 0 |
| #define CLK_SCP_SET_SPI1 1 |
| #define CLK_SCP_SET_SPI2 2 |
| #define CLK_SCP_SET_SPI3 3 |
| #define CLK_SCP_NR_CLK 4 |
| |
| /* SCP_IIC */ |
| #define CLK_SCP_IIC_I2C0 0 |
| #define CLK_SCP_IIC_I2C1 1 |
| #define CLK_SCP_IIC_I2C2 2 |
| #define CLK_SCP_IIC_I2C3 3 |
| #define CLK_SCP_IIC_I2C4 4 |
| #define CLK_SCP_IIC_I2C5 5 |
| #define CLK_SCP_IIC_I2C6 6 |
| #define CLK_SCP_IIC_I2C7 7 |
| #define CLK_SCP_IIC_NR_CLK 8 |
| |
| /* CAMSYS_MAIN */ |
| #define CLK_CAM_MAIN_LARB13_CON_0 0 |
| #define CLK_CAM_MAIN_LARB14_CON_0 1 |
| #define CLK_CAM_MAIN_LARB27_CON_0 2 |
| #define CLK_CAM_MAIN_LARB29_CON_0 3 |
| #define CLK_CAM_MAIN_CAM_CON_0 4 |
| #define CLK_CAM_MAIN_CAM_SUBA_CON_0 5 |
| #define CLK_CAM_MAIN_CAM_SUBB_CON_0 6 |
| #define CLK_CAM_MAIN_CAM_SUBC_CON_0 7 |
| #define CLK_CAM_MAIN_CAM_MRAW_CON_0 8 |
| #define CLK_CAM_MAIN_CAMTG_CON_0 9 |
| #define CLK_CAM_MAIN_SENINF_CON_0 10 |
| #define CLK_CAM_MAIN_CAMSV_TOP_CON_0 11 |
| #define CLK_CAM_MAIN_ADLRD_CON_0 12 |
| #define CLK_CAM_MAIN_ADLWR_CON_0 13 |
| #define CLK_CAM_MAIN_UISP_CON_0 14 |
| #define CLK_CAM_MAIN_FAKE_ENG_CON_0 15 |
| #define CLK_CAM_MAIN_CAM2MM0_GALS_CON_0 16 |
| #define CLK_CAM_MAIN_CAM2MM1_GALS_CON_0 17 |
| #define CLK_CAM_MAIN_CAM2SYS_GALS_CON_0 18 |
| #define CLK_CAM_MAIN_CAM2MM2_GALS_CON_0 19 |
| #define CLK_CAM_MAIN_CCUSYS_CON_0 20 |
| #define CLK_CAM_MAIN_IPS_CON_0 21 |
| #define CLK_CAM_MAIN_CAMSV_A_CON_1 22 |
| #define CLK_CAM_MAIN_CAMSV_B_CON_1 23 |
| #define CLK_CAM_MAIN_CAMSV_C_CON_1 24 |
| #define CLK_CAM_MAIN_CAMSV_D_CON_1 25 |
| #define CLK_CAM_MAIN_CAMSV_E_CON_1 26 |
| #define CLK_CAM_MAIN_CAMSV_CON_1 27 |
| #define CLK_CAM_M_NR_CLK 28 |
| |
| /* CAMSYS_RAWA */ |
| #define CLK_CAM_RA_LARBX 0 |
| #define CLK_CAM_RA_CAM 1 |
| #define CLK_CAM_RA_CAMTG 2 |
| #define CLK_CAM_RA_NR_CLK 3 |
| |
| /* CAMSYS_YUVA */ |
| #define CLK_CAM_YA_LARBX 0 |
| #define CLK_CAM_YA_CAM 1 |
| #define CLK_CAM_YA_CAMTG 2 |
| #define CLK_CAM_YA_NR_CLK 3 |
| |
| /* CAMSYS_RAWB */ |
| #define CLK_CAM_RB_LARBX 0 |
| #define CLK_CAM_RB_CAM 1 |
| #define CLK_CAM_RB_CAMTG 2 |
| #define CLK_CAM_RB_NR_CLK 3 |
| |
| /* CAMSYS_YUVB */ |
| #define CLK_CAM_YB_LARBX 0 |
| #define CLK_CAM_YB_CAM 1 |
| #define CLK_CAM_YB_CAMTG 2 |
| #define CLK_CAM_YB_NR_CLK 3 |
| |
| /* CAMSYS_RAWC */ |
| #define CLK_CAM_RC_LARBX 0 |
| #define CLK_CAM_RC_CAM 1 |
| #define CLK_CAM_RC_CAMTG 2 |
| #define CLK_CAM_RC_NR_CLK 3 |
| |
| /* CAMSYS_YUVC */ |
| #define CLK_CAM_YC_LARBX 0 |
| #define CLK_CAM_YC_CAM 1 |
| #define CLK_CAM_YC_CAMTG 2 |
| #define CLK_CAM_YC_NR_CLK 3 |
| |
| /* CAMSYS_MRAW */ |
| #define CLK_CAM_MR_LARBX 0 |
| #define CLK_CAM_MR_CAMTG 1 |
| #define CLK_CAM_MR_MRAW0 2 |
| #define CLK_CAM_MR_MRAW1 3 |
| #define CLK_CAM_MR_MRAW2 4 |
| #define CLK_CAM_MR_MRAW3 5 |
| #define CLK_CAM_MR_PDA0 6 |
| #define CLK_CAM_MR_PDA1 7 |
| #define CLK_CAM_MR_NR_CLK 8 |
| |
| /* CCU_MAIN */ |
| #define CLK_CCU_LARB19 0 |
| #define CLK_CCU_AHB 1 |
| #define CLK_CCUSYS_CCU0 2 |
| #define CLK_CCUSYS_CCU1 3 |
| #define CLK_CCUSYS_DPE 4 |
| #define CLK_CCUSYS_DHZE 5 |
| #define CLK_CCU_NR_CLK 6 |
| |
| /* MMINFRA_CONFIG */ |
| #define CLK_MMINFRA_GCE_D 0 |
| #define CLK_MMINFRA_GCE_M 1 |
| #define CLK_MMINFRA_SMI 2 |
| #define CLK_MMINFRA_GCE_26M 3 |
| #define CLK_MMINFRA_CONFIG_NR_CLK 4 |
| |
| /* MDPSYS_CONFIG */ |
| #define CLK_MDP_MUTEX0 0 |
| #define CLK_MDP_APB_BUS 1 |
| #define CLK_MDP_SMI0 2 |
| #define CLK_MDP_RDMA0 3 |
| #define CLK_MDP_RDMA2 4 |
| #define CLK_MDP_HDR0 5 |
| #define CLK_MDP_AAL0 6 |
| #define CLK_MDP_RSZ0 7 |
| #define CLK_MDP_TDSHP0 8 |
| #define CLK_MDP_COLOR0 9 |
| #define CLK_MDP_WROT0 10 |
| #define CLK_MDP_FAKE_ENG0 11 |
| #define CLK_MDP_DLI_ASYNC0 12 |
| #define CLK_MDP_DLI_ASYNC1 13 |
| #define CLK_MDP_RDMA1 14 |
| #define CLK_MDP_RDMA3 15 |
| #define CLK_MDP_HDR1 16 |
| #define CLK_MDP_AAL1 17 |
| #define CLK_MDP_RSZ1 18 |
| #define CLK_MDP_TDSHP1 19 |
| #define CLK_MDP_COLOR1 20 |
| #define CLK_MDP_WROT1 21 |
| #define CLK_MDP_RSZ2 22 |
| #define CLK_MDP_WROT2 23 |
| #define CLK_MDP_DLO_ASYNC0 24 |
| #define CLK_MDP_RSZ3 25 |
| #define CLK_MDP_WROT3 26 |
| #define CLK_MDP_DLO_ASYNC1 27 |
| #define CLK_MDP_DLI_ASYNC2 28 |
| #define CLK_MDP_DLI_ASYNC3 29 |
| #define CLK_MDP_DLO_ASYNC2 30 |
| #define CLK_MDP_DLO_ASYNC3 31 |
| #define CLK_MDP_BIRSZ0 32 |
| #define CLK_MDP_BIRSZ1 33 |
| #define CLK_MDP_IMG_DL_ASYNC0 34 |
| #define CLK_MDP_IMG_DL_ASYNC1 35 |
| #define CLK_MDP_HRE_TOP_MDPSYS 36 |
| #define CLK_MDP_NR_CLK 37 |
| |
| /* MDPSYS1_CONFIG */ |
| #define CLK_MDP1_MDP_MUTEX0 0 |
| #define CLK_MDP1_APB_BUS 1 |
| #define CLK_MDP1_SMI0 2 |
| #define CLK_MDP1_MDP_RDMA0 3 |
| #define CLK_MDP1_MDP_RDMA2 4 |
| #define CLK_MDP1_MDP_HDR0 5 |
| #define CLK_MDP1_MDP_AAL0 6 |
| #define CLK_MDP1_MDP_RSZ0 7 |
| #define CLK_MDP1_MDP_TDSHP0 8 |
| #define CLK_MDP1_MDP_COLOR0 9 |
| #define CLK_MDP1_MDP_WROT0 10 |
| #define CLK_MDP1_MDP_FAKE_ENG0 11 |
| #define CLK_MDP1_MDP_DLI_ASYNC0 12 |
| #define CLK_MDP1_MDP_DLI_ASYNC1 13 |
| #define CLK_MDP1_MDP_RDMA1 14 |
| #define CLK_MDP1_MDP_RDMA3 15 |
| #define CLK_MDP1_MDP_HDR1 16 |
| #define CLK_MDP1_MDP_AAL1 17 |
| #define CLK_MDP1_MDP_RSZ1 18 |
| #define CLK_MDP1_MDP_TDSHP1 19 |
| #define CLK_MDP1_MDP_COLOR1 20 |
| #define CLK_MDP1_MDP_WROT1 21 |
| #define CLK_MDP1_MDP_RSZ2 22 |
| #define CLK_MDP1_MDP_WROT2 23 |
| #define CLK_MDP1_MDP_DLO_ASYNC0 24 |
| #define CLK_MDP1_MDP_RSZ3 25 |
| #define CLK_MDP1_MDP_WROT3 26 |
| #define CLK_MDP1_MDP_DLO_ASYNC1 27 |
| #define CLK_MDP1_MDP_DLI_ASYNC2 28 |
| #define CLK_MDP1_MDP_DLI_ASYNC3 29 |
| #define CLK_MDP1_MDP_DLO_ASYNC2 30 |
| #define CLK_MDP1_MDP_DLO_ASYNC3 31 |
| #define CLK_MDP1_MDP_BIRSZ0 32 |
| #define CLK_MDP1_MDP_BIRSZ1 33 |
| #define CLK_MDP1_IMG_DL_ASYNC0 34 |
| #define CLK_MDP1_IMG_DL_ASYNC1 35 |
| #define CLK_MDP1_HRE_TOP_MDPSYS 36 |
| #define CLK_MDP1_NR_CLK 37 |
| |
| /* CCIPLL_PLL_CTRL */ |
| #define CLK_CCIPLL 0 |
| #define CLK_CCI_NR_CLK 1 |
| |
| /* ARMPLL_LL_PLL_CTRL */ |
| #define CLK_CPU_LL_ARMPLL_LL 0 |
| #define CLK_CPU_LL_NR_CLK 1 |
| |
| /* ARMPLL_BL_PLL_CTRL */ |
| #define CLK_CPU_BL_ARMPLL_BL 0 |
| #define CLK_CPU_BL_NR_CLK 1 |
| |
| /* ARMPLL_B_PLL_CTRL */ |
| #define CLK_CPU_B_ARMPLL_B 0 |
| #define CLK_CPU_B_NR_CLK 1 |
| |
| /* PTPPLL_PLL_CTRL */ |
| #define CLK_PTPPLL 0 |
| #define CLK_PTP_NR_CLK 1 |
| |
| #endif /* _DT_BINDINGS_CLK_MT6985_H */ |
